From ce9ea45d2944a24a2bb56a05046b2470cdb5d14e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?R=C3=A9my=20Rakic?= Date: Fri, 5 Mar 2021 00:08:24 +0100 Subject: [PATCH] convert `_mm512_srli_epi16` to const generics --- .../stdarch/crates/core_arch/src/x86/avx512bw.rs | 16 ++++++---------- 1 file changed, 6 insertions(+), 10 deletions(-) diff --git a/library/stdarch/crates/core_arch/src/x86/avx512bw.rs b/library/stdarch/crates/core_arch/src/x86/avx512bw.rs index 1589bd4b95f8..1c863a6d10d2 100644 --- a/library/stdarch/crates/core_arch/src/x86/avx512bw.rs +++ b/library/stdarch/crates/core_arch/src/x86/avx512bw.rs @@ -5328,16 +5328,12 @@ pub unsafe fn _mm_maskz_srl_epi16(k: __mmask8, a: __m128i, count: __m128i) -> __ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_srli_epi16&expand=5513) #[inline] #[target_feature(enable = "avx512bw")] -#[cfg_attr(test, assert_instr(vpsrlw, imm8 = 5))] -#[rustc_args_required_const(1)] -pub unsafe fn _mm512_srli_epi16(a: __m512i, imm8: u32) -> __m512i { +#[cfg_attr(test, assert_instr(vpsrlw, IMM8 = 5))] +#[rustc_legacy_const_generics(1)] +pub unsafe fn _mm512_srli_epi16(a: __m512i) -> __m512i { + static_assert_imm_u8!(IMM8); let a = a.as_i16x32(); - macro_rules! call { - ($imm8:expr) => { - vpsrliw(a, $imm8) - }; - } - let r = constify_imm8_sae!(imm8, call); + let r = vpsrliw(a, IMM8); transmute(r) } @@ -14704,7 +14700,7 @@ mod tests { #[simd_test(enable = "avx512bw")] unsafe fn test_mm512_srli_epi16() { let a = _mm512_set1_epi16(1 << 1); - let r = _mm512_srli_epi16(a, 2); + let r = _mm512_srli_epi16::<2>(a); let e = _mm512_set1_epi16(0); assert_eq_m512i(r, e); }