From b031c516641c53577d021da1a89d0c953acdc23a Mon Sep 17 00:00:00 2001
From: okaneco <47607823+okaneco@users.noreply.github.com>
Date: Tue, 7 Oct 2025 05:52:37 -0400
Subject: [PATCH 01/97] slice/ascii: Optimize `eq_ignore_ascii_case` with
 auto-vectorization

Refactor the current functionality into a helper function
Use `as_chunks` to encourage auto-vectorization in the optimized chunk processing function
Add a codegen test
Add benches for `eq_ignore_ascii_case`

The optimized function is initially only enabled for x86_64 which has `sse2` as
part of its baseline, but none of the code is platform specific. Other
platforms with SIMD instructions may also benefit from this implementation.

Performance improvements only manifest for slices of 16 bytes or longer, so the
optimized path is gated behind a length check for greater than or equal to 16.
---
 library/core/src/slice/ascii.rs               | 43 ++++++++++++++
 library/coretests/benches/ascii.rs            |  1 +
 .../benches/ascii/eq_ignore_ascii_case.rs     | 56 +++++++++++++++++++
 .../lib-optimizations/eq_ignore_ascii_case.rs | 14 +++++
 4 files changed, 114 insertions(+)
 create mode 100644 library/coretests/benches/ascii/eq_ignore_ascii_case.rs
 create mode 100644 tests/codegen-llvm/lib-optimizations/eq_ignore_ascii_case.rs

diff --git a/library/core/src/slice/ascii.rs b/library/core/src/slice/ascii.rs
index e17a2e03d2dc..1f9ca4bc6698 100644
--- a/library/core/src/slice/ascii.rs
+++ b/library/core/src/slice/ascii.rs
@@ -60,6 +60,18 @@ impl [u8] {
             return false;
         }
 
+        #[cfg(all(target_arch = "x86_64", target_feature = "sse2"))]
+        if self.len() >= 16 {
+            return self.eq_ignore_ascii_case_chunks(other);
+        }
+
+        self.eq_ignore_ascii_case_simple(other)
+    }
+
+    /// ASCII case-insensitive equality check without chunk-at-a-time
+    /// optimization.
+    #[inline]
+    const fn eq_ignore_ascii_case_simple(&self, other: &[u8]) -> bool {
         // FIXME(const-hack): This implementation can be reverted when
         // `core::iter::zip` is allowed in const. The original implementation:
         //  self.len() == other.len() && iter::zip(self, other).all(|(a, b)| a.eq_ignore_ascii_case(b))
@@ -78,6 +90,37 @@ impl [u8] {
         true
     }
 
+    /// Optimized version of `eq_ignore_ascii_case` which processes chunks at a
+    /// time.
+    ///
+    /// Platforms that have SIMD instructions may benefit from this
+    /// implementation over `eq_ignore_ascii_case_simple`.
+    #[cfg(all(target_arch = "x86_64", target_feature = "sse2"))]
+    #[inline]
+    const fn eq_ignore_ascii_case_chunks(&self, other: &[u8]) -> bool {
+        const N: usize = 16;
+        let (a, a_rem) = self.as_chunks::<N>();
+        let (b, b_rem) = other.as_chunks::<N>();
+
+        let mut i = 0;
+        while i < a.len() && i < b.len() {
+            let mut equal_ascii = true;
+            let mut j = 0;
+            while j < N {
+                equal_ascii &= a[i][j].eq_ignore_ascii_case(&b[i][j]);
+                j += 1;
+            }
+
+            if !equal_ascii {
+                return false;
+            }
+
+            i += 1;
+        }
+
+        a_rem.eq_ignore_ascii_case_simple(b_rem)
+    }
+
     /// Converts this slice to its ASCII upper case equivalent in-place.
     ///
     /// ASCII letters 'a' to 'z' are mapped to 'A' to 'Z',
diff --git a/library/coretests/benches/ascii.rs b/library/coretests/benches/ascii.rs
index 64bdc7fed118..17a520922bfa 100644
--- a/library/coretests/benches/ascii.rs
+++ b/library/coretests/benches/ascii.rs
@@ -1,3 +1,4 @@
+mod eq_ignore_ascii_case;
 mod is_ascii;
 
 // Lower-case ASCII 'a' is the first byte that has its highest bit set
diff --git a/library/coretests/benches/ascii/eq_ignore_ascii_case.rs b/library/coretests/benches/ascii/eq_ignore_ascii_case.rs
new file mode 100644
index 000000000000..a51acb1e8463
--- /dev/null
+++ b/library/coretests/benches/ascii/eq_ignore_ascii_case.rs
@@ -0,0 +1,56 @@
+use test::Bencher;
+
+#[bench]
+fn bench_str_under_8_bytes_eq(b: &mut Bencher) {
+    let s = "foo";
+    let other = "FOo";
+    b.iter(|| {
+        assert!(s.eq_ignore_ascii_case(other));
+    })
+}
+
+#[bench]
+fn bench_str_of_8_bytes_eq(b: &mut Bencher) {
+    let s = "foobar78";
+    let other = "FOObAr78";
+    b.iter(|| {
+        assert!(s.eq_ignore_ascii_case(other));
+    })
+}
+
+#[bench]
+fn bench_str_17_bytes_eq(b: &mut Bencher) {
+    let s = "performance-criti";
+    let other = "performANce-cRIti";
+    b.iter(|| {
+        assert!(s.eq_ignore_ascii_case(other));
+    })
+}
+
+#[bench]
+fn bench_str_31_bytes_eq(b: &mut Bencher) {
+    let s = "foobarbazquux02foobarbazquux025";
+    let other = "fooBARbazQuuX02fooBARbazQuuX025";
+    b.iter(|| {
+        assert!(s.eq_ignore_ascii_case(other));
+    })
+}
+
+#[bench]
+fn bench_long_str_eq(b: &mut Bencher) {
+    let s = "Lorem ipsum dolor sit amet, consectetur adipisicing elit, sed do eiusmod tempor \
+             incididunt ut labore et dolore magna aliqua. Ut enim ad minim veniam, quis nostrud \
+             exercitation ullamco laboris nisi ut aliquip ex ea commodo consequat. Duis aute \
+             irure dolor in reprehenderit in voluptate velit esse cillum dolore eu fugiat nulla \
+             pariatur. Excepteur sint occaecat cupidatat non proident, sunt in culpa qui \
+             officia deserunt mollit anim id est laborum.";
+    let other = "Lorem ipsum dolor sit amet, CONSECTETUR adipisicing elit, sed do eiusmod tempor \
+             incididunt ut labore et dolore MAGNA aliqua. Ut enim ad MINIM veniam, quis nostrud \
+             exercitation ullamco LABORIS nisi ut aliquip ex ea commodo consequat. Duis aute \
+             irure dolor in reprehenderit in voluptate velit esse cillum DOLORE eu fugiat nulla \
+             pariatur. Excepteur sint occaecat CUPIDATAT non proident, sunt in culpa qui \
+             officia deserunt mollit anim id est laborum.";
+    b.iter(|| {
+        assert!(s.eq_ignore_ascii_case(other));
+    })
+}
diff --git a/tests/codegen-llvm/lib-optimizations/eq_ignore_ascii_case.rs b/tests/codegen-llvm/lib-optimizations/eq_ignore_ascii_case.rs
new file mode 100644
index 000000000000..b733f1812c92
--- /dev/null
+++ b/tests/codegen-llvm/lib-optimizations/eq_ignore_ascii_case.rs
@@ -0,0 +1,14 @@
+//@ compile-flags: -Copt-level=3
+//@ only-x86_64
+#![crate_type = "lib"]
+
+// Ensure that the optimized variant of the function gets auto-vectorized.
+// CHECK-LABEL: @eq_ignore_ascii_case_autovectorized
+#[no_mangle]
+pub fn eq_ignore_ascii_case_autovectorized(s: &str, other: &str) -> bool {
+    // CHECK: load <16 x i8>
+    // CHECK: load <16 x i8>
+    // CHECK: bitcast <16 x i1>
+    // CHECK-NOT: panic
+    s.eq_ignore_ascii_case(other)
+}

From 7b88f48b530f6610581a0d023199c9563e635730 Mon Sep 17 00:00:00 2001
From: okaneco <47607823+okaneco@users.noreply.github.com>
Date: Tue, 7 Oct 2025 15:35:02 -0400
Subject: [PATCH 02/97] Avoid scalar fallback in chunk remainder check

Refactor the eq check into an inner function for reuse in tail checking

Rather than fall back to the simple implementation for tail handling,
load the last 16 bytes to take advantage of vectorization. This doesn't
seem to negatively impact check time even when the remainder count is low.
---
 library/core/src/slice/ascii.rs | 35 +++++++++++++++++++++++----------
 1 file changed, 25 insertions(+), 10 deletions(-)

diff --git a/library/core/src/slice/ascii.rs b/library/core/src/slice/ascii.rs
index 1f9ca4bc6698..3f3f5a8c441d 100644
--- a/library/core/src/slice/ascii.rs
+++ b/library/core/src/slice/ascii.rs
@@ -90,8 +90,8 @@ impl [u8] {
         true
     }
 
-    /// Optimized version of `eq_ignore_ascii_case` which processes chunks at a
-    /// time.
+    /// Optimized version of `eq_ignore_ascii_case` for byte lengths of at least
+    /// 16 bytes, which processes chunks at a time.
     ///
     /// Platforms that have SIMD instructions may benefit from this
     /// implementation over `eq_ignore_ascii_case_simple`.
@@ -99,26 +99,41 @@ impl [u8] {
     #[inline]
     const fn eq_ignore_ascii_case_chunks(&self, other: &[u8]) -> bool {
         const N: usize = 16;
-        let (a, a_rem) = self.as_chunks::<N>();
-        let (b, b_rem) = other.as_chunks::<N>();
+        let (self_chunks, self_rem) = self.as_chunks::<N>();
+        let (other_chunks, _) = other.as_chunks::<N>();
 
-        let mut i = 0;
-        while i < a.len() && i < b.len() {
+        // Branchless check to encourage auto-vectorization
+        const fn eq_ignore_ascii_inner(lhs: &[u8; N], rhs: &[u8; N]) -> bool {
             let mut equal_ascii = true;
             let mut j = 0;
             while j < N {
-                equal_ascii &= a[i][j].eq_ignore_ascii_case(&b[i][j]);
+                equal_ascii &= lhs[j].eq_ignore_ascii_case(&rhs[j]);
                 j += 1;
             }
 
-            if !equal_ascii {
+            equal_ascii
+        }
+
+        // Process the chunks, returning early if an inequality is found
+        let mut i = 0;
+        while i < self_chunks.len() && i < other_chunks.len() {
+            if !eq_ignore_ascii_inner(&self_chunks[i], &other_chunks[i]) {
                 return false;
             }
-
             i += 1;
         }
 
-        a_rem.eq_ignore_ascii_case_simple(b_rem)
+        // If there are remaining tails, load the last N bytes in the slices to
+        // avoid falling back to per-byte checking.
+        if !self_rem.is_empty() {
+            if let (Some(a_rem), Some(b_rem)) = (self.last_chunk::<N>(), other.last_chunk::<N>()) {
+                if !eq_ignore_ascii_inner(a_rem, b_rem) {
+                    return false;
+                }
+            }
+        }
+
+        true
     }
 
     /// Converts this slice to its ASCII upper case equivalent in-place.

From a5ba24843d6e4ceda580e49344bef73baec14204 Mon Sep 17 00:00:00 2001
From: okaneco <47607823+okaneco@users.noreply.github.com>
Date: Tue, 7 Oct 2025 19:04:32 -0400
Subject: [PATCH 03/97] Relocate bench and use str corpora for data

Add #[inline(always)] to inner function and check not for filecheck test
---
 library/core/src/slice/ascii.rs               |  1 +
 library/coretests/benches/ascii.rs            |  1 -
 .../benches/ascii/eq_ignore_ascii_case.rs     | 56 -------------------
 library/coretests/benches/str.rs              |  1 +
 .../benches/str/eq_ignore_ascii_case.rs       | 45 +++++++++++++++
 .../lib-optimizations/eq_ignore_ascii_case.rs |  4 +-
 6 files changed, 50 insertions(+), 58 deletions(-)
 delete mode 100644 library/coretests/benches/ascii/eq_ignore_ascii_case.rs
 create mode 100644 library/coretests/benches/str/eq_ignore_ascii_case.rs

diff --git a/library/core/src/slice/ascii.rs b/library/core/src/slice/ascii.rs
index 3f3f5a8c441d..8b713947cd9c 100644
--- a/library/core/src/slice/ascii.rs
+++ b/library/core/src/slice/ascii.rs
@@ -103,6 +103,7 @@ impl [u8] {
         let (other_chunks, _) = other.as_chunks::<N>();
 
         // Branchless check to encourage auto-vectorization
+        #[inline(always)]
         const fn eq_ignore_ascii_inner(lhs: &[u8; N], rhs: &[u8; N]) -> bool {
             let mut equal_ascii = true;
             let mut j = 0;
diff --git a/library/coretests/benches/ascii.rs b/library/coretests/benches/ascii.rs
index 17a520922bfa..64bdc7fed118 100644
--- a/library/coretests/benches/ascii.rs
+++ b/library/coretests/benches/ascii.rs
@@ -1,4 +1,3 @@
-mod eq_ignore_ascii_case;
 mod is_ascii;
 
 // Lower-case ASCII 'a' is the first byte that has its highest bit set
diff --git a/library/coretests/benches/ascii/eq_ignore_ascii_case.rs b/library/coretests/benches/ascii/eq_ignore_ascii_case.rs
deleted file mode 100644
index a51acb1e8463..000000000000
--- a/library/coretests/benches/ascii/eq_ignore_ascii_case.rs
+++ /dev/null
@@ -1,56 +0,0 @@
-use test::Bencher;
-
-#[bench]
-fn bench_str_under_8_bytes_eq(b: &mut Bencher) {
-    let s = "foo";
-    let other = "FOo";
-    b.iter(|| {
-        assert!(s.eq_ignore_ascii_case(other));
-    })
-}
-
-#[bench]
-fn bench_str_of_8_bytes_eq(b: &mut Bencher) {
-    let s = "foobar78";
-    let other = "FOObAr78";
-    b.iter(|| {
-        assert!(s.eq_ignore_ascii_case(other));
-    })
-}
-
-#[bench]
-fn bench_str_17_bytes_eq(b: &mut Bencher) {
-    let s = "performance-criti";
-    let other = "performANce-cRIti";
-    b.iter(|| {
-        assert!(s.eq_ignore_ascii_case(other));
-    })
-}
-
-#[bench]
-fn bench_str_31_bytes_eq(b: &mut Bencher) {
-    let s = "foobarbazquux02foobarbazquux025";
-    let other = "fooBARbazQuuX02fooBARbazQuuX025";
-    b.iter(|| {
-        assert!(s.eq_ignore_ascii_case(other));
-    })
-}
-
-#[bench]
-fn bench_long_str_eq(b: &mut Bencher) {
-    let s = "Lorem ipsum dolor sit amet, consectetur adipisicing elit, sed do eiusmod tempor \
-             incididunt ut labore et dolore magna aliqua. Ut enim ad minim veniam, quis nostrud \
-             exercitation ullamco laboris nisi ut aliquip ex ea commodo consequat. Duis aute \
-             irure dolor in reprehenderit in voluptate velit esse cillum dolore eu fugiat nulla \
-             pariatur. Excepteur sint occaecat cupidatat non proident, sunt in culpa qui \
-             officia deserunt mollit anim id est laborum.";
-    let other = "Lorem ipsum dolor sit amet, CONSECTETUR adipisicing elit, sed do eiusmod tempor \
-             incididunt ut labore et dolore MAGNA aliqua. Ut enim ad MINIM veniam, quis nostrud \
-             exercitation ullamco LABORIS nisi ut aliquip ex ea commodo consequat. Duis aute \
-             irure dolor in reprehenderit in voluptate velit esse cillum DOLORE eu fugiat nulla \
-             pariatur. Excepteur sint occaecat CUPIDATAT non proident, sunt in culpa qui \
-             officia deserunt mollit anim id est laborum.";
-    b.iter(|| {
-        assert!(s.eq_ignore_ascii_case(other));
-    })
-}
diff --git a/library/coretests/benches/str.rs b/library/coretests/benches/str.rs
index 2f7d9d56a70b..bf45a8f0a79b 100644
--- a/library/coretests/benches/str.rs
+++ b/library/coretests/benches/str.rs
@@ -5,6 +5,7 @@ use test::{Bencher, black_box};
 mod char_count;
 mod corpora;
 mod debug;
+mod eq_ignore_ascii_case;
 mod iter;
 
 #[bench]
diff --git a/library/coretests/benches/str/eq_ignore_ascii_case.rs b/library/coretests/benches/str/eq_ignore_ascii_case.rs
new file mode 100644
index 000000000000..29129b933bc4
--- /dev/null
+++ b/library/coretests/benches/str/eq_ignore_ascii_case.rs
@@ -0,0 +1,45 @@
+use test::{Bencher, black_box};
+
+use super::corpora::*;
+
+#[bench]
+fn bench_str_under_8_bytes_eq(b: &mut Bencher) {
+    let s = black_box("foo");
+    let other = black_box("foo");
+    b.iter(|| assert!(s.eq_ignore_ascii_case(other)))
+}
+
+#[bench]
+fn bench_str_of_8_bytes_eq(b: &mut Bencher) {
+    let s = black_box(en::TINY);
+    let other = black_box(en::TINY);
+    b.iter(|| assert!(s.eq_ignore_ascii_case(other)))
+}
+
+#[bench]
+fn bench_str_17_bytes_eq(b: &mut Bencher) {
+    let s = black_box(&en::SMALL[..17]);
+    let other = black_box(&en::SMALL[..17]);
+    b.iter(|| assert!(s.eq_ignore_ascii_case(other)))
+}
+
+#[bench]
+fn bench_str_31_bytes_eq(b: &mut Bencher) {
+    let s = black_box(&en::SMALL[..31]);
+    let other = black_box(&en::SMALL[..31]);
+    b.iter(|| assert!(s.eq_ignore_ascii_case(other)))
+}
+
+#[bench]
+fn bench_medium_str_eq(b: &mut Bencher) {
+    let s = black_box(en::MEDIUM);
+    let other = black_box(en::MEDIUM);
+    b.iter(|| assert!(s.eq_ignore_ascii_case(other)))
+}
+
+#[bench]
+fn bench_large_str_eq(b: &mut Bencher) {
+    let s = black_box(en::LARGE);
+    let other = black_box(en::LARGE);
+    b.iter(|| assert!(s.eq_ignore_ascii_case(other)))
+}
diff --git a/tests/codegen-llvm/lib-optimizations/eq_ignore_ascii_case.rs b/tests/codegen-llvm/lib-optimizations/eq_ignore_ascii_case.rs
index b733f1812c92..d4ac5d64585d 100644
--- a/tests/codegen-llvm/lib-optimizations/eq_ignore_ascii_case.rs
+++ b/tests/codegen-llvm/lib-optimizations/eq_ignore_ascii_case.rs
@@ -2,13 +2,15 @@
 //@ only-x86_64
 #![crate_type = "lib"]
 
-// Ensure that the optimized variant of the function gets auto-vectorized.
+// Ensure that the optimized variant of the function gets auto-vectorized and
+// that the inner helper function is inlined.
 // CHECK-LABEL: @eq_ignore_ascii_case_autovectorized
 #[no_mangle]
 pub fn eq_ignore_ascii_case_autovectorized(s: &str, other: &str) -> bool {
     // CHECK: load <16 x i8>
     // CHECK: load <16 x i8>
     // CHECK: bitcast <16 x i1>
+    // CHECK-NOT: call {{.*}}eq_ignore_ascii_inner
     // CHECK-NOT: panic
     s.eq_ignore_ascii_case(other)
 }

From 31bf836c74e5b53e654bed70158cabfdfdca8acf Mon Sep 17 00:00:00 2001
From: okaneco <47607823+okaneco@users.noreply.github.com>
Date: Tue, 14 Oct 2025 02:23:44 -0400
Subject: [PATCH 04/97] Use a const generic parameter for the function chunk
 size

Add comments for the optimized function invariants to the caller
Add const-hack fixme for using while-loops
Document the invariant for the `_chunks` function
Add a debug assert for the tail handling invariant
---
 library/core/src/slice/ascii.rs | 35 +++++++++++++++++++++++++--------
 1 file changed, 27 insertions(+), 8 deletions(-)

diff --git a/library/core/src/slice/ascii.rs b/library/core/src/slice/ascii.rs
index 8b713947cd9c..0f3cf243f164 100644
--- a/library/core/src/slice/ascii.rs
+++ b/library/core/src/slice/ascii.rs
@@ -61,8 +61,15 @@ impl [u8] {
         }
 
         #[cfg(all(target_arch = "x86_64", target_feature = "sse2"))]
-        if self.len() >= 16 {
-            return self.eq_ignore_ascii_case_chunks(other);
+        {
+            const CHUNK_SIZE: usize = 16;
+            // The following function has two invariants:
+            // 1. The slice lengths must be equal, which we checked above.
+            // 2. The slice lengths must greater than or equal to N, which this
+            //    if-statement is checking.
+            if self.len() >= CHUNK_SIZE {
+                return self.eq_ignore_ascii_case_chunks::<CHUNK_SIZE>(other);
+            }
         }
 
         self.eq_ignore_ascii_case_simple(other)
@@ -90,24 +97,30 @@ impl [u8] {
         true
     }
 
-    /// Optimized version of `eq_ignore_ascii_case` for byte lengths of at least
-    /// 16 bytes, which processes chunks at a time.
+    /// Optimized version of `eq_ignore_ascii_case` to process chunks at a time.
     ///
     /// Platforms that have SIMD instructions may benefit from this
     /// implementation over `eq_ignore_ascii_case_simple`.
+    ///
+    /// # Invariants
+    ///
+    /// The caller must guarantee that the slices are equal in length, and the
+    /// slice lengths are greater than or equal to `N` bytes.
     #[cfg(all(target_arch = "x86_64", target_feature = "sse2"))]
     #[inline]
-    const fn eq_ignore_ascii_case_chunks(&self, other: &[u8]) -> bool {
-        const N: usize = 16;
+    const fn eq_ignore_ascii_case_chunks<const N: usize>(&self, other: &[u8]) -> bool {
+        // FIXME(const-hack): The while-loops that follow should be replaced by
+        // for-loops when available in const.
+
         let (self_chunks, self_rem) = self.as_chunks::<N>();
         let (other_chunks, _) = other.as_chunks::<N>();
 
         // Branchless check to encourage auto-vectorization
         #[inline(always)]
-        const fn eq_ignore_ascii_inner(lhs: &[u8; N], rhs: &[u8; N]) -> bool {
+        const fn eq_ignore_ascii_inner<const L: usize>(lhs: &[u8; L], rhs: &[u8; L]) -> bool {
             let mut equal_ascii = true;
             let mut j = 0;
-            while j < N {
+            while j < L {
                 equal_ascii &= lhs[j].eq_ignore_ascii_case(&rhs[j]);
                 j += 1;
             }
@@ -124,6 +137,12 @@ impl [u8] {
             i += 1;
         }
 
+        // Check the length invariant which is necessary for the tail-handling
+        // logic to be correct. This should have been upheld by the caller,
+        // otherwise lengths less than N will compare as true without any
+        // checking.
+        debug_assert!(self.len() >= N);
+
         // If there are remaining tails, load the last N bytes in the slices to
         // avoid falling back to per-byte checking.
         if !self_rem.is_empty() {

From 79b30d64e76cdc44275822b481c0dd1832b81d0e Mon Sep 17 00:00:00 2001
From: Manuel Drehwald <git@manuel.drehwald.info>
Date: Tue, 9 Dec 2025 10:52:13 +0100
Subject: [PATCH 05/97] thread, grid, and block dim/idx can only return
 non-negative values

---
 .../stdarch/crates/core_arch/src/nvptx/mod.rs | 48 +++++++++----------
 1 file changed, 24 insertions(+), 24 deletions(-)

diff --git a/library/stdarch/crates/core_arch/src/nvptx/mod.rs b/library/stdarch/crates/core_arch/src/nvptx/mod.rs
index 8d16dfb53d43..5471ef819801 100644
--- a/library/stdarch/crates/core_arch/src/nvptx/mod.rs
+++ b/library/stdarch/crates/core_arch/src/nvptx/mod.rs
@@ -23,29 +23,29 @@ unsafe extern "C" {
     #[link_name = "llvm.nvvm.barrier0"]
     fn syncthreads() -> ();
     #[link_name = "llvm.nvvm.read.ptx.sreg.ntid.x"]
-    fn block_dim_x() -> i32;
+    fn block_dim_x() -> u32;
     #[link_name = "llvm.nvvm.read.ptx.sreg.ntid.y"]
-    fn block_dim_y() -> i32;
+    fn block_dim_y() -> u32;
     #[link_name = "llvm.nvvm.read.ptx.sreg.ntid.z"]
-    fn block_dim_z() -> i32;
+    fn block_dim_z() -> u32;
     #[link_name = "llvm.nvvm.read.ptx.sreg.ctaid.x"]
-    fn block_idx_x() -> i32;
+    fn block_idx_x() -> u32;
     #[link_name = "llvm.nvvm.read.ptx.sreg.ctaid.y"]
-    fn block_idx_y() -> i32;
+    fn block_idx_y() -> u32;
     #[link_name = "llvm.nvvm.read.ptx.sreg.ctaid.z"]
-    fn block_idx_z() -> i32;
+    fn block_idx_z() -> u32;
     #[link_name = "llvm.nvvm.read.ptx.sreg.nctaid.x"]
-    fn grid_dim_x() -> i32;
+    fn grid_dim_x() -> u32;
     #[link_name = "llvm.nvvm.read.ptx.sreg.nctaid.y"]
-    fn grid_dim_y() -> i32;
+    fn grid_dim_y() -> u32;
     #[link_name = "llvm.nvvm.read.ptx.sreg.nctaid.z"]
-    fn grid_dim_z() -> i32;
+    fn grid_dim_z() -> u32;
     #[link_name = "llvm.nvvm.read.ptx.sreg.tid.x"]
-    fn thread_idx_x() -> i32;
+    fn thread_idx_x() -> u32;
     #[link_name = "llvm.nvvm.read.ptx.sreg.tid.y"]
-    fn thread_idx_y() -> i32;
+    fn thread_idx_y() -> u32;
     #[link_name = "llvm.nvvm.read.ptx.sreg.tid.z"]
-    fn thread_idx_z() -> i32;
+    fn thread_idx_z() -> u32;
 }
 
 /// Synchronizes all threads in the block.
@@ -58,84 +58,84 @@ pub unsafe fn _syncthreads() -> () {
 /// x-th thread-block dimension.
 #[inline]
 #[unstable(feature = "stdarch_nvptx", issue = "111199")]
-pub unsafe fn _block_dim_x() -> i32 {
+pub unsafe fn _block_dim_x() -> u32 {
     block_dim_x()
 }
 
 /// y-th thread-block dimension.
 #[inline]
 #[unstable(feature = "stdarch_nvptx", issue = "111199")]
-pub unsafe fn _block_dim_y() -> i32 {
+pub unsafe fn _block_dim_y() -> u32 {
     block_dim_y()
 }
 
 /// z-th thread-block dimension.
 #[inline]
 #[unstable(feature = "stdarch_nvptx", issue = "111199")]
-pub unsafe fn _block_dim_z() -> i32 {
+pub unsafe fn _block_dim_z() -> u32 {
     block_dim_z()
 }
 
 /// x-th thread-block index.
 #[inline]
 #[unstable(feature = "stdarch_nvptx", issue = "111199")]
-pub unsafe fn _block_idx_x() -> i32 {
+pub unsafe fn _block_idx_x() -> u32 {
     block_idx_x()
 }
 
 /// y-th thread-block index.
 #[inline]
 #[unstable(feature = "stdarch_nvptx", issue = "111199")]
-pub unsafe fn _block_idx_y() -> i32 {
+pub unsafe fn _block_idx_y() -> u32 {
     block_idx_y()
 }
 
 /// z-th thread-block index.
 #[inline]
 #[unstable(feature = "stdarch_nvptx", issue = "111199")]
-pub unsafe fn _block_idx_z() -> i32 {
+pub unsafe fn _block_idx_z() -> u32 {
     block_idx_z()
 }
 
 /// x-th block-grid dimension.
 #[inline]
 #[unstable(feature = "stdarch_nvptx", issue = "111199")]
-pub unsafe fn _grid_dim_x() -> i32 {
+pub unsafe fn _grid_dim_x() -> u32 {
     grid_dim_x()
 }
 
 /// y-th block-grid dimension.
 #[inline]
 #[unstable(feature = "stdarch_nvptx", issue = "111199")]
-pub unsafe fn _grid_dim_y() -> i32 {
+pub unsafe fn _grid_dim_y() -> u32 {
     grid_dim_y()
 }
 
 /// z-th block-grid dimension.
 #[inline]
 #[unstable(feature = "stdarch_nvptx", issue = "111199")]
-pub unsafe fn _grid_dim_z() -> i32 {
+pub unsafe fn _grid_dim_z() -> u32 {
     grid_dim_z()
 }
 
 /// x-th thread index.
 #[inline]
 #[unstable(feature = "stdarch_nvptx", issue = "111199")]
-pub unsafe fn _thread_idx_x() -> i32 {
+pub unsafe fn _thread_idx_x() -> u32 {
     thread_idx_x()
 }
 
 /// y-th thread index.
 #[inline]
 #[unstable(feature = "stdarch_nvptx", issue = "111199")]
-pub unsafe fn _thread_idx_y() -> i32 {
+pub unsafe fn _thread_idx_y() -> u32 {
     thread_idx_y()
 }
 
 /// z-th thread index.
 #[inline]
 #[unstable(feature = "stdarch_nvptx", issue = "111199")]
-pub unsafe fn _thread_idx_z() -> i32 {
+pub unsafe fn _thread_idx_z() -> u32 {
     thread_idx_z()
 }
 

From 31ce232fda9790c5025d6f89a23b8fd67e8b9369 Mon Sep 17 00:00:00 2001
From: Paul Murphy <murp@redhat.com>
Date: Tue, 21 Oct 2025 15:02:52 -0500
Subject: [PATCH 06/97] Stabilize ppc inline assembly

---
 compiler/rustc_ast_lowering/src/asm.rs        |  2 +
 .../asm-experimental-arch.md                  | 41 +------------------
 2 files changed, 4 insertions(+), 39 deletions(-)

diff --git a/compiler/rustc_ast_lowering/src/asm.rs b/compiler/rustc_ast_lowering/src/asm.rs
index d44faad017ee..afcbae9c51b4 100644
--- a/compiler/rustc_ast_lowering/src/asm.rs
+++ b/compiler/rustc_ast_lowering/src/asm.rs
@@ -51,6 +51,8 @@ impl<'a, 'hir> LoweringContext<'a, 'hir> {
                     | asm::InlineAsmArch::LoongArch32
                     | asm::InlineAsmArch::LoongArch64
                     | asm::InlineAsmArch::S390x
+                    | asm::InlineAsmArch::PowerPC
+                    | asm::InlineAsmArch::PowerPC64
             );
             if !is_stable && !self.tcx.features().asm_experimental_arch() {
                 feature_err(
diff --git a/src/doc/unstable-book/src/language-features/asm-experimental-arch.md b/src/doc/unstable-book/src/language-features/asm-experimental-arch.md
index 77d43315a6d4..23ac46b72ea7 100644
--- a/src/doc/unstable-book/src/language-features/asm-experimental-arch.md
+++ b/src/doc/unstable-book/src/language-features/asm-experimental-arch.md
@@ -8,7 +8,6 @@ The tracking issue for this feature is: [#93335]
 
 This feature tracks `asm!` and `global_asm!` support for the following architectures:
 - NVPTX
-- PowerPC
 - Hexagon
 - MIPS32r2 and MIPS64r2
 - wasm32
@@ -31,16 +30,6 @@ This feature tracks `asm!` and `global_asm!` support for the following architect
 | NVPTX        | `reg64`        | None\*                             | `l`                  |
 | Hexagon      | `reg`          | `r[0-28]`                          | `r`                  |
 | Hexagon      | `preg`         | `p[0-3]`                           | Only clobbers        |
-| PowerPC      | `reg`          | `r0`, `r[3-12]`, `r[14-29]`\*      | `r`                  |
-| PowerPC      | `reg_nonzero`  | `r[3-12]`, `r[14-29]`\*            | `b`                  |
-| PowerPC      | `freg`         | `f[0-31]`                          | `f`                  |
-| PowerPC      | `vreg`         | `v[0-31]`                          | `v`                  |
-| PowerPC      | `vsreg         | `vs[0-63]`                         | `wa`                 |
-| PowerPC      | `cr`           | `cr[0-7]`, `cr`                    | Only clobbers        |
-| PowerPC      | `ctr`          | `ctr`                              | Only clobbers        |
-| PowerPC      | `lr`           | `lr`                               | Only clobbers        |
-| PowerPC      | `xer`          | `xer`                              | Only clobbers        |
-| PowerPC      | `spe_acc`      | `spe_acc`                          | Only clobbers        |
 | wasm32       | `local`        | None\*                             | `r`                  |
 | BPF          | `reg`          | `r[0-10]`                          | `r`                  |
 | BPF          | `wreg`         | `w[0-10]`                          | `w`                  |
@@ -62,10 +51,6 @@ This feature tracks `asm!` and `global_asm!` support for the following architect
 > - NVPTX doesn't have a fixed register set, so named registers are not supported.
 >
 > - WebAssembly doesn't have registers, so named registers are not supported.
->
-> - r29 is reserved only on 32 bit PowerPC targets.
->
-> - spe_acc is only available on PowerPC SPE targets.
 
 # Register class supported types
 
@@ -80,17 +65,6 @@ This feature tracks `asm!` and `global_asm!` support for the following architect
 | NVPTX        | `reg64`                         | None           | `i8`, `i16`, `i32`, `f32`, `i64`, `f64` |
 | Hexagon      | `reg`                           | None           | `i8`, `i16`, `i32`, `f32`               |
 | Hexagon      | `preg`                          | N/A            | Only clobbers                           |
-| PowerPC      | `reg`                           | None           | `i8`, `i16`, `i32`, `i64` (powerpc64 only) |
-| PowerPC      | `reg_nonzero`                   | None           | `i8`, `i16`, `i32`, `i64` (powerpc64 only) |
-| PowerPC      | `freg`                          | None           | `f32`, `f64`                            |
-| PowerPC      | `vreg`                          | `altivec`      | `i8x16`, `i16x8`, `i32x4`, `f32x4`      |
-| PowerPC      | `vreg`                          | `vsx`          | `f32`, `f64`, `i64x2`, `f64x2`          |
-| PowerPC      | `vsreg`                         | `vsx`          | The union of vsx and altivec vreg types |
-| PowerPC      | `cr`                            | N/A            | Only clobbers                           |
-| PowerPC      | `ctr`                           | N/A            | Only clobbers                           |
-| PowerPC      | `lr`                            | N/A            | Only clobbers                           |
-| PowerPC      | `xer`                           | N/A            | Only clobbers                           |
-| PowerPC      | `spe_acc`                       | N/A            | Only clobbers                           |
 | wasm32       | `local`                         | None           | `i8` `i16` `i32` `i64` `f32` `f64`      |
 | BPF          | `reg`                           | None           | `i8` `i16` `i32` `i64`                  |
 | BPF          | `wreg`                          | `alu32`        | `i8` `i16` `i32`                        |
@@ -111,10 +85,6 @@ This feature tracks `asm!` and `global_asm!` support for the following architect
 | Hexagon      | `r29`         | `sp`      |
 | Hexagon      | `r30`         | `fr`      |
 | Hexagon      | `r31`         | `lr`      |
-| PowerPC      | `r1`          | `sp`      |
-| PowerPC      | `r31`         | `fp`      |
-| PowerPC      | `r[0-31]`     | `[0-31]`  |
-| PowerPC      | `f[0-31]`     | `fr[0-31]`|
 | BPF          | `r[0-10]`     | `w[0-10]` |
 | AVR          | `XH`          | `r27`     |
 | AVR          | `XL`          | `r26`     |
@@ -153,16 +123,14 @@ This feature tracks `asm!` and `global_asm!` support for the following architect
 | Architecture | Unsupported register                    | Reason                                                                                                                                                                              |
 | ------------ | --------------------------------------- | ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- |
 | All          | `sp`, `r14`/`o6` (SPARC)                | The stack pointer must be restored to its original value at the end of an asm code block.                                                                                           |
-| All          | `fr` (Hexagon), `fp` (PowerPC), `$fp` (MIPS), `Y` (AVR), `r4` (MSP430), `a6` (M68k), `r30`/`i6` (SPARC) | The frame pointer cannot be used as an input or output.                                                             |
-| All          | `r19` (Hexagon), `r29` (PowerPC 32 bit only), `r30` (PowerPC) | These are used internally by LLVM as "base pointer" for functions with complex stack frames.                                                                              |
+| All          | `fr` (Hexagon) `$fp` (MIPS), `Y` (AVR), `r4` (MSP430), `a6` (M68k), `r30`/`i6` (SPARC) | The frame pointer cannot be used as an input or output.                                                             |
+| All          | `r19` (Hexagon) | These are used internally by LLVM as "base pointer" for functions with complex stack frames.                                                                              |
 | MIPS         | `$0` or `$zero`                         | This is a constant zero register which can't be modified.                                                                                                                           |
 | MIPS         | `$1` or `$at`                           | Reserved for assembler.                                                                                                                                                             |
 | MIPS         | `$26`/`$k0`, `$27`/`$k1`                | OS-reserved registers.                                                                                                                                                              |
 | MIPS         | `$28`/`$gp`                             | Global pointer cannot be used as inputs or outputs.                                                                                                                                 |
 | MIPS         | `$ra`                                   | Return address cannot be used as inputs or outputs.                                                                                                                                 |
 | Hexagon      | `lr`                                    | This is the link register which cannot be used as an input or output.                                                                                                               |
-| PowerPC      | `r2`, `r13`                             | These are system reserved registers.                                                                                                                                                |
-| PowerPC      | `vrsave`                                | The vrsave register cannot be used as an input or output.                                                                                                                           |
 | AVR          | `r0`, `r1`, `r1r0`                      | Due to an issue in LLVM, the `r0` and `r1` registers cannot be used as inputs or outputs.  If modified, they must be restored to their original values before the end of the block. |
 |MSP430        | `r0`, `r2`, `r3`                        | These are the program counter, status register, and constant generator respectively. Neither the status register nor constant generator can be written to.                          |
 | M68k         | `a4`, `a5`                              | Used internally by LLVM for the base pointer and global base pointer. |
@@ -189,11 +157,6 @@ This feature tracks `asm!` and `global_asm!` support for the following architect
 | NVPTX        | `reg32`        | None     | `r0`           | None          |
 | NVPTX        | `reg64`        | None     | `rd0`          | None          |
 | Hexagon      | `reg`          | None     | `r0`           | None          |
-| PowerPC      | `reg`          | None     | `0`            | None          |
-| PowerPC      | `reg_nonzero`  | None     | `3`            | None          |
-| PowerPC      | `freg`         | None     | `0`            | None          |
-| PowerPC      | `vreg`         | None     | `0`            | None          |
-| PowerPC      | `vsreg`        | None     | `0`            | None          |
 | SPARC        | `reg`          | None     | `%o0`          | None          |
 | CSKY         | `reg`          | None     | `r0`           | None          |
 | CSKY         | `freg`         | None     | `f0`           | None          |

From 69c7a7e40509575840cba379c32dd4d8b216519b Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Eduardo=20S=C3=A1nchez=20Mu=C3=B1oz?= <eduardosm-dev@e64.io>
Date: Thu, 1 Jan 2026 22:47:41 +0100
Subject: [PATCH 07/97] Use a generic type to implement SIMD types in
 `core_arch::simd`

This allows the `types` macro to easily implement `From<Simd<T, N>>` and `Into<Simd<T, N>>`
---
 library/stdarch/crates/core_arch/rustfmt.toml |   3 -
 library/stdarch/crates/core_arch/src/lib.rs   |   5 +-
 .../stdarch/crates/core_arch/src/macros.rs    |  16 +
 .../crates/core_arch/src/powerpc/altivec.rs   |   2 -
 .../crates/core_arch/src/powerpc/macros.rs    |  20 --
 .../crates/core_arch/src/s390x/macros.rs      |  20 --
 .../crates/core_arch/src/s390x/vector.rs      |   2 -
 library/stdarch/crates/core_arch/src/simd.rs  | 306 ++++++++++++------
 8 files changed, 219 insertions(+), 155 deletions(-)

diff --git a/library/stdarch/crates/core_arch/rustfmt.toml b/library/stdarch/crates/core_arch/rustfmt.toml
index 4ae742ba8d50..e69de29bb2d1 100644
--- a/library/stdarch/crates/core_arch/rustfmt.toml
+++ b/library/stdarch/crates/core_arch/rustfmt.toml
@@ -1,3 +0,0 @@
-ignore = [
-    "src/simd.rs",
-]
diff --git a/library/stdarch/crates/core_arch/src/lib.rs b/library/stdarch/crates/core_arch/src/lib.rs
index 5bedefe42d6e..d69089b95b0c 100644
--- a/library/stdarch/crates/core_arch/src/lib.rs
+++ b/library/stdarch/crates/core_arch/src/lib.rs
@@ -37,7 +37,8 @@
     avx10_target_feature,
     const_trait_impl,
     const_cmp,
-    const_eval_select
+    const_eval_select,
+    maybe_uninit_as_bytes
 )]
 #![cfg_attr(test, feature(test, abi_vectorcall, stdarch_internal))]
 #![deny(clippy::missing_inline_in_public_items)]
@@ -87,4 +88,4 @@ pub mod arch {
 }
 
 #[allow(unused_imports)]
-use core::{array, convert, ffi, fmt, hint, intrinsics, marker, mem, ops, ptr, sync};
+use core::{array, cmp, convert, ffi, fmt, hint, intrinsics, marker, mem, ops, ptr, sync};
diff --git a/library/stdarch/crates/core_arch/src/macros.rs b/library/stdarch/crates/core_arch/src/macros.rs
index 1030d7e9740a..849297b1fc36 100644
--- a/library/stdarch/crates/core_arch/src/macros.rs
+++ b/library/stdarch/crates/core_arch/src/macros.rs
@@ -135,6 +135,22 @@ macro_rules! types {
                 crate::core_arch::simd::debug_simd_finish(f, stringify!($name), self.as_array())
             }
         }
+
+        $(#[$stability])+
+        impl crate::convert::From<crate::core_arch::simd::Simd<$elem_type, $len>> for $name {
+            #[inline(always)]
+            fn from(simd: crate::core_arch::simd::Simd<$elem_type, $len>) -> Self {
+                unsafe { crate::mem::transmute(simd) }
+            }
+        }
+
+        $(#[$stability])+
+        impl crate::convert::From<$name> for crate::core_arch::simd::Simd<$elem_type, $len> {
+            #[inline(always)]
+            fn from(simd: $name) -> Self {
+                unsafe { crate::mem::transmute(simd) }
+            }
+        }
     )*);
 }
 
diff --git a/library/stdarch/crates/core_arch/src/powerpc/altivec.rs b/library/stdarch/crates/core_arch/src/powerpc/altivec.rs
index a7bbf35ed8d0..37b557c3b2af 100644
--- a/library/stdarch/crates/core_arch/src/powerpc/altivec.rs
+++ b/library/stdarch/crates/core_arch/src/powerpc/altivec.rs
@@ -364,8 +364,6 @@ unsafe extern "C" {
     fn vrfin(a: vector_float) -> vector_float;
 }
 
-impl_from! { i8x16, u8x16,  i16x8, u16x8, i32x4, u32x4, f32x4 }
-
 impl_neg! { i8x16 : 0 }
 impl_neg! { i16x8 : 0 }
 impl_neg! { i32x4 : 0 }
diff --git a/library/stdarch/crates/core_arch/src/powerpc/macros.rs b/library/stdarch/crates/core_arch/src/powerpc/macros.rs
index 24d86f1018c8..6097ca31adc9 100644
--- a/library/stdarch/crates/core_arch/src/powerpc/macros.rs
+++ b/library/stdarch/crates/core_arch/src/powerpc/macros.rs
@@ -274,25 +274,6 @@ macro_rules! t_b {
     };
 }
 
-macro_rules! impl_from {
-    ($s: ident) => {
-        #[unstable(feature = "stdarch_powerpc", issue = "111145")]
-        impl From<$s> for s_t_l!($s) {
-            #[inline]
-            fn from (v: $s) -> Self {
-                unsafe {
-                    transmute(v)
-                }
-            }
-        }
-    };
-    ($($s: ident),*) => {
-        $(
-            impl_from! { $s }
-        )*
-    };
-}
-
 macro_rules! impl_neg {
     ($s: ident : $zero: expr) => {
         #[unstable(feature = "stdarch_powerpc", issue = "111145")]
@@ -306,7 +287,6 @@ macro_rules! impl_neg {
     };
 }
 
-pub(crate) use impl_from;
 pub(crate) use impl_neg;
 pub(crate) use impl_vec_trait;
 pub(crate) use s_t_l;
diff --git a/library/stdarch/crates/core_arch/src/s390x/macros.rs b/library/stdarch/crates/core_arch/src/s390x/macros.rs
index 26afbaa45a74..b72560396c43 100644
--- a/library/stdarch/crates/core_arch/src/s390x/macros.rs
+++ b/library/stdarch/crates/core_arch/src/s390x/macros.rs
@@ -431,25 +431,6 @@ macro_rules! t_b {
     };
 }
 
-macro_rules! impl_from {
-    ($s: ident) => {
-        #[unstable(feature = "stdarch_s390x", issue = "135681")]
-        impl From<$s> for s_t_l!($s) {
-            #[inline]
-            fn from (v: $s) -> Self {
-                unsafe {
-                    transmute(v)
-                }
-            }
-        }
-    };
-    ($($s: ident),*) => {
-        $(
-            impl_from! { $s }
-        )*
-    };
-}
-
 macro_rules! impl_neg {
     ($s: ident : $zero: expr) => {
         #[unstable(feature = "stdarch_s390x", issue = "135681")]
@@ -463,7 +444,6 @@ macro_rules! impl_neg {
     };
 }
 
-pub(crate) use impl_from;
 pub(crate) use impl_neg;
 pub(crate) use impl_vec_trait;
 pub(crate) use l_t_t;
diff --git a/library/stdarch/crates/core_arch/src/s390x/vector.rs b/library/stdarch/crates/core_arch/src/s390x/vector.rs
index 1366b5c78273..d63f37eeb9a8 100644
--- a/library/stdarch/crates/core_arch/src/s390x/vector.rs
+++ b/library/stdarch/crates/core_arch/src/s390x/vector.rs
@@ -283,8 +283,6 @@ unsafe extern "unadjusted" {
     #[link_name = "llvm.s390.vfenezfs"] fn vfenezfs(a: i32x4, b: i32x4) -> PackedTuple<i32x4, i32>;
 }
 
-impl_from! { i8x16, u8x16,  i16x8, u16x8, i32x4, u32x4, i64x2, u64x2, f32x4, f64x2 }
-
 impl_neg! { i8x16 : 0 }
 impl_neg! { i16x8 : 0 }
 impl_neg! { i32x4 : 0 }
diff --git a/library/stdarch/crates/core_arch/src/simd.rs b/library/stdarch/crates/core_arch/src/simd.rs
index b9dbde75971d..926163ac4cad 100644
--- a/library/stdarch/crates/core_arch/src/simd.rs
+++ b/library/stdarch/crates/core_arch/src/simd.rs
@@ -16,129 +16,223 @@ pub(crate) const unsafe fn simd_imin<T: Copy>(a: T, b: T) -> T {
     crate::intrinsics::simd::simd_select(mask, a, b)
 }
 
+/// SAFETY: All bits patterns must be valid
+pub(crate) unsafe trait SimdElement:
+    Copy + const PartialEq + crate::fmt::Debug
+{
+}
+
+unsafe impl SimdElement for u8 {}
+unsafe impl SimdElement for u16 {}
+unsafe impl SimdElement for u32 {}
+unsafe impl SimdElement for u64 {}
+
+unsafe impl SimdElement for i8 {}
+unsafe impl SimdElement for i16 {}
+unsafe impl SimdElement for i32 {}
+unsafe impl SimdElement for i64 {}
+
+unsafe impl SimdElement for f16 {}
+unsafe impl SimdElement for f32 {}
+unsafe impl SimdElement for f64 {}
+
+#[repr(simd)]
+#[derive(Copy)]
+pub(crate) struct Simd<T: SimdElement, const N: usize>([T; N]);
+
+impl<T: SimdElement, const N: usize> Simd<T, N> {
+    /// A value of this type where all elements are zeroed out.
+    // SAFETY: `T` implements `SimdElement`, so it is zeroable.
+    pub(crate) const ZERO: Self = unsafe { crate::mem::zeroed() };
+
+    #[inline(always)]
+    pub(crate) const fn from_array(elements: [T; N]) -> Self {
+        Self(elements)
+    }
+
+    // FIXME: Workaround rust@60637
+    #[inline(always)]
+    #[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
+    pub(crate) const fn splat(value: T) -> Self {
+        let one = Simd([value]);
+        // SAFETY: 0 is always in-bounds because we're shuffling
+        // a simd type with exactly one element.
+        unsafe { simd_shuffle!(one, one, [0; N]) }
+    }
+
+    /// Extract the element at position `index`.
+    /// `index` is not a constant so this is not efficient!
+    /// Use for testing only.
+    // FIXME: Workaround rust@60637
+    #[inline(always)]
+    pub(crate) const fn extract(&self, index: usize) -> T {
+        self.as_array()[index]
+    }
+
+    #[inline]
+    pub(crate) const fn as_array(&self) -> &[T; N] {
+        let simd_ptr: *const Self = self;
+        let array_ptr: *const [T; N] = simd_ptr.cast();
+        // SAFETY: We can always read the prefix of a simd type as an array.
+        // There might be more padding afterwards for some widths, but
+        // that's not a problem for reading less than that.
+        unsafe { &*array_ptr }
+    }
+}
+
+// `#[derive(Clone)]` causes ICE "Projecting into SIMD type core_arch::simd::Simd is banned by MCP#838"
+impl<T: SimdElement, const N: usize> Clone for Simd<T, N> {
+    #[inline]
+    fn clone(&self) -> Self {
+        *self
+    }
+}
+
+#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
+impl<T: SimdElement, const N: usize> const crate::cmp::PartialEq for Simd<T, N> {
+    #[inline]
+    fn eq(&self, other: &Self) -> bool {
+        self.as_array() == other.as_array()
+    }
+}
+
+impl<T: SimdElement, const N: usize> crate::fmt::Debug for Simd<T, N> {
+    #[inline]
+    fn fmt(&self, f: &mut crate::fmt::Formatter<'_>) -> crate::fmt::Result {
+        debug_simd_finish(f, "Simd", self.as_array())
+    }
+}
+
+impl<const N: usize> Simd<f16, N> {
+    #[inline]
+    pub(crate) const fn to_bits(self) -> Simd<u16, N> {
+        assert!(size_of::<Self>() == size_of::<Simd<u16, N>>());
+        unsafe { crate::mem::transmute_copy(&self) }
+    }
+
+    #[inline]
+    pub(crate) const fn from_bits(bits: Simd<u16, N>) -> Self {
+        assert!(size_of::<Self>() == size_of::<Simd<u16, N>>());
+        unsafe { crate::mem::transmute_copy(&bits) }
+    }
+}
+
+impl<const N: usize> Simd<f32, N> {
+    #[inline]
+    pub(crate) const fn to_bits(self) -> Simd<u32, N> {
+        assert!(size_of::<Self>() == size_of::<Simd<u32, N>>());
+        unsafe { crate::mem::transmute_copy(&self) }
+    }
+
+    #[inline]
+    pub(crate) const fn from_bits(bits: Simd<u32, N>) -> Self {
+        assert!(size_of::<Self>() == size_of::<Simd<u32, N>>());
+        unsafe { crate::mem::transmute_copy(&bits) }
+    }
+}
+
+impl<const N: usize> Simd<f64, N> {
+    #[inline]
+    pub(crate) const fn to_bits(self) -> Simd<u64, N> {
+        assert!(size_of::<Self>() == size_of::<Simd<u64, N>>());
+        unsafe { crate::mem::transmute_copy(&self) }
+    }
+
+    #[inline]
+    pub(crate) const fn from_bits(bits: Simd<u64, N>) -> Self {
+        assert!(size_of::<Self>() == size_of::<Simd<u64, N>>());
+        unsafe { crate::mem::transmute_copy(&bits) }
+    }
+}
+
 macro_rules! simd_ty {
     ($id:ident [$elem_type:ty ; $len:literal]: $($param_name:ident),*) => {
-        #[repr(simd)]
-        #[derive(Copy, Clone)]
-        pub(crate) struct $id([$elem_type; $len]);
+        pub(crate) type $id = Simd<$elem_type, $len>;
 
-        #[allow(clippy::use_self)]
         impl $id {
-            /// A value of this type where all elements are zeroed out.
-            pub(crate) const ZERO: Self = unsafe { crate::mem::zeroed() };
-
             #[inline(always)]
             pub(crate) const fn new($($param_name: $elem_type),*) -> Self {
-                $id([$($param_name),*])
-            }
-            #[inline(always)]
-            pub(crate) const fn from_array(elements: [$elem_type; $len]) -> Self {
-                $id(elements)
-            }
-            // FIXME: Workaround rust@60637
-            #[inline(always)]
-            #[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
-            pub(crate) const fn splat(value: $elem_type) -> Self {
-                #[derive(Copy, Clone)]
-                #[repr(simd)]
-                struct JustOne([$elem_type; 1]);
-                let one = JustOne([value]);
-                // SAFETY: 0 is always in-bounds because we're shuffling
-                // a simd type with exactly one element.
-                unsafe { simd_shuffle!(one, one, [0; $len]) }
-            }
-
-            /// Extract the element at position `index`.
-            /// `index` is not a constant so this is not efficient!
-            /// Use for testing only.
-            // FIXME: Workaround rust@60637
-            #[inline(always)]
-            pub(crate) const fn extract(&self, index: usize) -> $elem_type {
-                self.as_array()[index]
-            }
-
-            #[inline]
-            pub(crate) const fn as_array(&self) -> &[$elem_type; $len] {
-                let simd_ptr: *const Self = self;
-                let array_ptr: *const [$elem_type; $len] = simd_ptr.cast();
-                // SAFETY: We can always read the prefix of a simd type as an array.
-                // There might be more padding afterwards for some widths, but
-                // that's not a problem for reading less than that.
-                unsafe { &*array_ptr }
-            }
-        }
-
-        #[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
-        const impl core::cmp::PartialEq for $id {
-            #[inline]
-            fn eq(&self, other: &Self) -> bool {
-                self.as_array() == other.as_array()
-            }
-        }
-
-        impl core::fmt::Debug for $id {
-            #[inline]
-            fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-                debug_simd_finish(f, stringify!($id), self.as_array())
+                Self([$($param_name),*])
             }
         }
     }
 }
 
+#[repr(simd)]
+#[derive(Copy)]
+pub(crate) struct SimdM<T: SimdElement, const N: usize>([T; N]);
+
+impl<T: SimdElement, const N: usize> SimdM<T, N> {
+    #[inline(always)]
+    const fn bool_to_internal(x: bool) -> T {
+        // SAFETY: `T` implements `SimdElement`, so all bit patterns are valid.
+        let zeros = const { unsafe { crate::mem::zeroed::<T>() } };
+        let ones = const {
+            // Ideally, this would be `transmute([0xFFu8; size_of::<T>()])`, but
+            // `size_of::<T>()` is not allowed to use a generic parameter there.
+            let mut r = crate::mem::MaybeUninit::<T>::uninit();
+            let mut i = 0;
+            while i < crate::mem::size_of::<T>() {
+                r.as_bytes_mut()[i] = crate::mem::MaybeUninit::new(0xFF);
+                i += 1;
+            }
+            unsafe { r.assume_init() }
+        };
+        [zeros, ones][x as usize]
+    }
+
+    // FIXME: Workaround rust@60637
+    #[inline(always)]
+    #[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
+    pub(crate) const fn splat(value: bool) -> Self {
+        let one = SimdM([Self::bool_to_internal(value)]);
+        // SAFETY: 0 is always in-bounds because we're shuffling
+        // a simd type with exactly one element.
+        unsafe { simd_shuffle!(one, one, [0; N]) }
+    }
+
+    #[inline]
+    pub(crate) const fn as_array(&self) -> &[T; N] {
+        let simd_ptr: *const Self = self;
+        let array_ptr: *const [T; N] = simd_ptr.cast();
+        // SAFETY: We can always read the prefix of a simd type as an array.
+        // There might be more padding afterwards for some widths, but
+        // that's not a problem for reading less than that.
+        unsafe { &*array_ptr }
+    }
+}
+
+// `#[derive(Clone)]` causes ICE "Projecting into SIMD type core_arch::simd::SimdM is banned by MCP#838"
+impl<T: SimdElement, const N: usize> Clone for SimdM<T, N> {
+    #[inline]
+    fn clone(&self) -> Self {
+        *self
+    }
+}
+
+#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
+impl<T: SimdElement, const N: usize> const crate::cmp::PartialEq for SimdM<T, N> {
+    #[inline]
+    fn eq(&self, other: &Self) -> bool {
+        self.as_array() == other.as_array()
+    }
+}
+
+impl<T: SimdElement, const N: usize> crate::fmt::Debug for SimdM<T, N> {
+    #[inline]
+    fn fmt(&self, f: &mut crate::fmt::Formatter<'_>) -> crate::fmt::Result {
+        debug_simd_finish(f, "SimdM", self.as_array())
+    }
+}
+
 macro_rules! simd_m_ty {
     ($id:ident [$elem_type:ident ; $len:literal]: $($param_name:ident),*) => {
-        #[repr(simd)]
-        #[derive(Copy, Clone)]
-        pub(crate) struct $id([$elem_type; $len]);
+        pub(crate) type $id  = SimdM<$elem_type, $len>;
 
-        #[allow(clippy::use_self)]
         impl $id {
-            #[inline(always)]
-            const fn bool_to_internal(x: bool) -> $elem_type {
-                [0 as $elem_type, !(0 as $elem_type)][x as usize]
-            }
-
             #[inline(always)]
             pub(crate) const fn new($($param_name: bool),*) -> Self {
-                $id([$(Self::bool_to_internal($param_name)),*])
-            }
-
-            // FIXME: Workaround rust@60637
-            #[inline(always)]
-            #[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
-            pub(crate) const fn splat(value: bool) -> Self {
-                #[derive(Copy, Clone)]
-                #[repr(simd)]
-                struct JustOne([$elem_type; 1]);
-                let one = JustOne([Self::bool_to_internal(value)]);
-                // SAFETY: 0 is always in-bounds because we're shuffling
-                // a simd type with exactly one element.
-                unsafe { simd_shuffle!(one, one, [0; $len]) }
-            }
-
-            #[inline]
-            pub(crate) const fn as_array(&self) -> &[$elem_type; $len] {
-                let simd_ptr: *const Self = self;
-                let array_ptr: *const [$elem_type; $len] = simd_ptr.cast();
-                // SAFETY: We can always read the prefix of a simd type as an array.
-                // There might be more padding afterwards for some widths, but
-                // that's not a problem for reading less than that.
-                unsafe { &*array_ptr }
-            }
-        }
-
-        #[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
-        const impl core::cmp::PartialEq for $id {
-            #[inline]
-            fn eq(&self, other: &Self) -> bool {
-                self.as_array() == other.as_array()
-            }
-        }
-
-        impl core::fmt::Debug for $id {
-            #[inline]
-            fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-                debug_simd_finish(f, stringify!($id), self.as_array())
+                Self([$(Self::bool_to_internal($param_name)),*])
             }
         }
     }

From dab553268a52a4f494f57e6db4feccae9e26a491 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Eduardo=20S=C3=A1nchez=20Mu=C3=B1oz?= <eduardosm-dev@e64.io>
Date: Thu, 1 Jan 2026 22:48:01 +0100
Subject: [PATCH 08/97] x86: avoid using `transmute` in some tests

---
 .../stdarch/crates/core_arch/src/x86/sse.rs   | 266 +++++++++---------
 .../stdarch/crates/core_arch/src/x86/sse2.rs  |  38 ++-
 2 files changed, 150 insertions(+), 154 deletions(-)

diff --git a/library/stdarch/crates/core_arch/src/x86/sse.rs b/library/stdarch/crates/core_arch/src/x86/sse.rs
index 751f969e50c3..f167e8381d27 100644
--- a/library/stdarch/crates/core_arch/src/x86/sse.rs
+++ b/library/stdarch/crates/core_arch/src/x86/sse.rs
@@ -2079,7 +2079,7 @@ pub unsafe fn _mm_stream_ps(mem_addr: *mut f32, a: __m128) {
 #[cfg(test)]
 mod tests {
     use crate::core_arch::assert_eq_const as assert_eq;
-    use crate::{hint::black_box, mem::transmute, ptr};
+    use crate::{hint::black_box, ptr};
     use std::boxed;
     use stdarch_test::simd_test;
 
@@ -2221,7 +2221,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_min_ps() {
+    fn test_mm_min_ps() {
         let a = _mm_setr_ps(-1.0, 5.0, 0.0, -10.0);
         let b = _mm_setr_ps(-100.0, 20.0, 0.0, -5.0);
         let r = _mm_min_ps(a, b);
@@ -2234,10 +2234,10 @@ mod tests {
         // `r1` to `a` and `r2` to `b`.
         let a = _mm_setr_ps(-0.0, 0.0, 0.0, 0.0);
         let b = _mm_setr_ps(0.0, 0.0, 0.0, 0.0);
-        let r1: [u8; 16] = transmute(_mm_min_ps(a, b));
-        let r2: [u8; 16] = transmute(_mm_min_ps(b, a));
-        let a: [u8; 16] = transmute(a);
-        let b: [u8; 16] = transmute(b);
+        let r1 = _mm_min_ps(a, b).as_f32x4().to_bits();
+        let r2 = _mm_min_ps(b, a).as_f32x4().to_bits();
+        let a = a.as_f32x4().to_bits();
+        let b = b.as_f32x4().to_bits();
         assert_eq!(r1, b);
         assert_eq!(r2, a);
         assert_ne!(a, b); // sanity check that -0.0 is actually present
@@ -2252,7 +2252,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_max_ps() {
+    fn test_mm_max_ps() {
         let a = _mm_setr_ps(-1.0, 5.0, 0.0, -10.0);
         let b = _mm_setr_ps(-100.0, 20.0, 0.0, -5.0);
         let r = _mm_max_ps(a, b);
@@ -2261,67 +2261,67 @@ mod tests {
         // Check SSE-specific semantics for -0.0 handling.
         let a = _mm_setr_ps(-0.0, 0.0, 0.0, 0.0);
         let b = _mm_setr_ps(0.0, 0.0, 0.0, 0.0);
-        let r1: [u8; 16] = transmute(_mm_max_ps(a, b));
-        let r2: [u8; 16] = transmute(_mm_max_ps(b, a));
-        let a: [u8; 16] = transmute(a);
-        let b: [u8; 16] = transmute(b);
+        let r1 = _mm_max_ps(a, b).as_f32x4().to_bits();
+        let r2 = _mm_max_ps(b, a).as_f32x4().to_bits();
+        let a = a.as_f32x4().to_bits();
+        let b = b.as_f32x4().to_bits();
         assert_eq!(r1, b);
         assert_eq!(r2, a);
         assert_ne!(a, b); // sanity check that -0.0 is actually present
     }
 
     #[simd_test(enable = "sse")]
-    const unsafe fn test_mm_and_ps() {
-        let a = transmute(u32x4::splat(0b0011));
-        let b = transmute(u32x4::splat(0b0101));
+    const fn test_mm_and_ps() {
+        let a = f32x4::from_bits(u32x4::splat(0b0011)).as_m128();
+        let b = f32x4::from_bits(u32x4::splat(0b0101)).as_m128();
         let r = _mm_and_ps(*black_box(&a), *black_box(&b));
-        let e = transmute(u32x4::splat(0b0001));
+        let e = f32x4::from_bits(u32x4::splat(0b0001)).as_m128();
         assert_eq_m128(r, e);
     }
 
     #[simd_test(enable = "sse")]
-    const unsafe fn test_mm_andnot_ps() {
-        let a = transmute(u32x4::splat(0b0011));
-        let b = transmute(u32x4::splat(0b0101));
+    const fn test_mm_andnot_ps() {
+        let a = f32x4::from_bits(u32x4::splat(0b0011)).as_m128();
+        let b = f32x4::from_bits(u32x4::splat(0b0101)).as_m128();
         let r = _mm_andnot_ps(*black_box(&a), *black_box(&b));
-        let e = transmute(u32x4::splat(0b0100));
+        let e = f32x4::from_bits(u32x4::splat(0b0100)).as_m128();
         assert_eq_m128(r, e);
     }
 
     #[simd_test(enable = "sse")]
-    const unsafe fn test_mm_or_ps() {
-        let a = transmute(u32x4::splat(0b0011));
-        let b = transmute(u32x4::splat(0b0101));
+    const fn test_mm_or_ps() {
+        let a = f32x4::from_bits(u32x4::splat(0b0011)).as_m128();
+        let b = f32x4::from_bits(u32x4::splat(0b0101)).as_m128();
         let r = _mm_or_ps(*black_box(&a), *black_box(&b));
-        let e = transmute(u32x4::splat(0b0111));
+        let e = f32x4::from_bits(u32x4::splat(0b0111)).as_m128();
         assert_eq_m128(r, e);
     }
 
     #[simd_test(enable = "sse")]
-    const unsafe fn test_mm_xor_ps() {
-        let a = transmute(u32x4::splat(0b0011));
-        let b = transmute(u32x4::splat(0b0101));
+    const fn test_mm_xor_ps() {
+        let a = f32x4::from_bits(u32x4::splat(0b0011)).as_m128();
+        let b = f32x4::from_bits(u32x4::splat(0b0101)).as_m128();
         let r = _mm_xor_ps(*black_box(&a), *black_box(&b));
-        let e = transmute(u32x4::splat(0b0110));
+        let e = f32x4::from_bits(u32x4::splat(0b0110)).as_m128();
         assert_eq_m128(r, e);
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_cmpeq_ss() {
+    fn test_mm_cmpeq_ss() {
         let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
         let b = _mm_setr_ps(-1.0, 5.0, 6.0, 7.0);
-        let r: u32x4 = transmute(_mm_cmpeq_ss(a, b));
-        let e: u32x4 = transmute(_mm_setr_ps(f32::from_bits(0), 2.0, 3.0, 4.0));
+        let r = _mm_cmpeq_ss(a, b).as_f32x4().to_bits();
+        let e = f32x4::new(f32::from_bits(0), 2.0, 3.0, 4.0).to_bits();
         assert_eq!(r, e);
 
         let b2 = _mm_setr_ps(1.0, 5.0, 6.0, 7.0);
-        let r2: u32x4 = transmute(_mm_cmpeq_ss(a, b2));
-        let e2: u32x4 = transmute(_mm_setr_ps(f32::from_bits(0xffffffff), 2.0, 3.0, 4.0));
+        let r2 = _mm_cmpeq_ss(a, b2).as_f32x4().to_bits();
+        let e2 = f32x4::new(f32::from_bits(0xffffffff), 2.0, 3.0, 4.0).to_bits();
         assert_eq!(r2, e2);
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_cmplt_ss() {
+    fn test_mm_cmplt_ss() {
         let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
         let b = _mm_setr_ps(0.0, 5.0, 6.0, 7.0);
         let c = _mm_setr_ps(1.0, 5.0, 6.0, 7.0);
@@ -2331,21 +2331,21 @@ mod tests {
         let c1 = 0u32; // a.extract(0) < c.extract(0)
         let d1 = !0u32; // a.extract(0) < d.extract(0)
 
-        let rb: u32x4 = transmute(_mm_cmplt_ss(a, b));
-        let eb: u32x4 = transmute(_mm_setr_ps(f32::from_bits(b1), 2.0, 3.0, 4.0));
+        let rb = _mm_cmplt_ss(a, b).as_f32x4().to_bits();
+        let eb = f32x4::new(f32::from_bits(b1), 2.0, 3.0, 4.0).to_bits();
         assert_eq!(rb, eb);
 
-        let rc: u32x4 = transmute(_mm_cmplt_ss(a, c));
-        let ec: u32x4 = transmute(_mm_setr_ps(f32::from_bits(c1), 2.0, 3.0, 4.0));
+        let rc = _mm_cmplt_ss(a, c).as_f32x4().to_bits();
+        let ec = f32x4::new(f32::from_bits(c1), 2.0, 3.0, 4.0).to_bits();
         assert_eq!(rc, ec);
 
-        let rd: u32x4 = transmute(_mm_cmplt_ss(a, d));
-        let ed: u32x4 = transmute(_mm_setr_ps(f32::from_bits(d1), 2.0, 3.0, 4.0));
+        let rd = _mm_cmplt_ss(a, d).as_f32x4().to_bits();
+        let ed = f32x4::new(f32::from_bits(d1), 2.0, 3.0, 4.0).to_bits();
         assert_eq!(rd, ed);
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_cmple_ss() {
+    fn test_mm_cmple_ss() {
         let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
         let b = _mm_setr_ps(0.0, 5.0, 6.0, 7.0);
         let c = _mm_setr_ps(1.0, 5.0, 6.0, 7.0);
@@ -2355,21 +2355,21 @@ mod tests {
         let c1 = !0u32; // a.extract(0) <= c.extract(0)
         let d1 = !0u32; // a.extract(0) <= d.extract(0)
 
-        let rb: u32x4 = transmute(_mm_cmple_ss(a, b));
-        let eb: u32x4 = transmute(_mm_setr_ps(f32::from_bits(b1), 2.0, 3.0, 4.0));
+        let rb = _mm_cmple_ss(a, b).as_f32x4().to_bits();
+        let eb = f32x4::new(f32::from_bits(b1), 2.0, 3.0, 4.0).to_bits();
         assert_eq!(rb, eb);
 
-        let rc: u32x4 = transmute(_mm_cmple_ss(a, c));
-        let ec: u32x4 = transmute(_mm_setr_ps(f32::from_bits(c1), 2.0, 3.0, 4.0));
+        let rc = _mm_cmple_ss(a, c).as_f32x4().to_bits();
+        let ec = f32x4::new(f32::from_bits(c1), 2.0, 3.0, 4.0).to_bits();
         assert_eq!(rc, ec);
 
-        let rd: u32x4 = transmute(_mm_cmple_ss(a, d));
-        let ed: u32x4 = transmute(_mm_setr_ps(f32::from_bits(d1), 2.0, 3.0, 4.0));
+        let rd = _mm_cmple_ss(a, d).as_f32x4().to_bits();
+        let ed = f32x4::new(f32::from_bits(d1), 2.0, 3.0, 4.0).to_bits();
         assert_eq!(rd, ed);
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_cmpgt_ss() {
+    fn test_mm_cmpgt_ss() {
         let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
         let b = _mm_setr_ps(0.0, 5.0, 6.0, 7.0);
         let c = _mm_setr_ps(1.0, 5.0, 6.0, 7.0);
@@ -2379,21 +2379,21 @@ mod tests {
         let c1 = 0u32; // a.extract(0) > c.extract(0)
         let d1 = 0u32; // a.extract(0) > d.extract(0)
 
-        let rb: u32x4 = transmute(_mm_cmpgt_ss(a, b));
-        let eb: u32x4 = transmute(_mm_setr_ps(f32::from_bits(b1), 2.0, 3.0, 4.0));
+        let rb = _mm_cmpgt_ss(a, b).as_f32x4().to_bits();
+        let eb = f32x4::new(f32::from_bits(b1), 2.0, 3.0, 4.0).to_bits();
         assert_eq!(rb, eb);
 
-        let rc: u32x4 = transmute(_mm_cmpgt_ss(a, c));
-        let ec: u32x4 = transmute(_mm_setr_ps(f32::from_bits(c1), 2.0, 3.0, 4.0));
+        let rc = _mm_cmpgt_ss(a, c).as_f32x4().to_bits();
+        let ec = f32x4::new(f32::from_bits(c1), 2.0, 3.0, 4.0).to_bits();
         assert_eq!(rc, ec);
 
-        let rd: u32x4 = transmute(_mm_cmpgt_ss(a, d));
-        let ed: u32x4 = transmute(_mm_setr_ps(f32::from_bits(d1), 2.0, 3.0, 4.0));
+        let rd = _mm_cmpgt_ss(a, d).as_f32x4().to_bits();
+        let ed = f32x4::new(f32::from_bits(d1), 2.0, 3.0, 4.0).to_bits();
         assert_eq!(rd, ed);
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_cmpge_ss() {
+    fn test_mm_cmpge_ss() {
         let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
         let b = _mm_setr_ps(0.0, 5.0, 6.0, 7.0);
         let c = _mm_setr_ps(1.0, 5.0, 6.0, 7.0);
@@ -2403,21 +2403,21 @@ mod tests {
         let c1 = !0u32; // a.extract(0) >= c.extract(0)
         let d1 = 0u32; // a.extract(0) >= d.extract(0)
 
-        let rb: u32x4 = transmute(_mm_cmpge_ss(a, b));
-        let eb: u32x4 = transmute(_mm_setr_ps(f32::from_bits(b1), 2.0, 3.0, 4.0));
+        let rb = _mm_cmpge_ss(a, b).as_f32x4().to_bits();
+        let eb = f32x4::new(f32::from_bits(b1), 2.0, 3.0, 4.0).to_bits();
         assert_eq!(rb, eb);
 
-        let rc: u32x4 = transmute(_mm_cmpge_ss(a, c));
-        let ec: u32x4 = transmute(_mm_setr_ps(f32::from_bits(c1), 2.0, 3.0, 4.0));
+        let rc = _mm_cmpge_ss(a, c).as_f32x4().to_bits();
+        let ec = f32x4::new(f32::from_bits(c1), 2.0, 3.0, 4.0).to_bits();
         assert_eq!(rc, ec);
 
-        let rd: u32x4 = transmute(_mm_cmpge_ss(a, d));
-        let ed: u32x4 = transmute(_mm_setr_ps(f32::from_bits(d1), 2.0, 3.0, 4.0));
+        let rd = _mm_cmpge_ss(a, d).as_f32x4().to_bits();
+        let ed = f32x4::new(f32::from_bits(d1), 2.0, 3.0, 4.0).to_bits();
         assert_eq!(rd, ed);
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_cmpneq_ss() {
+    fn test_mm_cmpneq_ss() {
         let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
         let b = _mm_setr_ps(0.0, 5.0, 6.0, 7.0);
         let c = _mm_setr_ps(1.0, 5.0, 6.0, 7.0);
@@ -2427,21 +2427,21 @@ mod tests {
         let c1 = 0u32; // a.extract(0) != c.extract(0)
         let d1 = !0u32; // a.extract(0) != d.extract(0)
 
-        let rb: u32x4 = transmute(_mm_cmpneq_ss(a, b));
-        let eb: u32x4 = transmute(_mm_setr_ps(f32::from_bits(b1), 2.0, 3.0, 4.0));
+        let rb = _mm_cmpneq_ss(a, b).as_f32x4().to_bits();
+        let eb = f32x4::new(f32::from_bits(b1), 2.0, 3.0, 4.0).to_bits();
         assert_eq!(rb, eb);
 
-        let rc: u32x4 = transmute(_mm_cmpneq_ss(a, c));
-        let ec: u32x4 = transmute(_mm_setr_ps(f32::from_bits(c1), 2.0, 3.0, 4.0));
+        let rc = _mm_cmpneq_ss(a, c).as_f32x4().to_bits();
+        let ec = f32x4::new(f32::from_bits(c1), 2.0, 3.0, 4.0).to_bits();
         assert_eq!(rc, ec);
 
-        let rd: u32x4 = transmute(_mm_cmpneq_ss(a, d));
-        let ed: u32x4 = transmute(_mm_setr_ps(f32::from_bits(d1), 2.0, 3.0, 4.0));
+        let rd = _mm_cmpneq_ss(a, d).as_f32x4().to_bits();
+        let ed = f32x4::new(f32::from_bits(d1), 2.0, 3.0, 4.0).to_bits();
         assert_eq!(rd, ed);
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_cmpnlt_ss() {
+    fn test_mm_cmpnlt_ss() {
         // TODO: this test is exactly the same as for `_mm_cmpge_ss`, but there
         // must be a difference. It may have to do with behavior in the
         // presence of NaNs (signaling or quiet). If so, we should add tests
@@ -2456,21 +2456,21 @@ mod tests {
         let c1 = !0u32; // a.extract(0) >= c.extract(0)
         let d1 = 0u32; // a.extract(0) >= d.extract(0)
 
-        let rb: u32x4 = transmute(_mm_cmpnlt_ss(a, b));
-        let eb: u32x4 = transmute(_mm_setr_ps(f32::from_bits(b1), 2.0, 3.0, 4.0));
+        let rb = _mm_cmpnlt_ss(a, b).as_f32x4().to_bits();
+        let eb = f32x4::new(f32::from_bits(b1), 2.0, 3.0, 4.0).to_bits();
         assert_eq!(rb, eb);
 
-        let rc: u32x4 = transmute(_mm_cmpnlt_ss(a, c));
-        let ec: u32x4 = transmute(_mm_setr_ps(f32::from_bits(c1), 2.0, 3.0, 4.0));
+        let rc = _mm_cmpnlt_ss(a, c).as_f32x4().to_bits();
+        let ec = f32x4::new(f32::from_bits(c1), 2.0, 3.0, 4.0).to_bits();
         assert_eq!(rc, ec);
 
-        let rd: u32x4 = transmute(_mm_cmpnlt_ss(a, d));
-        let ed: u32x4 = transmute(_mm_setr_ps(f32::from_bits(d1), 2.0, 3.0, 4.0));
+        let rd = _mm_cmpnlt_ss(a, d).as_f32x4().to_bits();
+        let ed = f32x4::new(f32::from_bits(d1), 2.0, 3.0, 4.0).to_bits();
         assert_eq!(rd, ed);
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_cmpnle_ss() {
+    fn test_mm_cmpnle_ss() {
         // TODO: this test is exactly the same as for `_mm_cmpgt_ss`, but there
         // must be a difference. It may have to do with behavior in the
         // presence
@@ -2485,21 +2485,21 @@ mod tests {
         let c1 = 0u32; // a.extract(0) > c.extract(0)
         let d1 = 0u32; // a.extract(0) > d.extract(0)
 
-        let rb: u32x4 = transmute(_mm_cmpnle_ss(a, b));
-        let eb: u32x4 = transmute(_mm_setr_ps(f32::from_bits(b1), 2.0, 3.0, 4.0));
+        let rb = _mm_cmpnle_ss(a, b).as_f32x4().to_bits();
+        let eb = f32x4::new(f32::from_bits(b1), 2.0, 3.0, 4.0).to_bits();
         assert_eq!(rb, eb);
 
-        let rc: u32x4 = transmute(_mm_cmpnle_ss(a, c));
-        let ec: u32x4 = transmute(_mm_setr_ps(f32::from_bits(c1), 2.0, 3.0, 4.0));
+        let rc = _mm_cmpnle_ss(a, c).as_f32x4().to_bits();
+        let ec = f32x4::new(f32::from_bits(c1), 2.0, 3.0, 4.0).to_bits();
         assert_eq!(rc, ec);
 
-        let rd: u32x4 = transmute(_mm_cmpnle_ss(a, d));
-        let ed: u32x4 = transmute(_mm_setr_ps(f32::from_bits(d1), 2.0, 3.0, 4.0));
+        let rd = _mm_cmpnle_ss(a, d).as_f32x4().to_bits();
+        let ed = f32x4::new(f32::from_bits(d1), 2.0, 3.0, 4.0).to_bits();
         assert_eq!(rd, ed);
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_cmpngt_ss() {
+    fn test_mm_cmpngt_ss() {
         // TODO: this test is exactly the same as for `_mm_cmple_ss`, but there
         // must be a difference. It may have to do with behavior in the
         // presence of NaNs (signaling or quiet). If so, we should add tests
@@ -2514,21 +2514,21 @@ mod tests {
         let c1 = !0u32; // a.extract(0) <= c.extract(0)
         let d1 = !0u32; // a.extract(0) <= d.extract(0)
 
-        let rb: u32x4 = transmute(_mm_cmpngt_ss(a, b));
-        let eb: u32x4 = transmute(_mm_setr_ps(f32::from_bits(b1), 2.0, 3.0, 4.0));
+        let rb = _mm_cmpngt_ss(a, b).as_f32x4().to_bits();
+        let eb = f32x4::new(f32::from_bits(b1), 2.0, 3.0, 4.0).to_bits();
         assert_eq!(rb, eb);
 
-        let rc: u32x4 = transmute(_mm_cmpngt_ss(a, c));
-        let ec: u32x4 = transmute(_mm_setr_ps(f32::from_bits(c1), 2.0, 3.0, 4.0));
+        let rc = _mm_cmpngt_ss(a, c).as_f32x4().to_bits();
+        let ec = f32x4::new(f32::from_bits(c1), 2.0, 3.0, 4.0).to_bits();
         assert_eq!(rc, ec);
 
-        let rd: u32x4 = transmute(_mm_cmpngt_ss(a, d));
-        let ed: u32x4 = transmute(_mm_setr_ps(f32::from_bits(d1), 2.0, 3.0, 4.0));
+        let rd = _mm_cmpngt_ss(a, d).as_f32x4().to_bits();
+        let ed = f32x4::new(f32::from_bits(d1), 2.0, 3.0, 4.0).to_bits();
         assert_eq!(rd, ed);
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_cmpnge_ss() {
+    fn test_mm_cmpnge_ss() {
         // TODO: this test is exactly the same as for `_mm_cmplt_ss`, but there
         // must be a difference. It may have to do with behavior in the
         // presence of NaNs (signaling or quiet). If so, we should add tests
@@ -2543,21 +2543,21 @@ mod tests {
         let c1 = 0u32; // a.extract(0) < c.extract(0)
         let d1 = !0u32; // a.extract(0) < d.extract(0)
 
-        let rb: u32x4 = transmute(_mm_cmpnge_ss(a, b));
-        let eb: u32x4 = transmute(_mm_setr_ps(f32::from_bits(b1), 2.0, 3.0, 4.0));
+        let rb = _mm_cmpnge_ss(a, b).as_f32x4().to_bits();
+        let eb = f32x4::new(f32::from_bits(b1), 2.0, 3.0, 4.0).to_bits();
         assert_eq!(rb, eb);
 
-        let rc: u32x4 = transmute(_mm_cmpnge_ss(a, c));
-        let ec: u32x4 = transmute(_mm_setr_ps(f32::from_bits(c1), 2.0, 3.0, 4.0));
+        let rc = _mm_cmpnge_ss(a, c).as_f32x4().to_bits();
+        let ec = f32x4::new(f32::from_bits(c1), 2.0, 3.0, 4.0).to_bits();
         assert_eq!(rc, ec);
 
-        let rd: u32x4 = transmute(_mm_cmpnge_ss(a, d));
-        let ed: u32x4 = transmute(_mm_setr_ps(f32::from_bits(d1), 2.0, 3.0, 4.0));
+        let rd = _mm_cmpnge_ss(a, d).as_f32x4().to_bits();
+        let ed = f32x4::new(f32::from_bits(d1), 2.0, 3.0, 4.0).to_bits();
         assert_eq!(rd, ed);
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_cmpord_ss() {
+    fn test_mm_cmpord_ss() {
         let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
         let b = _mm_setr_ps(0.0, 5.0, 6.0, 7.0);
         let c = _mm_setr_ps(NAN, 5.0, 6.0, 7.0);
@@ -2567,21 +2567,21 @@ mod tests {
         let c1 = 0u32; // a.extract(0) ord c.extract(0)
         let d1 = !0u32; // a.extract(0) ord d.extract(0)
 
-        let rb: u32x4 = transmute(_mm_cmpord_ss(a, b));
-        let eb: u32x4 = transmute(_mm_setr_ps(f32::from_bits(b1), 2.0, 3.0, 4.0));
+        let rb = _mm_cmpord_ss(a, b).as_f32x4().to_bits();
+        let eb = f32x4::new(f32::from_bits(b1), 2.0, 3.0, 4.0).to_bits();
         assert_eq!(rb, eb);
 
-        let rc: u32x4 = transmute(_mm_cmpord_ss(a, c));
-        let ec: u32x4 = transmute(_mm_setr_ps(f32::from_bits(c1), 2.0, 3.0, 4.0));
+        let rc = _mm_cmpord_ss(a, c).as_f32x4().to_bits();
+        let ec = f32x4::new(f32::from_bits(c1), 2.0, 3.0, 4.0).to_bits();
         assert_eq!(rc, ec);
 
-        let rd: u32x4 = transmute(_mm_cmpord_ss(a, d));
-        let ed: u32x4 = transmute(_mm_setr_ps(f32::from_bits(d1), 2.0, 3.0, 4.0));
+        let rd = _mm_cmpord_ss(a, d).as_f32x4().to_bits();
+        let ed = f32x4::new(f32::from_bits(d1), 2.0, 3.0, 4.0).to_bits();
         assert_eq!(rd, ed);
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_cmpunord_ss() {
+    fn test_mm_cmpunord_ss() {
         let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
         let b = _mm_setr_ps(0.0, 5.0, 6.0, 7.0);
         let c = _mm_setr_ps(NAN, 5.0, 6.0, 7.0);
@@ -2591,160 +2591,160 @@ mod tests {
         let c1 = !0u32; // a.extract(0) unord c.extract(0)
         let d1 = 0u32; // a.extract(0) unord d.extract(0)
 
-        let rb: u32x4 = transmute(_mm_cmpunord_ss(a, b));
-        let eb: u32x4 = transmute(_mm_setr_ps(f32::from_bits(b1), 2.0, 3.0, 4.0));
+        let rb = _mm_cmpunord_ss(a, b).as_f32x4().to_bits();
+        let eb = f32x4::new(f32::from_bits(b1), 2.0, 3.0, 4.0).to_bits();
         assert_eq!(rb, eb);
 
-        let rc: u32x4 = transmute(_mm_cmpunord_ss(a, c));
-        let ec: u32x4 = transmute(_mm_setr_ps(f32::from_bits(c1), 2.0, 3.0, 4.0));
+        let rc = _mm_cmpunord_ss(a, c).as_f32x4().to_bits();
+        let ec = f32x4::new(f32::from_bits(c1), 2.0, 3.0, 4.0).to_bits();
         assert_eq!(rc, ec);
 
-        let rd: u32x4 = transmute(_mm_cmpunord_ss(a, d));
-        let ed: u32x4 = transmute(_mm_setr_ps(f32::from_bits(d1), 2.0, 3.0, 4.0));
+        let rd = _mm_cmpunord_ss(a, d).as_f32x4().to_bits();
+        let ed = f32x4::new(f32::from_bits(d1), 2.0, 3.0, 4.0).to_bits();
         assert_eq!(rd, ed);
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_cmpeq_ps() {
+    fn test_mm_cmpeq_ps() {
         let a = _mm_setr_ps(10.0, 50.0, 1.0, NAN);
         let b = _mm_setr_ps(15.0, 20.0, 1.0, NAN);
         let tru = !0u32;
         let fls = 0u32;
 
         let e = u32x4::new(fls, fls, tru, fls);
-        let r: u32x4 = transmute(_mm_cmpeq_ps(a, b));
+        let r = _mm_cmpeq_ps(a, b).as_f32x4().to_bits();
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_cmplt_ps() {
+    fn test_mm_cmplt_ps() {
         let a = _mm_setr_ps(10.0, 50.0, 1.0, NAN);
         let b = _mm_setr_ps(15.0, 20.0, 1.0, NAN);
         let tru = !0u32;
         let fls = 0u32;
 
         let e = u32x4::new(tru, fls, fls, fls);
-        let r: u32x4 = transmute(_mm_cmplt_ps(a, b));
+        let r = _mm_cmplt_ps(a, b).as_f32x4().to_bits();
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_cmple_ps() {
+    fn test_mm_cmple_ps() {
         let a = _mm_setr_ps(10.0, 50.0, 1.0, 4.0);
         let b = _mm_setr_ps(15.0, 20.0, 1.0, NAN);
         let tru = !0u32;
         let fls = 0u32;
 
         let e = u32x4::new(tru, fls, tru, fls);
-        let r: u32x4 = transmute(_mm_cmple_ps(a, b));
+        let r = _mm_cmple_ps(a, b).as_f32x4().to_bits();
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_cmpgt_ps() {
+    fn test_mm_cmpgt_ps() {
         let a = _mm_setr_ps(10.0, 50.0, 1.0, NAN);
         let b = _mm_setr_ps(15.0, 20.0, 1.0, 42.0);
         let tru = !0u32;
         let fls = 0u32;
 
         let e = u32x4::new(fls, tru, fls, fls);
-        let r: u32x4 = transmute(_mm_cmpgt_ps(a, b));
+        let r = _mm_cmpgt_ps(a, b).as_f32x4().to_bits();
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_cmpge_ps() {
+    fn test_mm_cmpge_ps() {
         let a = _mm_setr_ps(10.0, 50.0, 1.0, NAN);
         let b = _mm_setr_ps(15.0, 20.0, 1.0, 42.0);
         let tru = !0u32;
         let fls = 0u32;
 
         let e = u32x4::new(fls, tru, tru, fls);
-        let r: u32x4 = transmute(_mm_cmpge_ps(a, b));
+        let r = _mm_cmpge_ps(a, b).as_f32x4().to_bits();
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_cmpneq_ps() {
+    fn test_mm_cmpneq_ps() {
         let a = _mm_setr_ps(10.0, 50.0, 1.0, NAN);
         let b = _mm_setr_ps(15.0, 20.0, 1.0, NAN);
         let tru = !0u32;
         let fls = 0u32;
 
         let e = u32x4::new(tru, tru, fls, tru);
-        let r: u32x4 = transmute(_mm_cmpneq_ps(a, b));
+        let r = _mm_cmpneq_ps(a, b).as_f32x4().to_bits();
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_cmpnlt_ps() {
+    fn test_mm_cmpnlt_ps() {
         let a = _mm_setr_ps(10.0, 50.0, 1.0, NAN);
         let b = _mm_setr_ps(15.0, 20.0, 1.0, 5.0);
         let tru = !0u32;
         let fls = 0u32;
 
         let e = u32x4::new(fls, tru, tru, tru);
-        let r: u32x4 = transmute(_mm_cmpnlt_ps(a, b));
+        let r = _mm_cmpnlt_ps(a, b).as_f32x4().to_bits();
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_cmpnle_ps() {
+    fn test_mm_cmpnle_ps() {
         let a = _mm_setr_ps(10.0, 50.0, 1.0, NAN);
         let b = _mm_setr_ps(15.0, 20.0, 1.0, 5.0);
         let tru = !0u32;
         let fls = 0u32;
 
         let e = u32x4::new(fls, tru, fls, tru);
-        let r: u32x4 = transmute(_mm_cmpnle_ps(a, b));
+        let r = _mm_cmpnle_ps(a, b).as_f32x4().to_bits();
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_cmpngt_ps() {
+    fn test_mm_cmpngt_ps() {
         let a = _mm_setr_ps(10.0, 50.0, 1.0, NAN);
         let b = _mm_setr_ps(15.0, 20.0, 1.0, 5.0);
         let tru = !0u32;
         let fls = 0u32;
 
         let e = u32x4::new(tru, fls, tru, tru);
-        let r: u32x4 = transmute(_mm_cmpngt_ps(a, b));
+        let r = _mm_cmpngt_ps(a, b).as_f32x4().to_bits();
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_cmpnge_ps() {
+    fn test_mm_cmpnge_ps() {
         let a = _mm_setr_ps(10.0, 50.0, 1.0, NAN);
         let b = _mm_setr_ps(15.0, 20.0, 1.0, 5.0);
         let tru = !0u32;
         let fls = 0u32;
 
         let e = u32x4::new(tru, fls, fls, tru);
-        let r: u32x4 = transmute(_mm_cmpnge_ps(a, b));
+        let r = _mm_cmpnge_ps(a, b).as_f32x4().to_bits();
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_cmpord_ps() {
+    fn test_mm_cmpord_ps() {
         let a = _mm_setr_ps(10.0, 50.0, NAN, NAN);
         let b = _mm_setr_ps(15.0, NAN, 1.0, NAN);
         let tru = !0u32;
         let fls = 0u32;
 
         let e = u32x4::new(tru, fls, fls, fls);
-        let r: u32x4 = transmute(_mm_cmpord_ps(a, b));
+        let r = _mm_cmpord_ps(a, b).as_f32x4().to_bits();
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "sse")]
-    unsafe fn test_mm_cmpunord_ps() {
+    fn test_mm_cmpunord_ps() {
         let a = _mm_setr_ps(10.0, 50.0, NAN, NAN);
         let b = _mm_setr_ps(15.0, NAN, 1.0, NAN);
         let tru = !0u32;
         let fls = 0u32;
 
         let e = u32x4::new(fls, tru, tru, tru);
-        let r: u32x4 = transmute(_mm_cmpunord_ps(a, b));
+        let r = _mm_cmpunord_ps(a, b).as_f32x4().to_bits();
         assert_eq!(r, e);
     }
 
diff --git a/library/stdarch/crates/core_arch/src/x86/sse2.rs b/library/stdarch/crates/core_arch/src/x86/sse2.rs
index d7ac00287f5e..0850d05445c6 100644
--- a/library/stdarch/crates/core_arch/src/x86/sse2.rs
+++ b/library/stdarch/crates/core_arch/src/x86/sse2.rs
@@ -3272,11 +3272,7 @@ mod tests {
         core_arch::{simd::*, x86::*},
         hint::black_box,
     };
-    use std::{
-        boxed, f32, f64,
-        mem::{self, transmute},
-        ptr,
-    };
+    use std::{boxed, f32, f64, mem, ptr};
     use stdarch_test::simd_test;
 
     const NAN: f64 = f64::NAN;
@@ -4585,38 +4581,38 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_and_pd() {
-        let a = transmute(u64x2::splat(5));
-        let b = transmute(u64x2::splat(3));
+    const fn test_mm_and_pd() {
+        let a = f64x2::from_bits(u64x2::splat(5)).as_m128d();
+        let b = f64x2::from_bits(u64x2::splat(3)).as_m128d();
         let r = _mm_and_pd(a, b);
-        let e = transmute(u64x2::splat(1));
+        let e = f64x2::from_bits(u64x2::splat(1)).as_m128d();
         assert_eq_m128d(r, e);
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_andnot_pd() {
-        let a = transmute(u64x2::splat(5));
-        let b = transmute(u64x2::splat(3));
+    const fn test_mm_andnot_pd() {
+        let a = f64x2::from_bits(u64x2::splat(5)).as_m128d();
+        let b = f64x2::from_bits(u64x2::splat(3)).as_m128d();
         let r = _mm_andnot_pd(a, b);
-        let e = transmute(u64x2::splat(2));
+        let e = f64x2::from_bits(u64x2::splat(2)).as_m128d();
         assert_eq_m128d(r, e);
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_or_pd() {
-        let a = transmute(u64x2::splat(5));
-        let b = transmute(u64x2::splat(3));
+    const fn test_mm_or_pd() {
+        let a = f64x2::from_bits(u64x2::splat(5)).as_m128d();
+        let b = f64x2::from_bits(u64x2::splat(3)).as_m128d();
         let r = _mm_or_pd(a, b);
-        let e = transmute(u64x2::splat(7));
+        let e = f64x2::from_bits(u64x2::splat(7)).as_m128d();
         assert_eq_m128d(r, e);
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_xor_pd() {
-        let a = transmute(u64x2::splat(5));
-        let b = transmute(u64x2::splat(3));
+    const fn test_mm_xor_pd() {
+        let a = f64x2::from_bits(u64x2::splat(5)).as_m128d();
+        let b = f64x2::from_bits(u64x2::splat(3)).as_m128d();
         let r = _mm_xor_pd(a, b);
-        let e = transmute(u64x2::splat(6));
+        let e = f64x2::from_bits(u64x2::splat(6)).as_m128d();
         assert_eq_m128d(r, e);
     }
 

From 68701ff93ad6e3168f7aa8a947b895746bfcb9bc Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Eduardo=20S=C3=A1nchez=20Mu=C3=B1oz?= <eduardosm-dev@e64.io>
Date: Thu, 1 Jan 2026 22:48:34 +0100
Subject: [PATCH 09/97] arm_shared: avoid using `transmute` and `unsafe fn` in
 tests

---
 library/stdarch/ci/run.sh                     |    2 +-
 .../src/arm_shared/neon/load_tests.rs         |   97 +-
 .../core_arch/src/arm_shared/neon/mod.rs      | 2177 +++++++++--------
 .../src/arm_shared/neon/store_tests.rs        |  144 +-
 .../src/arm_shared/neon/table_lookup_tests.rs |   27 +-
 .../core_arch/src/arm_shared/test_support.rs  |    8 +-
 .../stdarch/crates/simd-test-macro/src/lib.rs |   47 +-
 7 files changed, 1409 insertions(+), 1093 deletions(-)

diff --git a/library/stdarch/ci/run.sh b/library/stdarch/ci/run.sh
index bb3dcf93e75d..8a0b5fa26f66 100755
--- a/library/stdarch/ci/run.sh
+++ b/library/stdarch/ci/run.sh
@@ -40,7 +40,7 @@ case ${TARGET} in
 	export RUSTFLAGS="${RUSTFLAGS} -C llvm-args=-fast-isel=false"
 	;;
     armv7-*eabihf | thumbv7-*eabihf)
-        export RUSTFLAGS="${RUSTFLAGS} -Ctarget-feature=+neon"
+        export RUSTFLAGS="${RUSTFLAGS} -Ctarget-feature=+neon,+fp16"
         ;;
     amdgcn-*)
         export RUSTFLAGS="${RUSTFLAGS} -Ctarget-cpu=gfx1200"
diff --git a/library/stdarch/crates/core_arch/src/arm_shared/neon/load_tests.rs b/library/stdarch/crates/core_arch/src/arm_shared/neon/load_tests.rs
index bdf511ecf881..cc821b4af202 100644
--- a/library/stdarch/crates/core_arch/src/arm_shared/neon/load_tests.rs
+++ b/library/stdarch/crates/core_arch/src/arm_shared/neon/load_tests.rs
@@ -13,194 +13,195 @@ use crate::core_arch::aarch64::*;
 use crate::core_arch::simd::*;
 use std::mem;
 use stdarch_test::simd_test;
+
 #[simd_test(enable = "neon")]
-unsafe fn test_vld1_s8() {
+fn test_vld1_s8() {
     let a: [i8; 9] = [0, 1, 2, 3, 4, 5, 6, 7, 8];
     let e = i8x8::new(1, 2, 3, 4, 5, 6, 7, 8);
-    let r: i8x8 = transmute(vld1_s8(a[1..].as_ptr()));
+    let r = unsafe { i8x8::from(vld1_s8(a[1..].as_ptr())) };
     assert_eq!(r, e)
 }
 
 #[simd_test(enable = "neon")]
-unsafe fn test_vld1q_s8() {
+fn test_vld1q_s8() {
     let a: [i8; 17] = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16];
     let e = i8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
-    let r: i8x16 = transmute(vld1q_s8(a[1..].as_ptr()));
+    let r = unsafe { i8x16::from(vld1q_s8(a[1..].as_ptr())) };
     assert_eq!(r, e)
 }
 
 #[simd_test(enable = "neon")]
-unsafe fn test_vld1_s16() {
+fn test_vld1_s16() {
     let a: [i16; 5] = [0, 1, 2, 3, 4];
     let e = i16x4::new(1, 2, 3, 4);
-    let r: i16x4 = transmute(vld1_s16(a[1..].as_ptr()));
+    let r = unsafe { i16x4::from(vld1_s16(a[1..].as_ptr())) };
     assert_eq!(r, e)
 }
 
 #[simd_test(enable = "neon")]
-unsafe fn test_vld1q_s16() {
+fn test_vld1q_s16() {
     let a: [i16; 9] = [0, 1, 2, 3, 4, 5, 6, 7, 8];
     let e = i16x8::new(1, 2, 3, 4, 5, 6, 7, 8);
-    let r: i16x8 = transmute(vld1q_s16(a[1..].as_ptr()));
+    let r = unsafe { i16x8::from(vld1q_s16(a[1..].as_ptr())) };
     assert_eq!(r, e)
 }
 
 #[simd_test(enable = "neon")]
-unsafe fn test_vld1_s32() {
+fn test_vld1_s32() {
     let a: [i32; 3] = [0, 1, 2];
     let e = i32x2::new(1, 2);
-    let r: i32x2 = transmute(vld1_s32(a[1..].as_ptr()));
+    let r = unsafe { i32x2::from(vld1_s32(a[1..].as_ptr())) };
     assert_eq!(r, e)
 }
 
 #[simd_test(enable = "neon")]
-unsafe fn test_vld1q_s32() {
+fn test_vld1q_s32() {
     let a: [i32; 5] = [0, 1, 2, 3, 4];
     let e = i32x4::new(1, 2, 3, 4);
-    let r: i32x4 = transmute(vld1q_s32(a[1..].as_ptr()));
+    let r = unsafe { i32x4::from(vld1q_s32(a[1..].as_ptr())) };
     assert_eq!(r, e)
 }
 
 #[simd_test(enable = "neon")]
-unsafe fn test_vld1_s64() {
+fn test_vld1_s64() {
     let a: [i64; 2] = [0, 1];
     let e = i64x1::new(1);
-    let r: i64x1 = transmute(vld1_s64(a[1..].as_ptr()));
+    let r = unsafe { i64x1::from(vld1_s64(a[1..].as_ptr())) };
     assert_eq!(r, e)
 }
 
 #[simd_test(enable = "neon")]
-unsafe fn test_vld1q_s64() {
+fn test_vld1q_s64() {
     let a: [i64; 3] = [0, 1, 2];
     let e = i64x2::new(1, 2);
-    let r: i64x2 = transmute(vld1q_s64(a[1..].as_ptr()));
+    let r = unsafe { i64x2::from(vld1q_s64(a[1..].as_ptr())) };
     assert_eq!(r, e)
 }
 
 #[simd_test(enable = "neon")]
-unsafe fn test_vld1_u8() {
+fn test_vld1_u8() {
     let a: [u8; 9] = [0, 1, 2, 3, 4, 5, 6, 7, 8];
     let e = u8x8::new(1, 2, 3, 4, 5, 6, 7, 8);
-    let r: u8x8 = transmute(vld1_u8(a[1..].as_ptr()));
+    let r = unsafe { u8x8::from(vld1_u8(a[1..].as_ptr())) };
     assert_eq!(r, e)
 }
 
 #[simd_test(enable = "neon")]
-unsafe fn test_vld1q_u8() {
+fn test_vld1q_u8() {
     let a: [u8; 17] = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16];
     let e = u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
-    let r: u8x16 = transmute(vld1q_u8(a[1..].as_ptr()));
+    let r = unsafe { u8x16::from(vld1q_u8(a[1..].as_ptr())) };
     assert_eq!(r, e)
 }
 
 #[simd_test(enable = "neon")]
-unsafe fn test_vld1_u16() {
+fn test_vld1_u16() {
     let a: [u16; 5] = [0, 1, 2, 3, 4];
     let e = u16x4::new(1, 2, 3, 4);
-    let r: u16x4 = transmute(vld1_u16(a[1..].as_ptr()));
+    let r = unsafe { u16x4::from(vld1_u16(a[1..].as_ptr())) };
     assert_eq!(r, e)
 }
 
 #[simd_test(enable = "neon")]
-unsafe fn test_vld1q_u16() {
+fn test_vld1q_u16() {
     let a: [u16; 9] = [0, 1, 2, 3, 4, 5, 6, 7, 8];
     let e = u16x8::new(1, 2, 3, 4, 5, 6, 7, 8);
-    let r: u16x8 = transmute(vld1q_u16(a[1..].as_ptr()));
+    let r = unsafe { u16x8::from(vld1q_u16(a[1..].as_ptr())) };
     assert_eq!(r, e)
 }
 
 #[simd_test(enable = "neon")]
-unsafe fn test_vld1_u32() {
+fn test_vld1_u32() {
     let a: [u32; 3] = [0, 1, 2];
     let e = u32x2::new(1, 2);
-    let r: u32x2 = transmute(vld1_u32(a[1..].as_ptr()));
+    let r = unsafe { u32x2::from(vld1_u32(a[1..].as_ptr())) };
     assert_eq!(r, e)
 }
 
 #[simd_test(enable = "neon")]
-unsafe fn test_vld1q_u32() {
+fn test_vld1q_u32() {
     let a: [u32; 5] = [0, 1, 2, 3, 4];
     let e = u32x4::new(1, 2, 3, 4);
-    let r: u32x4 = transmute(vld1q_u32(a[1..].as_ptr()));
+    let r = unsafe { u32x4::from(vld1q_u32(a[1..].as_ptr())) };
     assert_eq!(r, e)
 }
 
 #[simd_test(enable = "neon")]
-unsafe fn test_vld1_u64() {
+fn test_vld1_u64() {
     let a: [u64; 2] = [0, 1];
     let e = u64x1::new(1);
-    let r: u64x1 = transmute(vld1_u64(a[1..].as_ptr()));
+    let r = unsafe { u64x1::from(vld1_u64(a[1..].as_ptr())) };
     assert_eq!(r, e)
 }
 
 #[simd_test(enable = "neon")]
-unsafe fn test_vld1q_u64() {
+fn test_vld1q_u64() {
     let a: [u64; 3] = [0, 1, 2];
     let e = u64x2::new(1, 2);
-    let r: u64x2 = transmute(vld1q_u64(a[1..].as_ptr()));
+    let r = unsafe { u64x2::from(vld1q_u64(a[1..].as_ptr())) };
     assert_eq!(r, e)
 }
 
 #[simd_test(enable = "neon")]
-unsafe fn test_vld1_p8() {
+fn test_vld1_p8() {
     let a: [p8; 9] = [0, 1, 2, 3, 4, 5, 6, 7, 8];
     let e = u8x8::new(1, 2, 3, 4, 5, 6, 7, 8);
-    let r: u8x8 = transmute(vld1_p8(a[1..].as_ptr()));
+    let r = unsafe { u8x8::from(vld1_p8(a[1..].as_ptr())) };
     assert_eq!(r, e)
 }
 
 #[simd_test(enable = "neon")]
-unsafe fn test_vld1q_p8() {
+fn test_vld1q_p8() {
     let a: [p8; 17] = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16];
     let e = u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
-    let r: u8x16 = transmute(vld1q_p8(a[1..].as_ptr()));
+    let r = unsafe { u8x16::from(vld1q_p8(a[1..].as_ptr())) };
     assert_eq!(r, e)
 }
 
 #[simd_test(enable = "neon")]
-unsafe fn test_vld1_p16() {
+fn test_vld1_p16() {
     let a: [p16; 5] = [0, 1, 2, 3, 4];
     let e = u16x4::new(1, 2, 3, 4);
-    let r: u16x4 = transmute(vld1_p16(a[1..].as_ptr()));
+    let r = unsafe { u16x4::from(vld1_p16(a[1..].as_ptr())) };
     assert_eq!(r, e)
 }
 
 #[simd_test(enable = "neon")]
-unsafe fn test_vld1q_p16() {
+fn test_vld1q_p16() {
     let a: [p16; 9] = [0, 1, 2, 3, 4, 5, 6, 7, 8];
     let e = u16x8::new(1, 2, 3, 4, 5, 6, 7, 8);
-    let r: u16x8 = transmute(vld1q_p16(a[1..].as_ptr()));
+    let r = unsafe { u16x8::from(vld1q_p16(a[1..].as_ptr())) };
     assert_eq!(r, e)
 }
 
 #[simd_test(enable = "neon,aes")]
-unsafe fn test_vld1_p64() {
+fn test_vld1_p64() {
     let a: [p64; 2] = [0, 1];
     let e = u64x1::new(1);
-    let r: u64x1 = transmute(vld1_p64(a[1..].as_ptr()));
+    let r = unsafe { u64x1::from(vld1_p64(a[1..].as_ptr())) };
     assert_eq!(r, e)
 }
 
 #[simd_test(enable = "neon,aes")]
-unsafe fn test_vld1q_p64() {
+fn test_vld1q_p64() {
     let a: [p64; 3] = [0, 1, 2];
     let e = u64x2::new(1, 2);
-    let r: u64x2 = transmute(vld1q_p64(a[1..].as_ptr()));
+    let r = unsafe { u64x2::from(vld1q_p64(a[1..].as_ptr())) };
     assert_eq!(r, e)
 }
 
 #[simd_test(enable = "neon")]
-unsafe fn test_vld1_f32() {
+fn test_vld1_f32() {
     let a: [f32; 3] = [0., 1., 2.];
     let e = f32x2::new(1., 2.);
-    let r: f32x2 = transmute(vld1_f32(a[1..].as_ptr()));
+    let r = unsafe { f32x2::from(vld1_f32(a[1..].as_ptr())) };
     assert_eq!(r, e)
 }
 
 #[simd_test(enable = "neon")]
-unsafe fn test_vld1q_f32() {
+fn test_vld1q_f32() {
     let a: [f32; 5] = [0., 1., 2., 3., 4.];
     let e = f32x4::new(1., 2., 3., 4.);
-    let r: f32x4 = transmute(vld1q_f32(a[1..].as_ptr()));
+    let r = unsafe { f32x4::from(vld1q_f32(a[1..].as_ptr())) };
     assert_eq!(r, e)
 }
diff --git a/library/stdarch/crates/core_arch/src/arm_shared/neon/mod.rs b/library/stdarch/crates/core_arch/src/arm_shared/neon/mod.rs
index 809892e0bfd4..1ca8ce2b1395 100644
--- a/library/stdarch/crates/core_arch/src/arm_shared/neon/mod.rs
+++ b/library/stdarch/crates/core_arch/src/arm_shared/neon/mod.rs
@@ -1247,1268 +1247,1273 @@ mod tests {
     use crate::core_arch::arm::*;
     use crate::core_arch::arm_shared::test_support::*;
     use crate::core_arch::simd::*;
-    use std::{mem::transmute, vec::Vec};
     use stdarch_test::simd_test;
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vld1_lane_s8() {
+    fn test_vld1_lane_s8() {
         let a = i8x8::new(0, 1, 2, 3, 4, 5, 6, 7);
         let elem: i8 = 42;
         let e = i8x8::new(0, 1, 2, 3, 4, 5, 6, 42);
-        let r: i8x8 = transmute(vld1_lane_s8::<7>(&elem, transmute(a)));
+        let r = unsafe { i8x8::from(vld1_lane_s8::<7>(&elem, a.into())) };
         assert_eq!(r, e)
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vld1q_lane_s8() {
+    fn test_vld1q_lane_s8() {
         let a = i8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let elem: i8 = 42;
         let e = i8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 42);
-        let r: i8x16 = transmute(vld1q_lane_s8::<15>(&elem, transmute(a)));
+        let r = unsafe { i8x16::from(vld1q_lane_s8::<15>(&elem, a.into())) };
         assert_eq!(r, e)
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vld1_lane_s16() {
+    fn test_vld1_lane_s16() {
         let a = i16x4::new(0, 1, 2, 3);
         let elem: i16 = 42;
         let e = i16x4::new(0, 1, 2, 42);
-        let r: i16x4 = transmute(vld1_lane_s16::<3>(&elem, transmute(a)));
+        let r = unsafe { i16x4::from(vld1_lane_s16::<3>(&elem, a.into())) };
         assert_eq!(r, e)
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vld1q_lane_s16() {
+    fn test_vld1q_lane_s16() {
         let a = i16x8::new(0, 1, 2, 3, 4, 5, 6, 7);
         let elem: i16 = 42;
         let e = i16x8::new(0, 1, 2, 3, 4, 5, 6, 42);
-        let r: i16x8 = transmute(vld1q_lane_s16::<7>(&elem, transmute(a)));
+        let r = unsafe { i16x8::from(vld1q_lane_s16::<7>(&elem, a.into())) };
         assert_eq!(r, e)
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vld1_lane_s32() {
+    fn test_vld1_lane_s32() {
         let a = i32x2::new(0, 1);
         let elem: i32 = 42;
         let e = i32x2::new(0, 42);
-        let r: i32x2 = transmute(vld1_lane_s32::<1>(&elem, transmute(a)));
+        let r = unsafe { i32x2::from(vld1_lane_s32::<1>(&elem, a.into())) };
         assert_eq!(r, e)
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vld1q_lane_s32() {
+    fn test_vld1q_lane_s32() {
         let a = i32x4::new(0, 1, 2, 3);
         let elem: i32 = 42;
         let e = i32x4::new(0, 1, 2, 42);
-        let r: i32x4 = transmute(vld1q_lane_s32::<3>(&elem, transmute(a)));
+        let r = unsafe { i32x4::from(vld1q_lane_s32::<3>(&elem, a.into())) };
         assert_eq!(r, e)
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vld1_lane_s64() {
+    fn test_vld1_lane_s64() {
         let a = i64x1::new(0);
         let elem: i64 = 42;
         let e = i64x1::new(42);
-        let r: i64x1 = transmute(vld1_lane_s64::<0>(&elem, transmute(a)));
+        let r = unsafe { i64x1::from(vld1_lane_s64::<0>(&elem, a.into())) };
         assert_eq!(r, e)
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vld1q_lane_s64() {
+    fn test_vld1q_lane_s64() {
         let a = i64x2::new(0, 1);
         let elem: i64 = 42;
         let e = i64x2::new(0, 42);
-        let r: i64x2 = transmute(vld1q_lane_s64::<1>(&elem, transmute(a)));
+        let r = unsafe { i64x2::from(vld1q_lane_s64::<1>(&elem, a.into())) };
         assert_eq!(r, e)
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vld1_lane_u8() {
+    fn test_vld1_lane_u8() {
         let a = u8x8::new(0, 1, 2, 3, 4, 5, 6, 7);
         let elem: u8 = 42;
         let e = u8x8::new(0, 1, 2, 3, 4, 5, 6, 42);
-        let r: u8x8 = transmute(vld1_lane_u8::<7>(&elem, transmute(a)));
+        let r = unsafe { u8x8::from(vld1_lane_u8::<7>(&elem, a.into())) };
         assert_eq!(r, e)
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vld1q_lane_u8() {
+    fn test_vld1q_lane_u8() {
         let a = u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let elem: u8 = 42;
         let e = u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 42);
-        let r: u8x16 = transmute(vld1q_lane_u8::<15>(&elem, transmute(a)));
+        let r = unsafe { u8x16::from(vld1q_lane_u8::<15>(&elem, a.into())) };
         assert_eq!(r, e)
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vld1_lane_u16() {
+    fn test_vld1_lane_u16() {
         let a = u16x4::new(0, 1, 2, 3);
         let elem: u16 = 42;
         let e = u16x4::new(0, 1, 2, 42);
-        let r: u16x4 = transmute(vld1_lane_u16::<3>(&elem, transmute(a)));
+        let r = unsafe { u16x4::from(vld1_lane_u16::<3>(&elem, a.into())) };
         assert_eq!(r, e)
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vld1q_lane_u16() {
+    fn test_vld1q_lane_u16() {
         let a = u16x8::new(0, 1, 2, 3, 4, 5, 6, 7);
         let elem: u16 = 42;
         let e = u16x8::new(0, 1, 2, 3, 4, 5, 6, 42);
-        let r: u16x8 = transmute(vld1q_lane_u16::<7>(&elem, transmute(a)));
+        let r = unsafe { u16x8::from(vld1q_lane_u16::<7>(&elem, a.into())) };
         assert_eq!(r, e)
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vld1_lane_u32() {
+    fn test_vld1_lane_u32() {
         let a = u32x2::new(0, 1);
         let elem: u32 = 42;
         let e = u32x2::new(0, 42);
-        let r: u32x2 = transmute(vld1_lane_u32::<1>(&elem, transmute(a)));
+        let r = unsafe { u32x2::from(vld1_lane_u32::<1>(&elem, a.into())) };
         assert_eq!(r, e)
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vld1q_lane_u32() {
+    fn test_vld1q_lane_u32() {
         let a = u32x4::new(0, 1, 2, 3);
         let elem: u32 = 42;
         let e = u32x4::new(0, 1, 2, 42);
-        let r: u32x4 = transmute(vld1q_lane_u32::<3>(&elem, transmute(a)));
+        let r = unsafe { u32x4::from(vld1q_lane_u32::<3>(&elem, a.into())) };
         assert_eq!(r, e)
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vld1_lane_u64() {
+    fn test_vld1_lane_u64() {
         let a = u64x1::new(0);
         let elem: u64 = 42;
         let e = u64x1::new(42);
-        let r: u64x1 = transmute(vld1_lane_u64::<0>(&elem, transmute(a)));
+        let r = unsafe { u64x1::from(vld1_lane_u64::<0>(&elem, a.into())) };
         assert_eq!(r, e)
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vld1q_lane_u64() {
+    fn test_vld1q_lane_u64() {
         let a = u64x2::new(0, 1);
         let elem: u64 = 42;
         let e = u64x2::new(0, 42);
-        let r: u64x2 = transmute(vld1q_lane_u64::<1>(&elem, transmute(a)));
+        let r = unsafe { u64x2::from(vld1q_lane_u64::<1>(&elem, a.into())) };
         assert_eq!(r, e)
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vld1_lane_p8() {
+    fn test_vld1_lane_p8() {
         let a = u8x8::new(0, 1, 2, 3, 4, 5, 6, 7);
         let elem: p8 = 42;
         let e = u8x8::new(0, 1, 2, 3, 4, 5, 6, 42);
-        let r: u8x8 = transmute(vld1_lane_p8::<7>(&elem, transmute(a)));
+        let r = unsafe { u8x8::from(vld1_lane_p8::<7>(&elem, a.into())) };
         assert_eq!(r, e)
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vld1q_lane_p8() {
+    fn test_vld1q_lane_p8() {
         let a = u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let elem: p8 = 42;
         let e = u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 42);
-        let r: u8x16 = transmute(vld1q_lane_p8::<15>(&elem, transmute(a)));
+        let r = unsafe { u8x16::from(vld1q_lane_p8::<15>(&elem, a.into())) };
         assert_eq!(r, e)
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vld1_lane_p16() {
+    fn test_vld1_lane_p16() {
         let a = u16x4::new(0, 1, 2, 3);
         let elem: p16 = 42;
         let e = u16x4::new(0, 1, 2, 42);
-        let r: u16x4 = transmute(vld1_lane_p16::<3>(&elem, transmute(a)));
+        let r = unsafe { u16x4::from(vld1_lane_p16::<3>(&elem, a.into())) };
         assert_eq!(r, e)
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vld1q_lane_p16() {
+    fn test_vld1q_lane_p16() {
         let a = u16x8::new(0, 1, 2, 3, 4, 5, 6, 7);
         let elem: p16 = 42;
         let e = u16x8::new(0, 1, 2, 3, 4, 5, 6, 42);
-        let r: u16x8 = transmute(vld1q_lane_p16::<7>(&elem, transmute(a)));
+        let r = unsafe { u16x8::from(vld1q_lane_p16::<7>(&elem, a.into())) };
         assert_eq!(r, e)
     }
 
     #[simd_test(enable = "neon,aes")]
-    unsafe fn test_vld1_lane_p64() {
+    fn test_vld1_lane_p64() {
         let a = u64x1::new(0);
         let elem: u64 = 42;
         let e = u64x1::new(42);
-        let r: u64x1 = transmute(vld1_lane_p64::<0>(&elem, transmute(a)));
+        let r = unsafe { u64x1::from(vld1_lane_p64::<0>(&elem, a.into())) };
         assert_eq!(r, e)
     }
 
     #[simd_test(enable = "neon,aes")]
-    unsafe fn test_vld1q_lane_p64() {
+    fn test_vld1q_lane_p64() {
         let a = u64x2::new(0, 1);
         let elem: u64 = 42;
         let e = u64x2::new(0, 42);
-        let r: u64x2 = transmute(vld1q_lane_p64::<1>(&elem, transmute(a)));
+        let r = unsafe { u64x2::from(vld1q_lane_p64::<1>(&elem, a.into())) };
         assert_eq!(r, e)
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vld1_lane_f32() {
+    fn test_vld1_lane_f32() {
         let a = f32x2::new(0., 1.);
         let elem: f32 = 42.;
         let e = f32x2::new(0., 42.);
-        let r: f32x2 = transmute(vld1_lane_f32::<1>(&elem, transmute(a)));
+        let r = unsafe { f32x2::from(vld1_lane_f32::<1>(&elem, a.into())) };
         assert_eq!(r, e)
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vld1q_lane_f32() {
+    fn test_vld1q_lane_f32() {
         let a = f32x4::new(0., 1., 2., 3.);
         let elem: f32 = 42.;
         let e = f32x4::new(0., 1., 2., 42.);
-        let r: f32x4 = transmute(vld1q_lane_f32::<3>(&elem, transmute(a)));
+        let r = unsafe { f32x4::from(vld1q_lane_f32::<3>(&elem, a.into())) };
         assert_eq!(r, e)
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vld1_dup_s8() {
+    fn test_vld1_dup_s8() {
         let elem: i8 = 42;
         let e = i8x8::new(42, 42, 42, 42, 42, 42, 42, 42);
-        let r: i8x8 = transmute(vld1_dup_s8(&elem));
+        let r = unsafe { i8x8::from(vld1_dup_s8(&elem)) };
         assert_eq!(r, e)
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vld1q_dup_s8() {
+    fn test_vld1q_dup_s8() {
         let elem: i8 = 42;
         let e = i8x16::new(
             42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42,
         );
-        let r: i8x16 = transmute(vld1q_dup_s8(&elem));
+        let r = unsafe { i8x16::from(vld1q_dup_s8(&elem)) };
         assert_eq!(r, e)
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vld1_dup_s16() {
+    fn test_vld1_dup_s16() {
         let elem: i16 = 42;
         let e = i16x4::new(42, 42, 42, 42);
-        let r: i16x4 = transmute(vld1_dup_s16(&elem));
+        let r = unsafe { i16x4::from(vld1_dup_s16(&elem)) };
         assert_eq!(r, e)
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vld1q_dup_s16() {
+    fn test_vld1q_dup_s16() {
         let elem: i16 = 42;
         let e = i16x8::new(42, 42, 42, 42, 42, 42, 42, 42);
-        let r: i16x8 = transmute(vld1q_dup_s16(&elem));
+        let r = unsafe { i16x8::from(vld1q_dup_s16(&elem)) };
         assert_eq!(r, e)
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vld1_dup_s32() {
+    fn test_vld1_dup_s32() {
         let elem: i32 = 42;
         let e = i32x2::new(42, 42);
-        let r: i32x2 = transmute(vld1_dup_s32(&elem));
+        let r = unsafe { i32x2::from(vld1_dup_s32(&elem)) };
         assert_eq!(r, e)
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vld1q_dup_s32() {
+    fn test_vld1q_dup_s32() {
         let elem: i32 = 42;
         let e = i32x4::new(42, 42, 42, 42);
-        let r: i32x4 = transmute(vld1q_dup_s32(&elem));
+        let r = unsafe { i32x4::from(vld1q_dup_s32(&elem)) };
         assert_eq!(r, e)
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vld1_dup_s64() {
+    fn test_vld1_dup_s64() {
         let elem: i64 = 42;
         let e = i64x1::new(42);
-        let r: i64x1 = transmute(vld1_dup_s64(&elem));
+        let r = unsafe { i64x1::from(vld1_dup_s64(&elem)) };
         assert_eq!(r, e)
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vld1q_dup_s64() {
+    fn test_vld1q_dup_s64() {
         let elem: i64 = 42;
         let e = i64x2::new(42, 42);
-        let r: i64x2 = transmute(vld1q_dup_s64(&elem));
+        let r = unsafe { i64x2::from(vld1q_dup_s64(&elem)) };
         assert_eq!(r, e)
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vld1_dup_u8() {
+    fn test_vld1_dup_u8() {
         let elem: u8 = 42;
         let e = u8x8::new(42, 42, 42, 42, 42, 42, 42, 42);
-        let r: u8x8 = transmute(vld1_dup_u8(&elem));
+        let r = unsafe { u8x8::from(vld1_dup_u8(&elem)) };
         assert_eq!(r, e)
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vld1q_dup_u8() {
+    fn test_vld1q_dup_u8() {
         let elem: u8 = 42;
         let e = u8x16::new(
             42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42,
         );
-        let r: u8x16 = transmute(vld1q_dup_u8(&elem));
+        let r = unsafe { u8x16::from(vld1q_dup_u8(&elem)) };
         assert_eq!(r, e)
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vld1_dup_u16() {
+    fn test_vld1_dup_u16() {
         let elem: u16 = 42;
         let e = u16x4::new(42, 42, 42, 42);
-        let r: u16x4 = transmute(vld1_dup_u16(&elem));
+        let r = unsafe { u16x4::from(vld1_dup_u16(&elem)) };
         assert_eq!(r, e)
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vld1q_dup_u16() {
+    fn test_vld1q_dup_u16() {
         let elem: u16 = 42;
         let e = u16x8::new(42, 42, 42, 42, 42, 42, 42, 42);
-        let r: u16x8 = transmute(vld1q_dup_u16(&elem));
+        let r = unsafe { u16x8::from(vld1q_dup_u16(&elem)) };
         assert_eq!(r, e)
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vld1_dup_u32() {
+    fn test_vld1_dup_u32() {
         let elem: u32 = 42;
         let e = u32x2::new(42, 42);
-        let r: u32x2 = transmute(vld1_dup_u32(&elem));
+        let r = unsafe { u32x2::from(vld1_dup_u32(&elem)) };
         assert_eq!(r, e)
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vld1q_dup_u32() {
+    fn test_vld1q_dup_u32() {
         let elem: u32 = 42;
         let e = u32x4::new(42, 42, 42, 42);
-        let r: u32x4 = transmute(vld1q_dup_u32(&elem));
+        let r = unsafe { u32x4::from(vld1q_dup_u32(&elem)) };
         assert_eq!(r, e)
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vld1_dup_u64() {
+    fn test_vld1_dup_u64() {
         let elem: u64 = 42;
         let e = u64x1::new(42);
-        let r: u64x1 = transmute(vld1_dup_u64(&elem));
+        let r = unsafe { u64x1::from(vld1_dup_u64(&elem)) };
         assert_eq!(r, e)
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vld1q_dup_u64() {
+    fn test_vld1q_dup_u64() {
         let elem: u64 = 42;
         let e = u64x2::new(42, 42);
-        let r: u64x2 = transmute(vld1q_dup_u64(&elem));
+        let r = unsafe { u64x2::from(vld1q_dup_u64(&elem)) };
         assert_eq!(r, e)
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vld1_dup_p8() {
+    fn test_vld1_dup_p8() {
         let elem: p8 = 42;
         let e = u8x8::new(42, 42, 42, 42, 42, 42, 42, 42);
-        let r: u8x8 = transmute(vld1_dup_p8(&elem));
+        let r = unsafe { u8x8::from(vld1_dup_p8(&elem)) };
         assert_eq!(r, e)
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vld1q_dup_p8() {
+    fn test_vld1q_dup_p8() {
         let elem: p8 = 42;
         let e = u8x16::new(
             42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42,
         );
-        let r: u8x16 = transmute(vld1q_dup_p8(&elem));
+        let r = unsafe { u8x16::from(vld1q_dup_p8(&elem)) };
         assert_eq!(r, e)
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vld1_dup_p16() {
+    fn test_vld1_dup_p16() {
         let elem: p16 = 42;
         let e = u16x4::new(42, 42, 42, 42);
-        let r: u16x4 = transmute(vld1_dup_p16(&elem));
+        let r = unsafe { u16x4::from(vld1_dup_p16(&elem)) };
         assert_eq!(r, e)
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vld1q_dup_p16() {
+    fn test_vld1q_dup_p16() {
         let elem: p16 = 42;
         let e = u16x8::new(42, 42, 42, 42, 42, 42, 42, 42);
-        let r: u16x8 = transmute(vld1q_dup_p16(&elem));
+        let r = unsafe { u16x8::from(vld1q_dup_p16(&elem)) };
         assert_eq!(r, e)
     }
 
     #[simd_test(enable = "neon,aes")]
-    unsafe fn test_vld1_dup_p64() {
+    fn test_vld1_dup_p64() {
         let elem: u64 = 42;
         let e = u64x1::new(42);
-        let r: u64x1 = transmute(vld1_dup_p64(&elem));
+        let r = unsafe { u64x1::from(vld1_dup_p64(&elem)) };
         assert_eq!(r, e)
     }
 
     #[simd_test(enable = "neon,aes")]
-    unsafe fn test_vld1q_dup_p64() {
+    fn test_vld1q_dup_p64() {
         let elem: u64 = 42;
         let e = u64x2::new(42, 42);
-        let r: u64x2 = transmute(vld1q_dup_p64(&elem));
+        let r = unsafe { u64x2::from(vld1q_dup_p64(&elem)) };
         assert_eq!(r, e)
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vld1_dup_f32() {
+    fn test_vld1_dup_f32() {
         let elem: f32 = 42.;
         let e = f32x2::new(42., 42.);
-        let r: f32x2 = transmute(vld1_dup_f32(&elem));
+        let r = unsafe { f32x2::from(vld1_dup_f32(&elem)) };
         assert_eq!(r, e)
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vld1q_dup_f32() {
+    fn test_vld1q_dup_f32() {
         let elem: f32 = 42.;
         let e = f32x4::new(42., 42., 42., 42.);
-        let r: f32x4 = transmute(vld1q_dup_f32(&elem));
+        let r = unsafe { f32x4::from(vld1q_dup_f32(&elem)) };
         assert_eq!(r, e)
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vget_lane_u8() {
-        let v = i8x8::new(1, 2, 3, 4, 5, 6, 7, 8);
-        let r = vget_lane_u8::<1>(transmute(v));
+    fn test_vget_lane_u8() {
+        let v = u8x8::new(1, 2, 3, 4, 5, 6, 7, 8);
+        let r = vget_lane_u8::<1>(v.into());
         assert_eq!(r, 2);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vgetq_lane_u32() {
+    fn test_vgetq_lane_u32() {
+        let v = u32x4::new(1, 2, 3, 4);
+        let r = vgetq_lane_u32::<1>(v.into());
+        assert_eq!(r, 2);
+    }
+
+    #[simd_test(enable = "neon")]
+    fn test_vgetq_lane_s32() {
         let v = i32x4::new(1, 2, 3, 4);
-        let r = vgetq_lane_u32::<1>(transmute(v));
+        let r = vgetq_lane_s32::<1>(v.into());
         assert_eq!(r, 2);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vgetq_lane_s32() {
-        let v = i32x4::new(1, 2, 3, 4);
-        let r = vgetq_lane_s32::<1>(transmute(v));
-        assert_eq!(r, 2);
-    }
-
-    #[simd_test(enable = "neon")]
-    unsafe fn test_vget_lane_u64() {
-        let v: u64 = 1;
-        let r = vget_lane_u64::<0>(transmute(v));
-        assert_eq!(r, 1);
-    }
-
-    #[simd_test(enable = "neon")]
-    unsafe fn test_vgetq_lane_u16() {
-        let v = i16x8::new(1, 2, 3, 4, 5, 6, 7, 8);
-        let r = vgetq_lane_u16::<1>(transmute(v));
-        assert_eq!(r, 2);
-    }
-
-    #[simd_test(enable = "neon")]
-    unsafe fn test_vget_lane_s8() {
-        let v = i8x8::new(0, 1, 2, 3, 4, 5, 6, 7);
-        let r = vget_lane_s8::<2>(transmute(v));
-        assert_eq!(r, 2);
-        let r = vget_lane_s8::<4>(transmute(v));
-        assert_eq!(r, 4);
-        let r = vget_lane_s8::<5>(transmute(v));
-        assert_eq!(r, 5);
-    }
-    #[simd_test(enable = "neon")]
-    unsafe fn test_vget_lane_p8() {
-        let v = u8x8::new(0, 1, 2, 3, 4, 5, 6, 7);
-        let r = vget_lane_p8::<2>(transmute(v));
-        assert_eq!(r, 2);
-        let r = vget_lane_p8::<3>(transmute(v));
-        assert_eq!(r, 3);
-        let r = vget_lane_p8::<5>(transmute(v));
-        assert_eq!(r, 5);
-    }
-
-    #[simd_test(enable = "neon")]
-    unsafe fn test_vget_lane_p16() {
-        let v = u16x4::new(0, 1, 2, 3);
-        let r = vget_lane_p16::<2>(transmute(v));
-        assert_eq!(r, 2);
-        let r = vget_lane_p16::<3>(transmute(v));
-        assert_eq!(r, 3);
-        let r = vget_lane_p16::<0>(transmute(v));
-        assert_eq!(r, 0);
-        let r = vget_lane_p16::<1>(transmute(v));
-        assert_eq!(r, 1);
-    }
-
-    #[simd_test(enable = "neon")]
-    unsafe fn test_vget_lane_s16() {
-        let v = i16x4::new(0, 1, 2, 3);
-        let r = vget_lane_s16::<2>(transmute(v));
-        assert_eq!(r, 2);
-        let r = vget_lane_s16::<3>(transmute(v));
-        assert_eq!(r, 3);
-        let r = vget_lane_s16::<0>(transmute(v));
-        assert_eq!(r, 0);
-        let r = vget_lane_s16::<1>(transmute(v));
-        assert_eq!(r, 1);
-    }
-
-    #[simd_test(enable = "neon")]
-    unsafe fn test_vget_lane_u16() {
-        let v = u16x4::new(0, 1, 2, 3);
-        let r = vget_lane_u16::<2>(transmute(v));
-        assert_eq!(r, 2);
-        let r = vget_lane_u16::<3>(transmute(v));
-        assert_eq!(r, 3);
-        let r = vget_lane_u16::<0>(transmute(v));
-        assert_eq!(r, 0);
-        let r = vget_lane_u16::<1>(transmute(v));
-        assert_eq!(r, 1);
-    }
-    #[simd_test(enable = "neon")]
-    unsafe fn test_vget_lane_f32() {
-        let v = f32x2::new(0.0, 1.0);
-        let r = vget_lane_f32::<1>(transmute(v));
-        assert_eq!(r, 1.0);
-        let r = vget_lane_f32::<0>(transmute(v));
-        assert_eq!(r, 0.0);
-    }
-
-    #[simd_test(enable = "neon")]
-    unsafe fn test_vget_lane_s32() {
-        let v = i32x2::new(0, 1);
-        let r = vget_lane_s32::<1>(transmute(v));
-        assert_eq!(r, 1);
-        let r = vget_lane_s32::<0>(transmute(v));
-        assert_eq!(r, 0);
-    }
-
-    #[simd_test(enable = "neon")]
-    unsafe fn test_vget_lane_u32() {
-        let v = u32x2::new(0, 1);
-        let r = vget_lane_u32::<1>(transmute(v));
-        assert_eq!(r, 1);
-        let r = vget_lane_u32::<0>(transmute(v));
-        assert_eq!(r, 0);
-    }
-
-    #[simd_test(enable = "neon")]
-    unsafe fn test_vget_lane_s64() {
-        let v = i64x1::new(1);
-        let r = vget_lane_s64::<0>(transmute(v));
-        assert_eq!(r, 1);
-    }
-
-    #[simd_test(enable = "neon")]
-    unsafe fn test_vget_lane_p64() {
+    fn test_vget_lane_u64() {
         let v = u64x1::new(1);
-        let r = vget_lane_p64::<0>(transmute(v));
+        let r = vget_lane_u64::<0>(v.into());
         assert_eq!(r, 1);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vgetq_lane_s8() {
-        let v = i8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
-        let r = vgetq_lane_s8::<7>(transmute(v));
-        assert_eq!(r, 7);
-        let r = vgetq_lane_s8::<13>(transmute(v));
-        assert_eq!(r, 13);
-        let r = vgetq_lane_s8::<3>(transmute(v));
-        assert_eq!(r, 3);
-        let r = vgetq_lane_s8::<0>(transmute(v));
-        assert_eq!(r, 0);
+    fn test_vgetq_lane_u16() {
+        let v = u16x8::new(1, 2, 3, 4, 5, 6, 7, 8);
+        let r = vgetq_lane_u16::<1>(v.into());
+        assert_eq!(r, 2);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vgetq_lane_p8() {
-        let v = u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
-        let r = vgetq_lane_p8::<7>(transmute(v));
-        assert_eq!(r, 7);
-        let r = vgetq_lane_p8::<13>(transmute(v));
-        assert_eq!(r, 13);
-        let r = vgetq_lane_p8::<3>(transmute(v));
-        assert_eq!(r, 3);
-        let r = vgetq_lane_p8::<0>(transmute(v));
-        assert_eq!(r, 0);
+    fn test_vget_lane_s8() {
+        let v = i8x8::new(0, 1, 2, 3, 4, 5, 6, 7);
+        let r = vget_lane_s8::<2>(v.into());
+        assert_eq!(r, 2);
+        let r = vget_lane_s8::<4>(v.into());
+        assert_eq!(r, 4);
+        let r = vget_lane_s8::<5>(v.into());
+        assert_eq!(r, 5);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vgetq_lane_u8() {
-        let v = u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
-        let r = vgetq_lane_u8::<7>(transmute(v));
-        assert_eq!(r, 7);
-        let r = vgetq_lane_u8::<13>(transmute(v));
-        assert_eq!(r, 13);
-        let r = vgetq_lane_u8::<3>(transmute(v));
+    fn test_vget_lane_p8() {
+        let v = u8x8::new(0, 1, 2, 3, 4, 5, 6, 7);
+        let r = vget_lane_p8::<2>(v.into());
+        assert_eq!(r, 2);
+        let r = vget_lane_p8::<3>(v.into());
         assert_eq!(r, 3);
-        let r = vgetq_lane_u8::<0>(transmute(v));
-        assert_eq!(r, 0);
+        let r = vget_lane_p8::<5>(v.into());
+        assert_eq!(r, 5);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vgetq_lane_s16() {
-        let v = i16x8::new(0, 1, 2, 3, 4, 5, 6, 7);
-        let r = vgetq_lane_s16::<3>(transmute(v));
+    fn test_vget_lane_p16() {
+        let v = u16x4::new(0, 1, 2, 3);
+        let r = vget_lane_p16::<2>(v.into());
+        assert_eq!(r, 2);
+        let r = vget_lane_p16::<3>(v.into());
         assert_eq!(r, 3);
-        let r = vgetq_lane_s16::<6>(transmute(v));
-        assert_eq!(r, 6);
-        let r = vgetq_lane_s16::<0>(transmute(v));
+        let r = vget_lane_p16::<0>(v.into());
         assert_eq!(r, 0);
-    }
-
-    #[simd_test(enable = "neon")]
-    unsafe fn test_vgetq_lane_p16() {
-        let v = u16x8::new(0, 1, 2, 3, 4, 5, 6, 7);
-        let r = vgetq_lane_p16::<3>(transmute(v));
-        assert_eq!(r, 3);
-        let r = vgetq_lane_p16::<7>(transmute(v));
-        assert_eq!(r, 7);
-        let r = vgetq_lane_p16::<1>(transmute(v));
+        let r = vget_lane_p16::<1>(v.into());
         assert_eq!(r, 1);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vgetq_lane_f32() {
-        let v = f32x4::new(0.0, 1.0, 2.0, 3.0);
-        let r = vgetq_lane_f32::<3>(transmute(v));
-        assert_eq!(r, 3.0);
-        let r = vgetq_lane_f32::<0>(transmute(v));
+    fn test_vget_lane_s16() {
+        let v = i16x4::new(0, 1, 2, 3);
+        let r = vget_lane_s16::<2>(v.into());
+        assert_eq!(r, 2);
+        let r = vget_lane_s16::<3>(v.into());
+        assert_eq!(r, 3);
+        let r = vget_lane_s16::<0>(v.into());
+        assert_eq!(r, 0);
+        let r = vget_lane_s16::<1>(v.into());
+        assert_eq!(r, 1);
+    }
+
+    #[simd_test(enable = "neon")]
+    fn test_vget_lane_u16() {
+        let v = u16x4::new(0, 1, 2, 3);
+        let r = vget_lane_u16::<2>(v.into());
+        assert_eq!(r, 2);
+        let r = vget_lane_u16::<3>(v.into());
+        assert_eq!(r, 3);
+        let r = vget_lane_u16::<0>(v.into());
+        assert_eq!(r, 0);
+        let r = vget_lane_u16::<1>(v.into());
+        assert_eq!(r, 1);
+    }
+
+    #[simd_test(enable = "neon")]
+    fn test_vget_lane_f32() {
+        let v = f32x2::new(0.0, 1.0);
+        let r = vget_lane_f32::<1>(v.into());
+        assert_eq!(r, 1.0);
+        let r = vget_lane_f32::<0>(v.into());
         assert_eq!(r, 0.0);
-        let r = vgetq_lane_f32::<2>(transmute(v));
+    }
+
+    #[simd_test(enable = "neon")]
+    fn test_vget_lane_s32() {
+        let v = i32x2::new(0, 1);
+        let r = vget_lane_s32::<1>(v.into());
+        assert_eq!(r, 1);
+        let r = vget_lane_s32::<0>(v.into());
+        assert_eq!(r, 0);
+    }
+
+    #[simd_test(enable = "neon")]
+    fn test_vget_lane_u32() {
+        let v = u32x2::new(0, 1);
+        let r = vget_lane_u32::<1>(v.into());
+        assert_eq!(r, 1);
+        let r = vget_lane_u32::<0>(v.into());
+        assert_eq!(r, 0);
+    }
+
+    #[simd_test(enable = "neon")]
+    fn test_vget_lane_s64() {
+        let v = i64x1::new(1);
+        let r = vget_lane_s64::<0>(v.into());
+        assert_eq!(r, 1);
+    }
+
+    #[simd_test(enable = "neon")]
+    fn test_vget_lane_p64() {
+        let v = u64x1::new(1);
+        let r = vget_lane_p64::<0>(v.into());
+        assert_eq!(r, 1);
+    }
+
+    #[simd_test(enable = "neon")]
+    fn test_vgetq_lane_s8() {
+        let v = i8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
+        let r = vgetq_lane_s8::<7>(v.into());
+        assert_eq!(r, 7);
+        let r = vgetq_lane_s8::<13>(v.into());
+        assert_eq!(r, 13);
+        let r = vgetq_lane_s8::<3>(v.into());
+        assert_eq!(r, 3);
+        let r = vgetq_lane_s8::<0>(v.into());
+        assert_eq!(r, 0);
+    }
+
+    #[simd_test(enable = "neon")]
+    fn test_vgetq_lane_p8() {
+        let v = u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
+        let r = vgetq_lane_p8::<7>(v.into());
+        assert_eq!(r, 7);
+        let r = vgetq_lane_p8::<13>(v.into());
+        assert_eq!(r, 13);
+        let r = vgetq_lane_p8::<3>(v.into());
+        assert_eq!(r, 3);
+        let r = vgetq_lane_p8::<0>(v.into());
+        assert_eq!(r, 0);
+    }
+
+    #[simd_test(enable = "neon")]
+    fn test_vgetq_lane_u8() {
+        let v = u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
+        let r = vgetq_lane_u8::<7>(v.into());
+        assert_eq!(r, 7);
+        let r = vgetq_lane_u8::<13>(v.into());
+        assert_eq!(r, 13);
+        let r = vgetq_lane_u8::<3>(v.into());
+        assert_eq!(r, 3);
+        let r = vgetq_lane_u8::<0>(v.into());
+        assert_eq!(r, 0);
+    }
+
+    #[simd_test(enable = "neon")]
+    fn test_vgetq_lane_s16() {
+        let v = i16x8::new(0, 1, 2, 3, 4, 5, 6, 7);
+        let r = vgetq_lane_s16::<3>(v.into());
+        assert_eq!(r, 3);
+        let r = vgetq_lane_s16::<6>(v.into());
+        assert_eq!(r, 6);
+        let r = vgetq_lane_s16::<0>(v.into());
+        assert_eq!(r, 0);
+    }
+
+    #[simd_test(enable = "neon")]
+    fn test_vgetq_lane_p16() {
+        let v = u16x8::new(0, 1, 2, 3, 4, 5, 6, 7);
+        let r = vgetq_lane_p16::<3>(v.into());
+        assert_eq!(r, 3);
+        let r = vgetq_lane_p16::<7>(v.into());
+        assert_eq!(r, 7);
+        let r = vgetq_lane_p16::<1>(v.into());
+        assert_eq!(r, 1);
+    }
+
+    #[simd_test(enable = "neon")]
+    fn test_vgetq_lane_f32() {
+        let v = f32x4::new(0.0, 1.0, 2.0, 3.0);
+        let r = vgetq_lane_f32::<3>(v.into());
+        assert_eq!(r, 3.0);
+        let r = vgetq_lane_f32::<0>(v.into());
+        assert_eq!(r, 0.0);
+        let r = vgetq_lane_f32::<2>(v.into());
         assert_eq!(r, 2.0);
-        let r = vgetq_lane_f32::<1>(transmute(v));
+        let r = vgetq_lane_f32::<1>(v.into());
         assert_eq!(r, 1.0);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vgetq_lane_s64() {
+    fn test_vgetq_lane_s64() {
         let v = i64x2::new(0, 1);
-        let r = vgetq_lane_s64::<1>(transmute(v));
+        let r = vgetq_lane_s64::<1>(v.into());
         assert_eq!(r, 1);
-        let r = vgetq_lane_s64::<0>(transmute(v));
+        let r = vgetq_lane_s64::<0>(v.into());
         assert_eq!(r, 0);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vgetq_lane_p64() {
+    fn test_vgetq_lane_p64() {
         let v = u64x2::new(0, 1);
-        let r = vgetq_lane_p64::<1>(transmute(v));
+        let r = vgetq_lane_p64::<1>(v.into());
         assert_eq!(r, 1);
-        let r = vgetq_lane_p64::<0>(transmute(v));
+        let r = vgetq_lane_p64::<0>(v.into());
         assert_eq!(r, 0);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vext_s64() {
+    fn test_vext_s64() {
         let a: i64x1 = i64x1::new(0);
         let b: i64x1 = i64x1::new(1);
         let e: i64x1 = i64x1::new(0);
-        let r: i64x1 = transmute(vext_s64::<0>(transmute(a), transmute(b)));
+        let r = unsafe { i64x1::from(vext_s64::<0>(a.into(), b.into())) };
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vext_u64() {
+    fn test_vext_u64() {
         let a: u64x1 = u64x1::new(0);
         let b: u64x1 = u64x1::new(1);
         let e: u64x1 = u64x1::new(0);
-        let r: u64x1 = transmute(vext_u64::<0>(transmute(a), transmute(b)));
+        let r = unsafe { u64x1::from(vext_u64::<0>(a.into(), b.into())) };
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vget_high_s8() {
+    fn test_vget_high_s8() {
         let a = i8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let e = i8x8::new(9, 10, 11, 12, 13, 14, 15, 16);
-        let r: i8x8 = transmute(vget_high_s8(transmute(a)));
+        let r = i8x8::from(vget_high_s8(a.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vget_high_s16() {
+    fn test_vget_high_s16() {
         let a = i16x8::new(1, 2, 3, 4, 5, 6, 7, 8);
         let e = i16x4::new(5, 6, 7, 8);
-        let r: i16x4 = transmute(vget_high_s16(transmute(a)));
+        let r = i16x4::from(vget_high_s16(a.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vget_high_s32() {
+    fn test_vget_high_s32() {
         let a = i32x4::new(1, 2, 3, 4);
         let e = i32x2::new(3, 4);
-        let r: i32x2 = transmute(vget_high_s32(transmute(a)));
+        let r = i32x2::from(vget_high_s32(a.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vget_high_s64() {
+    fn test_vget_high_s64() {
         let a = i64x2::new(1, 2);
         let e = i64x1::new(2);
-        let r: i64x1 = transmute(vget_high_s64(transmute(a)));
+        let r = i64x1::from(vget_high_s64(a.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vget_high_u8() {
+    fn test_vget_high_u8() {
         let a = u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let e = u8x8::new(9, 10, 11, 12, 13, 14, 15, 16);
-        let r: u8x8 = transmute(vget_high_u8(transmute(a)));
+        let r = u8x8::from(vget_high_u8(a.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vget_high_u16() {
+    fn test_vget_high_u16() {
         let a = u16x8::new(1, 2, 3, 4, 5, 6, 7, 8);
         let e = u16x4::new(5, 6, 7, 8);
-        let r: u16x4 = transmute(vget_high_u16(transmute(a)));
+        let r = u16x4::from(vget_high_u16(a.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vget_high_u32() {
+    fn test_vget_high_u32() {
         let a = u32x4::new(1, 2, 3, 4);
         let e = u32x2::new(3, 4);
-        let r: u32x2 = transmute(vget_high_u32(transmute(a)));
+        let r = u32x2::from(vget_high_u32(a.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vget_high_u64() {
+    fn test_vget_high_u64() {
         let a = u64x2::new(1, 2);
         let e = u64x1::new(2);
-        let r: u64x1 = transmute(vget_high_u64(transmute(a)));
+        let r = u64x1::from(vget_high_u64(a.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vget_high_p8() {
+    fn test_vget_high_p8() {
         let a = u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let e = u8x8::new(9, 10, 11, 12, 13, 14, 15, 16);
-        let r: u8x8 = transmute(vget_high_p8(transmute(a)));
+        let r = u8x8::from(vget_high_p8(a.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vget_high_p16() {
+    fn test_vget_high_p16() {
         let a = u16x8::new(1, 2, 3, 4, 5, 6, 7, 8);
         let e = u16x4::new(5, 6, 7, 8);
-        let r: u16x4 = transmute(vget_high_p16(transmute(a)));
+        let r = u16x4::from(vget_high_p16(a.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vget_high_f32() {
+    fn test_vget_high_f32() {
         let a = f32x4::new(1.0, 2.0, 3.0, 4.0);
         let e = f32x2::new(3.0, 4.0);
-        let r: f32x2 = transmute(vget_high_f32(transmute(a)));
+        let r = f32x2::from(vget_high_f32(a.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vget_low_s8() {
+    fn test_vget_low_s8() {
         let a = i8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let e = i8x8::new(1, 2, 3, 4, 5, 6, 7, 8);
-        let r: i8x8 = transmute(vget_low_s8(transmute(a)));
+        let r = i8x8::from(vget_low_s8(a.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vget_low_s16() {
+    fn test_vget_low_s16() {
         let a = i16x8::new(1, 2, 3, 4, 5, 6, 7, 8);
         let e = i16x4::new(1, 2, 3, 4);
-        let r: i16x4 = transmute(vget_low_s16(transmute(a)));
+        let r = i16x4::from(vget_low_s16(a.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vget_low_s32() {
+    fn test_vget_low_s32() {
         let a = i32x4::new(1, 2, 3, 4);
         let e = i32x2::new(1, 2);
-        let r: i32x2 = transmute(vget_low_s32(transmute(a)));
+        let r = i32x2::from(vget_low_s32(a.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vget_low_s64() {
+    fn test_vget_low_s64() {
         let a = i64x2::new(1, 2);
         let e = i64x1::new(1);
-        let r: i64x1 = transmute(vget_low_s64(transmute(a)));
+        let r = i64x1::from(vget_low_s64(a.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vget_low_u8() {
+    fn test_vget_low_u8() {
         let a = u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let e = u8x8::new(1, 2, 3, 4, 5, 6, 7, 8);
-        let r: u8x8 = transmute(vget_low_u8(transmute(a)));
+        let r = u8x8::from(vget_low_u8(a.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vget_low_u16() {
+    fn test_vget_low_u16() {
         let a = u16x8::new(1, 2, 3, 4, 5, 6, 7, 8);
         let e = u16x4::new(1, 2, 3, 4);
-        let r: u16x4 = transmute(vget_low_u16(transmute(a)));
+        let r = u16x4::from(vget_low_u16(a.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vget_low_u32() {
+    fn test_vget_low_u32() {
         let a = u32x4::new(1, 2, 3, 4);
         let e = u32x2::new(1, 2);
-        let r: u32x2 = transmute(vget_low_u32(transmute(a)));
+        let r = u32x2::from(vget_low_u32(a.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vget_low_u64() {
+    fn test_vget_low_u64() {
         let a = u64x2::new(1, 2);
         let e = u64x1::new(1);
-        let r: u64x1 = transmute(vget_low_u64(transmute(a)));
+        let r = u64x1::from(vget_low_u64(a.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vget_low_p8() {
+    fn test_vget_low_p8() {
         let a = u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let e = u8x8::new(1, 2, 3, 4, 5, 6, 7, 8);
-        let r: u8x8 = transmute(vget_low_p8(transmute(a)));
+        let r = u8x8::from(vget_low_p8(a.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vget_low_p16() {
+    fn test_vget_low_p16() {
         let a = u16x8::new(1, 2, 3, 4, 5, 6, 7, 8);
         let e = u16x4::new(1, 2, 3, 4);
-        let r: u16x4 = transmute(vget_low_p16(transmute(a)));
+        let r = u16x4::from(vget_low_p16(a.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vget_low_f32() {
+    fn test_vget_low_f32() {
         let a = f32x4::new(1.0, 2.0, 3.0, 4.0);
         let e = f32x2::new(1.0, 2.0);
-        let r: f32x2 = transmute(vget_low_f32(transmute(a)));
+        let r = f32x2::from(vget_low_f32(a.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vdupq_n_s8() {
+    fn test_vdupq_n_s8() {
         let v: i8 = 42;
         let e = i8x16::new(
             42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42,
         );
-        let r: i8x16 = transmute(vdupq_n_s8(v));
+        let r = i8x16::from(vdupq_n_s8(v));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vdupq_n_s16() {
+    fn test_vdupq_n_s16() {
         let v: i16 = 64;
         let e = i16x8::new(64, 64, 64, 64, 64, 64, 64, 64);
-        let r: i16x8 = transmute(vdupq_n_s16(v));
+        let r = i16x8::from(vdupq_n_s16(v));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vdupq_n_s32() {
+    fn test_vdupq_n_s32() {
         let v: i32 = 64;
         let e = i32x4::new(64, 64, 64, 64);
-        let r: i32x4 = transmute(vdupq_n_s32(v));
+        let r = i32x4::from(vdupq_n_s32(v));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vdupq_n_s64() {
+    fn test_vdupq_n_s64() {
         let v: i64 = 64;
         let e = i64x2::new(64, 64);
-        let r: i64x2 = transmute(vdupq_n_s64(v));
+        let r = i64x2::from(vdupq_n_s64(v));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vdupq_n_u8() {
+    fn test_vdupq_n_u8() {
         let v: u8 = 64;
         let e = u8x16::new(
             64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64,
         );
-        let r: u8x16 = transmute(vdupq_n_u8(v));
+        let r = u8x16::from(vdupq_n_u8(v));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vdupq_n_u16() {
+    fn test_vdupq_n_u16() {
         let v: u16 = 64;
         let e = u16x8::new(64, 64, 64, 64, 64, 64, 64, 64);
-        let r: u16x8 = transmute(vdupq_n_u16(v));
+        let r = u16x8::from(vdupq_n_u16(v));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vdupq_n_u32() {
+    fn test_vdupq_n_u32() {
         let v: u32 = 64;
         let e = u32x4::new(64, 64, 64, 64);
-        let r: u32x4 = transmute(vdupq_n_u32(v));
+        let r = u32x4::from(vdupq_n_u32(v));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vdupq_n_u64() {
+    fn test_vdupq_n_u64() {
         let v: u64 = 64;
         let e = u64x2::new(64, 64);
-        let r: u64x2 = transmute(vdupq_n_u64(v));
+        let r = u64x2::from(vdupq_n_u64(v));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vdupq_n_p8() {
+    fn test_vdupq_n_p8() {
         let v: p8 = 64;
         let e = u8x16::new(
             64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64,
         );
-        let r: u8x16 = transmute(vdupq_n_p8(v));
+        let r = u8x16::from(vdupq_n_p8(v));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vdupq_n_p16() {
+    fn test_vdupq_n_p16() {
         let v: p16 = 64;
         let e = u16x8::new(64, 64, 64, 64, 64, 64, 64, 64);
-        let r: u16x8 = transmute(vdupq_n_p16(v));
+        let r = u16x8::from(vdupq_n_p16(v));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vdupq_n_f32() {
+    fn test_vdupq_n_f32() {
         let v: f32 = 64.0;
         let e = f32x4::new(64.0, 64.0, 64.0, 64.0);
-        let r: f32x4 = transmute(vdupq_n_f32(v));
+        let r = f32x4::from(vdupq_n_f32(v));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vdup_n_s8() {
+    fn test_vdup_n_s8() {
         let v: i8 = 64;
         let e = i8x8::new(64, 64, 64, 64, 64, 64, 64, 64);
-        let r: i8x8 = transmute(vdup_n_s8(v));
+        let r = i8x8::from(vdup_n_s8(v));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vdup_n_s16() {
+    fn test_vdup_n_s16() {
         let v: i16 = 64;
         let e = i16x4::new(64, 64, 64, 64);
-        let r: i16x4 = transmute(vdup_n_s16(v));
+        let r = i16x4::from(vdup_n_s16(v));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vdup_n_s32() {
+    fn test_vdup_n_s32() {
         let v: i32 = 64;
         let e = i32x2::new(64, 64);
-        let r: i32x2 = transmute(vdup_n_s32(v));
+        let r = i32x2::from(vdup_n_s32(v));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vdup_n_s64() {
+    fn test_vdup_n_s64() {
         let v: i64 = 64;
         let e = i64x1::new(64);
-        let r: i64x1 = transmute(vdup_n_s64(v));
+        let r = i64x1::from(vdup_n_s64(v));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vdup_n_u8() {
+    fn test_vdup_n_u8() {
         let v: u8 = 64;
         let e = u8x8::new(64, 64, 64, 64, 64, 64, 64, 64);
-        let r: u8x8 = transmute(vdup_n_u8(v));
+        let r = u8x8::from(vdup_n_u8(v));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vdup_n_u16() {
+    fn test_vdup_n_u16() {
         let v: u16 = 64;
         let e = u16x4::new(64, 64, 64, 64);
-        let r: u16x4 = transmute(vdup_n_u16(v));
+        let r = u16x4::from(vdup_n_u16(v));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vdup_n_u32() {
+    fn test_vdup_n_u32() {
         let v: u32 = 64;
         let e = u32x2::new(64, 64);
-        let r: u32x2 = transmute(vdup_n_u32(v));
+        let r = u32x2::from(vdup_n_u32(v));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vdup_n_u64() {
+    fn test_vdup_n_u64() {
         let v: u64 = 64;
         let e = u64x1::new(64);
-        let r: u64x1 = transmute(vdup_n_u64(v));
+        let r = u64x1::from(vdup_n_u64(v));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vdup_n_p8() {
+    fn test_vdup_n_p8() {
         let v: p8 = 64;
         let e = u8x8::new(64, 64, 64, 64, 64, 64, 64, 64);
-        let r: u8x8 = transmute(vdup_n_p8(v));
+        let r = u8x8::from(vdup_n_p8(v));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vdup_n_p16() {
+    fn test_vdup_n_p16() {
         let v: p16 = 64;
         let e = u16x4::new(64, 64, 64, 64);
-        let r: u16x4 = transmute(vdup_n_p16(v));
+        let r = u16x4::from(vdup_n_p16(v));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vdup_n_f32() {
+    fn test_vdup_n_f32() {
         let v: f32 = 64.0;
         let e = f32x2::new(64.0, 64.0);
-        let r: f32x2 = transmute(vdup_n_f32(v));
+        let r = f32x2::from(vdup_n_f32(v));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vldrq_p128() {
+    fn test_vldrq_p128() {
         let v: [p128; 2] = [1, 2];
         let e: p128 = 2;
-        let r: p128 = vldrq_p128(v[1..].as_ptr());
+        let r: p128 = unsafe { vldrq_p128(v[1..].as_ptr()) };
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vstrq_p128() {
+    fn test_vstrq_p128() {
         let v: [p128; 2] = [1, 2];
         let e: p128 = 2;
         let mut r: p128 = 1;
-        vstrq_p128(&mut r, v[1]);
+        unsafe {
+            vstrq_p128(&mut r, v[1]);
+        }
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmov_n_s8() {
+    fn test_vmov_n_s8() {
         let v: i8 = 64;
         let e = i8x8::new(64, 64, 64, 64, 64, 64, 64, 64);
-        let r: i8x8 = transmute(vmov_n_s8(v));
+        let r = i8x8::from(vmov_n_s8(v));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmov_n_s16() {
+    fn test_vmov_n_s16() {
         let v: i16 = 64;
         let e = i16x4::new(64, 64, 64, 64);
-        let r: i16x4 = transmute(vmov_n_s16(v));
+        let r = i16x4::from(vmov_n_s16(v));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmov_n_s32() {
+    fn test_vmov_n_s32() {
         let v: i32 = 64;
         let e = i32x2::new(64, 64);
-        let r: i32x2 = transmute(vmov_n_s32(v));
+        let r = i32x2::from(vmov_n_s32(v));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmov_n_s64() {
+    fn test_vmov_n_s64() {
         let v: i64 = 64;
         let e = i64x1::new(64);
-        let r: i64x1 = transmute(vmov_n_s64(v));
+        let r = i64x1::from(vmov_n_s64(v));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmov_n_u8() {
+    fn test_vmov_n_u8() {
         let v: u8 = 64;
         let e = u8x8::new(64, 64, 64, 64, 64, 64, 64, 64);
-        let r: u8x8 = transmute(vmov_n_u8(v));
+        let r = u8x8::from(vmov_n_u8(v));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmov_n_u16() {
+    fn test_vmov_n_u16() {
         let v: u16 = 64;
         let e = u16x4::new(64, 64, 64, 64);
-        let r: u16x4 = transmute(vmov_n_u16(v));
+        let r = u16x4::from(vmov_n_u16(v));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmov_n_u32() {
+    fn test_vmov_n_u32() {
         let v: u32 = 64;
         let e = u32x2::new(64, 64);
-        let r: u32x2 = transmute(vmov_n_u32(v));
+        let r = u32x2::from(vmov_n_u32(v));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmov_n_u64() {
+    fn test_vmov_n_u64() {
         let v: u64 = 64;
         let e = u64x1::new(64);
-        let r: u64x1 = transmute(vmov_n_u64(v));
+        let r = u64x1::from(vmov_n_u64(v));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmov_n_p8() {
+    fn test_vmov_n_p8() {
         let v: p8 = 64;
         let e = u8x8::new(64, 64, 64, 64, 64, 64, 64, 64);
-        let r: u8x8 = transmute(vmov_n_p8(v));
+        let r = u8x8::from(vmov_n_p8(v));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmov_n_p16() {
+    fn test_vmov_n_p16() {
         let v: p16 = 64;
         let e = u16x4::new(64, 64, 64, 64);
-        let r: u16x4 = transmute(vmov_n_p16(v));
+        let r = u16x4::from(vmov_n_p16(v));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmov_n_f32() {
+    fn test_vmov_n_f32() {
         let v: f32 = 64.0;
         let e = f32x2::new(64.0, 64.0);
-        let r: f32x2 = transmute(vmov_n_f32(v));
+        let r = f32x2::from(vmov_n_f32(v));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmovq_n_s8() {
+    fn test_vmovq_n_s8() {
         let v: i8 = 64;
         let e = i8x16::new(
             64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64,
         );
-        let r: i8x16 = transmute(vmovq_n_s8(v));
+        let r = i8x16::from(vmovq_n_s8(v));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmovq_n_s16() {
+    fn test_vmovq_n_s16() {
         let v: i16 = 64;
         let e = i16x8::new(64, 64, 64, 64, 64, 64, 64, 64);
-        let r: i16x8 = transmute(vmovq_n_s16(v));
+        let r = i16x8::from(vmovq_n_s16(v));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmovq_n_s32() {
+    fn test_vmovq_n_s32() {
         let v: i32 = 64;
         let e = i32x4::new(64, 64, 64, 64);
-        let r: i32x4 = transmute(vmovq_n_s32(v));
+        let r = i32x4::from(vmovq_n_s32(v));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmovq_n_s64() {
+    fn test_vmovq_n_s64() {
         let v: i64 = 64;
         let e = i64x2::new(64, 64);
-        let r: i64x2 = transmute(vmovq_n_s64(v));
+        let r = i64x2::from(vmovq_n_s64(v));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmovq_n_u8() {
+    fn test_vmovq_n_u8() {
         let v: u8 = 64;
         let e = u8x16::new(
             64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64,
         );
-        let r: u8x16 = transmute(vmovq_n_u8(v));
+        let r = u8x16::from(vmovq_n_u8(v));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmovq_n_u16() {
+    fn test_vmovq_n_u16() {
         let v: u16 = 64;
         let e = u16x8::new(64, 64, 64, 64, 64, 64, 64, 64);
-        let r: u16x8 = transmute(vmovq_n_u16(v));
+        let r = u16x8::from(vmovq_n_u16(v));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmovq_n_u32() {
+    fn test_vmovq_n_u32() {
         let v: u32 = 64;
         let e = u32x4::new(64, 64, 64, 64);
-        let r: u32x4 = transmute(vmovq_n_u32(v));
+        let r = u32x4::from(vmovq_n_u32(v));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmovq_n_u64() {
+    fn test_vmovq_n_u64() {
         let v: u64 = 64;
         let e = u64x2::new(64, 64);
-        let r: u64x2 = transmute(vmovq_n_u64(v));
+        let r = u64x2::from(vmovq_n_u64(v));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmovq_n_p8() {
+    fn test_vmovq_n_p8() {
         let v: p8 = 64;
         let e = u8x16::new(
             64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64,
         );
-        let r: u8x16 = transmute(vmovq_n_p8(v));
+        let r = u8x16::from(vmovq_n_p8(v));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmovq_n_p16() {
+    fn test_vmovq_n_p16() {
         let v: p16 = 64;
         let e = u16x8::new(64, 64, 64, 64, 64, 64, 64, 64);
-        let r: u16x8 = transmute(vmovq_n_p16(v));
+        let r = u16x8::from(vmovq_n_p16(v));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmovq_n_f32() {
+    fn test_vmovq_n_f32() {
         let v: f32 = 64.0;
         let e = f32x4::new(64.0, 64.0, 64.0, 64.0);
-        let r: f32x4 = transmute(vmovq_n_f32(v));
+        let r = f32x4::from(vmovq_n_f32(v));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vgetq_lane_u64() {
-        let v = i64x2::new(1, 2);
-        let r = vgetq_lane_u64::<1>(transmute(v));
+    fn test_vgetq_lane_u64() {
+        let v = u64x2::new(1, 2);
+        let r = vgetq_lane_u64::<1>(v.into());
         assert_eq!(r, 2);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vadd_s8() {
+    fn test_vadd_s8() {
         test_ari_s8(
             |i, j| vadd_s8(i, j),
             |a: i8, b: i8| -> i8 { a.overflowing_add(b).0 },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vaddq_s8() {
+    fn test_vaddq_s8() {
         testq_ari_s8(
             |i, j| vaddq_s8(i, j),
             |a: i8, b: i8| -> i8 { a.overflowing_add(b).0 },
         );
     }
     #[simd_test(enable = "neon")]
-    unsafe fn test_vadd_s16() {
+    fn test_vadd_s16() {
         test_ari_s16(
             |i, j| vadd_s16(i, j),
             |a: i16, b: i16| -> i16 { a.overflowing_add(b).0 },
         );
     }
     #[simd_test(enable = "neon")]
-    unsafe fn test_vaddq_s16() {
+    fn test_vaddq_s16() {
         testq_ari_s16(
             |i, j| vaddq_s16(i, j),
             |a: i16, b: i16| -> i16 { a.overflowing_add(b).0 },
         );
     }
     #[simd_test(enable = "neon")]
-    unsafe fn test_vadd_s32() {
+    fn test_vadd_s32() {
         test_ari_s32(
             |i, j| vadd_s32(i, j),
             |a: i32, b: i32| -> i32 { a.overflowing_add(b).0 },
         );
     }
     #[simd_test(enable = "neon")]
-    unsafe fn test_vaddq_s32() {
+    fn test_vaddq_s32() {
         testq_ari_s32(
             |i, j| vaddq_s32(i, j),
             |a: i32, b: i32| -> i32 { a.overflowing_add(b).0 },
@@ -2516,42 +2521,47 @@ mod tests {
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vadd_u8() {
+    fn test_vadd_u8() {
         test_ari_u8(
             |i, j| vadd_u8(i, j),
             |a: u8, b: u8| -> u8 { a.overflowing_add(b).0 },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vaddq_u8() {
+    fn test_vaddq_u8() {
         testq_ari_u8(
             |i, j| vaddq_u8(i, j),
             |a: u8, b: u8| -> u8 { a.overflowing_add(b).0 },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vadd_u16() {
+    fn test_vadd_u16() {
         test_ari_u16(
             |i, j| vadd_u16(i, j),
             |a: u16, b: u16| -> u16 { a.overflowing_add(b).0 },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vaddq_u16() {
+    fn test_vaddq_u16() {
         testq_ari_u16(
             |i, j| vaddq_u16(i, j),
             |a: u16, b: u16| -> u16 { a.overflowing_add(b).0 },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vadd_u32() {
+    fn test_vadd_u32() {
         test_ari_u32(
             |i, j| vadd_u32(i, j),
             |a: u32, b: u32| -> u32 { a.overflowing_add(b).0 },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vaddq_u32() {
+    fn test_vaddq_u32() {
         testq_ari_u32(
             |i, j| vaddq_u32(i, j),
             |a: u32, b: u32| -> u32 { a.overflowing_add(b).0 },
@@ -2559,142 +2569,143 @@ mod tests {
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vadd_f32() {
+    fn test_vadd_f32() {
         test_ari_f32(|i, j| vadd_f32(i, j), |a: f32, b: f32| -> f32 { a + b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vaddq_f32() {
+    fn test_vaddq_f32() {
         testq_ari_f32(|i, j| vaddq_f32(i, j), |a: f32, b: f32| -> f32 { a + b });
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vaddl_s8() {
+    fn test_vaddl_s8() {
         let v = i8::MAX;
         let a = i8x8::new(v, v, v, v, v, v, v, v);
         let v = 2 * (v as i16);
         let e = i16x8::new(v, v, v, v, v, v, v, v);
-        let r: i16x8 = transmute(vaddl_s8(transmute(a), transmute(a)));
+        let r = i16x8::from(vaddl_s8(a.into(), a.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vaddl_s16() {
+    fn test_vaddl_s16() {
         let v = i16::MAX;
         let a = i16x4::new(v, v, v, v);
         let v = 2 * (v as i32);
         let e = i32x4::new(v, v, v, v);
-        let r: i32x4 = transmute(vaddl_s16(transmute(a), transmute(a)));
+        let r = i32x4::from(vaddl_s16(a.into(), a.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vaddl_s32() {
+    fn test_vaddl_s32() {
         let v = i32::MAX;
         let a = i32x2::new(v, v);
         let v = 2 * (v as i64);
         let e = i64x2::new(v, v);
-        let r: i64x2 = transmute(vaddl_s32(transmute(a), transmute(a)));
+        let r = i64x2::from(vaddl_s32(a.into(), a.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vaddl_u8() {
+    fn test_vaddl_u8() {
         let v = u8::MAX;
         let a = u8x8::new(v, v, v, v, v, v, v, v);
         let v = 2 * (v as u16);
         let e = u16x8::new(v, v, v, v, v, v, v, v);
-        let r: u16x8 = transmute(vaddl_u8(transmute(a), transmute(a)));
+        let r = u16x8::from(vaddl_u8(a.into(), a.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vaddl_u16() {
+    fn test_vaddl_u16() {
         let v = u16::MAX;
         let a = u16x4::new(v, v, v, v);
         let v = 2 * (v as u32);
         let e = u32x4::new(v, v, v, v);
-        let r: u32x4 = transmute(vaddl_u16(transmute(a), transmute(a)));
+        let r = u32x4::from(vaddl_u16(a.into(), a.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vaddl_u32() {
+    fn test_vaddl_u32() {
         let v = u32::MAX;
         let a = u32x2::new(v, v);
         let v = 2 * (v as u64);
         let e = u64x2::new(v, v);
-        let r: u64x2 = transmute(vaddl_u32(transmute(a), transmute(a)));
+        let r = u64x2::from(vaddl_u32(a.into(), a.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vaddl_high_s8() {
+    fn test_vaddl_high_s8() {
         let a = i8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let x = i8::MAX;
         let b = i8x16::new(x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, x);
         let x = x as i16;
         let e = i16x8::new(x + 8, x + 9, x + 10, x + 11, x + 12, x + 13, x + 14, x + 15);
-        let r: i16x8 = transmute(vaddl_high_s8(transmute(a), transmute(b)));
+        let r = i16x8::from(vaddl_high_s8(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vaddl_high_s16() {
+    fn test_vaddl_high_s16() {
         let a = i16x8::new(0, 1, 2, 3, 4, 5, 6, 7);
         let x = i16::MAX;
         let b = i16x8::new(x, x, x, x, x, x, x, x);
         let x = x as i32;
         let e = i32x4::new(x + 4, x + 5, x + 6, x + 7);
-        let r: i32x4 = transmute(vaddl_high_s16(transmute(a), transmute(b)));
+        let r = i32x4::from(vaddl_high_s16(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vaddl_high_s32() {
+    fn test_vaddl_high_s32() {
         let a = i32x4::new(0, 1, 2, 3);
         let x = i32::MAX;
         let b = i32x4::new(x, x, x, x);
         let x = x as i64;
         let e = i64x2::new(x + 2, x + 3);
-        let r: i64x2 = transmute(vaddl_high_s32(transmute(a), transmute(b)));
+        let r = i64x2::from(vaddl_high_s32(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vaddl_high_u8() {
+    fn test_vaddl_high_u8() {
         let a = u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let x = u8::MAX;
         let b = u8x16::new(x, x, x, x, x, x, x, x, x, x, x, x, x, x, x, x);
         let x = x as u16;
         let e = u16x8::new(x + 8, x + 9, x + 10, x + 11, x + 12, x + 13, x + 14, x + 15);
-        let r: u16x8 = transmute(vaddl_high_u8(transmute(a), transmute(b)));
+        let r = u16x8::from(vaddl_high_u8(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vaddl_high_u16() {
+    fn test_vaddl_high_u16() {
         let a = u16x8::new(0, 1, 2, 3, 4, 5, 6, 7);
         let x = u16::MAX;
         let b = u16x8::new(x, x, x, x, x, x, x, x);
         let x = x as u32;
         let e = u32x4::new(x + 4, x + 5, x + 6, x + 7);
-        let r: u32x4 = transmute(vaddl_high_u16(transmute(a), transmute(b)));
+        let r = u32x4::from(vaddl_high_u16(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vaddl_high_u32() {
+    fn test_vaddl_high_u32() {
         let a = u32x4::new(0, 1, 2, 3);
         let x = u32::MAX;
         let b = u32x4::new(x, x, x, x);
         let x = x as u64;
         let e = u64x2::new(x + 2, x + 3);
-        let r: u64x2 = transmute(vaddl_high_u32(transmute(a), transmute(b)));
+        let r = u64x2::from(vaddl_high_u32(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vaddw_s8() {
+    fn test_vaddw_s8() {
         let x = i16::MAX;
         let a = i16x8::new(x, 1, 2, 3, 4, 5, 6, 7);
         let y = i8::MAX;
@@ -2710,36 +2721,36 @@ mod tests {
             6 + y,
             7 + y,
         );
-        let r: i16x8 = transmute(vaddw_s8(transmute(a), transmute(b)));
+        let r = i16x8::from(vaddw_s8(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vaddw_s16() {
+    fn test_vaddw_s16() {
         let x = i32::MAX;
         let a = i32x4::new(x, 1, 2, 3);
         let y = i16::MAX;
         let b = i16x4::new(y, y, y, y);
         let y = y as i32;
         let e = i32x4::new(x.wrapping_add(y), 1 + y, 2 + y, 3 + y);
-        let r: i32x4 = transmute(vaddw_s16(transmute(a), transmute(b)));
+        let r = i32x4::from(vaddw_s16(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vaddw_s32() {
+    fn test_vaddw_s32() {
         let x = i64::MAX;
         let a = i64x2::new(x, 1);
         let y = i32::MAX;
         let b = i32x2::new(y, y);
         let y = y as i64;
         let e = i64x2::new(x.wrapping_add(y), 1 + y);
-        let r: i64x2 = transmute(vaddw_s32(transmute(a), transmute(b)));
+        let r = i64x2::from(vaddw_s32(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vaddw_u8() {
+    fn test_vaddw_u8() {
         let x = u16::MAX;
         let a = u16x8::new(x, 1, 2, 3, 4, 5, 6, 7);
         let y = u8::MAX;
@@ -2755,36 +2766,36 @@ mod tests {
             6 + y,
             7 + y,
         );
-        let r: u16x8 = transmute(vaddw_u8(transmute(a), transmute(b)));
+        let r = u16x8::from(vaddw_u8(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vaddw_u16() {
+    fn test_vaddw_u16() {
         let x = u32::MAX;
         let a = u32x4::new(x, 1, 2, 3);
         let y = u16::MAX;
         let b = u16x4::new(y, y, y, y);
         let y = y as u32;
         let e = u32x4::new(x.wrapping_add(y), 1 + y, 2 + y, 3 + y);
-        let r: u32x4 = transmute(vaddw_u16(transmute(a), transmute(b)));
+        let r = u32x4::from(vaddw_u16(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vaddw_u32() {
+    fn test_vaddw_u32() {
         let x = u64::MAX;
         let a = u64x2::new(x, 1);
         let y = u32::MAX;
         let b = u32x2::new(y, y);
         let y = y as u64;
         let e = u64x2::new(x.wrapping_add(y), 1 + y);
-        let r: u64x2 = transmute(vaddw_u32(transmute(a), transmute(b)));
+        let r = u64x2::from(vaddw_u32(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vaddw_high_s8() {
+    fn test_vaddw_high_s8() {
         let x = i16::MAX;
         let a = i16x8::new(x, 1, 2, 3, 4, 5, 6, 7);
         let y = i8::MAX;
@@ -2800,36 +2811,36 @@ mod tests {
             6 + y,
             7 + y,
         );
-        let r: i16x8 = transmute(vaddw_high_s8(transmute(a), transmute(b)));
+        let r = i16x8::from(vaddw_high_s8(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vaddw_high_s16() {
+    fn test_vaddw_high_s16() {
         let x = i32::MAX;
         let a = i32x4::new(x, 1, 2, 3);
         let y = i16::MAX;
         let b = i16x8::new(0, 0, 0, 0, y, y, y, y);
         let y = y as i32;
         let e = i32x4::new(x.wrapping_add(y), 1 + y, 2 + y, 3 + y);
-        let r: i32x4 = transmute(vaddw_high_s16(transmute(a), transmute(b)));
+        let r = i32x4::from(vaddw_high_s16(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vaddw_high_s32() {
+    fn test_vaddw_high_s32() {
         let x = i64::MAX;
         let a = i64x2::new(x, 1);
         let y = i32::MAX;
         let b = i32x4::new(0, 0, y, y);
         let y = y as i64;
         let e = i64x2::new(x.wrapping_add(y), 1 + y);
-        let r: i64x2 = transmute(vaddw_high_s32(transmute(a), transmute(b)));
+        let r = i64x2::from(vaddw_high_s32(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vaddw_high_u8() {
+    fn test_vaddw_high_u8() {
         let x = u16::MAX;
         let a = u16x8::new(x, 1, 2, 3, 4, 5, 6, 7);
         let y = u8::MAX;
@@ -2845,165 +2856,165 @@ mod tests {
             6 + y,
             7 + y,
         );
-        let r: u16x8 = transmute(vaddw_high_u8(transmute(a), transmute(b)));
+        let r = u16x8::from(vaddw_high_u8(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vaddw_high_u16() {
+    fn test_vaddw_high_u16() {
         let x = u32::MAX;
         let a = u32x4::new(x, 1, 2, 3);
         let y = u16::MAX;
         let b = u16x8::new(0, 0, 0, 0, y, y, y, y);
         let y = y as u32;
         let e = u32x4::new(x.wrapping_add(y), 1 + y, 2 + y, 3 + y);
-        let r: u32x4 = transmute(vaddw_high_u16(transmute(a), transmute(b)));
+        let r = u32x4::from(vaddw_high_u16(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vaddw_high_u32() {
+    fn test_vaddw_high_u32() {
         let x = u64::MAX;
         let a = u64x2::new(x, 1);
         let y = u32::MAX;
         let b = u32x4::new(0, 0, y, y);
         let y = y as u64;
         let e = u64x2::new(x.wrapping_add(y), 1 + y);
-        let r: u64x2 = transmute(vaddw_high_u32(transmute(a), transmute(b)));
+        let r = u64x2::from(vaddw_high_u32(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmvn_s8() {
+    fn test_vmvn_s8() {
         let a = i8x8::new(0, 1, 2, 3, 4, 5, 6, 7);
         let e = i8x8::new(-1, -2, -3, -4, -5, -6, -7, -8);
-        let r: i8x8 = transmute(vmvn_s8(transmute(a)));
+        let r = i8x8::from(vmvn_s8(a.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmvnq_s8() {
+    fn test_vmvnq_s8() {
         let a = i8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let e = i8x16::new(
             -1, -2, -3, -4, -5, -6, -7, -8, -9, -10, -11, -12, -13, -14, -15, -16,
         );
-        let r: i8x16 = transmute(vmvnq_s8(transmute(a)));
+        let r = i8x16::from(vmvnq_s8(a.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmvn_s16() {
+    fn test_vmvn_s16() {
         let a = i16x4::new(0, 1, 2, 3);
         let e = i16x4::new(-1, -2, -3, -4);
-        let r: i16x4 = transmute(vmvn_s16(transmute(a)));
+        let r = i16x4::from(vmvn_s16(a.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmvnq_s16() {
+    fn test_vmvnq_s16() {
         let a = i16x8::new(0, 1, 2, 3, 4, 5, 6, 7);
         let e = i16x8::new(-1, -2, -3, -4, -5, -6, -7, -8);
-        let r: i16x8 = transmute(vmvnq_s16(transmute(a)));
+        let r = i16x8::from(vmvnq_s16(a.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmvn_s32() {
+    fn test_vmvn_s32() {
         let a = i32x2::new(0, 1);
         let e = i32x2::new(-1, -2);
-        let r: i32x2 = transmute(vmvn_s32(transmute(a)));
+        let r = i32x2::from(vmvn_s32(a.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmvnq_s32() {
+    fn test_vmvnq_s32() {
         let a = i32x4::new(0, 1, 2, 3);
         let e = i32x4::new(-1, -2, -3, -4);
-        let r: i32x4 = transmute(vmvnq_s32(transmute(a)));
+        let r = i32x4::from(vmvnq_s32(a.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmvn_u8() {
+    fn test_vmvn_u8() {
         let a = u8x8::new(0, 1, 2, 3, 4, 5, 6, 7);
         let e = u8x8::new(255, 254, 253, 252, 251, 250, 249, 248);
-        let r: u8x8 = transmute(vmvn_u8(transmute(a)));
+        let r = u8x8::from(vmvn_u8(a.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmvnq_u8() {
+    fn test_vmvnq_u8() {
         let a = u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let e = u8x16::new(
             255, 254, 253, 252, 251, 250, 249, 248, 247, 246, 245, 244, 243, 242, 241, 240,
         );
-        let r: u8x16 = transmute(vmvnq_u8(transmute(a)));
+        let r = u8x16::from(vmvnq_u8(a.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmvn_u16() {
+    fn test_vmvn_u16() {
         let a = u16x4::new(0, 1, 2, 3);
         let e = u16x4::new(65_535, 65_534, 65_533, 65_532);
-        let r: u16x4 = transmute(vmvn_u16(transmute(a)));
+        let r = u16x4::from(vmvn_u16(a.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmvnq_u16() {
+    fn test_vmvnq_u16() {
         let a = u16x8::new(0, 1, 2, 3, 4, 5, 6, 7);
         let e = u16x8::new(
             65_535, 65_534, 65_533, 65_532, 65_531, 65_530, 65_529, 65_528,
         );
-        let r: u16x8 = transmute(vmvnq_u16(transmute(a)));
+        let r = u16x8::from(vmvnq_u16(a.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmvn_u32() {
+    fn test_vmvn_u32() {
         let a = u32x2::new(0, 1);
         let e = u32x2::new(4_294_967_295, 4_294_967_294);
-        let r: u32x2 = transmute(vmvn_u32(transmute(a)));
+        let r = u32x2::from(vmvn_u32(a.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmvnq_u32() {
+    fn test_vmvnq_u32() {
         let a = u32x4::new(0, 1, 2, 3);
         let e = u32x4::new(4_294_967_295, 4_294_967_294, 4_294_967_293, 4_294_967_292);
-        let r: u32x4 = transmute(vmvnq_u32(transmute(a)));
+        let r = u32x4::from(vmvnq_u32(a.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmvn_p8() {
+    fn test_vmvn_p8() {
         let a = u8x8::new(0, 1, 2, 3, 4, 5, 6, 7);
         let e = u8x8::new(255, 254, 253, 252, 251, 250, 249, 248);
-        let r: u8x8 = transmute(vmvn_p8(transmute(a)));
+        let r = u8x8::from(vmvn_p8(a.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmvnq_p8() {
+    fn test_vmvnq_p8() {
         let a = u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let e = u8x16::new(
             255, 254, 253, 252, 251, 250, 249, 248, 247, 246, 245, 244, 243, 242, 241, 240,
         );
-        let r: u8x16 = transmute(vmvnq_p8(transmute(a)));
+        let r = u8x16::from(vmvnq_p8(a.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vbic_s8() {
+    fn test_vbic_s8() {
         let a = i8x8::new(0, -1, -2, -3, -4, -5, -6, -7);
         let b = i8x8::new(1, 1, 1, 1, 1, 1, 1, 1);
         let e = i8x8::new(0, -2, -2, -4, -4, -6, -6, -8);
-        let r: i8x8 = transmute(vbic_s8(transmute(a), transmute(b)));
+        let r = i8x8::from(vbic_s8(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vbicq_s8() {
+    fn test_vbicq_s8() {
         let a = i8x16::new(
             0, -1, -2, -3, -4, -5, -6, -7, -8, -9, -10, -11, -12, -13, -14, -15,
         );
@@ -3011,138 +3022,138 @@ mod tests {
         let e = i8x16::new(
             0, -2, -2, -4, -4, -6, -6, -8, -8, -10, -10, -12, -12, -14, -14, -16,
         );
-        let r: i8x16 = transmute(vbicq_s8(transmute(a), transmute(b)));
+        let r = i8x16::from(vbicq_s8(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vbic_s16() {
+    fn test_vbic_s16() {
         let a = i16x4::new(0, -1, -2, -3);
         let b = i16x4::new(1, 1, 1, 1);
         let e = i16x4::new(0, -2, -2, -4);
-        let r: i16x4 = transmute(vbic_s16(transmute(a), transmute(b)));
+        let r = i16x4::from(vbic_s16(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vbicq_s16() {
+    fn test_vbicq_s16() {
         let a = i16x8::new(0, -1, -2, -3, -4, -5, -6, -7);
         let b = i16x8::new(1, 1, 1, 1, 1, 1, 1, 1);
         let e = i16x8::new(0, -2, -2, -4, -4, -6, -6, -8);
-        let r: i16x8 = transmute(vbicq_s16(transmute(a), transmute(b)));
+        let r = i16x8::from(vbicq_s16(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vbic_s32() {
+    fn test_vbic_s32() {
         let a = i32x2::new(0, -1);
         let b = i32x2::new(1, 1);
         let e = i32x2::new(0, -2);
-        let r: i32x2 = transmute(vbic_s32(transmute(a), transmute(b)));
+        let r = i32x2::from(vbic_s32(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vbicq_s32() {
+    fn test_vbicq_s32() {
         let a = i32x4::new(0, -1, -2, -3);
         let b = i32x4::new(1, 1, 1, 1);
         let e = i32x4::new(0, -2, -2, -4);
-        let r: i32x4 = transmute(vbicq_s32(transmute(a), transmute(b)));
+        let r = i32x4::from(vbicq_s32(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vbic_s64() {
+    fn test_vbic_s64() {
         let a = i64x1::new(-1);
         let b = i64x1::new(1);
         let e = i64x1::new(-2);
-        let r: i64x1 = transmute(vbic_s64(transmute(a), transmute(b)));
+        let r = i64x1::from(vbic_s64(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vbicq_s64() {
+    fn test_vbicq_s64() {
         let a = i64x2::new(0, -1);
         let b = i64x2::new(1, 1);
         let e = i64x2::new(0, -2);
-        let r: i64x2 = transmute(vbicq_s64(transmute(a), transmute(b)));
+        let r = i64x2::from(vbicq_s64(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vbic_u8() {
+    fn test_vbic_u8() {
         let a = u8x8::new(0, 1, 2, 3, 4, 5, 6, 7);
         let b = u8x8::new(1, 1, 1, 1, 1, 1, 1, 1);
         let e = u8x8::new(0, 0, 2, 2, 4, 4, 6, 6);
-        let r: u8x8 = transmute(vbic_u8(transmute(a), transmute(b)));
+        let r = u8x8::from(vbic_u8(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vbicq_u8() {
+    fn test_vbicq_u8() {
         let a = u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let b = u8x16::new(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
         let e = u8x16::new(0, 0, 2, 2, 4, 4, 6, 6, 8, 8, 10, 10, 12, 12, 14, 14);
-        let r: u8x16 = transmute(vbicq_u8(transmute(a), transmute(b)));
+        let r = u8x16::from(vbicq_u8(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vbic_u16() {
+    fn test_vbic_u16() {
         let a = u16x4::new(0, 1, 2, 3);
         let b = u16x4::new(1, 1, 1, 1);
         let e = u16x4::new(0, 0, 2, 2);
-        let r: u16x4 = transmute(vbic_u16(transmute(a), transmute(b)));
+        let r = u16x4::from(vbic_u16(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vbicq_u16() {
+    fn test_vbicq_u16() {
         let a = u16x8::new(0, 1, 2, 3, 4, 5, 6, 7);
         let b = u16x8::new(1, 1, 1, 1, 1, 1, 1, 1);
         let e = u16x8::new(0, 0, 2, 2, 4, 4, 6, 6);
-        let r: u16x8 = transmute(vbicq_u16(transmute(a), transmute(b)));
+        let r = u16x8::from(vbicq_u16(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vbic_u32() {
+    fn test_vbic_u32() {
         let a = u32x2::new(0, 1);
         let b = u32x2::new(1, 1);
         let e = u32x2::new(0, 0);
-        let r: u32x2 = transmute(vbic_u32(transmute(a), transmute(b)));
+        let r = u32x2::from(vbic_u32(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vbicq_u32() {
+    fn test_vbicq_u32() {
         let a = u32x4::new(0, 1, 2, 3);
         let b = u32x4::new(1, 1, 1, 1);
         let e = u32x4::new(0, 0, 2, 2);
-        let r: u32x4 = transmute(vbicq_u32(transmute(a), transmute(b)));
+        let r = u32x4::from(vbicq_u32(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vbic_u64() {
+    fn test_vbic_u64() {
         let a = u64x1::new(1);
         let b = u64x1::new(1);
         let e = u64x1::new(0);
-        let r: u64x1 = transmute(vbic_u64(transmute(a), transmute(b)));
+        let r = u64x1::from(vbic_u64(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vbicq_u64() {
+    fn test_vbicq_u64() {
         let a = u64x2::new(0, 1);
         let b = u64x2::new(1, 1);
         let e = u64x2::new(0, 0);
-        let r: u64x2 = transmute(vbicq_u64(transmute(a), transmute(b)));
+        let r = u64x2::from(vbicq_u64(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vbsl_s8() {
+    fn test_vbsl_s8() {
         let a = u8x8::new(u8::MAX, 1, u8::MAX, 2, u8::MAX, 0, u8::MAX, 0);
         let b = i8x8::new(
             i8::MAX,
@@ -3174,38 +3185,42 @@ mod tests {
             i8::MAX,
             i8::MIN,
         );
-        let r: i8x8 = transmute(vbsl_s8(transmute(a), transmute(b), transmute(c)));
+        let r = i8x8::from(vbsl_s8(a.into(), b.into(), c.into()));
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vbsl_s16() {
+    fn test_vbsl_s16() {
         let a = u16x4::new(u16::MAX, 0, 1, 2);
         let b = i16x4::new(i16::MAX, i16::MAX, i16::MAX, i16::MAX);
         let c = i16x4::new(i16::MIN, i16::MIN, i16::MIN, i16::MIN);
         let e = i16x4::new(i16::MAX, i16::MIN, i16::MIN | 1, i16::MIN | 2);
-        let r: i16x4 = transmute(vbsl_s16(transmute(a), transmute(b), transmute(c)));
+        let r = i16x4::from(vbsl_s16(a.into(), b.into(), c.into()));
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vbsl_s32() {
+    fn test_vbsl_s32() {
         let a = u32x2::new(u32::MAX, 1);
         let b = i32x2::new(i32::MAX, i32::MAX);
         let c = i32x2::new(i32::MIN, i32::MIN);
         let e = i32x2::new(i32::MAX, i32::MIN | 1);
-        let r: i32x2 = transmute(vbsl_s32(transmute(a), transmute(b), transmute(c)));
+        let r = i32x2::from(vbsl_s32(a.into(), b.into(), c.into()));
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vbsl_s64() {
+    fn test_vbsl_s64() {
         let a = u64x1::new(1);
         let b = i64x1::new(i64::MAX);
         let c = i64x1::new(i64::MIN);
         let e = i64x1::new(i64::MIN | 1);
-        let r: i64x1 = transmute(vbsl_s64(transmute(a), transmute(b), transmute(c)));
+        let r = i64x1::from(vbsl_s64(a.into(), b.into(), c.into()));
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vbsl_u8() {
+    fn test_vbsl_u8() {
         let a = u8x8::new(u8::MAX, 1, u8::MAX, 2, u8::MAX, 0, u8::MAX, 0);
         let b = u8x8::new(
             u8::MAX,
@@ -3228,47 +3243,52 @@ mod tests {
             u8::MIN,
         );
         let e = u8x8::new(u8::MAX, 1, u8::MAX, 2, u8::MAX, u8::MIN, u8::MAX, u8::MIN);
-        let r: u8x8 = transmute(vbsl_u8(transmute(a), transmute(b), transmute(c)));
+        let r = u8x8::from(vbsl_u8(a.into(), b.into(), c.into()));
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vbsl_u16() {
+    fn test_vbsl_u16() {
         let a = u16x4::new(u16::MAX, 0, 1, 2);
         let b = u16x4::new(u16::MAX, u16::MAX, u16::MAX, u16::MAX);
         let c = u16x4::new(u16::MIN, u16::MIN, u16::MIN, u16::MIN);
         let e = u16x4::new(u16::MAX, 0, 1, 2);
-        let r: u16x4 = transmute(vbsl_u16(transmute(a), transmute(b), transmute(c)));
+        let r = u16x4::from(vbsl_u16(a.into(), b.into(), c.into()));
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vbsl_u32() {
+    fn test_vbsl_u32() {
         let a = u32x2::new(u32::MAX, 2);
         let b = u32x2::new(u32::MAX, u32::MAX);
         let c = u32x2::new(u32::MIN, u32::MIN);
         let e = u32x2::new(u32::MAX, 2);
-        let r: u32x2 = transmute(vbsl_u32(transmute(a), transmute(b), transmute(c)));
+        let r = u32x2::from(vbsl_u32(a.into(), b.into(), c.into()));
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vbsl_u64() {
+    fn test_vbsl_u64() {
         let a = u64x1::new(2);
         let b = u64x1::new(u64::MAX);
         let c = u64x1::new(u64::MIN);
         let e = u64x1::new(2);
-        let r: u64x1 = transmute(vbsl_u64(transmute(a), transmute(b), transmute(c)));
+        let r = u64x1::from(vbsl_u64(a.into(), b.into(), c.into()));
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vbsl_f32() {
+    fn test_vbsl_f32() {
         let a = u32x2::new(1, 0x80000000);
         let b = f32x2::new(8388609f32, -1.23f32);
         let c = f32x2::new(2097152f32, 2.34f32);
         let e = f32x2::new(2097152.25f32, -2.34f32);
-        let r: f32x2 = transmute(vbsl_f32(transmute(a), transmute(b), transmute(c)));
+        let r = f32x2::from(vbsl_f32(a.into(), b.into(), c.into()));
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vbsl_p8() {
+    fn test_vbsl_p8() {
         let a = u8x8::new(u8::MAX, 1, u8::MAX, 2, u8::MAX, 0, u8::MAX, 0);
         let b = u8x8::new(
             u8::MAX,
@@ -3291,20 +3311,22 @@ mod tests {
             u8::MIN,
         );
         let e = u8x8::new(u8::MAX, 1, u8::MAX, 2, u8::MAX, u8::MIN, u8::MAX, u8::MIN);
-        let r: u8x8 = transmute(vbsl_p8(transmute(a), transmute(b), transmute(c)));
+        let r = u8x8::from(vbsl_p8(a.into(), b.into(), c.into()));
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vbsl_p16() {
+    fn test_vbsl_p16() {
         let a = u16x4::new(u16::MAX, 0, 1, 2);
         let b = u16x4::new(u16::MAX, u16::MAX, u16::MAX, u16::MAX);
         let c = u16x4::new(u16::MIN, u16::MIN, u16::MIN, u16::MIN);
         let e = u16x4::new(u16::MAX, 0, 1, 2);
-        let r: u16x4 = transmute(vbsl_p16(transmute(a), transmute(b), transmute(c)));
+        let r = u16x4::from(vbsl_p16(a.into(), b.into(), c.into()));
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vbslq_s8() {
+    fn test_vbslq_s8() {
         let a = u8x16::new(
             u8::MAX,
             1,
@@ -3377,11 +3399,12 @@ mod tests {
             i8::MAX,
             i8::MIN,
         );
-        let r: i8x16 = transmute(vbslq_s8(transmute(a), transmute(b), transmute(c)));
+        let r = i8x16::from(vbslq_s8(a.into(), b.into(), c.into()));
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vbslq_s16() {
+    fn test_vbslq_s16() {
         let a = u16x8::new(u16::MAX, 1, u16::MAX, 2, u16::MAX, 0, u16::MAX, 0);
         let b = i16x8::new(
             i16::MAX,
@@ -3413,29 +3436,32 @@ mod tests {
             i16::MAX,
             i16::MIN,
         );
-        let r: i16x8 = transmute(vbslq_s16(transmute(a), transmute(b), transmute(c)));
+        let r = i16x8::from(vbslq_s16(a.into(), b.into(), c.into()));
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vbslq_s32() {
+    fn test_vbslq_s32() {
         let a = u32x4::new(u32::MAX, 1, u32::MAX, 2);
         let b = i32x4::new(i32::MAX, i32::MAX, i32::MAX, i32::MAX);
         let c = i32x4::new(i32::MIN, i32::MIN, i32::MIN, i32::MIN);
         let e = i32x4::new(i32::MAX, i32::MIN | 1, i32::MAX, i32::MIN | 2);
-        let r: i32x4 = transmute(vbslq_s32(transmute(a), transmute(b), transmute(c)));
+        let r = i32x4::from(vbslq_s32(a.into(), b.into(), c.into()));
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vbslq_s64() {
+    fn test_vbslq_s64() {
         let a = u64x2::new(u64::MAX, 1);
         let b = i64x2::new(i64::MAX, i64::MAX);
         let c = i64x2::new(i64::MIN, i64::MIN);
         let e = i64x2::new(i64::MAX, i64::MIN | 1);
-        let r: i64x2 = transmute(vbslq_s64(transmute(a), transmute(b), transmute(c)));
+        let r = i64x2::from(vbslq_s64(a.into(), b.into(), c.into()));
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vbslq_u8() {
+    fn test_vbslq_u8() {
         let a = u8x16::new(
             u8::MAX,
             1,
@@ -3508,11 +3534,12 @@ mod tests {
             u8::MAX,
             u8::MIN,
         );
-        let r: u8x16 = transmute(vbslq_u8(transmute(a), transmute(b), transmute(c)));
+        let r = u8x16::from(vbslq_u8(a.into(), b.into(), c.into()));
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vbslq_u16() {
+    fn test_vbslq_u16() {
         let a = u16x8::new(u16::MAX, 1, u16::MAX, 2, u16::MAX, 0, u16::MAX, 0);
         let b = u16x8::new(
             u16::MAX,
@@ -3544,38 +3571,42 @@ mod tests {
             u16::MAX,
             u16::MIN,
         );
-        let r: u16x8 = transmute(vbslq_u16(transmute(a), transmute(b), transmute(c)));
+        let r = u16x8::from(vbslq_u16(a.into(), b.into(), c.into()));
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vbslq_u32() {
+    fn test_vbslq_u32() {
         let a = u32x4::new(u32::MAX, 1, u32::MAX, 2);
         let b = u32x4::new(u32::MAX, u32::MAX, u32::MAX, u32::MAX);
         let c = u32x4::new(u32::MIN, u32::MIN, u32::MIN, u32::MIN);
         let e = u32x4::new(u32::MAX, 1, u32::MAX, 2);
-        let r: u32x4 = transmute(vbslq_u32(transmute(a), transmute(b), transmute(c)));
+        let r = u32x4::from(vbslq_u32(a.into(), b.into(), c.into()));
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vbslq_u64() {
+    fn test_vbslq_u64() {
         let a = u64x2::new(u64::MAX, 1);
         let b = u64x2::new(u64::MAX, u64::MAX);
         let c = u64x2::new(u64::MIN, u64::MIN);
         let e = u64x2::new(u64::MAX, 1);
-        let r: u64x2 = transmute(vbslq_u64(transmute(a), transmute(b), transmute(c)));
+        let r = u64x2::from(vbslq_u64(a.into(), b.into(), c.into()));
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vbslq_f32() {
+    fn test_vbslq_f32() {
         let a = u32x4::new(u32::MAX, 0, 1, 0x80000000);
         let b = f32x4::new(-1.23f32, -1.23f32, 8388609f32, -1.23f32);
         let c = f32x4::new(2.34f32, 2.34f32, 2097152f32, 2.34f32);
         let e = f32x4::new(-1.23f32, 2.34f32, 2097152.25f32, -2.34f32);
-        let r: f32x4 = transmute(vbslq_f32(transmute(a), transmute(b), transmute(c)));
+        let r = f32x4::from(vbslq_f32(a.into(), b.into(), c.into()));
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vbslq_p8() {
+    fn test_vbslq_p8() {
         let a = u8x16::new(
             u8::MAX,
             1,
@@ -3648,11 +3679,12 @@ mod tests {
             u8::MAX,
             u8::MIN,
         );
-        let r: u8x16 = transmute(vbslq_p8(transmute(a), transmute(b), transmute(c)));
+        let r = u8x16::from(vbslq_p8(a.into(), b.into(), c.into()));
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vbslq_p16() {
+    fn test_vbslq_p16() {
         let a = u16x8::new(u16::MAX, 1, u16::MAX, 2, u16::MAX, 0, u16::MAX, 0);
         let b = u16x8::new(
             u16::MAX,
@@ -3684,21 +3716,21 @@ mod tests {
             u16::MAX,
             u16::MIN,
         );
-        let r: u16x8 = transmute(vbslq_p16(transmute(a), transmute(b), transmute(c)));
+        let r = u16x8::from(vbslq_p16(a.into(), b.into(), c.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vorn_s8() {
+    fn test_vorn_s8() {
         let a = i8x8::new(0, -1, -2, -3, -4, -5, -6, -7);
         let b = i8x8::new(-2, -2, -2, -2, -2, -2, -2, -2);
         let e = i8x8::new(1, -1, -1, -3, -3, -5, -5, -7);
-        let r: i8x8 = transmute(vorn_s8(transmute(a), transmute(b)));
+        let r = i8x8::from(vorn_s8(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vornq_s8() {
+    fn test_vornq_s8() {
         let a = i8x16::new(
             0, -1, -2, -3, -4, -5, -6, -7, -8, -9, -10, -11, -12, -13, -14, -15,
         );
@@ -3708,475 +3740,522 @@ mod tests {
         let e = i8x16::new(
             1, -1, -1, -3, -3, -5, -5, -7, -7, -9, -9, -11, -11, -13, -13, -15,
         );
-        let r: i8x16 = transmute(vornq_s8(transmute(a), transmute(b)));
+        let r = i8x16::from(vornq_s8(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vorn_s16() {
+    fn test_vorn_s16() {
         let a = i16x4::new(0, -1, -2, -3);
         let b = i16x4::new(-2, -2, -2, -2);
         let e = i16x4::new(1, -1, -1, -3);
-        let r: i16x4 = transmute(vorn_s16(transmute(a), transmute(b)));
+        let r = i16x4::from(vorn_s16(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vornq_s16() {
+    fn test_vornq_s16() {
         let a = i16x8::new(0, -1, -2, -3, -4, -5, -6, -7);
         let b = i16x8::new(-2, -2, -2, -2, -2, -2, -2, -2);
         let e = i16x8::new(1, -1, -1, -3, -3, -5, -5, -7);
-        let r: i16x8 = transmute(vornq_s16(transmute(a), transmute(b)));
+        let r = i16x8::from(vornq_s16(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vorn_s32() {
+    fn test_vorn_s32() {
         let a = i32x2::new(0, -1);
         let b = i32x2::new(-2, -2);
         let e = i32x2::new(1, -1);
-        let r: i32x2 = transmute(vorn_s32(transmute(a), transmute(b)));
+        let r = i32x2::from(vorn_s32(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vornq_s32() {
+    fn test_vornq_s32() {
         let a = i32x4::new(0, -1, -2, -3);
         let b = i32x4::new(-2, -2, -2, -2);
         let e = i32x4::new(1, -1, -1, -3);
-        let r: i32x4 = transmute(vornq_s32(transmute(a), transmute(b)));
+        let r = i32x4::from(vornq_s32(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vorn_s64() {
+    fn test_vorn_s64() {
         let a = i64x1::new(0);
         let b = i64x1::new(-2);
         let e = i64x1::new(1);
-        let r: i64x1 = transmute(vorn_s64(transmute(a), transmute(b)));
+        let r = i64x1::from(vorn_s64(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vornq_s64() {
+    fn test_vornq_s64() {
         let a = i64x2::new(0, -1);
         let b = i64x2::new(-2, -2);
         let e = i64x2::new(1, -1);
-        let r: i64x2 = transmute(vornq_s64(transmute(a), transmute(b)));
+        let r = i64x2::from(vornq_s64(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vorn_u8() {
+    fn test_vorn_u8() {
         let a = u8x8::new(0, 1, 2, 3, 4, 5, 6, 7);
         let t = u8::MAX - 1;
         let b = u8x8::new(t, t, t, t, t, t, t, t);
         let e = u8x8::new(1, 1, 3, 3, 5, 5, 7, 7);
-        let r: u8x8 = transmute(vorn_u8(transmute(a), transmute(b)));
+        let r = u8x8::from(vorn_u8(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vornq_u8() {
+    fn test_vornq_u8() {
         let a = u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let t = u8::MAX - 1;
         let b = u8x16::new(t, t, t, t, t, t, t, t, t, t, t, t, t, t, t, t);
         let e = u8x16::new(1, 1, 3, 3, 5, 5, 7, 7, 9, 9, 11, 11, 13, 13, 15, 15);
-        let r: u8x16 = transmute(vornq_u8(transmute(a), transmute(b)));
+        let r = u8x16::from(vornq_u8(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vorn_u16() {
+    fn test_vorn_u16() {
         let a = u16x4::new(0, 1, 2, 3);
         let t = u16::MAX - 1;
         let b = u16x4::new(t, t, t, t);
         let e = u16x4::new(1, 1, 3, 3);
-        let r: u16x4 = transmute(vorn_u16(transmute(a), transmute(b)));
+        let r = u16x4::from(vorn_u16(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vornq_u16() {
+    fn test_vornq_u16() {
         let a = u16x8::new(0, 1, 2, 3, 4, 5, 6, 7);
         let t = u16::MAX - 1;
         let b = u16x8::new(t, t, t, t, t, t, t, t);
         let e = u16x8::new(1, 1, 3, 3, 5, 5, 7, 7);
-        let r: u16x8 = transmute(vornq_u16(transmute(a), transmute(b)));
+        let r = u16x8::from(vornq_u16(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vorn_u32() {
+    fn test_vorn_u32() {
         let a = u32x2::new(0, 1);
         let t = u32::MAX - 1;
         let b = u32x2::new(t, t);
         let e = u32x2::new(1, 1);
-        let r: u32x2 = transmute(vorn_u32(transmute(a), transmute(b)));
+        let r = u32x2::from(vorn_u32(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vornq_u32() {
+    fn test_vornq_u32() {
         let a = u32x4::new(0, 1, 2, 3);
         let t = u32::MAX - 1;
         let b = u32x4::new(t, t, t, t);
         let e = u32x4::new(1, 1, 3, 3);
-        let r: u32x4 = transmute(vornq_u32(transmute(a), transmute(b)));
+        let r = u32x4::from(vornq_u32(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vorn_u64() {
+    fn test_vorn_u64() {
         let a = u64x1::new(0);
         let t = u64::MAX - 1;
         let b = u64x1::new(t);
         let e = u64x1::new(1);
-        let r: u64x1 = transmute(vorn_u64(transmute(a), transmute(b)));
+        let r = u64x1::from(vorn_u64(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vornq_u64() {
+    fn test_vornq_u64() {
         let a = u64x2::new(0, 1);
         let t = u64::MAX - 1;
         let b = u64x2::new(t, t);
         let e = u64x2::new(1, 1);
-        let r: u64x2 = transmute(vornq_u64(transmute(a), transmute(b)));
+        let r = u64x2::from(vornq_u64(a.into(), b.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmovn_s16() {
+    fn test_vmovn_s16() {
         let a = i16x8::new(1, 2, 3, 4, 5, 6, 7, 8);
         let e = i8x8::new(1, 2, 3, 4, 5, 6, 7, 8);
-        let r: i8x8 = transmute(vmovn_s16(transmute(a)));
+        let r = i8x8::from(vmovn_s16(a.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmovn_s32() {
+    fn test_vmovn_s32() {
         let a = i32x4::new(1, 2, 3, 4);
         let e = i16x4::new(1, 2, 3, 4);
-        let r: i16x4 = transmute(vmovn_s32(transmute(a)));
+        let r = i16x4::from(vmovn_s32(a.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmovn_s64() {
+    fn test_vmovn_s64() {
         let a = i64x2::new(1, 2);
         let e = i32x2::new(1, 2);
-        let r: i32x2 = transmute(vmovn_s64(transmute(a)));
+        let r = i32x2::from(vmovn_s64(a.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmovn_u16() {
+    fn test_vmovn_u16() {
         let a = u16x8::new(1, 2, 3, 4, 5, 6, 7, 8);
         let e = u8x8::new(1, 2, 3, 4, 5, 6, 7, 8);
-        let r: u8x8 = transmute(vmovn_u16(transmute(a)));
+        let r = u8x8::from(vmovn_u16(a.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmovn_u32() {
+    fn test_vmovn_u32() {
         let a = u32x4::new(1, 2, 3, 4);
         let e = u16x4::new(1, 2, 3, 4);
-        let r: u16x4 = transmute(vmovn_u32(transmute(a)));
+        let r = u16x4::from(vmovn_u32(a.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmovn_u64() {
+    fn test_vmovn_u64() {
         let a = u64x2::new(1, 2);
         let e = u32x2::new(1, 2);
-        let r: u32x2 = transmute(vmovn_u64(transmute(a)));
+        let r = u32x2::from(vmovn_u64(a.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmovl_s8() {
+    fn test_vmovl_s8() {
         let e = i16x8::new(1, 2, 3, 4, 5, 6, 7, 8);
         let a = i8x8::new(1, 2, 3, 4, 5, 6, 7, 8);
-        let r: i16x8 = transmute(vmovl_s8(transmute(a)));
+        let r = i16x8::from(vmovl_s8(a.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmovl_s16() {
+    fn test_vmovl_s16() {
         let e = i32x4::new(1, 2, 3, 4);
         let a = i16x4::new(1, 2, 3, 4);
-        let r: i32x4 = transmute(vmovl_s16(transmute(a)));
+        let r = i32x4::from(vmovl_s16(a.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmovl_s32() {
+    fn test_vmovl_s32() {
         let e = i64x2::new(1, 2);
         let a = i32x2::new(1, 2);
-        let r: i64x2 = transmute(vmovl_s32(transmute(a)));
+        let r = i64x2::from(vmovl_s32(a.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmovl_u8() {
+    fn test_vmovl_u8() {
         let e = u16x8::new(1, 2, 3, 4, 5, 6, 7, 8);
         let a = u8x8::new(1, 2, 3, 4, 5, 6, 7, 8);
-        let r: u16x8 = transmute(vmovl_u8(transmute(a)));
+        let r = u16x8::from(vmovl_u8(a.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmovl_u16() {
+    fn test_vmovl_u16() {
         let e = u32x4::new(1, 2, 3, 4);
         let a = u16x4::new(1, 2, 3, 4);
-        let r: u32x4 = transmute(vmovl_u16(transmute(a)));
+        let r = u32x4::from(vmovl_u16(a.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmovl_u32() {
+    fn test_vmovl_u32() {
         let e = u64x2::new(1, 2);
         let a = u32x2::new(1, 2);
-        let r: u64x2 = transmute(vmovl_u32(transmute(a)));
+        let r = u64x2::from(vmovl_u32(a.into()));
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vand_s8() {
+    fn test_vand_s8() {
         test_bit_s8(|i, j| vand_s8(i, j), |a: i8, b: i8| -> i8 { a & b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vandq_s8() {
+    fn test_vandq_s8() {
         testq_bit_s8(|i, j| vandq_s8(i, j), |a: i8, b: i8| -> i8 { a & b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vand_s16() {
+    fn test_vand_s16() {
         test_bit_s16(|i, j| vand_s16(i, j), |a: i16, b: i16| -> i16 { a & b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vandq_s16() {
+    fn test_vandq_s16() {
         testq_bit_s16(|i, j| vandq_s16(i, j), |a: i16, b: i16| -> i16 { a & b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vand_s32() {
+    fn test_vand_s32() {
         test_bit_s32(|i, j| vand_s32(i, j), |a: i32, b: i32| -> i32 { a & b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vandq_s32() {
+    fn test_vandq_s32() {
         testq_bit_s32(|i, j| vandq_s32(i, j), |a: i32, b: i32| -> i32 { a & b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vand_s64() {
+    fn test_vand_s64() {
         test_bit_s64(|i, j| vand_s64(i, j), |a: i64, b: i64| -> i64 { a & b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vandq_s64() {
+    fn test_vandq_s64() {
         testq_bit_s64(|i, j| vandq_s64(i, j), |a: i64, b: i64| -> i64 { a & b });
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vand_u8() {
+    fn test_vand_u8() {
         test_bit_u8(|i, j| vand_u8(i, j), |a: u8, b: u8| -> u8 { a & b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vandq_u8() {
+    fn test_vandq_u8() {
         testq_bit_u8(|i, j| vandq_u8(i, j), |a: u8, b: u8| -> u8 { a & b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vand_u16() {
+    fn test_vand_u16() {
         test_bit_u16(|i, j| vand_u16(i, j), |a: u16, b: u16| -> u16 { a & b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vandq_u16() {
+    fn test_vandq_u16() {
         testq_bit_u16(|i, j| vandq_u16(i, j), |a: u16, b: u16| -> u16 { a & b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vand_u32() {
+    fn test_vand_u32() {
         test_bit_u32(|i, j| vand_u32(i, j), |a: u32, b: u32| -> u32 { a & b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vandq_u32() {
+    fn test_vandq_u32() {
         testq_bit_u32(|i, j| vandq_u32(i, j), |a: u32, b: u32| -> u32 { a & b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vand_u64() {
+    fn test_vand_u64() {
         test_bit_u64(|i, j| vand_u64(i, j), |a: u64, b: u64| -> u64 { a & b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vandq_u64() {
+    fn test_vandq_u64() {
         testq_bit_u64(|i, j| vandq_u64(i, j), |a: u64, b: u64| -> u64 { a & b });
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vorr_s8() {
+    fn test_vorr_s8() {
         test_bit_s8(|i, j| vorr_s8(i, j), |a: i8, b: i8| -> i8 { a | b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vorrq_s8() {
+    fn test_vorrq_s8() {
         testq_bit_s8(|i, j| vorrq_s8(i, j), |a: i8, b: i8| -> i8 { a | b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vorr_s16() {
+    fn test_vorr_s16() {
         test_bit_s16(|i, j| vorr_s16(i, j), |a: i16, b: i16| -> i16 { a | b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vorrq_s16() {
+    fn test_vorrq_s16() {
         testq_bit_s16(|i, j| vorrq_s16(i, j), |a: i16, b: i16| -> i16 { a | b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vorr_s32() {
+    fn test_vorr_s32() {
         test_bit_s32(|i, j| vorr_s32(i, j), |a: i32, b: i32| -> i32 { a | b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vorrq_s32() {
+    fn test_vorrq_s32() {
         testq_bit_s32(|i, j| vorrq_s32(i, j), |a: i32, b: i32| -> i32 { a | b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vorr_s64() {
+    fn test_vorr_s64() {
         test_bit_s64(|i, j| vorr_s64(i, j), |a: i64, b: i64| -> i64 { a | b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vorrq_s64() {
+    fn test_vorrq_s64() {
         testq_bit_s64(|i, j| vorrq_s64(i, j), |a: i64, b: i64| -> i64 { a | b });
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vorr_u8() {
+    fn test_vorr_u8() {
         test_bit_u8(|i, j| vorr_u8(i, j), |a: u8, b: u8| -> u8 { a | b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vorrq_u8() {
+    fn test_vorrq_u8() {
         testq_bit_u8(|i, j| vorrq_u8(i, j), |a: u8, b: u8| -> u8 { a | b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vorr_u16() {
+    fn test_vorr_u16() {
         test_bit_u16(|i, j| vorr_u16(i, j), |a: u16, b: u16| -> u16 { a | b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vorrq_u16() {
+    fn test_vorrq_u16() {
         testq_bit_u16(|i, j| vorrq_u16(i, j), |a: u16, b: u16| -> u16 { a | b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vorr_u32() {
+    fn test_vorr_u32() {
         test_bit_u32(|i, j| vorr_u32(i, j), |a: u32, b: u32| -> u32 { a | b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vorrq_u32() {
+    fn test_vorrq_u32() {
         testq_bit_u32(|i, j| vorrq_u32(i, j), |a: u32, b: u32| -> u32 { a | b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vorr_u64() {
+    fn test_vorr_u64() {
         test_bit_u64(|i, j| vorr_u64(i, j), |a: u64, b: u64| -> u64 { a | b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vorrq_u64() {
+    fn test_vorrq_u64() {
         testq_bit_u64(|i, j| vorrq_u64(i, j), |a: u64, b: u64| -> u64 { a | b });
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_veor_s8() {
+    fn test_veor_s8() {
         test_bit_s8(|i, j| veor_s8(i, j), |a: i8, b: i8| -> i8 { a ^ b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_veorq_s8() {
+    fn test_veorq_s8() {
         testq_bit_s8(|i, j| veorq_s8(i, j), |a: i8, b: i8| -> i8 { a ^ b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_veor_s16() {
+    fn test_veor_s16() {
         test_bit_s16(|i, j| veor_s16(i, j), |a: i16, b: i16| -> i16 { a ^ b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_veorq_s16() {
+    fn test_veorq_s16() {
         testq_bit_s16(|i, j| veorq_s16(i, j), |a: i16, b: i16| -> i16 { a ^ b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_veor_s32() {
+    fn test_veor_s32() {
         test_bit_s32(|i, j| veor_s32(i, j), |a: i32, b: i32| -> i32 { a ^ b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_veorq_s32() {
+    fn test_veorq_s32() {
         testq_bit_s32(|i, j| veorq_s32(i, j), |a: i32, b: i32| -> i32 { a ^ b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_veor_s64() {
+    fn test_veor_s64() {
         test_bit_s64(|i, j| veor_s64(i, j), |a: i64, b: i64| -> i64 { a ^ b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_veorq_s64() {
+    fn test_veorq_s64() {
         testq_bit_s64(|i, j| veorq_s64(i, j), |a: i64, b: i64| -> i64 { a ^ b });
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_veor_u8() {
+    fn test_veor_u8() {
         test_bit_u8(|i, j| veor_u8(i, j), |a: u8, b: u8| -> u8 { a ^ b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_veorq_u8() {
+    fn test_veorq_u8() {
         testq_bit_u8(|i, j| veorq_u8(i, j), |a: u8, b: u8| -> u8 { a ^ b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_veor_u16() {
+    fn test_veor_u16() {
         test_bit_u16(|i, j| veor_u16(i, j), |a: u16, b: u16| -> u16 { a ^ b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_veorq_u16() {
+    fn test_veorq_u16() {
         testq_bit_u16(|i, j| veorq_u16(i, j), |a: u16, b: u16| -> u16 { a ^ b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_veor_u32() {
+    fn test_veor_u32() {
         test_bit_u32(|i, j| veor_u32(i, j), |a: u32, b: u32| -> u32 { a ^ b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_veorq_u32() {
+    fn test_veorq_u32() {
         testq_bit_u32(|i, j| veorq_u32(i, j), |a: u32, b: u32| -> u32 { a ^ b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_veor_u64() {
+    fn test_veor_u64() {
         test_bit_u64(|i, j| veor_u64(i, j), |a: u64, b: u64| -> u64 { a ^ b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_veorq_u64() {
+    fn test_veorq_u64() {
         testq_bit_u64(|i, j| veorq_u64(i, j), |a: u64, b: u64| -> u64 { a ^ b });
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vceq_s8() {
+    fn test_vceq_s8() {
         test_cmp_s8(
             |i, j| vceq_s8(i, j),
             |a: i8, b: i8| -> u8 { if a == b { 0xFF } else { 0 } },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vceqq_s8() {
+    fn test_vceqq_s8() {
         testq_cmp_s8(
             |i, j| vceqq_s8(i, j),
             |a: i8, b: i8| -> u8 { if a == b { 0xFF } else { 0 } },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vceq_s16() {
+    fn test_vceq_s16() {
         test_cmp_s16(
             |i, j| vceq_s16(i, j),
             |a: i16, b: i16| -> u16 { if a == b { 0xFFFF } else { 0 } },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vceqq_s16() {
+    fn test_vceqq_s16() {
         testq_cmp_s16(
             |i, j| vceqq_s16(i, j),
             |a: i16, b: i16| -> u16 { if a == b { 0xFFFF } else { 0 } },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vceq_s32() {
+    fn test_vceq_s32() {
         test_cmp_s32(
             |i, j| vceq_s32(i, j),
             |a: i32, b: i32| -> u32 { if a == b { 0xFFFFFFFF } else { 0 } },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vceqq_s32() {
+    fn test_vceqq_s32() {
         testq_cmp_s32(
             |i, j| vceqq_s32(i, j),
             |a: i32, b: i32| -> u32 { if a == b { 0xFFFFFFFF } else { 0 } },
@@ -4184,42 +4263,47 @@ mod tests {
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vceq_u8() {
+    fn test_vceq_u8() {
         test_cmp_u8(
             |i, j| vceq_u8(i, j),
             |a: u8, b: u8| -> u8 { if a == b { 0xFF } else { 0 } },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vceqq_u8() {
+    fn test_vceqq_u8() {
         testq_cmp_u8(
             |i, j| vceqq_u8(i, j),
             |a: u8, b: u8| -> u8 { if a == b { 0xFF } else { 0 } },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vceq_u16() {
+    fn test_vceq_u16() {
         test_cmp_u16(
             |i, j| vceq_u16(i, j),
             |a: u16, b: u16| -> u16 { if a == b { 0xFFFF } else { 0 } },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vceqq_u16() {
+    fn test_vceqq_u16() {
         testq_cmp_u16(
             |i, j| vceqq_u16(i, j),
             |a: u16, b: u16| -> u16 { if a == b { 0xFFFF } else { 0 } },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vceq_u32() {
+    fn test_vceq_u32() {
         test_cmp_u32(
             |i, j| vceq_u32(i, j),
             |a: u32, b: u32| -> u32 { if a == b { 0xFFFFFFFF } else { 0 } },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vceqq_u32() {
+    fn test_vceqq_u32() {
         testq_cmp_u32(
             |i, j| vceqq_u32(i, j),
             |a: u32, b: u32| -> u32 { if a == b { 0xFFFFFFFF } else { 0 } },
@@ -4227,14 +4311,15 @@ mod tests {
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vceq_f32() {
+    fn test_vceq_f32() {
         test_cmp_f32(
             |i, j| vcge_f32(i, j),
             |a: f32, b: f32| -> u32 { if a == b { 0xFFFFFFFF } else { 0 } },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vceqq_f32() {
+    fn test_vceqq_f32() {
         testq_cmp_f32(
             |i, j| vcgeq_f32(i, j),
             |a: f32, b: f32| -> u32 { if a == b { 0xFFFFFFFF } else { 0 } },
@@ -4242,42 +4327,47 @@ mod tests {
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vcgt_s8() {
+    fn test_vcgt_s8() {
         test_cmp_s8(
             |i, j| vcgt_s8(i, j),
             |a: i8, b: i8| -> u8 { if a > b { 0xFF } else { 0 } },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vcgtq_s8() {
+    fn test_vcgtq_s8() {
         testq_cmp_s8(
             |i, j| vcgtq_s8(i, j),
             |a: i8, b: i8| -> u8 { if a > b { 0xFF } else { 0 } },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vcgt_s16() {
+    fn test_vcgt_s16() {
         test_cmp_s16(
             |i, j| vcgt_s16(i, j),
             |a: i16, b: i16| -> u16 { if a > b { 0xFFFF } else { 0 } },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vcgtq_s16() {
+    fn test_vcgtq_s16() {
         testq_cmp_s16(
             |i, j| vcgtq_s16(i, j),
             |a: i16, b: i16| -> u16 { if a > b { 0xFFFF } else { 0 } },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vcgt_s32() {
+    fn test_vcgt_s32() {
         test_cmp_s32(
             |i, j| vcgt_s32(i, j),
             |a: i32, b: i32| -> u32 { if a > b { 0xFFFFFFFF } else { 0 } },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vcgtq_s32() {
+    fn test_vcgtq_s32() {
         testq_cmp_s32(
             |i, j| vcgtq_s32(i, j),
             |a: i32, b: i32| -> u32 { if a > b { 0xFFFFFFFF } else { 0 } },
@@ -4285,42 +4375,47 @@ mod tests {
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vcgt_u8() {
+    fn test_vcgt_u8() {
         test_cmp_u8(
             |i, j| vcgt_u8(i, j),
             |a: u8, b: u8| -> u8 { if a > b { 0xFF } else { 0 } },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vcgtq_u8() {
+    fn test_vcgtq_u8() {
         testq_cmp_u8(
             |i, j| vcgtq_u8(i, j),
             |a: u8, b: u8| -> u8 { if a > b { 0xFF } else { 0 } },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vcgt_u16() {
+    fn test_vcgt_u16() {
         test_cmp_u16(
             |i, j| vcgt_u16(i, j),
             |a: u16, b: u16| -> u16 { if a > b { 0xFFFF } else { 0 } },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vcgtq_u16() {
+    fn test_vcgtq_u16() {
         testq_cmp_u16(
             |i, j| vcgtq_u16(i, j),
             |a: u16, b: u16| -> u16 { if a > b { 0xFFFF } else { 0 } },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vcgt_u32() {
+    fn test_vcgt_u32() {
         test_cmp_u32(
             |i, j| vcgt_u32(i, j),
             |a: u32, b: u32| -> u32 { if a > b { 0xFFFFFF } else { 0 } },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vcgtq_u32() {
+    fn test_vcgtq_u32() {
         testq_cmp_u32(
             |i, j| vcgtq_u32(i, j),
             |a: u32, b: u32| -> u32 { if a > b { 0xFFFFFFFF } else { 0 } },
@@ -4328,14 +4423,15 @@ mod tests {
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vcgt_f32() {
+    fn test_vcgt_f32() {
         test_cmp_f32(
             |i, j| vcgt_f32(i, j),
             |a: f32, b: f32| -> u32 { if a > b { 0xFFFFFFFF } else { 0 } },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vcgtq_f32() {
+    fn test_vcgtq_f32() {
         testq_cmp_f32(
             |i, j| vcgtq_f32(i, j),
             |a: f32, b: f32| -> u32 { if a > b { 0xFFFFFFFF } else { 0 } },
@@ -4343,42 +4439,47 @@ mod tests {
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vclt_s8() {
+    fn test_vclt_s8() {
         test_cmp_s8(
             |i, j| vclt_s8(i, j),
             |a: i8, b: i8| -> u8 { if a < b { 0xFF } else { 0 } },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vcltq_s8() {
+    fn test_vcltq_s8() {
         testq_cmp_s8(
             |i, j| vcltq_s8(i, j),
             |a: i8, b: i8| -> u8 { if a < b { 0xFF } else { 0 } },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vclt_s16() {
+    fn test_vclt_s16() {
         test_cmp_s16(
             |i, j| vclt_s16(i, j),
             |a: i16, b: i16| -> u16 { if a < b { 0xFFFF } else { 0 } },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vcltq_s16() {
+    fn test_vcltq_s16() {
         testq_cmp_s16(
             |i, j| vcltq_s16(i, j),
             |a: i16, b: i16| -> u16 { if a < b { 0xFFFF } else { 0 } },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vclt_s32() {
+    fn test_vclt_s32() {
         test_cmp_s32(
             |i, j| vclt_s32(i, j),
             |a: i32, b: i32| -> u32 { if a < b { 0xFFFFFFFF } else { 0 } },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vcltq_s32() {
+    fn test_vcltq_s32() {
         testq_cmp_s32(
             |i, j| vcltq_s32(i, j),
             |a: i32, b: i32| -> u32 { if a < b { 0xFFFFFFFF } else { 0 } },
@@ -4386,42 +4487,47 @@ mod tests {
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vclt_u8() {
+    fn test_vclt_u8() {
         test_cmp_u8(
             |i, j| vclt_u8(i, j),
             |a: u8, b: u8| -> u8 { if a < b { 0xFF } else { 0 } },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vcltq_u8() {
+    fn test_vcltq_u8() {
         testq_cmp_u8(
             |i, j| vcltq_u8(i, j),
             |a: u8, b: u8| -> u8 { if a < b { 0xFF } else { 0 } },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vclt_u16() {
+    fn test_vclt_u16() {
         test_cmp_u16(
             |i, j| vclt_u16(i, j),
             |a: u16, b: u16| -> u16 { if a < b { 0xFFFF } else { 0 } },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vcltq_u16() {
+    fn test_vcltq_u16() {
         testq_cmp_u16(
             |i, j| vcltq_u16(i, j),
             |a: u16, b: u16| -> u16 { if a < b { 0xFFFF } else { 0 } },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vclt_u32() {
+    fn test_vclt_u32() {
         test_cmp_u32(
             |i, j| vclt_u32(i, j),
             |a: u32, b: u32| -> u32 { if a < b { 0xFFFFFF } else { 0 } },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vcltq_u32() {
+    fn test_vcltq_u32() {
         testq_cmp_u32(
             |i, j| vcltq_u32(i, j),
             |a: u32, b: u32| -> u32 { if a < b { 0xFFFFFFFF } else { 0 } },
@@ -4429,14 +4535,15 @@ mod tests {
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vclt_f32() {
+    fn test_vclt_f32() {
         test_cmp_f32(
             |i, j| vclt_f32(i, j),
             |a: f32, b: f32| -> u32 { if a < b { 0xFFFFFFFF } else { 0 } },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vcltq_f32() {
+    fn test_vcltq_f32() {
         testq_cmp_f32(
             |i, j| vcltq_f32(i, j),
             |a: f32, b: f32| -> u32 { if a < b { 0xFFFFFFFF } else { 0 } },
@@ -4444,42 +4551,47 @@ mod tests {
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vcle_s8() {
+    fn test_vcle_s8() {
         test_cmp_s8(
             |i, j| vcle_s8(i, j),
             |a: i8, b: i8| -> u8 { if a <= b { 0xFF } else { 0 } },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vcleq_s8() {
+    fn test_vcleq_s8() {
         testq_cmp_s8(
             |i, j| vcleq_s8(i, j),
             |a: i8, b: i8| -> u8 { if a <= b { 0xFF } else { 0 } },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vcle_s16() {
+    fn test_vcle_s16() {
         test_cmp_s16(
             |i, j| vcle_s16(i, j),
             |a: i16, b: i16| -> u16 { if a <= b { 0xFFFF } else { 0 } },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vcleq_s16() {
+    fn test_vcleq_s16() {
         testq_cmp_s16(
             |i, j| vcleq_s16(i, j),
             |a: i16, b: i16| -> u16 { if a <= b { 0xFFFF } else { 0 } },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vcle_s32() {
+    fn test_vcle_s32() {
         test_cmp_s32(
             |i, j| vcle_s32(i, j),
             |a: i32, b: i32| -> u32 { if a <= b { 0xFFFFFFFF } else { 0 } },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vcleq_s32() {
+    fn test_vcleq_s32() {
         testq_cmp_s32(
             |i, j| vcleq_s32(i, j),
             |a: i32, b: i32| -> u32 { if a <= b { 0xFFFFFFFF } else { 0 } },
@@ -4487,42 +4599,47 @@ mod tests {
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vcle_u8() {
+    fn test_vcle_u8() {
         test_cmp_u8(
             |i, j| vcle_u8(i, j),
             |a: u8, b: u8| -> u8 { if a <= b { 0xFF } else { 0 } },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vcleq_u8() {
+    fn test_vcleq_u8() {
         testq_cmp_u8(
             |i, j| vcleq_u8(i, j),
             |a: u8, b: u8| -> u8 { if a <= b { 0xFF } else { 0 } },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vcle_u16() {
+    fn test_vcle_u16() {
         test_cmp_u16(
             |i, j| vcle_u16(i, j),
             |a: u16, b: u16| -> u16 { if a <= b { 0xFFFF } else { 0 } },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vcleq_u16() {
+    fn test_vcleq_u16() {
         testq_cmp_u16(
             |i, j| vcleq_u16(i, j),
             |a: u16, b: u16| -> u16 { if a <= b { 0xFFFF } else { 0 } },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vcle_u32() {
+    fn test_vcle_u32() {
         test_cmp_u32(
             |i, j| vcle_u32(i, j),
             |a: u32, b: u32| -> u32 { if a <= b { 0xFFFFFFFF } else { 0 } },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vcleq_u32() {
+    fn test_vcleq_u32() {
         testq_cmp_u32(
             |i, j| vcleq_u32(i, j),
             |a: u32, b: u32| -> u32 { if a <= b { 0xFFFFFFFF } else { 0 } },
@@ -4530,14 +4647,15 @@ mod tests {
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vcle_f32() {
+    fn test_vcle_f32() {
         test_cmp_f32(
             |i, j| vcle_f32(i, j),
             |a: f32, b: f32| -> u32 { if a <= b { 0xFFFFFFFF } else { 0 } },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vcleq_f32() {
+    fn test_vcleq_f32() {
         testq_cmp_f32(
             |i, j| vcleq_f32(i, j),
             |a: f32, b: f32| -> u32 { if a <= b { 0xFFFFFFFF } else { 0 } },
@@ -4545,42 +4663,47 @@ mod tests {
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vcge_s8() {
+    fn test_vcge_s8() {
         test_cmp_s8(
             |i, j| vcge_s8(i, j),
             |a: i8, b: i8| -> u8 { if a >= b { 0xFF } else { 0 } },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vcgeq_s8() {
+    fn test_vcgeq_s8() {
         testq_cmp_s8(
             |i, j| vcgeq_s8(i, j),
             |a: i8, b: i8| -> u8 { if a >= b { 0xFF } else { 0 } },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vcge_s16() {
+    fn test_vcge_s16() {
         test_cmp_s16(
             |i, j| vcge_s16(i, j),
             |a: i16, b: i16| -> u16 { if a >= b { 0xFFFF } else { 0 } },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vcgeq_s16() {
+    fn test_vcgeq_s16() {
         testq_cmp_s16(
             |i, j| vcgeq_s16(i, j),
             |a: i16, b: i16| -> u16 { if a >= b { 0xFFFF } else { 0 } },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vcge_s32() {
+    fn test_vcge_s32() {
         test_cmp_s32(
             |i, j| vcge_s32(i, j),
             |a: i32, b: i32| -> u32 { if a >= b { 0xFFFFFFFF } else { 0 } },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vcgeq_s32() {
+    fn test_vcgeq_s32() {
         testq_cmp_s32(
             |i, j| vcgeq_s32(i, j),
             |a: i32, b: i32| -> u32 { if a >= b { 0xFFFFFFFF } else { 0 } },
@@ -4588,42 +4711,45 @@ mod tests {
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vcge_u8() {
+    fn test_vcge_u8() {
         test_cmp_u8(
             |i, j| vcge_u8(i, j),
             |a: u8, b: u8| -> u8 { if a >= b { 0xFF } else { 0 } },
         );
     }
     #[simd_test(enable = "neon")]
-    unsafe fn test_vcgeq_u8() {
+    fn test_vcgeq_u8() {
         testq_cmp_u8(
             |i, j| vcgeq_u8(i, j),
             |a: u8, b: u8| -> u8 { if a >= b { 0xFF } else { 0 } },
         );
     }
     #[simd_test(enable = "neon")]
-    unsafe fn test_vcge_u16() {
+    fn test_vcge_u16() {
         test_cmp_u16(
             |i, j| vcge_u16(i, j),
             |a: u16, b: u16| -> u16 { if a >= b { 0xFFFF } else { 0 } },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vcgeq_u16() {
+    fn test_vcgeq_u16() {
         testq_cmp_u16(
             |i, j| vcgeq_u16(i, j),
             |a: u16, b: u16| -> u16 { if a >= b { 0xFFFF } else { 0 } },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vcge_u32() {
+    fn test_vcge_u32() {
         test_cmp_u32(
             |i, j| vcge_u32(i, j),
             |a: u32, b: u32| -> u32 { if a >= b { 0xFFFFFFFF } else { 0 } },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vcgeq_u32() {
+    fn test_vcgeq_u32() {
         testq_cmp_u32(
             |i, j| vcgeq_u32(i, j),
             |a: u32, b: u32| -> u32 { if a >= b { 0xFFFFFFFF } else { 0 } },
@@ -4631,14 +4757,14 @@ mod tests {
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vcge_f32() {
+    fn test_vcge_f32() {
         test_cmp_f32(
             |i, j| vcge_f32(i, j),
             |a: f32, b: f32| -> u32 { if a >= b { 0xFFFFFFFF } else { 0 } },
         );
     }
     #[simd_test(enable = "neon")]
-    unsafe fn test_vcgeq_f32() {
+    fn test_vcgeq_f32() {
         testq_cmp_f32(
             |i, j| vcgeq_f32(i, j),
             |a: f32, b: f32| -> u32 { if a >= b { 0xFFFFFFFF } else { 0 } },
@@ -4646,42 +4772,47 @@ mod tests {
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vqsub_s8() {
+    fn test_vqsub_s8() {
         test_ari_s8(
             |i, j| vqsub_s8(i, j),
             |a: i8, b: i8| -> i8 { a.saturating_sub(b) },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vqsubq_s8() {
+    fn test_vqsubq_s8() {
         testq_ari_s8(
             |i, j| vqsubq_s8(i, j),
             |a: i8, b: i8| -> i8 { a.saturating_sub(b) },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vqsub_s16() {
+    fn test_vqsub_s16() {
         test_ari_s16(
             |i, j| vqsub_s16(i, j),
             |a: i16, b: i16| -> i16 { a.saturating_sub(b) },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vqsubq_s16() {
+    fn test_vqsubq_s16() {
         testq_ari_s16(
             |i, j| vqsubq_s16(i, j),
             |a: i16, b: i16| -> i16 { a.saturating_sub(b) },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vqsub_s32() {
+    fn test_vqsub_s32() {
         test_ari_s32(
             |i, j| vqsub_s32(i, j),
             |a: i32, b: i32| -> i32 { a.saturating_sub(b) },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vqsubq_s32() {
+    fn test_vqsubq_s32() {
         testq_ari_s32(
             |i, j| vqsubq_s32(i, j),
             |a: i32, b: i32| -> i32 { a.saturating_sub(b) },
@@ -4689,42 +4820,47 @@ mod tests {
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vqsub_u8() {
+    fn test_vqsub_u8() {
         test_ari_u8(
             |i, j| vqsub_u8(i, j),
             |a: u8, b: u8| -> u8 { a.saturating_sub(b) },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vqsubq_u8() {
+    fn test_vqsubq_u8() {
         testq_ari_u8(
             |i, j| vqsubq_u8(i, j),
             |a: u8, b: u8| -> u8 { a.saturating_sub(b) },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vqsub_u16() {
+    fn test_vqsub_u16() {
         test_ari_u16(
             |i, j| vqsub_u16(i, j),
             |a: u16, b: u16| -> u16 { a.saturating_sub(b) },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vqsubq_u16() {
+    fn test_vqsubq_u16() {
         testq_ari_u16(
             |i, j| vqsubq_u16(i, j),
             |a: u16, b: u16| -> u16 { a.saturating_sub(b) },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vqsub_u32() {
+    fn test_vqsub_u32() {
         test_ari_u32(
             |i, j| vqsub_u32(i, j),
             |a: u32, b: u32| -> u32 { a.saturating_sub(b) },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vqsubq_u32() {
+    fn test_vqsubq_u32() {
         testq_ari_u32(
             |i, j| vqsubq_u32(i, j),
             |a: u32, b: u32| -> u32 { a.saturating_sub(b) },
@@ -4732,142 +4868,166 @@ mod tests {
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vhadd_s8() {
+    fn test_vhadd_s8() {
         test_ari_s8(|i, j| vhadd_s8(i, j), |a: i8, b: i8| -> i8 { a & b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vhaddq_s8() {
+    fn test_vhaddq_s8() {
         testq_ari_s8(|i, j| vhaddq_s8(i, j), |a: i8, b: i8| -> i8 { a & b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vhadd_s16() {
+    fn test_vhadd_s16() {
         test_ari_s16(|i, j| vhadd_s16(i, j), |a: i16, b: i16| -> i16 { a & b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vhaddq_s16() {
+    fn test_vhaddq_s16() {
         testq_ari_s16(|i, j| vhaddq_s16(i, j), |a: i16, b: i16| -> i16 { a & b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vhadd_s32() {
+    fn test_vhadd_s32() {
         test_ari_s32(|i, j| vhadd_s32(i, j), |a: i32, b: i32| -> i32 { a & b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vhaddq_s32() {
+    fn test_vhaddq_s32() {
         testq_ari_s32(|i, j| vhaddq_s32(i, j), |a: i32, b: i32| -> i32 { a & b });
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vhadd_u8() {
+    fn test_vhadd_u8() {
         test_ari_u8(|i, j| vhadd_u8(i, j), |a: u8, b: u8| -> u8 { a & b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vhaddq_u8() {
+    fn test_vhaddq_u8() {
         testq_ari_u8(|i, j| vhaddq_u8(i, j), |a: u8, b: u8| -> u8 { a & b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vhadd_u16() {
+    fn test_vhadd_u16() {
         test_ari_u16(|i, j| vhadd_u16(i, j), |a: u16, b: u16| -> u16 { a & b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vhaddq_u16() {
+    fn test_vhaddq_u16() {
         testq_ari_u16(|i, j| vhaddq_u16(i, j), |a: u16, b: u16| -> u16 { a & b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vhadd_u32() {
+    fn test_vhadd_u32() {
         test_ari_u32(|i, j| vhadd_u32(i, j), |a: u32, b: u32| -> u32 { a & b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vhaddq_u32() {
+    fn test_vhaddq_u32() {
         testq_ari_u32(|i, j| vhaddq_u32(i, j), |a: u32, b: u32| -> u32 { a & b });
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vrhadd_s8() {
+    fn test_vrhadd_s8() {
         test_ari_s8(|i, j| vrhadd_s8(i, j), |a: i8, b: i8| -> i8 { a & b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vrhaddq_s8() {
+    fn test_vrhaddq_s8() {
         testq_ari_s8(|i, j| vrhaddq_s8(i, j), |a: i8, b: i8| -> i8 { a & b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vrhadd_s16() {
+    fn test_vrhadd_s16() {
         test_ari_s16(|i, j| vrhadd_s16(i, j), |a: i16, b: i16| -> i16 { a & b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vrhaddq_s16() {
+    fn test_vrhaddq_s16() {
         testq_ari_s16(|i, j| vrhaddq_s16(i, j), |a: i16, b: i16| -> i16 { a & b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vrhadd_s32() {
+    fn test_vrhadd_s32() {
         test_ari_s32(|i, j| vrhadd_s32(i, j), |a: i32, b: i32| -> i32 { a & b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vrhaddq_s32() {
+    fn test_vrhaddq_s32() {
         testq_ari_s32(|i, j| vrhaddq_s32(i, j), |a: i32, b: i32| -> i32 { a & b });
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vrhadd_u8() {
+    fn test_vrhadd_u8() {
         test_ari_u8(|i, j| vrhadd_u8(i, j), |a: u8, b: u8| -> u8 { a & b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vrhaddq_u8() {
+    fn test_vrhaddq_u8() {
         testq_ari_u8(|i, j| vrhaddq_u8(i, j), |a: u8, b: u8| -> u8 { a & b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vrhadd_u16() {
+    fn test_vrhadd_u16() {
         test_ari_u16(|i, j| vrhadd_u16(i, j), |a: u16, b: u16| -> u16 { a & b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vrhaddq_u16() {
+    fn test_vrhaddq_u16() {
         testq_ari_u16(|i, j| vrhaddq_u16(i, j), |a: u16, b: u16| -> u16 { a & b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vrhadd_u32() {
+    fn test_vrhadd_u32() {
         test_ari_u32(|i, j| vrhadd_u32(i, j), |a: u32, b: u32| -> u32 { a & b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vrhaddq_u32() {
+    fn test_vrhaddq_u32() {
         testq_ari_u32(|i, j| vrhaddq_u32(i, j), |a: u32, b: u32| -> u32 { a & b });
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vqadd_s8() {
+    fn test_vqadd_s8() {
         test_ari_s8(
             |i, j| vqadd_s8(i, j),
             |a: i8, b: i8| -> i8 { a.saturating_add(b) },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vqaddq_s8() {
+    fn test_vqaddq_s8() {
         testq_ari_s8(
             |i, j| vqaddq_s8(i, j),
             |a: i8, b: i8| -> i8 { a.saturating_add(b) },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vqadd_s16() {
+    fn test_vqadd_s16() {
         test_ari_s16(
             |i, j| vqadd_s16(i, j),
             |a: i16, b: i16| -> i16 { a.saturating_add(b) },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vqaddq_s16() {
+    fn test_vqaddq_s16() {
         testq_ari_s16(
             |i, j| vqaddq_s16(i, j),
             |a: i16, b: i16| -> i16 { a.saturating_add(b) },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vqadd_s32() {
+    fn test_vqadd_s32() {
         test_ari_s32(
             |i, j| vqadd_s32(i, j),
             |a: i32, b: i32| -> i32 { a.saturating_add(b) },
         );
     }
     #[simd_test(enable = "neon")]
-    unsafe fn test_vqaddq_s32() {
+    fn test_vqaddq_s32() {
         testq_ari_s32(
             |i, j| vqaddq_s32(i, j),
             |a: i32, b: i32| -> i32 { a.saturating_add(b) },
@@ -4875,42 +5035,47 @@ mod tests {
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vqadd_u8() {
+    fn test_vqadd_u8() {
         test_ari_u8(
             |i, j| vqadd_u8(i, j),
             |a: u8, b: u8| -> u8 { a.saturating_add(b) },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vqaddq_u8() {
+    fn test_vqaddq_u8() {
         testq_ari_u8(
             |i, j| vqaddq_u8(i, j),
             |a: u8, b: u8| -> u8 { a.saturating_add(b) },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vqadd_u16() {
+    fn test_vqadd_u16() {
         test_ari_u16(
             |i, j| vqadd_u16(i, j),
             |a: u16, b: u16| -> u16 { a.saturating_add(b) },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vqaddq_u16() {
+    fn test_vqaddq_u16() {
         testq_ari_u16(
             |i, j| vqaddq_u16(i, j),
             |a: u16, b: u16| -> u16 { a.saturating_add(b) },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vqadd_u32() {
+    fn test_vqadd_u32() {
         test_ari_u32(
             |i, j| vqadd_u32(i, j),
             |a: u32, b: u32| -> u32 { a.saturating_add(b) },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vqaddq_u32() {
+    fn test_vqaddq_u32() {
         testq_ari_u32(
             |i, j| vqaddq_u32(i, j),
             |a: u32, b: u32| -> u32 { a.saturating_add(b) },
@@ -4918,42 +5083,47 @@ mod tests {
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmul_s8() {
+    fn test_vmul_s8() {
         test_ari_s8(
             |i, j| vmul_s8(i, j),
             |a: i8, b: i8| -> i8 { a.overflowing_mul(b).0 },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmulq_s8() {
+    fn test_vmulq_s8() {
         testq_ari_s8(
             |i, j| vmulq_s8(i, j),
             |a: i8, b: i8| -> i8 { a.overflowing_mul(b).0 },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmul_s16() {
+    fn test_vmul_s16() {
         test_ari_s16(
             |i, j| vmul_s16(i, j),
             |a: i16, b: i16| -> i16 { a.overflowing_mul(b).0 },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmulq_s16() {
+    fn test_vmulq_s16() {
         testq_ari_s16(
             |i, j| vmulq_s16(i, j),
             |a: i16, b: i16| -> i16 { a.overflowing_mul(b).0 },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmul_s32() {
+    fn test_vmul_s32() {
         test_ari_s32(
             |i, j| vmul_s32(i, j),
             |a: i32, b: i32| -> i32 { a.overflowing_mul(b).0 },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmulq_s32() {
+    fn test_vmulq_s32() {
         testq_ari_s32(
             |i, j| vmulq_s32(i, j),
             |a: i32, b: i32| -> i32 { a.overflowing_mul(b).0 },
@@ -4961,42 +5131,47 @@ mod tests {
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmul_u8() {
+    fn test_vmul_u8() {
         test_ari_u8(
             |i, j| vmul_u8(i, j),
             |a: u8, b: u8| -> u8 { a.overflowing_mul(b).0 },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmulq_u8() {
+    fn test_vmulq_u8() {
         testq_ari_u8(
             |i, j| vmulq_u8(i, j),
             |a: u8, b: u8| -> u8 { a.overflowing_mul(b).0 },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmul_u16() {
+    fn test_vmul_u16() {
         test_ari_u16(
             |i, j| vmul_u16(i, j),
             |a: u16, b: u16| -> u16 { a.overflowing_mul(b).0 },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmulq_u16() {
+    fn test_vmulq_u16() {
         testq_ari_u16(
             |i, j| vmulq_u16(i, j),
             |a: u16, b: u16| -> u16 { a.overflowing_mul(b).0 },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmul_u32() {
+    fn test_vmul_u32() {
         test_ari_u32(
             |i, j| vmul_u32(i, j),
             |a: u32, b: u32| -> u32 { a.overflowing_mul(b).0 },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmulq_u32() {
+    fn test_vmulq_u32() {
         testq_ari_u32(
             |i, j| vmulq_u32(i, j),
             |a: u32, b: u32| -> u32 { a.overflowing_mul(b).0 },
@@ -5004,110 +5179,127 @@ mod tests {
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmul_f32() {
+    fn test_vmul_f32() {
         test_ari_f32(|i, j| vmul_f32(i, j), |a: f32, b: f32| -> f32 { a * b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vmulq_f32() {
+    fn test_vmulq_f32() {
         testq_ari_f32(|i, j| vmulq_f32(i, j), |a: f32, b: f32| -> f32 { a * b });
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vsub_s8() {
+    fn test_vsub_s8() {
         test_ari_s8(|i, j| vsub_s8(i, j), |a: i8, b: i8| -> i8 { a - b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vsubq_s8() {
+    fn test_vsubq_s8() {
         testq_ari_s8(|i, j| vsubq_s8(i, j), |a: i8, b: i8| -> i8 { a - b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vsub_s16() {
+    fn test_vsub_s16() {
         test_ari_s16(|i, j| vsub_s16(i, j), |a: i16, b: i16| -> i16 { a - b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vsubq_s16() {
+    fn test_vsubq_s16() {
         testq_ari_s16(|i, j| vsubq_s16(i, j), |a: i16, b: i16| -> i16 { a - b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vsub_s32() {
+    fn test_vsub_s32() {
         test_ari_s32(|i, j| vsub_s32(i, j), |a: i32, b: i32| -> i32 { a - b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vsubq_s32() {
+    fn test_vsubq_s32() {
         testq_ari_s32(|i, j| vsubq_s32(i, j), |a: i32, b: i32| -> i32 { a - b });
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vsub_u8() {
+    fn test_vsub_u8() {
         test_ari_u8(|i, j| vsub_u8(i, j), |a: u8, b: u8| -> u8 { a - b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vsubq_u8() {
+    fn test_vsubq_u8() {
         testq_ari_u8(|i, j| vsubq_u8(i, j), |a: u8, b: u8| -> u8 { a - b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vsub_u16() {
+    fn test_vsub_u16() {
         test_ari_u16(|i, j| vsub_u16(i, j), |a: u16, b: u16| -> u16 { a - b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vsubq_u16() {
+    fn test_vsubq_u16() {
         testq_ari_u16(|i, j| vsubq_u16(i, j), |a: u16, b: u16| -> u16 { a - b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vsub_u32() {
+    fn test_vsub_u32() {
         test_ari_u32(|i, j| vsub_u32(i, j), |a: u32, b: u32| -> u32 { a - b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vsubq_u32() {
+    fn test_vsubq_u32() {
         testq_ari_u32(|i, j| vsubq_u32(i, j), |a: u32, b: u32| -> u32 { a - b });
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vsub_f32() {
+    fn test_vsub_f32() {
         test_ari_f32(|i, j| vsub_f32(i, j), |a: f32, b: f32| -> f32 { a - b });
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vsubq_f32() {
+    fn test_vsubq_f32() {
         testq_ari_f32(|i, j| vsubq_f32(i, j), |a: f32, b: f32| -> f32 { a - b });
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vhsub_s8() {
+    fn test_vhsub_s8() {
         test_ari_s8(
             |i, j| vhsub_s8(i, j),
             |a: i8, b: i8| -> i8 { (((a as i16) - (b as i16)) / 2) as i8 },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vhsubq_s8() {
+    fn test_vhsubq_s8() {
         testq_ari_s8(
             |i, j| vhsubq_s8(i, j),
             |a: i8, b: i8| -> i8 { (((a as i16) - (b as i16)) / 2) as i8 },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vhsub_s16() {
+    fn test_vhsub_s16() {
         test_ari_s16(
             |i, j| vhsub_s16(i, j),
             |a: i16, b: i16| -> i16 { (((a as i32) - (b as i32)) / 2) as i16 },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vhsubq_s16() {
+    fn test_vhsubq_s16() {
         testq_ari_s16(
             |i, j| vhsubq_s16(i, j),
             |a: i16, b: i16| -> i16 { (((a as i32) - (b as i32)) / 2) as i16 },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vhsub_s32() {
+    fn test_vhsub_s32() {
         test_ari_s32(
             |i, j| vhsub_s32(i, j),
             |a: i32, b: i32| -> i32 { (((a as i64) - (b as i64)) / 2) as i32 },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vhsubq_s32() {
+    fn test_vhsubq_s32() {
         testq_ari_s32(
             |i, j| vhsubq_s32(i, j),
             |a: i32, b: i32| -> i32 { (((a as i64) - (b as i64)) / 2) as i32 },
@@ -5115,42 +5307,47 @@ mod tests {
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vhsub_u8() {
+    fn test_vhsub_u8() {
         test_ari_u8(
             |i, j| vhsub_u8(i, j),
             |a: u8, b: u8| -> u8 { (((a as u16) - (b as u16)) / 2) as u8 },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vhsubq_u8() {
+    fn test_vhsubq_u8() {
         testq_ari_u8(
             |i, j| vhsubq_u8(i, j),
             |a: u8, b: u8| -> u8 { (((a as u16) - (b as u16)) / 2) as u8 },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vhsub_u16() {
+    fn test_vhsub_u16() {
         test_ari_u16(
             |i, j| vhsub_u16(i, j),
             |a: u16, b: u16| -> u16 { (((a as u16) - (b as u16)) / 2) as u16 },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vhsubq_u16() {
+    fn test_vhsubq_u16() {
         testq_ari_u16(
             |i, j| vhsubq_u16(i, j),
             |a: u16, b: u16| -> u16 { (((a as u16) - (b as u16)) / 2) as u16 },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vhsub_u32() {
+    fn test_vhsub_u32() {
         test_ari_u32(
             |i, j| vhsub_u32(i, j),
             |a: u32, b: u32| -> u32 { (((a as u64) - (b as u64)) / 2) as u32 },
         );
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vhsubq_u32() {
+    fn test_vhsubq_u32() {
         testq_ari_u32(
             |i, j| vhsubq_u32(i, j),
             |a: u32, b: u32| -> u32 { (((a as u64) - (b as u64)) / 2) as u32 },
@@ -5158,368 +5355,414 @@ mod tests {
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vaba_s8() {
+    fn test_vaba_s8() {
         let a = i8x8::new(1, 2, 3, 4, 5, 6, 7, 8);
         let b = i8x8::new(1, 1, 1, 1, 1, 1, 1, 1);
         let c = i8x8::new(10, 9, 8, 7, 6, 5, 4, 3);
-        let r: i8x8 = transmute(vaba_s8(transmute(a), transmute(b), transmute(c)));
+        let r = i8x8::from(vaba_s8(a.into(), b.into(), c.into()));
         let e = i8x8::new(10, 10, 10, 10, 10, 10, 10, 10);
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vaba_s16() {
+    fn test_vaba_s16() {
         let a = i16x4::new(1, 2, 3, 4);
         let b = i16x4::new(1, 1, 1, 1);
         let c = i16x4::new(10, 9, 8, 7);
-        let r: i16x4 = transmute(vaba_s16(transmute(a), transmute(b), transmute(c)));
+        let r = i16x4::from(vaba_s16(a.into(), b.into(), c.into()));
         let e = i16x4::new(10, 10, 10, 10);
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vaba_s32() {
+    fn test_vaba_s32() {
         let a = i32x2::new(1, 2);
         let b = i32x2::new(1, 1);
         let c = i32x2::new(10, 9);
-        let r: i32x2 = transmute(vaba_s32(transmute(a), transmute(b), transmute(c)));
+        let r = i32x2::from(vaba_s32(a.into(), b.into(), c.into()));
         let e = i32x2::new(10, 10);
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vaba_u8() {
+    fn test_vaba_u8() {
         let a = u8x8::new(1, 2, 3, 4, 5, 6, 7, 8);
         let b = u8x8::new(1, 1, 1, 1, 1, 1, 1, 1);
         let c = u8x8::new(10, 9, 8, 7, 6, 5, 4, 3);
-        let r: u8x8 = transmute(vaba_u8(transmute(a), transmute(b), transmute(c)));
+        let r = u8x8::from(vaba_u8(a.into(), b.into(), c.into()));
         let e = u8x8::new(10, 10, 10, 10, 10, 10, 10, 10);
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vaba_u16() {
+    fn test_vaba_u16() {
         let a = u16x4::new(1, 2, 3, 4);
         let b = u16x4::new(1, 1, 1, 1);
         let c = u16x4::new(10, 9, 8, 7);
-        let r: u16x4 = transmute(vaba_u16(transmute(a), transmute(b), transmute(c)));
+        let r = u16x4::from(vaba_u16(a.into(), b.into(), c.into()));
         let e = u16x4::new(10, 10, 10, 10);
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vaba_u32() {
+    fn test_vaba_u32() {
         let a = u32x2::new(1, 2);
         let b = u32x2::new(1, 1);
         let c = u32x2::new(10, 9);
-        let r: u32x2 = transmute(vaba_u32(transmute(a), transmute(b), transmute(c)));
+        let r = u32x2::from(vaba_u32(a.into(), b.into(), c.into()));
         let e = u32x2::new(10, 10);
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vabaq_s8() {
+    fn test_vabaq_s8() {
         let a = i8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 8, 7, 6, 5, 4, 3, 2);
         let b = i8x16::new(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
         let c = i8x16::new(10, 9, 8, 7, 6, 5, 4, 3, 12, 13, 14, 15, 16, 17, 18, 19);
-        let r: i8x16 = transmute(vabaq_s8(transmute(a), transmute(b), transmute(c)));
+        let r = i8x16::from(vabaq_s8(a.into(), b.into(), c.into()));
         let e = i8x16::new(
             10, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 20, 20, 20,
         );
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vabaq_s16() {
+    fn test_vabaq_s16() {
         let a = i16x8::new(1, 2, 3, 4, 5, 6, 7, 8);
         let b = i16x8::new(1, 1, 1, 1, 1, 1, 1, 1);
         let c = i16x8::new(10, 9, 8, 7, 6, 5, 4, 3);
-        let r: i16x8 = transmute(vabaq_s16(transmute(a), transmute(b), transmute(c)));
+        let r = i16x8::from(vabaq_s16(a.into(), b.into(), c.into()));
         let e = i16x8::new(10, 10, 10, 10, 10, 10, 10, 10);
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vabaq_s32() {
+    fn test_vabaq_s32() {
         let a = i32x4::new(1, 2, 3, 4);
         let b = i32x4::new(1, 1, 1, 1);
         let c = i32x4::new(10, 9, 8, 7);
-        let r: i32x4 = transmute(vabaq_s32(transmute(a), transmute(b), transmute(c)));
+        let r = i32x4::from(vabaq_s32(a.into(), b.into(), c.into()));
         let e = i32x4::new(10, 10, 10, 10);
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vabaq_u8() {
+    fn test_vabaq_u8() {
         let a = u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 8, 7, 6, 5, 4, 3, 2);
         let b = u8x16::new(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
         let c = u8x16::new(10, 9, 8, 7, 6, 5, 4, 3, 12, 13, 14, 15, 16, 17, 18, 19);
-        let r: u8x16 = transmute(vabaq_u8(transmute(a), transmute(b), transmute(c)));
+        let r = u8x16::from(vabaq_u8(a.into(), b.into(), c.into()));
         let e = u8x16::new(
             10, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 20, 20, 20,
         );
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vabaq_u16() {
+    fn test_vabaq_u16() {
         let a = u16x8::new(1, 2, 3, 4, 5, 6, 7, 8);
         let b = u16x8::new(1, 1, 1, 1, 1, 1, 1, 1);
         let c = u16x8::new(10, 9, 8, 7, 6, 5, 4, 3);
-        let r: u16x8 = transmute(vabaq_u16(transmute(a), transmute(b), transmute(c)));
+        let r = u16x8::from(vabaq_u16(a.into(), b.into(), c.into()));
         let e = u16x8::new(10, 10, 10, 10, 10, 10, 10, 10);
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vabaq_u32() {
+    fn test_vabaq_u32() {
         let a = u32x4::new(1, 2, 3, 4);
         let b = u32x4::new(1, 1, 1, 1);
         let c = u32x4::new(10, 9, 8, 7);
-        let r: u32x4 = transmute(vabaq_u32(transmute(a), transmute(b), transmute(c)));
+        let r = u32x4::from(vabaq_u32(a.into(), b.into(), c.into()));
         let e = u32x4::new(10, 10, 10, 10);
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "neon")]
-    unsafe fn test_vrev16_s8() {
+    fn test_vrev16_s8() {
         let a = i8x8::new(0, 1, 2, 3, 4, 5, 6, 7);
         let r = i8x8::new(1, 0, 3, 2, 5, 4, 7, 6);
-        let e: i8x8 = transmute(vrev16_s8(transmute(a)));
+        let e = i8x8::from(vrev16_s8(a.into()));
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vrev16q_s8() {
+    fn test_vrev16q_s8() {
         let a = i8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let r = i8x16::new(1, 0, 3, 2, 5, 4, 7, 6, 9, 8, 11, 10, 13, 12, 15, 14);
-        let e: i8x16 = transmute(vrev16q_s8(transmute(a)));
+        let e = i8x16::from(vrev16q_s8(a.into()));
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vrev16_u8() {
+    fn test_vrev16_u8() {
         let a = u8x8::new(0, 1, 2, 3, 4, 5, 6, 7);
         let r = u8x8::new(1, 0, 3, 2, 5, 4, 7, 6);
-        let e: u8x8 = transmute(vrev16_u8(transmute(a)));
+        let e = u8x8::from(vrev16_u8(a.into()));
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vrev16q_u8() {
+    fn test_vrev16q_u8() {
         let a = u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let r = u8x16::new(1, 0, 3, 2, 5, 4, 7, 6, 9, 8, 11, 10, 13, 12, 15, 14);
-        let e: u8x16 = transmute(vrev16q_u8(transmute(a)));
+        let e = u8x16::from(vrev16q_u8(a.into()));
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vrev16_p8() {
-        let a = i8x8::new(0, 1, 2, 3, 4, 5, 6, 7);
-        let r = i8x8::new(1, 0, 3, 2, 5, 4, 7, 6);
-        let e: i8x8 = transmute(vrev16_p8(transmute(a)));
+    fn test_vrev16_p8() {
+        let a = u8x8::new(0, 1, 2, 3, 4, 5, 6, 7);
+        let r = u8x8::new(1, 0, 3, 2, 5, 4, 7, 6);
+        let e = u8x8::from(vrev16_p8(a.into()));
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vrev16q_p8() {
+    fn test_vrev16q_p8() {
         let a = u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let r = u8x16::new(1, 0, 3, 2, 5, 4, 7, 6, 9, 8, 11, 10, 13, 12, 15, 14);
-        let e: u8x16 = transmute(vrev16q_p8(transmute(a)));
+        let e = u8x16::from(vrev16q_p8(a.into()));
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vrev32_s8() {
+    fn test_vrev32_s8() {
         let a = i8x8::new(0, 1, 2, 3, 4, 5, 6, 7);
         let r = i8x8::new(3, 2, 1, 0, 7, 6, 5, 4);
-        let e: i8x8 = transmute(vrev32_s8(transmute(a)));
+        let e = i8x8::from(vrev32_s8(a.into()));
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vrev32q_s8() {
+    fn test_vrev32q_s8() {
         let a = i8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let r = i8x16::new(3, 2, 1, 0, 7, 6, 5, 4, 11, 10, 9, 8, 15, 14, 13, 12);
-        let e: i8x16 = transmute(vrev32q_s8(transmute(a)));
+        let e = i8x16::from(vrev32q_s8(a.into()));
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vrev32_u8() {
+    fn test_vrev32_u8() {
         let a = u8x8::new(0, 1, 2, 3, 4, 5, 6, 7);
         let r = u8x8::new(3, 2, 1, 0, 7, 6, 5, 4);
-        let e: u8x8 = transmute(vrev32_u8(transmute(a)));
+        let e = u8x8::from(vrev32_u8(a.into()));
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vrev32q_u8() {
+    fn test_vrev32q_u8() {
         let a = u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let r = u8x16::new(3, 2, 1, 0, 7, 6, 5, 4, 11, 10, 9, 8, 15, 14, 13, 12);
-        let e: u8x16 = transmute(vrev32q_u8(transmute(a)));
+        let e = u8x16::from(vrev32q_u8(a.into()));
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vrev32_s16() {
+    fn test_vrev32_s16() {
         let a = i16x4::new(0, 1, 2, 3);
         let r = i16x4::new(1, 0, 3, 2);
-        let e: i16x4 = transmute(vrev32_s16(transmute(a)));
+        let e = i16x4::from(vrev32_s16(a.into()));
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vrev32q_s16() {
+    fn test_vrev32q_s16() {
         let a = i16x8::new(0, 1, 2, 3, 4, 5, 6, 7);
         let r = i16x8::new(1, 0, 3, 2, 5, 4, 7, 6);
-        let e: i16x8 = transmute(vrev32q_s16(transmute(a)));
+        let e = i16x8::from(vrev32q_s16(a.into()));
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vrev32_p16() {
-        let a = i16x4::new(0, 1, 2, 3);
-        let r = i16x4::new(1, 0, 3, 2);
-        let e: i16x4 = transmute(vrev32_p16(transmute(a)));
-        assert_eq!(r, e);
-    }
-    #[simd_test(enable = "neon")]
-    unsafe fn test_vrev32q_p16() {
-        let a = i16x8::new(0, 1, 2, 3, 4, 5, 6, 7);
-        let r = i16x8::new(1, 0, 3, 2, 5, 4, 7, 6);
-        let e: i16x8 = transmute(vrev32q_p16(transmute(a)));
-        assert_eq!(r, e);
-    }
-    #[simd_test(enable = "neon")]
-    unsafe fn test_vrev32_u16() {
+    fn test_vrev32_p16() {
         let a = u16x4::new(0, 1, 2, 3);
         let r = u16x4::new(1, 0, 3, 2);
-        let e: u16x4 = transmute(vrev32_u16(transmute(a)));
+        let e = u16x4::from(vrev32_p16(a.into()));
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vrev32q_u16() {
+    fn test_vrev32q_p16() {
         let a = u16x8::new(0, 1, 2, 3, 4, 5, 6, 7);
         let r = u16x8::new(1, 0, 3, 2, 5, 4, 7, 6);
-        let e: u16x8 = transmute(vrev32q_u16(transmute(a)));
+        let e = u16x8::from(vrev32q_p16(a.into()));
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vrev32_p8() {
+    fn test_vrev32_u16() {
+        let a = u16x4::new(0, 1, 2, 3);
+        let r = u16x4::new(1, 0, 3, 2);
+        let e = u16x4::from(vrev32_u16(a.into()));
+        assert_eq!(r, e);
+    }
+
+    #[simd_test(enable = "neon")]
+    fn test_vrev32q_u16() {
+        let a = u16x8::new(0, 1, 2, 3, 4, 5, 6, 7);
+        let r = u16x8::new(1, 0, 3, 2, 5, 4, 7, 6);
+        let e = u16x8::from(vrev32q_u16(a.into()));
+        assert_eq!(r, e);
+    }
+
+    #[simd_test(enable = "neon")]
+    fn test_vrev32_p8() {
         let a = u8x8::new(0, 1, 2, 3, 4, 5, 6, 7);
         let r = u8x8::new(3, 2, 1, 0, 7, 6, 5, 4);
-        let e: u8x8 = transmute(vrev32_p8(transmute(a)));
+        let e = u8x8::from(vrev32_p8(a.into()));
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vrev32q_p8() {
+    fn test_vrev32q_p8() {
         let a = u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let r = u8x16::new(3, 2, 1, 0, 7, 6, 5, 4, 11, 10, 9, 8, 15, 14, 13, 12);
-        let e: u8x16 = transmute(vrev32q_p8(transmute(a)));
+        let e = u8x16::from(vrev32q_p8(a.into()));
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vrev64_s8() {
+    fn test_vrev64_s8() {
         let a = i8x8::new(0, 1, 2, 3, 4, 5, 6, 7);
         let r = i8x8::new(7, 6, 5, 4, 3, 2, 1, 0);
-        let e: i8x8 = transmute(vrev64_s8(transmute(a)));
+        let e = i8x8::from(vrev64_s8(a.into()));
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vrev64q_s8() {
+    fn test_vrev64q_s8() {
         let a = i8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let r = i8x16::new(7, 6, 5, 4, 3, 2, 1, 0, 15, 14, 13, 12, 11, 10, 9, 8);
-        let e: i8x16 = transmute(vrev64q_s8(transmute(a)));
+        let e = i8x16::from(vrev64q_s8(a.into()));
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vrev64_s16() {
+    fn test_vrev64_s16() {
         let a = i16x4::new(0, 1, 2, 3);
         let r = i16x4::new(3, 2, 1, 0);
-        let e: i16x4 = transmute(vrev64_s16(transmute(a)));
+        let e = i16x4::from(vrev64_s16(a.into()));
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vrev64q_s16() {
+    fn test_vrev64q_s16() {
         let a = i16x8::new(0, 1, 2, 3, 4, 5, 6, 7);
         let r = i16x8::new(3, 2, 1, 0, 7, 6, 5, 4);
-        let e: i16x8 = transmute(vrev64q_s16(transmute(a)));
+        let e = i16x8::from(vrev64q_s16(a.into()));
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vrev64_s32() {
+    fn test_vrev64_s32() {
         let a = i32x2::new(0, 1);
         let r = i32x2::new(1, 0);
-        let e: i32x2 = transmute(vrev64_s32(transmute(a)));
+        let e = i32x2::from(vrev64_s32(a.into()));
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vrev64q_s32() {
+    fn test_vrev64q_s32() {
         let a = i32x4::new(0, 1, 2, 3);
         let r = i32x4::new(1, 0, 3, 2);
-        let e: i32x4 = transmute(vrev64q_s32(transmute(a)));
+        let e = i32x4::from(vrev64q_s32(a.into()));
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vrev64_u8() {
+    fn test_vrev64_u8() {
         let a = u8x8::new(0, 1, 2, 3, 4, 5, 6, 7);
         let r = u8x8::new(7, 6, 5, 4, 3, 2, 1, 0);
-        let e: u8x8 = transmute(vrev64_u8(transmute(a)));
+        let e = u8x8::from(vrev64_u8(a.into()));
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vrev64q_u8() {
+    fn test_vrev64q_u8() {
         let a = u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let r = u8x16::new(7, 6, 5, 4, 3, 2, 1, 0, 15, 14, 13, 12, 11, 10, 9, 8);
-        let e: u8x16 = transmute(vrev64q_u8(transmute(a)));
+        let e = u8x16::from(vrev64q_u8(a.into()));
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vrev64_u16() {
+    fn test_vrev64_u16() {
         let a = u16x4::new(0, 1, 2, 3);
         let r = u16x4::new(3, 2, 1, 0);
-        let e: u16x4 = transmute(vrev64_u16(transmute(a)));
+        let e = u16x4::from(vrev64_u16(a.into()));
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vrev64q_u16() {
+    fn test_vrev64q_u16() {
         let a = u16x8::new(0, 1, 2, 3, 4, 5, 6, 7);
         let r = u16x8::new(3, 2, 1, 0, 7, 6, 5, 4);
-        let e: u16x8 = transmute(vrev64q_u16(transmute(a)));
+        let e = u16x8::from(vrev64q_u16(a.into()));
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vrev64_u32() {
+    fn test_vrev64_u32() {
         let a = u32x2::new(0, 1);
         let r = u32x2::new(1, 0);
-        let e: u32x2 = transmute(vrev64_u32(transmute(a)));
+        let e = u32x2::from(vrev64_u32(a.into()));
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vrev64q_u32() {
+    fn test_vrev64q_u32() {
         let a = u32x4::new(0, 1, 2, 3);
         let r = u32x4::new(1, 0, 3, 2);
-        let e: u32x4 = transmute(vrev64q_u32(transmute(a)));
+        let e = u32x4::from(vrev64q_u32(a.into()));
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vrev64_f32() {
+    fn test_vrev64_f32() {
         let a = f32x2::new(1.0, 2.0);
         let r = f32x2::new(2.0, 1.0);
-        let e: f32x2 = transmute(vrev64_f32(transmute(a)));
+        let e = f32x2::from(vrev64_f32(a.into()));
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vrev64q_f32() {
+    fn test_vrev64q_f32() {
         let a = f32x4::new(1.0, 2.0, -2.0, -1.0);
         let r = f32x4::new(2.0, 1.0, -1.0, -2.0);
-        let e: f32x4 = transmute(vrev64q_f32(transmute(a)));
+        let e = f32x4::from(vrev64q_f32(a.into()));
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vrev64_p8() {
+    fn test_vrev64_p8() {
         let a = u8x8::new(0, 1, 2, 3, 4, 5, 6, 7);
         let r = u8x8::new(7, 6, 5, 4, 3, 2, 1, 0);
-        let e: u8x8 = transmute(vrev64_p8(transmute(a)));
+        let e = u8x8::from(vrev64_p8(a.into()));
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vrev64q_p8() {
+    fn test_vrev64q_p8() {
         let a = u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let r = u8x16::new(7, 6, 5, 4, 3, 2, 1, 0, 15, 14, 13, 12, 11, 10, 9, 8);
-        let e: u8x16 = transmute(vrev64q_p8(transmute(a)));
+        let e = u8x16::from(vrev64q_p8(a.into()));
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vrev64_p16() {
+    fn test_vrev64_p16() {
         let a = u16x4::new(0, 1, 2, 3);
         let r = u16x4::new(3, 2, 1, 0);
-        let e: u16x4 = transmute(vrev64_p16(transmute(a)));
+        let e = u16x4::from(vrev64_p16(a.into()));
         assert_eq!(r, e);
     }
+
     #[simd_test(enable = "neon")]
-    unsafe fn test_vrev64q_p16() {
+    fn test_vrev64q_p16() {
         let a = u16x8::new(0, 1, 2, 3, 4, 5, 6, 7);
         let r = u16x8::new(3, 2, 1, 0, 7, 6, 5, 4);
-        let e: u16x8 = transmute(vrev64q_p16(transmute(a)));
+        let e = u16x8::from(vrev64q_p16(a.into()));
         assert_eq!(r, e);
     }
 
@@ -5527,13 +5770,13 @@ mod tests {
         ($test_id:ident => $fn_id:ident ([$($a:expr),*], [$($b:expr),*])) => {
             #[allow(unused_assignments)]
             #[simd_test(enable = "neon")]
-            unsafe fn $test_id() {
-                let a = [$($a),*];
-                let b = [$($b),*];
-                let e = [$($a),* $(, $b)*];
-                let c = $fn_id(transmute(a), transmute(b));
+            fn $test_id() {
+                let a = Simd::from_array([$($a),*]);
+                let b = Simd::from_array([$($b),*]);
+                let e = Simd::from_array([$($a),* $(, $b)*]);
+                let c = $fn_id(a.into(), b.into());
                 let mut d = e;
-                d = transmute(c);
+                d = c.into();
                 assert_eq!(d, e);
             }
         }
@@ -5546,11 +5789,19 @@ mod tests {
     test_vcombine!(test_vcombine_s16 => vcombine_s16([3_i16, -4, 5, -6], [13_i16, -14, 15, -16]));
     test_vcombine!(test_vcombine_u16 => vcombine_u16([3_u16, 4, 5, 6], [13_u16, 14, 15, 16]));
     test_vcombine!(test_vcombine_p16 => vcombine_p16([3_u16, 4, 5, 6], [13_u16, 14, 15, 16]));
+
     #[cfg(not(target_arch = "arm64ec"))]
     mod fp16 {
         use super::*;
-        test_vcombine!(test_vcombine_f16 => vcombine_f16([3_f16, 4., 5., 6.],
-        [13_f16, 14., 15., 16.]));
+        #[cfg_attr(target_arch = "arm", simd_test(enable = "neon,fp16"))]
+        #[cfg_attr(not(target_arch = "arm"), simd_test(enable = "neon"))]
+        fn test_vcombine_f16() {
+            let a = f16x4::from_array([3_f16, 4., 5., 6.]);
+            let b = f16x4::from_array([13_f16, 14., 15., 16.]);
+            let e = f16x8::from_array([3_f16, 4., 5., 6., 13_f16, 14., 15., 16.]);
+            let c = f16x8::from(vcombine_f16(a.into(), b.into()));
+            assert_eq!(c, e);
+        }
     }
 
     test_vcombine!(test_vcombine_s32 => vcombine_s32([3_i32, -4], [13_i32, -14]));
diff --git a/library/stdarch/crates/core_arch/src/arm_shared/neon/store_tests.rs b/library/stdarch/crates/core_arch/src/arm_shared/neon/store_tests.rs
index 6b5d4a19ad57..2b10b38f2dd8 100644
--- a/library/stdarch/crates/core_arch/src/arm_shared/neon/store_tests.rs
+++ b/library/stdarch/crates/core_arch/src/arm_shared/neon/store_tests.rs
@@ -14,11 +14,13 @@ use crate::core_arch::simd::*;
 use stdarch_test::simd_test;
 
 #[simd_test(enable = "neon")]
-unsafe fn test_vst1_s8() {
+fn test_vst1_s8() {
     let mut vals = [0_i8; 9];
     let a = i8x8::new(1, 2, 3, 4, 5, 6, 7, 8);
 
-    vst1_s8(vals[1..].as_mut_ptr(), transmute(a));
+    unsafe {
+        vst1_s8(vals[1..].as_mut_ptr(), a.into());
+    }
 
     assert_eq!(vals[0], 0);
     assert_eq!(vals[1], 1);
@@ -32,11 +34,13 @@ unsafe fn test_vst1_s8() {
 }
 
 #[simd_test(enable = "neon")]
-unsafe fn test_vst1q_s8() {
+fn test_vst1q_s8() {
     let mut vals = [0_i8; 17];
     let a = i8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
 
-    vst1q_s8(vals[1..].as_mut_ptr(), transmute(a));
+    unsafe {
+        vst1q_s8(vals[1..].as_mut_ptr(), a.into());
+    }
 
     assert_eq!(vals[0], 0);
     assert_eq!(vals[1], 1);
@@ -58,11 +62,13 @@ unsafe fn test_vst1q_s8() {
 }
 
 #[simd_test(enable = "neon")]
-unsafe fn test_vst1_s16() {
+fn test_vst1_s16() {
     let mut vals = [0_i16; 5];
     let a = i16x4::new(1, 2, 3, 4);
 
-    vst1_s16(vals[1..].as_mut_ptr(), transmute(a));
+    unsafe {
+        vst1_s16(vals[1..].as_mut_ptr(), a.into());
+    }
 
     assert_eq!(vals[0], 0);
     assert_eq!(vals[1], 1);
@@ -72,11 +78,13 @@ unsafe fn test_vst1_s16() {
 }
 
 #[simd_test(enable = "neon")]
-unsafe fn test_vst1q_s16() {
+fn test_vst1q_s16() {
     let mut vals = [0_i16; 9];
     let a = i16x8::new(1, 2, 3, 4, 5, 6, 7, 8);
 
-    vst1q_s16(vals[1..].as_mut_ptr(), transmute(a));
+    unsafe {
+        vst1q_s16(vals[1..].as_mut_ptr(), a.into());
+    }
 
     assert_eq!(vals[0], 0);
     assert_eq!(vals[1], 1);
@@ -90,11 +98,13 @@ unsafe fn test_vst1q_s16() {
 }
 
 #[simd_test(enable = "neon")]
-unsafe fn test_vst1_s32() {
+fn test_vst1_s32() {
     let mut vals = [0_i32; 3];
     let a = i32x2::new(1, 2);
 
-    vst1_s32(vals[1..].as_mut_ptr(), transmute(a));
+    unsafe {
+        vst1_s32(vals[1..].as_mut_ptr(), a.into());
+    }
 
     assert_eq!(vals[0], 0);
     assert_eq!(vals[1], 1);
@@ -102,11 +112,13 @@ unsafe fn test_vst1_s32() {
 }
 
 #[simd_test(enable = "neon")]
-unsafe fn test_vst1q_s32() {
+fn test_vst1q_s32() {
     let mut vals = [0_i32; 5];
     let a = i32x4::new(1, 2, 3, 4);
 
-    vst1q_s32(vals[1..].as_mut_ptr(), transmute(a));
+    unsafe {
+        vst1q_s32(vals[1..].as_mut_ptr(), a.into());
+    }
 
     assert_eq!(vals[0], 0);
     assert_eq!(vals[1], 1);
@@ -116,22 +128,26 @@ unsafe fn test_vst1q_s32() {
 }
 
 #[simd_test(enable = "neon")]
-unsafe fn test_vst1_s64() {
+fn test_vst1_s64() {
     let mut vals = [0_i64; 2];
     let a = i64x1::new(1);
 
-    vst1_s64(vals[1..].as_mut_ptr(), transmute(a));
+    unsafe {
+        vst1_s64(vals[1..].as_mut_ptr(), a.into());
+    }
 
     assert_eq!(vals[0], 0);
     assert_eq!(vals[1], 1);
 }
 
 #[simd_test(enable = "neon")]
-unsafe fn test_vst1q_s64() {
+fn test_vst1q_s64() {
     let mut vals = [0_i64; 3];
     let a = i64x2::new(1, 2);
 
-    vst1q_s64(vals[1..].as_mut_ptr(), transmute(a));
+    unsafe {
+        vst1q_s64(vals[1..].as_mut_ptr(), a.into());
+    }
 
     assert_eq!(vals[0], 0);
     assert_eq!(vals[1], 1);
@@ -139,11 +155,13 @@ unsafe fn test_vst1q_s64() {
 }
 
 #[simd_test(enable = "neon")]
-unsafe fn test_vst1_u8() {
+fn test_vst1_u8() {
     let mut vals = [0_u8; 9];
     let a = u8x8::new(1, 2, 3, 4, 5, 6, 7, 8);
 
-    vst1_u8(vals[1..].as_mut_ptr(), transmute(a));
+    unsafe {
+        vst1_u8(vals[1..].as_mut_ptr(), a.into());
+    }
 
     assert_eq!(vals[0], 0);
     assert_eq!(vals[1], 1);
@@ -157,11 +175,13 @@ unsafe fn test_vst1_u8() {
 }
 
 #[simd_test(enable = "neon")]
-unsafe fn test_vst1q_u8() {
+fn test_vst1q_u8() {
     let mut vals = [0_u8; 17];
     let a = u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
 
-    vst1q_u8(vals[1..].as_mut_ptr(), transmute(a));
+    unsafe {
+        vst1q_u8(vals[1..].as_mut_ptr(), a.into());
+    }
 
     assert_eq!(vals[0], 0);
     assert_eq!(vals[1], 1);
@@ -183,11 +203,13 @@ unsafe fn test_vst1q_u8() {
 }
 
 #[simd_test(enable = "neon")]
-unsafe fn test_vst1_u16() {
+fn test_vst1_u16() {
     let mut vals = [0_u16; 5];
     let a = u16x4::new(1, 2, 3, 4);
 
-    vst1_u16(vals[1..].as_mut_ptr(), transmute(a));
+    unsafe {
+        vst1_u16(vals[1..].as_mut_ptr(), a.into());
+    }
 
     assert_eq!(vals[0], 0);
     assert_eq!(vals[1], 1);
@@ -197,11 +219,13 @@ unsafe fn test_vst1_u16() {
 }
 
 #[simd_test(enable = "neon")]
-unsafe fn test_vst1q_u16() {
+fn test_vst1q_u16() {
     let mut vals = [0_u16; 9];
     let a = u16x8::new(1, 2, 3, 4, 5, 6, 7, 8);
 
-    vst1q_u16(vals[1..].as_mut_ptr(), transmute(a));
+    unsafe {
+        vst1q_u16(vals[1..].as_mut_ptr(), a.into());
+    }
 
     assert_eq!(vals[0], 0);
     assert_eq!(vals[1], 1);
@@ -215,11 +239,13 @@ unsafe fn test_vst1q_u16() {
 }
 
 #[simd_test(enable = "neon")]
-unsafe fn test_vst1_u32() {
+fn test_vst1_u32() {
     let mut vals = [0_u32; 3];
     let a = u32x2::new(1, 2);
 
-    vst1_u32(vals[1..].as_mut_ptr(), transmute(a));
+    unsafe {
+        vst1_u32(vals[1..].as_mut_ptr(), a.into());
+    }
 
     assert_eq!(vals[0], 0);
     assert_eq!(vals[1], 1);
@@ -227,11 +253,13 @@ unsafe fn test_vst1_u32() {
 }
 
 #[simd_test(enable = "neon")]
-unsafe fn test_vst1q_u32() {
+fn test_vst1q_u32() {
     let mut vals = [0_u32; 5];
     let a = u32x4::new(1, 2, 3, 4);
 
-    vst1q_u32(vals[1..].as_mut_ptr(), transmute(a));
+    unsafe {
+        vst1q_u32(vals[1..].as_mut_ptr(), a.into());
+    }
 
     assert_eq!(vals[0], 0);
     assert_eq!(vals[1], 1);
@@ -241,22 +269,26 @@ unsafe fn test_vst1q_u32() {
 }
 
 #[simd_test(enable = "neon")]
-unsafe fn test_vst1_u64() {
+fn test_vst1_u64() {
     let mut vals = [0_u64; 2];
     let a = u64x1::new(1);
 
-    vst1_u64(vals[1..].as_mut_ptr(), transmute(a));
+    unsafe {
+        vst1_u64(vals[1..].as_mut_ptr(), a.into());
+    }
 
     assert_eq!(vals[0], 0);
     assert_eq!(vals[1], 1);
 }
 
 #[simd_test(enable = "neon")]
-unsafe fn test_vst1q_u64() {
+fn test_vst1q_u64() {
     let mut vals = [0_u64; 3];
     let a = u64x2::new(1, 2);
 
-    vst1q_u64(vals[1..].as_mut_ptr(), transmute(a));
+    unsafe {
+        vst1q_u64(vals[1..].as_mut_ptr(), a.into());
+    }
 
     assert_eq!(vals[0], 0);
     assert_eq!(vals[1], 1);
@@ -264,11 +296,13 @@ unsafe fn test_vst1q_u64() {
 }
 
 #[simd_test(enable = "neon")]
-unsafe fn test_vst1_p8() {
+fn test_vst1_p8() {
     let mut vals = [0_u8; 9];
     let a = u8x8::new(1, 2, 3, 4, 5, 6, 7, 8);
 
-    vst1_p8(vals[1..].as_mut_ptr(), transmute(a));
+    unsafe {
+        vst1_p8(vals[1..].as_mut_ptr(), a.into());
+    }
 
     assert_eq!(vals[0], 0);
     assert_eq!(vals[1], 1);
@@ -282,11 +316,13 @@ unsafe fn test_vst1_p8() {
 }
 
 #[simd_test(enable = "neon")]
-unsafe fn test_vst1q_p8() {
+fn test_vst1q_p8() {
     let mut vals = [0_u8; 17];
     let a = u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
 
-    vst1q_p8(vals[1..].as_mut_ptr(), transmute(a));
+    unsafe {
+        vst1q_p8(vals[1..].as_mut_ptr(), a.into());
+    }
 
     assert_eq!(vals[0], 0);
     assert_eq!(vals[1], 1);
@@ -308,11 +344,13 @@ unsafe fn test_vst1q_p8() {
 }
 
 #[simd_test(enable = "neon")]
-unsafe fn test_vst1_p16() {
+fn test_vst1_p16() {
     let mut vals = [0_u16; 5];
     let a = u16x4::new(1, 2, 3, 4);
 
-    vst1_p16(vals[1..].as_mut_ptr(), transmute(a));
+    unsafe {
+        vst1_p16(vals[1..].as_mut_ptr(), a.into());
+    }
 
     assert_eq!(vals[0], 0);
     assert_eq!(vals[1], 1);
@@ -322,11 +360,13 @@ unsafe fn test_vst1_p16() {
 }
 
 #[simd_test(enable = "neon")]
-unsafe fn test_vst1q_p16() {
+fn test_vst1q_p16() {
     let mut vals = [0_u16; 9];
     let a = u16x8::new(1, 2, 3, 4, 5, 6, 7, 8);
 
-    vst1q_p16(vals[1..].as_mut_ptr(), transmute(a));
+    unsafe {
+        vst1q_p16(vals[1..].as_mut_ptr(), a.into());
+    }
 
     assert_eq!(vals[0], 0);
     assert_eq!(vals[1], 1);
@@ -340,22 +380,26 @@ unsafe fn test_vst1q_p16() {
 }
 
 #[simd_test(enable = "neon,aes")]
-unsafe fn test_vst1_p64() {
+fn test_vst1_p64() {
     let mut vals = [0_u64; 2];
     let a = u64x1::new(1);
 
-    vst1_p64(vals[1..].as_mut_ptr(), transmute(a));
+    unsafe {
+        vst1_p64(vals[1..].as_mut_ptr(), a.into());
+    }
 
     assert_eq!(vals[0], 0);
     assert_eq!(vals[1], 1);
 }
 
 #[simd_test(enable = "neon,aes")]
-unsafe fn test_vst1q_p64() {
+fn test_vst1q_p64() {
     let mut vals = [0_u64; 3];
     let a = u64x2::new(1, 2);
 
-    vst1q_p64(vals[1..].as_mut_ptr(), transmute(a));
+    unsafe {
+        vst1q_p64(vals[1..].as_mut_ptr(), a.into());
+    }
 
     assert_eq!(vals[0], 0);
     assert_eq!(vals[1], 1);
@@ -363,11 +407,13 @@ unsafe fn test_vst1q_p64() {
 }
 
 #[simd_test(enable = "neon")]
-unsafe fn test_vst1_f32() {
+fn test_vst1_f32() {
     let mut vals = [0_f32; 3];
     let a = f32x2::new(1., 2.);
 
-    vst1_f32(vals[1..].as_mut_ptr(), transmute(a));
+    unsafe {
+        vst1_f32(vals[1..].as_mut_ptr(), a.into());
+    }
 
     assert_eq!(vals[0], 0.);
     assert_eq!(vals[1], 1.);
@@ -375,11 +421,13 @@ unsafe fn test_vst1_f32() {
 }
 
 #[simd_test(enable = "neon")]
-unsafe fn test_vst1q_f32() {
+fn test_vst1q_f32() {
     let mut vals = [0_f32; 5];
     let a = f32x4::new(1., 2., 3., 4.);
 
-    vst1q_f32(vals[1..].as_mut_ptr(), transmute(a));
+    unsafe {
+        vst1q_f32(vals[1..].as_mut_ptr(), a.into());
+    }
 
     assert_eq!(vals[0], 0.);
     assert_eq!(vals[1], 1.);
diff --git a/library/stdarch/crates/core_arch/src/arm_shared/neon/table_lookup_tests.rs b/library/stdarch/crates/core_arch/src/arm_shared/neon/table_lookup_tests.rs
index 9403855f00e0..1e0333444b94 100644
--- a/library/stdarch/crates/core_arch/src/arm_shared/neon/table_lookup_tests.rs
+++ b/library/stdarch/crates/core_arch/src/arm_shared/neon/table_lookup_tests.rs
@@ -21,19 +21,19 @@ macro_rules! test_vtbl {
     ) => {
         #[cfg(target_endian = "little")]
         #[simd_test(enable = "neon")]
-        unsafe fn $test_name() {
+        fn $test_name() {
             // create table as array, and transmute it to
             // arm's table type
-            let table: $table_t = mem::transmute([$($table_v),*]);
+            let table: $table_t = unsafe { mem::transmute([$($table_v),*]) };
 
             // For each control vector, perform a table lookup and
             // verify the result:
             $(
                 {
-                    let ctrl: $ctrl_t = mem::transmute([$($ctrl_v),*]);
-                    let result = $fn_id(table, mem::transmute(ctrl));
-                    let result: $ctrl_t = mem::transmute(result);
-                    let expected: $ctrl_t = mem::transmute([$($exp_v),*]);
+                    let ctrl: $ctrl_t = unsafe { mem::transmute([$($ctrl_v),*]) };
+                    let result = $fn_id(table, unsafe { mem::transmute(ctrl) });
+                    let result: $ctrl_t = unsafe { mem::transmute(result) };
+                    let expected: $ctrl_t = unsafe { mem::transmute([$($exp_v),*]) };
                     assert_eq!(result, expected);
                 }
             )*
@@ -171,20 +171,19 @@ macro_rules! test_vtbx {
     ) => {
         #[cfg(target_endian = "little")]
         #[simd_test(enable = "neon")]
-        unsafe fn $test_name() {
+        fn $test_name() {
             // create table as array, and transmute it to
             // arm's table type
-            let table: $table_t = mem::transmute([$($table_v),*]);
-            let ext: $ext_t = mem::transmute([$($ext_v),*]);
-
+            let table: $table_t = unsafe { mem::transmute([$($table_v),*]) };
+            let ext: $ext_t = unsafe { mem::transmute([$($ext_v),*]) };
             // For each control vector, perform a table lookup and
             // verify the result:
             $(
                 {
-                    let ctrl: $ctrl_t = mem::transmute([$($ctrl_v),*]);
-                    let result = $fn_id(ext, table, mem::transmute(ctrl));
-                    let result: $ctrl_t = mem::transmute(result);
-                    let expected: $ctrl_t = mem::transmute([$($exp_v),*]);
+                    let ctrl: $ctrl_t = unsafe { mem::transmute([$($ctrl_v),*]) };
+                    let result = $fn_id(ext, table, unsafe { mem::transmute(ctrl) });
+                    let result: $ctrl_t = unsafe { mem::transmute(result) };
+                    let expected: $ctrl_t = unsafe { mem::transmute([$($exp_v),*]) };
                     assert_eq!(result, expected);
                 }
             )*
diff --git a/library/stdarch/crates/core_arch/src/arm_shared/test_support.rs b/library/stdarch/crates/core_arch/src/arm_shared/test_support.rs
index e2828f85561d..8117b81cd9a3 100644
--- a/library/stdarch/crates/core_arch/src/arm_shared/test_support.rs
+++ b/library/stdarch/crates/core_arch/src/arm_shared/test_support.rs
@@ -111,13 +111,13 @@ macro_rules! V_f32 {
 
 macro_rules! to64 {
     ($t : ident) => {
-        |v: $t| -> u64 { transmute(v) }
+        |v: $t| -> u64 { unsafe { transmute(v) } }
     };
 }
 
 macro_rules! to128 {
     ($t : ident) => {
-        |v: $t| -> u128 { transmute(v) }
+        |v: $t| -> u128 { unsafe { transmute(v) } }
     };
 }
 
@@ -158,9 +158,7 @@ pub(crate) fn test<T, U, V, W, X>(
 macro_rules! gen_test_fn {
     ($n: ident, $t: ident, $u: ident, $v: ident, $w: ident, $x: ident, $vals: expr, $fill1: expr, $fill2: expr, $cast: expr) => {
         pub(crate) fn $n(test_fun: fn($v, $v) -> $w, verify_fun: fn($t, $t) -> $u) {
-            unsafe {
-                test::<$t, $u, $v, $w, $x>($vals, $fill1, $fill2, $cast, test_fun, verify_fun)
-            };
+            test::<$t, $u, $v, $w, $x>($vals, $fill1, $fill2, $cast, test_fun, verify_fun);
         }
     };
 }
diff --git a/library/stdarch/crates/simd-test-macro/src/lib.rs b/library/stdarch/crates/simd-test-macro/src/lib.rs
index b8bb874480a0..92bb40946e1f 100644
--- a/library/stdarch/crates/simd-test-macro/src/lib.rs
+++ b/library/stdarch/crates/simd-test-macro/src/lib.rs
@@ -17,6 +17,15 @@ pub fn simd_test(
     item: proc_macro::TokenStream,
 ) -> proc_macro::TokenStream {
     let tokens = TokenStream::from(attr).into_iter().collect::<Vec<_>>();
+
+    let target = env::var("TARGET").expect(
+        "TARGET environment variable should be set for rustc (e.g. TARGET=x86_64-apple-darwin cargo test)"
+    );
+    let target_arch = target
+        .split('-')
+        .next()
+        .unwrap_or_else(|| panic!("target triple contained no \"-\": {target}"));
+
     let (target_features, target_feature_attr) = match &tokens[..] {
         [] => (Vec::new(), TokenStream::new()),
         [
@@ -24,13 +33,20 @@ pub fn simd_test(
             TokenTree::Punct(equals),
             TokenTree::Literal(literal),
         ] if enable == "enable" && equals.as_char() == '=' => {
-            let enable_feature = literal.to_string();
-            let enable_feature = enable_feature.trim_start_matches('"').trim_end_matches('"');
+            let mut enable_feature = literal
+                .to_string()
+                .trim_start_matches('"')
+                .trim_end_matches('"')
+                .to_string();
             let target_features: Vec<_> = enable_feature
                 .replace('+', "")
                 .split(',')
                 .map(String::from)
                 .collect();
+            // Allows using `#[simd_test(enable = "neon")]` on aarch64/armv7 shared tests.
+            if target_arch == "armv7" && target_features.iter().any(|feat| feat == "neon") {
+                enable_feature.push_str(",v7");
+            }
 
             (
                 target_features,
@@ -46,14 +62,7 @@ pub fn simd_test(
     let item_attrs = std::mem::take(&mut item.attrs);
     let name = &item.sig.ident;
 
-    let target = env::var("TARGET").expect(
-        "TARGET environment variable should be set for rustc (e.g. TARGET=x86_64-apple-darwin cargo test)"
-    );
-    let macro_test = match target
-        .split('-')
-        .next()
-        .unwrap_or_else(|| panic!("target triple contained no \"-\": {target}"))
-    {
+    let macro_test = match target_arch {
         "i686" | "x86_64" | "i586" => "is_x86_feature_detected",
         "arm" | "armv7" | "thumbv7neon" => "is_arm_feature_detected",
         "aarch64" | "arm64ec" | "aarch64_be" => "is_aarch64_feature_detected",
@@ -85,10 +94,20 @@ pub fn simd_test(
 
     let mut detect_missing_features = TokenStream::new();
     for feature in target_features {
-        let q = quote_spanned! {
-            proc_macro2::Span::call_site() =>
-            if !::std::arch::#macro_test!(#feature) {
-                missing_features.push(#feature);
+        let q = if target_arch == "armv7" && feature == "fp16" {
+            // "fp16" cannot be checked at runtime
+            quote_spanned! {
+                proc_macro2::Span::call_site() =>
+                if !cfg!(target_feature = #feature) {
+                    missing_features.push(#feature);
+                }
+            }
+        } else {
+            quote_spanned! {
+                proc_macro2::Span::call_site() =>
+                if !::std::arch::#macro_test!(#feature) {
+                    missing_features.push(#feature);
+                }
             }
         };
         q.to_tokens(&mut detect_missing_features);

From 7630884c55c77baf3cb399b67146f1f5bd5b18df Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Eduardo=20S=C3=A1nchez=20Mu=C3=B1oz?= <eduardosm-dev@e64.io>
Date: Tue, 6 Jan 2026 20:01:25 +0100
Subject: [PATCH 10/97] Avoid `unsafe fn` in remaining x86 tests

---
 .../stdarch/crates/core_arch/src/x86/avx.rs   | 231 +++--
 .../stdarch/crates/core_arch/src/x86/avx2.rs  | 374 ++++---
 .../crates/core_arch/src/x86/avx512bf16.rs    | 279 ++---
 .../crates/core_arch/src/x86/avx512bw.rs      | 314 +++---
 .../crates/core_arch/src/x86/avx512dq.rs      |  52 +-
 .../crates/core_arch/src/x86/avx512f.rs       | 966 +++++++++++-------
 .../crates/core_arch/src/x86/avx512fp16.rs    |  99 +-
 .../crates/core_arch/src/x86/avx512vbmi2.rs   | 124 ++-
 .../crates/core_arch/src/x86/avxneconvert.rs  |  56 +-
 .../stdarch/crates/core_arch/src/x86/f16c.rs  |   2 +-
 .../stdarch/crates/core_arch/src/x86/fxsr.rs  |  10 +-
 .../stdarch/crates/core_arch/src/x86/gfni.rs  | 210 ++--
 .../stdarch/crates/core_arch/src/x86/kl.rs    |  88 +-
 .../stdarch/crates/core_arch/src/x86/rtm.rs   |  34 +-
 .../stdarch/crates/core_arch/src/x86/sse.rs   |  60 +-
 .../stdarch/crates/core_arch/src/x86/sse2.rs  | 178 ++--
 .../stdarch/crates/core_arch/src/x86/sse3.rs  |   8 +-
 .../stdarch/crates/core_arch/src/x86/sse41.rs |  12 +-
 .../stdarch/crates/core_arch/src/x86/sse42.rs |   3 +-
 .../stdarch/crates/core_arch/src/x86/sse4a.rs |  12 +-
 .../stdarch/crates/core_arch/src/x86/xsave.rs |  36 +-
 .../crates/core_arch/src/x86_64/amx.rs        | 854 ++++++++--------
 .../crates/core_arch/src/x86_64/avx512f.rs    | 659 +++++++-----
 .../crates/core_arch/src/x86_64/fxsr.rs       |  10 +-
 .../crates/core_arch/src/x86_64/sse2.rs       |   6 +-
 .../crates/core_arch/src/x86_64/xsave.rs      |  30 +-
 26 files changed, 2691 insertions(+), 2016 deletions(-)

diff --git a/library/stdarch/crates/core_arch/src/x86/avx.rs b/library/stdarch/crates/core_arch/src/x86/avx.rs
index e0e01ae6d034..c406d537bc1c 100644
--- a/library/stdarch/crates/core_arch/src/x86/avx.rs
+++ b/library/stdarch/crates/core_arch/src/x86/avx.rs
@@ -3369,6 +3369,7 @@ unsafe extern "C" {
 #[cfg(test)]
 mod tests {
     use crate::core_arch::assert_eq_const as assert_eq;
+    use crate::core_arch::simd::*;
     use crate::hint::black_box;
     use crate::ptr;
     use stdarch_test::simd_test;
@@ -3464,7 +3465,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_max_pd() {
+    fn test_mm256_max_pd() {
         let a = _mm256_setr_pd(1., 4., 5., 8.);
         let b = _mm256_setr_pd(2., 3., 6., 7.);
         let r = _mm256_max_pd(a, b);
@@ -3474,23 +3475,22 @@ mod tests {
         // > value in the second operand (source operand) is returned.
         let w = _mm256_max_pd(_mm256_set1_pd(0.0), _mm256_set1_pd(-0.0));
         let x = _mm256_max_pd(_mm256_set1_pd(-0.0), _mm256_set1_pd(0.0));
-        let wu: [u64; 4] = transmute(w);
-        let xu: [u64; 4] = transmute(x);
-        assert_eq!(wu, [0x8000_0000_0000_0000u64; 4]);
-        assert_eq!(xu, [0u64; 4]);
+        let wu = _mm256_castpd_si256(w).as_u64x4();
+        let xu = _mm256_castpd_si256(x).as_u64x4();
+        assert_eq!(wu, u64x4::splat(0x8000_0000_0000_0000u64));
+        assert_eq!(xu, u64x4::splat(0u64));
         // > If only one value is a NaN (SNaN or QNaN) for this instruction, the
         // > second operand (source operand), either a NaN or a valid
         // > floating-point value, is written to the result.
         let y = _mm256_max_pd(_mm256_set1_pd(f64::NAN), _mm256_set1_pd(0.0));
         let z = _mm256_max_pd(_mm256_set1_pd(0.0), _mm256_set1_pd(f64::NAN));
-        let yf: [f64; 4] = transmute(y);
-        let zf: [f64; 4] = transmute(z);
-        assert_eq!(yf, [0.0; 4]);
+        assert_eq_m256d(y, _mm256_set1_pd(0.0));
+        let zf = *z.as_f64x4().as_array();
         assert!(zf.iter().all(|f| f.is_nan()), "{:?}", zf);
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_max_ps() {
+    fn test_mm256_max_ps() {
         let a = _mm256_setr_ps(1., 4., 5., 8., 9., 12., 13., 16.);
         let b = _mm256_setr_ps(2., 3., 6., 7., 10., 11., 14., 15.);
         let r = _mm256_max_ps(a, b);
@@ -3500,23 +3500,22 @@ mod tests {
         // > value in the second operand (source operand) is returned.
         let w = _mm256_max_ps(_mm256_set1_ps(0.0), _mm256_set1_ps(-0.0));
         let x = _mm256_max_ps(_mm256_set1_ps(-0.0), _mm256_set1_ps(0.0));
-        let wu: [u32; 8] = transmute(w);
-        let xu: [u32; 8] = transmute(x);
-        assert_eq!(wu, [0x8000_0000u32; 8]);
-        assert_eq!(xu, [0u32; 8]);
+        let wu = _mm256_castps_si256(w).as_u32x8();
+        let xu = _mm256_castps_si256(x).as_u32x8();
+        assert_eq!(wu, u32x8::splat(0x8000_0000u32));
+        assert_eq!(xu, u32x8::splat(0u32));
         // > If only one value is a NaN (SNaN or QNaN) for this instruction, the
         // > second operand (source operand), either a NaN or a valid
         // > floating-point value, is written to the result.
         let y = _mm256_max_ps(_mm256_set1_ps(f32::NAN), _mm256_set1_ps(0.0));
         let z = _mm256_max_ps(_mm256_set1_ps(0.0), _mm256_set1_ps(f32::NAN));
-        let yf: [f32; 8] = transmute(y);
-        let zf: [f32; 8] = transmute(z);
-        assert_eq!(yf, [0.0; 8]);
+        assert_eq_m256(y, _mm256_set1_ps(0.0));
+        let zf = *z.as_f32x8().as_array();
         assert!(zf.iter().all(|f| f.is_nan()), "{:?}", zf);
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_min_pd() {
+    fn test_mm256_min_pd() {
         let a = _mm256_setr_pd(1., 4., 5., 8.);
         let b = _mm256_setr_pd(2., 3., 6., 7.);
         let r = _mm256_min_pd(a, b);
@@ -3526,23 +3525,22 @@ mod tests {
         // > value in the second operand (source operand) is returned.
         let w = _mm256_min_pd(_mm256_set1_pd(0.0), _mm256_set1_pd(-0.0));
         let x = _mm256_min_pd(_mm256_set1_pd(-0.0), _mm256_set1_pd(0.0));
-        let wu: [u64; 4] = transmute(w);
-        let xu: [u64; 4] = transmute(x);
-        assert_eq!(wu, [0x8000_0000_0000_0000u64; 4]);
-        assert_eq!(xu, [0u64; 4]);
+        let wu = _mm256_castpd_si256(w).as_u64x4();
+        let xu = _mm256_castpd_si256(x).as_u64x4();
+        assert_eq!(wu, u64x4::splat(0x8000_0000_0000_0000u64));
+        assert_eq!(xu, u64x4::splat(0u64));
         // > If only one value is a NaN (SNaN or QNaN) for this instruction, the
         // > second operand (source operand), either a NaN or a valid
         // > floating-point value, is written to the result.
         let y = _mm256_min_pd(_mm256_set1_pd(f64::NAN), _mm256_set1_pd(0.0));
         let z = _mm256_min_pd(_mm256_set1_pd(0.0), _mm256_set1_pd(f64::NAN));
-        let yf: [f64; 4] = transmute(y);
-        let zf: [f64; 4] = transmute(z);
-        assert_eq!(yf, [0.0; 4]);
+        assert_eq_m256d(y, _mm256_set1_pd(0.0));
+        let zf = *z.as_f64x4().as_array();
         assert!(zf.iter().all(|f| f.is_nan()), "{:?}", zf);
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_min_ps() {
+    fn test_mm256_min_ps() {
         let a = _mm256_setr_ps(1., 4., 5., 8., 9., 12., 13., 16.);
         let b = _mm256_setr_ps(2., 3., 6., 7., 10., 11., 14., 15.);
         let r = _mm256_min_ps(a, b);
@@ -3552,18 +3550,17 @@ mod tests {
         // > value in the second operand (source operand) is returned.
         let w = _mm256_min_ps(_mm256_set1_ps(0.0), _mm256_set1_ps(-0.0));
         let x = _mm256_min_ps(_mm256_set1_ps(-0.0), _mm256_set1_ps(0.0));
-        let wu: [u32; 8] = transmute(w);
-        let xu: [u32; 8] = transmute(x);
-        assert_eq!(wu, [0x8000_0000u32; 8]);
-        assert_eq!(xu, [0u32; 8]);
+        let wu = _mm256_castps_si256(w).as_u32x8();
+        let xu = _mm256_castps_si256(x).as_u32x8();
+        assert_eq!(wu, u32x8::splat(0x8000_0000u32));
+        assert_eq!(xu, u32x8::splat(0u32));
         // > If only one value is a NaN (SNaN or QNaN) for this instruction, the
         // > second operand (source operand), either a NaN or a valid
         // > floating-point value, is written to the result.
         let y = _mm256_min_ps(_mm256_set1_ps(f32::NAN), _mm256_set1_ps(0.0));
         let z = _mm256_min_ps(_mm256_set1_ps(0.0), _mm256_set1_ps(f32::NAN));
-        let yf: [f32; 8] = transmute(y);
-        let zf: [f32; 8] = transmute(z);
-        assert_eq!(yf, [0.0; 8]);
+        assert_eq_m256(y, _mm256_set1_ps(0.0));
+        let zf = *z.as_f32x8().as_array();
         assert!(zf.iter().all(|f| f.is_nan()), "{:?}", zf);
     }
 
@@ -4247,183 +4244,203 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_load_pd() {
+    const fn test_mm256_load_pd() {
         let a = _mm256_setr_pd(1., 2., 3., 4.);
         let p = ptr::addr_of!(a) as *const f64;
-        let r = _mm256_load_pd(p);
+        let r = unsafe { _mm256_load_pd(p) };
         let e = _mm256_setr_pd(1., 2., 3., 4.);
         assert_eq_m256d(r, e);
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_store_pd() {
+    const fn test_mm256_store_pd() {
         let a = _mm256_setr_pd(1., 2., 3., 4.);
         let mut r = _mm256_undefined_pd();
-        _mm256_store_pd(ptr::addr_of_mut!(r) as *mut f64, a);
+        unsafe {
+            _mm256_store_pd(ptr::addr_of_mut!(r) as *mut f64, a);
+        }
         assert_eq_m256d(r, a);
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_load_ps() {
+    const fn test_mm256_load_ps() {
         let a = _mm256_setr_ps(4., 3., 2., 5., 8., 9., 64., 50.);
         let p = ptr::addr_of!(a) as *const f32;
-        let r = _mm256_load_ps(p);
+        let r = unsafe { _mm256_load_ps(p) };
         let e = _mm256_setr_ps(4., 3., 2., 5., 8., 9., 64., 50.);
         assert_eq_m256(r, e);
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_store_ps() {
+    const fn test_mm256_store_ps() {
         let a = _mm256_setr_ps(4., 3., 2., 5., 8., 9., 64., 50.);
         let mut r = _mm256_undefined_ps();
-        _mm256_store_ps(ptr::addr_of_mut!(r) as *mut f32, a);
+        unsafe {
+            _mm256_store_ps(ptr::addr_of_mut!(r) as *mut f32, a);
+        }
         assert_eq_m256(r, a);
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_loadu_pd() {
+    const fn test_mm256_loadu_pd() {
         let a = &[1.0f64, 2., 3., 4.];
         let p = a.as_ptr();
-        let r = _mm256_loadu_pd(black_box(p));
+        let r = unsafe { _mm256_loadu_pd(black_box(p)) };
         let e = _mm256_setr_pd(1., 2., 3., 4.);
         assert_eq_m256d(r, e);
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_storeu_pd() {
+    const fn test_mm256_storeu_pd() {
         let a = _mm256_set1_pd(9.);
         let mut r = _mm256_undefined_pd();
-        _mm256_storeu_pd(ptr::addr_of_mut!(r) as *mut f64, a);
+        unsafe {
+            _mm256_storeu_pd(ptr::addr_of_mut!(r) as *mut f64, a);
+        }
         assert_eq_m256d(r, a);
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_loadu_ps() {
+    const fn test_mm256_loadu_ps() {
         let a = &[4., 3., 2., 5., 8., 9., 64., 50.];
         let p = a.as_ptr();
-        let r = _mm256_loadu_ps(black_box(p));
+        let r = unsafe { _mm256_loadu_ps(black_box(p)) };
         let e = _mm256_setr_ps(4., 3., 2., 5., 8., 9., 64., 50.);
         assert_eq_m256(r, e);
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_storeu_ps() {
+    const fn test_mm256_storeu_ps() {
         let a = _mm256_set1_ps(9.);
         let mut r = _mm256_undefined_ps();
-        _mm256_storeu_ps(ptr::addr_of_mut!(r) as *mut f32, a);
+        unsafe {
+            _mm256_storeu_ps(ptr::addr_of_mut!(r) as *mut f32, a);
+        }
         assert_eq_m256(r, a);
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_load_si256() {
+    const fn test_mm256_load_si256() {
         let a = _mm256_setr_epi64x(1, 2, 3, 4);
         let p = ptr::addr_of!(a);
-        let r = _mm256_load_si256(p);
+        let r = unsafe { _mm256_load_si256(p) };
         let e = _mm256_setr_epi64x(1, 2, 3, 4);
         assert_eq_m256i(r, e);
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_store_si256() {
+    const fn test_mm256_store_si256() {
         let a = _mm256_setr_epi64x(1, 2, 3, 4);
         let mut r = _mm256_undefined_si256();
-        _mm256_store_si256(ptr::addr_of_mut!(r), a);
+        unsafe {
+            _mm256_store_si256(ptr::addr_of_mut!(r), a);
+        }
         assert_eq_m256i(r, a);
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_loadu_si256() {
+    const fn test_mm256_loadu_si256() {
         let a = _mm256_setr_epi64x(1, 2, 3, 4);
         let p = ptr::addr_of!(a);
-        let r = _mm256_loadu_si256(black_box(p));
+        let r = unsafe { _mm256_loadu_si256(black_box(p)) };
         let e = _mm256_setr_epi64x(1, 2, 3, 4);
         assert_eq_m256i(r, e);
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_storeu_si256() {
+    const fn test_mm256_storeu_si256() {
         let a = _mm256_set1_epi8(9);
         let mut r = _mm256_undefined_si256();
-        _mm256_storeu_si256(ptr::addr_of_mut!(r), a);
+        unsafe {
+            _mm256_storeu_si256(ptr::addr_of_mut!(r), a);
+        }
         assert_eq_m256i(r, a);
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_maskload_pd() {
+    const fn test_mm256_maskload_pd() {
         let a = &[1.0f64, 2., 3., 4.];
         let p = a.as_ptr();
         let mask = _mm256_setr_epi64x(0, !0, 0, !0);
-        let r = _mm256_maskload_pd(black_box(p), mask);
+        let r = unsafe { _mm256_maskload_pd(black_box(p), mask) };
         let e = _mm256_setr_pd(0., 2., 0., 4.);
         assert_eq_m256d(r, e);
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_maskstore_pd() {
+    const fn test_mm256_maskstore_pd() {
         let mut r = _mm256_set1_pd(0.);
         let mask = _mm256_setr_epi64x(0, !0, 0, !0);
         let a = _mm256_setr_pd(1., 2., 3., 4.);
-        _mm256_maskstore_pd(ptr::addr_of_mut!(r) as *mut f64, mask, a);
+        unsafe {
+            _mm256_maskstore_pd(ptr::addr_of_mut!(r) as *mut f64, mask, a);
+        }
         let e = _mm256_setr_pd(0., 2., 0., 4.);
         assert_eq_m256d(r, e);
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm_maskload_pd() {
+    const fn test_mm_maskload_pd() {
         let a = &[1.0f64, 2.];
         let p = a.as_ptr();
         let mask = _mm_setr_epi64x(0, !0);
-        let r = _mm_maskload_pd(black_box(p), mask);
+        let r = unsafe { _mm_maskload_pd(black_box(p), mask) };
         let e = _mm_setr_pd(0., 2.);
         assert_eq_m128d(r, e);
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm_maskstore_pd() {
+    const fn test_mm_maskstore_pd() {
         let mut r = _mm_set1_pd(0.);
         let mask = _mm_setr_epi64x(0, !0);
         let a = _mm_setr_pd(1., 2.);
-        _mm_maskstore_pd(ptr::addr_of_mut!(r) as *mut f64, mask, a);
+        unsafe {
+            _mm_maskstore_pd(ptr::addr_of_mut!(r) as *mut f64, mask, a);
+        }
         let e = _mm_setr_pd(0., 2.);
         assert_eq_m128d(r, e);
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_maskload_ps() {
+    const fn test_mm256_maskload_ps() {
         let a = &[1.0f32, 2., 3., 4., 5., 6., 7., 8.];
         let p = a.as_ptr();
         let mask = _mm256_setr_epi32(0, !0, 0, !0, 0, !0, 0, !0);
-        let r = _mm256_maskload_ps(black_box(p), mask);
+        let r = unsafe { _mm256_maskload_ps(black_box(p), mask) };
         let e = _mm256_setr_ps(0., 2., 0., 4., 0., 6., 0., 8.);
         assert_eq_m256(r, e);
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_maskstore_ps() {
+    const fn test_mm256_maskstore_ps() {
         let mut r = _mm256_set1_ps(0.);
         let mask = _mm256_setr_epi32(0, !0, 0, !0, 0, !0, 0, !0);
         let a = _mm256_setr_ps(1., 2., 3., 4., 5., 6., 7., 8.);
-        _mm256_maskstore_ps(ptr::addr_of_mut!(r) as *mut f32, mask, a);
+        unsafe {
+            _mm256_maskstore_ps(ptr::addr_of_mut!(r) as *mut f32, mask, a);
+        }
         let e = _mm256_setr_ps(0., 2., 0., 4., 0., 6., 0., 8.);
         assert_eq_m256(r, e);
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm_maskload_ps() {
+    const fn test_mm_maskload_ps() {
         let a = &[1.0f32, 2., 3., 4.];
         let p = a.as_ptr();
         let mask = _mm_setr_epi32(0, !0, 0, !0);
-        let r = _mm_maskload_ps(black_box(p), mask);
+        let r = unsafe { _mm_maskload_ps(black_box(p), mask) };
         let e = _mm_setr_ps(0., 2., 0., 4.);
         assert_eq_m128(r, e);
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm_maskstore_ps() {
+    const fn test_mm_maskstore_ps() {
         let mut r = _mm_set1_ps(0.);
         let mask = _mm_setr_epi32(0, !0, 0, !0);
         let a = _mm_setr_ps(1., 2., 3., 4.);
-        _mm_maskstore_ps(ptr::addr_of_mut!(r) as *mut f32, mask, a);
+        unsafe {
+            _mm_maskstore_ps(ptr::addr_of_mut!(r) as *mut f32, mask, a);
+        }
         let e = _mm_setr_ps(0., 2., 0., 4.);
         assert_eq_m128(r, e);
     }
@@ -4453,7 +4470,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    unsafe fn test_mm256_lddqu_si256() {
+    fn test_mm256_lddqu_si256() {
         #[rustfmt::skip]
         let a = _mm256_setr_epi8(
             1, 2, 3, 4, 5, 6, 7, 8,
@@ -4462,7 +4479,7 @@ mod tests {
             25, 26, 27, 28, 29, 30, 31, 32,
         );
         let p = ptr::addr_of!(a);
-        let r = _mm256_lddqu_si256(black_box(p));
+        let r = unsafe { _mm256_lddqu_si256(black_box(p)) };
         #[rustfmt::skip]
         let e = _mm256_setr_epi8(
             1, 2, 3, 4, 5, 6, 7, 8,
@@ -4475,17 +4492,19 @@ mod tests {
 
     #[simd_test(enable = "avx")]
     #[cfg_attr(miri, ignore)] // Non-temporal store, which is not supported by Miri
-    unsafe fn test_mm256_stream_si256() {
+    fn test_mm256_stream_si256() {
         let a = _mm256_setr_epi64x(1, 2, 3, 4);
         let mut r = _mm256_undefined_si256();
-        _mm256_stream_si256(ptr::addr_of_mut!(r), a);
+        unsafe {
+            _mm256_stream_si256(ptr::addr_of_mut!(r), a);
+        }
         _mm_sfence();
         assert_eq_m256i(r, a);
     }
 
     #[simd_test(enable = "avx")]
     #[cfg_attr(miri, ignore)] // Non-temporal store, which is not supported by Miri
-    unsafe fn test_mm256_stream_pd() {
+    fn test_mm256_stream_pd() {
         #[repr(align(32))]
         struct Memory {
             pub data: [f64; 4],
@@ -4493,7 +4512,9 @@ mod tests {
         let a = _mm256_set1_pd(7.0);
         let mut mem = Memory { data: [-1.0; 4] };
 
-        _mm256_stream_pd(ptr::addr_of_mut!(mem.data[0]), a);
+        unsafe {
+            _mm256_stream_pd(ptr::addr_of_mut!(mem.data[0]), a);
+        }
         _mm_sfence();
         for i in 0..4 {
             assert_eq!(mem.data[i], get_m256d(a, i));
@@ -4502,7 +4523,7 @@ mod tests {
 
     #[simd_test(enable = "avx")]
     #[cfg_attr(miri, ignore)] // Non-temporal store, which is not supported by Miri
-    unsafe fn test_mm256_stream_ps() {
+    fn test_mm256_stream_ps() {
         #[repr(align(32))]
         struct Memory {
             pub data: [f32; 8],
@@ -4510,7 +4531,9 @@ mod tests {
         let a = _mm256_set1_ps(7.0);
         let mut mem = Memory { data: [-1.0; 8] };
 
-        _mm256_stream_ps(ptr::addr_of_mut!(mem.data[0]), a);
+        unsafe {
+            _mm256_stream_ps(ptr::addr_of_mut!(mem.data[0]), a);
+        }
         _mm_sfence();
         for i in 0..8 {
             assert_eq!(mem.data[i], get_m256(a, i));
@@ -5147,29 +5170,29 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_loadu2_m128() {
+    const fn test_mm256_loadu2_m128() {
         let hi = &[5., 6., 7., 8.];
         let hiaddr = hi.as_ptr();
         let lo = &[1., 2., 3., 4.];
         let loaddr = lo.as_ptr();
-        let r = _mm256_loadu2_m128(hiaddr, loaddr);
+        let r = unsafe { _mm256_loadu2_m128(hiaddr, loaddr) };
         let e = _mm256_setr_ps(1., 2., 3., 4., 5., 6., 7., 8.);
         assert_eq_m256(r, e);
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_loadu2_m128d() {
+    const fn test_mm256_loadu2_m128d() {
         let hi = &[3., 4.];
         let hiaddr = hi.as_ptr();
         let lo = &[1., 2.];
         let loaddr = lo.as_ptr();
-        let r = _mm256_loadu2_m128d(hiaddr, loaddr);
+        let r = unsafe { _mm256_loadu2_m128d(hiaddr, loaddr) };
         let e = _mm256_setr_pd(1., 2., 3., 4.);
         assert_eq_m256d(r, e);
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_loadu2_m128i() {
+    const fn test_mm256_loadu2_m128i() {
         #[rustfmt::skip]
         let hi = _mm_setr_epi8(
             17, 18, 19, 20, 21, 22, 23, 24,
@@ -5180,7 +5203,9 @@ mod tests {
             1, 2, 3, 4, 5, 6, 7, 8,
             9, 10, 11, 12, 13, 14, 15, 16,
         );
-        let r = _mm256_loadu2_m128i(ptr::addr_of!(hi) as *const _, ptr::addr_of!(lo) as *const _);
+        let r = unsafe {
+            _mm256_loadu2_m128i(ptr::addr_of!(hi) as *const _, ptr::addr_of!(lo) as *const _)
+        };
         #[rustfmt::skip]
         let e = _mm256_setr_epi8(
             1, 2, 3, 4, 5, 6, 7, 8,
@@ -5192,35 +5217,39 @@ mod tests {
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_storeu2_m128() {
+    const fn test_mm256_storeu2_m128() {
         let a = _mm256_setr_ps(1., 2., 3., 4., 5., 6., 7., 8.);
         let mut hi = _mm_undefined_ps();
         let mut lo = _mm_undefined_ps();
-        _mm256_storeu2_m128(
-            ptr::addr_of_mut!(hi) as *mut f32,
-            ptr::addr_of_mut!(lo) as *mut f32,
-            a,
-        );
+        unsafe {
+            _mm256_storeu2_m128(
+                ptr::addr_of_mut!(hi) as *mut f32,
+                ptr::addr_of_mut!(lo) as *mut f32,
+                a,
+            );
+        }
         assert_eq_m128(hi, _mm_setr_ps(5., 6., 7., 8.));
         assert_eq_m128(lo, _mm_setr_ps(1., 2., 3., 4.));
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_storeu2_m128d() {
+    const fn test_mm256_storeu2_m128d() {
         let a = _mm256_setr_pd(1., 2., 3., 4.);
         let mut hi = _mm_undefined_pd();
         let mut lo = _mm_undefined_pd();
-        _mm256_storeu2_m128d(
-            ptr::addr_of_mut!(hi) as *mut f64,
-            ptr::addr_of_mut!(lo) as *mut f64,
-            a,
-        );
+        unsafe {
+            _mm256_storeu2_m128d(
+                ptr::addr_of_mut!(hi) as *mut f64,
+                ptr::addr_of_mut!(lo) as *mut f64,
+                a,
+            );
+        }
         assert_eq_m128d(hi, _mm_setr_pd(3., 4.));
         assert_eq_m128d(lo, _mm_setr_pd(1., 2.));
     }
 
     #[simd_test(enable = "avx")]
-    const unsafe fn test_mm256_storeu2_m128i() {
+    const fn test_mm256_storeu2_m128i() {
         #[rustfmt::skip]
         let a = _mm256_setr_epi8(
             1, 2, 3, 4, 5, 6, 7, 8,
@@ -5230,7 +5259,9 @@ mod tests {
         );
         let mut hi = _mm_undefined_si128();
         let mut lo = _mm_undefined_si128();
-        _mm256_storeu2_m128i(ptr::addr_of_mut!(hi), ptr::addr_of_mut!(lo), a);
+        unsafe {
+            _mm256_storeu2_m128i(ptr::addr_of_mut!(hi), ptr::addr_of_mut!(lo), a);
+        }
         #[rustfmt::skip]
         let e_hi = _mm_setr_epi8(
             17, 18, 19, 20, 21, 22, 23, 24,
diff --git a/library/stdarch/crates/core_arch/src/x86/avx2.rs b/library/stdarch/crates/core_arch/src/x86/avx2.rs
index 6f56e937c6db..6a39a0aaf8fe 100644
--- a/library/stdarch/crates/core_arch/src/x86/avx2.rs
+++ b/library/stdarch/crates/core_arch/src/x86/avx2.rs
@@ -4672,81 +4672,89 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm_maskload_epi32() {
+    const fn test_mm_maskload_epi32() {
         let nums = [1, 2, 3, 4];
         let a = &nums as *const i32;
         let mask = _mm_setr_epi32(-1, 0, 0, -1);
-        let r = _mm_maskload_epi32(a, mask);
+        let r = unsafe { _mm_maskload_epi32(a, mask) };
         let e = _mm_setr_epi32(1, 0, 0, 4);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm256_maskload_epi32() {
+    const fn test_mm256_maskload_epi32() {
         let nums = [1, 2, 3, 4, 5, 6, 7, 8];
         let a = &nums as *const i32;
         let mask = _mm256_setr_epi32(-1, 0, 0, -1, 0, -1, -1, 0);
-        let r = _mm256_maskload_epi32(a, mask);
+        let r = unsafe { _mm256_maskload_epi32(a, mask) };
         let e = _mm256_setr_epi32(1, 0, 0, 4, 0, 6, 7, 0);
         assert_eq_m256i(r, e);
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm_maskload_epi64() {
+    const fn test_mm_maskload_epi64() {
         let nums = [1_i64, 2_i64];
         let a = &nums as *const i64;
         let mask = _mm_setr_epi64x(0, -1);
-        let r = _mm_maskload_epi64(a, mask);
+        let r = unsafe { _mm_maskload_epi64(a, mask) };
         let e = _mm_setr_epi64x(0, 2);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm256_maskload_epi64() {
+    const fn test_mm256_maskload_epi64() {
         let nums = [1_i64, 2_i64, 3_i64, 4_i64];
         let a = &nums as *const i64;
         let mask = _mm256_setr_epi64x(0, -1, -1, 0);
-        let r = _mm256_maskload_epi64(a, mask);
+        let r = unsafe { _mm256_maskload_epi64(a, mask) };
         let e = _mm256_setr_epi64x(0, 2, 3, 0);
         assert_eq_m256i(r, e);
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm_maskstore_epi32() {
+    const fn test_mm_maskstore_epi32() {
         let a = _mm_setr_epi32(1, 2, 3, 4);
         let mut arr = [-1, -1, -1, -1];
         let mask = _mm_setr_epi32(-1, 0, 0, -1);
-        _mm_maskstore_epi32(arr.as_mut_ptr(), mask, a);
+        unsafe {
+            _mm_maskstore_epi32(arr.as_mut_ptr(), mask, a);
+        }
         let e = [1, -1, -1, 4];
         assert_eq!(arr, e);
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm256_maskstore_epi32() {
+    const fn test_mm256_maskstore_epi32() {
         let a = _mm256_setr_epi32(1, 0x6d726f, 3, 42, 0x777161, 6, 7, 8);
         let mut arr = [-1, -1, -1, 0x776173, -1, 0x68657265, -1, -1];
         let mask = _mm256_setr_epi32(-1, 0, 0, -1, 0, -1, -1, 0);
-        _mm256_maskstore_epi32(arr.as_mut_ptr(), mask, a);
+        unsafe {
+            _mm256_maskstore_epi32(arr.as_mut_ptr(), mask, a);
+        }
         let e = [1, -1, -1, 42, -1, 6, 7, -1];
         assert_eq!(arr, e);
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm_maskstore_epi64() {
+    const fn test_mm_maskstore_epi64() {
         let a = _mm_setr_epi64x(1_i64, 2_i64);
         let mut arr = [-1_i64, -1_i64];
         let mask = _mm_setr_epi64x(0, -1);
-        _mm_maskstore_epi64(arr.as_mut_ptr(), mask, a);
+        unsafe {
+            _mm_maskstore_epi64(arr.as_mut_ptr(), mask, a);
+        }
         let e = [-1, 2];
         assert_eq!(arr, e);
     }
 
     #[simd_test(enable = "avx2")]
-    const unsafe fn test_mm256_maskstore_epi64() {
+    const fn test_mm256_maskstore_epi64() {
         let a = _mm256_setr_epi64x(1_i64, 2_i64, 3_i64, 4_i64);
         let mut arr = [-1_i64, -1_i64, -1_i64, -1_i64];
         let mask = _mm256_setr_epi64x(0, -1, -1, 0);
-        _mm256_maskstore_epi64(arr.as_mut_ptr(), mask, a);
+        unsafe {
+            _mm256_maskstore_epi64(arr.as_mut_ptr(), mask, a);
+        }
         let e = [-1, 2, 3, -1];
         assert_eq!(arr, e);
     }
@@ -5301,9 +5309,9 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_stream_load_si256() {
+    fn test_mm256_stream_load_si256() {
         let a = _mm256_set_epi64x(5, 6, 7, 8);
-        let r = _mm256_stream_load_si256(core::ptr::addr_of!(a) as *const _);
+        let r = unsafe { _mm256_stream_load_si256(core::ptr::addr_of!(a) as *const _) };
         assert_eq_m256i(a, r);
     }
 
@@ -5506,88 +5514,98 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm_i32gather_epi32() {
+    fn test_mm_i32gather_epi32() {
         let arr: [i32; 128] = core::array::from_fn(|i| i as i32);
         // A multiplier of 4 is word-addressing
-        let r = _mm_i32gather_epi32::<4>(arr.as_ptr(), _mm_setr_epi32(0, 16, 32, 48));
+        let r = unsafe { _mm_i32gather_epi32::<4>(arr.as_ptr(), _mm_setr_epi32(0, 16, 32, 48)) };
         assert_eq_m128i(r, _mm_setr_epi32(0, 16, 32, 48));
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm_mask_i32gather_epi32() {
+    fn test_mm_mask_i32gather_epi32() {
         let arr: [i32; 128] = core::array::from_fn(|i| i as i32);
         // A multiplier of 4 is word-addressing
-        let r = _mm_mask_i32gather_epi32::<4>(
-            _mm_set1_epi32(256),
-            arr.as_ptr(),
-            _mm_setr_epi32(0, 16, 64, 96),
-            _mm_setr_epi32(-1, -1, -1, 0),
-        );
+        let r = unsafe {
+            _mm_mask_i32gather_epi32::<4>(
+                _mm_set1_epi32(256),
+                arr.as_ptr(),
+                _mm_setr_epi32(0, 16, 64, 96),
+                _mm_setr_epi32(-1, -1, -1, 0),
+            )
+        };
         assert_eq_m128i(r, _mm_setr_epi32(0, 16, 64, 256));
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_i32gather_epi32() {
+    fn test_mm256_i32gather_epi32() {
         let arr: [i32; 128] = core::array::from_fn(|i| i as i32);
         // A multiplier of 4 is word-addressing
-        let r =
-            _mm256_i32gather_epi32::<4>(arr.as_ptr(), _mm256_setr_epi32(0, 16, 32, 48, 1, 2, 3, 4));
+        let r = unsafe {
+            _mm256_i32gather_epi32::<4>(arr.as_ptr(), _mm256_setr_epi32(0, 16, 32, 48, 1, 2, 3, 4))
+        };
         assert_eq_m256i(r, _mm256_setr_epi32(0, 16, 32, 48, 1, 2, 3, 4));
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_mask_i32gather_epi32() {
+    fn test_mm256_mask_i32gather_epi32() {
         let arr: [i32; 128] = core::array::from_fn(|i| i as i32);
         // A multiplier of 4 is word-addressing
-        let r = _mm256_mask_i32gather_epi32::<4>(
-            _mm256_set1_epi32(256),
-            arr.as_ptr(),
-            _mm256_setr_epi32(0, 16, 64, 96, 0, 0, 0, 0),
-            _mm256_setr_epi32(-1, -1, -1, 0, 0, 0, 0, 0),
-        );
+        let r = unsafe {
+            _mm256_mask_i32gather_epi32::<4>(
+                _mm256_set1_epi32(256),
+                arr.as_ptr(),
+                _mm256_setr_epi32(0, 16, 64, 96, 0, 0, 0, 0),
+                _mm256_setr_epi32(-1, -1, -1, 0, 0, 0, 0, 0),
+            )
+        };
         assert_eq_m256i(r, _mm256_setr_epi32(0, 16, 64, 256, 256, 256, 256, 256));
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm_i32gather_ps() {
+    fn test_mm_i32gather_ps() {
         let arr: [f32; 128] = core::array::from_fn(|i| i as f32);
         // A multiplier of 4 is word-addressing for f32s
-        let r = _mm_i32gather_ps::<4>(arr.as_ptr(), _mm_setr_epi32(0, 16, 32, 48));
+        let r = unsafe { _mm_i32gather_ps::<4>(arr.as_ptr(), _mm_setr_epi32(0, 16, 32, 48)) };
         assert_eq_m128(r, _mm_setr_ps(0.0, 16.0, 32.0, 48.0));
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm_mask_i32gather_ps() {
+    fn test_mm_mask_i32gather_ps() {
         let arr: [f32; 128] = core::array::from_fn(|i| i as f32);
         // A multiplier of 4 is word-addressing for f32s
-        let r = _mm_mask_i32gather_ps::<4>(
-            _mm_set1_ps(256.0),
-            arr.as_ptr(),
-            _mm_setr_epi32(0, 16, 64, 96),
-            _mm_setr_ps(-1.0, -1.0, -1.0, 0.0),
-        );
+        let r = unsafe {
+            _mm_mask_i32gather_ps::<4>(
+                _mm_set1_ps(256.0),
+                arr.as_ptr(),
+                _mm_setr_epi32(0, 16, 64, 96),
+                _mm_setr_ps(-1.0, -1.0, -1.0, 0.0),
+            )
+        };
         assert_eq_m128(r, _mm_setr_ps(0.0, 16.0, 64.0, 256.0));
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_i32gather_ps() {
+    fn test_mm256_i32gather_ps() {
         let arr: [f32; 128] = core::array::from_fn(|i| i as f32);
         // A multiplier of 4 is word-addressing for f32s
-        let r =
-            _mm256_i32gather_ps::<4>(arr.as_ptr(), _mm256_setr_epi32(0, 16, 32, 48, 1, 2, 3, 4));
+        let r = unsafe {
+            _mm256_i32gather_ps::<4>(arr.as_ptr(), _mm256_setr_epi32(0, 16, 32, 48, 1, 2, 3, 4))
+        };
         assert_eq_m256(r, _mm256_setr_ps(0.0, 16.0, 32.0, 48.0, 1.0, 2.0, 3.0, 4.0));
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_mask_i32gather_ps() {
+    fn test_mm256_mask_i32gather_ps() {
         let arr: [f32; 128] = core::array::from_fn(|i| i as f32);
         // A multiplier of 4 is word-addressing for f32s
-        let r = _mm256_mask_i32gather_ps::<4>(
-            _mm256_set1_ps(256.0),
-            arr.as_ptr(),
-            _mm256_setr_epi32(0, 16, 64, 96, 0, 0, 0, 0),
-            _mm256_setr_ps(-1.0, -1.0, -1.0, 0.0, 0.0, 0.0, 0.0, 0.0),
-        );
+        let r = unsafe {
+            _mm256_mask_i32gather_ps::<4>(
+                _mm256_set1_ps(256.0),
+                arr.as_ptr(),
+                _mm256_setr_epi32(0, 16, 64, 96, 0, 0, 0, 0),
+                _mm256_setr_ps(-1.0, -1.0, -1.0, 0.0, 0.0, 0.0, 0.0, 0.0),
+            )
+        };
         assert_eq_m256(
             r,
             _mm256_setr_ps(0.0, 16.0, 64.0, 256.0, 256.0, 256.0, 256.0, 256.0),
@@ -5595,254 +5613,282 @@ mod tests {
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm_i32gather_epi64() {
+    fn test_mm_i32gather_epi64() {
         let arr: [i64; 128] = core::array::from_fn(|i| i as i64);
         // A multiplier of 8 is word-addressing for i64s
-        let r = _mm_i32gather_epi64::<8>(arr.as_ptr(), _mm_setr_epi32(0, 16, 0, 0));
+        let r = unsafe { _mm_i32gather_epi64::<8>(arr.as_ptr(), _mm_setr_epi32(0, 16, 0, 0)) };
         assert_eq_m128i(r, _mm_setr_epi64x(0, 16));
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm_mask_i32gather_epi64() {
+    fn test_mm_mask_i32gather_epi64() {
         let arr: [i64; 128] = core::array::from_fn(|i| i as i64);
         // A multiplier of 8 is word-addressing for i64s
-        let r = _mm_mask_i32gather_epi64::<8>(
-            _mm_set1_epi64x(256),
-            arr.as_ptr(),
-            _mm_setr_epi32(16, 16, 16, 16),
-            _mm_setr_epi64x(-1, 0),
-        );
+        let r = unsafe {
+            _mm_mask_i32gather_epi64::<8>(
+                _mm_set1_epi64x(256),
+                arr.as_ptr(),
+                _mm_setr_epi32(16, 16, 16, 16),
+                _mm_setr_epi64x(-1, 0),
+            )
+        };
         assert_eq_m128i(r, _mm_setr_epi64x(16, 256));
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_i32gather_epi64() {
+    fn test_mm256_i32gather_epi64() {
         let arr: [i64; 128] = core::array::from_fn(|i| i as i64);
         // A multiplier of 8 is word-addressing for i64s
-        let r = _mm256_i32gather_epi64::<8>(arr.as_ptr(), _mm_setr_epi32(0, 16, 32, 48));
+        let r = unsafe { _mm256_i32gather_epi64::<8>(arr.as_ptr(), _mm_setr_epi32(0, 16, 32, 48)) };
         assert_eq_m256i(r, _mm256_setr_epi64x(0, 16, 32, 48));
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_mask_i32gather_epi64() {
+    fn test_mm256_mask_i32gather_epi64() {
         let arr: [i64; 128] = core::array::from_fn(|i| i as i64);
         // A multiplier of 8 is word-addressing for i64s
-        let r = _mm256_mask_i32gather_epi64::<8>(
-            _mm256_set1_epi64x(256),
-            arr.as_ptr(),
-            _mm_setr_epi32(0, 16, 64, 96),
-            _mm256_setr_epi64x(-1, -1, -1, 0),
-        );
+        let r = unsafe {
+            _mm256_mask_i32gather_epi64::<8>(
+                _mm256_set1_epi64x(256),
+                arr.as_ptr(),
+                _mm_setr_epi32(0, 16, 64, 96),
+                _mm256_setr_epi64x(-1, -1, -1, 0),
+            )
+        };
         assert_eq_m256i(r, _mm256_setr_epi64x(0, 16, 64, 256));
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm_i32gather_pd() {
+    fn test_mm_i32gather_pd() {
         let arr: [f64; 128] = core::array::from_fn(|i| i as f64);
         // A multiplier of 8 is word-addressing for f64s
-        let r = _mm_i32gather_pd::<8>(arr.as_ptr(), _mm_setr_epi32(0, 16, 0, 0));
+        let r = unsafe { _mm_i32gather_pd::<8>(arr.as_ptr(), _mm_setr_epi32(0, 16, 0, 0)) };
         assert_eq_m128d(r, _mm_setr_pd(0.0, 16.0));
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm_mask_i32gather_pd() {
+    fn test_mm_mask_i32gather_pd() {
         let arr: [f64; 128] = core::array::from_fn(|i| i as f64);
         // A multiplier of 8 is word-addressing for f64s
-        let r = _mm_mask_i32gather_pd::<8>(
-            _mm_set1_pd(256.0),
-            arr.as_ptr(),
-            _mm_setr_epi32(16, 16, 16, 16),
-            _mm_setr_pd(-1.0, 0.0),
-        );
+        let r = unsafe {
+            _mm_mask_i32gather_pd::<8>(
+                _mm_set1_pd(256.0),
+                arr.as_ptr(),
+                _mm_setr_epi32(16, 16, 16, 16),
+                _mm_setr_pd(-1.0, 0.0),
+            )
+        };
         assert_eq_m128d(r, _mm_setr_pd(16.0, 256.0));
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_i32gather_pd() {
+    fn test_mm256_i32gather_pd() {
         let arr: [f64; 128] = core::array::from_fn(|i| i as f64);
         // A multiplier of 8 is word-addressing for f64s
-        let r = _mm256_i32gather_pd::<8>(arr.as_ptr(), _mm_setr_epi32(0, 16, 32, 48));
+        let r = unsafe { _mm256_i32gather_pd::<8>(arr.as_ptr(), _mm_setr_epi32(0, 16, 32, 48)) };
         assert_eq_m256d(r, _mm256_setr_pd(0.0, 16.0, 32.0, 48.0));
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_mask_i32gather_pd() {
+    fn test_mm256_mask_i32gather_pd() {
         let arr: [f64; 128] = core::array::from_fn(|i| i as f64);
         // A multiplier of 8 is word-addressing for f64s
-        let r = _mm256_mask_i32gather_pd::<8>(
-            _mm256_set1_pd(256.0),
-            arr.as_ptr(),
-            _mm_setr_epi32(0, 16, 64, 96),
-            _mm256_setr_pd(-1.0, -1.0, -1.0, 0.0),
-        );
+        let r = unsafe {
+            _mm256_mask_i32gather_pd::<8>(
+                _mm256_set1_pd(256.0),
+                arr.as_ptr(),
+                _mm_setr_epi32(0, 16, 64, 96),
+                _mm256_setr_pd(-1.0, -1.0, -1.0, 0.0),
+            )
+        };
         assert_eq_m256d(r, _mm256_setr_pd(0.0, 16.0, 64.0, 256.0));
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm_i64gather_epi32() {
+    fn test_mm_i64gather_epi32() {
         let arr: [i32; 128] = core::array::from_fn(|i| i as i32);
         // A multiplier of 4 is word-addressing
-        let r = _mm_i64gather_epi32::<4>(arr.as_ptr(), _mm_setr_epi64x(0, 16));
+        let r = unsafe { _mm_i64gather_epi32::<4>(arr.as_ptr(), _mm_setr_epi64x(0, 16)) };
         assert_eq_m128i(r, _mm_setr_epi32(0, 16, 0, 0));
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm_mask_i64gather_epi32() {
+    fn test_mm_mask_i64gather_epi32() {
         let arr: [i32; 128] = core::array::from_fn(|i| i as i32);
         // A multiplier of 4 is word-addressing
-        let r = _mm_mask_i64gather_epi32::<4>(
-            _mm_set1_epi32(256),
-            arr.as_ptr(),
-            _mm_setr_epi64x(0, 16),
-            _mm_setr_epi32(-1, 0, -1, 0),
-        );
+        let r = unsafe {
+            _mm_mask_i64gather_epi32::<4>(
+                _mm_set1_epi32(256),
+                arr.as_ptr(),
+                _mm_setr_epi64x(0, 16),
+                _mm_setr_epi32(-1, 0, -1, 0),
+            )
+        };
         assert_eq_m128i(r, _mm_setr_epi32(0, 256, 0, 0));
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_i64gather_epi32() {
+    fn test_mm256_i64gather_epi32() {
         let arr: [i32; 128] = core::array::from_fn(|i| i as i32);
         // A multiplier of 4 is word-addressing
-        let r = _mm256_i64gather_epi32::<4>(arr.as_ptr(), _mm256_setr_epi64x(0, 16, 32, 48));
+        let r =
+            unsafe { _mm256_i64gather_epi32::<4>(arr.as_ptr(), _mm256_setr_epi64x(0, 16, 32, 48)) };
         assert_eq_m128i(r, _mm_setr_epi32(0, 16, 32, 48));
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_mask_i64gather_epi32() {
+    fn test_mm256_mask_i64gather_epi32() {
         let arr: [i32; 128] = core::array::from_fn(|i| i as i32);
         // A multiplier of 4 is word-addressing
-        let r = _mm256_mask_i64gather_epi32::<4>(
-            _mm_set1_epi32(256),
-            arr.as_ptr(),
-            _mm256_setr_epi64x(0, 16, 64, 96),
-            _mm_setr_epi32(-1, -1, -1, 0),
-        );
+        let r = unsafe {
+            _mm256_mask_i64gather_epi32::<4>(
+                _mm_set1_epi32(256),
+                arr.as_ptr(),
+                _mm256_setr_epi64x(0, 16, 64, 96),
+                _mm_setr_epi32(-1, -1, -1, 0),
+            )
+        };
         assert_eq_m128i(r, _mm_setr_epi32(0, 16, 64, 256));
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm_i64gather_ps() {
+    fn test_mm_i64gather_ps() {
         let arr: [f32; 128] = core::array::from_fn(|i| i as f32);
         // A multiplier of 4 is word-addressing for f32s
-        let r = _mm_i64gather_ps::<4>(arr.as_ptr(), _mm_setr_epi64x(0, 16));
+        let r = unsafe { _mm_i64gather_ps::<4>(arr.as_ptr(), _mm_setr_epi64x(0, 16)) };
         assert_eq_m128(r, _mm_setr_ps(0.0, 16.0, 0.0, 0.0));
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm_mask_i64gather_ps() {
+    fn test_mm_mask_i64gather_ps() {
         let arr: [f32; 128] = core::array::from_fn(|i| i as f32);
         // A multiplier of 4 is word-addressing for f32s
-        let r = _mm_mask_i64gather_ps::<4>(
-            _mm_set1_ps(256.0),
-            arr.as_ptr(),
-            _mm_setr_epi64x(0, 16),
-            _mm_setr_ps(-1.0, 0.0, -1.0, 0.0),
-        );
+        let r = unsafe {
+            _mm_mask_i64gather_ps::<4>(
+                _mm_set1_ps(256.0),
+                arr.as_ptr(),
+                _mm_setr_epi64x(0, 16),
+                _mm_setr_ps(-1.0, 0.0, -1.0, 0.0),
+            )
+        };
         assert_eq_m128(r, _mm_setr_ps(0.0, 256.0, 0.0, 0.0));
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_i64gather_ps() {
+    fn test_mm256_i64gather_ps() {
         let arr: [f32; 128] = core::array::from_fn(|i| i as f32);
         // A multiplier of 4 is word-addressing for f32s
-        let r = _mm256_i64gather_ps::<4>(arr.as_ptr(), _mm256_setr_epi64x(0, 16, 32, 48));
+        let r =
+            unsafe { _mm256_i64gather_ps::<4>(arr.as_ptr(), _mm256_setr_epi64x(0, 16, 32, 48)) };
         assert_eq_m128(r, _mm_setr_ps(0.0, 16.0, 32.0, 48.0));
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_mask_i64gather_ps() {
+    fn test_mm256_mask_i64gather_ps() {
         let arr: [f32; 128] = core::array::from_fn(|i| i as f32);
         // A multiplier of 4 is word-addressing for f32s
-        let r = _mm256_mask_i64gather_ps::<4>(
-            _mm_set1_ps(256.0),
-            arr.as_ptr(),
-            _mm256_setr_epi64x(0, 16, 64, 96),
-            _mm_setr_ps(-1.0, -1.0, -1.0, 0.0),
-        );
+        let r = unsafe {
+            _mm256_mask_i64gather_ps::<4>(
+                _mm_set1_ps(256.0),
+                arr.as_ptr(),
+                _mm256_setr_epi64x(0, 16, 64, 96),
+                _mm_setr_ps(-1.0, -1.0, -1.0, 0.0),
+            )
+        };
         assert_eq_m128(r, _mm_setr_ps(0.0, 16.0, 64.0, 256.0));
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm_i64gather_epi64() {
+    fn test_mm_i64gather_epi64() {
         let arr: [i64; 128] = core::array::from_fn(|i| i as i64);
         // A multiplier of 8 is word-addressing for i64s
-        let r = _mm_i64gather_epi64::<8>(arr.as_ptr(), _mm_setr_epi64x(0, 16));
+        let r = unsafe { _mm_i64gather_epi64::<8>(arr.as_ptr(), _mm_setr_epi64x(0, 16)) };
         assert_eq_m128i(r, _mm_setr_epi64x(0, 16));
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm_mask_i64gather_epi64() {
+    fn test_mm_mask_i64gather_epi64() {
         let arr: [i64; 128] = core::array::from_fn(|i| i as i64);
         // A multiplier of 8 is word-addressing for i64s
-        let r = _mm_mask_i64gather_epi64::<8>(
-            _mm_set1_epi64x(256),
-            arr.as_ptr(),
-            _mm_setr_epi64x(16, 16),
-            _mm_setr_epi64x(-1, 0),
-        );
+        let r = unsafe {
+            _mm_mask_i64gather_epi64::<8>(
+                _mm_set1_epi64x(256),
+                arr.as_ptr(),
+                _mm_setr_epi64x(16, 16),
+                _mm_setr_epi64x(-1, 0),
+            )
+        };
         assert_eq_m128i(r, _mm_setr_epi64x(16, 256));
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_i64gather_epi64() {
+    fn test_mm256_i64gather_epi64() {
         let arr: [i64; 128] = core::array::from_fn(|i| i as i64);
         // A multiplier of 8 is word-addressing for i64s
-        let r = _mm256_i64gather_epi64::<8>(arr.as_ptr(), _mm256_setr_epi64x(0, 16, 32, 48));
+        let r =
+            unsafe { _mm256_i64gather_epi64::<8>(arr.as_ptr(), _mm256_setr_epi64x(0, 16, 32, 48)) };
         assert_eq_m256i(r, _mm256_setr_epi64x(0, 16, 32, 48));
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_mask_i64gather_epi64() {
+    fn test_mm256_mask_i64gather_epi64() {
         let arr: [i64; 128] = core::array::from_fn(|i| i as i64);
         // A multiplier of 8 is word-addressing for i64s
-        let r = _mm256_mask_i64gather_epi64::<8>(
-            _mm256_set1_epi64x(256),
-            arr.as_ptr(),
-            _mm256_setr_epi64x(0, 16, 64, 96),
-            _mm256_setr_epi64x(-1, -1, -1, 0),
-        );
+        let r = unsafe {
+            _mm256_mask_i64gather_epi64::<8>(
+                _mm256_set1_epi64x(256),
+                arr.as_ptr(),
+                _mm256_setr_epi64x(0, 16, 64, 96),
+                _mm256_setr_epi64x(-1, -1, -1, 0),
+            )
+        };
         assert_eq_m256i(r, _mm256_setr_epi64x(0, 16, 64, 256));
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm_i64gather_pd() {
+    fn test_mm_i64gather_pd() {
         let arr: [f64; 128] = core::array::from_fn(|i| i as f64);
         // A multiplier of 8 is word-addressing for f64s
-        let r = _mm_i64gather_pd::<8>(arr.as_ptr(), _mm_setr_epi64x(0, 16));
+        let r = unsafe { _mm_i64gather_pd::<8>(arr.as_ptr(), _mm_setr_epi64x(0, 16)) };
         assert_eq_m128d(r, _mm_setr_pd(0.0, 16.0));
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm_mask_i64gather_pd() {
+    fn test_mm_mask_i64gather_pd() {
         let arr: [f64; 128] = core::array::from_fn(|i| i as f64);
         // A multiplier of 8 is word-addressing for f64s
-        let r = _mm_mask_i64gather_pd::<8>(
-            _mm_set1_pd(256.0),
-            arr.as_ptr(),
-            _mm_setr_epi64x(16, 16),
-            _mm_setr_pd(-1.0, 0.0),
-        );
+        let r = unsafe {
+            _mm_mask_i64gather_pd::<8>(
+                _mm_set1_pd(256.0),
+                arr.as_ptr(),
+                _mm_setr_epi64x(16, 16),
+                _mm_setr_pd(-1.0, 0.0),
+            )
+        };
         assert_eq_m128d(r, _mm_setr_pd(16.0, 256.0));
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_i64gather_pd() {
+    fn test_mm256_i64gather_pd() {
         let arr: [f64; 128] = core::array::from_fn(|i| i as f64);
         // A multiplier of 8 is word-addressing for f64s
-        let r = _mm256_i64gather_pd::<8>(arr.as_ptr(), _mm256_setr_epi64x(0, 16, 32, 48));
+        let r =
+            unsafe { _mm256_i64gather_pd::<8>(arr.as_ptr(), _mm256_setr_epi64x(0, 16, 32, 48)) };
         assert_eq_m256d(r, _mm256_setr_pd(0.0, 16.0, 32.0, 48.0));
     }
 
     #[simd_test(enable = "avx2")]
-    unsafe fn test_mm256_mask_i64gather_pd() {
+    fn test_mm256_mask_i64gather_pd() {
         let arr: [f64; 128] = core::array::from_fn(|i| i as f64);
         // A multiplier of 8 is word-addressing for f64s
-        let r = _mm256_mask_i64gather_pd::<8>(
-            _mm256_set1_pd(256.0),
-            arr.as_ptr(),
-            _mm256_setr_epi64x(0, 16, 64, 96),
-            _mm256_setr_pd(-1.0, -1.0, -1.0, 0.0),
-        );
+        let r = unsafe {
+            _mm256_mask_i64gather_pd::<8>(
+                _mm256_set1_pd(256.0),
+                arr.as_ptr(),
+                _mm256_setr_epi64x(0, 16, 64, 96),
+                _mm256_setr_pd(-1.0, -1.0, -1.0, 0.0),
+            )
+        };
         assert_eq_m256d(r, _mm256_setr_pd(0.0, 16.0, 64.0, 256.0));
     }
 
diff --git a/library/stdarch/crates/core_arch/src/x86/avx512bf16.rs b/library/stdarch/crates/core_arch/src/x86/avx512bf16.rs
index 83dbc540a0c8..66eef063eed8 100644
--- a/library/stdarch/crates/core_arch/src/x86/avx512bf16.rs
+++ b/library/stdarch/crates/core_arch/src/x86/avx512bf16.rs
@@ -593,7 +593,7 @@ pub fn _mm_cvtness_sbh(a: f32) -> bf16 {
 
 #[cfg(test)]
 mod tests {
-    use crate::core_arch::simd::u16x4;
+    use crate::core_arch::simd::{f32x4, f32x8, f32x16, u16x4, u16x8, u16x16, u16x32};
     use crate::{
         core_arch::x86::*,
         mem::{transmute, transmute_copy},
@@ -601,13 +601,13 @@ mod tests {
     use stdarch_test::simd_test;
 
     #[simd_test(enable = "avx512bf16,avx512vl")]
-    unsafe fn test_mm_cvtne2ps_pbh() {
+    fn test_mm_cvtne2ps_pbh() {
         let a_array = [178.125_f32, 10.5_f32, 3.75_f32, 50.25_f32];
         let b_array = [-178.125_f32, -10.5_f32, -3.75_f32, -50.25_f32];
-        let a: __m128 = transmute(a_array);
-        let b: __m128 = transmute(b_array);
+        let a = f32x4::from_array(a_array).as_m128();
+        let b = f32x4::from_array(b_array).as_m128();
         let c: __m128bh = _mm_cvtne2ps_pbh(a, b);
-        let result: [u16; 8] = transmute(c.as_u16x8());
+        let result = *c.as_u16x8().as_array();
         #[rustfmt::skip]
         let expected_result: [u16; 8] = [
             0b1_10000110_0110010,
@@ -623,7 +623,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bf16,avx512vl")]
-    unsafe fn test_mm_mask_cvtne2ps_pbh() {
+    fn test_mm_mask_cvtne2ps_pbh() {
         let a_array = [178.125_f32, 10.5_f32, 3.75_f32, 50.25_f32];
         let b_array = [-178.125_f32, -10.5_f32, -3.75_f32, -50.25_f32];
         #[rustfmt::skip]
@@ -637,12 +637,12 @@ mod tests {
             0b0_10000000_1110000,
             0b0_10000100_1001001,
         ];
-        let src: __m128bh = transmute(src_array);
-        let a: __m128 = transmute(a_array);
-        let b: __m128 = transmute(b_array);
+        let src = u16x8::from_array(src_array).as_m128bh();
+        let a = f32x4::from_array(a_array).as_m128();
+        let b = f32x4::from_array(b_array).as_m128();
         let k: __mmask8 = 0b1111_1111;
         let c: __m128bh = _mm_mask_cvtne2ps_pbh(src, k, a, b);
-        let result: [u16; 8] = transmute(c.as_u16x8());
+        let result = *c.as_u16x8().as_array();
         #[rustfmt::skip]
         let expected_result: [u16; 8] = [
             0b1_10000110_0110010,
@@ -657,20 +657,20 @@ mod tests {
         assert_eq!(result, expected_result);
         let k = 0b0000_0000;
         let c = _mm_mask_cvtne2ps_pbh(src, k, a, b);
-        let result: [u16; 8] = transmute(c.as_u16x8());
+        let result = *c.as_u16x8().as_array();
         let expected_result = src_array;
         assert_eq!(result, expected_result);
     }
 
     #[simd_test(enable = "avx512bf16,avx512vl")]
-    unsafe fn test_mm_maskz_cvtne2ps_pbh() {
+    fn test_mm_maskz_cvtne2ps_pbh() {
         let a_array = [178.125_f32, 10.5_f32, 3.75_f32, 50.25_f32];
         let b_array = [-178.125_f32, -10.5_f32, -3.75_f32, -50.25_f32];
-        let a: __m128 = transmute(a_array);
-        let b: __m128 = transmute(b_array);
+        let a = f32x4::from_array(a_array).as_m128();
+        let b = f32x4::from_array(b_array).as_m128();
         let k: __mmask8 = 0b1111_1111;
         let c: __m128bh = _mm_maskz_cvtne2ps_pbh(k, a, b);
-        let result: [u16; 8] = transmute(c.as_u16x8());
+        let result = *c.as_u16x8().as_array();
         #[rustfmt::skip]
         let expected_result: [u16; 8] = [
             0b1_10000110_0110010,
@@ -685,7 +685,7 @@ mod tests {
         assert_eq!(result, expected_result);
         let k = 0b0011_1100;
         let c = _mm_maskz_cvtne2ps_pbh(k, a, b);
-        let result: [u16; 8] = transmute(c.as_u16x8());
+        let result = *c.as_u16x8().as_array();
         #[rustfmt::skip]
         let expected_result: [u16; 8] = [
             0,
@@ -701,7 +701,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bf16,avx512vl")]
-    unsafe fn test_mm256_cvtne2ps_pbh() {
+    fn test_mm256_cvtne2ps_pbh() {
         #[rustfmt::skip]
         let a_array = [
             178.125_f32,
@@ -723,10 +723,10 @@ mod tests {
             -1000.158_f32,
             -575.575_f32,
         ];
-        let a: __m256 = transmute(a_array);
-        let b: __m256 = transmute(b_array);
+        let a = f32x8::from_array(a_array).as_m256();
+        let b = f32x8::from_array(b_array).as_m256();
         let c: __m256bh = _mm256_cvtne2ps_pbh(a, b);
-        let result: [u16; 16] = transmute(c.as_u16x16());
+        let result = *c.as_u16x16().as_array();
         #[rustfmt::skip]
         let expected_result: [u16; 16] = [
             0b1_10000110_0110010,
@@ -750,7 +750,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bf16,avx512vl")]
-    unsafe fn test_mm256_mask_cvtne2ps_pbh() {
+    fn test_mm256_mask_cvtne2ps_pbh() {
         #[rustfmt::skip]
         let a_array = [
             178.125_f32,
@@ -790,12 +790,12 @@ mod tests {
             0b0_10000000_1110000,
             0b0_10000100_1001001,
         ];
-        let src: __m256bh = transmute(src_array);
-        let a: __m256 = transmute(a_array);
-        let b: __m256 = transmute(b_array);
+        let src = u16x16::from_array(src_array).as_m256bh();
+        let a = f32x8::from_array(a_array).as_m256();
+        let b = f32x8::from_array(b_array).as_m256();
         let k: __mmask16 = 0xffff;
         let c: __m256bh = _mm256_mask_cvtne2ps_pbh(src, k, a, b);
-        let result: [u16; 16] = transmute(c.as_u16x16());
+        let result = *c.as_u16x16().as_array();
         #[rustfmt::skip]
         let expected_result: [u16; 16] = [
             0b1_10000110_0110010,
@@ -818,13 +818,13 @@ mod tests {
         assert_eq!(result, expected_result);
         let k: __mmask16 = 0;
         let c: __m256bh = _mm256_mask_cvtne2ps_pbh(src, k, a, b);
-        let result: [u16; 16] = transmute(c.as_u16x16());
+        let result = *c.as_u16x16().as_array();
         let expected_result = src_array;
         assert_eq!(result, expected_result);
     }
 
     #[simd_test(enable = "avx512bf16,avx512vl")]
-    unsafe fn test_mm256_maskz_cvtne2ps_pbh() {
+    fn test_mm256_maskz_cvtne2ps_pbh() {
         #[rustfmt::skip]
         let a_array = [
             178.125_f32,
@@ -846,11 +846,11 @@ mod tests {
             -1000.158_f32,
             -575.575_f32,
         ];
-        let a: __m256 = transmute(a_array);
-        let b: __m256 = transmute(b_array);
+        let a = f32x8::from_array(a_array).as_m256();
+        let b = f32x8::from_array(b_array).as_m256();
         let k: __mmask16 = 0xffff;
         let c: __m256bh = _mm256_maskz_cvtne2ps_pbh(k, a, b);
-        let result: [u16; 16] = transmute(c.as_u16x16());
+        let result = *c.as_u16x16().as_array();
         #[rustfmt::skip]
         let expected_result: [u16; 16] = [
             0b1_10000110_0110010,
@@ -873,7 +873,7 @@ mod tests {
         assert_eq!(result, expected_result);
         let k: __mmask16 = 0b0110_1100_0011_0110;
         let c: __m256bh = _mm256_maskz_cvtne2ps_pbh(k, a, b);
-        let result: [u16; 16] = transmute(c.as_u16x16());
+        let result = *c.as_u16x16().as_array();
         #[rustfmt::skip]
         let expected_result: [u16; 16] = [
             0,
@@ -897,7 +897,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bf16,avx512f")]
-    unsafe fn test_mm512_cvtne2ps_pbh() {
+    fn test_mm512_cvtne2ps_pbh() {
         #[rustfmt::skip]
         let a_array = [
             178.125_f32,
@@ -935,10 +935,10 @@ mod tests {
             -1000.158_f32,
             -575.575_f32,
         ];
-        let a: __m512 = transmute(a_array);
-        let b: __m512 = transmute(b_array);
+        let a = f32x16::from_array(a_array).as_m512();
+        let b = f32x16::from_array(b_array).as_m512();
         let c: __m512bh = _mm512_cvtne2ps_pbh(a, b);
-        let result: [u16; 32] = transmute(c.as_u16x32());
+        let result = *c.as_u16x32().as_array();
         #[rustfmt::skip]
         let expected_result: [u16; 32] = [
             0b1_10000110_0110010,
@@ -978,7 +978,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bf16,avx512f")]
-    unsafe fn test_mm512_mask_cvtne2ps_pbh() {
+    fn test_mm512_mask_cvtne2ps_pbh() {
         #[rustfmt::skip]
         let a_array = [
             178.125_f32,
@@ -1050,12 +1050,12 @@ mod tests {
             0b0_10000000_1110000,
             0b0_10000100_1001001,
         ];
-        let src: __m512bh = transmute(src_array);
-        let a: __m512 = transmute(a_array);
-        let b: __m512 = transmute(b_array);
+        let src = u16x32::from_array(src_array).as_m512bh();
+        let a = f32x16::from_array(a_array).as_m512();
+        let b = f32x16::from_array(b_array).as_m512();
         let k: __mmask32 = 0xffffffff;
         let c: __m512bh = _mm512_mask_cvtne2ps_pbh(src, k, a, b);
-        let result: [u16; 32] = transmute(c.as_u16x32());
+        let result = *c.as_u16x32().as_array();
         #[rustfmt::skip]
         let expected_result: [u16; 32] = [
             0b1_10000110_0110010,
@@ -1094,13 +1094,13 @@ mod tests {
         assert_eq!(result, expected_result);
         let k: __mmask32 = 0;
         let c: __m512bh = _mm512_mask_cvtne2ps_pbh(src, k, a, b);
-        let result: [u16; 32] = transmute(c.as_u16x32());
+        let result = *c.as_u16x32().as_array();
         let expected_result = src_array;
         assert_eq!(result, expected_result);
     }
 
     #[simd_test(enable = "avx512bf16,avx512f")]
-    unsafe fn test_mm512_maskz_cvtne2ps_pbh() {
+    fn test_mm512_maskz_cvtne2ps_pbh() {
         #[rustfmt::skip]
         let a_array = [
             178.125_f32,
@@ -1138,11 +1138,11 @@ mod tests {
             -1000.158_f32,
             -575.575_f32,
         ];
-        let a: __m512 = transmute(a_array);
-        let b: __m512 = transmute(b_array);
+        let a = f32x16::from_array(a_array).as_m512();
+        let b = f32x16::from_array(b_array).as_m512();
         let k: __mmask32 = 0xffffffff;
         let c: __m512bh = _mm512_maskz_cvtne2ps_pbh(k, a, b);
-        let result: [u16; 32] = transmute(c.as_u16x32());
+        let result = *c.as_u16x32().as_array();
         #[rustfmt::skip]
         let expected_result: [u16; 32] = [
             0b1_10000110_0110010,
@@ -1181,7 +1181,7 @@ mod tests {
         assert_eq!(result, expected_result);
         let k: __mmask32 = 0b1100_1010_1001_0110_1010_0011_0101_0110;
         let c: __m512bh = _mm512_maskz_cvtne2ps_pbh(k, a, b);
-        let result: [u16; 32] = transmute(c.as_u16x32());
+        let result = *c.as_u16x32().as_array();
         #[rustfmt::skip]
         let expected_result: [u16; 32] = [
             0,
@@ -1221,7 +1221,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bf16,avx512vl")]
-    unsafe fn test_mm256_cvtneps_pbh() {
+    fn test_mm256_cvtneps_pbh() {
         #[rustfmt::skip]
         let a_array = [
             178.125_f32,
@@ -1233,9 +1233,9 @@ mod tests {
             1000.158_f32,
             575.575_f32,
         ];
-        let a: __m256 = transmute(a_array);
+        let a = f32x8::from_array(a_array).as_m256();
         let c: __m128bh = _mm256_cvtneps_pbh(a);
-        let result: [u16; 8] = transmute(c.as_u16x8());
+        let result = *c.as_u16x8().as_array();
         #[rustfmt::skip]
         let expected_result: [u16; 8] = [
             0b0_10000110_0110010,
@@ -1251,7 +1251,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bf16,avx512vl")]
-    unsafe fn test_mm256_mask_cvtneps_pbh() {
+    fn test_mm256_mask_cvtneps_pbh() {
         #[rustfmt::skip]
         let a_array = [
             178.125_f32,
@@ -1273,11 +1273,11 @@ mod tests {
             0b1_10001000_1111010,
             0b1_10001000_0010000,
         ];
-        let src: __m128bh = transmute(src_array);
-        let a: __m256 = transmute(a_array);
+        let src = u16x8::from_array(src_array).as_m128bh();
+        let a = f32x8::from_array(a_array).as_m256();
         let k: __mmask8 = 0xff;
         let b = _mm256_mask_cvtneps_pbh(src, k, a);
-        let result: [u16; 8] = transmute(b.as_u16x8());
+        let result = *b.as_u16x8().as_array();
         #[rustfmt::skip]
         let expected_result: [u16; 8] = [
             0b0_10000110_0110010,
@@ -1292,13 +1292,13 @@ mod tests {
         assert_eq!(result, expected_result);
         let k: __mmask8 = 0x0;
         let b: __m128bh = _mm256_mask_cvtneps_pbh(src, k, a);
-        let result: [u16; 8] = transmute(b.as_u16x8());
+        let result = *b.as_u16x8().as_array();
         let expected_result: [u16; 8] = src_array;
         assert_eq!(result, expected_result);
     }
 
     #[simd_test(enable = "avx512bf16,avx512vl")]
-    unsafe fn test_mm256_maskz_cvtneps_pbh() {
+    fn test_mm256_maskz_cvtneps_pbh() {
         #[rustfmt::skip]
         let a_array = [
             178.125_f32,
@@ -1310,10 +1310,10 @@ mod tests {
             1000.158_f32,
             575.575_f32,
         ];
-        let a: __m256 = transmute(a_array);
+        let a = f32x8::from_array(a_array).as_m256();
         let k: __mmask8 = 0xff;
         let b = _mm256_maskz_cvtneps_pbh(k, a);
-        let result: [u16; 8] = transmute(b.as_u16x8());
+        let result = *b.as_u16x8().as_array();
         #[rustfmt::skip]
         let expected_result: [u16; 8] = [
             0b0_10000110_0110010,
@@ -1328,14 +1328,14 @@ mod tests {
         assert_eq!(result, expected_result);
         let k: __mmask8 = 0x6;
         let b: __m128bh = _mm256_maskz_cvtneps_pbh(k, a);
-        let result: [u16; 8] = transmute(b.as_u16x8());
+        let result = *b.as_u16x8().as_array();
         let expected_result: [u16; 8] =
             [0, 0b0_10000010_0101000, 0b0_10000000_1110000, 0, 0, 0, 0, 0];
         assert_eq!(result, expected_result);
     }
 
     #[simd_test(enable = "avx512bf16,avx512f")]
-    unsafe fn test_mm512_cvtneps_pbh() {
+    fn test_mm512_cvtneps_pbh() {
         #[rustfmt::skip]
         let a_array = [
             178.125_f32,
@@ -1355,9 +1355,9 @@ mod tests {
             1000.158_f32,
             575.575_f32,
         ];
-        let a: __m512 = transmute(a_array);
+        let a = f32x16::from_array(a_array).as_m512();
         let c: __m256bh = _mm512_cvtneps_pbh(a);
-        let result: [u16; 16] = transmute(c.as_u16x16());
+        let result = *c.as_u16x16().as_array();
         #[rustfmt::skip]
         let expected_result: [u16; 16] = [
             0b0_10000110_0110010,
@@ -1381,7 +1381,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bf16,avx512f")]
-    unsafe fn test_mm512_mask_cvtneps_pbh() {
+    fn test_mm512_mask_cvtneps_pbh() {
         #[rustfmt::skip]
         let a_array = [
             178.125_f32,
@@ -1419,11 +1419,11 @@ mod tests {
             0b1_10001000_1111010,
             0b1_10001000_0010000,
         ];
-        let src: __m256bh = transmute(src_array);
-        let a: __m512 = transmute(a_array);
+        let src = u16x16::from_array(src_array).as_m256bh();
+        let a = f32x16::from_array(a_array).as_m512();
         let k: __mmask16 = 0xffff;
         let c: __m256bh = _mm512_mask_cvtneps_pbh(src, k, a);
-        let result: [u16; 16] = transmute(c.as_u16x16());
+        let result = *c.as_u16x16().as_array();
         #[rustfmt::skip]
         let expected_result: [u16; 16] = [
             0b0_10000110_0110010,
@@ -1446,13 +1446,13 @@ mod tests {
         assert_eq!(result, expected_result);
         let k: __mmask16 = 0;
         let c: __m256bh = _mm512_mask_cvtneps_pbh(src, k, a);
-        let result: [u16; 16] = transmute(c.as_u16x16());
+        let result = *c.as_u16x16().as_array();
         let expected_result = src_array;
         assert_eq!(result, expected_result);
     }
 
     #[simd_test(enable = "avx512bf16,avx512f")]
-    unsafe fn test_mm512_maskz_cvtneps_pbh() {
+    fn test_mm512_maskz_cvtneps_pbh() {
         #[rustfmt::skip]
         let a_array = [
             178.125_f32,
@@ -1472,10 +1472,10 @@ mod tests {
             1000.158_f32,
             575.575_f32,
         ];
-        let a: __m512 = transmute(a_array);
+        let a = f32x16::from_array(a_array).as_m512();
         let k: __mmask16 = 0xffff;
         let c: __m256bh = _mm512_maskz_cvtneps_pbh(k, a);
-        let result: [u16; 16] = transmute(c.as_u16x16());
+        let result = *c.as_u16x16().as_array();
         #[rustfmt::skip]
         let expected_result: [u16; 16] = [
             0b0_10000110_0110010,
@@ -1498,7 +1498,7 @@ mod tests {
         assert_eq!(result, expected_result);
         let k: __mmask16 = 0x653a;
         let c: __m256bh = _mm512_maskz_cvtneps_pbh(k, a);
-        let result: [u16; 16] = transmute(c.as_u16x16());
+        let result = *c.as_u16x16().as_array();
         #[rustfmt::skip]
         let expected_result: [u16; 16] = [
             0,
@@ -1522,74 +1522,74 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bf16,avx512vl")]
-    unsafe fn test_mm_dpbf16_ps() {
+    fn test_mm_dpbf16_ps() {
         let a_array = [8.5_f32, 10.5_f32, 3.75_f32, 50.25_f32];
         let b_array = [-1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32];
-        let a1: __m128 = transmute(a_array);
-        let b1: __m128 = transmute(b_array);
-        let src: __m128 = transmute([1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32]);
+        let a1 = f32x4::from_array(a_array).as_m128();
+        let b1 = f32x4::from_array(b_array).as_m128();
+        let src = f32x4::from_array([1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32]).as_m128();
         let a: __m128bh = _mm_cvtne2ps_pbh(a1, a1);
         let b: __m128bh = _mm_cvtne2ps_pbh(b1, b1);
         let c: __m128 = _mm_dpbf16_ps(src, a, b);
-        let result: [f32; 4] = transmute(c.as_f32x4());
+        let result = *c.as_f32x4().as_array();
         let expected_result: [f32; 4] = [-18.0_f32, -52.0_f32, -16.0_f32, -50.0_f32];
         assert_eq!(result, expected_result);
     }
 
     #[simd_test(enable = "avx512bf16,avx512vl")]
-    unsafe fn test_mm_mask_dpbf16_ps() {
+    fn test_mm_mask_dpbf16_ps() {
         let a_array = [8.5_f32, 10.5_f32, 3.75_f32, 50.25_f32];
         let b_array = [-1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32];
-        let a1: __m128 = transmute(a_array);
-        let b1: __m128 = transmute(b_array);
+        let a1 = f32x4::from_array(a_array).as_m128();
+        let b1 = f32x4::from_array(b_array).as_m128();
         let k: __mmask8 = 0xf3;
-        let src: __m128 = transmute([1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32]);
+        let src = f32x4::from_array([1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32]).as_m128();
         let a: __m128bh = _mm_cvtne2ps_pbh(a1, a1);
         let b: __m128bh = _mm_cvtne2ps_pbh(b1, b1);
         let c: __m128 = _mm_mask_dpbf16_ps(src, k, a, b);
-        let result: [f32; 4] = transmute(c.as_f32x4());
+        let result = *c.as_f32x4().as_array();
         let expected_result: [f32; 4] = [-18.0_f32, -52.0_f32, 3.0_f32, 4.0_f32];
         assert_eq!(result, expected_result);
         let k: __mmask8 = 0xff;
         let c: __m128 = _mm_mask_dpbf16_ps(src, k, a, b);
-        let result: [f32; 4] = transmute(c.as_f32x4());
+        let result = *c.as_f32x4().as_array();
         let expected_result: [f32; 4] = [-18.0_f32, -52.0_f32, -16.0_f32, -50.0_f32];
         assert_eq!(result, expected_result);
         let k: __mmask8 = 0;
         let c: __m128 = _mm_mask_dpbf16_ps(src, k, a, b);
-        let result: [f32; 4] = transmute(c.as_f32x4());
+        let result = *c.as_f32x4().as_array();
         let expected_result: [f32; 4] = [1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32];
         assert_eq!(result, expected_result);
     }
 
     #[simd_test(enable = "avx512bf16,avx512vl")]
-    unsafe fn test_mm_maskz_dpbf16_ps() {
+    fn test_mm_maskz_dpbf16_ps() {
         let a_array = [8.5_f32, 10.5_f32, 3.75_f32, 50.25_f32];
         let b_array = [-1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32];
-        let a1: __m128 = transmute(a_array);
-        let b1: __m128 = transmute(b_array);
+        let a1 = f32x4::from_array(a_array).as_m128();
+        let b1 = f32x4::from_array(b_array).as_m128();
         let k: __mmask8 = 0xf3;
-        let src: __m128 = transmute([1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32]);
+        let src = f32x4::from_array([1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32]).as_m128();
         let a: __m128bh = _mm_cvtne2ps_pbh(a1, a1);
         let b: __m128bh = _mm_cvtne2ps_pbh(b1, b1);
         let c: __m128 = _mm_maskz_dpbf16_ps(k, src, a, b);
-        let result: [f32; 4] = transmute(c.as_f32x4());
+        let result = *c.as_f32x4().as_array();
         let expected_result: [f32; 4] = [-18.0_f32, -52.0_f32, 0.0, 0.0];
         assert_eq!(result, expected_result);
         let k: __mmask8 = 0xff;
         let c: __m128 = _mm_maskz_dpbf16_ps(k, src, a, b);
-        let result: [f32; 4] = transmute(c.as_f32x4());
+        let result = *c.as_f32x4().as_array();
         let expected_result: [f32; 4] = [-18.0_f32, -52.0_f32, -16.0_f32, -50.0_f32];
         assert_eq!(result, expected_result);
         let k: __mmask8 = 0;
         let c: __m128 = _mm_maskz_dpbf16_ps(k, src, a, b);
-        let result: [f32; 4] = transmute(c.as_f32x4());
+        let result = *c.as_f32x4().as_array();
         let expected_result: [f32; 4] = [0.0, 0.0, 0.0, 0.0];
         assert_eq!(result, expected_result);
     }
 
     #[simd_test(enable = "avx512bf16,avx512vl")]
-    unsafe fn test_mm256_dpbf16_ps() {
+    fn test_mm256_dpbf16_ps() {
         #[rustfmt::skip]
         let a_array = [
             8.5_f32, 10.5_f32, 3.75_f32, 50.25_f32, 8.5_f32, 10.5_f32, 3.75_f32, 50.25_f32,
@@ -1597,16 +1597,16 @@ mod tests {
         let b_array = [
             -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32,
         ];
-        let a1: __m256 = transmute(a_array);
-        let b1: __m256 = transmute(b_array);
+        let a1 = f32x8::from_array(a_array).as_m256();
+        let b1 = f32x8::from_array(b_array).as_m256();
         #[rustfmt::skip]
-        let src: __m256 = transmute([
+        let src = f32x8::from_array([
             1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32, 1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32,
-        ]);
+        ]).as_m256();
         let a: __m256bh = _mm256_cvtne2ps_pbh(a1, a1);
         let b: __m256bh = _mm256_cvtne2ps_pbh(b1, b1);
         let c: __m256 = _mm256_dpbf16_ps(src, a, b);
-        let result: [f32; 8] = transmute(c.as_f32x8());
+        let result = *c.as_f32x8().as_array();
         #[rustfmt::skip]
         let expected_result: [f32; 8] = [
             -18.0_f32, -52.0_f32, -16.0_f32, -50.0_f32, -18.0_f32, -52.0_f32, -16.0_f32, -50.0_f32,
@@ -1615,7 +1615,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bf16,avx512vl")]
-    unsafe fn test_mm256_mask_dpbf16_ps() {
+    fn test_mm256_mask_dpbf16_ps() {
         #[rustfmt::skip]
         let a_array = [
             8.5_f32, 10.5_f32, 3.75_f32, 50.25_f32, 8.5_f32, 10.5_f32, 3.75_f32, 50.25_f32,
@@ -1623,17 +1623,17 @@ mod tests {
         let b_array = [
             -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32,
         ];
-        let a1: __m256 = transmute(a_array);
-        let b1: __m256 = transmute(b_array);
+        let a1 = f32x8::from_array(a_array).as_m256();
+        let b1 = f32x8::from_array(b_array).as_m256();
         let k: __mmask8 = 0x33;
         #[rustfmt::skip]
-        let src: __m256 = transmute([
+        let src = f32x8::from_array([
             1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32, 1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32,
-        ]);
+        ]).as_m256();
         let a: __m256bh = _mm256_cvtne2ps_pbh(a1, a1);
         let b: __m256bh = _mm256_cvtne2ps_pbh(b1, b1);
         let c: __m256 = _mm256_mask_dpbf16_ps(src, k, a, b);
-        let result: [f32; 8] = transmute(c.as_f32x8());
+        let result = *c.as_f32x8().as_array();
         #[rustfmt::skip]
         let expected_result: [f32; 8] = [
             -18.0_f32, -52.0_f32, 3.0_f32, 4.0_f32, -18.0_f32, -52.0_f32, 3.0_f32, 4.0_f32,
@@ -1641,7 +1641,7 @@ mod tests {
         assert_eq!(result, expected_result);
         let k: __mmask8 = 0xff;
         let c: __m256 = _mm256_mask_dpbf16_ps(src, k, a, b);
-        let result: [f32; 8] = transmute(c.as_f32x8());
+        let result = *c.as_f32x8().as_array();
         #[rustfmt::skip]
         let expected_result: [f32; 8] = [
             -18.0_f32, -52.0_f32, -16.0_f32, -50.0_f32, -18.0_f32, -52.0_f32, -16.0_f32, -50.0_f32,
@@ -1649,7 +1649,7 @@ mod tests {
         assert_eq!(result, expected_result);
         let k: __mmask8 = 0;
         let c: __m256 = _mm256_mask_dpbf16_ps(src, k, a, b);
-        let result: [f32; 8] = transmute(c.as_f32x8());
+        let result = *c.as_f32x8().as_array();
         #[rustfmt::skip]
         let expected_result: [f32; 8] = [
             1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32, 1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32,
@@ -1658,7 +1658,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bf16,avx512vl")]
-    unsafe fn test_mm256_maskz_dpbf16_ps() {
+    fn test_mm256_maskz_dpbf16_ps() {
         #[rustfmt::skip]
         let a_array = [
             8.5_f32, 10.5_f32, 3.75_f32, 50.25_f32, 8.5_f32, 10.5_f32, 3.75_f32, 50.25_f32,
@@ -1666,17 +1666,17 @@ mod tests {
         let b_array = [
             -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32,
         ];
-        let a1: __m256 = transmute(a_array);
-        let b1: __m256 = transmute(b_array);
+        let a1 = f32x8::from_array(a_array).as_m256();
+        let b1 = f32x8::from_array(b_array).as_m256();
         let k: __mmask8 = 0x33;
         #[rustfmt::skip]
-        let src: __m256 = transmute([
+        let src = f32x8::from_array([
             1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32, 1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32,
-        ]);
+        ]).as_m256();
         let a: __m256bh = _mm256_cvtne2ps_pbh(a1, a1);
         let b: __m256bh = _mm256_cvtne2ps_pbh(b1, b1);
         let c: __m256 = _mm256_maskz_dpbf16_ps(k, src, a, b);
-        let result: [f32; 8] = transmute(c.as_f32x8());
+        let result = *c.as_f32x8().as_array();
         #[rustfmt::skip]
         let expected_result: [f32; 8] = [
             -18.0_f32, -52.0_f32, 0.0, 0.0, -18.0_f32, -52.0_f32, 0.0, 0.0,
@@ -1684,7 +1684,7 @@ mod tests {
         assert_eq!(result, expected_result);
         let k: __mmask8 = 0xff;
         let c: __m256 = _mm256_maskz_dpbf16_ps(k, src, a, b);
-        let result: [f32; 8] = transmute(c.as_f32x8());
+        let result = *c.as_f32x8().as_array();
         #[rustfmt::skip]
         let expected_result: [f32; 8] = [
             -18.0_f32, -52.0_f32, -16.0_f32, -50.0_f32, -18.0_f32, -52.0_f32, -16.0_f32, -50.0_f32,
@@ -1692,13 +1692,13 @@ mod tests {
         assert_eq!(result, expected_result);
         let k: __mmask8 = 0;
         let c: __m256 = _mm256_maskz_dpbf16_ps(k, src, a, b);
-        let result: [f32; 8] = transmute(c.as_f32x8());
+        let result = *c.as_f32x8().as_array();
         let expected_result: [f32; 8] = [0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0];
         assert_eq!(result, expected_result);
     }
 
     #[simd_test(enable = "avx512bf16,avx512f")]
-    unsafe fn test_mm512_dpbf16_ps() {
+    fn test_mm512_dpbf16_ps() {
         #[rustfmt::skip]
         let a_array = [
             8.5_f32, 10.5_f32, 3.75_f32, 50.25_f32, 8.5_f32, 10.5_f32, 3.75_f32, 50.25_f32,
@@ -1708,16 +1708,17 @@ mod tests {
             -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32,
             -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32,
         ];
-        let a1: __m512 = transmute(a_array);
-        let b1: __m512 = transmute(b_array);
-        let src: __m512 = transmute([
+        let a1 = f32x16::from_array(a_array).as_m512();
+        let b1 = f32x16::from_array(b_array).as_m512();
+        let src = f32x16::from_array([
             1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32, 1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32, 1.0_f32,
             2.0_f32, 3.0_f32, 4.0_f32, 1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32,
-        ]);
+        ])
+        .as_m512();
         let a: __m512bh = _mm512_cvtne2ps_pbh(a1, a1);
         let b: __m512bh = _mm512_cvtne2ps_pbh(b1, b1);
         let c: __m512 = _mm512_dpbf16_ps(src, a, b);
-        let result: [f32; 16] = transmute(c.as_f32x16());
+        let result = *c.as_f32x16().as_array();
         #[rustfmt::skip]
         let expected_result: [f32; 16] = [
             -18.0_f32, -52.0_f32, -16.0_f32, -50.0_f32, -18.0_f32, -52.0_f32, -16.0_f32, -50.0_f32,
@@ -1727,7 +1728,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bf16,avx512f")]
-    unsafe fn test_mm512_mask_dpbf16_ps() {
+    fn test_mm512_mask_dpbf16_ps() {
         #[rustfmt::skip]
         let a_array = [
             8.5_f32, 10.5_f32, 3.75_f32, 50.25_f32, 8.5_f32, 10.5_f32, 3.75_f32, 50.25_f32,
@@ -1737,18 +1738,18 @@ mod tests {
             -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32,
             -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32,
         ];
-        let a1: __m512 = transmute(a_array);
-        let b1: __m512 = transmute(b_array);
+        let a1 = f32x16::from_array(a_array).as_m512();
+        let b1 = f32x16::from_array(b_array).as_m512();
         let k: __mmask16 = 0x3333;
         #[rustfmt::skip]
-        let src: __m512 = transmute([
+        let src = f32x16::from_array([
             1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32, 1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32, 1.0_f32,
             2.0_f32, 3.0_f32, 4.0_f32, 1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32,
-        ]);
+        ]).as_m512();
         let a: __m512bh = _mm512_cvtne2ps_pbh(a1, a1);
         let b: __m512bh = _mm512_cvtne2ps_pbh(b1, b1);
         let c: __m512 = _mm512_mask_dpbf16_ps(src, k, a, b);
-        let result: [f32; 16] = transmute(c.as_f32x16());
+        let result = *c.as_f32x16().as_array();
         #[rustfmt::skip]
         let expected_result: [f32; 16] = [
             -18.0_f32, -52.0_f32, 3.0_f32, 4.0_f32, -18.0_f32, -52.0_f32, 3.0_f32, 4.0_f32,
@@ -1757,7 +1758,7 @@ mod tests {
         assert_eq!(result, expected_result);
         let k: __mmask16 = 0xffff;
         let c: __m512 = _mm512_mask_dpbf16_ps(src, k, a, b);
-        let result: [f32; 16] = transmute(c.as_f32x16());
+        let result = *c.as_f32x16().as_array();
         #[rustfmt::skip]
         let expected_result: [f32; 16] = [
             -18.0_f32, -52.0_f32, -16.0_f32, -50.0_f32, -18.0_f32, -52.0_f32, -16.0_f32, -50.0_f32,
@@ -1766,7 +1767,7 @@ mod tests {
         assert_eq!(result, expected_result);
         let k: __mmask16 = 0;
         let c: __m512 = _mm512_mask_dpbf16_ps(src, k, a, b);
-        let result: [f32; 16] = transmute(c.as_f32x16());
+        let result = *c.as_f32x16().as_array();
         #[rustfmt::skip]
         let expected_result: [f32; 16] = [
             1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32, 1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32, 1.0_f32,
@@ -1776,7 +1777,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bf16,avx512f")]
-    unsafe fn test_mm512_maskz_dpbf16_ps() {
+    fn test_mm512_maskz_dpbf16_ps() {
         #[rustfmt::skip]
         let a_array = [
             8.5_f32, 10.5_f32, 3.75_f32, 50.25_f32, 8.5_f32, 10.5_f32, 3.75_f32, 50.25_f32,
@@ -1786,18 +1787,18 @@ mod tests {
             -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32,
             -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32, -1.0_f32,
         ];
-        let a1: __m512 = transmute(a_array);
-        let b1: __m512 = transmute(b_array);
+        let a1 = f32x16::from_array(a_array).as_m512();
+        let b1 = f32x16::from_array(b_array).as_m512();
         let k: __mmask16 = 0x3333;
         #[rustfmt::skip]
-        let src: __m512 = transmute([
+        let src = f32x16::from_array([
             1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32, 1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32, 1.0_f32,
             2.0_f32, 3.0_f32, 4.0_f32, 1.0_f32, 2.0_f32, 3.0_f32, 4.0_f32,
-        ]);
+        ]).as_m512();
         let a: __m512bh = _mm512_cvtne2ps_pbh(a1, a1);
         let b: __m512bh = _mm512_cvtne2ps_pbh(b1, b1);
         let c: __m512 = _mm512_maskz_dpbf16_ps(k, src, a, b);
-        let result: [f32; 16] = transmute(c.as_f32x16());
+        let result = *c.as_f32x16().as_array();
         #[rustfmt::skip]
         let expected_result: [f32; 16] = [
             -18.0_f32, -52.0_f32, 0.0, 0.0, -18.0_f32, -52.0_f32, 0.0, 0.0, -18.0_f32, -52.0_f32,
@@ -1806,7 +1807,7 @@ mod tests {
         assert_eq!(result, expected_result);
         let k: __mmask16 = 0xffff;
         let c: __m512 = _mm512_maskz_dpbf16_ps(k, src, a, b);
-        let result: [f32; 16] = transmute(c.as_f32x16());
+        let result = *c.as_f32x16().as_array();
         #[rustfmt::skip]
         let expected_result: [f32; 16] = [
             -18.0_f32, -52.0_f32, -16.0_f32, -50.0_f32, -18.0_f32, -52.0_f32, -16.0_f32, -50.0_f32,
@@ -1815,7 +1816,7 @@ mod tests {
         assert_eq!(result, expected_result);
         let k: __mmask16 = 0;
         let c: __m512 = _mm512_maskz_dpbf16_ps(k, src, a, b);
-        let result: [f32; 16] = transmute(c.as_f32x16());
+        let result = *c.as_f32x16().as_array();
         #[rustfmt::skip]
         let expected_result: [f32; 16] = [
             0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0,
@@ -1943,28 +1944,28 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bf16,avx512vl")]
-    unsafe fn test_mm_cvtneps_pbh() {
+    fn test_mm_cvtneps_pbh() {
         let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
-        let r: u16x4 = transmute_copy(&_mm_cvtneps_pbh(a));
+        let r: u16x4 = unsafe { transmute_copy(&_mm_cvtneps_pbh(a)) };
         let e = u16x4::new(BF16_ONE, BF16_TWO, BF16_THREE, BF16_FOUR);
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "avx512bf16,avx512vl")]
-    unsafe fn test_mm_mask_cvtneps_pbh() {
+    fn test_mm_mask_cvtneps_pbh() {
         let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
         let src = __m128bh([5, 6, 7, 8, !0, !0, !0, !0]);
         let k = 0b1010;
-        let r: u16x4 = transmute_copy(&_mm_mask_cvtneps_pbh(src, k, a));
+        let r: u16x4 = unsafe { transmute_copy(&_mm_mask_cvtneps_pbh(src, k, a)) };
         let e = u16x4::new(5, BF16_TWO, 7, BF16_FOUR);
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "avx512bf16,avx512vl")]
-    unsafe fn test_mm_maskz_cvtneps_pbh() {
+    fn test_mm_maskz_cvtneps_pbh() {
         let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
         let k = 0b1010;
-        let r: u16x4 = transmute_copy(&_mm_maskz_cvtneps_pbh(k, a));
+        let r: u16x4 = unsafe { transmute_copy(&_mm_maskz_cvtneps_pbh(k, a)) };
         let e = u16x4::new(0, BF16_TWO, 0, BF16_FOUR);
         assert_eq!(r, e);
     }
diff --git a/library/stdarch/crates/core_arch/src/x86/avx512bw.rs b/library/stdarch/crates/core_arch/src/x86/avx512bw.rs
index 6b4b88621efd..8e074fdcfa48 100644
--- a/library/stdarch/crates/core_arch/src/x86/avx512bw.rs
+++ b/library/stdarch/crates/core_arch/src/x86/avx512bw.rs
@@ -17098,37 +17098,37 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_loadu_epi16() {
+    const fn test_mm512_loadu_epi16() {
         #[rustfmt::skip]
         let a: [i16; 32] = [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32];
-        let r = _mm512_loadu_epi16(&a[0]);
+        let r = unsafe { _mm512_loadu_epi16(&a[0]) };
         #[rustfmt::skip]
         let e = _mm512_set_epi16(32, 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1);
         assert_eq_m512i(r, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_loadu_epi16() {
+    const fn test_mm256_loadu_epi16() {
         let a: [i16; 16] = [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16];
-        let r = _mm256_loadu_epi16(&a[0]);
+        let r = unsafe { _mm256_loadu_epi16(&a[0]) };
         let e = _mm256_set_epi16(16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1);
         assert_eq_m256i(r, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_loadu_epi16() {
+    const fn test_mm_loadu_epi16() {
         let a: [i16; 8] = [1, 2, 3, 4, 5, 6, 7, 8];
-        let r = _mm_loadu_epi16(&a[0]);
+        let r = unsafe { _mm_loadu_epi16(&a[0]) };
         let e = _mm_set_epi16(8, 7, 6, 5, 4, 3, 2, 1);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_loadu_epi8() {
+    const fn test_mm512_loadu_epi8() {
         #[rustfmt::skip]
         let a: [i8; 64] = [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32,
                            1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32];
-        let r = _mm512_loadu_epi8(&a[0]);
+        let r = unsafe { _mm512_loadu_epi8(&a[0]) };
         #[rustfmt::skip]
         let e = _mm512_set_epi8(32, 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1,
                                 32, 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1);
@@ -17136,73 +17136,85 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_loadu_epi8() {
+    const fn test_mm256_loadu_epi8() {
         #[rustfmt::skip]
         let a: [i8; 32] = [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32];
-        let r = _mm256_loadu_epi8(&a[0]);
+        let r = unsafe { _mm256_loadu_epi8(&a[0]) };
         #[rustfmt::skip]
         let e = _mm256_set_epi8(32, 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1);
         assert_eq_m256i(r, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_loadu_epi8() {
+    const fn test_mm_loadu_epi8() {
         let a: [i8; 16] = [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16];
-        let r = _mm_loadu_epi8(&a[0]);
+        let r = unsafe { _mm_loadu_epi8(&a[0]) };
         let e = _mm_set_epi8(16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_storeu_epi16() {
+    const fn test_mm512_storeu_epi16() {
         let a = _mm512_set1_epi16(9);
         let mut r = _mm512_undefined_epi32();
-        _mm512_storeu_epi16(&mut r as *mut _ as *mut i16, a);
+        unsafe {
+            _mm512_storeu_epi16(&mut r as *mut _ as *mut i16, a);
+        }
         assert_eq_m512i(r, a);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_storeu_epi16() {
+    const fn test_mm256_storeu_epi16() {
         let a = _mm256_set1_epi16(9);
         let mut r = _mm256_set1_epi32(0);
-        _mm256_storeu_epi16(&mut r as *mut _ as *mut i16, a);
+        unsafe {
+            _mm256_storeu_epi16(&mut r as *mut _ as *mut i16, a);
+        }
         assert_eq_m256i(r, a);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_storeu_epi16() {
+    const fn test_mm_storeu_epi16() {
         let a = _mm_set1_epi16(9);
         let mut r = _mm_set1_epi32(0);
-        _mm_storeu_epi16(&mut r as *mut _ as *mut i16, a);
+        unsafe {
+            _mm_storeu_epi16(&mut r as *mut _ as *mut i16, a);
+        }
         assert_eq_m128i(r, a);
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_storeu_epi8() {
+    const fn test_mm512_storeu_epi8() {
         let a = _mm512_set1_epi8(9);
         let mut r = _mm512_undefined_epi32();
-        _mm512_storeu_epi8(&mut r as *mut _ as *mut i8, a);
+        unsafe {
+            _mm512_storeu_epi8(&mut r as *mut _ as *mut i8, a);
+        }
         assert_eq_m512i(r, a);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_storeu_epi8() {
+    const fn test_mm256_storeu_epi8() {
         let a = _mm256_set1_epi8(9);
         let mut r = _mm256_set1_epi32(0);
-        _mm256_storeu_epi8(&mut r as *mut _ as *mut i8, a);
+        unsafe {
+            _mm256_storeu_epi8(&mut r as *mut _ as *mut i8, a);
+        }
         assert_eq_m256i(r, a);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_storeu_epi8() {
+    const fn test_mm_storeu_epi8() {
         let a = _mm_set1_epi8(9);
         let mut r = _mm_set1_epi32(0);
-        _mm_storeu_epi8(&mut r as *mut _ as *mut i8, a);
+        unsafe {
+            _mm_storeu_epi8(&mut r as *mut _ as *mut i8, a);
+        }
         assert_eq_m128i(r, a);
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_mask_loadu_epi16() {
+    const fn test_mm512_mask_loadu_epi16() {
         let src = _mm512_set1_epi16(42);
         let a = &[
             1_i16, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23,
@@ -17210,52 +17222,54 @@ mod tests {
         ];
         let p = a.as_ptr();
         let m = 0b10101010_11001100_11101000_11001010;
-        let r = _mm512_mask_loadu_epi16(src, m, black_box(p));
+        let r = unsafe { _mm512_mask_loadu_epi16(src, m, black_box(p)) };
         let e = &[
             42_i16, 2, 42, 4, 42, 42, 7, 8, 42, 42, 42, 12, 42, 14, 15, 16, 42, 42, 19, 20, 42, 42,
             23, 24, 42, 26, 42, 28, 42, 30, 42, 32,
         ];
-        let e = _mm512_loadu_epi16(e.as_ptr());
+        let e = unsafe { _mm512_loadu_epi16(e.as_ptr()) };
         assert_eq_m512i(r, e);
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_maskz_loadu_epi16() {
+    const fn test_mm512_maskz_loadu_epi16() {
         let a = &[
             1_i16, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23,
             24, 25, 26, 27, 28, 29, 30, 31, 32,
         ];
         let p = a.as_ptr();
         let m = 0b10101010_11001100_11101000_11001010;
-        let r = _mm512_maskz_loadu_epi16(m, black_box(p));
+        let r = unsafe { _mm512_maskz_loadu_epi16(m, black_box(p)) };
         let e = &[
             0_i16, 2, 0, 4, 0, 0, 7, 8, 0, 0, 0, 12, 0, 14, 15, 16, 0, 0, 19, 20, 0, 0, 23, 24, 0,
             26, 0, 28, 0, 30, 0, 32,
         ];
-        let e = _mm512_loadu_epi16(e.as_ptr());
+        let e = unsafe { _mm512_loadu_epi16(e.as_ptr()) };
         assert_eq_m512i(r, e);
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_mask_storeu_epi16() {
+    const fn test_mm512_mask_storeu_epi16() {
         let mut r = [42_i16; 32];
         let a = &[
             1_i16, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23,
             24, 25, 26, 27, 28, 29, 30, 31, 32,
         ];
-        let a = _mm512_loadu_epi16(a.as_ptr());
+        let a = unsafe { _mm512_loadu_epi16(a.as_ptr()) };
         let m = 0b10101010_11001100_11101000_11001010;
-        _mm512_mask_storeu_epi16(r.as_mut_ptr(), m, a);
+        unsafe {
+            _mm512_mask_storeu_epi16(r.as_mut_ptr(), m, a);
+        }
         let e = &[
             42_i16, 2, 42, 4, 42, 42, 7, 8, 42, 42, 42, 12, 42, 14, 15, 16, 42, 42, 19, 20, 42, 42,
             23, 24, 42, 26, 42, 28, 42, 30, 42, 32,
         ];
-        let e = _mm512_loadu_epi16(e.as_ptr());
-        assert_eq_m512i(_mm512_loadu_epi16(r.as_ptr()), e);
+        let e = unsafe { _mm512_loadu_epi16(e.as_ptr()) };
+        assert_eq_m512i(unsafe { _mm512_loadu_epi16(r.as_ptr()) }, e);
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_mask_loadu_epi8() {
+    const fn test_mm512_mask_loadu_epi8() {
         let src = _mm512_set1_epi8(42);
         let a = &[
             1_i8, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23,
@@ -17264,18 +17278,18 @@ mod tests {
         ];
         let p = a.as_ptr();
         let m = 0b00000000_11111111_11111111_00000000_10101010_11001100_11101000_11001010;
-        let r = _mm512_mask_loadu_epi8(src, m, black_box(p));
+        let r = unsafe { _mm512_mask_loadu_epi8(src, m, black_box(p)) };
         let e = &[
             42_i8, 2, 42, 4, 42, 42, 7, 8, 42, 42, 42, 12, 42, 14, 15, 16, 42, 42, 19, 20, 42, 42,
             23, 24, 42, 26, 42, 28, 42, 30, 42, 32, 42, 42, 42, 42, 42, 42, 42, 42, 41, 42, 43, 44,
             45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 42, 42, 42, 42, 42, 42, 42, 42,
         ];
-        let e = _mm512_loadu_epi8(e.as_ptr());
+        let e = unsafe { _mm512_loadu_epi8(e.as_ptr()) };
         assert_eq_m512i(r, e);
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_maskz_loadu_epi8() {
+    const fn test_mm512_maskz_loadu_epi8() {
         let a = &[
             1_i8, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23,
             24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45,
@@ -17283,77 +17297,81 @@ mod tests {
         ];
         let p = a.as_ptr();
         let m = 0b00000000_11111111_11111111_00000000_10101010_11001100_11101000_11001010;
-        let r = _mm512_maskz_loadu_epi8(m, black_box(p));
+        let r = unsafe { _mm512_maskz_loadu_epi8(m, black_box(p)) };
         let e = &[
             0_i8, 2, 0, 4, 0, 0, 7, 8, 0, 0, 0, 12, 0, 14, 15, 16, 0, 0, 19, 20, 0, 0, 23, 24, 0,
             26, 0, 28, 0, 30, 0, 32, 0, 0, 0, 0, 0, 0, 0, 0, 41, 42, 43, 44, 45, 46, 47, 48, 49,
             50, 51, 52, 53, 54, 55, 56, 0, 0, 0, 0, 0, 0, 0, 0,
         ];
-        let e = _mm512_loadu_epi8(e.as_ptr());
+        let e = unsafe { _mm512_loadu_epi8(e.as_ptr()) };
         assert_eq_m512i(r, e);
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_mm512_mask_storeu_epi8() {
+    const fn test_mm512_mask_storeu_epi8() {
         let mut r = [42_i8; 64];
         let a = &[
             1_i8, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23,
             24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45,
             46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64,
         ];
-        let a = _mm512_loadu_epi8(a.as_ptr());
+        let a = unsafe { _mm512_loadu_epi8(a.as_ptr()) };
         let m = 0b00000000_11111111_11111111_00000000_10101010_11001100_11101000_11001010;
-        _mm512_mask_storeu_epi8(r.as_mut_ptr(), m, a);
+        unsafe {
+            _mm512_mask_storeu_epi8(r.as_mut_ptr(), m, a);
+        }
         let e = &[
             42_i8, 2, 42, 4, 42, 42, 7, 8, 42, 42, 42, 12, 42, 14, 15, 16, 42, 42, 19, 20, 42, 42,
             23, 24, 42, 26, 42, 28, 42, 30, 42, 32, 42, 42, 42, 42, 42, 42, 42, 42, 41, 42, 43, 44,
             45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 42, 42, 42, 42, 42, 42, 42, 42,
         ];
-        let e = _mm512_loadu_epi8(e.as_ptr());
-        assert_eq_m512i(_mm512_loadu_epi8(r.as_ptr()), e);
+        let e = unsafe { _mm512_loadu_epi8(e.as_ptr()) };
+        assert_eq_m512i(unsafe { _mm512_loadu_epi8(r.as_ptr()) }, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_mask_loadu_epi16() {
+    const fn test_mm256_mask_loadu_epi16() {
         let src = _mm256_set1_epi16(42);
         let a = &[1_i16, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16];
         let p = a.as_ptr();
         let m = 0b11101000_11001010;
-        let r = _mm256_mask_loadu_epi16(src, m, black_box(p));
+        let r = unsafe { _mm256_mask_loadu_epi16(src, m, black_box(p)) };
         let e = &[
             42_i16, 2, 42, 4, 42, 42, 7, 8, 42, 42, 42, 12, 42, 14, 15, 16,
         ];
-        let e = _mm256_loadu_epi16(e.as_ptr());
+        let e = unsafe { _mm256_loadu_epi16(e.as_ptr()) };
         assert_eq_m256i(r, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_maskz_loadu_epi16() {
+    const fn test_mm256_maskz_loadu_epi16() {
         let a = &[1_i16, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16];
         let p = a.as_ptr();
         let m = 0b11101000_11001010;
-        let r = _mm256_maskz_loadu_epi16(m, black_box(p));
+        let r = unsafe { _mm256_maskz_loadu_epi16(m, black_box(p)) };
         let e = &[0_i16, 2, 0, 4, 0, 0, 7, 8, 0, 0, 0, 12, 0, 14, 15, 16];
-        let e = _mm256_loadu_epi16(e.as_ptr());
+        let e = unsafe { _mm256_loadu_epi16(e.as_ptr()) };
         assert_eq_m256i(r, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_mask_storeu_epi16() {
+    const fn test_mm256_mask_storeu_epi16() {
         let mut r = [42_i16; 16];
         let a = &[1_i16, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16];
-        let a = _mm256_loadu_epi16(a.as_ptr());
+        let a = unsafe { _mm256_loadu_epi16(a.as_ptr()) };
         let m = 0b11101000_11001010;
-        _mm256_mask_storeu_epi16(r.as_mut_ptr(), m, a);
+        unsafe {
+            _mm256_mask_storeu_epi16(r.as_mut_ptr(), m, a);
+        }
         let e = &[
             42_i16, 2, 42, 4, 42, 42, 7, 8, 42, 42, 42, 12, 42, 14, 15, 16,
         ];
-        let e = _mm256_loadu_epi16(e.as_ptr());
-        assert_eq_m256i(_mm256_loadu_epi16(r.as_ptr()), e);
+        let e = unsafe { _mm256_loadu_epi16(e.as_ptr()) };
+        assert_eq_m256i(unsafe { _mm256_loadu_epi16(r.as_ptr()) }, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_mask_loadu_epi8() {
+    const fn test_mm256_mask_loadu_epi8() {
         let src = _mm256_set1_epi8(42);
         let a = &[
             1_i8, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23,
@@ -17361,122 +17379,124 @@ mod tests {
         ];
         let p = a.as_ptr();
         let m = 0b10101010_11001100_11101000_11001010;
-        let r = _mm256_mask_loadu_epi8(src, m, black_box(p));
+        let r = unsafe { _mm256_mask_loadu_epi8(src, m, black_box(p)) };
         let e = &[
             42_i8, 2, 42, 4, 42, 42, 7, 8, 42, 42, 42, 12, 42, 14, 15, 16, 42, 42, 19, 20, 42, 42,
             23, 24, 42, 26, 42, 28, 42, 30, 42, 32,
         ];
-        let e = _mm256_loadu_epi8(e.as_ptr());
+        let e = unsafe { _mm256_loadu_epi8(e.as_ptr()) };
         assert_eq_m256i(r, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_maskz_loadu_epi8() {
+    const fn test_mm256_maskz_loadu_epi8() {
         let a = &[
             1_i8, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23,
             24, 25, 26, 27, 28, 29, 30, 31, 32,
         ];
         let p = a.as_ptr();
         let m = 0b10101010_11001100_11101000_11001010;
-        let r = _mm256_maskz_loadu_epi8(m, black_box(p));
+        let r = unsafe { _mm256_maskz_loadu_epi8(m, black_box(p)) };
         let e = &[
             0_i8, 2, 0, 4, 0, 0, 7, 8, 0, 0, 0, 12, 0, 14, 15, 16, 0, 0, 19, 20, 0, 0, 23, 24, 0,
             26, 0, 28, 0, 30, 0, 32,
         ];
-        let e = _mm256_loadu_epi8(e.as_ptr());
+        let e = unsafe { _mm256_loadu_epi8(e.as_ptr()) };
         assert_eq_m256i(r, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm256_mask_storeu_epi8() {
+    const fn test_mm256_mask_storeu_epi8() {
         let mut r = [42_i8; 32];
         let a = &[
             1_i8, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23,
             24, 25, 26, 27, 28, 29, 30, 31, 32,
         ];
-        let a = _mm256_loadu_epi8(a.as_ptr());
+        let a = unsafe { _mm256_loadu_epi8(a.as_ptr()) };
         let m = 0b10101010_11001100_11101000_11001010;
-        _mm256_mask_storeu_epi8(r.as_mut_ptr(), m, a);
+        unsafe {
+            _mm256_mask_storeu_epi8(r.as_mut_ptr(), m, a);
+        }
         let e = &[
             42_i8, 2, 42, 4, 42, 42, 7, 8, 42, 42, 42, 12, 42, 14, 15, 16, 42, 42, 19, 20, 42, 42,
             23, 24, 42, 26, 42, 28, 42, 30, 42, 32,
         ];
-        let e = _mm256_loadu_epi8(e.as_ptr());
-        assert_eq_m256i(_mm256_loadu_epi8(r.as_ptr()), e);
+        let e = unsafe { _mm256_loadu_epi8(e.as_ptr()) };
+        assert_eq_m256i(unsafe { _mm256_loadu_epi8(r.as_ptr()) }, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_mask_loadu_epi16() {
+    const fn test_mm_mask_loadu_epi16() {
         let src = _mm_set1_epi16(42);
         let a = &[1_i16, 2, 3, 4, 5, 6, 7, 8];
         let p = a.as_ptr();
         let m = 0b11001010;
-        let r = _mm_mask_loadu_epi16(src, m, black_box(p));
+        let r = unsafe { _mm_mask_loadu_epi16(src, m, black_box(p)) };
         let e = &[42_i16, 2, 42, 4, 42, 42, 7, 8];
-        let e = _mm_loadu_epi16(e.as_ptr());
+        let e = unsafe { _mm_loadu_epi16(e.as_ptr()) };
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_maskz_loadu_epi16() {
+    const fn test_mm_maskz_loadu_epi16() {
         let a = &[1_i16, 2, 3, 4, 5, 6, 7, 8];
         let p = a.as_ptr();
         let m = 0b11001010;
-        let r = _mm_maskz_loadu_epi16(m, black_box(p));
+        let r = unsafe { _mm_maskz_loadu_epi16(m, black_box(p)) };
         let e = &[0_i16, 2, 0, 4, 0, 0, 7, 8];
-        let e = _mm_loadu_epi16(e.as_ptr());
+        let e = unsafe { _mm_loadu_epi16(e.as_ptr()) };
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_mask_storeu_epi16() {
+    const fn test_mm_mask_storeu_epi16() {
         let mut r = [42_i16; 8];
         let a = &[1_i16, 2, 3, 4, 5, 6, 7, 8];
-        let a = _mm_loadu_epi16(a.as_ptr());
+        let a = unsafe { _mm_loadu_epi16(a.as_ptr()) };
         let m = 0b11001010;
-        _mm_mask_storeu_epi16(r.as_mut_ptr(), m, a);
+        unsafe { _mm_mask_storeu_epi16(r.as_mut_ptr(), m, a) };
         let e = &[42_i16, 2, 42, 4, 42, 42, 7, 8];
-        let e = _mm_loadu_epi16(e.as_ptr());
-        assert_eq_m128i(_mm_loadu_epi16(r.as_ptr()), e);
+        let e = unsafe { _mm_loadu_epi16(e.as_ptr()) };
+        assert_eq_m128i(unsafe { _mm_loadu_epi16(r.as_ptr()) }, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_mask_loadu_epi8() {
+    const fn test_mm_mask_loadu_epi8() {
         let src = _mm_set1_epi8(42);
         let a = &[1_i8, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16];
         let p = a.as_ptr();
         let m = 0b11101000_11001010;
-        let r = _mm_mask_loadu_epi8(src, m, black_box(p));
+        let r = unsafe { _mm_mask_loadu_epi8(src, m, black_box(p)) };
         let e = &[
             42_i8, 2, 42, 4, 42, 42, 7, 8, 42, 42, 42, 12, 42, 14, 15, 16,
         ];
-        let e = _mm_loadu_epi8(e.as_ptr());
+        let e = unsafe { _mm_loadu_epi8(e.as_ptr()) };
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_maskz_loadu_epi8() {
+    const fn test_mm_maskz_loadu_epi8() {
         let a = &[1_i8, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16];
         let p = a.as_ptr();
         let m = 0b11101000_11001010;
-        let r = _mm_maskz_loadu_epi8(m, black_box(p));
+        let r = unsafe { _mm_maskz_loadu_epi8(m, black_box(p)) };
         let e = &[0_i8, 2, 0, 4, 0, 0, 7, 8, 0, 0, 0, 12, 0, 14, 15, 16];
-        let e = _mm_loadu_epi8(e.as_ptr());
+        let e = unsafe { _mm_loadu_epi8(e.as_ptr()) };
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    const unsafe fn test_mm_mask_storeu_epi8() {
+    const fn test_mm_mask_storeu_epi8() {
         let mut r = [42_i8; 16];
         let a = &[1_i8, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16];
-        let a = _mm_loadu_epi8(a.as_ptr());
+        let a = unsafe { _mm_loadu_epi8(a.as_ptr()) };
         let m = 0b11101000_11001010;
-        _mm_mask_storeu_epi8(r.as_mut_ptr(), m, a);
+        unsafe { _mm_mask_storeu_epi8(r.as_mut_ptr(), m, a) };
         let e = &[
             42_i8, 2, 42, 4, 42, 42, 7, 8, 42, 42, 42, 12, 42, 14, 15, 16,
         ];
-        let e = _mm_loadu_epi8(e.as_ptr());
-        assert_eq_m128i(_mm_loadu_epi8(r.as_ptr()), e);
+        let e = unsafe { _mm_loadu_epi8(e.as_ptr()) };
+        assert_eq_m128i(unsafe { _mm_loadu_epi8(r.as_ptr()) }, e);
     }
 
     #[simd_test(enable = "avx512bw")]
@@ -20714,36 +20734,40 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_store_mask64() {
+    const fn test_store_mask64() {
         let a: __mmask64 =
             0b11111111_00000000_11111111_00000000_11111111_00000000_11111111_00000000;
         let mut r = 0;
-        _store_mask64(&mut r, a);
+        unsafe {
+            _store_mask64(&mut r, a);
+        }
         assert_eq!(r, a);
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_store_mask32() {
+    const fn test_store_mask32() {
         let a: __mmask32 = 0b11111111_00000000_11111111_00000000;
         let mut r = 0;
-        _store_mask32(&mut r, a);
+        unsafe {
+            _store_mask32(&mut r, a);
+        }
         assert_eq!(r, a);
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_load_mask64() {
+    const fn test_load_mask64() {
         let p: __mmask64 =
             0b11111111_00000000_11111111_00000000_11111111_00000000_11111111_00000000;
-        let r = _load_mask64(&p);
+        let r = unsafe { _load_mask64(&p) };
         let e: __mmask64 =
             0b11111111_00000000_11111111_00000000_11111111_00000000_11111111_00000000;
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_load_mask32() {
+    const fn test_load_mask32() {
         let p: __mmask32 = 0b11111111_00000000_11111111_00000000;
-        let r = _load_mask32(&p);
+        let r = unsafe { _load_mask32(&p) };
         let e: __mmask32 = 0b11111111_00000000_11111111_00000000;
         assert_eq!(r, e);
     }
@@ -21163,21 +21187,21 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_kortest_mask32_u8() {
+    const fn test_kortest_mask32_u8() {
         let a: __mmask32 = 0b0110100101101001_0110100101101001;
         let b: __mmask32 = 0b1011011010110110_1011011010110110;
         let mut all_ones: u8 = 0;
-        let r = _kortest_mask32_u8(a, b, &mut all_ones);
+        let r = unsafe { _kortest_mask32_u8(a, b, &mut all_ones) };
         assert_eq!(r, 0);
         assert_eq!(all_ones, 1);
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_kortest_mask64_u8() {
+    const fn test_kortest_mask64_u8() {
         let a: __mmask64 = 0b0110100101101001_0110100101101001;
         let b: __mmask64 = 0b1011011010110110_1011011010110110;
         let mut all_ones: u8 = 0;
-        let r = _kortest_mask64_u8(a, b, &mut all_ones);
+        let r = unsafe { _kortest_mask64_u8(a, b, &mut all_ones) };
         assert_eq!(r, 0);
         assert_eq!(all_ones, 0);
     }
@@ -21299,11 +21323,11 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_ktest_mask32_u8() {
+    const fn test_ktest_mask32_u8() {
         let a: __mmask32 = 0b0110100100111100_0110100100111100;
         let b: __mmask32 = 0b1001011011000011_1001011011000011;
         let mut and_not: u8 = 0;
-        let r = _ktest_mask32_u8(a, b, &mut and_not);
+        let r = unsafe { _ktest_mask32_u8(a, b, &mut and_not) };
         assert_eq!(r, 1);
         assert_eq!(and_not, 0);
     }
@@ -21325,11 +21349,11 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    const unsafe fn test_ktest_mask64_u8() {
+    const fn test_ktest_mask64_u8() {
         let a: __mmask64 = 0b0110100100111100_0110100100111100;
         let b: __mmask64 = 0b1001011011000011_1001011011000011;
         let mut and_not: u8 = 0;
-        let r = _ktest_mask64_u8(a, b, &mut and_not);
+        let r = unsafe { _ktest_mask64_u8(a, b, &mut and_not) };
         assert_eq!(r, 1);
         assert_eq!(and_not, 0);
     }
@@ -21951,32 +21975,38 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mask_cvtsepi16_storeu_epi8() {
+    fn test_mm512_mask_cvtsepi16_storeu_epi8() {
         let a = _mm512_set1_epi16(i16::MAX);
         let mut r = _mm256_undefined_si256();
-        _mm512_mask_cvtsepi16_storeu_epi8(
-            &mut r as *mut _ as *mut i8,
-            0b11111111_11111111_11111111_11111111,
-            a,
-        );
+        unsafe {
+            _mm512_mask_cvtsepi16_storeu_epi8(
+                &mut r as *mut _ as *mut i8,
+                0b11111111_11111111_11111111_11111111,
+                a,
+            );
+        }
         let e = _mm256_set1_epi8(i8::MAX);
         assert_eq_m256i(r, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_cvtsepi16_storeu_epi8() {
+    fn test_mm256_mask_cvtsepi16_storeu_epi8() {
         let a = _mm256_set1_epi16(i16::MAX);
         let mut r = _mm_undefined_si128();
-        _mm256_mask_cvtsepi16_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111_11111111, a);
+        unsafe {
+            _mm256_mask_cvtsepi16_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111_11111111, a);
+        }
         let e = _mm_set1_epi8(i8::MAX);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_cvtsepi16_storeu_epi8() {
+    fn test_mm_mask_cvtsepi16_storeu_epi8() {
         let a = _mm_set1_epi16(i16::MAX);
         let mut r = _mm_set1_epi8(0);
-        _mm_mask_cvtsepi16_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
+        unsafe {
+            _mm_mask_cvtsepi16_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
+        }
         #[rustfmt::skip]
         let e = _mm_set_epi8(
             0, 0, 0, 0, 0, 0, 0, 0,
@@ -21986,63 +22016,75 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mask_cvtepi16_storeu_epi8() {
+    fn test_mm512_mask_cvtepi16_storeu_epi8() {
         let a = _mm512_set1_epi16(8);
         let mut r = _mm256_undefined_si256();
-        _mm512_mask_cvtepi16_storeu_epi8(
-            &mut r as *mut _ as *mut i8,
-            0b11111111_11111111_11111111_11111111,
-            a,
-        );
+        unsafe {
+            _mm512_mask_cvtepi16_storeu_epi8(
+                &mut r as *mut _ as *mut i8,
+                0b11111111_11111111_11111111_11111111,
+                a,
+            );
+        }
         let e = _mm256_set1_epi8(8);
         assert_eq_m256i(r, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_cvtepi16_storeu_epi8() {
+    fn test_mm256_mask_cvtepi16_storeu_epi8() {
         let a = _mm256_set1_epi16(8);
         let mut r = _mm_undefined_si128();
-        _mm256_mask_cvtepi16_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111_11111111, a);
+        unsafe {
+            _mm256_mask_cvtepi16_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111_11111111, a);
+        }
         let e = _mm_set1_epi8(8);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_cvtepi16_storeu_epi8() {
+    fn test_mm_mask_cvtepi16_storeu_epi8() {
         let a = _mm_set1_epi16(8);
         let mut r = _mm_set1_epi8(0);
-        _mm_mask_cvtepi16_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
+        unsafe {
+            _mm_mask_cvtepi16_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
+        }
         let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 8, 8, 8, 8, 8, 8, 8, 8);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512bw")]
-    unsafe fn test_mm512_mask_cvtusepi16_storeu_epi8() {
+    fn test_mm512_mask_cvtusepi16_storeu_epi8() {
         let a = _mm512_set1_epi16(i16::MAX);
         let mut r = _mm256_undefined_si256();
-        _mm512_mask_cvtusepi16_storeu_epi8(
-            &mut r as *mut _ as *mut i8,
-            0b11111111_11111111_11111111_11111111,
-            a,
-        );
+        unsafe {
+            _mm512_mask_cvtusepi16_storeu_epi8(
+                &mut r as *mut _ as *mut i8,
+                0b11111111_11111111_11111111_11111111,
+                a,
+            );
+        }
         let e = _mm256_set1_epi8(u8::MAX as i8);
         assert_eq_m256i(r, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_cvtusepi16_storeu_epi8() {
+    fn test_mm256_mask_cvtusepi16_storeu_epi8() {
         let a = _mm256_set1_epi16(i16::MAX);
         let mut r = _mm_undefined_si128();
-        _mm256_mask_cvtusepi16_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111_11111111, a);
+        unsafe {
+            _mm256_mask_cvtusepi16_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111_11111111, a);
+        }
         let e = _mm_set1_epi8(u8::MAX as i8);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_cvtusepi16_storeu_epi8() {
+    fn test_mm_mask_cvtusepi16_storeu_epi8() {
         let a = _mm_set1_epi16(i16::MAX);
         let mut r = _mm_set1_epi8(0);
-        _mm_mask_cvtusepi16_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
+        unsafe {
+            _mm_mask_cvtusepi16_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
+        }
         #[rustfmt::skip]
         let e = _mm_set_epi8(
             0, 0, 0, 0,
diff --git a/library/stdarch/crates/core_arch/src/x86/avx512dq.rs b/library/stdarch/crates/core_arch/src/x86/avx512dq.rs
index ebe75cd22d8e..9e1a4c0b2955 100644
--- a/library/stdarch/crates/core_arch/src/x86/avx512dq.rs
+++ b/library/stdarch/crates/core_arch/src/x86/avx512dq.rs
@@ -7401,27 +7401,25 @@ unsafe extern "C" {
 mod tests {
     use super::*;
     use crate::core_arch::assert_eq_const as assert_eq;
+    use crate::core_arch::x86::*;
 
     use stdarch_test::simd_test;
 
-    use crate::core_arch::x86::*;
-    use crate::mem::transmute;
+    const OPRND1_64: f64 = f64::from_bits(0x3333333333333333);
+    const OPRND2_64: f64 = f64::from_bits(0x5555555555555555);
 
-    const OPRND1_64: f64 = unsafe { transmute(0x3333333333333333_u64) };
-    const OPRND2_64: f64 = unsafe { transmute(0x5555555555555555_u64) };
+    const AND_64: f64 = f64::from_bits(0x1111111111111111);
+    const ANDN_64: f64 = f64::from_bits(0x4444444444444444);
+    const OR_64: f64 = f64::from_bits(0x7777777777777777);
+    const XOR_64: f64 = f64::from_bits(0x6666666666666666);
 
-    const AND_64: f64 = unsafe { transmute(0x1111111111111111_u64) };
-    const ANDN_64: f64 = unsafe { transmute(0x4444444444444444_u64) };
-    const OR_64: f64 = unsafe { transmute(0x7777777777777777_u64) };
-    const XOR_64: f64 = unsafe { transmute(0x6666666666666666_u64) };
+    const OPRND1_32: f32 = f32::from_bits(0x33333333);
+    const OPRND2_32: f32 = f32::from_bits(0x55555555);
 
-    const OPRND1_32: f32 = unsafe { transmute(0x33333333_u32) };
-    const OPRND2_32: f32 = unsafe { transmute(0x55555555_u32) };
-
-    const AND_32: f32 = unsafe { transmute(0x11111111_u32) };
-    const ANDN_32: f32 = unsafe { transmute(0x44444444_u32) };
-    const OR_32: f32 = unsafe { transmute(0x77777777_u32) };
-    const XOR_32: f32 = unsafe { transmute(0x66666666_u32) };
+    const AND_32: f32 = f32::from_bits(0x11111111);
+    const ANDN_32: f32 = f32::from_bits(0x44444444);
+    const OR_32: f32 = f32::from_bits(0x77777777);
+    const XOR_32: f32 = f32::from_bits(0x66666666);
 
     #[simd_test(enable = "avx512dq,avx512vl")]
     const fn test_mm_mask_and_pd() {
@@ -10023,11 +10021,11 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    const unsafe fn test_kortest_mask8_u8() {
+    const fn test_kortest_mask8_u8() {
         let a: __mmask8 = 0b01101001;
         let b: __mmask8 = 0b10110110;
         let mut all_ones: u8 = 0;
-        let r = _kortest_mask8_u8(a, b, &mut all_ones);
+        let r = unsafe { _kortest_mask8_u8(a, b, &mut all_ones) };
         assert_eq!(r, 0);
         assert_eq!(all_ones, 1);
     }
@@ -10049,7 +10047,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    const unsafe fn test_kshiftli_mask8() {
+    const fn test_kshiftli_mask8() {
         let a: __mmask8 = 0b01101001;
         let r = _kshiftli_mask8::<3>(a);
         let e: __mmask8 = 0b01001000;
@@ -10089,11 +10087,11 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    const unsafe fn test_ktest_mask8_u8() {
+    const fn test_ktest_mask8_u8() {
         let a: __mmask8 = 0b01101001;
         let b: __mmask8 = 0b10010110;
         let mut and_not: u8 = 0;
-        let r = _ktest_mask8_u8(a, b, &mut and_not);
+        let r = unsafe { _ktest_mask8_u8(a, b, &mut and_not) };
         assert_eq!(r, 1);
         assert_eq!(and_not, 0);
     }
@@ -10115,11 +10113,11 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    const unsafe fn test_ktest_mask16_u8() {
+    const fn test_ktest_mask16_u8() {
         let a: __mmask16 = 0b0110100100111100;
         let b: __mmask16 = 0b1001011011000011;
         let mut and_not: u8 = 0;
-        let r = _ktest_mask16_u8(a, b, &mut and_not);
+        let r = unsafe { _ktest_mask16_u8(a, b, &mut and_not) };
         assert_eq!(r, 1);
         assert_eq!(and_not, 0);
     }
@@ -10141,18 +10139,20 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512dq")]
-    const unsafe fn test_load_mask8() {
+    const fn test_load_mask8() {
         let a: __mmask8 = 0b01101001;
-        let r = _load_mask8(&a);
+        let r = unsafe { _load_mask8(&a) };
         let e: __mmask8 = 0b01101001;
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "avx512dq")]
-    const unsafe fn test_store_mask8() {
+    const fn test_store_mask8() {
         let a: __mmask8 = 0b01101001;
         let mut r = 0;
-        _store_mask8(&mut r, a);
+        unsafe {
+            _store_mask8(&mut r, a);
+        }
         let e: __mmask8 = 0b01101001;
         assert_eq!(r, e);
     }
diff --git a/library/stdarch/crates/core_arch/src/x86/avx512f.rs b/library/stdarch/crates/core_arch/src/x86/avx512f.rs
index 76b753938383..3730496e1ec3 100644
--- a/library/stdarch/crates/core_arch/src/x86/avx512f.rs
+++ b/library/stdarch/crates/core_arch/src/x86/avx512f.rs
@@ -48062,9 +48062,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_ternarylogic_epi32() {
-        use core::intrinsics::simd::simd_xor;
-
+    fn test_mm512_ternarylogic_epi32() {
         let a = _mm512_set4_epi32(0b100, 0b110, 0b001, 0b101);
         let b = _mm512_set4_epi32(0b010, 0b011, 0b001, 0b110);
         let c = _mm512_set4_epi32(0b001, 0b000, 0b001, 0b111);
@@ -48077,7 +48075,7 @@ mod tests {
         let r = _mm512_ternarylogic_epi32::<0b10010110>(a, b, c);
         let e = _mm512_set4_epi32(0b111, 0b101, 0b001, 0b100);
         assert_eq_m512i(r, e);
-        assert_eq_m512i(r, simd_xor(simd_xor(a, b), c));
+        assert_eq_m512i(r, _mm512_xor_si512(_mm512_xor_si512(a, b), c));
 
         // Majority (2 or more bits set).
         let r = _mm512_ternarylogic_epi32::<0b1110_1000>(a, b, c);
@@ -48110,9 +48108,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_ternarylogic_epi32() {
-        use core::intrinsics::simd::simd_xor;
-
+    fn test_mm256_ternarylogic_epi32() {
         let _mm256_set4_epi32 = |a, b, c, d| _mm256_setr_epi32(a, b, c, d, a, b, c, d);
 
         let a = _mm256_set4_epi32(0b100, 0b110, 0b001, 0b101);
@@ -48127,7 +48123,7 @@ mod tests {
         let r = _mm256_ternarylogic_epi32::<0b10010110>(a, b, c);
         let e = _mm256_set4_epi32(0b111, 0b101, 0b001, 0b100);
         assert_eq_m256i(r, e);
-        assert_eq_m256i(r, simd_xor(simd_xor(a, b), c));
+        assert_eq_m256i(r, _mm256_xor_si256(_mm256_xor_si256(a, b), c));
 
         // Majority (2 or more bits set).
         let r = _mm256_ternarylogic_epi32::<0b1110_1000>(a, b, c);
@@ -48160,9 +48156,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_ternarylogic_epi32() {
-        use core::intrinsics::simd::simd_xor;
-
+    fn test_mm_ternarylogic_epi32() {
         let a = _mm_setr_epi32(0b100, 0b110, 0b001, 0b101);
         let b = _mm_setr_epi32(0b010, 0b011, 0b001, 0b110);
         let c = _mm_setr_epi32(0b001, 0b000, 0b001, 0b111);
@@ -48175,7 +48169,7 @@ mod tests {
         let r = _mm_ternarylogic_epi32::<0b10010110>(a, b, c);
         let e = _mm_setr_epi32(0b111, 0b101, 0b001, 0b100);
         assert_eq_m128i(r, e);
-        assert_eq_m128i(r, simd_xor(simd_xor(a, b), c));
+        assert_eq_m128i(r, _mm_xor_si128(_mm_xor_si128(a, b), c));
 
         // Majority (2 or more bits set).
         let r = _mm_ternarylogic_epi32::<0b1110_1000>(a, b, c);
@@ -51447,20 +51441,20 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_i32gather_ps() {
+    fn test_mm512_i32gather_ps() {
         let arr: [f32; 256] = core::array::from_fn(|i| i as f32);
         // A multiplier of 4 is word-addressing
         #[rustfmt::skip]
         let index = _mm512_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112,
                                       120, 128, 136, 144, 152, 160, 168, 176);
-        let r = _mm512_i32gather_ps::<4>(index, arr.as_ptr());
+        let r = unsafe { _mm512_i32gather_ps::<4>(index, arr.as_ptr()) };
         #[rustfmt::skip]
         assert_eq_m512(r, _mm512_setr_ps(0., 16., 32., 48., 64., 80., 96., 112.,
                                          120., 128., 136., 144., 152., 160., 168., 176.));
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_i32gather_ps() {
+    fn test_mm512_mask_i32gather_ps() {
         let arr: [f32; 256] = core::array::from_fn(|i| i as f32);
         let src = _mm512_set1_ps(2.);
         let mask = 0b10101010_10101010;
@@ -51468,27 +51462,27 @@ mod tests {
         let index = _mm512_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112,
                                       120, 128, 136, 144, 152, 160, 168, 176);
         // A multiplier of 4 is word-addressing
-        let r = _mm512_mask_i32gather_ps::<4>(src, mask, index, arr.as_ptr());
+        let r = unsafe { _mm512_mask_i32gather_ps::<4>(src, mask, index, arr.as_ptr()) };
         #[rustfmt::skip]
         assert_eq_m512(r, _mm512_setr_ps(2., 16., 2., 48., 2., 80., 2., 112.,
                                          2., 128., 2., 144., 2., 160., 2., 176.));
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_i32gather_epi32() {
+    fn test_mm512_i32gather_epi32() {
         let arr: [i32; 256] = core::array::from_fn(|i| i as i32);
         // A multiplier of 4 is word-addressing
         #[rustfmt::skip]
         let index = _mm512_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112,
                                       120, 128, 136, 144, 152, 160, 168, 176);
-        let r = _mm512_i32gather_epi32::<4>(index, arr.as_ptr());
+        let r = unsafe { _mm512_i32gather_epi32::<4>(index, arr.as_ptr()) };
         #[rustfmt::skip]
         assert_eq_m512i(r, _mm512_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112,
                                              120, 128, 136, 144, 152, 160, 168, 176));
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_i32gather_epi32() {
+    fn test_mm512_mask_i32gather_epi32() {
         let arr: [i32; 256] = core::array::from_fn(|i| i as i32);
         let src = _mm512_set1_epi32(2);
         let mask = 0b10101010_10101010;
@@ -51496,7 +51490,7 @@ mod tests {
             0, 16, 32, 48, 64, 80, 96, 112, 128, 144, 160, 176, 192, 208, 224, 240,
         );
         // A multiplier of 4 is word-addressing
-        let r = _mm512_mask_i32gather_epi32::<4>(src, mask, index, arr.as_ptr());
+        let r = unsafe { _mm512_mask_i32gather_epi32::<4>(src, mask, index, arr.as_ptr()) };
         assert_eq_m512i(
             r,
             _mm512_setr_epi32(2, 16, 2, 48, 2, 80, 2, 112, 2, 144, 2, 176, 2, 208, 2, 240),
@@ -51504,7 +51498,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_i32scatter_ps() {
+    fn test_mm512_i32scatter_ps() {
         let mut arr = [0f32; 256];
         #[rustfmt::skip]
         let index = _mm512_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112,
@@ -51513,7 +51507,9 @@ mod tests {
             1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16.,
         );
         // A multiplier of 4 is word-addressing
-        _mm512_i32scatter_ps::<4>(arr.as_mut_ptr(), index, src);
+        unsafe {
+            _mm512_i32scatter_ps::<4>(arr.as_mut_ptr(), index, src);
+        }
         let mut expected = [0f32; 256];
         for i in 0..16 {
             expected[i * 16] = (i + 1) as f32;
@@ -51522,7 +51518,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_i32scatter_ps() {
+    fn test_mm512_mask_i32scatter_ps() {
         let mut arr = [0f32; 256];
         let mask = 0b10101010_10101010;
         #[rustfmt::skip]
@@ -51532,7 +51528,9 @@ mod tests {
             1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16.,
         );
         // A multiplier of 4 is word-addressing
-        _mm512_mask_i32scatter_ps::<4>(arr.as_mut_ptr(), mask, index, src);
+        unsafe {
+            _mm512_mask_i32scatter_ps::<4>(arr.as_mut_ptr(), mask, index, src);
+        }
         let mut expected = [0f32; 256];
         for i in 0..8 {
             expected[i * 32 + 16] = 2. * (i + 1) as f32;
@@ -51541,7 +51539,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_i32scatter_epi32() {
+    fn test_mm512_i32scatter_epi32() {
         let mut arr = [0i32; 256];
         #[rustfmt::skip]
 
@@ -51549,7 +51547,9 @@ mod tests {
                                       128, 144, 160, 176, 192, 208, 224, 240);
         let src = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         // A multiplier of 4 is word-addressing
-        _mm512_i32scatter_epi32::<4>(arr.as_mut_ptr(), index, src);
+        unsafe {
+            _mm512_i32scatter_epi32::<4>(arr.as_mut_ptr(), index, src);
+        }
         let mut expected = [0i32; 256];
         for i in 0..16 {
             expected[i * 16] = (i + 1) as i32;
@@ -51558,7 +51558,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_i32scatter_epi32() {
+    fn test_mm512_mask_i32scatter_epi32() {
         let mut arr = [0i32; 256];
         let mask = 0b10101010_10101010;
         #[rustfmt::skip]
@@ -51566,7 +51566,9 @@ mod tests {
                                       128, 144, 160, 176, 192, 208, 224, 240);
         let src = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         // A multiplier of 4 is word-addressing
-        _mm512_mask_i32scatter_epi32::<4>(arr.as_mut_ptr(), mask, index, src);
+        unsafe {
+            _mm512_mask_i32scatter_epi32::<4>(arr.as_mut_ptr(), mask, index, src);
+        }
         let mut expected = [0i32; 256];
         for i in 0..8 {
             expected[i * 32 + 16] = 2 * (i + 1) as i32;
@@ -52850,29 +52852,31 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_loadu_pd() {
+    const fn test_mm512_loadu_pd() {
         let a = &[4., 3., 2., 5., 8., 9., 64., 50.];
         let p = a.as_ptr();
-        let r = _mm512_loadu_pd(black_box(p));
+        let r = unsafe { _mm512_loadu_pd(black_box(p)) };
         let e = _mm512_setr_pd(4., 3., 2., 5., 8., 9., 64., 50.);
         assert_eq_m512d(r, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_storeu_pd() {
+    const fn test_mm512_storeu_pd() {
         let a = _mm512_set1_pd(9.);
         let mut r = _mm512_undefined_pd();
-        _mm512_storeu_pd(&mut r as *mut _ as *mut f64, a);
+        unsafe {
+            _mm512_storeu_pd(&mut r as *mut _ as *mut f64, a);
+        }
         assert_eq_m512d(r, a);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_loadu_ps() {
+    const fn test_mm512_loadu_ps() {
         let a = &[
             4., 3., 2., 5., 8., 9., 64., 50., -4., -3., -2., -5., -8., -9., -64., -50.,
         ];
         let p = a.as_ptr();
-        let r = _mm512_loadu_ps(black_box(p));
+        let r = unsafe { _mm512_loadu_ps(black_box(p)) };
         let e = _mm512_setr_ps(
             4., 3., 2., 5., 8., 9., 64., 50., -4., -3., -2., -5., -8., -9., -64., -50.,
         );
@@ -52880,36 +52884,38 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_storeu_ps() {
+    const fn test_mm512_storeu_ps() {
         let a = _mm512_set1_ps(9.);
         let mut r = _mm512_undefined_ps();
-        _mm512_storeu_ps(&mut r as *mut _ as *mut f32, a);
+        unsafe {
+            _mm512_storeu_ps(&mut r as *mut _ as *mut f32, a);
+        }
         assert_eq_m512(r, a);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_loadu_epi32() {
+    const fn test_mm512_mask_loadu_epi32() {
         let src = _mm512_set1_epi32(42);
         let a = &[1_i32, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16];
         let p = a.as_ptr();
         let m = 0b11101000_11001010;
-        let r = _mm512_mask_loadu_epi32(src, m, black_box(p));
+        let r = unsafe { _mm512_mask_loadu_epi32(src, m, black_box(p)) };
         let e = _mm512_setr_epi32(42, 2, 42, 4, 42, 42, 7, 8, 42, 42, 42, 12, 42, 14, 15, 16);
         assert_eq_m512i(r, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_loadu_epi32() {
+    const fn test_mm512_maskz_loadu_epi32() {
         let a = &[1_i32, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16];
         let p = a.as_ptr();
         let m = 0b11101000_11001010;
-        let r = _mm512_maskz_loadu_epi32(m, black_box(p));
+        let r = unsafe { _mm512_maskz_loadu_epi32(m, black_box(p)) };
         let e = _mm512_setr_epi32(0, 2, 0, 4, 0, 0, 7, 8, 0, 0, 0, 12, 0, 14, 15, 16);
         assert_eq_m512i(r, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_load_epi32() {
+    const fn test_mm512_mask_load_epi32() {
         #[repr(align(64))]
         struct Align {
             data: [i32; 16], // 64 bytes
@@ -52920,13 +52926,13 @@ mod tests {
         };
         let p = a.data.as_ptr();
         let m = 0b11101000_11001010;
-        let r = _mm512_mask_load_epi32(src, m, black_box(p));
+        let r = unsafe { _mm512_mask_load_epi32(src, m, black_box(p)) };
         let e = _mm512_setr_epi32(42, 2, 42, 4, 42, 42, 7, 8, 42, 42, 42, 12, 42, 14, 15, 16);
         assert_eq_m512i(r, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_load_epi32() {
+    const fn test_mm512_maskz_load_epi32() {
         #[repr(align(64))]
         struct Align {
             data: [i32; 16], // 64 bytes
@@ -52936,23 +52942,25 @@ mod tests {
         };
         let p = a.data.as_ptr();
         let m = 0b11101000_11001010;
-        let r = _mm512_maskz_load_epi32(m, black_box(p));
+        let r = unsafe { _mm512_maskz_load_epi32(m, black_box(p)) };
         let e = _mm512_setr_epi32(0, 2, 0, 4, 0, 0, 7, 8, 0, 0, 0, 12, 0, 14, 15, 16);
         assert_eq_m512i(r, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_storeu_epi32() {
+    const fn test_mm512_mask_storeu_epi32() {
         let mut r = [42_i32; 16];
         let a = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let m = 0b11101000_11001010;
-        _mm512_mask_storeu_epi32(r.as_mut_ptr(), m, a);
+        unsafe {
+            _mm512_mask_storeu_epi32(r.as_mut_ptr(), m, a);
+        }
         let e = _mm512_setr_epi32(42, 2, 42, 4, 42, 42, 7, 8, 42, 42, 42, 12, 42, 14, 15, 16);
-        assert_eq_m512i(_mm512_loadu_epi32(r.as_ptr()), e);
+        assert_eq_m512i(unsafe { _mm512_loadu_epi32(r.as_ptr()) }, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_store_epi32() {
+    const fn test_mm512_mask_store_epi32() {
         #[repr(align(64))]
         struct Align {
             data: [i32; 16],
@@ -52960,34 +52968,36 @@ mod tests {
         let mut r = Align { data: [42; 16] };
         let a = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let m = 0b11101000_11001010;
-        _mm512_mask_store_epi32(r.data.as_mut_ptr(), m, a);
+        unsafe {
+            _mm512_mask_store_epi32(r.data.as_mut_ptr(), m, a);
+        }
         let e = _mm512_setr_epi32(42, 2, 42, 4, 42, 42, 7, 8, 42, 42, 42, 12, 42, 14, 15, 16);
-        assert_eq_m512i(_mm512_load_epi32(r.data.as_ptr()), e);
+        assert_eq_m512i(unsafe { _mm512_load_epi32(r.data.as_ptr()) }, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_loadu_epi64() {
+    const fn test_mm512_mask_loadu_epi64() {
         let src = _mm512_set1_epi64(42);
         let a = &[1_i64, 2, 3, 4, 5, 6, 7, 8];
         let p = a.as_ptr();
         let m = 0b11001010;
-        let r = _mm512_mask_loadu_epi64(src, m, black_box(p));
+        let r = unsafe { _mm512_mask_loadu_epi64(src, m, black_box(p)) };
         let e = _mm512_setr_epi64(42, 2, 42, 4, 42, 42, 7, 8);
         assert_eq_m512i(r, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_loadu_epi64() {
+    const fn test_mm512_maskz_loadu_epi64() {
         let a = &[1_i64, 2, 3, 4, 5, 6, 7, 8];
         let p = a.as_ptr();
         let m = 0b11001010;
-        let r = _mm512_maskz_loadu_epi64(m, black_box(p));
+        let r = unsafe { _mm512_maskz_loadu_epi64(m, black_box(p)) };
         let e = _mm512_setr_epi64(0, 2, 0, 4, 0, 0, 7, 8);
         assert_eq_m512i(r, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_load_epi64() {
+    const fn test_mm512_mask_load_epi64() {
         #[repr(align(64))]
         struct Align {
             data: [i64; 8], // 64 bytes
@@ -52998,13 +53008,13 @@ mod tests {
         };
         let p = a.data.as_ptr();
         let m = 0b11001010;
-        let r = _mm512_mask_load_epi64(src, m, black_box(p));
+        let r = unsafe { _mm512_mask_load_epi64(src, m, black_box(p)) };
         let e = _mm512_setr_epi64(42, 2, 42, 4, 42, 42, 7, 8);
         assert_eq_m512i(r, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_load_epi64() {
+    const fn test_mm512_maskz_load_epi64() {
         #[repr(align(64))]
         struct Align {
             data: [i64; 8], // 64 bytes
@@ -53014,23 +53024,25 @@ mod tests {
         };
         let p = a.data.as_ptr();
         let m = 0b11001010;
-        let r = _mm512_maskz_load_epi64(m, black_box(p));
+        let r = unsafe { _mm512_maskz_load_epi64(m, black_box(p)) };
         let e = _mm512_setr_epi64(0, 2, 0, 4, 0, 0, 7, 8);
         assert_eq_m512i(r, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_storeu_epi64() {
+    const fn test_mm512_mask_storeu_epi64() {
         let mut r = [42_i64; 8];
         let a = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
         let m = 0b11001010;
-        _mm512_mask_storeu_epi64(r.as_mut_ptr(), m, a);
+        unsafe {
+            _mm512_mask_storeu_epi64(r.as_mut_ptr(), m, a);
+        }
         let e = _mm512_setr_epi64(42, 2, 42, 4, 42, 42, 7, 8);
-        assert_eq_m512i(_mm512_loadu_epi64(r.as_ptr()), e);
+        assert_eq_m512i(unsafe { _mm512_loadu_epi64(r.as_ptr()) }, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_store_epi64() {
+    const fn test_mm512_mask_store_epi64() {
         #[repr(align(64))]
         struct Align {
             data: [i64; 8],
@@ -53039,13 +53051,15 @@ mod tests {
         let a = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
         let m = 0b11001010;
         let p = r.data.as_mut_ptr();
-        _mm512_mask_store_epi64(p, m, a);
+        unsafe {
+            _mm512_mask_store_epi64(p, m, a);
+        }
         let e = _mm512_setr_epi64(42, 2, 42, 4, 42, 42, 7, 8);
-        assert_eq_m512i(_mm512_load_epi64(r.data.as_ptr()), e);
+        assert_eq_m512i(unsafe { _mm512_load_epi64(r.data.as_ptr()) }, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_loadu_ps() {
+    const fn test_mm512_mask_loadu_ps() {
         let src = _mm512_set1_ps(42.0);
         let a = &[
             1.0_f32, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0,
@@ -53053,7 +53067,7 @@ mod tests {
         ];
         let p = a.as_ptr();
         let m = 0b11101000_11001010;
-        let r = _mm512_mask_loadu_ps(src, m, black_box(p));
+        let r = unsafe { _mm512_mask_loadu_ps(src, m, black_box(p)) };
         let e = _mm512_setr_ps(
             42.0, 2.0, 42.0, 4.0, 42.0, 42.0, 7.0, 8.0, 42.0, 42.0, 42.0, 12.0, 42.0, 14.0, 15.0,
             16.0,
@@ -53062,14 +53076,14 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_loadu_ps() {
+    const fn test_mm512_maskz_loadu_ps() {
         let a = &[
             1.0_f32, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0,
             16.0,
         ];
         let p = a.as_ptr();
         let m = 0b11101000_11001010;
-        let r = _mm512_maskz_loadu_ps(m, black_box(p));
+        let r = unsafe { _mm512_maskz_loadu_ps(m, black_box(p)) };
         let e = _mm512_setr_ps(
             0.0, 2.0, 0.0, 4.0, 0.0, 0.0, 7.0, 8.0, 0.0, 0.0, 0.0, 12.0, 0.0, 14.0, 15.0, 16.0,
         );
@@ -53077,7 +53091,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_load_ps() {
+    const fn test_mm512_mask_load_ps() {
         #[repr(align(64))]
         struct Align {
             data: [f32; 16], // 64 bytes
@@ -53091,7 +53105,7 @@ mod tests {
         };
         let p = a.data.as_ptr();
         let m = 0b11101000_11001010;
-        let r = _mm512_mask_load_ps(src, m, black_box(p));
+        let r = unsafe { _mm512_mask_load_ps(src, m, black_box(p)) };
         let e = _mm512_setr_ps(
             42.0, 2.0, 42.0, 4.0, 42.0, 42.0, 7.0, 8.0, 42.0, 42.0, 42.0, 12.0, 42.0, 14.0, 15.0,
             16.0,
@@ -53100,7 +53114,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_load_ps() {
+    const fn test_mm512_maskz_load_ps() {
         #[repr(align(64))]
         struct Align {
             data: [f32; 16], // 64 bytes
@@ -53113,7 +53127,7 @@ mod tests {
         };
         let p = a.data.as_ptr();
         let m = 0b11101000_11001010;
-        let r = _mm512_maskz_load_ps(m, black_box(p));
+        let r = unsafe { _mm512_maskz_load_ps(m, black_box(p)) };
         let e = _mm512_setr_ps(
             0.0, 2.0, 0.0, 4.0, 0.0, 0.0, 7.0, 8.0, 0.0, 0.0, 0.0, 12.0, 0.0, 14.0, 15.0, 16.0,
         );
@@ -53121,22 +53135,24 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_storeu_ps() {
+    const fn test_mm512_mask_storeu_ps() {
         let mut r = [42_f32; 16];
         let a = _mm512_setr_ps(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
         );
         let m = 0b11101000_11001010;
-        _mm512_mask_storeu_ps(r.as_mut_ptr(), m, a);
+        unsafe {
+            _mm512_mask_storeu_ps(r.as_mut_ptr(), m, a);
+        }
         let e = _mm512_setr_ps(
             42.0, 2.0, 42.0, 4.0, 42.0, 42.0, 7.0, 8.0, 42.0, 42.0, 42.0, 12.0, 42.0, 14.0, 15.0,
             16.0,
         );
-        assert_eq_m512(_mm512_loadu_ps(r.as_ptr()), e);
+        assert_eq_m512(unsafe { _mm512_loadu_ps(r.as_ptr()) }, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_store_ps() {
+    const fn test_mm512_mask_store_ps() {
         #[repr(align(64))]
         struct Align {
             data: [f32; 16],
@@ -53146,37 +53162,39 @@ mod tests {
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
         );
         let m = 0b11101000_11001010;
-        _mm512_mask_store_ps(r.data.as_mut_ptr(), m, a);
+        unsafe {
+            _mm512_mask_store_ps(r.data.as_mut_ptr(), m, a);
+        }
         let e = _mm512_setr_ps(
             42.0, 2.0, 42.0, 4.0, 42.0, 42.0, 7.0, 8.0, 42.0, 42.0, 42.0, 12.0, 42.0, 14.0, 15.0,
             16.0,
         );
-        assert_eq_m512(_mm512_load_ps(r.data.as_ptr()), e);
+        assert_eq_m512(unsafe { _mm512_load_ps(r.data.as_ptr()) }, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_loadu_pd() {
+    const fn test_mm512_mask_loadu_pd() {
         let src = _mm512_set1_pd(42.0);
         let a = &[1.0_f64, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0];
         let p = a.as_ptr();
         let m = 0b11001010;
-        let r = _mm512_mask_loadu_pd(src, m, black_box(p));
+        let r = unsafe { _mm512_mask_loadu_pd(src, m, black_box(p)) };
         let e = _mm512_setr_pd(42.0, 2.0, 42.0, 4.0, 42.0, 42.0, 7.0, 8.0);
         assert_eq_m512d(r, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_loadu_pd() {
+    const fn test_mm512_maskz_loadu_pd() {
         let a = &[1.0_f64, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0];
         let p = a.as_ptr();
         let m = 0b11001010;
-        let r = _mm512_maskz_loadu_pd(m, black_box(p));
+        let r = unsafe { _mm512_maskz_loadu_pd(m, black_box(p)) };
         let e = _mm512_setr_pd(0.0, 2.0, 0.0, 4.0, 0.0, 0.0, 7.0, 8.0);
         assert_eq_m512d(r, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_load_pd() {
+    const fn test_mm512_mask_load_pd() {
         #[repr(align(64))]
         struct Align {
             data: [f64; 8], // 64 bytes
@@ -53187,13 +53205,13 @@ mod tests {
         };
         let p = a.data.as_ptr();
         let m = 0b11001010;
-        let r = _mm512_mask_load_pd(src, m, black_box(p));
+        let r = unsafe { _mm512_mask_load_pd(src, m, black_box(p)) };
         let e = _mm512_setr_pd(42.0, 2.0, 42.0, 4.0, 42.0, 42.0, 7.0, 8.0);
         assert_eq_m512d(r, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_maskz_load_pd() {
+    const fn test_mm512_maskz_load_pd() {
         #[repr(align(64))]
         struct Align {
             data: [f64; 8], // 64 bytes
@@ -53203,23 +53221,25 @@ mod tests {
         };
         let p = a.data.as_ptr();
         let m = 0b11001010;
-        let r = _mm512_maskz_load_pd(m, black_box(p));
+        let r = unsafe { _mm512_maskz_load_pd(m, black_box(p)) };
         let e = _mm512_setr_pd(0.0, 2.0, 0.0, 4.0, 0.0, 0.0, 7.0, 8.0);
         assert_eq_m512d(r, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_storeu_pd() {
+    const fn test_mm512_mask_storeu_pd() {
         let mut r = [42_f64; 8];
         let a = _mm512_setr_pd(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let m = 0b11001010;
-        _mm512_mask_storeu_pd(r.as_mut_ptr(), m, a);
+        unsafe {
+            _mm512_mask_storeu_pd(r.as_mut_ptr(), m, a);
+        }
         let e = _mm512_setr_pd(42.0, 2.0, 42.0, 4.0, 42.0, 42.0, 7.0, 8.0);
-        assert_eq_m512d(_mm512_loadu_pd(r.as_ptr()), e);
+        assert_eq_m512d(unsafe { _mm512_loadu_pd(r.as_ptr()) }, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_mask_store_pd() {
+    const fn test_mm512_mask_store_pd() {
         #[repr(align(64))]
         struct Align {
             data: [f64; 8],
@@ -53227,34 +53247,36 @@ mod tests {
         let mut r = Align { data: [42.0; 8] };
         let a = _mm512_setr_pd(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let m = 0b11001010;
-        _mm512_mask_store_pd(r.data.as_mut_ptr(), m, a);
+        unsafe {
+            _mm512_mask_store_pd(r.data.as_mut_ptr(), m, a);
+        }
         let e = _mm512_setr_pd(42.0, 2.0, 42.0, 4.0, 42.0, 42.0, 7.0, 8.0);
-        assert_eq_m512d(_mm512_load_pd(r.data.as_ptr()), e);
+        assert_eq_m512d(unsafe { _mm512_load_pd(r.data.as_ptr()) }, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_loadu_epi32() {
+    const fn test_mm256_mask_loadu_epi32() {
         let src = _mm256_set1_epi32(42);
         let a = &[1_i32, 2, 3, 4, 5, 6, 7, 8];
         let p = a.as_ptr();
         let m = 0b11001010;
-        let r = _mm256_mask_loadu_epi32(src, m, black_box(p));
+        let r = unsafe { _mm256_mask_loadu_epi32(src, m, black_box(p)) };
         let e = _mm256_setr_epi32(42, 2, 42, 4, 42, 42, 7, 8);
         assert_eq_m256i(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_loadu_epi32() {
+    const fn test_mm256_maskz_loadu_epi32() {
         let a = &[1_i32, 2, 3, 4, 5, 6, 7, 8];
         let p = a.as_ptr();
         let m = 0b11001010;
-        let r = _mm256_maskz_loadu_epi32(m, black_box(p));
+        let r = unsafe { _mm256_maskz_loadu_epi32(m, black_box(p)) };
         let e = _mm256_setr_epi32(0, 2, 0, 4, 0, 0, 7, 8);
         assert_eq_m256i(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_load_epi32() {
+    const fn test_mm256_mask_load_epi32() {
         #[repr(align(32))]
         struct Align {
             data: [i32; 8], // 32 bytes
@@ -53265,13 +53287,13 @@ mod tests {
         };
         let p = a.data.as_ptr();
         let m = 0b11001010;
-        let r = _mm256_mask_load_epi32(src, m, black_box(p));
+        let r = unsafe { _mm256_mask_load_epi32(src, m, black_box(p)) };
         let e = _mm256_setr_epi32(42, 2, 42, 4, 42, 42, 7, 8);
         assert_eq_m256i(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_load_epi32() {
+    const fn test_mm256_maskz_load_epi32() {
         #[repr(align(32))]
         struct Align {
             data: [i32; 8], // 32 bytes
@@ -53281,23 +53303,25 @@ mod tests {
         };
         let p = a.data.as_ptr();
         let m = 0b11001010;
-        let r = _mm256_maskz_load_epi32(m, black_box(p));
+        let r = unsafe { _mm256_maskz_load_epi32(m, black_box(p)) };
         let e = _mm256_setr_epi32(0, 2, 0, 4, 0, 0, 7, 8);
         assert_eq_m256i(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_storeu_epi32() {
+    const fn test_mm256_mask_storeu_epi32() {
         let mut r = [42_i32; 8];
         let a = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8);
         let m = 0b11001010;
-        _mm256_mask_storeu_epi32(r.as_mut_ptr(), m, a);
+        unsafe {
+            _mm256_mask_storeu_epi32(r.as_mut_ptr(), m, a);
+        }
         let e = _mm256_setr_epi32(42, 2, 42, 4, 42, 42, 7, 8);
-        assert_eq_m256i(_mm256_loadu_epi32(r.as_ptr()), e);
+        assert_eq_m256i(unsafe { _mm256_loadu_epi32(r.as_ptr()) }, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_store_epi32() {
+    const fn test_mm256_mask_store_epi32() {
         #[repr(align(64))]
         struct Align {
             data: [i32; 8],
@@ -53305,34 +53329,36 @@ mod tests {
         let mut r = Align { data: [42; 8] };
         let a = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8);
         let m = 0b11001010;
-        _mm256_mask_store_epi32(r.data.as_mut_ptr(), m, a);
+        unsafe {
+            _mm256_mask_store_epi32(r.data.as_mut_ptr(), m, a);
+        }
         let e = _mm256_setr_epi32(42, 2, 42, 4, 42, 42, 7, 8);
-        assert_eq_m256i(_mm256_load_epi32(r.data.as_ptr()), e);
+        assert_eq_m256i(unsafe { _mm256_load_epi32(r.data.as_ptr()) }, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_loadu_epi64() {
+    const fn test_mm256_mask_loadu_epi64() {
         let src = _mm256_set1_epi64x(42);
         let a = &[1_i64, 2, 3, 4];
         let p = a.as_ptr();
         let m = 0b1010;
-        let r = _mm256_mask_loadu_epi64(src, m, black_box(p));
+        let r = unsafe { _mm256_mask_loadu_epi64(src, m, black_box(p)) };
         let e = _mm256_setr_epi64x(42, 2, 42, 4);
         assert_eq_m256i(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_loadu_epi64() {
+    const fn test_mm256_maskz_loadu_epi64() {
         let a = &[1_i64, 2, 3, 4];
         let p = a.as_ptr();
         let m = 0b1010;
-        let r = _mm256_maskz_loadu_epi64(m, black_box(p));
+        let r = unsafe { _mm256_maskz_loadu_epi64(m, black_box(p)) };
         let e = _mm256_setr_epi64x(0, 2, 0, 4);
         assert_eq_m256i(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_load_epi64() {
+    const fn test_mm256_mask_load_epi64() {
         #[repr(align(32))]
         struct Align {
             data: [i64; 4], // 32 bytes
@@ -53343,13 +53369,13 @@ mod tests {
         };
         let p = a.data.as_ptr();
         let m = 0b1010;
-        let r = _mm256_mask_load_epi64(src, m, black_box(p));
+        let r = unsafe { _mm256_mask_load_epi64(src, m, black_box(p)) };
         let e = _mm256_setr_epi64x(42, 2, 42, 4);
         assert_eq_m256i(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_load_epi64() {
+    const fn test_mm256_maskz_load_epi64() {
         #[repr(align(32))]
         struct Align {
             data: [i64; 4], // 32 bytes
@@ -53359,23 +53385,25 @@ mod tests {
         };
         let p = a.data.as_ptr();
         let m = 0b1010;
-        let r = _mm256_maskz_load_epi64(m, black_box(p));
+        let r = unsafe { _mm256_maskz_load_epi64(m, black_box(p)) };
         let e = _mm256_setr_epi64x(0, 2, 0, 4);
         assert_eq_m256i(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_storeu_epi64() {
+    const fn test_mm256_mask_storeu_epi64() {
         let mut r = [42_i64; 4];
         let a = _mm256_setr_epi64x(1, 2, 3, 4);
         let m = 0b1010;
-        _mm256_mask_storeu_epi64(r.as_mut_ptr(), m, a);
+        unsafe {
+            _mm256_mask_storeu_epi64(r.as_mut_ptr(), m, a);
+        }
         let e = _mm256_setr_epi64x(42, 2, 42, 4);
-        assert_eq_m256i(_mm256_loadu_epi64(r.as_ptr()), e);
+        assert_eq_m256i(unsafe { _mm256_loadu_epi64(r.as_ptr()) }, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_store_epi64() {
+    const fn test_mm256_mask_store_epi64() {
         #[repr(align(32))]
         struct Align {
             data: [i64; 4],
@@ -53383,34 +53411,36 @@ mod tests {
         let mut r = Align { data: [42; 4] };
         let a = _mm256_setr_epi64x(1, 2, 3, 4);
         let m = 0b1010;
-        _mm256_mask_store_epi64(r.data.as_mut_ptr(), m, a);
+        unsafe {
+            _mm256_mask_store_epi64(r.data.as_mut_ptr(), m, a);
+        }
         let e = _mm256_setr_epi64x(42, 2, 42, 4);
-        assert_eq_m256i(_mm256_load_epi64(r.data.as_ptr()), e);
+        assert_eq_m256i(unsafe { _mm256_load_epi64(r.data.as_ptr()) }, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_loadu_ps() {
+    const fn test_mm256_mask_loadu_ps() {
         let src = _mm256_set1_ps(42.0);
         let a = &[1.0_f32, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0];
         let p = a.as_ptr();
         let m = 0b11001010;
-        let r = _mm256_mask_loadu_ps(src, m, black_box(p));
+        let r = unsafe { _mm256_mask_loadu_ps(src, m, black_box(p)) };
         let e = _mm256_setr_ps(42.0, 2.0, 42.0, 4.0, 42.0, 42.0, 7.0, 8.0);
         assert_eq_m256(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_loadu_ps() {
+    const fn test_mm256_maskz_loadu_ps() {
         let a = &[1.0_f32, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0];
         let p = a.as_ptr();
         let m = 0b11001010;
-        let r = _mm256_maskz_loadu_ps(m, black_box(p));
+        let r = unsafe { _mm256_maskz_loadu_ps(m, black_box(p)) };
         let e = _mm256_setr_ps(0.0, 2.0, 0.0, 4.0, 0.0, 0.0, 7.0, 8.0);
         assert_eq_m256(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_load_ps() {
+    const fn test_mm256_mask_load_ps() {
         #[repr(align(32))]
         struct Align {
             data: [f32; 8], // 32 bytes
@@ -53421,13 +53451,13 @@ mod tests {
         };
         let p = a.data.as_ptr();
         let m = 0b11001010;
-        let r = _mm256_mask_load_ps(src, m, black_box(p));
+        let r = unsafe { _mm256_mask_load_ps(src, m, black_box(p)) };
         let e = _mm256_setr_ps(42.0, 2.0, 42.0, 4.0, 42.0, 42.0, 7.0, 8.0);
         assert_eq_m256(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_load_ps() {
+    const fn test_mm256_maskz_load_ps() {
         #[repr(align(32))]
         struct Align {
             data: [f32; 8], // 32 bytes
@@ -53437,23 +53467,25 @@ mod tests {
         };
         let p = a.data.as_ptr();
         let m = 0b11001010;
-        let r = _mm256_maskz_load_ps(m, black_box(p));
+        let r = unsafe { _mm256_maskz_load_ps(m, black_box(p)) };
         let e = _mm256_setr_ps(0.0, 2.0, 0.0, 4.0, 0.0, 0.0, 7.0, 8.0);
         assert_eq_m256(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_storeu_ps() {
+    const fn test_mm256_mask_storeu_ps() {
         let mut r = [42_f32; 8];
         let a = _mm256_setr_ps(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let m = 0b11001010;
-        _mm256_mask_storeu_ps(r.as_mut_ptr(), m, a);
+        unsafe {
+            _mm256_mask_storeu_ps(r.as_mut_ptr(), m, a);
+        }
         let e = _mm256_setr_ps(42.0, 2.0, 42.0, 4.0, 42.0, 42.0, 7.0, 8.0);
-        assert_eq_m256(_mm256_loadu_ps(r.as_ptr()), e);
+        assert_eq_m256(unsafe { _mm256_loadu_ps(r.as_ptr()) }, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_store_ps() {
+    const fn test_mm256_mask_store_ps() {
         #[repr(align(32))]
         struct Align {
             data: [f32; 8],
@@ -53461,34 +53493,36 @@ mod tests {
         let mut r = Align { data: [42.0; 8] };
         let a = _mm256_setr_ps(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let m = 0b11001010;
-        _mm256_mask_store_ps(r.data.as_mut_ptr(), m, a);
+        unsafe {
+            _mm256_mask_store_ps(r.data.as_mut_ptr(), m, a);
+        }
         let e = _mm256_setr_ps(42.0, 2.0, 42.0, 4.0, 42.0, 42.0, 7.0, 8.0);
-        assert_eq_m256(_mm256_load_ps(r.data.as_ptr()), e);
+        assert_eq_m256(unsafe { _mm256_load_ps(r.data.as_ptr()) }, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_loadu_pd() {
+    const fn test_mm256_mask_loadu_pd() {
         let src = _mm256_set1_pd(42.0);
         let a = &[1.0_f64, 2.0, 3.0, 4.0];
         let p = a.as_ptr();
         let m = 0b1010;
-        let r = _mm256_mask_loadu_pd(src, m, black_box(p));
+        let r = unsafe { _mm256_mask_loadu_pd(src, m, black_box(p)) };
         let e = _mm256_setr_pd(42.0, 2.0, 42.0, 4.0);
         assert_eq_m256d(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_loadu_pd() {
+    const fn test_mm256_maskz_loadu_pd() {
         let a = &[1.0_f64, 2.0, 3.0, 4.0];
         let p = a.as_ptr();
         let m = 0b1010;
-        let r = _mm256_maskz_loadu_pd(m, black_box(p));
+        let r = unsafe { _mm256_maskz_loadu_pd(m, black_box(p)) };
         let e = _mm256_setr_pd(0.0, 2.0, 0.0, 4.0);
         assert_eq_m256d(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_load_pd() {
+    const fn test_mm256_mask_load_pd() {
         #[repr(align(32))]
         struct Align {
             data: [f64; 4], // 32 bytes
@@ -53499,13 +53533,13 @@ mod tests {
         };
         let p = a.data.as_ptr();
         let m = 0b1010;
-        let r = _mm256_mask_load_pd(src, m, black_box(p));
+        let r = unsafe { _mm256_mask_load_pd(src, m, black_box(p)) };
         let e = _mm256_setr_pd(42.0, 2.0, 42.0, 4.0);
         assert_eq_m256d(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_maskz_load_pd() {
+    const fn test_mm256_maskz_load_pd() {
         #[repr(align(32))]
         struct Align {
             data: [f64; 4], // 32 bytes
@@ -53515,23 +53549,25 @@ mod tests {
         };
         let p = a.data.as_ptr();
         let m = 0b1010;
-        let r = _mm256_maskz_load_pd(m, black_box(p));
+        let r = unsafe { _mm256_maskz_load_pd(m, black_box(p)) };
         let e = _mm256_setr_pd(0.0, 2.0, 0.0, 4.0);
         assert_eq_m256d(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_storeu_pd() {
+    const fn test_mm256_mask_storeu_pd() {
         let mut r = [42_f64; 4];
         let a = _mm256_setr_pd(1.0, 2.0, 3.0, 4.0);
         let m = 0b1010;
-        _mm256_mask_storeu_pd(r.as_mut_ptr(), m, a);
+        unsafe {
+            _mm256_mask_storeu_pd(r.as_mut_ptr(), m, a);
+        }
         let e = _mm256_setr_pd(42.0, 2.0, 42.0, 4.0);
-        assert_eq_m256d(_mm256_loadu_pd(r.as_ptr()), e);
+        assert_eq_m256d(unsafe { _mm256_loadu_pd(r.as_ptr()) }, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_mask_store_pd() {
+    const fn test_mm256_mask_store_pd() {
         #[repr(align(32))]
         struct Align {
             data: [f64; 4],
@@ -53539,34 +53575,36 @@ mod tests {
         let mut r = Align { data: [42.0; 4] };
         let a = _mm256_setr_pd(1.0, 2.0, 3.0, 4.0);
         let m = 0b1010;
-        _mm256_mask_store_pd(r.data.as_mut_ptr(), m, a);
+        unsafe {
+            _mm256_mask_store_pd(r.data.as_mut_ptr(), m, a);
+        }
         let e = _mm256_setr_pd(42.0, 2.0, 42.0, 4.0);
-        assert_eq_m256d(_mm256_load_pd(r.data.as_ptr()), e);
+        assert_eq_m256d(unsafe { _mm256_load_pd(r.data.as_ptr()) }, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_loadu_epi32() {
+    const fn test_mm_mask_loadu_epi32() {
         let src = _mm_set1_epi32(42);
         let a = &[1_i32, 2, 3, 4];
         let p = a.as_ptr();
         let m = 0b1010;
-        let r = _mm_mask_loadu_epi32(src, m, black_box(p));
+        let r = unsafe { _mm_mask_loadu_epi32(src, m, black_box(p)) };
         let e = _mm_setr_epi32(42, 2, 42, 4);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_loadu_epi32() {
+    const fn test_mm_maskz_loadu_epi32() {
         let a = &[1_i32, 2, 3, 4];
         let p = a.as_ptr();
         let m = 0b1010;
-        let r = _mm_maskz_loadu_epi32(m, black_box(p));
+        let r = unsafe { _mm_maskz_loadu_epi32(m, black_box(p)) };
         let e = _mm_setr_epi32(0, 2, 0, 4);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_load_epi32() {
+    const fn test_mm_mask_load_epi32() {
         #[repr(align(16))]
         struct Align {
             data: [i32; 4], // 32 bytes
@@ -53577,13 +53615,13 @@ mod tests {
         };
         let p = a.data.as_ptr();
         let m = 0b1010;
-        let r = _mm_mask_load_epi32(src, m, black_box(p));
+        let r = unsafe { _mm_mask_load_epi32(src, m, black_box(p)) };
         let e = _mm_setr_epi32(42, 2, 42, 4);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_load_epi32() {
+    const fn test_mm_maskz_load_epi32() {
         #[repr(align(16))]
         struct Align {
             data: [i32; 4], // 16 bytes
@@ -53593,23 +53631,25 @@ mod tests {
         };
         let p = a.data.as_ptr();
         let m = 0b1010;
-        let r = _mm_maskz_load_epi32(m, black_box(p));
+        let r = unsafe { _mm_maskz_load_epi32(m, black_box(p)) };
         let e = _mm_setr_epi32(0, 2, 0, 4);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_storeu_epi32() {
+    const fn test_mm_mask_storeu_epi32() {
         let mut r = [42_i32; 4];
         let a = _mm_setr_epi32(1, 2, 3, 4);
         let m = 0b1010;
-        _mm_mask_storeu_epi32(r.as_mut_ptr(), m, a);
+        unsafe {
+            _mm_mask_storeu_epi32(r.as_mut_ptr(), m, a);
+        }
         let e = _mm_setr_epi32(42, 2, 42, 4);
-        assert_eq_m128i(_mm_loadu_epi32(r.as_ptr()), e);
+        assert_eq_m128i(unsafe { _mm_loadu_epi32(r.as_ptr()) }, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_store_epi32() {
+    const fn test_mm_mask_store_epi32() {
         #[repr(align(16))]
         struct Align {
             data: [i32; 4], // 16 bytes
@@ -53617,34 +53657,36 @@ mod tests {
         let mut r = Align { data: [42; 4] };
         let a = _mm_setr_epi32(1, 2, 3, 4);
         let m = 0b1010;
-        _mm_mask_store_epi32(r.data.as_mut_ptr(), m, a);
+        unsafe {
+            _mm_mask_store_epi32(r.data.as_mut_ptr(), m, a);
+        }
         let e = _mm_setr_epi32(42, 2, 42, 4);
-        assert_eq_m128i(_mm_load_epi32(r.data.as_ptr()), e);
+        assert_eq_m128i(unsafe { _mm_load_epi32(r.data.as_ptr()) }, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_loadu_epi64() {
+    const fn test_mm_mask_loadu_epi64() {
         let src = _mm_set1_epi64x(42);
         let a = &[1_i64, 2];
         let p = a.as_ptr();
         let m = 0b10;
-        let r = _mm_mask_loadu_epi64(src, m, black_box(p));
+        let r = unsafe { _mm_mask_loadu_epi64(src, m, black_box(p)) };
         let e = _mm_setr_epi64x(42, 2);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_loadu_epi64() {
+    const fn test_mm_maskz_loadu_epi64() {
         let a = &[1_i64, 2];
         let p = a.as_ptr();
         let m = 0b10;
-        let r = _mm_maskz_loadu_epi64(m, black_box(p));
+        let r = unsafe { _mm_maskz_loadu_epi64(m, black_box(p)) };
         let e = _mm_setr_epi64x(0, 2);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_load_epi64() {
+    const fn test_mm_mask_load_epi64() {
         #[repr(align(16))]
         struct Align {
             data: [i64; 2], // 16 bytes
@@ -53653,13 +53695,13 @@ mod tests {
         let a = Align { data: [1_i64, 2] };
         let p = a.data.as_ptr();
         let m = 0b10;
-        let r = _mm_mask_load_epi64(src, m, black_box(p));
+        let r = unsafe { _mm_mask_load_epi64(src, m, black_box(p)) };
         let e = _mm_setr_epi64x(42, 2);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_load_epi64() {
+    const fn test_mm_maskz_load_epi64() {
         #[repr(align(16))]
         struct Align {
             data: [i64; 2], // 16 bytes
@@ -53667,23 +53709,25 @@ mod tests {
         let a = Align { data: [1_i64, 2] };
         let p = a.data.as_ptr();
         let m = 0b10;
-        let r = _mm_maskz_load_epi64(m, black_box(p));
+        let r = unsafe { _mm_maskz_load_epi64(m, black_box(p)) };
         let e = _mm_setr_epi64x(0, 2);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_storeu_epi64() {
+    const fn test_mm_mask_storeu_epi64() {
         let mut r = [42_i64; 2];
         let a = _mm_setr_epi64x(1, 2);
         let m = 0b10;
-        _mm_mask_storeu_epi64(r.as_mut_ptr(), m, a);
+        unsafe {
+            _mm_mask_storeu_epi64(r.as_mut_ptr(), m, a);
+        }
         let e = _mm_setr_epi64x(42, 2);
-        assert_eq_m128i(_mm_loadu_epi64(r.as_ptr()), e);
+        assert_eq_m128i(unsafe { _mm_loadu_epi64(r.as_ptr()) }, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_store_epi64() {
+    const fn test_mm_mask_store_epi64() {
         #[repr(align(16))]
         struct Align {
             data: [i64; 2], // 16 bytes
@@ -53691,34 +53735,36 @@ mod tests {
         let mut r = Align { data: [42; 2] };
         let a = _mm_setr_epi64x(1, 2);
         let m = 0b10;
-        _mm_mask_store_epi64(r.data.as_mut_ptr(), m, a);
+        unsafe {
+            _mm_mask_store_epi64(r.data.as_mut_ptr(), m, a);
+        }
         let e = _mm_setr_epi64x(42, 2);
-        assert_eq_m128i(_mm_load_epi64(r.data.as_ptr()), e);
+        assert_eq_m128i(unsafe { _mm_load_epi64(r.data.as_ptr()) }, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_loadu_ps() {
+    const fn test_mm_mask_loadu_ps() {
         let src = _mm_set1_ps(42.0);
         let a = &[1.0_f32, 2.0, 3.0, 4.0];
         let p = a.as_ptr();
         let m = 0b1010;
-        let r = _mm_mask_loadu_ps(src, m, black_box(p));
+        let r = unsafe { _mm_mask_loadu_ps(src, m, black_box(p)) };
         let e = _mm_setr_ps(42.0, 2.0, 42.0, 4.0);
         assert_eq_m128(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_loadu_ps() {
+    const fn test_mm_maskz_loadu_ps() {
         let a = &[1.0_f32, 2.0, 3.0, 4.0];
         let p = a.as_ptr();
         let m = 0b1010;
-        let r = _mm_maskz_loadu_ps(m, black_box(p));
+        let r = unsafe { _mm_maskz_loadu_ps(m, black_box(p)) };
         let e = _mm_setr_ps(0.0, 2.0, 0.0, 4.0);
         assert_eq_m128(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_load_ps() {
+    const fn test_mm_mask_load_ps() {
         #[repr(align(16))]
         struct Align {
             data: [f32; 4], // 16 bytes
@@ -53729,13 +53775,13 @@ mod tests {
         };
         let p = a.data.as_ptr();
         let m = 0b1010;
-        let r = _mm_mask_load_ps(src, m, black_box(p));
+        let r = unsafe { _mm_mask_load_ps(src, m, black_box(p)) };
         let e = _mm_setr_ps(42.0, 2.0, 42.0, 4.0);
         assert_eq_m128(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_load_ps() {
+    const fn test_mm_maskz_load_ps() {
         #[repr(align(16))]
         struct Align {
             data: [f32; 4], // 16 bytes
@@ -53745,23 +53791,25 @@ mod tests {
         };
         let p = a.data.as_ptr();
         let m = 0b1010;
-        let r = _mm_maskz_load_ps(m, black_box(p));
+        let r = unsafe { _mm_maskz_load_ps(m, black_box(p)) };
         let e = _mm_setr_ps(0.0, 2.0, 0.0, 4.0);
         assert_eq_m128(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_storeu_ps() {
+    const fn test_mm_mask_storeu_ps() {
         let mut r = [42_f32; 4];
         let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
         let m = 0b1010;
-        _mm_mask_storeu_ps(r.as_mut_ptr(), m, a);
+        unsafe {
+            _mm_mask_storeu_ps(r.as_mut_ptr(), m, a);
+        }
         let e = _mm_setr_ps(42.0, 2.0, 42.0, 4.0);
-        assert_eq_m128(_mm_loadu_ps(r.as_ptr()), e);
+        assert_eq_m128(unsafe { _mm_loadu_ps(r.as_ptr()) }, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_store_ps() {
+    const fn test_mm_mask_store_ps() {
         #[repr(align(16))]
         struct Align {
             data: [f32; 4], // 16 bytes
@@ -53769,34 +53817,36 @@ mod tests {
         let mut r = Align { data: [42.0; 4] };
         let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
         let m = 0b1010;
-        _mm_mask_store_ps(r.data.as_mut_ptr(), m, a);
+        unsafe {
+            _mm_mask_store_ps(r.data.as_mut_ptr(), m, a);
+        }
         let e = _mm_setr_ps(42.0, 2.0, 42.0, 4.0);
-        assert_eq_m128(_mm_load_ps(r.data.as_ptr()), e);
+        assert_eq_m128(unsafe { _mm_load_ps(r.data.as_ptr()) }, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_loadu_pd() {
+    const fn test_mm_mask_loadu_pd() {
         let src = _mm_set1_pd(42.0);
         let a = &[1.0_f64, 2.0];
         let p = a.as_ptr();
         let m = 0b10;
-        let r = _mm_mask_loadu_pd(src, m, black_box(p));
+        let r = unsafe { _mm_mask_loadu_pd(src, m, black_box(p)) };
         let e = _mm_setr_pd(42.0, 2.0);
         assert_eq_m128d(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_loadu_pd() {
+    const fn test_mm_maskz_loadu_pd() {
         let a = &[1.0_f64, 2.0];
         let p = a.as_ptr();
         let m = 0b10;
-        let r = _mm_maskz_loadu_pd(m, black_box(p));
+        let r = unsafe { _mm_maskz_loadu_pd(m, black_box(p)) };
         let e = _mm_setr_pd(0.0, 2.0);
         assert_eq_m128d(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_load_pd() {
+    const fn test_mm_mask_load_pd() {
         #[repr(align(16))]
         struct Align {
             data: [f64; 2], // 16 bytes
@@ -53807,13 +53857,13 @@ mod tests {
         };
         let p = a.data.as_ptr();
         let m = 0b10;
-        let r = _mm_mask_load_pd(src, m, black_box(p));
+        let r = unsafe { _mm_mask_load_pd(src, m, black_box(p)) };
         let e = _mm_setr_pd(42.0, 2.0);
         assert_eq_m128d(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_maskz_load_pd() {
+    const fn test_mm_maskz_load_pd() {
         #[repr(align(16))]
         struct Align {
             data: [f64; 2], // 16 bytes
@@ -53823,77 +53873,79 @@ mod tests {
         };
         let p = a.data.as_ptr();
         let m = 0b10;
-        let r = _mm_maskz_load_pd(m, black_box(p));
+        let r = unsafe { _mm_maskz_load_pd(m, black_box(p)) };
         let e = _mm_setr_pd(0.0, 2.0);
         assert_eq_m128d(r, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_mask_load_ss() {
+    fn test_mm_mask_load_ss() {
         #[repr(align(16))]
         struct Align {
             data: f32,
         }
         let src = _mm_set_ss(2.0);
         let mem = Align { data: 1.0 };
-        let r = _mm_mask_load_ss(src, 0b1, &mem.data);
+        let r = unsafe { _mm_mask_load_ss(src, 0b1, &mem.data) };
         assert_eq_m128(r, _mm_set_ss(1.0));
-        let r = _mm_mask_load_ss(src, 0b0, &mem.data);
+        let r = unsafe { _mm_mask_load_ss(src, 0b0, &mem.data) };
         assert_eq_m128(r, _mm_set_ss(2.0));
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_maskz_load_ss() {
+    fn test_mm_maskz_load_ss() {
         #[repr(align(16))]
         struct Align {
             data: f32,
         }
         let mem = Align { data: 1.0 };
-        let r = _mm_maskz_load_ss(0b1, &mem.data);
+        let r = unsafe { _mm_maskz_load_ss(0b1, &mem.data) };
         assert_eq_m128(r, _mm_set_ss(1.0));
-        let r = _mm_maskz_load_ss(0b0, &mem.data);
+        let r = unsafe { _mm_maskz_load_ss(0b0, &mem.data) };
         assert_eq_m128(r, _mm_set_ss(0.0));
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_mask_load_sd() {
+    fn test_mm_mask_load_sd() {
         #[repr(align(16))]
         struct Align {
             data: f64,
         }
         let src = _mm_set_sd(2.0);
         let mem = Align { data: 1.0 };
-        let r = _mm_mask_load_sd(src, 0b1, &mem.data);
+        let r = unsafe { _mm_mask_load_sd(src, 0b1, &mem.data) };
         assert_eq_m128d(r, _mm_set_sd(1.0));
-        let r = _mm_mask_load_sd(src, 0b0, &mem.data);
+        let r = unsafe { _mm_mask_load_sd(src, 0b0, &mem.data) };
         assert_eq_m128d(r, _mm_set_sd(2.0));
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_maskz_load_sd() {
+    fn test_mm_maskz_load_sd() {
         #[repr(align(16))]
         struct Align {
             data: f64,
         }
         let mem = Align { data: 1.0 };
-        let r = _mm_maskz_load_sd(0b1, &mem.data);
+        let r = unsafe { _mm_maskz_load_sd(0b1, &mem.data) };
         assert_eq_m128d(r, _mm_set_sd(1.0));
-        let r = _mm_maskz_load_sd(0b0, &mem.data);
+        let r = unsafe { _mm_maskz_load_sd(0b0, &mem.data) };
         assert_eq_m128d(r, _mm_set_sd(0.0));
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_storeu_pd() {
+    const fn test_mm_mask_storeu_pd() {
         let mut r = [42_f64; 2];
         let a = _mm_setr_pd(1.0, 2.0);
         let m = 0b10;
-        _mm_mask_storeu_pd(r.as_mut_ptr(), m, a);
+        unsafe {
+            _mm_mask_storeu_pd(r.as_mut_ptr(), m, a);
+        }
         let e = _mm_setr_pd(42.0, 2.0);
-        assert_eq_m128d(_mm_loadu_pd(r.as_ptr()), e);
+        assert_eq_m128d(unsafe { _mm_loadu_pd(r.as_ptr()) }, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_mask_store_pd() {
+    const fn test_mm_mask_store_pd() {
         #[repr(align(16))]
         struct Align {
             data: [f64; 2], // 16 bytes
@@ -53901,36 +53953,46 @@ mod tests {
         let mut r = Align { data: [42.0; 2] };
         let a = _mm_setr_pd(1.0, 2.0);
         let m = 0b10;
-        _mm_mask_store_pd(r.data.as_mut_ptr(), m, a);
+        unsafe {
+            _mm_mask_store_pd(r.data.as_mut_ptr(), m, a);
+        }
         let e = _mm_setr_pd(42.0, 2.0);
-        assert_eq_m128d(_mm_load_pd(r.data.as_ptr()), e);
+        assert_eq_m128d(unsafe { _mm_load_pd(r.data.as_ptr()) }, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_mask_store_ss() {
+    fn test_mm_mask_store_ss() {
         #[repr(align(16))]
         struct Align {
             data: f32,
         }
         let a = _mm_set_ss(2.0);
         let mut mem = Align { data: 1.0 };
-        _mm_mask_store_ss(&mut mem.data, 0b1, a);
+        unsafe {
+            _mm_mask_store_ss(&mut mem.data, 0b1, a);
+        }
         assert_eq!(mem.data, 2.0);
-        _mm_mask_store_ss(&mut mem.data, 0b0, a);
+        unsafe {
+            _mm_mask_store_ss(&mut mem.data, 0b0, a);
+        }
         assert_eq!(mem.data, 2.0);
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm_mask_store_sd() {
+    fn test_mm_mask_store_sd() {
         #[repr(align(16))]
         struct Align {
             data: f64,
         }
         let a = _mm_set_sd(2.0);
         let mut mem = Align { data: 1.0 };
-        _mm_mask_store_sd(&mut mem.data, 0b1, a);
+        unsafe {
+            _mm_mask_store_sd(&mut mem.data, 0b1, a);
+        }
         assert_eq!(mem.data, 2.0);
-        _mm_mask_store_sd(&mut mem.data, 0b0, a);
+        unsafe {
+            _mm_mask_store_sd(&mut mem.data, 0b0, a);
+        }
         assert_eq!(mem.data, 2.0);
     }
 
@@ -57931,11 +57993,11 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_kortest_mask16_u8() {
+    const fn test_kortest_mask16_u8() {
         let a: __mmask16 = 0b0110100101101001;
         let b: __mmask16 = 0b1011011010110110;
         let mut all_ones: u8 = 0;
-        let r = _kortest_mask16_u8(a, b, &mut all_ones);
+        let r = unsafe { _kortest_mask16_u8(a, b, &mut all_ones) };
         assert_eq!(r, 0);
         assert_eq!(all_ones, 1);
     }
@@ -57997,18 +58059,20 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_load_mask16() {
+    const fn test_load_mask16() {
         let a: __mmask16 = 0b1001011011000011;
-        let r = _load_mask16(&a);
+        let r = unsafe { _load_mask16(&a) };
         let e: __mmask16 = 0b1001011011000011;
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_store_mask16() {
+    const fn test_store_mask16() {
         let a: __mmask16 = 0b0110100100111100;
         let mut r = 0;
-        _store_mask16(&mut r, a);
+        unsafe {
+            _store_mask16(&mut r, a);
+        }
         let e: __mmask16 = 0b0110100100111100;
         assert_eq!(r, e);
     }
@@ -58189,7 +58253,7 @@ mod tests {
 
     #[simd_test(enable = "avx512f")]
     #[cfg_attr(miri, ignore)]
-    unsafe fn test_mm512_stream_ps() {
+    fn test_mm512_stream_ps() {
         #[repr(align(64))]
         struct Memory {
             pub data: [f32; 16], // 64 bytes
@@ -58197,7 +58261,9 @@ mod tests {
         let a = _mm512_set1_ps(7.0);
         let mut mem = Memory { data: [-1.0; 16] };
 
-        _mm512_stream_ps(&mut mem.data[0] as *mut f32, a);
+        unsafe {
+            _mm512_stream_ps(&mut mem.data[0] as *mut f32, a);
+        }
         _mm_sfence();
         for i in 0..16 {
             assert_eq!(mem.data[i], get_m512(a, i));
@@ -58206,7 +58272,7 @@ mod tests {
 
     #[simd_test(enable = "avx512f")]
     #[cfg_attr(miri, ignore)]
-    unsafe fn test_mm512_stream_pd() {
+    fn test_mm512_stream_pd() {
         #[repr(align(64))]
         struct Memory {
             pub data: [f64; 8],
@@ -58214,7 +58280,9 @@ mod tests {
         let a = _mm512_set1_pd(7.0);
         let mut mem = Memory { data: [-1.0; 8] };
 
-        _mm512_stream_pd(&mut mem.data[0] as *mut f64, a);
+        unsafe {
+            _mm512_stream_pd(&mut mem.data[0] as *mut f64, a);
+        }
         _mm_sfence();
         for i in 0..8 {
             assert_eq!(mem.data[i], get_m512d(a, i));
@@ -58223,7 +58291,7 @@ mod tests {
 
     #[simd_test(enable = "avx512f")]
     #[cfg_attr(miri, ignore)]
-    unsafe fn test_mm512_stream_si512() {
+    fn test_mm512_stream_si512() {
         #[repr(align(64))]
         struct Memory {
             pub data: [i64; 8],
@@ -58231,7 +58299,9 @@ mod tests {
         let a = _mm512_set1_epi32(7);
         let mut mem = Memory { data: [-1; 8] };
 
-        _mm512_stream_si512(mem.data.as_mut_ptr().cast(), a);
+        unsafe {
+            _mm512_stream_si512(mem.data.as_mut_ptr().cast(), a);
+        }
         _mm_sfence();
         for i in 0..8 {
             assert_eq!(mem.data[i], get_m512i(a, i));
@@ -58239,9 +58309,9 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_stream_load_si512() {
+    fn test_mm512_stream_load_si512() {
         let a = _mm512_set_epi64(1, 2, 3, 4, 5, 6, 7, 8);
-        let r = _mm512_stream_load_si512(core::ptr::addr_of!(a) as *const _);
+        let r = unsafe { _mm512_stream_load_si512(core::ptr::addr_of!(a) as *const _) };
         assert_eq_m512i(a, r);
     }
 
@@ -58558,75 +58628,103 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_compressstoreu_epi32() {
+    fn test_mm512_mask_compressstoreu_epi32() {
         let a = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
         let mut r = [0_i32; 16];
-        _mm512_mask_compressstoreu_epi32(r.as_mut_ptr(), 0, a);
+        unsafe {
+            _mm512_mask_compressstoreu_epi32(r.as_mut_ptr(), 0, a);
+        }
         assert_eq!(&r, &[0_i32; 16]);
-        _mm512_mask_compressstoreu_epi32(r.as_mut_ptr(), 0b1111000011001010, a);
+        unsafe {
+            _mm512_mask_compressstoreu_epi32(r.as_mut_ptr(), 0b1111000011001010, a);
+        }
         assert_eq!(&r, &[2, 4, 7, 8, 13, 14, 15, 16, 0, 0, 0, 0, 0, 0, 0, 0]);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_compressstoreu_epi32() {
+    fn test_mm256_mask_compressstoreu_epi32() {
         let a = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8);
         let mut r = [0_i32; 8];
-        _mm256_mask_compressstoreu_epi32(r.as_mut_ptr(), 0, a);
+        unsafe {
+            _mm256_mask_compressstoreu_epi32(r.as_mut_ptr(), 0, a);
+        }
         assert_eq!(&r, &[0_i32; 8]);
-        _mm256_mask_compressstoreu_epi32(r.as_mut_ptr(), 0b11001010, a);
+        unsafe {
+            _mm256_mask_compressstoreu_epi32(r.as_mut_ptr(), 0b11001010, a);
+        }
         assert_eq!(&r, &[2, 4, 7, 8, 0, 0, 0, 0]);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_compressstoreu_epi32() {
+    fn test_mm_mask_compressstoreu_epi32() {
         let a = _mm_setr_epi32(1, 2, 3, 4);
         let mut r = [0_i32; 4];
-        _mm_mask_compressstoreu_epi32(r.as_mut_ptr(), 0, a);
+        unsafe {
+            _mm_mask_compressstoreu_epi32(r.as_mut_ptr(), 0, a);
+        }
         assert_eq!(&r, &[0_i32; 4]);
-        _mm_mask_compressstoreu_epi32(r.as_mut_ptr(), 0b1011, a);
+        unsafe {
+            _mm_mask_compressstoreu_epi32(r.as_mut_ptr(), 0b1011, a);
+        }
         assert_eq!(&r, &[1, 2, 4, 0]);
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_compressstoreu_epi64() {
+    fn test_mm512_mask_compressstoreu_epi64() {
         let a = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
         let mut r = [0_i64; 8];
-        _mm512_mask_compressstoreu_epi64(r.as_mut_ptr(), 0, a);
+        unsafe {
+            _mm512_mask_compressstoreu_epi64(r.as_mut_ptr(), 0, a);
+        }
         assert_eq!(&r, &[0_i64; 8]);
-        _mm512_mask_compressstoreu_epi64(r.as_mut_ptr(), 0b11001010, a);
+        unsafe {
+            _mm512_mask_compressstoreu_epi64(r.as_mut_ptr(), 0b11001010, a);
+        }
         assert_eq!(&r, &[2, 4, 7, 8, 0, 0, 0, 0]);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_compressstoreu_epi64() {
+    fn test_mm256_mask_compressstoreu_epi64() {
         let a = _mm256_setr_epi64x(1, 2, 3, 4);
         let mut r = [0_i64; 4];
-        _mm256_mask_compressstoreu_epi64(r.as_mut_ptr(), 0, a);
+        unsafe {
+            _mm256_mask_compressstoreu_epi64(r.as_mut_ptr(), 0, a);
+        }
         assert_eq!(&r, &[0_i64; 4]);
-        _mm256_mask_compressstoreu_epi64(r.as_mut_ptr(), 0b1011, a);
+        unsafe {
+            _mm256_mask_compressstoreu_epi64(r.as_mut_ptr(), 0b1011, a);
+        }
         assert_eq!(&r, &[1, 2, 4, 0]);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_compressstoreu_epi64() {
+    fn test_mm_mask_compressstoreu_epi64() {
         let a = _mm_setr_epi64x(1, 2);
         let mut r = [0_i64; 2];
-        _mm_mask_compressstoreu_epi64(r.as_mut_ptr(), 0, a);
+        unsafe {
+            _mm_mask_compressstoreu_epi64(r.as_mut_ptr(), 0, a);
+        }
         assert_eq!(&r, &[0_i64; 2]);
-        _mm_mask_compressstoreu_epi64(r.as_mut_ptr(), 0b10, a);
+        unsafe {
+            _mm_mask_compressstoreu_epi64(r.as_mut_ptr(), 0b10, a);
+        }
         assert_eq!(&r, &[2, 0]);
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_compressstoreu_ps() {
+    fn test_mm512_mask_compressstoreu_ps() {
         let a = _mm512_setr_ps(
             1_f32, 2_f32, 3_f32, 4_f32, 5_f32, 6_f32, 7_f32, 8_f32, 9_f32, 10_f32, 11_f32, 12_f32,
             13_f32, 14_f32, 15_f32, 16_f32,
         );
         let mut r = [0_f32; 16];
-        _mm512_mask_compressstoreu_ps(r.as_mut_ptr(), 0, a);
+        unsafe {
+            _mm512_mask_compressstoreu_ps(r.as_mut_ptr(), 0, a);
+        }
         assert_eq!(&r, &[0_f32; 16]);
-        _mm512_mask_compressstoreu_ps(r.as_mut_ptr(), 0b1111000011001010, a);
+        unsafe {
+            _mm512_mask_compressstoreu_ps(r.as_mut_ptr(), 0b1111000011001010, a);
+        }
         assert_eq!(
             &r,
             &[
@@ -58637,12 +58735,16 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_compressstoreu_ps() {
+    fn test_mm256_mask_compressstoreu_ps() {
         let a = _mm256_setr_ps(1_f32, 2_f32, 3_f32, 4_f32, 5_f32, 6_f32, 7_f32, 8_f32);
         let mut r = [0_f32; 8];
-        _mm256_mask_compressstoreu_ps(r.as_mut_ptr(), 0, a);
+        unsafe {
+            _mm256_mask_compressstoreu_ps(r.as_mut_ptr(), 0, a);
+        }
         assert_eq!(&r, &[0_f32; 8]);
-        _mm256_mask_compressstoreu_ps(r.as_mut_ptr(), 0b11001010, a);
+        unsafe {
+            _mm256_mask_compressstoreu_ps(r.as_mut_ptr(), 0b11001010, a);
+        }
         assert_eq!(
             &r,
             &[2_f32, 4_f32, 7_f32, 8_f32, 0_f32, 0_f32, 0_f32, 0_f32]
@@ -58650,47 +58752,63 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_compressstoreu_ps() {
+    fn test_mm_mask_compressstoreu_ps() {
         let a = _mm_setr_ps(1_f32, 2_f32, 3_f32, 4_f32);
         let mut r = [0.; 4];
-        _mm_mask_compressstoreu_ps(r.as_mut_ptr(), 0, a);
+        unsafe {
+            _mm_mask_compressstoreu_ps(r.as_mut_ptr(), 0, a);
+        }
         assert_eq!(&r, &[0.; 4]);
-        _mm_mask_compressstoreu_ps(r.as_mut_ptr(), 0b1011, a);
+        unsafe {
+            _mm_mask_compressstoreu_ps(r.as_mut_ptr(), 0b1011, a);
+        }
         assert_eq!(&r, &[1_f32, 2_f32, 4_f32, 0_f32]);
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_compressstoreu_pd() {
+    fn test_mm512_mask_compressstoreu_pd() {
         let a = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
         let mut r = [0.; 8];
-        _mm512_mask_compressstoreu_pd(r.as_mut_ptr(), 0, a);
+        unsafe {
+            _mm512_mask_compressstoreu_pd(r.as_mut_ptr(), 0, a);
+        }
         assert_eq!(&r, &[0.; 8]);
-        _mm512_mask_compressstoreu_pd(r.as_mut_ptr(), 0b11001010, a);
+        unsafe {
+            _mm512_mask_compressstoreu_pd(r.as_mut_ptr(), 0b11001010, a);
+        }
         assert_eq!(&r, &[2., 4., 7., 8., 0., 0., 0., 0.]);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_compressstoreu_pd() {
+    fn test_mm256_mask_compressstoreu_pd() {
         let a = _mm256_setr_pd(1., 2., 3., 4.);
         let mut r = [0.; 4];
-        _mm256_mask_compressstoreu_pd(r.as_mut_ptr(), 0, a);
+        unsafe {
+            _mm256_mask_compressstoreu_pd(r.as_mut_ptr(), 0, a);
+        }
         assert_eq!(&r, &[0.; 4]);
-        _mm256_mask_compressstoreu_pd(r.as_mut_ptr(), 0b1011, a);
+        unsafe {
+            _mm256_mask_compressstoreu_pd(r.as_mut_ptr(), 0b1011, a);
+        }
         assert_eq!(&r, &[1., 2., 4., 0.]);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_compressstoreu_pd() {
+    fn test_mm_mask_compressstoreu_pd() {
         let a = _mm_setr_pd(1., 2.);
         let mut r = [0.; 2];
-        _mm_mask_compressstoreu_pd(r.as_mut_ptr(), 0, a);
+        unsafe {
+            _mm_mask_compressstoreu_pd(r.as_mut_ptr(), 0, a);
+        }
         assert_eq!(&r, &[0.; 2]);
-        _mm_mask_compressstoreu_pd(r.as_mut_ptr(), 0b10, a);
+        unsafe {
+            _mm_mask_compressstoreu_pd(r.as_mut_ptr(), 0b10, a);
+        }
         assert_eq!(&r, &[2., 0.]);
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_expand_epi32() {
+    fn test_mm512_mask_expand_epi32() {
         let src = _mm512_set1_epi32(200);
         let a = _mm512_set_epi32(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
         let r = _mm512_mask_expand_epi32(src, 0, a);
@@ -58826,109 +58944,135 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_loadu_epi32() {
+    const fn test_mm512_loadu_epi32() {
         let a = &[4, 3, 2, 5, 8, 9, 64, 50, -4, -3, -2, -5, -8, -9, -64, -50];
         let p = a.as_ptr();
-        let r = _mm512_loadu_epi32(black_box(p));
+        let r = unsafe { _mm512_loadu_epi32(black_box(p)) };
         let e = _mm512_setr_epi32(4, 3, 2, 5, 8, 9, 64, 50, -4, -3, -2, -5, -8, -9, -64, -50);
         assert_eq_m512i(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_loadu_epi32() {
+    const fn test_mm256_loadu_epi32() {
         let a = &[4, 3, 2, 5, 8, 9, 64, 50];
         let p = a.as_ptr();
-        let r = _mm256_loadu_epi32(black_box(p));
+        let r = unsafe { _mm256_loadu_epi32(black_box(p)) };
         let e = _mm256_setr_epi32(4, 3, 2, 5, 8, 9, 64, 50);
         assert_eq_m256i(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_loadu_epi32() {
+    const fn test_mm_loadu_epi32() {
         let a = &[4, 3, 2, 5];
         let p = a.as_ptr();
-        let r = _mm_loadu_epi32(black_box(p));
+        let r = unsafe { _mm_loadu_epi32(black_box(p)) };
         let e = _mm_setr_epi32(4, 3, 2, 5);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cvtepi32_storeu_epi16() {
+    fn test_mm512_mask_cvtepi32_storeu_epi16() {
         let a = _mm512_set1_epi32(9);
         let mut r = _mm256_undefined_si256();
-        _mm512_mask_cvtepi32_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111_11111111, a);
+        unsafe {
+            _mm512_mask_cvtepi32_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111_11111111, a);
+        }
         let e = _mm256_set1_epi16(9);
         assert_eq_m256i(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_cvtepi32_storeu_epi16() {
+    fn test_mm256_mask_cvtepi32_storeu_epi16() {
         let a = _mm256_set1_epi32(9);
         let mut r = _mm_undefined_si128();
-        _mm256_mask_cvtepi32_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a);
+        unsafe {
+            _mm256_mask_cvtepi32_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a);
+        }
         let e = _mm_set1_epi16(9);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_cvtepi32_storeu_epi16() {
+    fn test_mm_mask_cvtepi32_storeu_epi16() {
         let a = _mm_set1_epi32(9);
         let mut r = _mm_set1_epi8(0);
-        _mm_mask_cvtepi32_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a);
+        unsafe {
+            _mm_mask_cvtepi32_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a);
+        }
         let e = _mm_set_epi16(0, 0, 0, 0, 9, 9, 9, 9);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cvtsepi32_storeu_epi16() {
+    fn test_mm512_mask_cvtsepi32_storeu_epi16() {
         let a = _mm512_set1_epi32(i32::MAX);
         let mut r = _mm256_undefined_si256();
-        _mm512_mask_cvtsepi32_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111_11111111, a);
+        unsafe {
+            _mm512_mask_cvtsepi32_storeu_epi16(
+                &mut r as *mut _ as *mut i16,
+                0b11111111_11111111,
+                a,
+            );
+        }
         let e = _mm256_set1_epi16(i16::MAX);
         assert_eq_m256i(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_cvtsepi32_storeu_epi16() {
+    fn test_mm256_mask_cvtsepi32_storeu_epi16() {
         let a = _mm256_set1_epi32(i32::MAX);
         let mut r = _mm_undefined_si128();
-        _mm256_mask_cvtsepi32_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a);
+        unsafe {
+            _mm256_mask_cvtsepi32_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a);
+        }
         let e = _mm_set1_epi16(i16::MAX);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_cvtsepi32_storeu_epi16() {
+    fn test_mm_mask_cvtsepi32_storeu_epi16() {
         let a = _mm_set1_epi32(i32::MAX);
         let mut r = _mm_set1_epi8(0);
-        _mm_mask_cvtsepi32_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a);
+        unsafe {
+            _mm_mask_cvtsepi32_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a);
+        }
         let e = _mm_set_epi16(0, 0, 0, 0, i16::MAX, i16::MAX, i16::MAX, i16::MAX);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cvtusepi32_storeu_epi16() {
+    fn test_mm512_mask_cvtusepi32_storeu_epi16() {
         let a = _mm512_set1_epi32(i32::MAX);
         let mut r = _mm256_undefined_si256();
-        _mm512_mask_cvtusepi32_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111_11111111, a);
+        unsafe {
+            _mm512_mask_cvtusepi32_storeu_epi16(
+                &mut r as *mut _ as *mut i16,
+                0b11111111_11111111,
+                a,
+            );
+        }
         let e = _mm256_set1_epi16(u16::MAX as i16);
         assert_eq_m256i(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_cvtusepi32_storeu_epi16() {
+    fn test_mm256_mask_cvtusepi32_storeu_epi16() {
         let a = _mm256_set1_epi32(i32::MAX);
         let mut r = _mm_undefined_si128();
-        _mm256_mask_cvtusepi32_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a);
+        unsafe {
+            _mm256_mask_cvtusepi32_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a);
+        }
         let e = _mm_set1_epi16(u16::MAX as i16);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_cvtusepi32_storeu_epi16() {
+    fn test_mm_mask_cvtusepi32_storeu_epi16() {
         let a = _mm_set1_epi32(i32::MAX);
         let mut r = _mm_set1_epi8(0);
-        _mm_mask_cvtusepi32_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a);
+        unsafe {
+            _mm_mask_cvtusepi32_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a);
+        }
         let e = _mm_set_epi16(
             0,
             0,
@@ -58943,46 +59087,56 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cvtepi32_storeu_epi8() {
+    fn test_mm512_mask_cvtepi32_storeu_epi8() {
         let a = _mm512_set1_epi32(9);
         let mut r = _mm_undefined_si128();
-        _mm512_mask_cvtepi32_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111_11111111, a);
+        unsafe {
+            _mm512_mask_cvtepi32_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111_11111111, a);
+        }
         let e = _mm_set1_epi8(9);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_cvtepi32_storeu_epi8() {
+    fn test_mm256_mask_cvtepi32_storeu_epi8() {
         let a = _mm256_set1_epi32(9);
         let mut r = _mm_set1_epi8(0);
-        _mm256_mask_cvtepi32_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
+        unsafe {
+            _mm256_mask_cvtepi32_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
+        }
         let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 9, 9, 9, 9, 9, 9, 9, 9);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_cvtepi32_storeu_epi8() {
+    fn test_mm_mask_cvtepi32_storeu_epi8() {
         let a = _mm_set1_epi32(9);
         let mut r = _mm_set1_epi8(0);
-        _mm_mask_cvtepi32_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
+        unsafe {
+            _mm_mask_cvtepi32_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
+        }
         let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 9, 9, 9, 9);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cvtsepi32_storeu_epi8() {
+    fn test_mm512_mask_cvtsepi32_storeu_epi8() {
         let a = _mm512_set1_epi32(i32::MAX);
         let mut r = _mm_undefined_si128();
-        _mm512_mask_cvtsepi32_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111_11111111, a);
+        unsafe {
+            _mm512_mask_cvtsepi32_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111_11111111, a);
+        }
         let e = _mm_set1_epi8(i8::MAX);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_cvtsepi32_storeu_epi8() {
+    fn test_mm256_mask_cvtsepi32_storeu_epi8() {
         let a = _mm256_set1_epi32(i32::MAX);
         let mut r = _mm_set1_epi8(0);
-        _mm256_mask_cvtsepi32_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
+        unsafe {
+            _mm256_mask_cvtsepi32_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
+        }
         #[rustfmt::skip]
         let e = _mm_set_epi8(
             0, 0, 0, 0,
@@ -58994,10 +59148,12 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_cvtsepi32_storeu_epi8() {
+    fn test_mm_mask_cvtsepi32_storeu_epi8() {
         let a = _mm_set1_epi32(i32::MAX);
         let mut r = _mm_set1_epi8(0);
-        _mm_mask_cvtsepi32_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
+        unsafe {
+            _mm_mask_cvtsepi32_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
+        }
         #[rustfmt::skip]
         let e = _mm_set_epi8(
             0, 0, 0, 0,
@@ -59009,19 +59165,23 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cvtusepi32_storeu_epi8() {
+    fn test_mm512_mask_cvtusepi32_storeu_epi8() {
         let a = _mm512_set1_epi32(i32::MAX);
         let mut r = _mm_undefined_si128();
-        _mm512_mask_cvtusepi32_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111_11111111, a);
+        unsafe {
+            _mm512_mask_cvtusepi32_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111_11111111, a);
+        }
         let e = _mm_set1_epi8(u8::MAX as i8);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_cvtusepi32_storeu_epi8() {
+    fn test_mm256_mask_cvtusepi32_storeu_epi8() {
         let a = _mm256_set1_epi32(i32::MAX);
         let mut r = _mm_set1_epi8(0);
-        _mm256_mask_cvtusepi32_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
+        unsafe {
+            _mm256_mask_cvtusepi32_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
+        }
         #[rustfmt::skip]
         let e = _mm_set_epi8(
             0, 0, 0, 0,
@@ -59033,10 +59193,12 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_cvtusepi32_storeu_epi8() {
+    fn test_mm_mask_cvtusepi32_storeu_epi8() {
         let a = _mm_set1_epi32(i32::MAX);
         let mut r = _mm_set1_epi8(0);
-        _mm_mask_cvtusepi32_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
+        unsafe {
+            _mm_mask_cvtusepi32_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
+        }
         #[rustfmt::skip]
         let e = _mm_set_epi8(
             0, 0, 0, 0,
@@ -59048,48 +59210,56 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_storeu_epi32() {
+    const fn test_mm512_storeu_epi32() {
         let a = _mm512_set1_epi32(9);
         let mut r = _mm512_undefined_epi32();
-        _mm512_storeu_epi32(&mut r as *mut _ as *mut i32, a);
+        unsafe {
+            _mm512_storeu_epi32(&mut r as *mut _ as *mut i32, a);
+        }
         assert_eq_m512i(r, a);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_storeu_epi32() {
+    const fn test_mm256_storeu_epi32() {
         let a = _mm256_set1_epi32(9);
         let mut r = _mm256_undefined_si256();
-        _mm256_storeu_epi32(&mut r as *mut _ as *mut i32, a);
+        unsafe {
+            _mm256_storeu_epi32(&mut r as *mut _ as *mut i32, a);
+        }
         assert_eq_m256i(r, a);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_storeu_epi32() {
+    const fn test_mm_storeu_epi32() {
         let a = _mm_set1_epi32(9);
         let mut r = _mm_undefined_si128();
-        _mm_storeu_epi32(&mut r as *mut _ as *mut i32, a);
+        unsafe {
+            _mm_storeu_epi32(&mut r as *mut _ as *mut i32, a);
+        }
         assert_eq_m128i(r, a);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_loadu_si512() {
+    const fn test_mm512_loadu_si512() {
         let a = &[4, 3, 2, 5, 8, 9, 64, 50, -4, -3, -2, -5, -8, -9, -64, -50];
         let p = a.as_ptr().cast();
-        let r = _mm512_loadu_si512(black_box(p));
+        let r = unsafe { _mm512_loadu_si512(black_box(p)) };
         let e = _mm512_setr_epi32(4, 3, 2, 5, 8, 9, 64, 50, -4, -3, -2, -5, -8, -9, -64, -50);
         assert_eq_m512i(r, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_storeu_si512() {
+    const fn test_mm512_storeu_si512() {
         let a = _mm512_set1_epi32(9);
         let mut r = _mm512_undefined_epi32();
-        _mm512_storeu_si512(&mut r as *mut _, a);
+        unsafe {
+            _mm512_storeu_si512(&mut r as *mut _, a);
+        }
         assert_eq_m512i(r, a);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_load_si512() {
+    const fn test_mm512_load_si512() {
         #[repr(align(64))]
         struct Align {
             data: [i32; 16], // 64 bytes
@@ -59098,21 +59268,23 @@ mod tests {
             data: [4, 3, 2, 5, 8, 9, 64, 50, -4, -3, -2, -5, -8, -9, -64, -50],
         };
         let p = (a.data).as_ptr().cast();
-        let r = _mm512_load_si512(black_box(p));
+        let r = unsafe { _mm512_load_si512(black_box(p)) };
         let e = _mm512_setr_epi32(4, 3, 2, 5, 8, 9, 64, 50, -4, -3, -2, -5, -8, -9, -64, -50);
         assert_eq_m512i(r, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_store_si512() {
+    const fn test_mm512_store_si512() {
         let a = _mm512_set1_epi32(9);
         let mut r = _mm512_undefined_epi32();
-        _mm512_store_si512(&mut r as *mut _, a);
+        unsafe {
+            _mm512_store_si512(&mut r as *mut _, a);
+        }
         assert_eq_m512i(r, a);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_load_epi32() {
+    const fn test_mm512_load_epi32() {
         #[repr(align(64))]
         struct Align {
             data: [i32; 16], // 64 bytes
@@ -59121,13 +59293,13 @@ mod tests {
             data: [4, 3, 2, 5, 8, 9, 64, 50, -4, -3, -2, -5, -8, -9, -64, -50],
         };
         let p = (a.data).as_ptr();
-        let r = _mm512_load_epi32(black_box(p));
+        let r = unsafe { _mm512_load_epi32(black_box(p)) };
         let e = _mm512_setr_epi32(4, 3, 2, 5, 8, 9, 64, 50, -4, -3, -2, -5, -8, -9, -64, -50);
         assert_eq_m512i(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_load_epi32() {
+    const fn test_mm256_load_epi32() {
         #[repr(align(64))]
         struct Align {
             data: [i32; 8],
@@ -59136,50 +59308,56 @@ mod tests {
             data: [4, 3, 2, 5, 8, 9, 64, 50],
         };
         let p = (a.data).as_ptr();
-        let r = _mm256_load_epi32(black_box(p));
+        let r = unsafe { _mm256_load_epi32(black_box(p)) };
         let e = _mm256_setr_epi32(4, 3, 2, 5, 8, 9, 64, 50);
         assert_eq_m256i(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_load_epi32() {
+    const fn test_mm_load_epi32() {
         #[repr(align(64))]
         struct Align {
             data: [i32; 4],
         }
         let a = Align { data: [4, 3, 2, 5] };
         let p = (a.data).as_ptr();
-        let r = _mm_load_epi32(black_box(p));
+        let r = unsafe { _mm_load_epi32(black_box(p)) };
         let e = _mm_setr_epi32(4, 3, 2, 5);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_store_epi32() {
+    const fn test_mm512_store_epi32() {
         let a = _mm512_set1_epi32(9);
         let mut r = _mm512_undefined_epi32();
-        _mm512_store_epi32(&mut r as *mut _ as *mut i32, a);
+        unsafe {
+            _mm512_store_epi32(&mut r as *mut _ as *mut i32, a);
+        }
         assert_eq_m512i(r, a);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_store_epi32() {
+    const fn test_mm256_store_epi32() {
         let a = _mm256_set1_epi32(9);
         let mut r = _mm256_undefined_si256();
-        _mm256_store_epi32(&mut r as *mut _ as *mut i32, a);
+        unsafe {
+            _mm256_store_epi32(&mut r as *mut _ as *mut i32, a);
+        }
         assert_eq_m256i(r, a);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_store_epi32() {
+    const fn test_mm_store_epi32() {
         let a = _mm_set1_epi32(9);
         let mut r = _mm_undefined_si128();
-        _mm_store_epi32(&mut r as *mut _ as *mut i32, a);
+        unsafe {
+            _mm_store_epi32(&mut r as *mut _ as *mut i32, a);
+        }
         assert_eq_m128i(r, a);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_load_ps() {
+    const fn test_mm512_load_ps() {
         #[repr(align(64))]
         struct Align {
             data: [f32; 16], // 64 bytes
@@ -59190,7 +59368,7 @@ mod tests {
             ],
         };
         let p = (a.data).as_ptr();
-        let r = _mm512_load_ps(black_box(p));
+        let r = unsafe { _mm512_load_ps(black_box(p)) };
         let e = _mm512_setr_ps(
             4., 3., 2., 5., 8., 9., 64., 50., -4., -3., -2., -5., -8., -9., -64., -50.,
         );
@@ -59198,10 +59376,12 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_store_ps() {
+    const fn test_mm512_store_ps() {
         let a = _mm512_set1_ps(9.);
         let mut r = _mm512_undefined_ps();
-        _mm512_store_ps(&mut r as *mut _ as *mut f32, a);
+        unsafe {
+            _mm512_store_ps(&mut r as *mut _ as *mut f32, a);
+        }
         assert_eq_m512(r, a);
     }
 
@@ -62191,140 +62371,140 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_expandloadu_epi32() {
+    fn test_mm512_mask_expandloadu_epi32() {
         let src = _mm512_set1_epi32(42);
         let a = &[1_i32, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16];
         let p = a.as_ptr();
         let m = 0b11101000_11001010;
-        let r = _mm512_mask_expandloadu_epi32(src, m, black_box(p));
+        let r = unsafe { _mm512_mask_expandloadu_epi32(src, m, black_box(p)) };
         let e = _mm512_set_epi32(8, 7, 6, 42, 5, 42, 42, 42, 4, 3, 42, 42, 2, 42, 1, 42);
         assert_eq_m512i(r, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_expandloadu_epi32() {
+    fn test_mm512_maskz_expandloadu_epi32() {
         let a = &[1_i32, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16];
         let p = a.as_ptr();
         let m = 0b11101000_11001010;
-        let r = _mm512_maskz_expandloadu_epi32(m, black_box(p));
+        let r = unsafe { _mm512_maskz_expandloadu_epi32(m, black_box(p)) };
         let e = _mm512_set_epi32(8, 7, 6, 0, 5, 0, 0, 0, 4, 3, 0, 0, 2, 0, 1, 0);
         assert_eq_m512i(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_expandloadu_epi32() {
+    fn test_mm256_mask_expandloadu_epi32() {
         let src = _mm256_set1_epi32(42);
         let a = &[1_i32, 2, 3, 4, 5, 6, 7, 8];
         let p = a.as_ptr();
         let m = 0b11101000;
-        let r = _mm256_mask_expandloadu_epi32(src, m, black_box(p));
+        let r = unsafe { _mm256_mask_expandloadu_epi32(src, m, black_box(p)) };
         let e = _mm256_set_epi32(4, 3, 2, 42, 1, 42, 42, 42);
         assert_eq_m256i(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_expandloadu_epi32() {
+    fn test_mm256_maskz_expandloadu_epi32() {
         let a = &[1_i32, 2, 3, 4, 5, 6, 7, 8];
         let p = a.as_ptr();
         let m = 0b11101000;
-        let r = _mm256_maskz_expandloadu_epi32(m, black_box(p));
+        let r = unsafe { _mm256_maskz_expandloadu_epi32(m, black_box(p)) };
         let e = _mm256_set_epi32(4, 3, 2, 0, 1, 0, 0, 0);
         assert_eq_m256i(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_expandloadu_epi32() {
+    fn test_mm_mask_expandloadu_epi32() {
         let src = _mm_set1_epi32(42);
         let a = &[1_i32, 2, 3, 4];
         let p = a.as_ptr();
         let m = 0b11111000;
-        let r = _mm_mask_expandloadu_epi32(src, m, black_box(p));
+        let r = unsafe { _mm_mask_expandloadu_epi32(src, m, black_box(p)) };
         let e = _mm_set_epi32(1, 42, 42, 42);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_expandloadu_epi32() {
+    fn test_mm_maskz_expandloadu_epi32() {
         let a = &[1_i32, 2, 3, 4];
         let p = a.as_ptr();
         let m = 0b11111000;
-        let r = _mm_maskz_expandloadu_epi32(m, black_box(p));
+        let r = unsafe { _mm_maskz_expandloadu_epi32(m, black_box(p)) };
         let e = _mm_set_epi32(1, 0, 0, 0);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_expandloadu_epi64() {
+    fn test_mm512_mask_expandloadu_epi64() {
         let src = _mm512_set1_epi64(42);
         let a = &[1_i64, 2, 3, 4, 5, 6, 7, 8];
         let p = a.as_ptr();
         let m = 0b11101000;
-        let r = _mm512_mask_expandloadu_epi64(src, m, black_box(p));
+        let r = unsafe { _mm512_mask_expandloadu_epi64(src, m, black_box(p)) };
         let e = _mm512_set_epi64(4, 3, 2, 42, 1, 42, 42, 42);
         assert_eq_m512i(r, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_expandloadu_epi64() {
+    fn test_mm512_maskz_expandloadu_epi64() {
         let a = &[1_i64, 2, 3, 4, 5, 6, 7, 8];
         let p = a.as_ptr();
         let m = 0b11101000;
-        let r = _mm512_maskz_expandloadu_epi64(m, black_box(p));
+        let r = unsafe { _mm512_maskz_expandloadu_epi64(m, black_box(p)) };
         let e = _mm512_set_epi64(4, 3, 2, 0, 1, 0, 0, 0);
         assert_eq_m512i(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_expandloadu_epi64() {
+    fn test_mm256_mask_expandloadu_epi64() {
         let src = _mm256_set1_epi64x(42);
         let a = &[1_i64, 2, 3, 4];
         let p = a.as_ptr();
         let m = 0b11101000;
-        let r = _mm256_mask_expandloadu_epi64(src, m, black_box(p));
+        let r = unsafe { _mm256_mask_expandloadu_epi64(src, m, black_box(p)) };
         let e = _mm256_set_epi64x(1, 42, 42, 42);
         assert_eq_m256i(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_expandloadu_epi64() {
+    fn test_mm256_maskz_expandloadu_epi64() {
         let a = &[1_i64, 2, 3, 4];
         let p = a.as_ptr();
         let m = 0b11101000;
-        let r = _mm256_maskz_expandloadu_epi64(m, black_box(p));
+        let r = unsafe { _mm256_maskz_expandloadu_epi64(m, black_box(p)) };
         let e = _mm256_set_epi64x(1, 0, 0, 0);
         assert_eq_m256i(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_expandloadu_epi64() {
+    fn test_mm_mask_expandloadu_epi64() {
         let src = _mm_set1_epi64x(42);
         let a = &[1_i64, 2];
         let p = a.as_ptr();
         let m = 0b11101000;
-        let r = _mm_mask_expandloadu_epi64(src, m, black_box(p));
+        let r = unsafe { _mm_mask_expandloadu_epi64(src, m, black_box(p)) };
         let e = _mm_set_epi64x(42, 42);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_expandloadu_epi64() {
+    fn test_mm_maskz_expandloadu_epi64() {
         let a = &[1_i64, 2];
         let p = a.as_ptr();
         let m = 0b11101000;
-        let r = _mm_maskz_expandloadu_epi64(m, black_box(p));
+        let r = unsafe { _mm_maskz_expandloadu_epi64(m, black_box(p)) };
         let e = _mm_set_epi64x(0, 0);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_expandloadu_ps() {
+    fn test_mm512_mask_expandloadu_ps() {
         let src = _mm512_set1_ps(42.);
         let a = &[
             1.0f32, 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16.,
         ];
         let p = a.as_ptr();
         let m = 0b11101000_11001010;
-        let r = _mm512_mask_expandloadu_ps(src, m, black_box(p));
+        let r = unsafe { _mm512_mask_expandloadu_ps(src, m, black_box(p)) };
         let e = _mm512_set_ps(
             8., 7., 6., 42., 5., 42., 42., 42., 4., 3., 42., 42., 2., 42., 1., 42.,
         );
@@ -62332,13 +62512,13 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_expandloadu_ps() {
+    fn test_mm512_maskz_expandloadu_ps() {
         let a = &[
             1.0f32, 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16.,
         ];
         let p = a.as_ptr();
         let m = 0b11101000_11001010;
-        let r = _mm512_maskz_expandloadu_ps(m, black_box(p));
+        let r = unsafe { _mm512_maskz_expandloadu_ps(m, black_box(p)) };
         let e = _mm512_set_ps(
             8., 7., 6., 0., 5., 0., 0., 0., 4., 3., 0., 0., 2., 0., 1., 0.,
         );
@@ -62346,106 +62526,106 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_expandloadu_ps() {
+    fn test_mm256_mask_expandloadu_ps() {
         let src = _mm256_set1_ps(42.);
         let a = &[1.0f32, 2., 3., 4., 5., 6., 7., 8.];
         let p = a.as_ptr();
         let m = 0b11101000;
-        let r = _mm256_mask_expandloadu_ps(src, m, black_box(p));
+        let r = unsafe { _mm256_mask_expandloadu_ps(src, m, black_box(p)) };
         let e = _mm256_set_ps(4., 3., 2., 42., 1., 42., 42., 42.);
         assert_eq_m256(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_expandloadu_ps() {
+    fn test_mm256_maskz_expandloadu_ps() {
         let a = &[1.0f32, 2., 3., 4., 5., 6., 7., 8.];
         let p = a.as_ptr();
         let m = 0b11101000;
-        let r = _mm256_maskz_expandloadu_ps(m, black_box(p));
+        let r = unsafe { _mm256_maskz_expandloadu_ps(m, black_box(p)) };
         let e = _mm256_set_ps(4., 3., 2., 0., 1., 0., 0., 0.);
         assert_eq_m256(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_expandloadu_ps() {
+    fn test_mm_mask_expandloadu_ps() {
         let src = _mm_set1_ps(42.);
         let a = &[1.0f32, 2., 3., 4.];
         let p = a.as_ptr();
         let m = 0b11101000;
-        let r = _mm_mask_expandloadu_ps(src, m, black_box(p));
+        let r = unsafe { _mm_mask_expandloadu_ps(src, m, black_box(p)) };
         let e = _mm_set_ps(1., 42., 42., 42.);
         assert_eq_m128(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_expandloadu_ps() {
+    fn test_mm_maskz_expandloadu_ps() {
         let a = &[1.0f32, 2., 3., 4.];
         let p = a.as_ptr();
         let m = 0b11101000;
-        let r = _mm_maskz_expandloadu_ps(m, black_box(p));
+        let r = unsafe { _mm_maskz_expandloadu_ps(m, black_box(p)) };
         let e = _mm_set_ps(1., 0., 0., 0.);
         assert_eq_m128(r, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_expandloadu_pd() {
+    fn test_mm512_mask_expandloadu_pd() {
         let src = _mm512_set1_pd(42.);
         let a = &[1.0f64, 2., 3., 4., 5., 6., 7., 8.];
         let p = a.as_ptr();
         let m = 0b11101000;
-        let r = _mm512_mask_expandloadu_pd(src, m, black_box(p));
+        let r = unsafe { _mm512_mask_expandloadu_pd(src, m, black_box(p)) };
         let e = _mm512_set_pd(4., 3., 2., 42., 1., 42., 42., 42.);
         assert_eq_m512d(r, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_maskz_expandloadu_pd() {
+    fn test_mm512_maskz_expandloadu_pd() {
         let a = &[1.0f64, 2., 3., 4., 5., 6., 7., 8.];
         let p = a.as_ptr();
         let m = 0b11101000;
-        let r = _mm512_maskz_expandloadu_pd(m, black_box(p));
+        let r = unsafe { _mm512_maskz_expandloadu_pd(m, black_box(p)) };
         let e = _mm512_set_pd(4., 3., 2., 0., 1., 0., 0., 0.);
         assert_eq_m512d(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_expandloadu_pd() {
+    fn test_mm256_mask_expandloadu_pd() {
         let src = _mm256_set1_pd(42.);
         let a = &[1.0f64, 2., 3., 4.];
         let p = a.as_ptr();
         let m = 0b11101000;
-        let r = _mm256_mask_expandloadu_pd(src, m, black_box(p));
+        let r = unsafe { _mm256_mask_expandloadu_pd(src, m, black_box(p)) };
         let e = _mm256_set_pd(1., 42., 42., 42.);
         assert_eq_m256d(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_maskz_expandloadu_pd() {
+    fn test_mm256_maskz_expandloadu_pd() {
         let a = &[1.0f64, 2., 3., 4.];
         let p = a.as_ptr();
         let m = 0b11101000;
-        let r = _mm256_maskz_expandloadu_pd(m, black_box(p));
+        let r = unsafe { _mm256_maskz_expandloadu_pd(m, black_box(p)) };
         let e = _mm256_set_pd(1., 0., 0., 0.);
         assert_eq_m256d(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_expandloadu_pd() {
+    fn test_mm_mask_expandloadu_pd() {
         let src = _mm_set1_pd(42.);
         let a = &[1.0f64, 2.];
         let p = a.as_ptr();
         let m = 0b11101000;
-        let r = _mm_mask_expandloadu_pd(src, m, black_box(p));
+        let r = unsafe { _mm_mask_expandloadu_pd(src, m, black_box(p)) };
         let e = _mm_set_pd(42., 42.);
         assert_eq_m128d(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_maskz_expandloadu_pd() {
+    fn test_mm_maskz_expandloadu_pd() {
         let a = &[1.0f64, 2.];
         let p = a.as_ptr();
         let m = 0b11101000;
-        let r = _mm_maskz_expandloadu_pd(m, black_box(p));
+        let r = unsafe { _mm_maskz_expandloadu_pd(m, black_box(p)) };
         let e = _mm_set_pd(0., 0.);
         assert_eq_m128d(r, e);
     }
diff --git a/library/stdarch/crates/core_arch/src/x86/avx512fp16.rs b/library/stdarch/crates/core_arch/src/x86/avx512fp16.rs
index 57d47c0bb010..f581711a3c99 100644
--- a/library/stdarch/crates/core_arch/src/x86/avx512fp16.rs
+++ b/library/stdarch/crates/core_arch/src/x86/avx512fp16.rs
@@ -16932,7 +16932,6 @@ unsafe extern "C" {
 mod tests {
     use crate::core_arch::assert_eq_const as assert_eq;
     use crate::core_arch::x86::*;
-    use crate::mem::transmute;
     use crate::ptr::{addr_of, addr_of_mut};
     use stdarch_test::simd_test;
 
@@ -17569,72 +17568,72 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm_load_ph() {
+    const fn test_mm_load_ph() {
         let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
-        let b = _mm_load_ph(addr_of!(a).cast());
+        let b = unsafe { _mm_load_ph(addr_of!(a).cast()) };
         assert_eq_m128h(a, b);
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm256_load_ph() {
+    const fn test_mm256_load_ph() {
         let a = _mm256_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
         );
-        let b = _mm256_load_ph(addr_of!(a).cast());
+        let b = unsafe { _mm256_load_ph(addr_of!(a).cast()) };
         assert_eq_m256h(a, b);
     }
 
     #[simd_test(enable = "avx512fp16")]
-    const unsafe fn test_mm512_load_ph() {
+    const fn test_mm512_load_ph() {
         let a = _mm512_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
             17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
             31.0, 32.0,
         );
-        let b = _mm512_load_ph(addr_of!(a).cast());
+        let b = unsafe { _mm512_load_ph(addr_of!(a).cast()) };
         assert_eq_m512h(a, b);
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm_load_sh() {
+    const fn test_mm_load_sh() {
         let a = _mm_set_sh(1.0);
-        let b = _mm_load_sh(addr_of!(a).cast());
+        let b = unsafe { _mm_load_sh(addr_of!(a).cast()) };
         assert_eq_m128h(a, b);
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask_load_sh() {
+    fn test_mm_mask_load_sh() {
         let a = _mm_set_sh(1.0);
         let src = _mm_set_sh(2.);
-        let b = _mm_mask_load_sh(src, 1, addr_of!(a).cast());
+        let b = unsafe { _mm_mask_load_sh(src, 1, addr_of!(a).cast()) };
         assert_eq_m128h(a, b);
-        let b = _mm_mask_load_sh(src, 0, addr_of!(a).cast());
+        let b = unsafe { _mm_mask_load_sh(src, 0, addr_of!(a).cast()) };
         assert_eq_m128h(src, b);
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_maskz_load_sh() {
+    fn test_mm_maskz_load_sh() {
         let a = _mm_set_sh(1.0);
-        let b = _mm_maskz_load_sh(1, addr_of!(a).cast());
+        let b = unsafe { _mm_maskz_load_sh(1, addr_of!(a).cast()) };
         assert_eq_m128h(a, b);
-        let b = _mm_maskz_load_sh(0, addr_of!(a).cast());
+        let b = unsafe { _mm_maskz_load_sh(0, addr_of!(a).cast()) };
         assert_eq_m128h(_mm_setzero_ph(), b);
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm_loadu_ph() {
+    const fn test_mm_loadu_ph() {
         let array = [1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0];
-        let r = _mm_loadu_ph(array.as_ptr());
+        let r = unsafe { _mm_loadu_ph(array.as_ptr()) };
         let e = _mm_setr_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         assert_eq_m128h(r, e);
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm256_loadu_ph() {
+    const fn test_mm256_loadu_ph() {
         let array = [
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
         ];
-        let r = _mm256_loadu_ph(array.as_ptr());
+        let r = unsafe { _mm256_loadu_ph(array.as_ptr()) };
         let e = _mm256_setr_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
         );
@@ -17642,13 +17641,13 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16")]
-    const unsafe fn test_mm512_loadu_ph() {
+    const fn test_mm512_loadu_ph() {
         let array = [
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
             17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
             31.0, 32.0,
         ];
-        let r = _mm512_loadu_ph(array.as_ptr());
+        let r = unsafe { _mm512_loadu_ph(array.as_ptr()) };
         let e = _mm512_setr_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
             17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
@@ -17686,81 +17685,99 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm_store_ph() {
+    const fn test_mm_store_ph() {
         let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let mut b = _mm_setzero_ph();
-        _mm_store_ph(addr_of_mut!(b).cast(), a);
+        unsafe {
+            _mm_store_ph(addr_of_mut!(b).cast(), a);
+        }
         assert_eq_m128h(a, b);
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm256_store_ph() {
+    const fn test_mm256_store_ph() {
         let a = _mm256_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
         );
         let mut b = _mm256_setzero_ph();
-        _mm256_store_ph(addr_of_mut!(b).cast(), a);
+        unsafe {
+            _mm256_store_ph(addr_of_mut!(b).cast(), a);
+        }
         assert_eq_m256h(a, b);
     }
 
     #[simd_test(enable = "avx512fp16")]
-    const unsafe fn test_mm512_store_ph() {
+    const fn test_mm512_store_ph() {
         let a = _mm512_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
             17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
             31.0, 32.0,
         );
         let mut b = _mm512_setzero_ph();
-        _mm512_store_ph(addr_of_mut!(b).cast(), a);
+        unsafe {
+            _mm512_store_ph(addr_of_mut!(b).cast(), a);
+        }
         assert_eq_m512h(a, b);
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm_store_sh() {
+    const fn test_mm_store_sh() {
         let a = _mm_set_sh(1.0);
         let mut b = _mm_setzero_ph();
-        _mm_store_sh(addr_of_mut!(b).cast(), a);
+        unsafe {
+            _mm_store_sh(addr_of_mut!(b).cast(), a);
+        }
         assert_eq_m128h(a, b);
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    unsafe fn test_mm_mask_store_sh() {
+    fn test_mm_mask_store_sh() {
         let a = _mm_set_sh(1.0);
         let mut b = _mm_setzero_ph();
-        _mm_mask_store_sh(addr_of_mut!(b).cast(), 0, a);
+        unsafe {
+            _mm_mask_store_sh(addr_of_mut!(b).cast(), 0, a);
+        }
         assert_eq_m128h(_mm_setzero_ph(), b);
-        _mm_mask_store_sh(addr_of_mut!(b).cast(), 1, a);
+        unsafe {
+            _mm_mask_store_sh(addr_of_mut!(b).cast(), 1, a);
+        }
         assert_eq_m128h(a, b);
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm_storeu_ph() {
+    const fn test_mm_storeu_ph() {
         let a = _mm_set_ph(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
         let mut array = [0.0; 8];
-        _mm_storeu_ph(array.as_mut_ptr(), a);
-        assert_eq_m128h(a, _mm_loadu_ph(array.as_ptr()));
+        unsafe {
+            _mm_storeu_ph(array.as_mut_ptr(), a);
+        }
+        assert_eq_m128h(a, unsafe { _mm_loadu_ph(array.as_ptr()) });
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
-    const unsafe fn test_mm256_storeu_ph() {
+    const fn test_mm256_storeu_ph() {
         let a = _mm256_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
         );
         let mut array = [0.0; 16];
-        _mm256_storeu_ph(array.as_mut_ptr(), a);
-        assert_eq_m256h(a, _mm256_loadu_ph(array.as_ptr()));
+        unsafe {
+            _mm256_storeu_ph(array.as_mut_ptr(), a);
+        }
+        assert_eq_m256h(a, unsafe { _mm256_loadu_ph(array.as_ptr()) });
     }
 
     #[simd_test(enable = "avx512fp16")]
-    const unsafe fn test_mm512_storeu_ph() {
+    const fn test_mm512_storeu_ph() {
         let a = _mm512_set_ph(
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
             17.0, 18.0, 19.0, 20.0, 21.0, 22.0, 23.0, 24.0, 25.0, 26.0, 27.0, 28.0, 29.0, 30.0,
             31.0, 32.0,
         );
         let mut array = [0.0; 32];
-        _mm512_storeu_ph(array.as_mut_ptr(), a);
-        assert_eq_m512h(a, _mm512_loadu_ph(array.as_ptr()));
+        unsafe {
+            _mm512_storeu_ph(array.as_mut_ptr(), a);
+        }
+        assert_eq_m512h(a, unsafe { _mm512_loadu_ph(array.as_ptr()) });
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
diff --git a/library/stdarch/crates/core_arch/src/x86/avx512vbmi2.rs b/library/stdarch/crates/core_arch/src/x86/avx512vbmi2.rs
index 26cef5814e9c..78a50b90c861 100644
--- a/library/stdarch/crates/core_arch/src/x86/avx512vbmi2.rs
+++ b/library/stdarch/crates/core_arch/src/x86/avx512vbmi2.rs
@@ -3932,7 +3932,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2")]
-    unsafe fn test_mm512_mask_expandloadu_epi16() {
+    fn test_mm512_mask_expandloadu_epi16() {
         let src = _mm512_set1_epi16(42);
         let a = &[
             1_i16, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23,
@@ -3940,7 +3940,7 @@ mod tests {
         ];
         let p = a.as_ptr();
         let m = 0b11101000_11001010_11110000_00001111;
-        let r = _mm512_mask_expandloadu_epi16(src, m, black_box(p));
+        let r = unsafe { _mm512_mask_expandloadu_epi16(src, m, black_box(p)) };
         let e = _mm512_set_epi16(
             16, 15, 14, 42, 13, 42, 42, 42, 12, 11, 42, 42, 10, 42, 9, 42, 8, 7, 6, 5, 42, 42, 42,
             42, 42, 42, 42, 42, 4, 3, 2, 1,
@@ -3949,14 +3949,14 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2")]
-    unsafe fn test_mm512_maskz_expandloadu_epi16() {
+    fn test_mm512_maskz_expandloadu_epi16() {
         let a = &[
             1_i16, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23,
             24, 25, 26, 27, 28, 29, 30, 31, 32,
         ];
         let p = a.as_ptr();
         let m = 0b11101000_11001010_11110000_00001111;
-        let r = _mm512_maskz_expandloadu_epi16(m, black_box(p));
+        let r = unsafe { _mm512_maskz_expandloadu_epi16(m, black_box(p)) };
         let e = _mm512_set_epi16(
             16, 15, 14, 0, 13, 0, 0, 0, 12, 11, 0, 0, 10, 0, 9, 0, 8, 7, 6, 5, 0, 0, 0, 0, 0, 0, 0,
             0, 4, 3, 2, 1,
@@ -3965,49 +3965,49 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    unsafe fn test_mm256_mask_expandloadu_epi16() {
+    fn test_mm256_mask_expandloadu_epi16() {
         let src = _mm256_set1_epi16(42);
         let a = &[1_i16, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16];
         let p = a.as_ptr();
         let m = 0b11101000_11001010;
-        let r = _mm256_mask_expandloadu_epi16(src, m, black_box(p));
+        let r = unsafe { _mm256_mask_expandloadu_epi16(src, m, black_box(p)) };
         let e = _mm256_set_epi16(8, 7, 6, 42, 5, 42, 42, 42, 4, 3, 42, 42, 2, 42, 1, 42);
         assert_eq_m256i(r, e);
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    unsafe fn test_mm256_maskz_expandloadu_epi16() {
+    fn test_mm256_maskz_expandloadu_epi16() {
         let a = &[1_i16, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16];
         let p = a.as_ptr();
         let m = 0b11101000_11001010;
-        let r = _mm256_maskz_expandloadu_epi16(m, black_box(p));
+        let r = unsafe { _mm256_maskz_expandloadu_epi16(m, black_box(p)) };
         let e = _mm256_set_epi16(8, 7, 6, 0, 5, 0, 0, 0, 4, 3, 0, 0, 2, 0, 1, 0);
         assert_eq_m256i(r, e);
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    unsafe fn test_mm_mask_expandloadu_epi16() {
+    fn test_mm_mask_expandloadu_epi16() {
         let src = _mm_set1_epi16(42);
         let a = &[1_i16, 2, 3, 4, 5, 6, 7, 8];
         let p = a.as_ptr();
         let m = 0b11101000;
-        let r = _mm_mask_expandloadu_epi16(src, m, black_box(p));
+        let r = unsafe { _mm_mask_expandloadu_epi16(src, m, black_box(p)) };
         let e = _mm_set_epi16(4, 3, 2, 42, 1, 42, 42, 42);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    unsafe fn test_mm_maskz_expandloadu_epi16() {
+    fn test_mm_maskz_expandloadu_epi16() {
         let a = &[1_i16, 2, 3, 4, 5, 6, 7, 8];
         let p = a.as_ptr();
         let m = 0b11101000;
-        let r = _mm_maskz_expandloadu_epi16(m, black_box(p));
+        let r = unsafe { _mm_maskz_expandloadu_epi16(m, black_box(p)) };
         let e = _mm_set_epi16(4, 3, 2, 0, 1, 0, 0, 0);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512vbmi2")]
-    unsafe fn test_mm512_mask_expandloadu_epi8() {
+    fn test_mm512_mask_expandloadu_epi8() {
         let src = _mm512_set1_epi8(42);
         let a = &[
             1_i8, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23,
@@ -4016,7 +4016,7 @@ mod tests {
         ];
         let p = a.as_ptr();
         let m = 0b11101000_11001010_11110000_00001111_11111111_00000000_10101010_01010101;
-        let r = _mm512_mask_expandloadu_epi8(src, m, black_box(p));
+        let r = unsafe { _mm512_mask_expandloadu_epi8(src, m, black_box(p)) };
         let e = _mm512_set_epi8(
             32, 31, 30, 42, 29, 42, 42, 42, 28, 27, 42, 42, 26, 42, 25, 42, 24, 23, 22, 21, 42, 42,
             42, 42, 42, 42, 42, 42, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 42, 42, 42, 42,
@@ -4026,7 +4026,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2")]
-    unsafe fn test_mm512_maskz_expandloadu_epi8() {
+    fn test_mm512_maskz_expandloadu_epi8() {
         let a = &[
             1_i8, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23,
             24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45,
@@ -4034,7 +4034,7 @@ mod tests {
         ];
         let p = a.as_ptr();
         let m = 0b11101000_11001010_11110000_00001111_11111111_00000000_10101010_01010101;
-        let r = _mm512_maskz_expandloadu_epi8(m, black_box(p));
+        let r = unsafe { _mm512_maskz_expandloadu_epi8(m, black_box(p)) };
         let e = _mm512_set_epi8(
             32, 31, 30, 0, 29, 0, 0, 0, 28, 27, 0, 0, 26, 0, 25, 0, 24, 23, 22, 21, 0, 0, 0, 0, 0,
             0, 0, 0, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 0, 0, 0, 0, 0, 0, 0, 0, 8, 0,
@@ -4044,7 +4044,7 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    unsafe fn test_mm256_mask_expandloadu_epi8() {
+    fn test_mm256_mask_expandloadu_epi8() {
         let src = _mm256_set1_epi8(42);
         let a = &[
             1_i8, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23,
@@ -4052,7 +4052,7 @@ mod tests {
         ];
         let p = a.as_ptr();
         let m = 0b11101000_11001010_11110000_00001111;
-        let r = _mm256_mask_expandloadu_epi8(src, m, black_box(p));
+        let r = unsafe { _mm256_mask_expandloadu_epi8(src, m, black_box(p)) };
         let e = _mm256_set_epi8(
             16, 15, 14, 42, 13, 42, 42, 42, 12, 11, 42, 42, 10, 42, 9, 42, 8, 7, 6, 5, 42, 42, 42,
             42, 42, 42, 42, 42, 4, 3, 2, 1,
@@ -4061,14 +4061,14 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    unsafe fn test_mm256_maskz_expandloadu_epi8() {
+    fn test_mm256_maskz_expandloadu_epi8() {
         let a = &[
             1_i8, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23,
             24, 25, 26, 27, 28, 29, 30, 31, 32,
         ];
         let p = a.as_ptr();
         let m = 0b11101000_11001010_11110000_00001111;
-        let r = _mm256_maskz_expandloadu_epi8(m, black_box(p));
+        let r = unsafe { _mm256_maskz_expandloadu_epi8(m, black_box(p)) };
         let e = _mm256_set_epi8(
             16, 15, 14, 0, 13, 0, 0, 0, 12, 11, 0, 0, 10, 0, 9, 0, 8, 7, 6, 5, 0, 0, 0, 0, 0, 0, 0,
             0, 4, 3, 2, 1,
@@ -4077,36 +4077,44 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    unsafe fn test_mm_mask_expandloadu_epi8() {
+    fn test_mm_mask_expandloadu_epi8() {
         let src = _mm_set1_epi8(42);
         let a = &[1_i8, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16];
         let p = a.as_ptr();
         let m = 0b11101000_11001010;
-        let r = _mm_mask_expandloadu_epi8(src, m, black_box(p));
+        let r = unsafe { _mm_mask_expandloadu_epi8(src, m, black_box(p)) };
         let e = _mm_set_epi8(8, 7, 6, 42, 5, 42, 42, 42, 4, 3, 42, 42, 2, 42, 1, 42);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    unsafe fn test_mm_maskz_expandloadu_epi8() {
+    fn test_mm_maskz_expandloadu_epi8() {
         let a = &[1_i8, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16];
         let p = a.as_ptr();
         let m = 0b11101000_11001010;
-        let r = _mm_maskz_expandloadu_epi8(m, black_box(p));
+        let r = unsafe { _mm_maskz_expandloadu_epi8(m, black_box(p)) };
         let e = _mm_set_epi8(8, 7, 6, 0, 5, 0, 0, 0, 4, 3, 0, 0, 2, 0, 1, 0);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512vbmi2")]
-    unsafe fn test_mm512_mask_compressstoreu_epi16() {
+    fn test_mm512_mask_compressstoreu_epi16() {
         let a = _mm512_set_epi16(
             32, 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11,
             10, 9, 8, 7, 6, 5, 4, 3, 2, 1,
         );
         let mut r = [0_i16; 32];
-        _mm512_mask_compressstoreu_epi16(r.as_mut_ptr(), 0, a);
+        unsafe {
+            _mm512_mask_compressstoreu_epi16(r.as_mut_ptr(), 0, a);
+        }
         assert_eq!(&r, &[0_i16; 32]);
-        _mm512_mask_compressstoreu_epi16(r.as_mut_ptr(), 0b11110000_11001010_11111111_00000000, a);
+        unsafe {
+            _mm512_mask_compressstoreu_epi16(
+                r.as_mut_ptr(),
+                0b11110000_11001010_11111111_00000000,
+                a,
+            );
+        }
         assert_eq!(
             &r,
             &[
@@ -4117,40 +4125,52 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    unsafe fn test_mm256_mask_compressstoreu_epi16() {
+    fn test_mm256_mask_compressstoreu_epi16() {
         let a = _mm256_set_epi16(16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1);
         let mut r = [0_i16; 16];
-        _mm256_mask_compressstoreu_epi16(r.as_mut_ptr(), 0, a);
+        unsafe {
+            _mm256_mask_compressstoreu_epi16(r.as_mut_ptr(), 0, a);
+        }
         assert_eq!(&r, &[0_i16; 16]);
-        _mm256_mask_compressstoreu_epi16(r.as_mut_ptr(), 0b11110000_11001010, a);
+        unsafe {
+            _mm256_mask_compressstoreu_epi16(r.as_mut_ptr(), 0b11110000_11001010, a);
+        }
         assert_eq!(&r, &[2, 4, 7, 8, 13, 14, 15, 16, 0, 0, 0, 0, 0, 0, 0, 0]);
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    unsafe fn test_mm_mask_compressstoreu_epi16() {
+    fn test_mm_mask_compressstoreu_epi16() {
         let a = _mm_set_epi16(8, 7, 6, 5, 4, 3, 2, 1);
         let mut r = [0_i16; 8];
-        _mm_mask_compressstoreu_epi16(r.as_mut_ptr(), 0, a);
+        unsafe {
+            _mm_mask_compressstoreu_epi16(r.as_mut_ptr(), 0, a);
+        }
         assert_eq!(&r, &[0_i16; 8]);
-        _mm_mask_compressstoreu_epi16(r.as_mut_ptr(), 0b11110000, a);
+        unsafe {
+            _mm_mask_compressstoreu_epi16(r.as_mut_ptr(), 0b11110000, a);
+        }
         assert_eq!(&r, &[5, 6, 7, 8, 0, 0, 0, 0]);
     }
 
     #[simd_test(enable = "avx512vbmi2")]
-    unsafe fn test_mm512_mask_compressstoreu_epi8() {
+    fn test_mm512_mask_compressstoreu_epi8() {
         let a = _mm512_set_epi8(
             64, 63, 62, 61, 60, 59, 58, 57, 56, 55, 54, 53, 52, 51, 50, 49, 48, 47, 46, 45, 44, 43,
             42, 41, 40, 39, 38, 37, 36, 35, 34, 33, 32, 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21,
             20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1,
         );
         let mut r = [0_i8; 64];
-        _mm512_mask_compressstoreu_epi8(r.as_mut_ptr(), 0, a);
+        unsafe {
+            _mm512_mask_compressstoreu_epi8(r.as_mut_ptr(), 0, a);
+        }
         assert_eq!(&r, &[0_i8; 64]);
-        _mm512_mask_compressstoreu_epi8(
-            r.as_mut_ptr(),
-            0b11110000_11001010_11111111_00000000_10101010_01010101_11110000_00001111,
-            a,
-        );
+        unsafe {
+            _mm512_mask_compressstoreu_epi8(
+                r.as_mut_ptr(),
+                0b11110000_11001010_11111111_00000000_10101010_01010101_11110000_00001111,
+                a,
+            );
+        }
         assert_eq!(
             &r,
             &[
@@ -4162,15 +4182,23 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    unsafe fn test_mm256_mask_compressstoreu_epi8() {
+    fn test_mm256_mask_compressstoreu_epi8() {
         let a = _mm256_set_epi8(
             32, 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11,
             10, 9, 8, 7, 6, 5, 4, 3, 2, 1,
         );
         let mut r = [0_i8; 32];
-        _mm256_mask_compressstoreu_epi8(r.as_mut_ptr(), 0, a);
+        unsafe {
+            _mm256_mask_compressstoreu_epi8(r.as_mut_ptr(), 0, a);
+        }
         assert_eq!(&r, &[0_i8; 32]);
-        _mm256_mask_compressstoreu_epi8(r.as_mut_ptr(), 0b11110000_11001010_11111111_00000000, a);
+        unsafe {
+            _mm256_mask_compressstoreu_epi8(
+                r.as_mut_ptr(),
+                0b11110000_11001010_11111111_00000000,
+                a,
+            );
+        }
         assert_eq!(
             &r,
             &[
@@ -4181,12 +4209,16 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512vbmi2,avx512vl")]
-    unsafe fn test_mm_mask_compressstoreu_epi8() {
+    fn test_mm_mask_compressstoreu_epi8() {
         let a = _mm_set_epi8(16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1);
         let mut r = [0_i8; 16];
-        _mm_mask_compressstoreu_epi8(r.as_mut_ptr(), 0, a);
+        unsafe {
+            _mm_mask_compressstoreu_epi8(r.as_mut_ptr(), 0, a);
+        }
         assert_eq!(&r, &[0_i8; 16]);
-        _mm_mask_compressstoreu_epi8(r.as_mut_ptr(), 0b11110000_11001010, a);
+        unsafe {
+            _mm_mask_compressstoreu_epi8(r.as_mut_ptr(), 0b11110000_11001010, a);
+        }
         assert_eq!(&r, &[2, 4, 7, 8, 13, 14, 15, 16, 0, 0, 0, 0, 0, 0, 0, 0]);
     }
 }
diff --git a/library/stdarch/crates/core_arch/src/x86/avxneconvert.rs b/library/stdarch/crates/core_arch/src/x86/avxneconvert.rs
index a53d6d97e8a0..91b6be2b09d7 100644
--- a/library/stdarch/crates/core_arch/src/x86/avxneconvert.rs
+++ b/library/stdarch/crates/core_arch/src/x86/avxneconvert.rs
@@ -242,127 +242,127 @@ mod tests {
     const BF16_EIGHT: u16 = 0b0_10000010_0000000;
 
     #[simd_test(enable = "avxneconvert")]
-    unsafe fn test_mm_bcstnebf16_ps() {
+    fn test_mm_bcstnebf16_ps() {
         let a = bf16::from_bits(BF16_ONE);
-        let r = _mm_bcstnebf16_ps(addr_of!(a));
+        let r = unsafe { _mm_bcstnebf16_ps(addr_of!(a)) };
         let e = _mm_set_ps(1., 1., 1., 1.);
         assert_eq_m128(r, e);
     }
 
     #[simd_test(enable = "avxneconvert")]
-    unsafe fn test_mm256_bcstnebf16_ps() {
+    fn test_mm256_bcstnebf16_ps() {
         let a = bf16::from_bits(BF16_ONE);
-        let r = _mm256_bcstnebf16_ps(addr_of!(a));
+        let r = unsafe { _mm256_bcstnebf16_ps(addr_of!(a)) };
         let e = _mm256_set_ps(1., 1., 1., 1., 1., 1., 1., 1.);
         assert_eq_m256(r, e);
     }
 
     #[simd_test(enable = "avxneconvert")]
-    unsafe fn test_mm_bcstnesh_ps() {
+    fn test_mm_bcstnesh_ps() {
         let a = 1.0_f16;
-        let r = _mm_bcstnesh_ps(addr_of!(a));
+        let r = unsafe { _mm_bcstnesh_ps(addr_of!(a)) };
         let e = _mm_set_ps(1., 1., 1., 1.);
         assert_eq_m128(r, e);
     }
 
     #[simd_test(enable = "avxneconvert")]
-    unsafe fn test_mm256_bcstnesh_ps() {
+    fn test_mm256_bcstnesh_ps() {
         let a = 1.0_f16;
-        let r = _mm256_bcstnesh_ps(addr_of!(a));
+        let r = unsafe { _mm256_bcstnesh_ps(addr_of!(a)) };
         let e = _mm256_set_ps(1., 1., 1., 1., 1., 1., 1., 1.);
         assert_eq_m256(r, e);
     }
 
     #[simd_test(enable = "avxneconvert")]
-    unsafe fn test_mm_cvtneebf16_ps() {
+    fn test_mm_cvtneebf16_ps() {
         let a = __m128bh([
             BF16_ONE, BF16_TWO, BF16_THREE, BF16_FOUR, BF16_FIVE, BF16_SIX, BF16_SEVEN, BF16_EIGHT,
         ]);
-        let r = _mm_cvtneebf16_ps(addr_of!(a));
+        let r = unsafe { _mm_cvtneebf16_ps(addr_of!(a)) };
         let e = _mm_setr_ps(1., 3., 5., 7.);
         assert_eq_m128(r, e);
     }
 
     #[simd_test(enable = "avxneconvert")]
-    unsafe fn test_mm256_cvtneebf16_ps() {
+    fn test_mm256_cvtneebf16_ps() {
         let a = __m256bh([
             BF16_ONE, BF16_TWO, BF16_THREE, BF16_FOUR, BF16_FIVE, BF16_SIX, BF16_SEVEN, BF16_EIGHT,
             BF16_ONE, BF16_TWO, BF16_THREE, BF16_FOUR, BF16_FIVE, BF16_SIX, BF16_SEVEN, BF16_EIGHT,
         ]);
-        let r = _mm256_cvtneebf16_ps(addr_of!(a));
+        let r = unsafe { _mm256_cvtneebf16_ps(addr_of!(a)) };
         let e = _mm256_setr_ps(1., 3., 5., 7., 1., 3., 5., 7.);
         assert_eq_m256(r, e);
     }
 
     #[simd_test(enable = "avxneconvert")]
-    unsafe fn test_mm_cvtneeph_ps() {
+    fn test_mm_cvtneeph_ps() {
         let a = __m128h([1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0]);
-        let r = _mm_cvtneeph_ps(addr_of!(a));
+        let r = unsafe { _mm_cvtneeph_ps(addr_of!(a)) };
         let e = _mm_setr_ps(1., 3., 5., 7.);
         assert_eq_m128(r, e);
     }
 
     #[simd_test(enable = "avxneconvert")]
-    unsafe fn test_mm256_cvtneeph_ps() {
+    fn test_mm256_cvtneeph_ps() {
         let a = __m256h([
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
         ]);
-        let r = _mm256_cvtneeph_ps(addr_of!(a));
+        let r = unsafe { _mm256_cvtneeph_ps(addr_of!(a)) };
         let e = _mm256_setr_ps(1., 3., 5., 7., 9., 11., 13., 15.);
         assert_eq_m256(r, e);
     }
 
     #[simd_test(enable = "avxneconvert")]
-    unsafe fn test_mm_cvtneobf16_ps() {
+    fn test_mm_cvtneobf16_ps() {
         let a = __m128bh([
             BF16_ONE, BF16_TWO, BF16_THREE, BF16_FOUR, BF16_FIVE, BF16_SIX, BF16_SEVEN, BF16_EIGHT,
         ]);
-        let r = _mm_cvtneobf16_ps(addr_of!(a));
+        let r = unsafe { _mm_cvtneobf16_ps(addr_of!(a)) };
         let e = _mm_setr_ps(2., 4., 6., 8.);
         assert_eq_m128(r, e);
     }
 
     #[simd_test(enable = "avxneconvert")]
-    unsafe fn test_mm256_cvtneobf16_ps() {
+    fn test_mm256_cvtneobf16_ps() {
         let a = __m256bh([
             BF16_ONE, BF16_TWO, BF16_THREE, BF16_FOUR, BF16_FIVE, BF16_SIX, BF16_SEVEN, BF16_EIGHT,
             BF16_ONE, BF16_TWO, BF16_THREE, BF16_FOUR, BF16_FIVE, BF16_SIX, BF16_SEVEN, BF16_EIGHT,
         ]);
-        let r = _mm256_cvtneobf16_ps(addr_of!(a));
+        let r = unsafe { _mm256_cvtneobf16_ps(addr_of!(a)) };
         let e = _mm256_setr_ps(2., 4., 6., 8., 2., 4., 6., 8.);
         assert_eq_m256(r, e);
     }
 
     #[simd_test(enable = "avxneconvert")]
-    unsafe fn test_mm_cvtneoph_ps() {
+    fn test_mm_cvtneoph_ps() {
         let a = __m128h([1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0]);
-        let r = _mm_cvtneoph_ps(addr_of!(a));
+        let r = unsafe { _mm_cvtneoph_ps(addr_of!(a)) };
         let e = _mm_setr_ps(2., 4., 6., 8.);
         assert_eq_m128(r, e);
     }
 
     #[simd_test(enable = "avxneconvert")]
-    unsafe fn test_mm256_cvtneoph_ps() {
+    fn test_mm256_cvtneoph_ps() {
         let a = __m256h([
             1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0,
         ]);
-        let r = _mm256_cvtneoph_ps(addr_of!(a));
+        let r = unsafe { _mm256_cvtneoph_ps(addr_of!(a)) };
         let e = _mm256_setr_ps(2., 4., 6., 8., 10., 12., 14., 16.);
         assert_eq_m256(r, e);
     }
 
     #[simd_test(enable = "avxneconvert")]
-    unsafe fn test_mm_cvtneps_avx_pbh() {
+    fn test_mm_cvtneps_avx_pbh() {
         let a = _mm_setr_ps(1., 2., 3., 4.);
-        let r: u16x4 = transmute_copy(&_mm_cvtneps_avx_pbh(a));
+        let r: u16x4 = unsafe { transmute_copy(&_mm_cvtneps_avx_pbh(a)) };
         let e = u16x4::new(BF16_ONE, BF16_TWO, BF16_THREE, BF16_FOUR);
         assert_eq!(r, e);
     }
 
     #[simd_test(enable = "avxneconvert")]
-    unsafe fn test_mm256_cvtneps_avx_pbh() {
+    fn test_mm256_cvtneps_avx_pbh() {
         let a = _mm256_setr_ps(1., 2., 3., 4., 5., 6., 7., 8.);
-        let r: u16x8 = transmute(_mm256_cvtneps_avx_pbh(a));
+        let r: u16x8 = _mm256_cvtneps_avx_pbh(a).as_u16x8();
         let e = u16x8::new(
             BF16_ONE, BF16_TWO, BF16_THREE, BF16_FOUR, BF16_FIVE, BF16_SIX, BF16_SEVEN, BF16_EIGHT,
         );
diff --git a/library/stdarch/crates/core_arch/src/x86/f16c.rs b/library/stdarch/crates/core_arch/src/x86/f16c.rs
index 0a26a9ff8d25..a0bb992bb9d4 100644
--- a/library/stdarch/crates/core_arch/src/x86/f16c.rs
+++ b/library/stdarch/crates/core_arch/src/x86/f16c.rs
@@ -106,7 +106,7 @@ pub fn _mm256_cvtps_ph<const IMM_ROUNDING: i32>(a: __m256) -> __m128i {
 #[cfg(test)]
 mod tests {
     use crate::core_arch::assert_eq_const as assert_eq;
-    use crate::{core_arch::x86::*, mem::transmute};
+    use crate::core_arch::x86::*;
     use stdarch_test::simd_test;
 
     const F16_ONE: i16 = 0x3c00;
diff --git a/library/stdarch/crates/core_arch/src/x86/fxsr.rs b/library/stdarch/crates/core_arch/src/x86/fxsr.rs
index 71fd52ca1496..08619efe7c9e 100644
--- a/library/stdarch/crates/core_arch/src/x86/fxsr.rs
+++ b/library/stdarch/crates/core_arch/src/x86/fxsr.rs
@@ -77,12 +77,14 @@ mod tests {
 
     #[simd_test(enable = "fxsr")]
     #[cfg_attr(miri, ignore)] // Register saving/restoring is not supported in Miri
-    unsafe fn test_fxsave() {
+    fn test_fxsave() {
         let mut a = FxsaveArea::new();
         let mut b = FxsaveArea::new();
 
-        fxsr::_fxsave(a.ptr());
-        fxsr::_fxrstor(a.ptr());
-        fxsr::_fxsave(b.ptr());
+        unsafe {
+            fxsr::_fxsave(a.ptr());
+            fxsr::_fxrstor(a.ptr());
+            fxsr::_fxsave(b.ptr());
+        }
     }
 }
diff --git a/library/stdarch/crates/core_arch/src/x86/gfni.rs b/library/stdarch/crates/core_arch/src/x86/gfni.rs
index 681b8ae330d4..e9ee27a7b823 100644
--- a/library/stdarch/crates/core_arch/src/x86/gfni.rs
+++ b/library/stdarch/crates/core_arch/src/x86/gfni.rs
@@ -898,25 +898,25 @@ mod tests {
     }
 
     #[simd_test(enable = "gfni,avx512f")]
-    unsafe fn test_mm512_gf2p8mul_epi8() {
+    fn test_mm512_gf2p8mul_epi8() {
         let (left, right, expected) = generate_byte_mul_test_data();
 
         for i in 0..NUM_TEST_WORDS_512 {
-            let left = load_m512i_word(&left, i);
-            let right = load_m512i_word(&right, i);
-            let expected = load_m512i_word(&expected, i);
+            let left = unsafe { load_m512i_word(&left, i) };
+            let right = unsafe { load_m512i_word(&right, i) };
+            let expected = unsafe { load_m512i_word(&expected, i) };
             let result = _mm512_gf2p8mul_epi8(left, right);
             assert_eq_m512i(result, expected);
         }
     }
 
     #[simd_test(enable = "gfni,avx512bw")]
-    unsafe fn test_mm512_maskz_gf2p8mul_epi8() {
+    fn test_mm512_maskz_gf2p8mul_epi8() {
         let (left, right, _expected) = generate_byte_mul_test_data();
 
         for i in 0..NUM_TEST_WORDS_512 {
-            let left = load_m512i_word(&left, i);
-            let right = load_m512i_word(&right, i);
+            let left = unsafe { load_m512i_word(&left, i) };
+            let right = unsafe { load_m512i_word(&right, i) };
             let result_zero = _mm512_maskz_gf2p8mul_epi8(0, left, right);
             assert_eq_m512i(result_zero, _mm512_setzero_si512());
             let mask_bytes: __mmask64 = 0x0F_0F_0F_0F_FF_FF_00_00;
@@ -930,12 +930,12 @@ mod tests {
     }
 
     #[simd_test(enable = "gfni,avx512bw")]
-    unsafe fn test_mm512_mask_gf2p8mul_epi8() {
+    fn test_mm512_mask_gf2p8mul_epi8() {
         let (left, right, _expected) = generate_byte_mul_test_data();
 
         for i in 0..NUM_TEST_WORDS_512 {
-            let left = load_m512i_word(&left, i);
-            let right = load_m512i_word(&right, i);
+            let left = unsafe { load_m512i_word(&left, i) };
+            let right = unsafe { load_m512i_word(&right, i) };
             let result_left = _mm512_mask_gf2p8mul_epi8(left, 0, left, right);
             assert_eq_m512i(result_left, left);
             let mask_bytes: __mmask64 = 0x0F_0F_0F_0F_FF_FF_00_00;
@@ -948,25 +948,25 @@ mod tests {
     }
 
     #[simd_test(enable = "gfni,avx")]
-    unsafe fn test_mm256_gf2p8mul_epi8() {
+    fn test_mm256_gf2p8mul_epi8() {
         let (left, right, expected) = generate_byte_mul_test_data();
 
         for i in 0..NUM_TEST_WORDS_256 {
-            let left = load_m256i_word(&left, i);
-            let right = load_m256i_word(&right, i);
-            let expected = load_m256i_word(&expected, i);
+            let left = unsafe { load_m256i_word(&left, i) };
+            let right = unsafe { load_m256i_word(&right, i) };
+            let expected = unsafe { load_m256i_word(&expected, i) };
             let result = _mm256_gf2p8mul_epi8(left, right);
             assert_eq_m256i(result, expected);
         }
     }
 
     #[simd_test(enable = "gfni,avx512bw,avx512vl")]
-    unsafe fn test_mm256_maskz_gf2p8mul_epi8() {
+    fn test_mm256_maskz_gf2p8mul_epi8() {
         let (left, right, _expected) = generate_byte_mul_test_data();
 
         for i in 0..NUM_TEST_WORDS_256 {
-            let left = load_m256i_word(&left, i);
-            let right = load_m256i_word(&right, i);
+            let left = unsafe { load_m256i_word(&left, i) };
+            let right = unsafe { load_m256i_word(&right, i) };
             let result_zero = _mm256_maskz_gf2p8mul_epi8(0, left, right);
             assert_eq_m256i(result_zero, _mm256_setzero_si256());
             let mask_bytes: __mmask32 = 0x0F_F0_FF_00;
@@ -980,12 +980,12 @@ mod tests {
     }
 
     #[simd_test(enable = "gfni,avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_gf2p8mul_epi8() {
+    fn test_mm256_mask_gf2p8mul_epi8() {
         let (left, right, _expected) = generate_byte_mul_test_data();
 
         for i in 0..NUM_TEST_WORDS_256 {
-            let left = load_m256i_word(&left, i);
-            let right = load_m256i_word(&right, i);
+            let left = unsafe { load_m256i_word(&left, i) };
+            let right = unsafe { load_m256i_word(&right, i) };
             let result_left = _mm256_mask_gf2p8mul_epi8(left, 0, left, right);
             assert_eq_m256i(result_left, left);
             let mask_bytes: __mmask32 = 0x0F_F0_FF_00;
@@ -998,25 +998,25 @@ mod tests {
     }
 
     #[simd_test(enable = "gfni")]
-    unsafe fn test_mm_gf2p8mul_epi8() {
+    fn test_mm_gf2p8mul_epi8() {
         let (left, right, expected) = generate_byte_mul_test_data();
 
         for i in 0..NUM_TEST_WORDS_128 {
-            let left = load_m128i_word(&left, i);
-            let right = load_m128i_word(&right, i);
-            let expected = load_m128i_word(&expected, i);
+            let left = unsafe { load_m128i_word(&left, i) };
+            let right = unsafe { load_m128i_word(&right, i) };
+            let expected = unsafe { load_m128i_word(&expected, i) };
             let result = _mm_gf2p8mul_epi8(left, right);
             assert_eq_m128i(result, expected);
         }
     }
 
     #[simd_test(enable = "gfni,avx512bw,avx512vl")]
-    unsafe fn test_mm_maskz_gf2p8mul_epi8() {
+    fn test_mm_maskz_gf2p8mul_epi8() {
         let (left, right, _expected) = generate_byte_mul_test_data();
 
         for i in 0..NUM_TEST_WORDS_128 {
-            let left = load_m128i_word(&left, i);
-            let right = load_m128i_word(&right, i);
+            let left = unsafe { load_m128i_word(&left, i) };
+            let right = unsafe { load_m128i_word(&right, i) };
             let result_zero = _mm_maskz_gf2p8mul_epi8(0, left, right);
             assert_eq_m128i(result_zero, _mm_setzero_si128());
             let mask_bytes: __mmask16 = 0x0F_F0;
@@ -1030,12 +1030,12 @@ mod tests {
     }
 
     #[simd_test(enable = "gfni,avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_gf2p8mul_epi8() {
+    fn test_mm_mask_gf2p8mul_epi8() {
         let (left, right, _expected) = generate_byte_mul_test_data();
 
         for i in 0..NUM_TEST_WORDS_128 {
-            let left = load_m128i_word(&left, i);
-            let right = load_m128i_word(&right, i);
+            let left = unsafe { load_m128i_word(&left, i) };
+            let right = unsafe { load_m128i_word(&right, i) };
             let result_left = _mm_mask_gf2p8mul_epi8(left, 0, left, right);
             assert_eq_m128i(result_left, left);
             let mask_bytes: __mmask16 = 0x0F_F0;
@@ -1048,7 +1048,7 @@ mod tests {
     }
 
     #[simd_test(enable = "gfni,avx512f")]
-    unsafe fn test_mm512_gf2p8affine_epi64_epi8() {
+    fn test_mm512_gf2p8affine_epi64_epi8() {
         let identity: i64 = 0x01_02_04_08_10_20_40_80;
         const IDENTITY_BYTE: i32 = 0;
         let constant: i64 = 0;
@@ -1061,20 +1061,20 @@ mod tests {
         let (matrices, vectors, references) = generate_affine_mul_test_data(IDENTITY_BYTE as u8);
 
         for i in 0..NUM_TEST_WORDS_512 {
-            let data = load_m512i_word(&bytes, i);
+            let data = unsafe { load_m512i_word(&bytes, i) };
             let result = _mm512_gf2p8affine_epi64_epi8::<IDENTITY_BYTE>(data, identity);
             assert_eq_m512i(result, data);
             let result = _mm512_gf2p8affine_epi64_epi8::<CONSTANT_BYTE>(data, constant);
             assert_eq_m512i(result, constant_reference);
-            let data = load_m512i_word(&more_bytes, i);
+            let data = unsafe { load_m512i_word(&more_bytes, i) };
             let result = _mm512_gf2p8affine_epi64_epi8::<IDENTITY_BYTE>(data, identity);
             assert_eq_m512i(result, data);
             let result = _mm512_gf2p8affine_epi64_epi8::<CONSTANT_BYTE>(data, constant);
             assert_eq_m512i(result, constant_reference);
 
-            let matrix = load_m512i_word(&matrices, i);
-            let vector = load_m512i_word(&vectors, i);
-            let reference = load_m512i_word(&references, i);
+            let matrix = unsafe { load_m512i_word(&matrices, i) };
+            let vector = unsafe { load_m512i_word(&vectors, i) };
+            let reference = unsafe { load_m512i_word(&references, i) };
 
             let result = _mm512_gf2p8affine_epi64_epi8::<IDENTITY_BYTE>(vector, matrix);
             assert_eq_m512i(result, reference);
@@ -1082,13 +1082,13 @@ mod tests {
     }
 
     #[simd_test(enable = "gfni,avx512bw")]
-    unsafe fn test_mm512_maskz_gf2p8affine_epi64_epi8() {
+    fn test_mm512_maskz_gf2p8affine_epi64_epi8() {
         const CONSTANT_BYTE: i32 = 0x63;
         let (matrices, vectors, _expected) = generate_affine_mul_test_data(CONSTANT_BYTE as u8);
 
         for i in 0..NUM_TEST_WORDS_512 {
-            let matrix = load_m512i_word(&matrices, i);
-            let vector = load_m512i_word(&vectors, i);
+            let matrix = unsafe { load_m512i_word(&matrices, i) };
+            let vector = unsafe { load_m512i_word(&vectors, i) };
             let result_zero =
                 _mm512_maskz_gf2p8affine_epi64_epi8::<CONSTANT_BYTE>(0, vector, matrix);
             assert_eq_m512i(result_zero, _mm512_setzero_si512());
@@ -1104,13 +1104,13 @@ mod tests {
     }
 
     #[simd_test(enable = "gfni,avx512bw")]
-    unsafe fn test_mm512_mask_gf2p8affine_epi64_epi8() {
+    fn test_mm512_mask_gf2p8affine_epi64_epi8() {
         const CONSTANT_BYTE: i32 = 0x63;
         let (matrices, vectors, _expected) = generate_affine_mul_test_data(CONSTANT_BYTE as u8);
 
         for i in 0..NUM_TEST_WORDS_512 {
-            let left = load_m512i_word(&vectors, i);
-            let right = load_m512i_word(&matrices, i);
+            let left = unsafe { load_m512i_word(&vectors, i) };
+            let right = unsafe { load_m512i_word(&matrices, i) };
             let result_left =
                 _mm512_mask_gf2p8affine_epi64_epi8::<CONSTANT_BYTE>(left, 0, left, right);
             assert_eq_m512i(result_left, left);
@@ -1125,7 +1125,7 @@ mod tests {
     }
 
     #[simd_test(enable = "gfni,avx")]
-    unsafe fn test_mm256_gf2p8affine_epi64_epi8() {
+    fn test_mm256_gf2p8affine_epi64_epi8() {
         let identity: i64 = 0x01_02_04_08_10_20_40_80;
         const IDENTITY_BYTE: i32 = 0;
         let constant: i64 = 0;
@@ -1138,20 +1138,20 @@ mod tests {
         let (matrices, vectors, references) = generate_affine_mul_test_data(IDENTITY_BYTE as u8);
 
         for i in 0..NUM_TEST_WORDS_256 {
-            let data = load_m256i_word(&bytes, i);
+            let data = unsafe { load_m256i_word(&bytes, i) };
             let result = _mm256_gf2p8affine_epi64_epi8::<IDENTITY_BYTE>(data, identity);
             assert_eq_m256i(result, data);
             let result = _mm256_gf2p8affine_epi64_epi8::<CONSTANT_BYTE>(data, constant);
             assert_eq_m256i(result, constant_reference);
-            let data = load_m256i_word(&more_bytes, i);
+            let data = unsafe { load_m256i_word(&more_bytes, i) };
             let result = _mm256_gf2p8affine_epi64_epi8::<IDENTITY_BYTE>(data, identity);
             assert_eq_m256i(result, data);
             let result = _mm256_gf2p8affine_epi64_epi8::<CONSTANT_BYTE>(data, constant);
             assert_eq_m256i(result, constant_reference);
 
-            let matrix = load_m256i_word(&matrices, i);
-            let vector = load_m256i_word(&vectors, i);
-            let reference = load_m256i_word(&references, i);
+            let matrix = unsafe { load_m256i_word(&matrices, i) };
+            let vector = unsafe { load_m256i_word(&vectors, i) };
+            let reference = unsafe { load_m256i_word(&references, i) };
 
             let result = _mm256_gf2p8affine_epi64_epi8::<IDENTITY_BYTE>(vector, matrix);
             assert_eq_m256i(result, reference);
@@ -1159,13 +1159,13 @@ mod tests {
     }
 
     #[simd_test(enable = "gfni,avx512bw,avx512vl")]
-    unsafe fn test_mm256_maskz_gf2p8affine_epi64_epi8() {
+    fn test_mm256_maskz_gf2p8affine_epi64_epi8() {
         const CONSTANT_BYTE: i32 = 0x63;
         let (matrices, vectors, _expected) = generate_affine_mul_test_data(CONSTANT_BYTE as u8);
 
         for i in 0..NUM_TEST_WORDS_256 {
-            let matrix = load_m256i_word(&matrices, i);
-            let vector = load_m256i_word(&vectors, i);
+            let matrix = unsafe { load_m256i_word(&matrices, i) };
+            let vector = unsafe { load_m256i_word(&vectors, i) };
             let result_zero =
                 _mm256_maskz_gf2p8affine_epi64_epi8::<CONSTANT_BYTE>(0, vector, matrix);
             assert_eq_m256i(result_zero, _mm256_setzero_si256());
@@ -1181,13 +1181,13 @@ mod tests {
     }
 
     #[simd_test(enable = "gfni,avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_gf2p8affine_epi64_epi8() {
+    fn test_mm256_mask_gf2p8affine_epi64_epi8() {
         const CONSTANT_BYTE: i32 = 0x63;
         let (matrices, vectors, _expected) = generate_affine_mul_test_data(CONSTANT_BYTE as u8);
 
         for i in 0..NUM_TEST_WORDS_256 {
-            let left = load_m256i_word(&vectors, i);
-            let right = load_m256i_word(&matrices, i);
+            let left = unsafe { load_m256i_word(&vectors, i) };
+            let right = unsafe { load_m256i_word(&matrices, i) };
             let result_left =
                 _mm256_mask_gf2p8affine_epi64_epi8::<CONSTANT_BYTE>(left, 0, left, right);
             assert_eq_m256i(result_left, left);
@@ -1202,7 +1202,7 @@ mod tests {
     }
 
     #[simd_test(enable = "gfni")]
-    unsafe fn test_mm_gf2p8affine_epi64_epi8() {
+    fn test_mm_gf2p8affine_epi64_epi8() {
         let identity: i64 = 0x01_02_04_08_10_20_40_80;
         const IDENTITY_BYTE: i32 = 0;
         let constant: i64 = 0;
@@ -1215,20 +1215,20 @@ mod tests {
         let (matrices, vectors, references) = generate_affine_mul_test_data(IDENTITY_BYTE as u8);
 
         for i in 0..NUM_TEST_WORDS_128 {
-            let data = load_m128i_word(&bytes, i);
+            let data = unsafe { load_m128i_word(&bytes, i) };
             let result = _mm_gf2p8affine_epi64_epi8::<IDENTITY_BYTE>(data, identity);
             assert_eq_m128i(result, data);
             let result = _mm_gf2p8affine_epi64_epi8::<CONSTANT_BYTE>(data, constant);
             assert_eq_m128i(result, constant_reference);
-            let data = load_m128i_word(&more_bytes, i);
+            let data = unsafe { load_m128i_word(&more_bytes, i) };
             let result = _mm_gf2p8affine_epi64_epi8::<IDENTITY_BYTE>(data, identity);
             assert_eq_m128i(result, data);
             let result = _mm_gf2p8affine_epi64_epi8::<CONSTANT_BYTE>(data, constant);
             assert_eq_m128i(result, constant_reference);
 
-            let matrix = load_m128i_word(&matrices, i);
-            let vector = load_m128i_word(&vectors, i);
-            let reference = load_m128i_word(&references, i);
+            let matrix = unsafe { load_m128i_word(&matrices, i) };
+            let vector = unsafe { load_m128i_word(&vectors, i) };
+            let reference = unsafe { load_m128i_word(&references, i) };
 
             let result = _mm_gf2p8affine_epi64_epi8::<IDENTITY_BYTE>(vector, matrix);
             assert_eq_m128i(result, reference);
@@ -1236,13 +1236,13 @@ mod tests {
     }
 
     #[simd_test(enable = "gfni,avx512bw,avx512vl")]
-    unsafe fn test_mm_maskz_gf2p8affine_epi64_epi8() {
+    fn test_mm_maskz_gf2p8affine_epi64_epi8() {
         const CONSTANT_BYTE: i32 = 0x63;
         let (matrices, vectors, _expected) = generate_affine_mul_test_data(CONSTANT_BYTE as u8);
 
         for i in 0..NUM_TEST_WORDS_128 {
-            let matrix = load_m128i_word(&matrices, i);
-            let vector = load_m128i_word(&vectors, i);
+            let matrix = unsafe { load_m128i_word(&matrices, i) };
+            let vector = unsafe { load_m128i_word(&vectors, i) };
             let result_zero = _mm_maskz_gf2p8affine_epi64_epi8::<CONSTANT_BYTE>(0, vector, matrix);
             assert_eq_m128i(result_zero, _mm_setzero_si128());
             let mask_bytes: __mmask16 = 0x0F_F0;
@@ -1257,13 +1257,13 @@ mod tests {
     }
 
     #[simd_test(enable = "gfni,avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_gf2p8affine_epi64_epi8() {
+    fn test_mm_mask_gf2p8affine_epi64_epi8() {
         const CONSTANT_BYTE: i32 = 0x63;
         let (matrices, vectors, _expected) = generate_affine_mul_test_data(CONSTANT_BYTE as u8);
 
         for i in 0..NUM_TEST_WORDS_128 {
-            let left = load_m128i_word(&vectors, i);
-            let right = load_m128i_word(&matrices, i);
+            let left = unsafe { load_m128i_word(&vectors, i) };
+            let right = unsafe { load_m128i_word(&matrices, i) };
             let result_left =
                 _mm_mask_gf2p8affine_epi64_epi8::<CONSTANT_BYTE>(left, 0, left, right);
             assert_eq_m128i(result_left, left);
@@ -1278,7 +1278,7 @@ mod tests {
     }
 
     #[simd_test(enable = "gfni,avx512f")]
-    unsafe fn test_mm512_gf2p8affineinv_epi64_epi8() {
+    fn test_mm512_gf2p8affineinv_epi64_epi8() {
         let identity: i64 = 0x01_02_04_08_10_20_40_80;
         const IDENTITY_BYTE: i32 = 0;
         const CONSTANT_BYTE: i32 = 0x63;
@@ -1288,8 +1288,8 @@ mod tests {
         let (inputs, results) = generate_inv_tests_data();
 
         for i in 0..NUM_BYTES_WORDS_512 {
-            let input = load_m512i_word(&inputs, i);
-            let reference = load_m512i_word(&results, i);
+            let input = unsafe { load_m512i_word(&inputs, i) };
+            let reference = unsafe { load_m512i_word(&results, i) };
             let result = _mm512_gf2p8affineinv_epi64_epi8::<IDENTITY_BYTE>(input, identity);
             let remultiplied = _mm512_gf2p8mul_epi8(result, input);
             assert_eq_m512i(remultiplied, reference);
@@ -1300,8 +1300,8 @@ mod tests {
             generate_affine_mul_test_data(CONSTANT_BYTE as u8);
 
         for i in 0..NUM_TEST_WORDS_512 {
-            let vector = load_m512i_word(&vectors, i);
-            let matrix = load_m512i_word(&matrices, i);
+            let vector = unsafe { load_m512i_word(&vectors, i) };
+            let matrix = unsafe { load_m512i_word(&matrices, i) };
 
             let inv_vec = _mm512_gf2p8affineinv_epi64_epi8::<IDENTITY_BYTE>(vector, identity);
             let reference = _mm512_gf2p8affine_epi64_epi8::<CONSTANT_BYTE>(inv_vec, matrix);
@@ -1314,21 +1314,21 @@ mod tests {
         let sbox_matrix = _mm512_set1_epi64(AES_S_BOX_MATRIX);
 
         for i in 0..NUM_BYTES_WORDS_512 {
-            let reference = load_m512i_word(&AES_S_BOX, i);
-            let input = load_m512i_word(&inputs, i);
+            let reference = unsafe { load_m512i_word(&AES_S_BOX, i) };
+            let input = unsafe { load_m512i_word(&inputs, i) };
             let result = _mm512_gf2p8affineinv_epi64_epi8::<CONSTANT_BYTE>(input, sbox_matrix);
             assert_eq_m512i(result, reference);
         }
     }
 
     #[simd_test(enable = "gfni,avx512bw")]
-    unsafe fn test_mm512_maskz_gf2p8affineinv_epi64_epi8() {
+    fn test_mm512_maskz_gf2p8affineinv_epi64_epi8() {
         const CONSTANT_BYTE: i32 = 0x63;
         let (matrices, vectors, _expected) = generate_affine_mul_test_data(CONSTANT_BYTE as u8);
 
         for i in 0..NUM_TEST_WORDS_512 {
-            let matrix = load_m512i_word(&matrices, i);
-            let vector = load_m512i_word(&vectors, i);
+            let matrix = unsafe { load_m512i_word(&matrices, i) };
+            let vector = unsafe { load_m512i_word(&vectors, i) };
             let result_zero =
                 _mm512_maskz_gf2p8affineinv_epi64_epi8::<CONSTANT_BYTE>(0, vector, matrix);
             assert_eq_m512i(result_zero, _mm512_setzero_si512());
@@ -1344,13 +1344,13 @@ mod tests {
     }
 
     #[simd_test(enable = "gfni,avx512bw")]
-    unsafe fn test_mm512_mask_gf2p8affineinv_epi64_epi8() {
+    fn test_mm512_mask_gf2p8affineinv_epi64_epi8() {
         const CONSTANT_BYTE: i32 = 0x63;
         let (matrices, vectors, _expected) = generate_affine_mul_test_data(CONSTANT_BYTE as u8);
 
         for i in 0..NUM_TEST_WORDS_512 {
-            let left = load_m512i_word(&vectors, i);
-            let right = load_m512i_word(&matrices, i);
+            let left = unsafe { load_m512i_word(&vectors, i) };
+            let right = unsafe { load_m512i_word(&matrices, i) };
             let result_left =
                 _mm512_mask_gf2p8affineinv_epi64_epi8::<CONSTANT_BYTE>(left, 0, left, right);
             assert_eq_m512i(result_left, left);
@@ -1366,7 +1366,7 @@ mod tests {
     }
 
     #[simd_test(enable = "gfni,avx")]
-    unsafe fn test_mm256_gf2p8affineinv_epi64_epi8() {
+    fn test_mm256_gf2p8affineinv_epi64_epi8() {
         let identity: i64 = 0x01_02_04_08_10_20_40_80;
         const IDENTITY_BYTE: i32 = 0;
         const CONSTANT_BYTE: i32 = 0x63;
@@ -1376,8 +1376,8 @@ mod tests {
         let (inputs, results) = generate_inv_tests_data();
 
         for i in 0..NUM_BYTES_WORDS_256 {
-            let input = load_m256i_word(&inputs, i);
-            let reference = load_m256i_word(&results, i);
+            let input = unsafe { load_m256i_word(&inputs, i) };
+            let reference = unsafe { load_m256i_word(&results, i) };
             let result = _mm256_gf2p8affineinv_epi64_epi8::<IDENTITY_BYTE>(input, identity);
             let remultiplied = _mm256_gf2p8mul_epi8(result, input);
             assert_eq_m256i(remultiplied, reference);
@@ -1388,8 +1388,8 @@ mod tests {
             generate_affine_mul_test_data(CONSTANT_BYTE as u8);
 
         for i in 0..NUM_TEST_WORDS_256 {
-            let vector = load_m256i_word(&vectors, i);
-            let matrix = load_m256i_word(&matrices, i);
+            let vector = unsafe { load_m256i_word(&vectors, i) };
+            let matrix = unsafe { load_m256i_word(&matrices, i) };
 
             let inv_vec = _mm256_gf2p8affineinv_epi64_epi8::<IDENTITY_BYTE>(vector, identity);
             let reference = _mm256_gf2p8affine_epi64_epi8::<CONSTANT_BYTE>(inv_vec, matrix);
@@ -1402,21 +1402,21 @@ mod tests {
         let sbox_matrix = _mm256_set1_epi64x(AES_S_BOX_MATRIX);
 
         for i in 0..NUM_BYTES_WORDS_256 {
-            let reference = load_m256i_word(&AES_S_BOX, i);
-            let input = load_m256i_word(&inputs, i);
+            let reference = unsafe { load_m256i_word(&AES_S_BOX, i) };
+            let input = unsafe { load_m256i_word(&inputs, i) };
             let result = _mm256_gf2p8affineinv_epi64_epi8::<CONSTANT_BYTE>(input, sbox_matrix);
             assert_eq_m256i(result, reference);
         }
     }
 
     #[simd_test(enable = "gfni,avx512bw,avx512vl")]
-    unsafe fn test_mm256_maskz_gf2p8affineinv_epi64_epi8() {
+    fn test_mm256_maskz_gf2p8affineinv_epi64_epi8() {
         const CONSTANT_BYTE: i32 = 0x63;
         let (matrices, vectors, _expected) = generate_affine_mul_test_data(CONSTANT_BYTE as u8);
 
         for i in 0..NUM_TEST_WORDS_256 {
-            let matrix = load_m256i_word(&matrices, i);
-            let vector = load_m256i_word(&vectors, i);
+            let matrix = unsafe { load_m256i_word(&matrices, i) };
+            let vector = unsafe { load_m256i_word(&vectors, i) };
             let result_zero =
                 _mm256_maskz_gf2p8affineinv_epi64_epi8::<CONSTANT_BYTE>(0, vector, matrix);
             assert_eq_m256i(result_zero, _mm256_setzero_si256());
@@ -1432,13 +1432,13 @@ mod tests {
     }
 
     #[simd_test(enable = "gfni,avx512bw,avx512vl")]
-    unsafe fn test_mm256_mask_gf2p8affineinv_epi64_epi8() {
+    fn test_mm256_mask_gf2p8affineinv_epi64_epi8() {
         const CONSTANT_BYTE: i32 = 0x63;
         let (matrices, vectors, _expected) = generate_affine_mul_test_data(CONSTANT_BYTE as u8);
 
         for i in 0..NUM_TEST_WORDS_256 {
-            let left = load_m256i_word(&vectors, i);
-            let right = load_m256i_word(&matrices, i);
+            let left = unsafe { load_m256i_word(&vectors, i) };
+            let right = unsafe { load_m256i_word(&matrices, i) };
             let result_left =
                 _mm256_mask_gf2p8affineinv_epi64_epi8::<CONSTANT_BYTE>(left, 0, left, right);
             assert_eq_m256i(result_left, left);
@@ -1454,7 +1454,7 @@ mod tests {
     }
 
     #[simd_test(enable = "gfni")]
-    unsafe fn test_mm_gf2p8affineinv_epi64_epi8() {
+    fn test_mm_gf2p8affineinv_epi64_epi8() {
         let identity: i64 = 0x01_02_04_08_10_20_40_80;
         const IDENTITY_BYTE: i32 = 0;
         const CONSTANT_BYTE: i32 = 0x63;
@@ -1464,8 +1464,8 @@ mod tests {
         let (inputs, results) = generate_inv_tests_data();
 
         for i in 0..NUM_BYTES_WORDS_128 {
-            let input = load_m128i_word(&inputs, i);
-            let reference = load_m128i_word(&results, i);
+            let input = unsafe { load_m128i_word(&inputs, i) };
+            let reference = unsafe { load_m128i_word(&results, i) };
             let result = _mm_gf2p8affineinv_epi64_epi8::<IDENTITY_BYTE>(input, identity);
             let remultiplied = _mm_gf2p8mul_epi8(result, input);
             assert_eq_m128i(remultiplied, reference);
@@ -1476,8 +1476,8 @@ mod tests {
             generate_affine_mul_test_data(CONSTANT_BYTE as u8);
 
         for i in 0..NUM_TEST_WORDS_128 {
-            let vector = load_m128i_word(&vectors, i);
-            let matrix = load_m128i_word(&matrices, i);
+            let vector = unsafe { load_m128i_word(&vectors, i) };
+            let matrix = unsafe { load_m128i_word(&matrices, i) };
 
             let inv_vec = _mm_gf2p8affineinv_epi64_epi8::<IDENTITY_BYTE>(vector, identity);
             let reference = _mm_gf2p8affine_epi64_epi8::<CONSTANT_BYTE>(inv_vec, matrix);
@@ -1490,21 +1490,21 @@ mod tests {
         let sbox_matrix = _mm_set1_epi64x(AES_S_BOX_MATRIX);
 
         for i in 0..NUM_BYTES_WORDS_128 {
-            let reference = load_m128i_word(&AES_S_BOX, i);
-            let input = load_m128i_word(&inputs, i);
+            let reference = unsafe { load_m128i_word(&AES_S_BOX, i) };
+            let input = unsafe { load_m128i_word(&inputs, i) };
             let result = _mm_gf2p8affineinv_epi64_epi8::<CONSTANT_BYTE>(input, sbox_matrix);
             assert_eq_m128i(result, reference);
         }
     }
 
     #[simd_test(enable = "gfni,avx512bw,avx512vl")]
-    unsafe fn test_mm_maskz_gf2p8affineinv_epi64_epi8() {
+    fn test_mm_maskz_gf2p8affineinv_epi64_epi8() {
         const CONSTANT_BYTE: i32 = 0x63;
         let (matrices, vectors, _expected) = generate_affine_mul_test_data(CONSTANT_BYTE as u8);
 
         for i in 0..NUM_TEST_WORDS_128 {
-            let matrix = load_m128i_word(&matrices, i);
-            let vector = load_m128i_word(&vectors, i);
+            let matrix = unsafe { load_m128i_word(&matrices, i) };
+            let vector = unsafe { load_m128i_word(&vectors, i) };
             let result_zero =
                 _mm_maskz_gf2p8affineinv_epi64_epi8::<CONSTANT_BYTE>(0, vector, matrix);
             assert_eq_m128i(result_zero, _mm_setzero_si128());
@@ -1520,13 +1520,13 @@ mod tests {
     }
 
     #[simd_test(enable = "gfni,avx512bw,avx512vl")]
-    unsafe fn test_mm_mask_gf2p8affineinv_epi64_epi8() {
+    fn test_mm_mask_gf2p8affineinv_epi64_epi8() {
         const CONSTANT_BYTE: i32 = 0x63;
         let (matrices, vectors, _expected) = generate_affine_mul_test_data(CONSTANT_BYTE as u8);
 
         for i in 0..NUM_TEST_WORDS_128 {
-            let left = load_m128i_word(&vectors, i);
-            let right = load_m128i_word(&matrices, i);
+            let left = unsafe { load_m128i_word(&vectors, i) };
+            let right = unsafe { load_m128i_word(&matrices, i) };
             let result_left =
                 _mm_mask_gf2p8affineinv_epi64_epi8::<CONSTANT_BYTE>(left, 0, left, right);
             assert_eq_m128i(result_left, left);
diff --git a/library/stdarch/crates/core_arch/src/x86/kl.rs b/library/stdarch/crates/core_arch/src/x86/kl.rs
index 26e5a46c6293..7cb52847f50d 100644
--- a/library/stdarch/crates/core_arch/src/x86/kl.rs
+++ b/library/stdarch/crates/core_arch/src/x86/kl.rs
@@ -352,45 +352,47 @@ mod tests {
     use stdarch_test::simd_test;
 
     #[target_feature(enable = "kl")]
-    unsafe fn encodekey128() -> [u8; 48] {
+    fn encodekey128() -> [u8; 48] {
         let mut handle = [0; 48];
-        let _ = _mm_encodekey128_u32(0, _mm_setzero_si128(), handle.as_mut_ptr());
+        let _ = unsafe { _mm_encodekey128_u32(0, _mm_setzero_si128(), handle.as_mut_ptr()) };
         handle
     }
 
     #[target_feature(enable = "kl")]
-    unsafe fn encodekey256() -> [u8; 64] {
+    fn encodekey256() -> [u8; 64] {
         let mut handle = [0; 64];
-        let _ = _mm_encodekey256_u32(
-            0,
-            _mm_setzero_si128(),
-            _mm_setzero_si128(),
-            handle.as_mut_ptr(),
-        );
+        let _ = unsafe {
+            _mm_encodekey256_u32(
+                0,
+                _mm_setzero_si128(),
+                _mm_setzero_si128(),
+                handle.as_mut_ptr(),
+            )
+        };
         handle
     }
 
     #[simd_test(enable = "kl")]
-    unsafe fn test_mm_encodekey128_u32() {
+    fn test_mm_encodekey128_u32() {
         encodekey128();
     }
 
     #[simd_test(enable = "kl")]
-    unsafe fn test_mm_encodekey256_u32() {
+    fn test_mm_encodekey256_u32() {
         encodekey256();
     }
 
     #[simd_test(enable = "kl")]
-    unsafe fn test_mm_aesenc128kl_u8() {
+    fn test_mm_aesenc128kl_u8() {
         let mut buffer = _mm_setzero_si128();
         let key = encodekey128();
 
         for _ in 0..100 {
-            let status = _mm_aesenc128kl_u8(&mut buffer, buffer, key.as_ptr());
+            let status = unsafe { _mm_aesenc128kl_u8(&mut buffer, buffer, key.as_ptr()) };
             assert_eq!(status, 0);
         }
         for _ in 0..100 {
-            let status = _mm_aesdec128kl_u8(&mut buffer, buffer, key.as_ptr());
+            let status = unsafe { _mm_aesdec128kl_u8(&mut buffer, buffer, key.as_ptr()) };
             assert_eq!(status, 0);
         }
 
@@ -398,16 +400,16 @@ mod tests {
     }
 
     #[simd_test(enable = "kl")]
-    unsafe fn test_mm_aesdec128kl_u8() {
+    fn test_mm_aesdec128kl_u8() {
         let mut buffer = _mm_setzero_si128();
         let key = encodekey128();
 
         for _ in 0..100 {
-            let status = _mm_aesdec128kl_u8(&mut buffer, buffer, key.as_ptr());
+            let status = unsafe { _mm_aesdec128kl_u8(&mut buffer, buffer, key.as_ptr()) };
             assert_eq!(status, 0);
         }
         for _ in 0..100 {
-            let status = _mm_aesenc128kl_u8(&mut buffer, buffer, key.as_ptr());
+            let status = unsafe { _mm_aesenc128kl_u8(&mut buffer, buffer, key.as_ptr()) };
             assert_eq!(status, 0);
         }
 
@@ -415,16 +417,16 @@ mod tests {
     }
 
     #[simd_test(enable = "kl")]
-    unsafe fn test_mm_aesenc256kl_u8() {
+    fn test_mm_aesenc256kl_u8() {
         let mut buffer = _mm_setzero_si128();
         let key = encodekey256();
 
         for _ in 0..100 {
-            let status = _mm_aesenc256kl_u8(&mut buffer, buffer, key.as_ptr());
+            let status = unsafe { _mm_aesenc256kl_u8(&mut buffer, buffer, key.as_ptr()) };
             assert_eq!(status, 0);
         }
         for _ in 0..100 {
-            let status = _mm_aesdec256kl_u8(&mut buffer, buffer, key.as_ptr());
+            let status = unsafe { _mm_aesdec256kl_u8(&mut buffer, buffer, key.as_ptr()) };
             assert_eq!(status, 0);
         }
 
@@ -432,16 +434,16 @@ mod tests {
     }
 
     #[simd_test(enable = "kl")]
-    unsafe fn test_mm_aesdec256kl_u8() {
+    fn test_mm_aesdec256kl_u8() {
         let mut buffer = _mm_setzero_si128();
         let key = encodekey256();
 
         for _ in 0..100 {
-            let status = _mm_aesdec256kl_u8(&mut buffer, buffer, key.as_ptr());
+            let status = unsafe { _mm_aesdec256kl_u8(&mut buffer, buffer, key.as_ptr()) };
             assert_eq!(status, 0);
         }
         for _ in 0..100 {
-            let status = _mm_aesenc256kl_u8(&mut buffer, buffer, key.as_ptr());
+            let status = unsafe { _mm_aesenc256kl_u8(&mut buffer, buffer, key.as_ptr()) };
             assert_eq!(status, 0);
         }
 
@@ -449,16 +451,20 @@ mod tests {
     }
 
     #[simd_test(enable = "widekl")]
-    unsafe fn test_mm_aesencwide128kl_u8() {
+    fn test_mm_aesencwide128kl_u8() {
         let mut buffer = [_mm_setzero_si128(); 8];
         let key = encodekey128();
 
         for _ in 0..100 {
-            let status = _mm_aesencwide128kl_u8(buffer.as_mut_ptr(), buffer.as_ptr(), key.as_ptr());
+            let status = unsafe {
+                _mm_aesencwide128kl_u8(buffer.as_mut_ptr(), buffer.as_ptr(), key.as_ptr())
+            };
             assert_eq!(status, 0);
         }
         for _ in 0..100 {
-            let status = _mm_aesdecwide128kl_u8(buffer.as_mut_ptr(), buffer.as_ptr(), key.as_ptr());
+            let status = unsafe {
+                _mm_aesdecwide128kl_u8(buffer.as_mut_ptr(), buffer.as_ptr(), key.as_ptr())
+            };
             assert_eq!(status, 0);
         }
 
@@ -468,16 +474,20 @@ mod tests {
     }
 
     #[simd_test(enable = "widekl")]
-    unsafe fn test_mm_aesdecwide128kl_u8() {
+    fn test_mm_aesdecwide128kl_u8() {
         let mut buffer = [_mm_setzero_si128(); 8];
         let key = encodekey128();
 
         for _ in 0..100 {
-            let status = _mm_aesdecwide128kl_u8(buffer.as_mut_ptr(), buffer.as_ptr(), key.as_ptr());
+            let status = unsafe {
+                _mm_aesdecwide128kl_u8(buffer.as_mut_ptr(), buffer.as_ptr(), key.as_ptr())
+            };
             assert_eq!(status, 0);
         }
         for _ in 0..100 {
-            let status = _mm_aesencwide128kl_u8(buffer.as_mut_ptr(), buffer.as_ptr(), key.as_ptr());
+            let status = unsafe {
+                _mm_aesencwide128kl_u8(buffer.as_mut_ptr(), buffer.as_ptr(), key.as_ptr())
+            };
             assert_eq!(status, 0);
         }
 
@@ -487,16 +497,20 @@ mod tests {
     }
 
     #[simd_test(enable = "widekl")]
-    unsafe fn test_mm_aesencwide256kl_u8() {
+    fn test_mm_aesencwide256kl_u8() {
         let mut buffer = [_mm_setzero_si128(); 8];
         let key = encodekey256();
 
         for _ in 0..100 {
-            let status = _mm_aesencwide256kl_u8(buffer.as_mut_ptr(), buffer.as_ptr(), key.as_ptr());
+            let status = unsafe {
+                _mm_aesencwide256kl_u8(buffer.as_mut_ptr(), buffer.as_ptr(), key.as_ptr())
+            };
             assert_eq!(status, 0);
         }
         for _ in 0..100 {
-            let status = _mm_aesdecwide256kl_u8(buffer.as_mut_ptr(), buffer.as_ptr(), key.as_ptr());
+            let status = unsafe {
+                _mm_aesdecwide256kl_u8(buffer.as_mut_ptr(), buffer.as_ptr(), key.as_ptr())
+            };
             assert_eq!(status, 0);
         }
 
@@ -506,16 +520,20 @@ mod tests {
     }
 
     #[simd_test(enable = "widekl")]
-    unsafe fn test_mm_aesdecwide256kl_u8() {
+    fn test_mm_aesdecwide256kl_u8() {
         let mut buffer = [_mm_setzero_si128(); 8];
         let key = encodekey256();
 
         for _ in 0..100 {
-            let status = _mm_aesdecwide256kl_u8(buffer.as_mut_ptr(), buffer.as_ptr(), key.as_ptr());
+            let status = unsafe {
+                _mm_aesdecwide256kl_u8(buffer.as_mut_ptr(), buffer.as_ptr(), key.as_ptr())
+            };
             assert_eq!(status, 0);
         }
         for _ in 0..100 {
-            let status = _mm_aesencwide256kl_u8(buffer.as_mut_ptr(), buffer.as_ptr(), key.as_ptr());
+            let status = unsafe {
+                _mm_aesencwide256kl_u8(buffer.as_mut_ptr(), buffer.as_ptr(), key.as_ptr())
+            };
             assert_eq!(status, 0);
         }
 
diff --git a/library/stdarch/crates/core_arch/src/x86/rtm.rs b/library/stdarch/crates/core_arch/src/x86/rtm.rs
index b37e7571eb8f..c88bd6592d78 100644
--- a/library/stdarch/crates/core_arch/src/x86/rtm.rs
+++ b/library/stdarch/crates/core_arch/src/x86/rtm.rs
@@ -120,13 +120,15 @@ mod tests {
     use crate::core_arch::x86::*;
 
     #[simd_test(enable = "rtm")]
-    unsafe fn test_xbegin() {
+    fn test_xbegin() {
         let mut x = 0;
         for _ in 0..10 {
-            let code = _xbegin();
+            let code = unsafe { _xbegin() };
             if code == _XBEGIN_STARTED {
                 x += 1;
-                _xend();
+                unsafe {
+                    _xend();
+                }
                 assert_eq!(x, 1);
                 break;
             }
@@ -135,19 +137,23 @@ mod tests {
     }
 
     #[simd_test(enable = "rtm")]
-    unsafe fn test_xabort() {
+    fn test_xabort() {
         const ABORT_CODE: u32 = 42;
         // aborting outside a transactional region does nothing
-        _xabort::<ABORT_CODE>();
+        unsafe {
+            _xabort::<ABORT_CODE>();
+        }
 
         for _ in 0..10 {
             let mut x = 0;
-            let code = rtm::_xbegin();
+            let code = unsafe { _xbegin() };
             if code == _XBEGIN_STARTED {
                 x += 1;
-                rtm::_xabort::<ABORT_CODE>();
+                unsafe {
+                    _xabort::<ABORT_CODE>();
+                }
             } else if code & _XABORT_EXPLICIT != 0 {
-                let test_abort_code = rtm::_xabort_code(code);
+                let test_abort_code = _xabort_code(code);
                 assert_eq!(test_abort_code, ABORT_CODE);
             }
             assert_eq!(x, 0);
@@ -155,14 +161,16 @@ mod tests {
     }
 
     #[simd_test(enable = "rtm")]
-    unsafe fn test_xtest() {
-        assert_eq!(_xtest(), 0);
+    fn test_xtest() {
+        assert_eq!(unsafe { _xtest() }, 0);
 
         for _ in 0..10 {
-            let code = rtm::_xbegin();
+            let code = unsafe { _xbegin() };
             if code == _XBEGIN_STARTED {
-                let in_tx = _xtest();
-                rtm::_xend();
+                let in_tx = unsafe { _xtest() };
+                unsafe {
+                    _xend();
+                }
 
                 // putting the assert inside the transaction would abort the transaction on fail
                 // without any output/panic/etc
diff --git a/library/stdarch/crates/core_arch/src/x86/sse.rs b/library/stdarch/crates/core_arch/src/x86/sse.rs
index f167e8381d27..1812721db4d3 100644
--- a/library/stdarch/crates/core_arch/src/x86/sse.rs
+++ b/library/stdarch/crates/core_arch/src/x86/sse.rs
@@ -3147,21 +3147,21 @@ mod tests {
     }
 
     #[simd_test(enable = "sse")]
-    const unsafe fn test_mm_load_ss() {
+    const fn test_mm_load_ss() {
         let a = 42.0f32;
-        let r = _mm_load_ss(ptr::addr_of!(a));
+        let r = unsafe { _mm_load_ss(ptr::addr_of!(a)) };
         assert_eq_m128(r, _mm_setr_ps(42.0, 0.0, 0.0, 0.0));
     }
 
     #[simd_test(enable = "sse")]
-    const unsafe fn test_mm_load1_ps() {
+    const fn test_mm_load1_ps() {
         let a = 42.0f32;
-        let r = _mm_load1_ps(ptr::addr_of!(a));
+        let r = unsafe { _mm_load1_ps(ptr::addr_of!(a)) };
         assert_eq_m128(r, _mm_setr_ps(42.0, 42.0, 42.0, 42.0));
     }
 
     #[simd_test(enable = "sse")]
-    const unsafe fn test_mm_load_ps() {
+    const fn test_mm_load_ps() {
         let vals = Memory {
             data: [1.0f32, 2.0, 3.0, 4.0],
         };
@@ -3169,21 +3169,21 @@ mod tests {
         // guaranteed to be aligned to 16 bytes
         let p = vals.data.as_ptr();
 
-        let r = _mm_load_ps(p);
+        let r = unsafe { _mm_load_ps(p) };
         let e = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
         assert_eq_m128(r, e);
     }
 
     #[simd_test(enable = "sse")]
-    const unsafe fn test_mm_loadu_ps() {
+    const fn test_mm_loadu_ps() {
         let vals = &[1.0f32, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0];
-        let p = vals.as_ptr().add(3);
-        let r = _mm_loadu_ps(black_box(p));
+        let p = unsafe { vals.as_ptr().add(3) };
+        let r = unsafe { _mm_loadu_ps(black_box(p)) };
         assert_eq_m128(r, _mm_setr_ps(4.0, 5.0, 6.0, 7.0));
     }
 
     #[simd_test(enable = "sse")]
-    const unsafe fn test_mm_loadr_ps() {
+    const fn test_mm_loadr_ps() {
         let vals = Memory {
             data: [1.0f32, 2.0, 3.0, 4.0],
         };
@@ -3191,16 +3191,18 @@ mod tests {
         // guaranteed to be aligned to 16 bytes
         let p = vals.data.as_ptr();
 
-        let r = _mm_loadr_ps(p);
+        let r = unsafe { _mm_loadr_ps(p) };
         let e = _mm_setr_ps(4.0, 3.0, 2.0, 1.0);
         assert_eq_m128(r, e);
     }
 
     #[simd_test(enable = "sse")]
-    const unsafe fn test_mm_store_ss() {
+    const fn test_mm_store_ss() {
         let mut vals = [0.0f32; 8];
         let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
-        _mm_store_ss(vals.as_mut_ptr().add(1), a);
+        unsafe {
+            _mm_store_ss(vals.as_mut_ptr().add(1), a);
+        }
 
         assert_eq!(vals[0], 0.0);
         assert_eq!(vals[1], 1.0);
@@ -3208,46 +3210,52 @@ mod tests {
     }
 
     #[simd_test(enable = "sse")]
-    const unsafe fn test_mm_store1_ps() {
+    const fn test_mm_store1_ps() {
         let mut vals = Memory { data: [0.0f32; 4] };
         let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
 
         // guaranteed to be aligned to 16 bytes
         let p = vals.data.as_mut_ptr();
 
-        _mm_store1_ps(p, *black_box(&a));
+        unsafe {
+            _mm_store1_ps(p, *black_box(&a));
+        }
 
         assert_eq!(vals.data, [1.0, 1.0, 1.0, 1.0]);
     }
 
     #[simd_test(enable = "sse")]
-    const unsafe fn test_mm_store_ps() {
+    const fn test_mm_store_ps() {
         let mut vals = Memory { data: [0.0f32; 4] };
         let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
 
         // guaranteed to be aligned to 16 bytes
         let p = vals.data.as_mut_ptr();
 
-        _mm_store_ps(p, *black_box(&a));
+        unsafe {
+            _mm_store_ps(p, *black_box(&a));
+        }
 
         assert_eq!(vals.data, [1.0, 2.0, 3.0, 4.0]);
     }
 
     #[simd_test(enable = "sse")]
-    const unsafe fn test_mm_storer_ps() {
+    const fn test_mm_storer_ps() {
         let mut vals = Memory { data: [0.0f32; 4] };
         let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
 
         // guaranteed to be aligned to 16 bytes
         let p = vals.data.as_mut_ptr();
 
-        _mm_storer_ps(p, *black_box(&a));
+        unsafe {
+            _mm_storer_ps(p, *black_box(&a));
+        }
 
         assert_eq!(vals.data, [4.0, 3.0, 2.0, 1.0]);
     }
 
     #[simd_test(enable = "sse")]
-    const unsafe fn test_mm_storeu_ps() {
+    const fn test_mm_storeu_ps() {
         #[repr(align(16))]
         struct Memory8 {
             data: [f32; 8],
@@ -3258,9 +3266,11 @@ mod tests {
         let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
 
         // guaranteed to be *not* aligned to 16 bytes
-        let p = vals.data.as_mut_ptr().offset(1);
+        let p = unsafe { vals.data.as_mut_ptr().offset(1) };
 
-        _mm_storeu_ps(p, *black_box(&a));
+        unsafe {
+            _mm_storeu_ps(p, *black_box(&a));
+        }
 
         assert_eq!(vals.data, [0.0, 1.0, 2.0, 3.0, 4.0, 0.0, 0.0, 0.0]);
     }
@@ -3315,11 +3325,13 @@ mod tests {
     // Miri cannot support this until it is clear how it fits in the Rust memory model
     // (non-temporal store)
     #[cfg_attr(miri, ignore)]
-    unsafe fn test_mm_stream_ps() {
+    fn test_mm_stream_ps() {
         let a = _mm_set1_ps(7.0);
         let mut mem = Memory { data: [-1.0; 4] };
 
-        _mm_stream_ps(ptr::addr_of_mut!(mem.data[0]), a);
+        unsafe {
+            _mm_stream_ps(ptr::addr_of_mut!(mem.data[0]), a);
+        }
         _mm_sfence();
         for i in 0..4 {
             assert_eq!(mem.data[i], get_m128(a, i));
diff --git a/library/stdarch/crates/core_arch/src/x86/sse2.rs b/library/stdarch/crates/core_arch/src/x86/sse2.rs
index fc010e8467bb..c58e1b86a470 100644
--- a/library/stdarch/crates/core_arch/src/x86/sse2.rs
+++ b/library/stdarch/crates/core_arch/src/x86/sse2.rs
@@ -3291,9 +3291,11 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_clflush() {
+    fn test_mm_clflush() {
         let x = 0_u8;
-        _mm_clflush(ptr::addr_of!(x));
+        unsafe {
+            _mm_clflush(ptr::addr_of!(x));
+        }
     }
 
     #[simd_test(enable = "sse2")]
@@ -3725,7 +3727,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_sll_epi16() {
+    fn test_mm_sll_epi16() {
         let a = _mm_setr_epi16(0xCC, -0xCC, 0xDD, -0xDD, 0xEE, -0xEE, 0xFF, -0xFF);
         let r = _mm_sll_epi16(a, _mm_set_epi64x(0, 4));
         assert_eq_m128i(
@@ -4071,7 +4073,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn test_mm_cvtps_epi32() {
+    fn test_mm_cvtps_epi32() {
         let a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0);
         let r = _mm_cvtps_epi32(a);
         assert_eq_m128i(r, _mm_setr_epi32(1, 2, 3, 4));
@@ -4178,23 +4180,23 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_loadl_epi64() {
+    const fn test_mm_loadl_epi64() {
         let a = _mm_setr_epi64x(6, 5);
-        let r = _mm_loadl_epi64(ptr::addr_of!(a));
+        let r = unsafe { _mm_loadl_epi64(ptr::addr_of!(a)) };
         assert_eq_m128i(r, _mm_setr_epi64x(6, 0));
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_load_si128() {
+    const fn test_mm_load_si128() {
         let a = _mm_set_epi64x(5, 6);
-        let r = _mm_load_si128(ptr::addr_of!(a) as *const _);
+        let r = unsafe { _mm_load_si128(ptr::addr_of!(a) as *const _) };
         assert_eq_m128i(a, r);
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_loadu_si128() {
+    const fn test_mm_loadu_si128() {
         let a = _mm_set_epi64x(5, 6);
-        let r = _mm_loadu_si128(ptr::addr_of!(a) as *const _);
+        let r = unsafe { _mm_loadu_si128(ptr::addr_of!(a) as *const _) };
         assert_eq_m128i(a, r);
     }
 
@@ -4202,7 +4204,7 @@ mod tests {
     // Miri cannot support this until it is clear how it fits in the Rust memory model
     // (non-temporal store)
     #[cfg_attr(miri, ignore)]
-    unsafe fn test_mm_maskmoveu_si128() {
+    fn test_mm_maskmoveu_si128() {
         let a = _mm_set1_epi8(9);
         #[rustfmt::skip]
         let mask = _mm_set_epi8(
@@ -4210,33 +4212,41 @@ mod tests {
             0, 0, 0, 0, 0, 0, 0, 0,
         );
         let mut r = _mm_set1_epi8(0);
-        _mm_maskmoveu_si128(a, mask, ptr::addr_of_mut!(r) as *mut i8);
+        unsafe {
+            _mm_maskmoveu_si128(a, mask, ptr::addr_of_mut!(r) as *mut i8);
+        }
         _mm_sfence();
         let e = _mm_set_epi8(0, 0, 9, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_store_si128() {
+    const fn test_mm_store_si128() {
         let a = _mm_set1_epi8(9);
         let mut r = _mm_set1_epi8(0);
-        _mm_store_si128(&mut r, a);
+        unsafe {
+            _mm_store_si128(&mut r, a);
+        }
         assert_eq_m128i(r, a);
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_storeu_si128() {
+    const fn test_mm_storeu_si128() {
         let a = _mm_set1_epi8(9);
         let mut r = _mm_set1_epi8(0);
-        _mm_storeu_si128(&mut r, a);
+        unsafe {
+            _mm_storeu_si128(&mut r, a);
+        }
         assert_eq_m128i(r, a);
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_storel_epi64() {
+    const fn test_mm_storel_epi64() {
         let a = _mm_setr_epi64x(2, 9);
         let mut r = _mm_set1_epi8(0);
-        _mm_storel_epi64(&mut r, a);
+        unsafe {
+            _mm_storel_epi64(&mut r, a);
+        }
         assert_eq_m128i(r, _mm_setr_epi64x(2, 0));
     }
 
@@ -4244,10 +4254,12 @@ mod tests {
     // Miri cannot support this until it is clear how it fits in the Rust memory model
     // (non-temporal store)
     #[cfg_attr(miri, ignore)]
-    unsafe fn test_mm_stream_si128() {
+    fn test_mm_stream_si128() {
         let a = _mm_setr_epi32(1, 2, 3, 4);
         let mut r = _mm_undefined_si128();
-        _mm_stream_si128(ptr::addr_of_mut!(r), a);
+        unsafe {
+            _mm_stream_si128(ptr::addr_of_mut!(r), a);
+        }
         _mm_sfence();
         assert_eq_m128i(r, a);
     }
@@ -4256,10 +4268,12 @@ mod tests {
     // Miri cannot support this until it is clear how it fits in the Rust memory model
     // (non-temporal store)
     #[cfg_attr(miri, ignore)]
-    unsafe fn test_mm_stream_si32() {
+    fn test_mm_stream_si32() {
         let a: i32 = 7;
         let mut mem = boxed::Box::<i32>::new(-1);
-        _mm_stream_si32(ptr::addr_of_mut!(*mem), a);
+        unsafe {
+            _mm_stream_si32(ptr::addr_of_mut!(*mem), a);
+        }
         _mm_sfence();
         assert_eq!(a, *mem);
     }
@@ -4909,40 +4923,40 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_load_pd() {
+    const fn test_mm_load_pd() {
         let mem = Memory {
             data: [1.0f64, 2.0, 3.0, 4.0],
         };
         let vals = &mem.data;
         let d = vals.as_ptr();
 
-        let r = _mm_load_pd(d);
+        let r = unsafe { _mm_load_pd(d) };
         assert_eq_m128d(r, _mm_setr_pd(1.0, 2.0));
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_load_sd() {
+    const fn test_mm_load_sd() {
         let a = 1.;
         let expected = _mm_setr_pd(a, 0.);
-        let r = _mm_load_sd(&a);
+        let r = unsafe { _mm_load_sd(&a) };
         assert_eq_m128d(r, expected);
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_loadh_pd() {
+    const fn test_mm_loadh_pd() {
         let a = _mm_setr_pd(1., 2.);
         let b = 3.;
         let expected = _mm_setr_pd(_mm_cvtsd_f64(a), 3.);
-        let r = _mm_loadh_pd(a, &b);
+        let r = unsafe { _mm_loadh_pd(a, &b) };
         assert_eq_m128d(r, expected);
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_loadl_pd() {
+    const fn test_mm_loadl_pd() {
         let a = _mm_setr_pd(1., 2.);
         let b = 3.;
         let expected = _mm_setr_pd(3., get_m128d(a, 1));
-        let r = _mm_loadl_pd(a, &b);
+        let r = unsafe { _mm_loadl_pd(a, &b) };
         assert_eq_m128d(r, expected);
     }
 
@@ -4950,7 +4964,7 @@ mod tests {
     // Miri cannot support this until it is clear how it fits in the Rust memory model
     // (non-temporal store)
     #[cfg_attr(miri, ignore)]
-    unsafe fn test_mm_stream_pd() {
+    fn test_mm_stream_pd() {
         #[repr(align(128))]
         struct Memory {
             pub data: [f64; 2],
@@ -4958,7 +4972,9 @@ mod tests {
         let a = _mm_set1_pd(7.0);
         let mut mem = Memory { data: [-1.0; 2] };
 
-        _mm_stream_pd(ptr::addr_of_mut!(mem.data[0]), a);
+        unsafe {
+            _mm_stream_pd(ptr::addr_of_mut!(mem.data[0]), a);
+        }
         _mm_sfence();
         for i in 0..2 {
             assert_eq!(mem.data[i], get_m128d(a, i));
@@ -4966,132 +4982,154 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_store_sd() {
+    const fn test_mm_store_sd() {
         let mut dest = 0.;
         let a = _mm_setr_pd(1., 2.);
-        _mm_store_sd(&mut dest, a);
+        unsafe {
+            _mm_store_sd(&mut dest, a);
+        }
         assert_eq!(dest, _mm_cvtsd_f64(a));
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_store_pd() {
+    const fn test_mm_store_pd() {
         let mut mem = Memory { data: [0.0f64; 4] };
         let vals = &mut mem.data;
         let a = _mm_setr_pd(1.0, 2.0);
         let d = vals.as_mut_ptr();
 
-        _mm_store_pd(d, *black_box(&a));
+        unsafe {
+            _mm_store_pd(d, *black_box(&a));
+        }
         assert_eq!(vals[0], 1.0);
         assert_eq!(vals[1], 2.0);
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_storeu_pd() {
+    const fn test_mm_storeu_pd() {
         // guaranteed to be aligned to 16 bytes
         let mut mem = Memory { data: [0.0f64; 4] };
         let vals = &mut mem.data;
         let a = _mm_setr_pd(1.0, 2.0);
 
         // so p is *not* aligned to 16 bytes
-        let p = vals.as_mut_ptr().offset(1);
-        _mm_storeu_pd(p, *black_box(&a));
+        unsafe {
+            let p = vals.as_mut_ptr().offset(1);
+            _mm_storeu_pd(p, *black_box(&a));
+        }
 
         assert_eq!(*vals, [0.0, 1.0, 2.0, 0.0]);
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_storeu_si16() {
+    const fn test_mm_storeu_si16() {
         let a = _mm_setr_epi16(1, 2, 3, 4, 5, 6, 7, 8);
         let mut r = _mm_setr_epi16(9, 10, 11, 12, 13, 14, 15, 16);
-        _mm_storeu_si16(ptr::addr_of_mut!(r).cast(), a);
+        unsafe {
+            _mm_storeu_si16(ptr::addr_of_mut!(r).cast(), a);
+        }
         let e = _mm_setr_epi16(1, 10, 11, 12, 13, 14, 15, 16);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_storeu_si32() {
+    const fn test_mm_storeu_si32() {
         let a = _mm_setr_epi32(1, 2, 3, 4);
         let mut r = _mm_setr_epi32(5, 6, 7, 8);
-        _mm_storeu_si32(ptr::addr_of_mut!(r).cast(), a);
+        unsafe {
+            _mm_storeu_si32(ptr::addr_of_mut!(r).cast(), a);
+        }
         let e = _mm_setr_epi32(1, 6, 7, 8);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_storeu_si64() {
+    const fn test_mm_storeu_si64() {
         let a = _mm_setr_epi64x(1, 2);
         let mut r = _mm_setr_epi64x(3, 4);
-        _mm_storeu_si64(ptr::addr_of_mut!(r).cast(), a);
+        unsafe {
+            _mm_storeu_si64(ptr::addr_of_mut!(r).cast(), a);
+        }
         let e = _mm_setr_epi64x(1, 4);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_store1_pd() {
+    const fn test_mm_store1_pd() {
         let mut mem = Memory { data: [0.0f64; 4] };
         let vals = &mut mem.data;
         let a = _mm_setr_pd(1.0, 2.0);
         let d = vals.as_mut_ptr();
 
-        _mm_store1_pd(d, *black_box(&a));
+        unsafe {
+            _mm_store1_pd(d, *black_box(&a));
+        }
         assert_eq!(vals[0], 1.0);
         assert_eq!(vals[1], 1.0);
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_store_pd1() {
+    const fn test_mm_store_pd1() {
         let mut mem = Memory { data: [0.0f64; 4] };
         let vals = &mut mem.data;
         let a = _mm_setr_pd(1.0, 2.0);
         let d = vals.as_mut_ptr();
 
-        _mm_store_pd1(d, *black_box(&a));
+        unsafe {
+            _mm_store_pd1(d, *black_box(&a));
+        }
         assert_eq!(vals[0], 1.0);
         assert_eq!(vals[1], 1.0);
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_storer_pd() {
+    const fn test_mm_storer_pd() {
         let mut mem = Memory { data: [0.0f64; 4] };
         let vals = &mut mem.data;
         let a = _mm_setr_pd(1.0, 2.0);
         let d = vals.as_mut_ptr();
 
-        _mm_storer_pd(d, *black_box(&a));
+        unsafe {
+            _mm_storer_pd(d, *black_box(&a));
+        }
         assert_eq!(vals[0], 2.0);
         assert_eq!(vals[1], 1.0);
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_storeh_pd() {
+    const fn test_mm_storeh_pd() {
         let mut dest = 0.;
         let a = _mm_setr_pd(1., 2.);
-        _mm_storeh_pd(&mut dest, a);
+        unsafe {
+            _mm_storeh_pd(&mut dest, a);
+        }
         assert_eq!(dest, get_m128d(a, 1));
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_storel_pd() {
+    const fn test_mm_storel_pd() {
         let mut dest = 0.;
         let a = _mm_setr_pd(1., 2.);
-        _mm_storel_pd(&mut dest, a);
+        unsafe {
+            _mm_storel_pd(&mut dest, a);
+        }
         assert_eq!(dest, _mm_cvtsd_f64(a));
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_loadr_pd() {
+    const fn test_mm_loadr_pd() {
         let mut mem = Memory {
             data: [1.0f64, 2.0, 3.0, 4.0],
         };
         let vals = &mut mem.data;
         let d = vals.as_ptr();
 
-        let r = _mm_loadr_pd(d);
+        let r = unsafe { _mm_loadr_pd(d) };
         assert_eq_m128d(r, _mm_setr_pd(2.0, 1.0));
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_loadu_pd() {
+    const fn test_mm_loadu_pd() {
         // guaranteed to be aligned to 16 bytes
         let mut mem = Memory {
             data: [1.0f64, 2.0, 3.0, 4.0],
@@ -5099,31 +5137,31 @@ mod tests {
         let vals = &mut mem.data;
 
         // so this will *not* be aligned to 16 bytes
-        let d = vals.as_ptr().offset(1);
+        let d = unsafe { vals.as_ptr().offset(1) };
 
-        let r = _mm_loadu_pd(d);
+        let r = unsafe { _mm_loadu_pd(d) };
         let e = _mm_setr_pd(2.0, 3.0);
         assert_eq_m128d(r, e);
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_loadu_si16() {
+    const fn test_mm_loadu_si16() {
         let a = _mm_setr_epi16(1, 2, 3, 4, 5, 6, 7, 8);
-        let r = _mm_loadu_si16(ptr::addr_of!(a) as *const _);
+        let r = unsafe { _mm_loadu_si16(ptr::addr_of!(a) as *const _) };
         assert_eq_m128i(r, _mm_setr_epi16(1, 0, 0, 0, 0, 0, 0, 0));
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_loadu_si32() {
+    const fn test_mm_loadu_si32() {
         let a = _mm_setr_epi32(1, 2, 3, 4);
-        let r = _mm_loadu_si32(ptr::addr_of!(a) as *const _);
+        let r = unsafe { _mm_loadu_si32(ptr::addr_of!(a) as *const _) };
         assert_eq_m128i(r, _mm_setr_epi32(1, 0, 0, 0));
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_loadu_si64() {
+    const fn test_mm_loadu_si64() {
         let a = _mm_setr_epi64x(5, 6);
-        let r = _mm_loadu_si64(ptr::addr_of!(a) as *const _);
+        let r = unsafe { _mm_loadu_si64(ptr::addr_of!(a) as *const _) };
         assert_eq_m128i(r, _mm_setr_epi64x(5, 0));
     }
 
@@ -5302,16 +5340,16 @@ mod tests {
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_load1_pd() {
+    const fn test_mm_load1_pd() {
         let d = -5.0;
-        let r = _mm_load1_pd(&d);
+        let r = unsafe { _mm_load1_pd(&d) };
         assert_eq_m128d(r, _mm_setr_pd(d, d));
     }
 
     #[simd_test(enable = "sse2")]
-    const unsafe fn test_mm_load_pd1() {
+    const fn test_mm_load_pd1() {
         let d = -5.0;
-        let r = _mm_load_pd1(&d);
+        let r = unsafe { _mm_load_pd1(&d) };
         assert_eq_m128d(r, _mm_setr_pd(d, d));
     }
 
diff --git a/library/stdarch/crates/core_arch/src/x86/sse3.rs b/library/stdarch/crates/core_arch/src/x86/sse3.rs
index 68817856f44a..e4c75702544d 100644
--- a/library/stdarch/crates/core_arch/src/x86/sse3.rs
+++ b/library/stdarch/crates/core_arch/src/x86/sse3.rs
@@ -239,7 +239,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse3")]
-    unsafe fn test_mm_lddqu_si128() {
+    fn test_mm_lddqu_si128() {
         #[rustfmt::skip]
         let a = _mm_setr_epi8(
             1, 2, 3, 4,
@@ -247,7 +247,7 @@ mod tests {
             9, 10, 11, 12,
             13, 14, 15, 16,
         );
-        let r = _mm_lddqu_si128(&a);
+        let r = unsafe { _mm_lddqu_si128(&a) };
         assert_eq_m128i(a, r);
     }
 
@@ -273,9 +273,9 @@ mod tests {
     }
 
     #[simd_test(enable = "sse3")]
-    const unsafe fn test_mm_loaddup_pd() {
+    const fn test_mm_loaddup_pd() {
         let d = -5.0;
-        let r = _mm_loaddup_pd(&d);
+        let r = unsafe { _mm_loaddup_pd(&d) };
         assert_eq_m128d(r, _mm_setr_pd(d, d));
     }
 }
diff --git a/library/stdarch/crates/core_arch/src/x86/sse41.rs b/library/stdarch/crates/core_arch/src/x86/sse41.rs
index a499bf898b80..7ad4306f36f2 100644
--- a/library/stdarch/crates/core_arch/src/x86/sse41.rs
+++ b/library/stdarch/crates/core_arch/src/x86/sse41.rs
@@ -1219,20 +1219,20 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.1")]
-    const unsafe fn test_mm_blendv_pd() {
+    const fn test_mm_blendv_pd() {
         let a = _mm_set1_pd(0.0);
         let b = _mm_set1_pd(1.0);
-        let mask = transmute(_mm_setr_epi64x(0, -1));
+        let mask = _mm_castsi128_pd(_mm_setr_epi64x(0, -1));
         let r = _mm_blendv_pd(a, b, mask);
         let e = _mm_setr_pd(0.0, 1.0);
         assert_eq_m128d(r, e);
     }
 
     #[simd_test(enable = "sse4.1")]
-    const unsafe fn test_mm_blendv_ps() {
+    const fn test_mm_blendv_ps() {
         let a = _mm_set1_ps(0.0);
         let b = _mm_set1_ps(1.0);
-        let mask = transmute(_mm_setr_epi32(0, -1, 0, -1));
+        let mask = _mm_castsi128_ps(_mm_setr_epi32(0, -1, 0, -1));
         let r = _mm_blendv_ps(a, b, mask);
         let e = _mm_setr_ps(0.0, 1.0, 0.0, 1.0);
         assert_eq_m128(r, e);
@@ -1949,9 +1949,9 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.1")]
-    unsafe fn test_mm_stream_load_si128() {
+    fn test_mm_stream_load_si128() {
         let a = _mm_set_epi64x(5, 6);
-        let r = _mm_stream_load_si128(core::ptr::addr_of!(a) as *const _);
+        let r = unsafe { _mm_stream_load_si128(core::ptr::addr_of!(a) as *const _) };
         assert_eq_m128i(a, r);
     }
 }
diff --git a/library/stdarch/crates/core_arch/src/x86/sse42.rs b/library/stdarch/crates/core_arch/src/x86/sse42.rs
index 65d1fe4d6233..55e22592637f 100644
--- a/library/stdarch/crates/core_arch/src/x86/sse42.rs
+++ b/library/stdarch/crates/core_arch/src/x86/sse42.rs
@@ -613,6 +613,7 @@ mod tests {
     use crate::core_arch::assert_eq_const as assert_eq;
     use stdarch_test::simd_test;
 
+    use crate::core_arch::simd::*;
     use crate::core_arch::x86::*;
     use std::ptr;
 
@@ -625,7 +626,7 @@ mod tests {
         assert!(s.len() <= 16);
         let mut array = [0u8; 16];
         array[..s.len()].copy_from_slice(s);
-        unsafe { transmute(array) }
+        u8x16::from_array(array).as_m128i()
     }
 
     #[simd_test(enable = "sse4.2")]
diff --git a/library/stdarch/crates/core_arch/src/x86/sse4a.rs b/library/stdarch/crates/core_arch/src/x86/sse4a.rs
index 020baeff152d..f36b879a030e 100644
--- a/library/stdarch/crates/core_arch/src/x86/sse4a.rs
+++ b/library/stdarch/crates/core_arch/src/x86/sse4a.rs
@@ -206,7 +206,7 @@ mod tests {
     // Miri cannot support this until it is clear how it fits in the Rust memory model
     // (non-temporal store)
     #[cfg_attr(miri, ignore)]
-    unsafe fn test_mm_stream_sd() {
+    fn test_mm_stream_sd() {
         let mut mem = MemoryF64 {
             data: [1.0_f64, 2.0],
         };
@@ -216,7 +216,9 @@ mod tests {
 
             let x = _mm_setr_pd(3.0, 4.0);
 
-            _mm_stream_sd(d, x);
+            unsafe {
+                _mm_stream_sd(d, x);
+            }
             _mm_sfence();
         }
         assert_eq!(mem.data[0], 3.0);
@@ -232,7 +234,7 @@ mod tests {
     // Miri cannot support this until it is clear how it fits in the Rust memory model
     // (non-temporal store)
     #[cfg_attr(miri, ignore)]
-    unsafe fn test_mm_stream_ss() {
+    fn test_mm_stream_ss() {
         let mut mem = MemoryF32 {
             data: [1.0_f32, 2.0, 3.0, 4.0],
         };
@@ -242,7 +244,9 @@ mod tests {
 
             let x = _mm_setr_ps(5.0, 6.0, 7.0, 8.0);
 
-            _mm_stream_ss(d, x);
+            unsafe {
+                _mm_stream_ss(d, x);
+            }
             _mm_sfence();
         }
         assert_eq!(mem.data[0], 5.0);
diff --git a/library/stdarch/crates/core_arch/src/x86/xsave.rs b/library/stdarch/crates/core_arch/src/x86/xsave.rs
index 653eb28c4268..e22d3580ff46 100644
--- a/library/stdarch/crates/core_arch/src/x86/xsave.rs
+++ b/library/stdarch/crates/core_arch/src/x86/xsave.rs
@@ -197,47 +197,53 @@ mod tests {
 
     #[simd_test(enable = "xsave")]
     #[cfg_attr(miri, ignore)] // Register saving/restoring is not supported in Miri
-    unsafe fn test_xsave() {
+    fn test_xsave() {
         let m = 0xFFFFFFFFFFFFFFFF_u64; //< all registers
         let mut a = XsaveArea::new();
         let mut b = XsaveArea::new();
 
-        _xsave(a.ptr(), m);
-        _xrstor(a.ptr(), m);
-        _xsave(b.ptr(), m);
+        unsafe {
+            _xsave(a.ptr(), m);
+            _xrstor(a.ptr(), m);
+            _xsave(b.ptr(), m);
+        }
     }
 
     #[simd_test(enable = "xsave")]
     #[cfg_attr(miri, ignore)] // Register saving/restoring is not supported in Miri
-    unsafe fn test_xgetbv() {
+    fn test_xgetbv() {
         let xcr_n: u32 = _XCR_XFEATURE_ENABLED_MASK;
 
-        let xcr: u64 = _xgetbv(xcr_n);
-        let xcr_cpy: u64 = _xgetbv(xcr_n);
+        let xcr: u64 = unsafe { _xgetbv(xcr_n) };
+        let xcr_cpy: u64 = unsafe { _xgetbv(xcr_n) };
         assert_eq!(xcr, xcr_cpy);
     }
 
     #[simd_test(enable = "xsave,xsaveopt")]
     #[cfg_attr(miri, ignore)] // Register saving/restoring is not supported in Miri
-    unsafe fn test_xsaveopt() {
+    fn test_xsaveopt() {
         let m = 0xFFFFFFFFFFFFFFFF_u64; //< all registers
         let mut a = XsaveArea::new();
         let mut b = XsaveArea::new();
 
-        _xsaveopt(a.ptr(), m);
-        _xrstor(a.ptr(), m);
-        _xsaveopt(b.ptr(), m);
+        unsafe {
+            _xsaveopt(a.ptr(), m);
+            _xrstor(a.ptr(), m);
+            _xsaveopt(b.ptr(), m);
+        }
     }
 
     #[simd_test(enable = "xsave,xsavec")]
     #[cfg_attr(miri, ignore)] // Register saving/restoring is not supported in Miri
-    unsafe fn test_xsavec() {
+    fn test_xsavec() {
         let m = 0xFFFFFFFFFFFFFFFF_u64; //< all registers
         let mut a = XsaveArea::new();
         let mut b = XsaveArea::new();
 
-        _xsavec(a.ptr(), m);
-        _xrstor(a.ptr(), m);
-        _xsavec(b.ptr(), m);
+        unsafe {
+            _xsavec(a.ptr(), m);
+            _xrstor(a.ptr(), m);
+            _xsavec(b.ptr(), m);
+        }
     }
 }
diff --git a/library/stdarch/crates/core_arch/src/x86_64/amx.rs b/library/stdarch/crates/core_arch/src/x86_64/amx.rs
index f372f7066d51..4e20e014cf20 100644
--- a/library/stdarch/crates/core_arch/src/x86_64/amx.rs
+++ b/library/stdarch/crates/core_arch/src/x86_64/amx.rs
@@ -581,267 +581,297 @@ mod tests {
     }
 
     #[simd_test(enable = "amx-tile")]
-    unsafe fn test_tile_loadconfig() {
-        let config = __tilecfg::default();
-        _tile_loadconfig(config.as_ptr());
-        _tile_release();
+    fn test_tile_loadconfig() {
+        unsafe {
+            let config = __tilecfg::default();
+            _tile_loadconfig(config.as_ptr());
+            _tile_release();
+        }
     }
 
     #[simd_test(enable = "amx-tile")]
-    unsafe fn test_tile_storeconfig() {
-        let config = __tilecfg::new(1, 0, [32; 8], [8; 8]);
-        _tile_loadconfig(config.as_ptr());
-        let mut _config = __tilecfg::default();
-        _tile_storeconfig(_config.as_mut_ptr());
-        _tile_release();
-        assert_eq!(config, _config);
+    fn test_tile_storeconfig() {
+        unsafe {
+            let config = __tilecfg::new(1, 0, [32; 8], [8; 8]);
+            _tile_loadconfig(config.as_ptr());
+            let mut _config = __tilecfg::default();
+            _tile_storeconfig(_config.as_mut_ptr());
+            _tile_release();
+            assert_eq!(config, _config);
+        }
     }
 
     #[simd_test(enable = "amx-tile")]
-    unsafe fn test_tile_zero() {
-        _init_amx();
-        let mut config = __tilecfg::default();
-        config.palette = 1;
-        config.colsb[0] = 64;
-        config.rows[0] = 16;
-        _tile_loadconfig(config.as_ptr());
-        _tile_zero::<0>();
-        let mut out = [[1_i8; 64]; 16];
-        _tile_stored::<0>(&mut out as *mut [i8; 64] as *mut u8, 64);
-        _tile_release();
-        assert_eq!(out, [[0; 64]; 16]);
+    fn test_tile_zero() {
+        unsafe {
+            _init_amx();
+            let mut config = __tilecfg::default();
+            config.palette = 1;
+            config.colsb[0] = 64;
+            config.rows[0] = 16;
+            _tile_loadconfig(config.as_ptr());
+            _tile_zero::<0>();
+            let mut out = [[1_i8; 64]; 16];
+            _tile_stored::<0>(&mut out as *mut [i8; 64] as *mut u8, 64);
+            _tile_release();
+            assert_eq!(out, [[0; 64]; 16]);
+        }
     }
 
     #[simd_test(enable = "amx-tile")]
-    unsafe fn test_tile_stored() {
-        _init_amx();
-        let mut config = __tilecfg::default();
-        config.palette = 1;
-        config.colsb[0] = 64;
-        config.rows[0] = 16;
-        _tile_loadconfig(config.as_ptr());
-        _tile_zero::<0>();
-        let mut out = [[1_i8; 64]; 16];
-        _tile_stored::<0>(&mut out as *mut [i8; 64] as *mut u8, 64);
-        _tile_release();
-        assert_eq!(out, [[0; 64]; 16]);
+    fn test_tile_stored() {
+        unsafe {
+            _init_amx();
+            let mut config = __tilecfg::default();
+            config.palette = 1;
+            config.colsb[0] = 64;
+            config.rows[0] = 16;
+            _tile_loadconfig(config.as_ptr());
+            _tile_zero::<0>();
+            let mut out = [[1_i8; 64]; 16];
+            _tile_stored::<0>(&mut out as *mut [i8; 64] as *mut u8, 64);
+            _tile_release();
+            assert_eq!(out, [[0; 64]; 16]);
+        }
     }
 
     #[simd_test(enable = "amx-tile")]
-    unsafe fn test_tile_loadd() {
-        _init_amx();
-        let mut config = __tilecfg::default();
-        config.palette = 1;
-        config.colsb[0] = 64;
-        config.rows[0] = 16;
-        _tile_loadconfig(config.as_ptr());
-        _tile_zero::<0>();
-        let mat = [1_i8; 1024];
-        _tile_loadd::<0>(&mat as *const i8 as *const u8, 64);
-        let mut out = [[0_i8; 64]; 16];
-        _tile_stored::<0>(&mut out as *mut [i8; 64] as *mut u8, 64);
-        _tile_release();
-        assert_eq!(out, [[1; 64]; 16]);
+    fn test_tile_loadd() {
+        unsafe {
+            _init_amx();
+            let mut config = __tilecfg::default();
+            config.palette = 1;
+            config.colsb[0] = 64;
+            config.rows[0] = 16;
+            _tile_loadconfig(config.as_ptr());
+            _tile_zero::<0>();
+            let mat = [1_i8; 1024];
+            _tile_loadd::<0>(&mat as *const i8 as *const u8, 64);
+            let mut out = [[0_i8; 64]; 16];
+            _tile_stored::<0>(&mut out as *mut [i8; 64] as *mut u8, 64);
+            _tile_release();
+            assert_eq!(out, [[1; 64]; 16]);
+        }
     }
 
     #[simd_test(enable = "amx-tile")]
-    unsafe fn test_tile_stream_loadd() {
-        _init_amx();
-        let mut config = __tilecfg::default();
-        config.palette = 1;
-        config.colsb[0] = 64;
-        config.rows[0] = 16;
-        _tile_loadconfig(config.as_ptr());
-        _tile_zero::<0>();
-        let mat = [1_i8; 1024];
-        _tile_stream_loadd::<0>(&mat as *const i8 as *const u8, 64);
-        let mut out = [[0_i8; 64]; 16];
-        _tile_stored::<0>(&mut out as *mut [i8; 64] as *mut u8, 64);
-        _tile_release();
-        assert_eq!(out, [[1; 64]; 16]);
+    fn test_tile_stream_loadd() {
+        unsafe {
+            _init_amx();
+            let mut config = __tilecfg::default();
+            config.palette = 1;
+            config.colsb[0] = 64;
+            config.rows[0] = 16;
+            _tile_loadconfig(config.as_ptr());
+            _tile_zero::<0>();
+            let mat = [1_i8; 1024];
+            _tile_stream_loadd::<0>(&mat as *const i8 as *const u8, 64);
+            let mut out = [[0_i8; 64]; 16];
+            _tile_stored::<0>(&mut out as *mut [i8; 64] as *mut u8, 64);
+            _tile_release();
+            assert_eq!(out, [[1; 64]; 16]);
+        }
     }
 
     #[simd_test(enable = "amx-tile")]
-    unsafe fn test_tile_release() {
-        _tile_release();
+    fn test_tile_release() {
+        unsafe {
+            _tile_release();
+        }
     }
 
     #[simd_test(enable = "amx-bf16,avx512f")]
-    unsafe fn test_tile_dpbf16ps() {
-        _init_amx();
-        let bf16_1: u16 = _mm_cvtness_sbh(1.0).to_bits();
-        let bf16_2: u16 = _mm_cvtness_sbh(2.0).to_bits();
-        let ones: [u8; 1024] = transmute([bf16_1; 512]);
-        let twos: [u8; 1024] = transmute([bf16_2; 512]);
-        let mut res = [[0f32; 16]; 16];
-        let mut config = __tilecfg::default();
-        config.palette = 1;
-        (0..=2).for_each(|i| {
-            config.colsb[i] = 64;
-            config.rows[i] = 16;
-        });
-        _tile_loadconfig(config.as_ptr());
-        _tile_zero::<0>();
-        _tile_loadd::<1>(&ones as *const u8, 64);
-        _tile_loadd::<2>(&twos as *const u8, 64);
-        _tile_dpbf16ps::<0, 1, 2>();
-        _tile_stored::<0>(&mut res as *mut [f32; 16] as *mut u8, 64);
-        _tile_release();
-        assert_eq!(res, [[64f32; 16]; 16]);
+    fn test_tile_dpbf16ps() {
+        unsafe {
+            _init_amx();
+            let bf16_1: u16 = _mm_cvtness_sbh(1.0).to_bits();
+            let bf16_2: u16 = _mm_cvtness_sbh(2.0).to_bits();
+            let ones: [u8; 1024] = transmute([bf16_1; 512]);
+            let twos: [u8; 1024] = transmute([bf16_2; 512]);
+            let mut res = [[0f32; 16]; 16];
+            let mut config = __tilecfg::default();
+            config.palette = 1;
+            (0..=2).for_each(|i| {
+                config.colsb[i] = 64;
+                config.rows[i] = 16;
+            });
+            _tile_loadconfig(config.as_ptr());
+            _tile_zero::<0>();
+            _tile_loadd::<1>(&ones as *const u8, 64);
+            _tile_loadd::<2>(&twos as *const u8, 64);
+            _tile_dpbf16ps::<0, 1, 2>();
+            _tile_stored::<0>(&mut res as *mut [f32; 16] as *mut u8, 64);
+            _tile_release();
+            assert_eq!(res, [[64f32; 16]; 16]);
+        }
     }
 
     #[simd_test(enable = "amx-int8")]
-    unsafe fn test_tile_dpbssd() {
-        _init_amx();
-        let ones = [-1_i8; 1024];
-        let twos = [-2_i8; 1024];
-        let mut res = [[0_i32; 16]; 16];
-        let mut config = __tilecfg::default();
-        config.palette = 1;
-        (0..=2).for_each(|i| {
-            config.colsb[i] = 64;
-            config.rows[i] = 16;
-        });
-        _tile_loadconfig(config.as_ptr());
-        _tile_zero::<0>();
-        _tile_loadd::<1>(&ones as *const i8 as *const u8, 64);
-        _tile_loadd::<2>(&twos as *const i8 as *const u8, 64);
-        _tile_dpbssd::<0, 1, 2>();
-        _tile_stored::<0>(&mut res as *mut [i32; 16] as *mut u8, 64);
-        _tile_release();
-        assert_eq!(res, [[128_i32; 16]; 16]);
+    fn test_tile_dpbssd() {
+        unsafe {
+            _init_amx();
+            let ones = [-1_i8; 1024];
+            let twos = [-2_i8; 1024];
+            let mut res = [[0_i32; 16]; 16];
+            let mut config = __tilecfg::default();
+            config.palette = 1;
+            (0..=2).for_each(|i| {
+                config.colsb[i] = 64;
+                config.rows[i] = 16;
+            });
+            _tile_loadconfig(config.as_ptr());
+            _tile_zero::<0>();
+            _tile_loadd::<1>(&ones as *const i8 as *const u8, 64);
+            _tile_loadd::<2>(&twos as *const i8 as *const u8, 64);
+            _tile_dpbssd::<0, 1, 2>();
+            _tile_stored::<0>(&mut res as *mut [i32; 16] as *mut u8, 64);
+            _tile_release();
+            assert_eq!(res, [[128_i32; 16]; 16]);
+        }
     }
 
     #[simd_test(enable = "amx-int8")]
-    unsafe fn test_tile_dpbsud() {
-        _init_amx();
-        let ones = [-1_i8; 1024];
-        let twos = [2_u8; 1024];
-        let mut res = [[0_i32; 16]; 16];
-        let mut config = __tilecfg::default();
-        config.palette = 1;
-        (0..=2).for_each(|i| {
-            config.colsb[i] = 64;
-            config.rows[i] = 16;
-        });
-        _tile_loadconfig(config.as_ptr());
-        _tile_zero::<0>();
-        _tile_loadd::<1>(&ones as *const i8 as *const u8, 64);
-        _tile_loadd::<2>(&twos as *const u8, 64);
-        _tile_dpbsud::<0, 1, 2>();
-        _tile_stored::<0>(&mut res as *mut [i32; 16] as *mut u8, 64);
-        _tile_release();
-        assert_eq!(res, [[-128_i32; 16]; 16]);
+    fn test_tile_dpbsud() {
+        unsafe {
+            _init_amx();
+            let ones = [-1_i8; 1024];
+            let twos = [2_u8; 1024];
+            let mut res = [[0_i32; 16]; 16];
+            let mut config = __tilecfg::default();
+            config.palette = 1;
+            (0..=2).for_each(|i| {
+                config.colsb[i] = 64;
+                config.rows[i] = 16;
+            });
+            _tile_loadconfig(config.as_ptr());
+            _tile_zero::<0>();
+            _tile_loadd::<1>(&ones as *const i8 as *const u8, 64);
+            _tile_loadd::<2>(&twos as *const u8, 64);
+            _tile_dpbsud::<0, 1, 2>();
+            _tile_stored::<0>(&mut res as *mut [i32; 16] as *mut u8, 64);
+            _tile_release();
+            assert_eq!(res, [[-128_i32; 16]; 16]);
+        }
     }
 
     #[simd_test(enable = "amx-int8")]
-    unsafe fn test_tile_dpbusd() {
-        _init_amx();
-        let ones = [1_u8; 1024];
-        let twos = [-2_i8; 1024];
-        let mut res = [[0_i32; 16]; 16];
-        let mut config = __tilecfg::default();
-        config.palette = 1;
-        (0..=2).for_each(|i| {
-            config.colsb[i] = 64;
-            config.rows[i] = 16;
-        });
-        _tile_loadconfig(config.as_ptr());
-        _tile_zero::<0>();
-        _tile_loadd::<1>(&ones as *const u8, 64);
-        _tile_loadd::<2>(&twos as *const i8 as *const u8, 64);
-        _tile_dpbusd::<0, 1, 2>();
-        _tile_stored::<0>(&mut res as *mut [i32; 16] as *mut u8, 64);
-        _tile_release();
-        assert_eq!(res, [[-128_i32; 16]; 16]);
+    fn test_tile_dpbusd() {
+        unsafe {
+            _init_amx();
+            let ones = [1_u8; 1024];
+            let twos = [-2_i8; 1024];
+            let mut res = [[0_i32; 16]; 16];
+            let mut config = __tilecfg::default();
+            config.palette = 1;
+            (0..=2).for_each(|i| {
+                config.colsb[i] = 64;
+                config.rows[i] = 16;
+            });
+            _tile_loadconfig(config.as_ptr());
+            _tile_zero::<0>();
+            _tile_loadd::<1>(&ones as *const u8, 64);
+            _tile_loadd::<2>(&twos as *const i8 as *const u8, 64);
+            _tile_dpbusd::<0, 1, 2>();
+            _tile_stored::<0>(&mut res as *mut [i32; 16] as *mut u8, 64);
+            _tile_release();
+            assert_eq!(res, [[-128_i32; 16]; 16]);
+        }
     }
 
     #[simd_test(enable = "amx-int8")]
-    unsafe fn test_tile_dpbuud() {
-        _init_amx();
-        let ones = [1_u8; 1024];
-        let twos = [2_u8; 1024];
-        let mut res = [[0_i32; 16]; 16];
-        let mut config = __tilecfg::default();
-        config.palette = 1;
-        (0..=2).for_each(|i| {
-            config.colsb[i] = 64;
-            config.rows[i] = 16;
-        });
-        _tile_loadconfig(config.as_ptr());
-        _tile_zero::<0>();
-        _tile_loadd::<1>(&ones as *const u8, 64);
-        _tile_loadd::<2>(&twos as *const u8, 64);
-        _tile_dpbuud::<0, 1, 2>();
-        _tile_stored::<0>(&mut res as *mut [i32; 16] as *mut u8, 64);
-        _tile_release();
-        assert_eq!(res, [[128_i32; 16]; 16]);
+    fn test_tile_dpbuud() {
+        unsafe {
+            _init_amx();
+            let ones = [1_u8; 1024];
+            let twos = [2_u8; 1024];
+            let mut res = [[0_i32; 16]; 16];
+            let mut config = __tilecfg::default();
+            config.palette = 1;
+            (0..=2).for_each(|i| {
+                config.colsb[i] = 64;
+                config.rows[i] = 16;
+            });
+            _tile_loadconfig(config.as_ptr());
+            _tile_zero::<0>();
+            _tile_loadd::<1>(&ones as *const u8, 64);
+            _tile_loadd::<2>(&twos as *const u8, 64);
+            _tile_dpbuud::<0, 1, 2>();
+            _tile_stored::<0>(&mut res as *mut [i32; 16] as *mut u8, 64);
+            _tile_release();
+            assert_eq!(res, [[128_i32; 16]; 16]);
+        }
     }
 
     #[simd_test(enable = "amx-fp16")]
-    unsafe fn test_tile_dpfp16ps() {
-        _init_amx();
-        let ones = [1f16; 512];
-        let twos = [2f16; 512];
-        let mut res = [[0f32; 16]; 16];
-        let mut config = __tilecfg::default();
-        config.palette = 1;
-        (0..=2).for_each(|i| {
-            config.colsb[i] = 64;
-            config.rows[i] = 16;
-        });
-        _tile_loadconfig(config.as_ptr());
-        _tile_zero::<0>();
-        _tile_loadd::<1>(&ones as *const f16 as *const u8, 64);
-        _tile_loadd::<2>(&twos as *const f16 as *const u8, 64);
-        _tile_dpfp16ps::<0, 1, 2>();
-        _tile_stored::<0>(&mut res as *mut [f32; 16] as *mut u8, 64);
-        _tile_release();
-        assert_eq!(res, [[64f32; 16]; 16]);
+    fn test_tile_dpfp16ps() {
+        unsafe {
+            _init_amx();
+            let ones = [1f16; 512];
+            let twos = [2f16; 512];
+            let mut res = [[0f32; 16]; 16];
+            let mut config = __tilecfg::default();
+            config.palette = 1;
+            (0..=2).for_each(|i| {
+                config.colsb[i] = 64;
+                config.rows[i] = 16;
+            });
+            _tile_loadconfig(config.as_ptr());
+            _tile_zero::<0>();
+            _tile_loadd::<1>(&ones as *const f16 as *const u8, 64);
+            _tile_loadd::<2>(&twos as *const f16 as *const u8, 64);
+            _tile_dpfp16ps::<0, 1, 2>();
+            _tile_stored::<0>(&mut res as *mut [f32; 16] as *mut u8, 64);
+            _tile_release();
+            assert_eq!(res, [[64f32; 16]; 16]);
+        }
     }
 
     #[simd_test(enable = "amx-complex")]
-    unsafe fn test_tile_cmmimfp16ps() {
-        _init_amx();
-        let ones = [1f16; 512];
-        let twos = [2f16; 512];
-        let mut res = [[0f32; 16]; 16];
-        let mut config = __tilecfg::default();
-        config.palette = 1;
-        (0..=2).for_each(|i| {
-            config.colsb[i] = 64;
-            config.rows[i] = 16;
-        });
-        _tile_loadconfig(config.as_ptr());
-        _tile_zero::<0>();
-        _tile_loadd::<1>(&ones as *const f16 as *const u8, 64);
-        _tile_loadd::<2>(&twos as *const f16 as *const u8, 64);
-        _tile_cmmimfp16ps::<0, 1, 2>();
-        _tile_stored::<0>(&mut res as *mut [f32; 16] as *mut u8, 64);
-        _tile_release();
-        assert_eq!(res, [[64f32; 16]; 16]);
+    fn test_tile_cmmimfp16ps() {
+        unsafe {
+            _init_amx();
+            let ones = [1f16; 512];
+            let twos = [2f16; 512];
+            let mut res = [[0f32; 16]; 16];
+            let mut config = __tilecfg::default();
+            config.palette = 1;
+            (0..=2).for_each(|i| {
+                config.colsb[i] = 64;
+                config.rows[i] = 16;
+            });
+            _tile_loadconfig(config.as_ptr());
+            _tile_zero::<0>();
+            _tile_loadd::<1>(&ones as *const f16 as *const u8, 64);
+            _tile_loadd::<2>(&twos as *const f16 as *const u8, 64);
+            _tile_cmmimfp16ps::<0, 1, 2>();
+            _tile_stored::<0>(&mut res as *mut [f32; 16] as *mut u8, 64);
+            _tile_release();
+            assert_eq!(res, [[64f32; 16]; 16]);
+        }
     }
 
     #[simd_test(enable = "amx-complex")]
-    unsafe fn test_tile_cmmrlfp16ps() {
-        _init_amx();
-        let ones = [1f16; 512];
-        let twos = [2f16; 512];
-        let mut res = [[0f32; 16]; 16];
-        let mut config = __tilecfg::default();
-        config.palette = 1;
-        (0..=2).for_each(|i| {
-            config.colsb[i] = 64;
-            config.rows[i] = 16;
-        });
-        _tile_loadconfig(config.as_ptr());
-        _tile_zero::<0>();
-        _tile_loadd::<1>(&ones as *const f16 as *const u8, 64);
-        _tile_loadd::<2>(&twos as *const f16 as *const u8, 64);
-        _tile_cmmrlfp16ps::<0, 1, 2>();
-        _tile_stored::<0>(&mut res as *mut [f32; 16] as *mut u8, 64);
-        _tile_release();
-        assert_eq!(res, [[0f32; 16]; 16]);
+    fn test_tile_cmmrlfp16ps() {
+        unsafe {
+            _init_amx();
+            let ones = [1f16; 512];
+            let twos = [2f16; 512];
+            let mut res = [[0f32; 16]; 16];
+            let mut config = __tilecfg::default();
+            config.palette = 1;
+            (0..=2).for_each(|i| {
+                config.colsb[i] = 64;
+                config.rows[i] = 16;
+            });
+            _tile_loadconfig(config.as_ptr());
+            _tile_zero::<0>();
+            _tile_loadd::<1>(&ones as *const f16 as *const u8, 64);
+            _tile_loadd::<2>(&twos as *const f16 as *const u8, 64);
+            _tile_cmmrlfp16ps::<0, 1, 2>();
+            _tile_stored::<0>(&mut res as *mut [f32; 16] as *mut u8, 64);
+            _tile_release();
+            assert_eq!(res, [[0f32; 16]; 16]);
+        }
     }
 
     const BF8_ONE: u8 = 0x3c;
@@ -850,223 +880,245 @@ mod tests {
     const HF8_TWO: u8 = 0x40;
 
     #[simd_test(enable = "amx-fp8")]
-    unsafe fn test_tile_dpbf8ps() {
-        _init_amx();
-        let ones = [BF8_ONE; 1024];
-        let twos = [BF8_TWO; 1024];
-        let mut res = [[0.0_f32; 16]; 16];
-        let mut config = __tilecfg::default();
-        config.palette = 1;
-        (0..=2).for_each(|i| {
-            config.colsb[i] = 64;
-            config.rows[i] = 16;
-        });
-        _tile_loadconfig(config.as_ptr());
-        _tile_zero::<0>();
-        _tile_loadd::<1>(&ones as *const u8, 64);
-        _tile_loadd::<2>(&twos as *const u8, 64);
-        _tile_dpbf8ps::<0, 1, 2>();
-        _tile_stored::<0>(res.as_mut_ptr().cast(), 64);
-        _tile_release();
-        assert_eq!(res, [[128.0_f32; 16]; 16]);
+    fn test_tile_dpbf8ps() {
+        unsafe {
+            _init_amx();
+            let ones = [BF8_ONE; 1024];
+            let twos = [BF8_TWO; 1024];
+            let mut res = [[0.0_f32; 16]; 16];
+            let mut config = __tilecfg::default();
+            config.palette = 1;
+            (0..=2).for_each(|i| {
+                config.colsb[i] = 64;
+                config.rows[i] = 16;
+            });
+            _tile_loadconfig(config.as_ptr());
+            _tile_zero::<0>();
+            _tile_loadd::<1>(&ones as *const u8, 64);
+            _tile_loadd::<2>(&twos as *const u8, 64);
+            _tile_dpbf8ps::<0, 1, 2>();
+            _tile_stored::<0>(res.as_mut_ptr().cast(), 64);
+            _tile_release();
+            assert_eq!(res, [[128.0_f32; 16]; 16]);
+        }
     }
 
     #[simd_test(enable = "amx-fp8")]
-    unsafe fn test_tile_dpbhf8ps() {
-        _init_amx();
-        let ones = [BF8_ONE; 1024];
-        let twos = [HF8_TWO; 1024];
-        let mut res = [[0.0_f32; 16]; 16];
-        let mut config = __tilecfg::default();
-        config.palette = 1;
-        (0..=2).for_each(|i| {
-            config.colsb[i] = 64;
-            config.rows[i] = 16;
-        });
-        _tile_loadconfig(config.as_ptr());
-        _tile_zero::<0>();
-        _tile_loadd::<1>(&ones as *const u8, 64);
-        _tile_loadd::<2>(&twos as *const u8, 64);
-        _tile_dpbhf8ps::<0, 1, 2>();
-        _tile_stored::<0>(res.as_mut_ptr().cast(), 64);
-        _tile_release();
-        assert_eq!(res, [[128.0_f32; 16]; 16]);
+    fn test_tile_dpbhf8ps() {
+        unsafe {
+            _init_amx();
+            let ones = [BF8_ONE; 1024];
+            let twos = [HF8_TWO; 1024];
+            let mut res = [[0.0_f32; 16]; 16];
+            let mut config = __tilecfg::default();
+            config.palette = 1;
+            (0..=2).for_each(|i| {
+                config.colsb[i] = 64;
+                config.rows[i] = 16;
+            });
+            _tile_loadconfig(config.as_ptr());
+            _tile_zero::<0>();
+            _tile_loadd::<1>(&ones as *const u8, 64);
+            _tile_loadd::<2>(&twos as *const u8, 64);
+            _tile_dpbhf8ps::<0, 1, 2>();
+            _tile_stored::<0>(res.as_mut_ptr().cast(), 64);
+            _tile_release();
+            assert_eq!(res, [[128.0_f32; 16]; 16]);
+        }
     }
 
     #[simd_test(enable = "amx-fp8")]
-    unsafe fn test_tile_dphbf8ps() {
-        _init_amx();
-        let ones = [HF8_ONE; 1024];
-        let twos = [BF8_TWO; 1024];
-        let mut res = [[0.0_f32; 16]; 16];
-        let mut config = __tilecfg::default();
-        config.palette = 1;
-        (0..=2).for_each(|i| {
-            config.colsb[i] = 64;
-            config.rows[i] = 16;
-        });
-        _tile_loadconfig(config.as_ptr());
-        _tile_zero::<0>();
-        _tile_loadd::<1>(&ones as *const u8, 64);
-        _tile_loadd::<2>(&twos as *const u8, 64);
-        _tile_dphbf8ps::<0, 1, 2>();
-        _tile_stored::<0>(res.as_mut_ptr().cast(), 64);
-        _tile_release();
-        assert_eq!(res, [[128.0_f32; 16]; 16]);
+    fn test_tile_dphbf8ps() {
+        unsafe {
+            _init_amx();
+            let ones = [HF8_ONE; 1024];
+            let twos = [BF8_TWO; 1024];
+            let mut res = [[0.0_f32; 16]; 16];
+            let mut config = __tilecfg::default();
+            config.palette = 1;
+            (0..=2).for_each(|i| {
+                config.colsb[i] = 64;
+                config.rows[i] = 16;
+            });
+            _tile_loadconfig(config.as_ptr());
+            _tile_zero::<0>();
+            _tile_loadd::<1>(&ones as *const u8, 64);
+            _tile_loadd::<2>(&twos as *const u8, 64);
+            _tile_dphbf8ps::<0, 1, 2>();
+            _tile_stored::<0>(res.as_mut_ptr().cast(), 64);
+            _tile_release();
+            assert_eq!(res, [[128.0_f32; 16]; 16]);
+        }
     }
 
     #[simd_test(enable = "amx-fp8")]
-    unsafe fn test_tile_dphf8ps() {
-        _init_amx();
-        let ones = [HF8_ONE; 1024];
-        let twos = [HF8_TWO; 1024];
-        let mut res = [[0.0_f32; 16]; 16];
-        let mut config = __tilecfg::default();
-        config.palette = 1;
-        (0..=2).for_each(|i| {
-            config.colsb[i] = 64;
-            config.rows[i] = 16;
-        });
-        _tile_loadconfig(config.as_ptr());
-        _tile_zero::<0>();
-        _tile_loadd::<1>(&ones as *const u8, 64);
-        _tile_loadd::<2>(&twos as *const u8, 64);
-        _tile_dphf8ps::<0, 1, 2>();
-        _tile_stored::<0>(res.as_mut_ptr().cast(), 64);
-        _tile_release();
-        assert_eq!(res, [[128.0_f32; 16]; 16]);
+    fn test_tile_dphf8ps() {
+        unsafe {
+            _init_amx();
+            let ones = [HF8_ONE; 1024];
+            let twos = [HF8_TWO; 1024];
+            let mut res = [[0.0_f32; 16]; 16];
+            let mut config = __tilecfg::default();
+            config.palette = 1;
+            (0..=2).for_each(|i| {
+                config.colsb[i] = 64;
+                config.rows[i] = 16;
+            });
+            _tile_loadconfig(config.as_ptr());
+            _tile_zero::<0>();
+            _tile_loadd::<1>(&ones as *const u8, 64);
+            _tile_loadd::<2>(&twos as *const u8, 64);
+            _tile_dphf8ps::<0, 1, 2>();
+            _tile_stored::<0>(res.as_mut_ptr().cast(), 64);
+            _tile_release();
+            assert_eq!(res, [[128.0_f32; 16]; 16]);
+        }
     }
 
     #[simd_test(enable = "amx-movrs")]
-    unsafe fn test_tile_loaddrs() {
-        _init_amx();
-        let mut config = __tilecfg::default();
-        config.palette = 1;
-        config.colsb[0] = 64;
-        config.rows[0] = 16;
-        _tile_loadconfig(config.as_ptr());
-        _tile_zero::<0>();
-        let mat = [1_i8; 1024];
-        _tile_loaddrs::<0>(&mat as *const i8 as *const u8, 64);
-        let mut out = [[0_i8; 64]; 16];
-        _tile_stored::<0>(&mut out as *mut [i8; 64] as *mut u8, 64);
-        _tile_release();
-        assert_eq!(out, [[1; 64]; 16]);
+    fn test_tile_loaddrs() {
+        unsafe {
+            _init_amx();
+            let mut config = __tilecfg::default();
+            config.palette = 1;
+            config.colsb[0] = 64;
+            config.rows[0] = 16;
+            _tile_loadconfig(config.as_ptr());
+            _tile_zero::<0>();
+            let mat = [1_i8; 1024];
+            _tile_loaddrs::<0>(&mat as *const i8 as *const u8, 64);
+            let mut out = [[0_i8; 64]; 16];
+            _tile_stored::<0>(&mut out as *mut [i8; 64] as *mut u8, 64);
+            _tile_release();
+            assert_eq!(out, [[1; 64]; 16]);
+        }
     }
 
     #[simd_test(enable = "amx-movrs")]
-    unsafe fn test_tile_stream_loaddrs() {
-        _init_amx();
-        let mut config = __tilecfg::default();
-        config.palette = 1;
-        config.colsb[0] = 64;
-        config.rows[0] = 16;
-        _tile_loadconfig(config.as_ptr());
-        _tile_zero::<0>();
-        let mat = [1_i8; 1024];
-        _tile_stream_loaddrs::<0>(&mat as *const i8 as *const u8, 64);
-        let mut out = [[0_i8; 64]; 16];
-        _tile_stored::<0>(&mut out as *mut [i8; 64] as *mut u8, 64);
-        _tile_release();
-        assert_eq!(out, [[1; 64]; 16]);
-    }
-
-    #[simd_test(enable = "amx-avx512,avx10.2")]
-    unsafe fn test_tile_movrow() {
-        _init_amx();
-        let array: [[u8; 64]; 16] = array::from_fn(|i| [i as _; _]);
-
-        let mut config = __tilecfg::default();
-        config.palette = 1;
-        config.colsb[0] = 64;
-        config.rows[0] = 16;
-        _tile_loadconfig(config.as_ptr());
-        _tile_loadd::<0>(array.as_ptr().cast(), 64);
-        for i in 0..16 {
-            let row = _tile_movrow::<0>(i);
-            assert_eq!(*row.as_u8x64().as_array(), [i as _; _]);
+    fn test_tile_stream_loaddrs() {
+        unsafe {
+            _init_amx();
+            let mut config = __tilecfg::default();
+            config.palette = 1;
+            config.colsb[0] = 64;
+            config.rows[0] = 16;
+            _tile_loadconfig(config.as_ptr());
+            _tile_zero::<0>();
+            let mat = [1_i8; 1024];
+            _tile_stream_loaddrs::<0>(&mat as *const i8 as *const u8, 64);
+            let mut out = [[0_i8; 64]; 16];
+            _tile_stored::<0>(&mut out as *mut [i8; 64] as *mut u8, 64);
+            _tile_release();
+            assert_eq!(out, [[1; 64]; 16]);
         }
     }
 
     #[simd_test(enable = "amx-avx512,avx10.2")]
-    unsafe fn test_tile_cvtrowd2ps() {
-        _init_amx();
-        let array: [[u32; 16]; 16] = array::from_fn(|i| [i as _; _]);
+    fn test_tile_movrow() {
+        unsafe {
+            _init_amx();
+            let array: [[u8; 64]; 16] = array::from_fn(|i| [i as _; _]);
 
-        let mut config = __tilecfg::default();
-        config.palette = 1;
-        config.colsb[0] = 64;
-        config.rows[0] = 16;
-        _tile_loadconfig(config.as_ptr());
-        _tile_loadd::<0>(array.as_ptr().cast(), 64);
-        for i in 0..16 {
-            let row = _tile_cvtrowd2ps::<0>(i);
-            assert_eq!(*row.as_f32x16().as_array(), [i as _; _]);
+            let mut config = __tilecfg::default();
+            config.palette = 1;
+            config.colsb[0] = 64;
+            config.rows[0] = 16;
+            _tile_loadconfig(config.as_ptr());
+            _tile_loadd::<0>(array.as_ptr().cast(), 64);
+            for i in 0..16 {
+                let row = _tile_movrow::<0>(i);
+                assert_eq!(*row.as_u8x64().as_array(), [i as _; _]);
+            }
         }
     }
 
     #[simd_test(enable = "amx-avx512,avx10.2")]
-    unsafe fn test_tile_cvtrowps2phh() {
-        _init_amx();
-        let array: [[f32; 16]; 16] = array::from_fn(|i| [i as _; _]);
+    fn test_tile_cvtrowd2ps() {
+        unsafe {
+            _init_amx();
+            let array: [[u32; 16]; 16] = array::from_fn(|i| [i as _; _]);
 
-        let mut config = __tilecfg::default();
-        config.palette = 1;
-        config.colsb[0] = 64;
-        config.rows[0] = 16;
-        _tile_loadconfig(config.as_ptr());
-        _tile_loadd::<0>(array.as_ptr().cast(), 64);
-        for i in 0..16 {
-            let row = _tile_cvtrowps2phh::<0>(i);
-            assert_eq!(
-                *row.as_f16x32().as_array(),
-                array::from_fn(|j| if j & 1 == 0 { 0.0 } else { i as _ })
-            );
+            let mut config = __tilecfg::default();
+            config.palette = 1;
+            config.colsb[0] = 64;
+            config.rows[0] = 16;
+            _tile_loadconfig(config.as_ptr());
+            _tile_loadd::<0>(array.as_ptr().cast(), 64);
+            for i in 0..16 {
+                let row = _tile_cvtrowd2ps::<0>(i);
+                assert_eq!(*row.as_f32x16().as_array(), [i as _; _]);
+            }
         }
     }
 
     #[simd_test(enable = "amx-avx512,avx10.2")]
-    unsafe fn test_tile_cvtrowps2phl() {
-        _init_amx();
-        let array: [[f32; 16]; 16] = array::from_fn(|i| [i as _; _]);
+    fn test_tile_cvtrowps2phh() {
+        unsafe {
+            _init_amx();
+            let array: [[f32; 16]; 16] = array::from_fn(|i| [i as _; _]);
 
-        let mut config = __tilecfg::default();
-        config.palette = 1;
-        config.colsb[0] = 64;
-        config.rows[0] = 16;
-        _tile_loadconfig(config.as_ptr());
-        _tile_loadd::<0>(array.as_ptr().cast(), 64);
-        for i in 0..16 {
-            let row = _tile_cvtrowps2phl::<0>(i);
-            assert_eq!(
-                *row.as_f16x32().as_array(),
-                array::from_fn(|j| if j & 1 == 0 { i as _ } else { 0.0 })
-            );
+            let mut config = __tilecfg::default();
+            config.palette = 1;
+            config.colsb[0] = 64;
+            config.rows[0] = 16;
+            _tile_loadconfig(config.as_ptr());
+            _tile_loadd::<0>(array.as_ptr().cast(), 64);
+            for i in 0..16 {
+                let row = _tile_cvtrowps2phh::<0>(i);
+                assert_eq!(
+                    *row.as_f16x32().as_array(),
+                    array::from_fn(|j| if j & 1 == 0 { 0.0 } else { i as _ })
+                );
+            }
+        }
+    }
+
+    #[simd_test(enable = "amx-avx512,avx10.2")]
+    fn test_tile_cvtrowps2phl() {
+        unsafe {
+            _init_amx();
+            let array: [[f32; 16]; 16] = array::from_fn(|i| [i as _; _]);
+
+            let mut config = __tilecfg::default();
+            config.palette = 1;
+            config.colsb[0] = 64;
+            config.rows[0] = 16;
+            _tile_loadconfig(config.as_ptr());
+            _tile_loadd::<0>(array.as_ptr().cast(), 64);
+            for i in 0..16 {
+                let row = _tile_cvtrowps2phl::<0>(i);
+                assert_eq!(
+                    *row.as_f16x32().as_array(),
+                    array::from_fn(|j| if j & 1 == 0 { i as _ } else { 0.0 })
+                );
+            }
         }
     }
 
     #[simd_test(enable = "amx-tf32")]
-    unsafe fn test_tile_mmultf32ps() {
-        _init_amx();
-        let a: [[f32; 16]; 16] = array::from_fn(|i| [i as _; _]);
-        let b: [[f32; 16]; 16] = [array::from_fn(|j| j as _); _];
-        let mut res = [[0.0; 16]; 16];
+    fn test_tile_mmultf32ps() {
+        unsafe {
+            _init_amx();
+            let a: [[f32; 16]; 16] = array::from_fn(|i| [i as _; _]);
+            let b: [[f32; 16]; 16] = [array::from_fn(|j| j as _); _];
+            let mut res = [[0.0; 16]; 16];
 
-        let mut config = __tilecfg::default();
-        config.palette = 1;
-        (0..=2).for_each(|i| {
-            config.colsb[i] = 64;
-            config.rows[i] = 16;
-        });
-        _tile_loadconfig(config.as_ptr());
-        _tile_zero::<0>();
-        _tile_loadd::<1>(a.as_ptr().cast(), 64);
-        _tile_loadd::<2>(b.as_ptr().cast(), 64);
-        _tile_mmultf32ps::<0, 1, 2>();
-        _tile_stored::<0>(res.as_mut_ptr().cast(), 64);
-        _tile_release();
+            let mut config = __tilecfg::default();
+            config.palette = 1;
+            (0..=2).for_each(|i| {
+                config.colsb[i] = 64;
+                config.rows[i] = 16;
+            });
+            _tile_loadconfig(config.as_ptr());
+            _tile_zero::<0>();
+            _tile_loadd::<1>(a.as_ptr().cast(), 64);
+            _tile_loadd::<2>(b.as_ptr().cast(), 64);
+            _tile_mmultf32ps::<0, 1, 2>();
+            _tile_stored::<0>(res.as_mut_ptr().cast(), 64);
+            _tile_release();
 
-        let expected = array::from_fn(|i| array::from_fn(|j| 16.0 * i as f32 * j as f32));
-        assert_eq!(res, expected);
+            let expected = array::from_fn(|i| array::from_fn(|j| 16.0 * i as f32 * j as f32));
+            assert_eq!(res, expected);
+        }
     }
 }
diff --git a/library/stdarch/crates/core_arch/src/x86_64/avx512f.rs b/library/stdarch/crates/core_arch/src/x86_64/avx512f.rs
index 368fb0c238e4..0fd9b09363d4 100644
--- a/library/stdarch/crates/core_arch/src/x86_64/avx512f.rs
+++ b/library/stdarch/crates/core_arch/src/x86_64/avx512f.rs
@@ -7446,81 +7446,81 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_i32gather_pd() {
+    fn test_mm512_i32gather_pd() {
         let arr: [f64; 128] = core::array::from_fn(|i| i as f64);
         // A multiplier of 8 is word-addressing
         let index = _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112);
-        let r = _mm512_i32gather_pd::<8>(index, arr.as_ptr());
+        let r = unsafe { _mm512_i32gather_pd::<8>(index, arr.as_ptr()) };
         assert_eq_m512d(r, _mm512_setr_pd(0., 16., 32., 48., 64., 80., 96., 112.));
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_i32gather_pd() {
+    fn test_mm512_mask_i32gather_pd() {
         let arr: [f64; 128] = core::array::from_fn(|i| i as f64);
         let src = _mm512_set1_pd(2.);
         let mask = 0b10101010;
         let index = _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112);
         // A multiplier of 8 is word-addressing
-        let r = _mm512_mask_i32gather_pd::<8>(src, mask, index, arr.as_ptr());
+        let r = unsafe { _mm512_mask_i32gather_pd::<8>(src, mask, index, arr.as_ptr()) };
         assert_eq_m512d(r, _mm512_setr_pd(2., 16., 2., 48., 2., 80., 2., 112.));
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_i64gather_pd() {
+    fn test_mm512_i64gather_pd() {
         let arr: [f64; 128] = core::array::from_fn(|i| i as f64);
         // A multiplier of 8 is word-addressing
         let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
-        let r = _mm512_i64gather_pd::<8>(index, arr.as_ptr());
+        let r = unsafe { _mm512_i64gather_pd::<8>(index, arr.as_ptr()) };
         assert_eq_m512d(r, _mm512_setr_pd(0., 16., 32., 48., 64., 80., 96., 112.));
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_i64gather_pd() {
+    fn test_mm512_mask_i64gather_pd() {
         let arr: [f64; 128] = core::array::from_fn(|i| i as f64);
         let src = _mm512_set1_pd(2.);
         let mask = 0b10101010;
         let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
         // A multiplier of 8 is word-addressing
-        let r = _mm512_mask_i64gather_pd::<8>(src, mask, index, arr.as_ptr());
+        let r = unsafe { _mm512_mask_i64gather_pd::<8>(src, mask, index, arr.as_ptr()) };
         assert_eq_m512d(r, _mm512_setr_pd(2., 16., 2., 48., 2., 80., 2., 112.));
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_i64gather_ps() {
+    fn test_mm512_i64gather_ps() {
         let arr: [f32; 128] = core::array::from_fn(|i| i as f32);
         // A multiplier of 4 is word-addressing
         #[rustfmt::skip]
         let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
-        let r = _mm512_i64gather_ps::<4>(index, arr.as_ptr());
+        let r = unsafe { _mm512_i64gather_ps::<4>(index, arr.as_ptr()) };
         assert_eq_m256(r, _mm256_setr_ps(0., 16., 32., 48., 64., 80., 96., 112.));
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_i64gather_ps() {
+    fn test_mm512_mask_i64gather_ps() {
         let arr: [f32; 128] = core::array::from_fn(|i| i as f32);
         let src = _mm256_set1_ps(2.);
         let mask = 0b10101010;
         #[rustfmt::skip]
         let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
         // A multiplier of 4 is word-addressing
-        let r = _mm512_mask_i64gather_ps::<4>(src, mask, index, arr.as_ptr());
+        let r = unsafe { _mm512_mask_i64gather_ps::<4>(src, mask, index, arr.as_ptr()) };
         assert_eq_m256(r, _mm256_setr_ps(2., 16., 2., 48., 2., 80., 2., 112.));
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_i32gather_epi64() {
+    fn test_mm512_i32gather_epi64() {
         let mut arr = [0i64; 128];
         for i in 0..128i64 {
             arr[i as usize] = i;
         }
         // A multiplier of 8 is word-addressing
         let index = _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112);
-        let r = _mm512_i32gather_epi64::<8>(index, arr.as_ptr());
+        let r = unsafe { _mm512_i32gather_epi64::<8>(index, arr.as_ptr()) };
         assert_eq_m512i(r, _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112));
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_i32gather_epi64() {
+    fn test_mm512_mask_i32gather_epi64() {
         let mut arr = [0i64; 128];
         for i in 0..128i64 {
             arr[i as usize] = i;
@@ -7529,24 +7529,24 @@ mod tests {
         let mask = 0b10101010;
         let index = _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112);
         // A multiplier of 8 is word-addressing
-        let r = _mm512_mask_i32gather_epi64::<8>(src, mask, index, arr.as_ptr());
+        let r = unsafe { _mm512_mask_i32gather_epi64::<8>(src, mask, index, arr.as_ptr()) };
         assert_eq_m512i(r, _mm512_setr_epi64(2, 16, 2, 48, 2, 80, 2, 112));
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_i64gather_epi64() {
+    fn test_mm512_i64gather_epi64() {
         let mut arr = [0i64; 128];
         for i in 0..128i64 {
             arr[i as usize] = i;
         }
         // A multiplier of 8 is word-addressing
         let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
-        let r = _mm512_i64gather_epi64::<8>(index, arr.as_ptr());
+        let r = unsafe { _mm512_i64gather_epi64::<8>(index, arr.as_ptr()) };
         assert_eq_m512i(r, _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112));
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_i64gather_epi64() {
+    fn test_mm512_mask_i64gather_epi64() {
         let mut arr = [0i64; 128];
         for i in 0..128i64 {
             arr[i as usize] = i;
@@ -7555,24 +7555,24 @@ mod tests {
         let mask = 0b10101010;
         let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
         // A multiplier of 8 is word-addressing
-        let r = _mm512_mask_i64gather_epi64::<8>(src, mask, index, arr.as_ptr());
+        let r = unsafe { _mm512_mask_i64gather_epi64::<8>(src, mask, index, arr.as_ptr()) };
         assert_eq_m512i(r, _mm512_setr_epi64(2, 16, 2, 48, 2, 80, 2, 112));
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_i64gather_epi32() {
+    fn test_mm512_i64gather_epi32() {
         let mut arr = [0i64; 128];
         for i in 0..128i64 {
             arr[i as usize] = i;
         }
         // A multiplier of 8 is word-addressing
         let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
-        let r = _mm512_i64gather_epi32::<8>(index, arr.as_ptr() as *const i32);
+        let r = unsafe { _mm512_i64gather_epi32::<8>(index, arr.as_ptr() as *const i32) };
         assert_eq_m256i(r, _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112));
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_i64gather_epi32() {
+    fn test_mm512_mask_i64gather_epi32() {
         let mut arr = [0i64; 128];
         for i in 0..128i64 {
             arr[i as usize] = i;
@@ -7581,17 +7581,21 @@ mod tests {
         let mask = 0b10101010;
         let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
         // A multiplier of 8 is word-addressing
-        let r = _mm512_mask_i64gather_epi32::<8>(src, mask, index, arr.as_ptr() as *const i32);
+        let r = unsafe {
+            _mm512_mask_i64gather_epi32::<8>(src, mask, index, arr.as_ptr() as *const i32)
+        };
         assert_eq_m256i(r, _mm256_setr_epi32(2, 16, 2, 48, 2, 80, 2, 112));
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_i32scatter_pd() {
+    fn test_mm512_i32scatter_pd() {
         let mut arr = [0f64; 128];
         let index = _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112);
         let src = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
         // A multiplier of 8 is word-addressing
-        _mm512_i32scatter_pd::<8>(arr.as_mut_ptr(), index, src);
+        unsafe {
+            _mm512_i32scatter_pd::<8>(arr.as_mut_ptr(), index, src);
+        }
         let mut expected = [0f64; 128];
         for i in 0..8 {
             expected[i * 16] = (i + 1) as f64;
@@ -7600,13 +7604,15 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_i32scatter_pd() {
+    fn test_mm512_mask_i32scatter_pd() {
         let mut arr = [0f64; 128];
         let mask = 0b10101010;
         let index = _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112);
         let src = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
         // A multiplier of 8 is word-addressing
-        _mm512_mask_i32scatter_pd::<8>(arr.as_mut_ptr(), mask, index, src);
+        unsafe {
+            _mm512_mask_i32scatter_pd::<8>(arr.as_mut_ptr(), mask, index, src);
+        }
         let mut expected = [0f64; 128];
         for i in 0..4 {
             expected[i * 32 + 16] = 2. * (i + 1) as f64;
@@ -7615,12 +7621,14 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_i64scatter_pd() {
+    fn test_mm512_i64scatter_pd() {
         let mut arr = [0f64; 128];
         let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
         let src = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
         // A multiplier of 8 is word-addressing
-        _mm512_i64scatter_pd::<8>(arr.as_mut_ptr(), index, src);
+        unsafe {
+            _mm512_i64scatter_pd::<8>(arr.as_mut_ptr(), index, src);
+        }
         let mut expected = [0f64; 128];
         for i in 0..8 {
             expected[i * 16] = (i + 1) as f64;
@@ -7629,13 +7637,15 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_i64scatter_pd() {
+    fn test_mm512_mask_i64scatter_pd() {
         let mut arr = [0f64; 128];
         let mask = 0b10101010;
         let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
         let src = _mm512_setr_pd(1., 2., 3., 4., 5., 6., 7., 8.);
         // A multiplier of 8 is word-addressing
-        _mm512_mask_i64scatter_pd::<8>(arr.as_mut_ptr(), mask, index, src);
+        unsafe {
+            _mm512_mask_i64scatter_pd::<8>(arr.as_mut_ptr(), mask, index, src);
+        }
         let mut expected = [0f64; 128];
         for i in 0..4 {
             expected[i * 32 + 16] = 2. * (i + 1) as f64;
@@ -7644,12 +7654,14 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_i64scatter_ps() {
+    fn test_mm512_i64scatter_ps() {
         let mut arr = [0f32; 128];
         let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
         let src = _mm256_setr_ps(1., 2., 3., 4., 5., 6., 7., 8.);
         // A multiplier of 4 is word-addressing
-        _mm512_i64scatter_ps::<4>(arr.as_mut_ptr(), index, src);
+        unsafe {
+            _mm512_i64scatter_ps::<4>(arr.as_mut_ptr(), index, src);
+        }
         let mut expected = [0f32; 128];
         for i in 0..8 {
             expected[i * 16] = (i + 1) as f32;
@@ -7658,13 +7670,15 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_i64scatter_ps() {
+    fn test_mm512_mask_i64scatter_ps() {
         let mut arr = [0f32; 128];
         let mask = 0b10101010;
         let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
         let src = _mm256_setr_ps(1., 2., 3., 4., 5., 6., 7., 8.);
         // A multiplier of 4 is word-addressing
-        _mm512_mask_i64scatter_ps::<4>(arr.as_mut_ptr(), mask, index, src);
+        unsafe {
+            _mm512_mask_i64scatter_ps::<4>(arr.as_mut_ptr(), mask, index, src);
+        }
         let mut expected = [0f32; 128];
         for i in 0..4 {
             expected[i * 32 + 16] = 2. * (i + 1) as f32;
@@ -7673,12 +7687,14 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_i32scatter_epi64() {
+    fn test_mm512_i32scatter_epi64() {
         let mut arr = [0i64; 128];
         let index = _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112);
         let src = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
         // A multiplier of 8 is word-addressing
-        _mm512_i32scatter_epi64::<8>(arr.as_mut_ptr(), index, src);
+        unsafe {
+            _mm512_i32scatter_epi64::<8>(arr.as_mut_ptr(), index, src);
+        }
         let mut expected = [0i64; 128];
         for i in 0..8 {
             expected[i * 16] = (i + 1) as i64;
@@ -7687,13 +7703,15 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_i32scatter_epi64() {
+    fn test_mm512_mask_i32scatter_epi64() {
         let mut arr = [0i64; 128];
         let mask = 0b10101010;
         let index = _mm256_setr_epi32(0, 16, 32, 48, 64, 80, 96, 112);
         let src = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
         // A multiplier of 8 is word-addressing
-        _mm512_mask_i32scatter_epi64::<8>(arr.as_mut_ptr(), mask, index, src);
+        unsafe {
+            _mm512_mask_i32scatter_epi64::<8>(arr.as_mut_ptr(), mask, index, src);
+        }
         let mut expected = [0i64; 128];
         for i in 0..4 {
             expected[i * 32 + 16] = 2 * (i + 1) as i64;
@@ -7702,12 +7720,14 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_i64scatter_epi64() {
+    fn test_mm512_i64scatter_epi64() {
         let mut arr = [0i64; 128];
         let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
         let src = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
         // A multiplier of 8 is word-addressing
-        _mm512_i64scatter_epi64::<8>(arr.as_mut_ptr(), index, src);
+        unsafe {
+            _mm512_i64scatter_epi64::<8>(arr.as_mut_ptr(), index, src);
+        }
         let mut expected = [0i64; 128];
         for i in 0..8 {
             expected[i * 16] = (i + 1) as i64;
@@ -7716,13 +7736,15 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_i64scatter_epi64() {
+    fn test_mm512_mask_i64scatter_epi64() {
         let mut arr = [0i64; 128];
         let mask = 0b10101010;
         let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
         let src = _mm512_setr_epi64(1, 2, 3, 4, 5, 6, 7, 8);
         // A multiplier of 8 is word-addressing
-        _mm512_mask_i64scatter_epi64::<8>(arr.as_mut_ptr(), mask, index, src);
+        unsafe {
+            _mm512_mask_i64scatter_epi64::<8>(arr.as_mut_ptr(), mask, index, src);
+        }
         let mut expected = [0i64; 128];
         for i in 0..4 {
             expected[i * 32 + 16] = 2 * (i + 1) as i64;
@@ -7731,12 +7753,14 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_i64scatter_epi32() {
+    fn test_mm512_i64scatter_epi32() {
         let mut arr = [0i32; 128];
         let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
         let src = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8);
         // A multiplier of 4 is word-addressing
-        _mm512_i64scatter_epi32::<4>(arr.as_mut_ptr(), index, src);
+        unsafe {
+            _mm512_i64scatter_epi32::<4>(arr.as_mut_ptr(), index, src);
+        }
         let mut expected = [0i32; 128];
         for i in 0..8 {
             expected[i * 16] = (i + 1) as i32;
@@ -7745,13 +7769,15 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_i64scatter_epi32() {
+    fn test_mm512_mask_i64scatter_epi32() {
         let mut arr = [0i32; 128];
         let mask = 0b10101010;
         let index = _mm512_setr_epi64(0, 16, 32, 48, 64, 80, 96, 112);
         let src = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 8);
         // A multiplier of 4 is word-addressing
-        _mm512_mask_i64scatter_epi32::<4>(arr.as_mut_ptr(), mask, index, src);
+        unsafe {
+            _mm512_mask_i64scatter_epi32::<4>(arr.as_mut_ptr(), mask, index, src);
+        }
         let mut expected = [0i32; 128];
         for i in 0..4 {
             expected[i * 32 + 16] = 2 * (i + 1) as i32;
@@ -7760,559 +7786,640 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_i32logather_epi64() {
+    fn test_mm512_i32logather_epi64() {
         let base_addr: [i64; 8] = [1, 2, 3, 4, 5, 6, 7, 8];
         let vindex = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0, -1, -1, -1, -1, -1, -1, -1, -1);
-        let r = _mm512_i32logather_epi64::<8>(vindex, base_addr.as_ptr());
+        let r = unsafe { _mm512_i32logather_epi64::<8>(vindex, base_addr.as_ptr()) };
         let expected = _mm512_setr_epi64(2, 3, 4, 5, 6, 7, 8, 1);
         assert_eq_m512i(expected, r);
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_i32logather_epi64() {
+    fn test_mm512_mask_i32logather_epi64() {
         let base_addr: [i64; 8] = [1, 2, 3, 4, 5, 6, 7, 8];
         let src = _mm512_setr_epi64(9, 10, 11, 12, 13, 14, 15, 16);
         let vindex = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0, -1, -1, -1, -1, -1, -1, -1, -1);
-        let r = _mm512_mask_i32logather_epi64::<8>(src, 0b01010101, vindex, base_addr.as_ptr());
+        let r = unsafe {
+            _mm512_mask_i32logather_epi64::<8>(src, 0b01010101, vindex, base_addr.as_ptr())
+        };
         let expected = _mm512_setr_epi64(2, 10, 4, 12, 6, 14, 8, 16);
         assert_eq_m512i(expected, r);
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_i32logather_pd() {
+    fn test_mm512_i32logather_pd() {
         let base_addr: [f64; 8] = [1., 2., 3., 4., 5., 6., 7., 8.];
         let vindex = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0, -1, -1, -1, -1, -1, -1, -1, -1);
-        let r = _mm512_i32logather_pd::<8>(vindex, base_addr.as_ptr());
+        let r = unsafe { _mm512_i32logather_pd::<8>(vindex, base_addr.as_ptr()) };
         let expected = _mm512_setr_pd(2., 3., 4., 5., 6., 7., 8., 1.);
         assert_eq_m512d(expected, r);
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_i32logather_pd() {
+    fn test_mm512_mask_i32logather_pd() {
         let base_addr: [f64; 8] = [1., 2., 3., 4., 5., 6., 7., 8.];
         let src = _mm512_setr_pd(9., 10., 11., 12., 13., 14., 15., 16.);
         let vindex = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0, -1, -1, -1, -1, -1, -1, -1, -1);
-        let r = _mm512_mask_i32logather_pd::<8>(src, 0b01010101, vindex, base_addr.as_ptr());
+        let r =
+            unsafe { _mm512_mask_i32logather_pd::<8>(src, 0b01010101, vindex, base_addr.as_ptr()) };
         let expected = _mm512_setr_pd(2., 10., 4., 12., 6., 14., 8., 16.);
         assert_eq_m512d(expected, r);
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_i32loscatter_epi64() {
+    fn test_mm512_i32loscatter_epi64() {
         let mut base_addr: [i64; 8] = [0; 8];
         let vindex = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0, -1, -1, -1, -1, -1, -1, -1, -1);
         let src = _mm512_setr_epi64(2, 3, 4, 5, 6, 7, 8, 1);
-        _mm512_i32loscatter_epi64::<8>(base_addr.as_mut_ptr(), vindex, src);
+        unsafe {
+            _mm512_i32loscatter_epi64::<8>(base_addr.as_mut_ptr(), vindex, src);
+        }
         let expected = [1, 2, 3, 4, 5, 6, 7, 8];
         assert_eq!(expected, base_addr);
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_i32loscatter_epi64() {
+    fn test_mm512_mask_i32loscatter_epi64() {
         let mut base_addr: [i64; 8] = [0; 8];
         let vindex = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0, -1, -1, -1, -1, -1, -1, -1, -1);
         let src = _mm512_setr_epi64(2, 3, 4, 5, 6, 7, 8, 1);
-        _mm512_mask_i32loscatter_epi64::<8>(base_addr.as_mut_ptr(), 0b01010101, vindex, src);
+        unsafe {
+            _mm512_mask_i32loscatter_epi64::<8>(base_addr.as_mut_ptr(), 0b01010101, vindex, src);
+        }
         let expected = [0, 2, 0, 4, 0, 6, 0, 8];
         assert_eq!(expected, base_addr);
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_i32loscatter_pd() {
+    fn test_mm512_i32loscatter_pd() {
         let mut base_addr: [f64; 8] = [0.; 8];
         let vindex = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0, -1, -1, -1, -1, -1, -1, -1, -1);
         let src = _mm512_setr_pd(2., 3., 4., 5., 6., 7., 8., 1.);
-        _mm512_i32loscatter_pd::<8>(base_addr.as_mut_ptr(), vindex, src);
+        unsafe {
+            _mm512_i32loscatter_pd::<8>(base_addr.as_mut_ptr(), vindex, src);
+        }
         let expected = [1., 2., 3., 4., 5., 6., 7., 8.];
         assert_eq!(expected, base_addr);
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_i32loscatter_pd() {
+    fn test_mm512_mask_i32loscatter_pd() {
         let mut base_addr: [f64; 8] = [0.; 8];
         let vindex = _mm512_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0, -1, -1, -1, -1, -1, -1, -1, -1);
         let src = _mm512_setr_pd(2., 3., 4., 5., 6., 7., 8., 1.);
-        _mm512_mask_i32loscatter_pd::<8>(base_addr.as_mut_ptr(), 0b01010101, vindex, src);
+        unsafe {
+            _mm512_mask_i32loscatter_pd::<8>(base_addr.as_mut_ptr(), 0b01010101, vindex, src);
+        }
         let expected = [0., 2., 0., 4., 0., 6., 0., 8.];
         assert_eq!(expected, base_addr);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mmask_i32gather_epi32() {
+    fn test_mm_mmask_i32gather_epi32() {
         let base_addr: [i32; 4] = [1, 2, 3, 4];
         let src = _mm_setr_epi32(5, 6, 7, 8);
         let vindex = _mm_setr_epi32(1, 2, 3, 0);
-        let r = _mm_mmask_i32gather_epi32::<4>(src, 0b0101, vindex, base_addr.as_ptr());
+        let r = unsafe { _mm_mmask_i32gather_epi32::<4>(src, 0b0101, vindex, base_addr.as_ptr()) };
         let expected = _mm_setr_epi32(2, 6, 4, 8);
         assert_eq_m128i(expected, r);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mmask_i32gather_epi64() {
+    fn test_mm_mmask_i32gather_epi64() {
         let base_addr: [i64; 2] = [1, 2];
         let src = _mm_setr_epi64x(5, 6);
         let vindex = _mm_setr_epi32(1, 0, -1, -1);
-        let r = _mm_mmask_i32gather_epi64::<8>(src, 0b01, vindex, base_addr.as_ptr());
+        let r = unsafe { _mm_mmask_i32gather_epi64::<8>(src, 0b01, vindex, base_addr.as_ptr()) };
         let expected = _mm_setr_epi64x(2, 6);
         assert_eq_m128i(expected, r);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mmask_i32gather_pd() {
+    fn test_mm_mmask_i32gather_pd() {
         let base_addr: [f64; 2] = [1., 2.];
         let src = _mm_setr_pd(5., 6.);
         let vindex = _mm_setr_epi32(1, 0, -1, -1);
-        let r = _mm_mmask_i32gather_pd::<8>(src, 0b01, vindex, base_addr.as_ptr());
+        let r = unsafe { _mm_mmask_i32gather_pd::<8>(src, 0b01, vindex, base_addr.as_ptr()) };
         let expected = _mm_setr_pd(2., 6.);
         assert_eq_m128d(expected, r);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mmask_i32gather_ps() {
+    fn test_mm_mmask_i32gather_ps() {
         let base_addr: [f32; 4] = [1., 2., 3., 4.];
         let src = _mm_setr_ps(5., 6., 7., 8.);
         let vindex = _mm_setr_epi32(1, 2, 3, 0);
-        let r = _mm_mmask_i32gather_ps::<4>(src, 0b0101, vindex, base_addr.as_ptr());
+        let r = unsafe { _mm_mmask_i32gather_ps::<4>(src, 0b0101, vindex, base_addr.as_ptr()) };
         let expected = _mm_setr_ps(2., 6., 4., 8.);
         assert_eq_m128(expected, r);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mmask_i64gather_epi32() {
+    fn test_mm_mmask_i64gather_epi32() {
         let base_addr: [i32; 2] = [1, 2];
         let src = _mm_setr_epi32(5, 6, 7, 8);
         let vindex = _mm_setr_epi64x(1, 0);
-        let r = _mm_mmask_i64gather_epi32::<4>(src, 0b01, vindex, base_addr.as_ptr());
+        let r = unsafe { _mm_mmask_i64gather_epi32::<4>(src, 0b01, vindex, base_addr.as_ptr()) };
         let expected = _mm_setr_epi32(2, 6, 0, 0);
         assert_eq_m128i(expected, r);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mmask_i64gather_epi64() {
+    fn test_mm_mmask_i64gather_epi64() {
         let base_addr: [i64; 2] = [1, 2];
         let src = _mm_setr_epi64x(5, 6);
         let vindex = _mm_setr_epi64x(1, 0);
-        let r = _mm_mmask_i64gather_epi64::<8>(src, 0b01, vindex, base_addr.as_ptr());
+        let r = unsafe { _mm_mmask_i64gather_epi64::<8>(src, 0b01, vindex, base_addr.as_ptr()) };
         let expected = _mm_setr_epi64x(2, 6);
         assert_eq_m128i(expected, r);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mmask_i64gather_pd() {
+    fn test_mm_mmask_i64gather_pd() {
         let base_addr: [f64; 2] = [1., 2.];
         let src = _mm_setr_pd(5., 6.);
         let vindex = _mm_setr_epi64x(1, 0);
-        let r = _mm_mmask_i64gather_pd::<8>(src, 0b01, vindex, base_addr.as_ptr());
+        let r = unsafe { _mm_mmask_i64gather_pd::<8>(src, 0b01, vindex, base_addr.as_ptr()) };
         let expected = _mm_setr_pd(2., 6.);
         assert_eq_m128d(expected, r);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mmask_i64gather_ps() {
+    fn test_mm_mmask_i64gather_ps() {
         let base_addr: [f32; 2] = [1., 2.];
         let src = _mm_setr_ps(5., 6., 7., 8.);
         let vindex = _mm_setr_epi64x(1, 0);
-        let r = _mm_mmask_i64gather_ps::<4>(src, 0b01, vindex, base_addr.as_ptr());
+        let r = unsafe { _mm_mmask_i64gather_ps::<4>(src, 0b01, vindex, base_addr.as_ptr()) };
         let expected = _mm_setr_ps(2., 6., 0., 0.);
         assert_eq_m128(expected, r);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mmask_i32gather_epi32() {
+    fn test_mm256_mmask_i32gather_epi32() {
         let base_addr: [i32; 8] = [1, 2, 3, 4, 5, 6, 7, 8];
         let src = _mm256_setr_epi32(9, 10, 11, 12, 13, 14, 15, 16);
         let vindex = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0);
-        let r = _mm256_mmask_i32gather_epi32::<4>(src, 0b01010101, vindex, base_addr.as_ptr());
+        let r = unsafe {
+            _mm256_mmask_i32gather_epi32::<4>(src, 0b01010101, vindex, base_addr.as_ptr())
+        };
         let expected = _mm256_setr_epi32(2, 10, 4, 12, 6, 14, 8, 16);
         assert_eq_m256i(expected, r);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mmask_i32gather_epi64() {
+    fn test_mm256_mmask_i32gather_epi64() {
         let base_addr: [i64; 4] = [1, 2, 3, 4];
         let src = _mm256_setr_epi64x(9, 10, 11, 12);
         let vindex = _mm_setr_epi32(1, 2, 3, 4);
-        let r = _mm256_mmask_i32gather_epi64::<8>(src, 0b0101, vindex, base_addr.as_ptr());
+        let r =
+            unsafe { _mm256_mmask_i32gather_epi64::<8>(src, 0b0101, vindex, base_addr.as_ptr()) };
         let expected = _mm256_setr_epi64x(2, 10, 4, 12);
         assert_eq_m256i(expected, r);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mmask_i32gather_pd() {
+    fn test_mm256_mmask_i32gather_pd() {
         let base_addr: [f64; 4] = [1., 2., 3., 4.];
         let src = _mm256_setr_pd(9., 10., 11., 12.);
         let vindex = _mm_setr_epi32(1, 2, 3, 4);
-        let r = _mm256_mmask_i32gather_pd::<8>(src, 0b0101, vindex, base_addr.as_ptr());
+        let r = unsafe { _mm256_mmask_i32gather_pd::<8>(src, 0b0101, vindex, base_addr.as_ptr()) };
         let expected = _mm256_setr_pd(2., 10., 4., 12.);
         assert_eq_m256d(expected, r);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mmask_i32gather_ps() {
+    fn test_mm256_mmask_i32gather_ps() {
         let base_addr: [f32; 8] = [1., 2., 3., 4., 5., 6., 7., 8.];
         let src = _mm256_setr_ps(9., 10., 11., 12., 13., 14., 15., 16.);
         let vindex = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0);
-        let r = _mm256_mmask_i32gather_ps::<4>(src, 0b01010101, vindex, base_addr.as_ptr());
+        let r =
+            unsafe { _mm256_mmask_i32gather_ps::<4>(src, 0b01010101, vindex, base_addr.as_ptr()) };
         let expected = _mm256_setr_ps(2., 10., 4., 12., 6., 14., 8., 16.);
         assert_eq_m256(expected, r);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mmask_i64gather_epi32() {
+    fn test_mm256_mmask_i64gather_epi32() {
         let base_addr: [i32; 4] = [1, 2, 3, 4];
         let src = _mm_setr_epi32(9, 10, 11, 12);
         let vindex = _mm256_setr_epi64x(1, 2, 3, 0);
-        let r = _mm256_mmask_i64gather_epi32::<4>(src, 0b0101, vindex, base_addr.as_ptr());
+        let r =
+            unsafe { _mm256_mmask_i64gather_epi32::<4>(src, 0b0101, vindex, base_addr.as_ptr()) };
         let expected = _mm_setr_epi32(2, 10, 4, 12);
         assert_eq_m128i(expected, r);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mmask_i64gather_epi64() {
+    fn test_mm256_mmask_i64gather_epi64() {
         let base_addr: [i64; 4] = [1, 2, 3, 4];
         let src = _mm256_setr_epi64x(9, 10, 11, 12);
         let vindex = _mm256_setr_epi64x(1, 2, 3, 0);
-        let r = _mm256_mmask_i64gather_epi64::<8>(src, 0b0101, vindex, base_addr.as_ptr());
+        let r =
+            unsafe { _mm256_mmask_i64gather_epi64::<8>(src, 0b0101, vindex, base_addr.as_ptr()) };
         let expected = _mm256_setr_epi64x(2, 10, 4, 12);
         assert_eq_m256i(expected, r);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mmask_i64gather_pd() {
+    fn test_mm256_mmask_i64gather_pd() {
         let base_addr: [f64; 4] = [1., 2., 3., 4.];
         let src = _mm256_setr_pd(9., 10., 11., 12.);
         let vindex = _mm256_setr_epi64x(1, 2, 3, 0);
-        let r = _mm256_mmask_i64gather_pd::<8>(src, 0b0101, vindex, base_addr.as_ptr());
+        let r = unsafe { _mm256_mmask_i64gather_pd::<8>(src, 0b0101, vindex, base_addr.as_ptr()) };
         let expected = _mm256_setr_pd(2., 10., 4., 12.);
         assert_eq_m256d(expected, r);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mmask_i64gather_ps() {
+    fn test_mm256_mmask_i64gather_ps() {
         let base_addr: [f32; 4] = [1., 2., 3., 4.];
         let src = _mm_setr_ps(9., 10., 11., 12.);
         let vindex = _mm256_setr_epi64x(1, 2, 3, 0);
-        let r = _mm256_mmask_i64gather_ps::<4>(src, 0b0101, vindex, base_addr.as_ptr());
+        let r = unsafe { _mm256_mmask_i64gather_ps::<4>(src, 0b0101, vindex, base_addr.as_ptr()) };
         let expected = _mm_setr_ps(2., 10., 4., 12.);
         assert_eq_m128(expected, r);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_i32scatter_epi32() {
+    fn test_mm_i32scatter_epi32() {
         let mut base_addr: [i32; 4] = [0; 4];
         let vindex = _mm_setr_epi32(1, 2, 3, 0);
         let src = _mm_setr_epi32(2, 3, 4, 1);
-        _mm_i32scatter_epi32::<4>(base_addr.as_mut_ptr(), vindex, src);
+        unsafe {
+            _mm_i32scatter_epi32::<4>(base_addr.as_mut_ptr(), vindex, src);
+        }
         let expected = [1, 2, 3, 4];
         assert_eq!(expected, base_addr);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_i32scatter_epi32() {
+    fn test_mm_mask_i32scatter_epi32() {
         let mut base_addr: [i32; 4] = [0; 4];
         let vindex = _mm_setr_epi32(1, 2, 3, 0);
         let src = _mm_setr_epi32(2, 3, 4, 1);
-        _mm_mask_i32scatter_epi32::<4>(base_addr.as_mut_ptr(), 0b0101, vindex, src);
+        unsafe {
+            _mm_mask_i32scatter_epi32::<4>(base_addr.as_mut_ptr(), 0b0101, vindex, src);
+        }
         let expected = [0, 2, 0, 4];
         assert_eq!(expected, base_addr);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_i32scatter_epi64() {
+    fn test_mm_i32scatter_epi64() {
         let mut base_addr: [i64; 2] = [0; 2];
         let vindex = _mm_setr_epi32(1, 0, -1, -1);
         let src = _mm_setr_epi64x(2, 1);
-        _mm_i32scatter_epi64::<8>(base_addr.as_mut_ptr(), vindex, src);
+        unsafe {
+            _mm_i32scatter_epi64::<8>(base_addr.as_mut_ptr(), vindex, src);
+        }
         let expected = [1, 2];
         assert_eq!(expected, base_addr);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_i32scatter_epi64() {
+    fn test_mm_mask_i32scatter_epi64() {
         let mut base_addr: [i64; 2] = [0; 2];
         let vindex = _mm_setr_epi32(1, 0, -1, -1);
         let src = _mm_setr_epi64x(2, 1);
-        _mm_mask_i32scatter_epi64::<8>(base_addr.as_mut_ptr(), 0b01, vindex, src);
+        unsafe {
+            _mm_mask_i32scatter_epi64::<8>(base_addr.as_mut_ptr(), 0b01, vindex, src);
+        }
         let expected = [0, 2];
         assert_eq!(expected, base_addr);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_i32scatter_pd() {
+    fn test_mm_i32scatter_pd() {
         let mut base_addr: [f64; 2] = [0.; 2];
         let vindex = _mm_setr_epi32(1, 0, -1, -1);
         let src = _mm_setr_pd(2., 1.);
-        _mm_i32scatter_pd::<8>(base_addr.as_mut_ptr(), vindex, src);
+        unsafe {
+            _mm_i32scatter_pd::<8>(base_addr.as_mut_ptr(), vindex, src);
+        }
         let expected = [1., 2.];
         assert_eq!(expected, base_addr);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_i32scatter_pd() {
+    fn test_mm_mask_i32scatter_pd() {
         let mut base_addr: [f64; 2] = [0.; 2];
         let vindex = _mm_setr_epi32(1, 0, -1, -1);
         let src = _mm_setr_pd(2., 1.);
-        _mm_mask_i32scatter_pd::<8>(base_addr.as_mut_ptr(), 0b01, vindex, src);
+        unsafe {
+            _mm_mask_i32scatter_pd::<8>(base_addr.as_mut_ptr(), 0b01, vindex, src);
+        }
         let expected = [0., 2.];
         assert_eq!(expected, base_addr);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_i32scatter_ps() {
+    fn test_mm_i32scatter_ps() {
         let mut base_addr: [f32; 4] = [0.; 4];
         let vindex = _mm_setr_epi32(1, 2, 3, 0);
         let src = _mm_setr_ps(2., 3., 4., 1.);
-        _mm_i32scatter_ps::<4>(base_addr.as_mut_ptr(), vindex, src);
+        unsafe {
+            _mm_i32scatter_ps::<4>(base_addr.as_mut_ptr(), vindex, src);
+        }
         let expected = [1., 2., 3., 4.];
         assert_eq!(expected, base_addr);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_i32scatter_ps() {
+    fn test_mm_mask_i32scatter_ps() {
         let mut base_addr: [f32; 4] = [0.; 4];
         let vindex = _mm_setr_epi32(1, 2, 3, 0);
         let src = _mm_setr_ps(2., 3., 4., 1.);
-        _mm_mask_i32scatter_ps::<4>(base_addr.as_mut_ptr(), 0b0101, vindex, src);
+        unsafe {
+            _mm_mask_i32scatter_ps::<4>(base_addr.as_mut_ptr(), 0b0101, vindex, src);
+        }
         let expected = [0., 2., 0., 4.];
         assert_eq!(expected, base_addr);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_i64scatter_epi32() {
+    fn test_mm_i64scatter_epi32() {
         let mut base_addr: [i32; 2] = [0; 2];
         let vindex = _mm_setr_epi64x(1, 0);
         let src = _mm_setr_epi32(2, 1, -1, -1);
-        _mm_i64scatter_epi32::<4>(base_addr.as_mut_ptr(), vindex, src);
+        unsafe {
+            _mm_i64scatter_epi32::<4>(base_addr.as_mut_ptr(), vindex, src);
+        }
         let expected = [1, 2];
         assert_eq!(expected, base_addr);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_i64scatter_epi32() {
+    fn test_mm_mask_i64scatter_epi32() {
         let mut base_addr: [i32; 2] = [0; 2];
         let vindex = _mm_setr_epi64x(1, 0);
         let src = _mm_setr_epi32(2, 1, -1, -1);
-        _mm_mask_i64scatter_epi32::<4>(base_addr.as_mut_ptr(), 0b01, vindex, src);
+        unsafe {
+            _mm_mask_i64scatter_epi32::<4>(base_addr.as_mut_ptr(), 0b01, vindex, src);
+        }
         let expected = [0, 2];
         assert_eq!(expected, base_addr);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_i64scatter_epi64() {
+    fn test_mm_i64scatter_epi64() {
         let mut base_addr: [i64; 2] = [0; 2];
         let vindex = _mm_setr_epi64x(1, 0);
         let src = _mm_setr_epi64x(2, 1);
-        _mm_i64scatter_epi64::<8>(base_addr.as_mut_ptr(), vindex, src);
+        unsafe {
+            _mm_i64scatter_epi64::<8>(base_addr.as_mut_ptr(), vindex, src);
+        }
         let expected = [1, 2];
         assert_eq!(expected, base_addr);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_i64scatter_epi64() {
+    fn test_mm_mask_i64scatter_epi64() {
         let mut base_addr: [i64; 2] = [0; 2];
         let vindex = _mm_setr_epi64x(1, 0);
         let src = _mm_setr_epi64x(2, 1);
-        _mm_mask_i64scatter_epi64::<8>(base_addr.as_mut_ptr(), 0b01, vindex, src);
+        unsafe {
+            _mm_mask_i64scatter_epi64::<8>(base_addr.as_mut_ptr(), 0b01, vindex, src);
+        }
         let expected = [0, 2];
         assert_eq!(expected, base_addr);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_i64scatter_pd() {
+    fn test_mm_i64scatter_pd() {
         let mut base_addr: [f64; 2] = [0.; 2];
         let vindex = _mm_setr_epi64x(1, 0);
         let src = _mm_setr_pd(2., 1.);
-        _mm_i64scatter_pd::<8>(base_addr.as_mut_ptr(), vindex, src);
+        unsafe {
+            _mm_i64scatter_pd::<8>(base_addr.as_mut_ptr(), vindex, src);
+        }
         let expected = [1., 2.];
         assert_eq!(expected, base_addr);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_i64scatter_pd() {
+    fn test_mm_mask_i64scatter_pd() {
         let mut base_addr: [f64; 2] = [0.; 2];
         let vindex = _mm_setr_epi64x(1, 0);
         let src = _mm_setr_pd(2., 1.);
-        _mm_mask_i64scatter_pd::<8>(base_addr.as_mut_ptr(), 0b01, vindex, src);
+        unsafe {
+            _mm_mask_i64scatter_pd::<8>(base_addr.as_mut_ptr(), 0b01, vindex, src);
+        }
         let expected = [0., 2.];
         assert_eq!(expected, base_addr);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_i64scatter_ps() {
+    fn test_mm_i64scatter_ps() {
         let mut base_addr: [f32; 2] = [0.; 2];
         let vindex = _mm_setr_epi64x(1, 0);
         let src = _mm_setr_ps(2., 1., -1., -1.);
-        _mm_i64scatter_ps::<4>(base_addr.as_mut_ptr(), vindex, src);
+        unsafe {
+            _mm_i64scatter_ps::<4>(base_addr.as_mut_ptr(), vindex, src);
+        }
         let expected = [1., 2.];
         assert_eq!(expected, base_addr);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_i64scatter_ps() {
+    fn test_mm_mask_i64scatter_ps() {
         let mut base_addr: [f32; 2] = [0.; 2];
         let vindex = _mm_setr_epi64x(1, 0);
         let src = _mm_setr_ps(2., 1., -1., -1.);
-        _mm_mask_i64scatter_ps::<4>(base_addr.as_mut_ptr(), 0b01, vindex, src);
+        unsafe {
+            _mm_mask_i64scatter_ps::<4>(base_addr.as_mut_ptr(), 0b01, vindex, src);
+        }
         let expected = [0., 2.];
         assert_eq!(expected, base_addr);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_i32scatter_epi32() {
+    fn test_mm256_i32scatter_epi32() {
         let mut base_addr: [i32; 8] = [0; 8];
         let vindex = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0);
         let src = _mm256_setr_epi32(2, 3, 4, 5, 6, 7, 8, 1);
-        _mm256_i32scatter_epi32::<4>(base_addr.as_mut_ptr(), vindex, src);
+        unsafe {
+            _mm256_i32scatter_epi32::<4>(base_addr.as_mut_ptr(), vindex, src);
+        }
         let expected = [1, 2, 3, 4, 5, 6, 7, 8];
         assert_eq!(expected, base_addr);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_i32scatter_epi32() {
+    fn test_mm256_mask_i32scatter_epi32() {
         let mut base_addr: [i32; 8] = [0; 8];
         let vindex = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0);
         let src = _mm256_setr_epi32(2, 3, 4, 5, 6, 7, 8, 1);
-        _mm256_mask_i32scatter_epi32::<4>(base_addr.as_mut_ptr(), 0b01010101, vindex, src);
+        unsafe {
+            _mm256_mask_i32scatter_epi32::<4>(base_addr.as_mut_ptr(), 0b01010101, vindex, src);
+        }
         let expected = [0, 2, 0, 4, 0, 6, 0, 8];
         assert_eq!(expected, base_addr);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_i32scatter_epi64() {
+    fn test_mm256_i32scatter_epi64() {
         let mut base_addr: [i64; 4] = [0; 4];
         let vindex = _mm_setr_epi32(1, 2, 3, 0);
         let src = _mm256_setr_epi64x(2, 3, 4, 1);
-        _mm256_i32scatter_epi64::<8>(base_addr.as_mut_ptr(), vindex, src);
+        unsafe {
+            _mm256_i32scatter_epi64::<8>(base_addr.as_mut_ptr(), vindex, src);
+        }
         let expected = [1, 2, 3, 4];
         assert_eq!(expected, base_addr);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_i32scatter_epi64() {
+    fn test_mm256_mask_i32scatter_epi64() {
         let mut base_addr: [i64; 4] = [0; 4];
         let vindex = _mm_setr_epi32(1, 2, 3, 0);
         let src = _mm256_setr_epi64x(2, 3, 4, 1);
-        _mm256_mask_i32scatter_epi64::<8>(base_addr.as_mut_ptr(), 0b0101, vindex, src);
+        unsafe {
+            _mm256_mask_i32scatter_epi64::<8>(base_addr.as_mut_ptr(), 0b0101, vindex, src);
+        }
         let expected = [0, 2, 0, 4];
         assert_eq!(expected, base_addr);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_i32scatter_pd() {
+    fn test_mm256_i32scatter_pd() {
         let mut base_addr: [f64; 4] = [0.; 4];
         let vindex = _mm_setr_epi32(1, 2, 3, 0);
         let src = _mm256_setr_pd(2., 3., 4., 1.);
-        _mm256_i32scatter_pd::<8>(base_addr.as_mut_ptr(), vindex, src);
+        unsafe {
+            _mm256_i32scatter_pd::<8>(base_addr.as_mut_ptr(), vindex, src);
+        }
         let expected = [1., 2., 3., 4.];
         assert_eq!(expected, base_addr);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_i32scatter_pd() {
+    fn test_mm256_mask_i32scatter_pd() {
         let mut base_addr: [f64; 4] = [0.; 4];
         let vindex = _mm_setr_epi32(1, 2, 3, 0);
         let src = _mm256_setr_pd(2., 3., 4., 1.);
-        _mm256_mask_i32scatter_pd::<8>(base_addr.as_mut_ptr(), 0b0101, vindex, src);
+        unsafe {
+            _mm256_mask_i32scatter_pd::<8>(base_addr.as_mut_ptr(), 0b0101, vindex, src);
+        }
         let expected = [0., 2., 0., 4.];
         assert_eq!(expected, base_addr);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_i32scatter_ps() {
+    fn test_mm256_i32scatter_ps() {
         let mut base_addr: [f32; 8] = [0.; 8];
         let vindex = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0);
         let src = _mm256_setr_ps(2., 3., 4., 5., 6., 7., 8., 1.);
-        _mm256_i32scatter_ps::<4>(base_addr.as_mut_ptr(), vindex, src);
+        unsafe {
+            _mm256_i32scatter_ps::<4>(base_addr.as_mut_ptr(), vindex, src);
+        }
         let expected = [1., 2., 3., 4., 5., 6., 7., 8.];
         assert_eq!(expected, base_addr);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_i32scatter_ps() {
+    fn test_mm256_mask_i32scatter_ps() {
         let mut base_addr: [f32; 8] = [0.; 8];
         let vindex = _mm256_setr_epi32(1, 2, 3, 4, 5, 6, 7, 0);
         let src = _mm256_setr_ps(2., 3., 4., 5., 6., 7., 8., 1.);
-        _mm256_mask_i32scatter_ps::<4>(base_addr.as_mut_ptr(), 0b01010101, vindex, src);
+        unsafe {
+            _mm256_mask_i32scatter_ps::<4>(base_addr.as_mut_ptr(), 0b01010101, vindex, src);
+        }
         let expected = [0., 2., 0., 4., 0., 6., 0., 8.];
         assert_eq!(expected, base_addr);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_i64scatter_epi32() {
+    fn test_mm256_i64scatter_epi32() {
         let mut base_addr: [i32; 4] = [0; 4];
         let vindex = _mm256_setr_epi64x(1, 2, 3, 0);
         let src = _mm_setr_epi32(2, 3, 4, 1);
-        _mm256_i64scatter_epi32::<4>(base_addr.as_mut_ptr(), vindex, src);
+        unsafe {
+            _mm256_i64scatter_epi32::<4>(base_addr.as_mut_ptr(), vindex, src);
+        }
         let expected = [1, 2, 3, 4];
         assert_eq!(expected, base_addr);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_i64scatter_epi32() {
+    fn test_mm256_mask_i64scatter_epi32() {
         let mut base_addr: [i32; 4] = [0; 4];
         let vindex = _mm256_setr_epi64x(1, 2, 3, 0);
         let src = _mm_setr_epi32(2, 3, 4, 1);
-        _mm256_mask_i64scatter_epi32::<4>(base_addr.as_mut_ptr(), 0b0101, vindex, src);
+        unsafe {
+            _mm256_mask_i64scatter_epi32::<4>(base_addr.as_mut_ptr(), 0b0101, vindex, src);
+        }
         let expected = [0, 2, 0, 4];
         assert_eq!(expected, base_addr);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_i64scatter_epi64() {
+    fn test_mm256_i64scatter_epi64() {
         let mut base_addr: [i64; 4] = [0; 4];
         let vindex = _mm256_setr_epi64x(1, 2, 3, 0);
         let src = _mm256_setr_epi64x(2, 3, 4, 1);
-        _mm256_i64scatter_epi64::<8>(base_addr.as_mut_ptr(), vindex, src);
+        unsafe {
+            _mm256_i64scatter_epi64::<8>(base_addr.as_mut_ptr(), vindex, src);
+        }
         let expected = [1, 2, 3, 4];
         assert_eq!(expected, base_addr);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_i64scatter_epi64() {
+    fn test_mm256_mask_i64scatter_epi64() {
         let mut base_addr: [i64; 4] = [0; 4];
         let vindex = _mm256_setr_epi64x(1, 2, 3, 0);
         let src = _mm256_setr_epi64x(2, 3, 4, 1);
-        _mm256_mask_i64scatter_epi64::<8>(base_addr.as_mut_ptr(), 0b0101, vindex, src);
+        unsafe {
+            _mm256_mask_i64scatter_epi64::<8>(base_addr.as_mut_ptr(), 0b0101, vindex, src);
+        }
         let expected = [0, 2, 0, 4];
         assert_eq!(expected, base_addr);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_i64scatter_pd() {
+    fn test_mm256_i64scatter_pd() {
         let mut base_addr: [f64; 4] = [0.; 4];
         let vindex = _mm256_setr_epi64x(1, 2, 3, 0);
         let src = _mm256_setr_pd(2., 3., 4., 1.);
-        _mm256_i64scatter_pd::<8>(base_addr.as_mut_ptr(), vindex, src);
+        unsafe {
+            _mm256_i64scatter_pd::<8>(base_addr.as_mut_ptr(), vindex, src);
+        }
         let expected = [1., 2., 3., 4.];
         assert_eq!(expected, base_addr);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_i64scatter_pd() {
+    fn test_mm256_mask_i64scatter_pd() {
         let mut base_addr: [f64; 4] = [0.; 4];
         let vindex = _mm256_setr_epi64x(1, 2, 3, 0);
         let src = _mm256_setr_pd(2., 3., 4., 1.);
-        _mm256_mask_i64scatter_pd::<8>(base_addr.as_mut_ptr(), 0b0101, vindex, src);
+        unsafe {
+            _mm256_mask_i64scatter_pd::<8>(base_addr.as_mut_ptr(), 0b0101, vindex, src);
+        }
         let expected = [0., 2., 0., 4.];
         assert_eq!(expected, base_addr);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_i64scatter_ps() {
+    fn test_mm256_i64scatter_ps() {
         let mut base_addr: [f32; 4] = [0.; 4];
         let vindex = _mm256_setr_epi64x(1, 2, 3, 0);
         let src = _mm_setr_ps(2., 3., 4., 1.);
-        _mm256_i64scatter_ps::<4>(base_addr.as_mut_ptr(), vindex, src);
+        unsafe {
+            _mm256_i64scatter_ps::<4>(base_addr.as_mut_ptr(), vindex, src);
+        }
         let expected = [1., 2., 3., 4.];
         assert_eq!(expected, base_addr);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_i64scatter_ps() {
+    fn test_mm256_mask_i64scatter_ps() {
         let mut base_addr: [f32; 4] = [0.; 4];
         let vindex = _mm256_setr_epi64x(1, 2, 3, 0);
         let src = _mm_setr_ps(2., 3., 4., 1.);
-        _mm256_mask_i64scatter_ps::<4>(base_addr.as_mut_ptr(), 0b0101, vindex, src);
+        unsafe {
+            _mm256_mask_i64scatter_ps::<4>(base_addr.as_mut_ptr(), 0b0101, vindex, src);
+        }
         let expected = [0., 2., 0., 4.];
         assert_eq!(expected, base_addr);
     }
@@ -12168,100 +12275,116 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_loadu_epi64() {
+    const fn test_mm512_loadu_epi64() {
         let a = &[4, 3, 2, 5, -8, -9, -64, -50];
         let p = a.as_ptr();
-        let r = _mm512_loadu_epi64(black_box(p));
+        let r = unsafe { _mm512_loadu_epi64(black_box(p)) };
         let e = _mm512_setr_epi64(4, 3, 2, 5, -8, -9, -64, -50);
         assert_eq_m512i(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_loadu_epi64() {
+    const fn test_mm256_loadu_epi64() {
         let a = &[4, 3, 2, 5];
         let p = a.as_ptr();
-        let r = _mm256_loadu_epi64(black_box(p));
+        let r = unsafe { _mm256_loadu_epi64(black_box(p)) };
         let e = _mm256_setr_epi64x(4, 3, 2, 5);
         assert_eq_m256i(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_loadu_epi64() {
+    const fn test_mm_loadu_epi64() {
         let a = &[4, 3];
         let p = a.as_ptr();
-        let r = _mm_loadu_epi64(black_box(p));
+        let r = unsafe { _mm_loadu_epi64(black_box(p)) };
         let e = _mm_setr_epi64x(4, 3);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cvtepi64_storeu_epi16() {
+    fn test_mm512_mask_cvtepi64_storeu_epi16() {
         let a = _mm512_set1_epi64(9);
         let mut r = _mm_undefined_si128();
-        _mm512_mask_cvtepi64_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a);
+        unsafe {
+            _mm512_mask_cvtepi64_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a);
+        }
         let e = _mm_set1_epi16(9);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_cvtepi64_storeu_epi16() {
+    fn test_mm256_mask_cvtepi64_storeu_epi16() {
         let a = _mm256_set1_epi64x(9);
         let mut r = _mm_set1_epi16(0);
-        _mm256_mask_cvtepi64_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a);
+        unsafe {
+            _mm256_mask_cvtepi64_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a);
+        }
         let e = _mm_set_epi16(0, 0, 0, 0, 9, 9, 9, 9);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_cvtepi64_storeu_epi16() {
+    fn test_mm_mask_cvtepi64_storeu_epi16() {
         let a = _mm_set1_epi64x(9);
         let mut r = _mm_set1_epi16(0);
-        _mm_mask_cvtepi64_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a);
+        unsafe {
+            _mm_mask_cvtepi64_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a);
+        }
         let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, 9, 9);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cvtsepi64_storeu_epi16() {
+    fn test_mm512_mask_cvtsepi64_storeu_epi16() {
         let a = _mm512_set1_epi64(i64::MAX);
         let mut r = _mm_undefined_si128();
-        _mm512_mask_cvtsepi64_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a);
+        unsafe {
+            _mm512_mask_cvtsepi64_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a);
+        }
         let e = _mm_set1_epi16(i16::MAX);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_cvtsepi64_storeu_epi16() {
+    fn test_mm256_mask_cvtsepi64_storeu_epi16() {
         let a = _mm256_set1_epi64x(i64::MAX);
         let mut r = _mm_set1_epi16(0);
-        _mm256_mask_cvtsepi64_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a);
+        unsafe {
+            _mm256_mask_cvtsepi64_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a);
+        }
         let e = _mm_set_epi16(0, 0, 0, 0, i16::MAX, i16::MAX, i16::MAX, i16::MAX);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_cvtsepi64_storeu_epi16() {
+    fn test_mm_mask_cvtsepi64_storeu_epi16() {
         let a = _mm_set1_epi64x(i64::MAX);
         let mut r = _mm_set1_epi16(0);
-        _mm_mask_cvtsepi64_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a);
+        unsafe {
+            _mm_mask_cvtsepi64_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a);
+        }
         let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, i16::MAX, i16::MAX);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cvtusepi64_storeu_epi16() {
+    fn test_mm512_mask_cvtusepi64_storeu_epi16() {
         let a = _mm512_set1_epi64(i64::MAX);
         let mut r = _mm_undefined_si128();
-        _mm512_mask_cvtusepi64_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a);
+        unsafe {
+            _mm512_mask_cvtusepi64_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a);
+        }
         let e = _mm_set1_epi16(u16::MAX as i16);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_cvtusepi64_storeu_epi16() {
+    fn test_mm256_mask_cvtusepi64_storeu_epi16() {
         let a = _mm256_set1_epi64x(i64::MAX);
         let mut r = _mm_set1_epi16(0);
-        _mm256_mask_cvtusepi64_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a);
+        unsafe {
+            _mm256_mask_cvtusepi64_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a);
+        }
         let e = _mm_set_epi16(
             0,
             0,
@@ -12276,46 +12399,56 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_cvtusepi64_storeu_epi16() {
+    fn test_mm_mask_cvtusepi64_storeu_epi16() {
         let a = _mm_set1_epi64x(i64::MAX);
         let mut r = _mm_set1_epi16(0);
-        _mm_mask_cvtusepi64_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a);
+        unsafe {
+            _mm_mask_cvtusepi64_storeu_epi16(&mut r as *mut _ as *mut i16, 0b11111111, a);
+        }
         let e = _mm_set_epi16(0, 0, 0, 0, 0, 0, u16::MAX as i16, u16::MAX as i16);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cvtepi64_storeu_epi8() {
+    fn test_mm512_mask_cvtepi64_storeu_epi8() {
         let a = _mm512_set1_epi64(9);
         let mut r = _mm_set1_epi8(0);
-        _mm512_mask_cvtepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
+        unsafe {
+            _mm512_mask_cvtepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
+        }
         let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 9, 9, 9, 9, 9, 9, 9, 9);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_cvtepi64_storeu_epi8() {
+    fn test_mm256_mask_cvtepi64_storeu_epi8() {
         let a = _mm256_set1_epi64x(9);
         let mut r = _mm_set1_epi8(0);
-        _mm256_mask_cvtepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
+        unsafe {
+            _mm256_mask_cvtepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
+        }
         let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 9, 9, 9, 9);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_cvtepi64_storeu_epi8() {
+    fn test_mm_mask_cvtepi64_storeu_epi8() {
         let a = _mm_set1_epi64x(9);
         let mut r = _mm_set1_epi8(0);
-        _mm_mask_cvtepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
+        unsafe {
+            _mm_mask_cvtepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
+        }
         let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 9, 9);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cvtsepi64_storeu_epi8() {
+    fn test_mm512_mask_cvtsepi64_storeu_epi8() {
         let a = _mm512_set1_epi64(i64::MAX);
         let mut r = _mm_set1_epi8(0);
-        _mm512_mask_cvtsepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
+        unsafe {
+            _mm512_mask_cvtsepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
+        }
         #[rustfmt::skip]
         let e = _mm_set_epi8(
             0, 0, 0, 0,
@@ -12327,10 +12460,12 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_cvtsepi64_storeu_epi8() {
+    fn test_mm256_mask_cvtsepi64_storeu_epi8() {
         let a = _mm256_set1_epi64x(i64::MAX);
         let mut r = _mm_set1_epi8(0);
-        _mm256_mask_cvtsepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
+        unsafe {
+            _mm256_mask_cvtsepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
+        }
         #[rustfmt::skip]
         let e = _mm_set_epi8(
             0, 0, 0, 0,
@@ -12342,19 +12477,23 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_cvtsepi64_storeu_epi8() {
+    fn test_mm_mask_cvtsepi64_storeu_epi8() {
         let a = _mm_set1_epi64x(i64::MAX);
         let mut r = _mm_set1_epi8(0);
-        _mm_mask_cvtsepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
+        unsafe {
+            _mm_mask_cvtsepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
+        }
         let e = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, i8::MAX, i8::MAX);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cvtusepi64_storeu_epi8() {
+    fn test_mm512_mask_cvtusepi64_storeu_epi8() {
         let a = _mm512_set1_epi64(i64::MAX);
         let mut r = _mm_set1_epi8(0);
-        _mm512_mask_cvtusepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
+        unsafe {
+            _mm512_mask_cvtusepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
+        }
         #[rustfmt::skip]
         let e = _mm_set_epi8(
             0, 0, 0, 0,
@@ -12366,10 +12505,12 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_cvtusepi64_storeu_epi8() {
+    fn test_mm256_mask_cvtusepi64_storeu_epi8() {
         let a = _mm256_set1_epi64x(i64::MAX);
         let mut r = _mm_set1_epi8(0);
-        _mm256_mask_cvtusepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
+        unsafe {
+            _mm256_mask_cvtusepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
+        }
         #[rustfmt::skip]
         let e = _mm_set_epi8(
             0, 0, 0, 0,
@@ -12381,10 +12522,12 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_cvtusepi64_storeu_epi8() {
+    fn test_mm_mask_cvtusepi64_storeu_epi8() {
         let a = _mm_set1_epi64x(i64::MAX);
         let mut r = _mm_set1_epi8(0);
-        _mm_mask_cvtusepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
+        unsafe {
+            _mm_mask_cvtusepi64_storeu_epi8(&mut r as *mut _ as *mut i8, 0b11111111, a);
+        }
         #[rustfmt::skip]
         let e = _mm_set_epi8(
             0, 0, 0, 0,
@@ -12396,112 +12539,136 @@ mod tests {
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cvtepi64_storeu_epi32() {
+    fn test_mm512_mask_cvtepi64_storeu_epi32() {
         let a = _mm512_set1_epi64(9);
         let mut r = _mm256_undefined_si256();
-        _mm512_mask_cvtepi64_storeu_epi32(&mut r as *mut _ as *mut i32, 0b11111111, a);
+        unsafe {
+            _mm512_mask_cvtepi64_storeu_epi32(&mut r as *mut _ as *mut i32, 0b11111111, a);
+        }
         let e = _mm256_set1_epi32(9);
         assert_eq_m256i(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_cvtepi64_storeu_epi32() {
+    fn test_mm256_mask_cvtepi64_storeu_epi32() {
         let a = _mm256_set1_epi64x(9);
         let mut r = _mm_set1_epi32(0);
-        _mm256_mask_cvtepi64_storeu_epi32(&mut r as *mut _ as *mut i32, 0b11111111, a);
+        unsafe {
+            _mm256_mask_cvtepi64_storeu_epi32(&mut r as *mut _ as *mut i32, 0b11111111, a);
+        }
         let e = _mm_set_epi32(9, 9, 9, 9);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_cvtepi64_storeu_epi32() {
+    fn test_mm_mask_cvtepi64_storeu_epi32() {
         let a = _mm_set1_epi64x(9);
         let mut r = _mm_set1_epi16(0);
-        _mm_mask_cvtepi64_storeu_epi32(&mut r as *mut _ as *mut i32, 0b11111111, a);
+        unsafe {
+            _mm_mask_cvtepi64_storeu_epi32(&mut r as *mut _ as *mut i32, 0b11111111, a);
+        }
         let e = _mm_set_epi32(0, 0, 9, 9);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cvtsepi64_storeu_epi32() {
+    fn test_mm512_mask_cvtsepi64_storeu_epi32() {
         let a = _mm512_set1_epi64(i64::MAX);
         let mut r = _mm256_undefined_si256();
-        _mm512_mask_cvtsepi64_storeu_epi32(&mut r as *mut _ as *mut i32, 0b11111111, a);
+        unsafe {
+            _mm512_mask_cvtsepi64_storeu_epi32(&mut r as *mut _ as *mut i32, 0b11111111, a);
+        }
         let e = _mm256_set1_epi32(i32::MAX);
         assert_eq_m256i(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_cvtsepi64_storeu_epi32() {
+    fn test_mm256_mask_cvtsepi64_storeu_epi32() {
         let a = _mm256_set1_epi64x(i64::MAX);
         let mut r = _mm_set1_epi32(0);
-        _mm256_mask_cvtsepi64_storeu_epi32(&mut r as *mut _ as *mut i32, 0b00001111, a);
+        unsafe {
+            _mm256_mask_cvtsepi64_storeu_epi32(&mut r as *mut _ as *mut i32, 0b00001111, a);
+        }
         let e = _mm_set1_epi32(i32::MAX);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_cvtsepi64_storeu_epi32() {
+    fn test_mm_mask_cvtsepi64_storeu_epi32() {
         let a = _mm_set1_epi64x(i64::MAX);
         let mut r = _mm_set1_epi16(0);
-        _mm_mask_cvtsepi64_storeu_epi32(&mut r as *mut _ as *mut i32, 0b00000011, a);
+        unsafe {
+            _mm_mask_cvtsepi64_storeu_epi32(&mut r as *mut _ as *mut i32, 0b00000011, a);
+        }
         let e = _mm_set_epi32(0, 0, i32::MAX, i32::MAX);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    unsafe fn test_mm512_mask_cvtusepi64_storeu_epi32() {
+    fn test_mm512_mask_cvtusepi64_storeu_epi32() {
         let a = _mm512_set1_epi64(i64::MAX);
         let mut r = _mm256_undefined_si256();
-        _mm512_mask_cvtusepi64_storeu_epi32(&mut r as *mut _ as *mut i32, 0b11111111, a);
+        unsafe {
+            _mm512_mask_cvtusepi64_storeu_epi32(&mut r as *mut _ as *mut i32, 0b11111111, a);
+        }
         let e = _mm256_set1_epi32(u32::MAX as i32);
         assert_eq_m256i(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm256_mask_cvtusepi64_storeu_epi32() {
+    fn test_mm256_mask_cvtusepi64_storeu_epi32() {
         let a = _mm256_set1_epi64x(i64::MAX);
         let mut r = _mm_set1_epi32(0);
-        _mm256_mask_cvtusepi64_storeu_epi32(&mut r as *mut _ as *mut i32, 0b00001111, a);
+        unsafe {
+            _mm256_mask_cvtusepi64_storeu_epi32(&mut r as *mut _ as *mut i32, 0b00001111, a);
+        }
         let e = _mm_set1_epi32(u32::MAX as i32);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    unsafe fn test_mm_mask_cvtusepi64_storeu_epi32() {
+    fn test_mm_mask_cvtusepi64_storeu_epi32() {
         let a = _mm_set1_epi64x(i64::MAX);
         let mut r = _mm_set1_epi16(0);
-        _mm_mask_cvtusepi64_storeu_epi32(&mut r as *mut _ as *mut i32, 0b00000011, a);
+        unsafe {
+            _mm_mask_cvtusepi64_storeu_epi32(&mut r as *mut _ as *mut i32, 0b00000011, a);
+        }
         let e = _mm_set_epi32(0, 0, u32::MAX as i32, u32::MAX as i32);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_storeu_epi64() {
+    const fn test_mm512_storeu_epi64() {
         let a = _mm512_set1_epi64(9);
         let mut r = _mm512_set1_epi64(0);
-        _mm512_storeu_epi64(&mut r as *mut _ as *mut i64, a);
+        unsafe {
+            _mm512_storeu_epi64(&mut r as *mut _ as *mut i64, a);
+        }
         assert_eq_m512i(r, a);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_storeu_epi64() {
+    const fn test_mm256_storeu_epi64() {
         let a = _mm256_set1_epi64x(9);
         let mut r = _mm256_set1_epi64x(0);
-        _mm256_storeu_epi64(&mut r as *mut _ as *mut i64, a);
+        unsafe {
+            _mm256_storeu_epi64(&mut r as *mut _ as *mut i64, a);
+        }
         assert_eq_m256i(r, a);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_storeu_epi64() {
+    const fn test_mm_storeu_epi64() {
         let a = _mm_set1_epi64x(9);
         let mut r = _mm_set1_epi64x(0);
-        _mm_storeu_epi64(&mut r as *mut _ as *mut i64, a);
+        unsafe {
+            _mm_storeu_epi64(&mut r as *mut _ as *mut i64, a);
+        }
         assert_eq_m128i(r, a);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_load_epi64() {
+    const fn test_mm512_load_epi64() {
         #[repr(align(64))]
         struct Align {
             data: [i64; 8], // 64 bytes
@@ -12510,63 +12677,69 @@ mod tests {
             data: [4, 3, 2, 5, -8, -9, -64, -50],
         };
         let p = (a.data).as_ptr();
-        let r = _mm512_load_epi64(black_box(p));
+        let r = unsafe { _mm512_load_epi64(black_box(p)) };
         let e = _mm512_setr_epi64(4, 3, 2, 5, -8, -9, -64, -50);
         assert_eq_m512i(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_load_epi64() {
+    const fn test_mm256_load_epi64() {
         #[repr(align(64))]
         struct Align {
             data: [i64; 4],
         }
         let a = Align { data: [4, 3, 2, 5] };
         let p = (a.data).as_ptr();
-        let r = _mm256_load_epi64(black_box(p));
+        let r = unsafe { _mm256_load_epi64(black_box(p)) };
         let e = _mm256_set_epi64x(5, 2, 3, 4);
         assert_eq_m256i(r, e);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_load_epi64() {
+    const fn test_mm_load_epi64() {
         #[repr(align(64))]
         struct Align {
             data: [i64; 2],
         }
         let a = Align { data: [4, 3] };
         let p = (a.data).as_ptr();
-        let r = _mm_load_epi64(black_box(p));
+        let r = unsafe { _mm_load_epi64(black_box(p)) };
         let e = _mm_set_epi64x(3, 4);
         assert_eq_m128i(r, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_store_epi64() {
+    const fn test_mm512_store_epi64() {
         let a = _mm512_set1_epi64(9);
         let mut r = _mm512_set1_epi64(0);
-        _mm512_store_epi64(&mut r as *mut _ as *mut i64, a);
+        unsafe {
+            _mm512_store_epi64(&mut r as *mut _ as *mut i64, a);
+        }
         assert_eq_m512i(r, a);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm256_store_epi64() {
+    const fn test_mm256_store_epi64() {
         let a = _mm256_set1_epi64x(9);
         let mut r = _mm256_set1_epi64x(0);
-        _mm256_store_epi64(&mut r as *mut _ as *mut i64, a);
+        unsafe {
+            _mm256_store_epi64(&mut r as *mut _ as *mut i64, a);
+        }
         assert_eq_m256i(r, a);
     }
 
     #[simd_test(enable = "avx512f,avx512vl")]
-    const unsafe fn test_mm_store_epi64() {
+    const fn test_mm_store_epi64() {
         let a = _mm_set1_epi64x(9);
         let mut r = _mm_set1_epi64x(0);
-        _mm_store_epi64(&mut r as *mut _ as *mut i64, a);
+        unsafe {
+            _mm_store_epi64(&mut r as *mut _ as *mut i64, a);
+        }
         assert_eq_m128i(r, a);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_load_pd() {
+    const fn test_mm512_load_pd() {
         #[repr(align(64))]
         struct Align {
             data: [f64; 8], // 64 bytes
@@ -12575,16 +12748,18 @@ mod tests {
             data: [4., 3., 2., 5., -8., -9., -64., -50.],
         };
         let p = (a.data).as_ptr();
-        let r = _mm512_load_pd(black_box(p));
+        let r = unsafe { _mm512_load_pd(black_box(p)) };
         let e = _mm512_setr_pd(4., 3., 2., 5., -8., -9., -64., -50.);
         assert_eq_m512d(r, e);
     }
 
     #[simd_test(enable = "avx512f")]
-    const unsafe fn test_mm512_store_pd() {
+    const fn test_mm512_store_pd() {
         let a = _mm512_set1_pd(9.);
         let mut r = _mm512_undefined_pd();
-        _mm512_store_pd(&mut r as *mut _ as *mut f64, a);
+        unsafe {
+            _mm512_store_pd(&mut r as *mut _ as *mut f64, a);
+        }
         assert_eq_m512d(r, a);
     }
 
diff --git a/library/stdarch/crates/core_arch/src/x86_64/fxsr.rs b/library/stdarch/crates/core_arch/src/x86_64/fxsr.rs
index a24b44fb1f7e..28bf1951167a 100644
--- a/library/stdarch/crates/core_arch/src/x86_64/fxsr.rs
+++ b/library/stdarch/crates/core_arch/src/x86_64/fxsr.rs
@@ -77,12 +77,14 @@ mod tests {
 
     #[simd_test(enable = "fxsr")]
     #[cfg_attr(miri, ignore)] // Register saving/restoring is not supported in Miri
-    unsafe fn test_fxsave64() {
+    fn test_fxsave64() {
         let mut a = FxsaveArea::new();
         let mut b = FxsaveArea::new();
 
-        fxsr::_fxsave64(a.ptr());
-        fxsr::_fxrstor64(a.ptr());
-        fxsr::_fxsave64(b.ptr());
+        unsafe {
+            fxsr::_fxsave64(a.ptr());
+            fxsr::_fxrstor64(a.ptr());
+            fxsr::_fxsave64(b.ptr());
+        }
     }
 }
diff --git a/library/stdarch/crates/core_arch/src/x86_64/sse2.rs b/library/stdarch/crates/core_arch/src/x86_64/sse2.rs
index b156af078a32..08dabf053d42 100644
--- a/library/stdarch/crates/core_arch/src/x86_64/sse2.rs
+++ b/library/stdarch/crates/core_arch/src/x86_64/sse2.rs
@@ -204,10 +204,12 @@ mod tests {
     // Miri cannot support this until it is clear how it fits in the Rust memory model
     // (non-temporal store)
     #[cfg_attr(miri, ignore)]
-    unsafe fn test_mm_stream_si64() {
+    fn test_mm_stream_si64() {
         let a: i64 = 7;
         let mut mem = boxed::Box::<i64>::new(-1);
-        _mm_stream_si64(ptr::addr_of_mut!(*mem), a);
+        unsafe {
+            _mm_stream_si64(ptr::addr_of_mut!(*mem), a);
+        }
         _mm_sfence();
         assert_eq!(a, *mem);
     }
diff --git a/library/stdarch/crates/core_arch/src/x86_64/xsave.rs b/library/stdarch/crates/core_arch/src/x86_64/xsave.rs
index fa1454a822e3..30a7123315e5 100644
--- a/library/stdarch/crates/core_arch/src/x86_64/xsave.rs
+++ b/library/stdarch/crates/core_arch/src/x86_64/xsave.rs
@@ -132,37 +132,43 @@ mod tests {
 
     #[simd_test(enable = "xsave")]
     #[cfg_attr(miri, ignore)] // Register saving/restoring is not supported in Miri
-    unsafe fn test_xsave64() {
+    fn test_xsave64() {
         let m = 0xFFFFFFFFFFFFFFFF_u64; //< all registers
         let mut a = XsaveArea::new();
         let mut b = XsaveArea::new();
 
-        _xsave64(a.ptr(), m);
-        _xrstor64(a.ptr(), m);
-        _xsave64(b.ptr(), m);
+        unsafe {
+            _xsave64(a.ptr(), m);
+            _xrstor64(a.ptr(), m);
+            _xsave64(b.ptr(), m);
+        }
     }
 
     #[simd_test(enable = "xsave,xsaveopt")]
     #[cfg_attr(miri, ignore)] // Register saving/restoring is not supported in Miri
-    unsafe fn test_xsaveopt64() {
+    fn test_xsaveopt64() {
         let m = 0xFFFFFFFFFFFFFFFF_u64; //< all registers
         let mut a = XsaveArea::new();
         let mut b = XsaveArea::new();
 
-        _xsaveopt64(a.ptr(), m);
-        _xrstor64(a.ptr(), m);
-        _xsaveopt64(b.ptr(), m);
+        unsafe {
+            _xsaveopt64(a.ptr(), m);
+            _xrstor64(a.ptr(), m);
+            _xsaveopt64(b.ptr(), m);
+        }
     }
 
     #[simd_test(enable = "xsave,xsavec")]
     #[cfg_attr(miri, ignore)] // Register saving/restoring is not supported in Miri
-    unsafe fn test_xsavec64() {
+    fn test_xsavec64() {
         let m = 0xFFFFFFFFFFFFFFFF_u64; //< all registers
         let mut a = XsaveArea::new();
         let mut b = XsaveArea::new();
 
-        _xsavec64(a.ptr(), m);
-        _xrstor64(a.ptr(), m);
-        _xsavec64(b.ptr(), m);
+        unsafe {
+            _xsavec64(a.ptr(), m);
+            _xrstor64(a.ptr(), m);
+            _xsavec64(b.ptr(), m);
+        }
     }
 }

From c7c5adbe6452c1c904fbe6b6bb3fdd0ed7671a55 Mon Sep 17 00:00:00 2001
From: Trevor Gross <tg@trevorgross.com>
Date: Sun, 11 Jan 2026 07:00:54 -0600
Subject: [PATCH 11/97] compiler-builtins: Remove the no-f16-f128 feature

This option was used to gate `f16` and `f128` when support across
backends and targets was inconsistent. We now have the rustc builtin cfg
`target_has_reliable{f16,f128}` which has taken over this usecase.
Remove no-f16-f128 since it is now unused and redundant.
---
 library/alloc/Cargo.toml                                 | 1 -
 library/compiler-builtins/builtins-shim/Cargo.toml       | 4 ----
 library/compiler-builtins/builtins-test/Cargo.toml       | 1 -
 library/compiler-builtins/ci/run.sh                      | 4 ----
 library/compiler-builtins/compiler-builtins/Cargo.toml   | 4 ----
 library/compiler-builtins/compiler-builtins/configure.rs | 7 ++-----
 library/compiler-builtins/libm/configure.rs              | 7 ++-----
 library/std/Cargo.toml                                   | 1 -
 library/sysroot/Cargo.toml                               | 1 -
 9 files changed, 4 insertions(+), 26 deletions(-)

diff --git a/library/alloc/Cargo.toml b/library/alloc/Cargo.toml
index fb1f8c86dbfd..541257b6cda6 100644
--- a/library/alloc/Cargo.toml
+++ b/library/alloc/Cargo.toml
@@ -21,7 +21,6 @@ compiler_builtins = { path = "../compiler-builtins/compiler-builtins", features
 [features]
 compiler-builtins-mem = ['compiler_builtins/mem']
 compiler-builtins-c = ["compiler_builtins/c"]
-compiler-builtins-no-f16-f128 = ["compiler_builtins/no-f16-f128"]
 # Choose algorithms that are optimized for binary size instead of runtime performance
 optimize_for_size = ["core/optimize_for_size"]
 
diff --git a/library/compiler-builtins/builtins-shim/Cargo.toml b/library/compiler-builtins/builtins-shim/Cargo.toml
index ac77224f5ce1..746d5b21dc3f 100644
--- a/library/compiler-builtins/builtins-shim/Cargo.toml
+++ b/library/compiler-builtins/builtins-shim/Cargo.toml
@@ -47,10 +47,6 @@ c = ["dep:cc"]
 # the generic versions on all platforms.
 no-asm = []
 
-# Workaround for codegen backends which haven't yet implemented `f16` and
-# `f128` support. Disabled any intrinsics which use those types.
-no-f16-f128 = []
-
 # Flag this library as the unstable compiler-builtins lib
 compiler-builtins = []
 
diff --git a/library/compiler-builtins/builtins-test/Cargo.toml b/library/compiler-builtins/builtins-test/Cargo.toml
index 9346ea65420b..550f736a76db 100644
--- a/library/compiler-builtins/builtins-test/Cargo.toml
+++ b/library/compiler-builtins/builtins-test/Cargo.toml
@@ -33,7 +33,6 @@ utest-macros = { git = "https://github.com/japaric/utest" }
 default = ["mangled-names"]
 c = ["compiler_builtins/c"]
 no-asm = ["compiler_builtins/no-asm"]
-no-f16-f128 = ["compiler_builtins/no-f16-f128"]
 mem = ["compiler_builtins/mem"]
 mangled-names = ["compiler_builtins/mangled-names"]
 # Skip tests that rely on f128 symbols being available on the system
diff --git a/library/compiler-builtins/ci/run.sh b/library/compiler-builtins/ci/run.sh
index bc94d42fe837..0c07b32c74b9 100755
--- a/library/compiler-builtins/ci/run.sh
+++ b/library/compiler-builtins/ci/run.sh
@@ -36,8 +36,6 @@ else
     "${test_builtins[@]}" --features c --release
     "${test_builtins[@]}" --features no-asm
     "${test_builtins[@]}" --features no-asm --release
-    "${test_builtins[@]}" --features no-f16-f128
-    "${test_builtins[@]}" --features no-f16-f128 --release
     "${test_builtins[@]}" --benches
     "${test_builtins[@]}" --benches --release
 
@@ -63,8 +61,6 @@ symcheck+=(-- build-and-check)
 "${symcheck[@]}" "$target" -- -p compiler_builtins --features c --release
 "${symcheck[@]}" "$target" -- -p compiler_builtins --features no-asm
 "${symcheck[@]}" "$target" -- -p compiler_builtins --features no-asm --release
-"${symcheck[@]}" "$target" -- -p compiler_builtins --features no-f16-f128
-"${symcheck[@]}" "$target" -- -p compiler_builtins --features no-f16-f128 --release
 
 run_intrinsics_test() {
     build_args=(--verbose --manifest-path builtins-test-intrinsics/Cargo.toml)
diff --git a/library/compiler-builtins/compiler-builtins/Cargo.toml b/library/compiler-builtins/compiler-builtins/Cargo.toml
index 0845861dcfe3..496dde2d4cf2 100644
--- a/library/compiler-builtins/compiler-builtins/Cargo.toml
+++ b/library/compiler-builtins/compiler-builtins/Cargo.toml
@@ -45,10 +45,6 @@ c = ["dep:cc"]
 # the generic versions on all platforms.
 no-asm = []
 
-# Workaround for codegen backends which haven't yet implemented `f16` and
-# `f128` support. Disabled any intrinsics which use those types.
-no-f16-f128 = []
-
 # Flag this library as the unstable compiler-builtins lib
 compiler-builtins = []
 
diff --git a/library/compiler-builtins/compiler-builtins/configure.rs b/library/compiler-builtins/compiler-builtins/configure.rs
index 79e238abc0f6..f16da6b58f81 100644
--- a/library/compiler-builtins/compiler-builtins/configure.rs
+++ b/library/compiler-builtins/compiler-builtins/configure.rs
@@ -95,16 +95,13 @@ pub fn configure_aliases(target: &Target) {
      * * https://github.com/rust-lang/rustc_codegen_cranelift/blob/c713ffab3c6e28ab4b4dd4e392330f786ea657ad/src/lib.rs#L196-L226
      */
 
-    // If the feature is set, disable both of these types.
-    let no_f16_f128 = target.cargo_features.iter().any(|s| s == "no-f16-f128");
-
     println!("cargo::rustc-check-cfg=cfg(f16_enabled)");
-    if target.reliable_f16 && !no_f16_f128 {
+    if target.reliable_f16 {
         println!("cargo::rustc-cfg=f16_enabled");
     }
 
     println!("cargo::rustc-check-cfg=cfg(f128_enabled)");
-    if target.reliable_f128 && !no_f16_f128 {
+    if target.reliable_f128 {
         println!("cargo::rustc-cfg=f128_enabled");
     }
 }
diff --git a/library/compiler-builtins/libm/configure.rs b/library/compiler-builtins/libm/configure.rs
index 857a30229716..ee65a3a8d624 100644
--- a/library/compiler-builtins/libm/configure.rs
+++ b/library/compiler-builtins/libm/configure.rs
@@ -143,16 +143,13 @@ fn emit_f16_f128_cfg(cfg: &Config) {
 
     /* See the compiler-builtins configure file for info about the meaning of these options */
 
-    // If the feature is set, disable both of these types.
-    let no_f16_f128 = cfg.cargo_features.iter().any(|s| s == "no-f16-f128");
-
     println!("cargo:rustc-check-cfg=cfg(f16_enabled)");
-    if cfg.reliable_f16 && !no_f16_f128 {
+    if cfg.reliable_f16 {
         println!("cargo:rustc-cfg=f16_enabled");
     }
 
     println!("cargo:rustc-check-cfg=cfg(f128_enabled)");
-    if cfg.reliable_f128 && !no_f16_f128 {
+    if cfg.reliable_f128 {
         println!("cargo:rustc-cfg=f128_enabled");
     }
 }
diff --git a/library/std/Cargo.toml b/library/std/Cargo.toml
index 5c9ae52d9e6c..b6683a2ae9ec 100644
--- a/library/std/Cargo.toml
+++ b/library/std/Cargo.toml
@@ -115,7 +115,6 @@ backtrace-trace-only = []
 panic-unwind = ["dep:panic_unwind"]
 compiler-builtins-c = ["alloc/compiler-builtins-c"]
 compiler-builtins-mem = ["alloc/compiler-builtins-mem"]
-compiler-builtins-no-f16-f128 = ["alloc/compiler-builtins-no-f16-f128"]
 llvm-libunwind = ["unwind/llvm-libunwind"]
 system-llvm-libunwind = ["unwind/system-llvm-libunwind"]
 
diff --git a/library/sysroot/Cargo.toml b/library/sysroot/Cargo.toml
index a18868082916..b2069ef6a613 100644
--- a/library/sysroot/Cargo.toml
+++ b/library/sysroot/Cargo.toml
@@ -25,7 +25,6 @@ backtrace = ["std/backtrace"]
 backtrace-trace-only = ["std/backtrace-trace-only"]
 compiler-builtins-c = ["std/compiler-builtins-c"]
 compiler-builtins-mem = ["std/compiler-builtins-mem"]
-compiler-builtins-no-f16-f128 = ["std/compiler-builtins-no-f16-f128"]
 debug_refcell = ["std/debug_refcell"]
 llvm-libunwind = ["std/llvm-libunwind"]
 system-llvm-libunwind = ["std/system-llvm-libunwind"]

From d0204a399a7f3a2d9c5ea4d2d2c897ce0536b5eb Mon Sep 17 00:00:00 2001
From: Folkert de Vries <folkert@folkertdev.nl>
Date: Sun, 11 Jan 2026 21:10:17 +0100
Subject: [PATCH 12/97] remove `impl Neg` on s390x/powerpc vector types

For other targets we don't have such instances. We specifically decided agains implementing arithmetic operators on these low-level vector types
---
 .../crates/core_arch/src/powerpc/altivec.rs   | 51 +++++++++++++++---
 .../crates/core_arch/src/powerpc/macros.rs    | 14 -----
 .../crates/core_arch/src/s390x/macros.rs      | 14 -----
 .../crates/core_arch/src/s390x/vector.rs      | 54 ++++++++++++++++---
 4 files changed, 91 insertions(+), 42 deletions(-)

diff --git a/library/stdarch/crates/core_arch/src/powerpc/altivec.rs b/library/stdarch/crates/core_arch/src/powerpc/altivec.rs
index 37b557c3b2af..c1881da08f86 100644
--- a/library/stdarch/crates/core_arch/src/powerpc/altivec.rs
+++ b/library/stdarch/crates/core_arch/src/powerpc/altivec.rs
@@ -364,15 +364,46 @@ unsafe extern "C" {
     fn vrfin(a: vector_float) -> vector_float;
 }
 
-impl_neg! { i8x16 : 0 }
-impl_neg! { i16x8 : 0 }
-impl_neg! { i32x4 : 0 }
-impl_neg! { f32x4 : 0f32 }
-
 #[macro_use]
 mod sealed {
     use super::*;
 
+    #[unstable(feature = "stdarch_powerpc", issue = "111145")]
+    pub trait VectorNeg {
+        unsafe fn vec_neg(self) -> Self;
+    }
+
+    macro_rules! impl_neg {
+        ($($v:ty)*) => {
+            $(
+                #[unstable(feature = "stdarch_powerpc", issue = "111145")]
+                impl VectorNeg for $v {
+                    #[inline]
+                    #[target_feature(enable = "altivec")]
+                    unsafe fn vec_neg(self) -> Self {
+                        simd_neg(self)
+                    }
+                }
+            )*
+        }
+    }
+
+    impl_neg! {
+        vector_signed_char
+        vector_unsigned_char
+        vector_bool_char
+
+        vector_signed_short
+        vector_unsigned_short
+        vector_bool_short
+
+        vector_signed_int
+        vector_unsigned_int
+        vector_bool_int
+
+        vector_float
+    }
+
     #[unstable(feature = "stdarch_powerpc", issue = "111145")]
     pub trait VectorInsert {
         type Scalar;
@@ -1378,7 +1409,7 @@ mod sealed {
             #[inline]
             #[target_feature(enable = "altivec")]
             unsafe fn $name(v: s_t_l!($ty)) -> s_t_l!($ty) {
-                v.vec_max(-v)
+                v.vec_max(simd_neg(v))
             }
 
             impl_vec_trait! { [VectorAbs vec_abs] $name (s_t_l!($ty)) }
@@ -4030,6 +4061,14 @@ pub unsafe fn vec_mfvscr() -> vector_unsigned_short {
     mfvscr()
 }
 
+/// Vector Negate
+#[inline]
+#[target_feature(enable = "altivec")]
+#[unstable(feature = "stdarch_powerpc", issue = "111145")]
+pub unsafe fn vec_neg<T: sealed::VectorNeg>(a: T) -> T {
+    a.vec_neg()
+}
+
 /// Vector add.
 #[inline]
 #[target_feature(enable = "altivec")]
diff --git a/library/stdarch/crates/core_arch/src/powerpc/macros.rs b/library/stdarch/crates/core_arch/src/powerpc/macros.rs
index 6097ca31adc9..f697d4d25748 100644
--- a/library/stdarch/crates/core_arch/src/powerpc/macros.rs
+++ b/library/stdarch/crates/core_arch/src/powerpc/macros.rs
@@ -274,20 +274,6 @@ macro_rules! t_b {
     };
 }
 
-macro_rules! impl_neg {
-    ($s: ident : $zero: expr) => {
-        #[unstable(feature = "stdarch_powerpc", issue = "111145")]
-        impl crate::ops::Neg for s_t_l!($s) {
-            type Output = s_t_l!($s);
-            #[inline]
-            fn neg(self) -> Self::Output {
-                unsafe { simd_neg(self) }
-            }
-        }
-    };
-}
-
-pub(crate) use impl_neg;
 pub(crate) use impl_vec_trait;
 pub(crate) use s_t_l;
 pub(crate) use t_b;
diff --git a/library/stdarch/crates/core_arch/src/s390x/macros.rs b/library/stdarch/crates/core_arch/src/s390x/macros.rs
index b72560396c43..c47f242948df 100644
--- a/library/stdarch/crates/core_arch/src/s390x/macros.rs
+++ b/library/stdarch/crates/core_arch/src/s390x/macros.rs
@@ -431,20 +431,6 @@ macro_rules! t_b {
     };
 }
 
-macro_rules! impl_neg {
-    ($s: ident : $zero: expr) => {
-        #[unstable(feature = "stdarch_s390x", issue = "135681")]
-        impl crate::ops::Neg for s_t_l!($s) {
-            type Output = s_t_l!($s);
-            #[inline]
-            fn neg(self) -> Self::Output {
-                unsafe { simd_neg(self) }
-            }
-        }
-    };
-}
-
-pub(crate) use impl_neg;
 pub(crate) use impl_vec_trait;
 pub(crate) use l_t_t;
 pub(crate) use s_t_l;
diff --git a/library/stdarch/crates/core_arch/src/s390x/vector.rs b/library/stdarch/crates/core_arch/src/s390x/vector.rs
index d63f37eeb9a8..97bfa32f17ad 100644
--- a/library/stdarch/crates/core_arch/src/s390x/vector.rs
+++ b/library/stdarch/crates/core_arch/src/s390x/vector.rs
@@ -283,13 +283,6 @@ unsafe extern "unadjusted" {
     #[link_name = "llvm.s390.vfenezfs"] fn vfenezfs(a: i32x4, b: i32x4) -> PackedTuple<i32x4, i32>;
 }
 
-impl_neg! { i8x16 : 0 }
-impl_neg! { i16x8 : 0 }
-impl_neg! { i32x4 : 0 }
-impl_neg! { i64x2 : 0 }
-impl_neg! { f32x4 : 0f32 }
-impl_neg! { f64x2 : 0f64 }
-
 #[repr(simd)]
 struct ShuffleMask<const N: usize>([u32; N]);
 
@@ -437,6 +430,43 @@ enum FindImm {
 mod sealed {
     use super::*;
 
+    #[unstable(feature = "stdarch_s390x", issue = "135681")]
+    pub trait VectorNeg {
+        unsafe fn vec_neg(self) -> Self;
+    }
+
+    macro_rules! impl_neg {
+        ($($v:ty)*) => {
+            $(
+                #[unstable(feature = "stdarch_s390x", issue = "135681")]
+                impl VectorNeg for $v {
+                    #[inline]
+                    #[target_feature(enable = "vector")]
+                    unsafe fn vec_neg(self) -> Self {
+                        simd_neg(self)
+                    }
+                }
+            )*
+        }
+    }
+
+    impl_neg! {
+        vector_signed_char
+        vector_unsigned_char
+
+        vector_signed_short
+        vector_unsigned_short
+
+        vector_signed_int
+        vector_unsigned_int
+
+        vector_signed_long_long
+        vector_unsigned_long_long
+
+        vector_float
+        vector_double
+    }
+
     #[unstable(feature = "stdarch_s390x", issue = "135681")]
     pub trait VectorAdd<Other> {
         type Result;
@@ -759,7 +789,7 @@ mod sealed {
             #[inline]
             #[target_feature(enable = "vector")]
             unsafe fn $name(v: s_t_l!($ty)) -> s_t_l!($ty) {
-                v.vec_max(-v)
+                v.vec_max(simd_neg(v))
             }
 
             impl_vec_trait! { [VectorAbs vec_abs] $name (s_t_l!($ty)) }
@@ -4053,6 +4083,14 @@ unsafe fn __lcbb<const BLOCK_BOUNDARY: u16>(ptr: *const u8) -> u32 {
     lcbb(ptr, const { validate_block_boundary(BLOCK_BOUNDARY) })
 }
 
+/// Vector Negate
+#[inline]
+#[target_feature(enable = "vector")]
+#[unstable(feature = "stdarch_s390x", issue = "135681")]
+pub unsafe fn vec_neg<T: sealed::VectorNeg>(a: T) -> T {
+    a.vec_neg()
+}
+
 /// Vector Add
 #[inline]
 #[target_feature(enable = "vector")]

From 78952f6aaa56544d1ab9ce3c18a97e34ea1f390b Mon Sep 17 00:00:00 2001
From: Jamie Cunliffe <Jamie.Cunliffe@arm.com>
Date: Tue, 9 Dec 2025 16:33:40 +0000
Subject: [PATCH 13/97] Mark the neon intrinsics as inline(always).

The inline(always) attribute is now applied to the call site when a
function has target features enabled so that it can determine that the
call is safe to inline.
---
 .../core_arch/src/aarch64/neon/generated.rs   | 3892 +++++-----
 .../src/arm_shared/neon/generated.rs          | 6530 ++++++++---------
 library/stdarch/crates/core_arch/src/lib.rs   |    1 +
 .../crates/stdarch-gen-arm/src/intrinsic.rs   |    2 +-
 4 files changed, 5213 insertions(+), 5212 deletions(-)

diff --git a/library/stdarch/crates/core_arch/src/aarch64/neon/generated.rs b/library/stdarch/crates/core_arch/src/aarch64/neon/generated.rs
index 7743e52f4fe1..23b44294aa8f 100644
--- a/library/stdarch/crates/core_arch/src/aarch64/neon/generated.rs
+++ b/library/stdarch/crates/core_arch/src/aarch64/neon/generated.rs
@@ -14,7 +14,7 @@ use super::*;
 
 #[doc = "CRC32-C single round checksum for quad words (64 bits)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32cd)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "crc")]
 #[cfg_attr(test, assert_instr(crc32cx))]
 #[stable(feature = "stdarch_aarch64_crc32", since = "1.80.0")]
@@ -30,7 +30,7 @@ pub fn __crc32cd(crc: u32, data: u64) -> u32 {
 }
 #[doc = "CRC32 single round checksum for quad words (64 bits)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32d)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "crc")]
 #[cfg_attr(test, assert_instr(crc32x))]
 #[stable(feature = "stdarch_aarch64_crc32", since = "1.80.0")]
@@ -46,7 +46,7 @@ pub fn __crc32d(crc: u32, data: u64) -> u32 {
 }
 #[doc = "Floating-point JavaScript convert to signed fixed-point, rounding toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__jcvt)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "jsconv")]
 #[cfg_attr(test, assert_instr(fjcvtzs))]
 #[unstable(feature = "stdarch_aarch64_jscvt", issue = "147555")]
@@ -62,7 +62,7 @@ pub fn __jcvt(a: f64) -> i32 {
 }
 #[doc = "Signed Absolute difference and Accumulate Long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_high_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sabal2))]
@@ -77,7 +77,7 @@ pub fn vabal_high_s8(a: int16x8_t, b: int8x16_t, c: int8x16_t) -> int16x8_t {
 }
 #[doc = "Signed Absolute difference and Accumulate Long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_high_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sabal2))]
@@ -92,7 +92,7 @@ pub fn vabal_high_s16(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t {
 }
 #[doc = "Signed Absolute difference and Accumulate Long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_high_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sabal2))]
@@ -107,7 +107,7 @@ pub fn vabal_high_s32(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t {
 }
 #[doc = "Unsigned Absolute difference and Accumulate Long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_high_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uabal2))]
@@ -121,7 +121,7 @@ pub fn vabal_high_u8(a: uint16x8_t, b: uint8x16_t, c: uint8x16_t) -> uint16x8_t
 }
 #[doc = "Unsigned Absolute difference and Accumulate Long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_high_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uabal2))]
@@ -135,7 +135,7 @@ pub fn vabal_high_u16(a: uint32x4_t, b: uint16x8_t, c: uint16x8_t) -> uint32x4_t
 }
 #[doc = "Unsigned Absolute difference and Accumulate Long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_high_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uabal2))]
@@ -149,7 +149,7 @@ pub fn vabal_high_u32(a: uint64x2_t, b: uint32x4_t, c: uint32x4_t) -> uint64x2_t
 }
 #[doc = "Absolute difference between the arguments of Floating"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fabd))]
@@ -165,7 +165,7 @@ pub fn vabd_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t {
 }
 #[doc = "Absolute difference between the arguments of Floating"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fabd))]
@@ -181,7 +181,7 @@ pub fn vabdq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
 }
 #[doc = "Floating-point absolute difference"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdd_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fabd))]
@@ -190,7 +190,7 @@ pub fn vabdd_f64(a: f64, b: f64) -> f64 {
 }
 #[doc = "Floating-point absolute difference"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabds_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fabd))]
@@ -199,7 +199,7 @@ pub fn vabds_f32(a: f32, b: f32) -> f32 {
 }
 #[doc = "Floating-point absolute difference"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdh_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -209,7 +209,7 @@ pub fn vabdh_f16(a: f16, b: f16) -> f16 {
 }
 #[doc = "Signed Absolute difference Long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_high_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sabdl2))]
@@ -223,7 +223,7 @@ pub fn vabdl_high_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t {
 }
 #[doc = "Signed Absolute difference Long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_high_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sabdl2))]
@@ -237,7 +237,7 @@ pub fn vabdl_high_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t {
 }
 #[doc = "Signed Absolute difference Long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_high_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sabdl2))]
@@ -251,7 +251,7 @@ pub fn vabdl_high_s8(a: int8x16_t, b: int8x16_t) -> int16x8_t {
 }
 #[doc = "Unsigned Absolute difference Long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_high_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(uabdl2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -264,7 +264,7 @@ pub fn vabdl_high_u8(a: uint8x16_t, b: uint8x16_t) -> uint16x8_t {
 }
 #[doc = "Unsigned Absolute difference Long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_high_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(uabdl2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -277,7 +277,7 @@ pub fn vabdl_high_u16(a: uint16x8_t, b: uint16x8_t) -> uint32x4_t {
 }
 #[doc = "Unsigned Absolute difference Long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_high_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(uabdl2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -290,7 +290,7 @@ pub fn vabdl_high_u32(a: uint32x4_t, b: uint32x4_t) -> uint64x2_t {
 }
 #[doc = "Floating-point absolute value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabs_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fabs))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -299,7 +299,7 @@ pub fn vabs_f64(a: float64x1_t) -> float64x1_t {
 }
 #[doc = "Floating-point absolute value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabsq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fabs))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -308,7 +308,7 @@ pub fn vabsq_f64(a: float64x2_t) -> float64x2_t {
 }
 #[doc = "Absolute Value (wrapping)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabs_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(abs))]
@@ -321,7 +321,7 @@ pub fn vabs_s64(a: int64x1_t) -> int64x1_t {
 }
 #[doc = "Absolute Value (wrapping)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabsq_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(abs))]
@@ -334,7 +334,7 @@ pub fn vabsq_s64(a: int64x2_t) -> int64x2_t {
 }
 #[doc = "Absolute Value (wrapping)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabsd_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(abs))]
@@ -350,7 +350,7 @@ pub fn vabsd_s64(a: i64) -> i64 {
 }
 #[doc = "Add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddd_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(nop))]
@@ -359,7 +359,7 @@ pub fn vaddd_s64(a: i64, b: i64) -> i64 {
 }
 #[doc = "Add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddd_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(nop))]
@@ -368,7 +368,7 @@ pub fn vaddd_u64(a: u64, b: u64) -> u64 {
 }
 #[doc = "Signed Add Long across Vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlv_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(saddlv))]
@@ -384,7 +384,7 @@ pub fn vaddlv_s16(a: int16x4_t) -> i32 {
 }
 #[doc = "Signed Add Long across Vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlvq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(saddlv))]
@@ -400,7 +400,7 @@ pub fn vaddlvq_s16(a: int16x8_t) -> i32 {
 }
 #[doc = "Signed Add Long across Vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlvq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(saddlv))]
@@ -416,7 +416,7 @@ pub fn vaddlvq_s32(a: int32x4_t) -> i64 {
 }
 #[doc = "Signed Add Long across Vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlv_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(saddlp))]
@@ -432,7 +432,7 @@ pub fn vaddlv_s32(a: int32x2_t) -> i64 {
 }
 #[doc = "Signed Add Long across Vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlv_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(saddlv))]
@@ -448,7 +448,7 @@ pub fn vaddlv_s8(a: int8x8_t) -> i16 {
 }
 #[doc = "Signed Add Long across Vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlvq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(saddlv))]
@@ -464,7 +464,7 @@ pub fn vaddlvq_s8(a: int8x16_t) -> i16 {
 }
 #[doc = "Unsigned Add Long across Vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlv_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(uaddlv))]
@@ -480,7 +480,7 @@ pub fn vaddlv_u16(a: uint16x4_t) -> u32 {
 }
 #[doc = "Unsigned Add Long across Vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlvq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(uaddlv))]
@@ -496,7 +496,7 @@ pub fn vaddlvq_u16(a: uint16x8_t) -> u32 {
 }
 #[doc = "Unsigned Add Long across Vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlvq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(uaddlv))]
@@ -512,7 +512,7 @@ pub fn vaddlvq_u32(a: uint32x4_t) -> u64 {
 }
 #[doc = "Unsigned Add Long across Vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlv_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(uaddlp))]
@@ -528,7 +528,7 @@ pub fn vaddlv_u32(a: uint32x2_t) -> u64 {
 }
 #[doc = "Unsigned Add Long across Vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlv_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(uaddlv))]
@@ -544,7 +544,7 @@ pub fn vaddlv_u8(a: uint8x8_t) -> u16 {
 }
 #[doc = "Unsigned Add Long across Vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlvq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(uaddlv))]
@@ -560,7 +560,7 @@ pub fn vaddlvq_u8(a: uint8x16_t) -> u16 {
 }
 #[doc = "Floating-point add across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddv_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(faddp))]
@@ -576,7 +576,7 @@ pub fn vaddv_f32(a: float32x2_t) -> f32 {
 }
 #[doc = "Floating-point add across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddvq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(faddp))]
@@ -592,7 +592,7 @@ pub fn vaddvq_f32(a: float32x4_t) -> f32 {
 }
 #[doc = "Floating-point add across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddvq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(faddp))]
@@ -608,7 +608,7 @@ pub fn vaddvq_f64(a: float64x2_t) -> f64 {
 }
 #[doc = "Add across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddv_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(addp))]
@@ -617,7 +617,7 @@ pub fn vaddv_s32(a: int32x2_t) -> i32 {
 }
 #[doc = "Add across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddv_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(addv))]
@@ -626,7 +626,7 @@ pub fn vaddv_s8(a: int8x8_t) -> i8 {
 }
 #[doc = "Add across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddvq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(addv))]
@@ -635,7 +635,7 @@ pub fn vaddvq_s8(a: int8x16_t) -> i8 {
 }
 #[doc = "Add across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddv_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(addv))]
@@ -644,7 +644,7 @@ pub fn vaddv_s16(a: int16x4_t) -> i16 {
 }
 #[doc = "Add across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddvq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(addv))]
@@ -653,7 +653,7 @@ pub fn vaddvq_s16(a: int16x8_t) -> i16 {
 }
 #[doc = "Add across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddvq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(addv))]
@@ -662,7 +662,7 @@ pub fn vaddvq_s32(a: int32x4_t) -> i32 {
 }
 #[doc = "Add across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddv_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(addp))]
@@ -671,7 +671,7 @@ pub fn vaddv_u32(a: uint32x2_t) -> u32 {
 }
 #[doc = "Add across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddv_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(addv))]
@@ -680,7 +680,7 @@ pub fn vaddv_u8(a: uint8x8_t) -> u8 {
 }
 #[doc = "Add across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddvq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(addv))]
@@ -689,7 +689,7 @@ pub fn vaddvq_u8(a: uint8x16_t) -> u8 {
 }
 #[doc = "Add across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddv_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(addv))]
@@ -698,7 +698,7 @@ pub fn vaddv_u16(a: uint16x4_t) -> u16 {
 }
 #[doc = "Add across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddvq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(addv))]
@@ -707,7 +707,7 @@ pub fn vaddvq_u16(a: uint16x8_t) -> u16 {
 }
 #[doc = "Add across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddvq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(addv))]
@@ -716,7 +716,7 @@ pub fn vaddvq_u32(a: uint32x4_t) -> u32 {
 }
 #[doc = "Add across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddvq_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(addp))]
@@ -725,7 +725,7 @@ pub fn vaddvq_s64(a: int64x2_t) -> i64 {
 }
 #[doc = "Add across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddvq_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(addp))]
@@ -734,7 +734,7 @@ pub fn vaddvq_u64(a: uint64x2_t) -> u64 {
 }
 #[doc = "Multi-vector floating-point absolute maximum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vamax_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,faminmax")]
 #[cfg_attr(test, assert_instr(nop))]
 #[unstable(feature = "faminmax", issue = "137933")]
@@ -750,7 +750,7 @@ pub fn vamax_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
 }
 #[doc = "Multi-vector floating-point absolute maximum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vamaxq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,faminmax")]
 #[cfg_attr(test, assert_instr(nop))]
 #[unstable(feature = "faminmax", issue = "137933")]
@@ -766,7 +766,7 @@ pub fn vamaxq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
 }
 #[doc = "Multi-vector floating-point absolute maximum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vamaxq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,faminmax")]
 #[cfg_attr(test, assert_instr(nop))]
 #[unstable(feature = "faminmax", issue = "137933")]
@@ -782,7 +782,7 @@ pub fn vamaxq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
 }
 #[doc = "Multi-vector floating-point absolute minimum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vamin_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,faminmax")]
 #[cfg_attr(test, assert_instr(nop))]
 #[unstable(feature = "faminmax", issue = "137933")]
@@ -798,7 +798,7 @@ pub fn vamin_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
 }
 #[doc = "Multi-vector floating-point absolute minimum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaminq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,faminmax")]
 #[cfg_attr(test, assert_instr(nop))]
 #[unstable(feature = "faminmax", issue = "137933")]
@@ -814,7 +814,7 @@ pub fn vaminq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
 }
 #[doc = "Multi-vector floating-point absolute minimum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaminq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,faminmax")]
 #[cfg_attr(test, assert_instr(nop))]
 #[unstable(feature = "faminmax", issue = "137933")]
@@ -830,7 +830,7 @@ pub fn vaminq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
 }
 #[doc = "Bit clear and exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbcaxq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,sha3")]
 #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")]
 #[cfg_attr(test, assert_instr(bcax))]
@@ -846,7 +846,7 @@ pub fn vbcaxq_s8(a: int8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t {
 }
 #[doc = "Bit clear and exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbcaxq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,sha3")]
 #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")]
 #[cfg_attr(test, assert_instr(bcax))]
@@ -862,7 +862,7 @@ pub fn vbcaxq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t {
 }
 #[doc = "Bit clear and exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbcaxq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,sha3")]
 #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")]
 #[cfg_attr(test, assert_instr(bcax))]
@@ -878,7 +878,7 @@ pub fn vbcaxq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t {
 }
 #[doc = "Bit clear and exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbcaxq_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,sha3")]
 #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")]
 #[cfg_attr(test, assert_instr(bcax))]
@@ -894,7 +894,7 @@ pub fn vbcaxq_s64(a: int64x2_t, b: int64x2_t, c: int64x2_t) -> int64x2_t {
 }
 #[doc = "Bit clear and exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbcaxq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,sha3")]
 #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")]
 #[cfg_attr(test, assert_instr(bcax))]
@@ -910,7 +910,7 @@ pub fn vbcaxq_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Bit clear and exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbcaxq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,sha3")]
 #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")]
 #[cfg_attr(test, assert_instr(bcax))]
@@ -926,7 +926,7 @@ pub fn vbcaxq_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Bit clear and exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbcaxq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,sha3")]
 #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")]
 #[cfg_attr(test, assert_instr(bcax))]
@@ -942,7 +942,7 @@ pub fn vbcaxq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Bit clear and exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbcaxq_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,sha3")]
 #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")]
 #[cfg_attr(test, assert_instr(bcax))]
@@ -958,7 +958,7 @@ pub fn vbcaxq_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Floating-point complex add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcadd_rot270_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fcma"))]
 #[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
@@ -976,7 +976,7 @@ pub fn vcadd_rot270_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 }
 #[doc = "Floating-point complex add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaddq_rot270_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fcma"))]
 #[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
@@ -994,7 +994,7 @@ pub fn vcaddq_rot270_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
 }
 #[doc = "Floating-point complex add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcadd_rot270_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
 #[cfg_attr(test, assert_instr(fcadd))]
@@ -1010,7 +1010,7 @@ pub fn vcadd_rot270_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
 }
 #[doc = "Floating-point complex add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaddq_rot270_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
 #[cfg_attr(test, assert_instr(fcadd))]
@@ -1026,7 +1026,7 @@ pub fn vcaddq_rot270_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
 }
 #[doc = "Floating-point complex add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaddq_rot270_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
 #[cfg_attr(test, assert_instr(fcadd))]
@@ -1042,7 +1042,7 @@ pub fn vcaddq_rot270_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
 }
 #[doc = "Floating-point complex add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcadd_rot90_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fcma"))]
 #[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
@@ -1060,7 +1060,7 @@ pub fn vcadd_rot90_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 }
 #[doc = "Floating-point complex add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaddq_rot90_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fcma"))]
 #[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
@@ -1078,7 +1078,7 @@ pub fn vcaddq_rot90_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
 }
 #[doc = "Floating-point complex add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcadd_rot90_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
 #[cfg_attr(test, assert_instr(fcadd))]
@@ -1094,7 +1094,7 @@ pub fn vcadd_rot90_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
 }
 #[doc = "Floating-point complex add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaddq_rot90_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
 #[cfg_attr(test, assert_instr(fcadd))]
@@ -1110,7 +1110,7 @@ pub fn vcaddq_rot90_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
 }
 #[doc = "Floating-point complex add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaddq_rot90_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
 #[cfg_attr(test, assert_instr(fcadd))]
@@ -1126,7 +1126,7 @@ pub fn vcaddq_rot90_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
 }
 #[doc = "Floating-point absolute compare greater than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcage_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(facge))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1142,7 +1142,7 @@ pub fn vcage_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t {
 }
 #[doc = "Floating-point absolute compare greater than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcageq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(facge))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1158,7 +1158,7 @@ pub fn vcageq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t {
 }
 #[doc = "Floating-point absolute compare greater than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaged_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(facge))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1174,7 +1174,7 @@ pub fn vcaged_f64(a: f64, b: f64) -> u64 {
 }
 #[doc = "Floating-point absolute compare greater than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcages_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(facge))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1190,7 +1190,7 @@ pub fn vcages_f32(a: f32, b: f32) -> u32 {
 }
 #[doc = "Floating-point absolute compare greater than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcageh_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(facge))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -1207,7 +1207,7 @@ pub fn vcageh_f16(a: f16, b: f16) -> u16 {
 }
 #[doc = "Floating-point absolute compare greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcagt_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(facgt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1223,7 +1223,7 @@ pub fn vcagt_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t {
 }
 #[doc = "Floating-point absolute compare greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcagtq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(facgt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1239,7 +1239,7 @@ pub fn vcagtq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t {
 }
 #[doc = "Floating-point absolute compare greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcagtd_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(facgt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1255,7 +1255,7 @@ pub fn vcagtd_f64(a: f64, b: f64) -> u64 {
 }
 #[doc = "Floating-point absolute compare greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcagts_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(facgt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1271,7 +1271,7 @@ pub fn vcagts_f32(a: f32, b: f32) -> u32 {
 }
 #[doc = "Floating-point absolute compare greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcagth_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(facgt))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -1288,7 +1288,7 @@ pub fn vcagth_f16(a: f16, b: f16) -> u16 {
 }
 #[doc = "Floating-point absolute compare less than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcale_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(facge))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1297,7 +1297,7 @@ pub fn vcale_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t {
 }
 #[doc = "Floating-point absolute compare less than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaleq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(facge))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1306,7 +1306,7 @@ pub fn vcaleq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t {
 }
 #[doc = "Floating-point absolute compare less than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaled_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(facge))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1315,7 +1315,7 @@ pub fn vcaled_f64(a: f64, b: f64) -> u64 {
 }
 #[doc = "Floating-point absolute compare less than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcales_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(facge))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1324,7 +1324,7 @@ pub fn vcales_f32(a: f32, b: f32) -> u32 {
 }
 #[doc = "Floating-point absolute compare less than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaleh_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(facge))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -1334,7 +1334,7 @@ pub fn vcaleh_f16(a: f16, b: f16) -> u16 {
 }
 #[doc = "Floating-point absolute compare less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcalt_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(facgt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1343,7 +1343,7 @@ pub fn vcalt_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t {
 }
 #[doc = "Floating-point absolute compare less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaltq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(facgt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1352,7 +1352,7 @@ pub fn vcaltq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t {
 }
 #[doc = "Floating-point absolute compare less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaltd_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(facgt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1361,7 +1361,7 @@ pub fn vcaltd_f64(a: f64, b: f64) -> u64 {
 }
 #[doc = "Floating-point absolute compare less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcalts_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(facgt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1370,7 +1370,7 @@ pub fn vcalts_f32(a: f32, b: f32) -> u32 {
 }
 #[doc = "Floating-point absolute compare less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcalth_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(facgt))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -1380,7 +1380,7 @@ pub fn vcalth_f16(a: f16, b: f16) -> u16 {
 }
 #[doc = "Floating-point compare equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmeq))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1389,7 +1389,7 @@ pub fn vceq_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t {
 }
 #[doc = "Floating-point compare equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmeq))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1398,7 +1398,7 @@ pub fn vceqq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t {
 }
 #[doc = "Compare bitwise Equal (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmeq))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1407,7 +1407,7 @@ pub fn vceq_s64(a: int64x1_t, b: int64x1_t) -> uint64x1_t {
 }
 #[doc = "Compare bitwise Equal (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmeq))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1416,7 +1416,7 @@ pub fn vceqq_s64(a: int64x2_t, b: int64x2_t) -> uint64x2_t {
 }
 #[doc = "Compare bitwise Equal (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmeq))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1425,7 +1425,7 @@ pub fn vceq_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
 }
 #[doc = "Compare bitwise Equal (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmeq))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1434,7 +1434,7 @@ pub fn vceqq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Compare bitwise Equal (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_p64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmeq))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1443,7 +1443,7 @@ pub fn vceq_p64(a: poly64x1_t, b: poly64x1_t) -> uint64x1_t {
 }
 #[doc = "Compare bitwise Equal (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_p64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmeq))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1452,7 +1452,7 @@ pub fn vceqq_p64(a: poly64x2_t, b: poly64x2_t) -> uint64x2_t {
 }
 #[doc = "Floating-point compare equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqd_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1461,7 +1461,7 @@ pub fn vceqd_f64(a: f64, b: f64) -> u64 {
 }
 #[doc = "Floating-point compare equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqs_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1470,7 +1470,7 @@ pub fn vceqs_f32(a: f32, b: f32) -> u32 {
 }
 #[doc = "Compare bitwise equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqd_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1479,7 +1479,7 @@ pub fn vceqd_s64(a: i64, b: i64) -> u64 {
 }
 #[doc = "Compare bitwise equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqd_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1488,7 +1488,7 @@ pub fn vceqd_u64(a: u64, b: u64) -> u64 {
 }
 #[doc = "Floating-point compare equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqh_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcmp))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -1498,7 +1498,7 @@ pub fn vceqh_f16(a: f16, b: f16) -> u16 {
 }
 #[doc = "Floating-point compare bitwise equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcmeq))]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
@@ -1509,7 +1509,7 @@ pub fn vceqz_f16(a: float16x4_t) -> uint16x4_t {
 }
 #[doc = "Floating-point compare bitwise equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcmeq))]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
@@ -1520,7 +1520,7 @@ pub fn vceqzq_f16(a: float16x8_t) -> uint16x8_t {
 }
 #[doc = "Floating-point compare bitwise equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmeq))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1530,7 +1530,7 @@ pub fn vceqz_f32(a: float32x2_t) -> uint32x2_t {
 }
 #[doc = "Floating-point compare bitwise equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmeq))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1540,7 +1540,7 @@ pub fn vceqzq_f32(a: float32x4_t) -> uint32x4_t {
 }
 #[doc = "Floating-point compare bitwise equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmeq))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1550,7 +1550,7 @@ pub fn vceqz_f64(a: float64x1_t) -> uint64x1_t {
 }
 #[doc = "Floating-point compare bitwise equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmeq))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1560,7 +1560,7 @@ pub fn vceqzq_f64(a: float64x2_t) -> uint64x2_t {
 }
 #[doc = "Signed compare bitwise equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmeq))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1570,7 +1570,7 @@ pub fn vceqz_s8(a: int8x8_t) -> uint8x8_t {
 }
 #[doc = "Signed compare bitwise equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmeq))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1580,7 +1580,7 @@ pub fn vceqzq_s8(a: int8x16_t) -> uint8x16_t {
 }
 #[doc = "Signed compare bitwise equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmeq))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1590,7 +1590,7 @@ pub fn vceqz_s16(a: int16x4_t) -> uint16x4_t {
 }
 #[doc = "Signed compare bitwise equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmeq))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1600,7 +1600,7 @@ pub fn vceqzq_s16(a: int16x8_t) -> uint16x8_t {
 }
 #[doc = "Signed compare bitwise equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmeq))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1610,7 +1610,7 @@ pub fn vceqz_s32(a: int32x2_t) -> uint32x2_t {
 }
 #[doc = "Signed compare bitwise equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmeq))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1620,7 +1620,7 @@ pub fn vceqzq_s32(a: int32x4_t) -> uint32x4_t {
 }
 #[doc = "Signed compare bitwise equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmeq))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1630,7 +1630,7 @@ pub fn vceqz_s64(a: int64x1_t) -> uint64x1_t {
 }
 #[doc = "Signed compare bitwise equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmeq))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1640,7 +1640,7 @@ pub fn vceqzq_s64(a: int64x2_t) -> uint64x2_t {
 }
 #[doc = "Signed compare bitwise equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmeq))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1650,7 +1650,7 @@ pub fn vceqz_p8(a: poly8x8_t) -> uint8x8_t {
 }
 #[doc = "Signed compare bitwise equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmeq))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1660,7 +1660,7 @@ pub fn vceqzq_p8(a: poly8x16_t) -> uint8x16_t {
 }
 #[doc = "Signed compare bitwise equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_p64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmeq))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1670,7 +1670,7 @@ pub fn vceqz_p64(a: poly64x1_t) -> uint64x1_t {
 }
 #[doc = "Signed compare bitwise equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_p64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmeq))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1680,7 +1680,7 @@ pub fn vceqzq_p64(a: poly64x2_t) -> uint64x2_t {
 }
 #[doc = "Unsigned compare bitwise equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmeq))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1690,7 +1690,7 @@ pub fn vceqz_u8(a: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Unsigned compare bitwise equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmeq))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1700,7 +1700,7 @@ pub fn vceqzq_u8(a: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Unsigned compare bitwise equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmeq))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1710,7 +1710,7 @@ pub fn vceqz_u16(a: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Unsigned compare bitwise equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmeq))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1720,7 +1720,7 @@ pub fn vceqzq_u16(a: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Unsigned compare bitwise equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmeq))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1730,7 +1730,7 @@ pub fn vceqz_u32(a: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Unsigned compare bitwise equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmeq))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1740,7 +1740,7 @@ pub fn vceqzq_u32(a: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Unsigned compare bitwise equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmeq))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1750,7 +1750,7 @@ pub fn vceqz_u64(a: uint64x1_t) -> uint64x1_t {
 }
 #[doc = "Unsigned compare bitwise equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmeq))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1760,7 +1760,7 @@ pub fn vceqzq_u64(a: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Compare bitwise equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzd_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1769,7 +1769,7 @@ pub fn vceqzd_s64(a: i64) -> u64 {
 }
 #[doc = "Compare bitwise equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzd_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1778,7 +1778,7 @@ pub fn vceqzd_u64(a: u64) -> u64 {
 }
 #[doc = "Floating-point compare bitwise equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzh_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcmp))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -1788,7 +1788,7 @@ pub fn vceqzh_f16(a: f16) -> u16 {
 }
 #[doc = "Floating-point compare bitwise equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzs_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1797,7 +1797,7 @@ pub fn vceqzs_f32(a: f32) -> u32 {
 }
 #[doc = "Floating-point compare bitwise equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzd_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1806,7 +1806,7 @@ pub fn vceqzd_f64(a: f64) -> u64 {
 }
 #[doc = "Floating-point compare greater than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmge))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1815,7 +1815,7 @@ pub fn vcge_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t {
 }
 #[doc = "Floating-point compare greater than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmge))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1824,7 +1824,7 @@ pub fn vcgeq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t {
 }
 #[doc = "Compare signed greater than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmge))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1833,7 +1833,7 @@ pub fn vcge_s64(a: int64x1_t, b: int64x1_t) -> uint64x1_t {
 }
 #[doc = "Compare signed greater than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmge))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1842,7 +1842,7 @@ pub fn vcgeq_s64(a: int64x2_t, b: int64x2_t) -> uint64x2_t {
 }
 #[doc = "Compare unsigned greater than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmhs))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1851,7 +1851,7 @@ pub fn vcge_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
 }
 #[doc = "Compare unsigned greater than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmhs))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1860,7 +1860,7 @@ pub fn vcgeq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Floating-point compare greater than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcged_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1869,7 +1869,7 @@ pub fn vcged_f64(a: f64, b: f64) -> u64 {
 }
 #[doc = "Floating-point compare greater than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcges_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1878,7 +1878,7 @@ pub fn vcges_f32(a: f32, b: f32) -> u32 {
 }
 #[doc = "Compare greater than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcged_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1887,7 +1887,7 @@ pub fn vcged_s64(a: i64, b: i64) -> u64 {
 }
 #[doc = "Compare greater than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcged_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1896,7 +1896,7 @@ pub fn vcged_u64(a: u64, b: u64) -> u64 {
 }
 #[doc = "Floating-point compare greater than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeh_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcmp))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -1906,7 +1906,7 @@ pub fn vcgeh_f16(a: f16, b: f16) -> u16 {
 }
 #[doc = "Floating-point compare greater than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgez_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmge))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1916,7 +1916,7 @@ pub fn vcgez_f32(a: float32x2_t) -> uint32x2_t {
 }
 #[doc = "Floating-point compare greater than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmge))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1926,7 +1926,7 @@ pub fn vcgezq_f32(a: float32x4_t) -> uint32x4_t {
 }
 #[doc = "Floating-point compare greater than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgez_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmge))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1936,7 +1936,7 @@ pub fn vcgez_f64(a: float64x1_t) -> uint64x1_t {
 }
 #[doc = "Floating-point compare greater than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmge))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1946,7 +1946,7 @@ pub fn vcgezq_f64(a: float64x2_t) -> uint64x2_t {
 }
 #[doc = "Compare signed greater than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgez_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmge))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1956,7 +1956,7 @@ pub fn vcgez_s8(a: int8x8_t) -> uint8x8_t {
 }
 #[doc = "Compare signed greater than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmge))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1966,7 +1966,7 @@ pub fn vcgezq_s8(a: int8x16_t) -> uint8x16_t {
 }
 #[doc = "Compare signed greater than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgez_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmge))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1976,7 +1976,7 @@ pub fn vcgez_s16(a: int16x4_t) -> uint16x4_t {
 }
 #[doc = "Compare signed greater than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmge))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1986,7 +1986,7 @@ pub fn vcgezq_s16(a: int16x8_t) -> uint16x8_t {
 }
 #[doc = "Compare signed greater than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgez_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmge))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -1996,7 +1996,7 @@ pub fn vcgez_s32(a: int32x2_t) -> uint32x2_t {
 }
 #[doc = "Compare signed greater than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmge))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2006,7 +2006,7 @@ pub fn vcgezq_s32(a: int32x4_t) -> uint32x4_t {
 }
 #[doc = "Compare signed greater than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgez_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmge))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2016,7 +2016,7 @@ pub fn vcgez_s64(a: int64x1_t) -> uint64x1_t {
 }
 #[doc = "Compare signed greater than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezq_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmge))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2026,7 +2026,7 @@ pub fn vcgezq_s64(a: int64x2_t) -> uint64x2_t {
 }
 #[doc = "Floating-point compare greater than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezd_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2035,7 +2035,7 @@ pub fn vcgezd_f64(a: f64) -> u64 {
 }
 #[doc = "Floating-point compare greater than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezs_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2044,7 +2044,7 @@ pub fn vcgezs_f32(a: f32) -> u32 {
 }
 #[doc = "Compare signed greater than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezd_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(nop))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2053,7 +2053,7 @@ pub fn vcgezd_s64(a: i64) -> u64 {
 }
 #[doc = "Floating-point compare greater than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezh_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcmp))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -2063,7 +2063,7 @@ pub fn vcgezh_f16(a: f16) -> u16 {
 }
 #[doc = "Floating-point compare greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmgt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2072,7 +2072,7 @@ pub fn vcgt_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t {
 }
 #[doc = "Floating-point compare greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmgt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2081,7 +2081,7 @@ pub fn vcgtq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t {
 }
 #[doc = "Compare signed greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmgt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2090,7 +2090,7 @@ pub fn vcgt_s64(a: int64x1_t, b: int64x1_t) -> uint64x1_t {
 }
 #[doc = "Compare signed greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmgt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2099,7 +2099,7 @@ pub fn vcgtq_s64(a: int64x2_t, b: int64x2_t) -> uint64x2_t {
 }
 #[doc = "Compare unsigned greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmhi))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2108,7 +2108,7 @@ pub fn vcgt_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
 }
 #[doc = "Compare unsigned greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmhi))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2117,7 +2117,7 @@ pub fn vcgtq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Floating-point compare greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtd_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2126,7 +2126,7 @@ pub fn vcgtd_f64(a: f64, b: f64) -> u64 {
 }
 #[doc = "Floating-point compare greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgts_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2135,7 +2135,7 @@ pub fn vcgts_f32(a: f32, b: f32) -> u32 {
 }
 #[doc = "Compare greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtd_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2144,7 +2144,7 @@ pub fn vcgtd_s64(a: i64, b: i64) -> u64 {
 }
 #[doc = "Compare greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtd_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2153,7 +2153,7 @@ pub fn vcgtd_u64(a: u64, b: u64) -> u64 {
 }
 #[doc = "Floating-point compare greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgth_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcmp))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -2163,7 +2163,7 @@ pub fn vcgth_f16(a: f16, b: f16) -> u16 {
 }
 #[doc = "Floating-point compare greater than zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtz_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmgt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2173,7 +2173,7 @@ pub fn vcgtz_f32(a: float32x2_t) -> uint32x2_t {
 }
 #[doc = "Floating-point compare greater than zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtzq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmgt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2183,7 +2183,7 @@ pub fn vcgtzq_f32(a: float32x4_t) -> uint32x4_t {
 }
 #[doc = "Floating-point compare greater than zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtz_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmgt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2193,7 +2193,7 @@ pub fn vcgtz_f64(a: float64x1_t) -> uint64x1_t {
 }
 #[doc = "Floating-point compare greater than zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtzq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmgt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2203,7 +2203,7 @@ pub fn vcgtzq_f64(a: float64x2_t) -> uint64x2_t {
 }
 #[doc = "Compare signed greater than zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtz_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmgt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2213,7 +2213,7 @@ pub fn vcgtz_s8(a: int8x8_t) -> uint8x8_t {
 }
 #[doc = "Compare signed greater than zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtzq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmgt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2223,7 +2223,7 @@ pub fn vcgtzq_s8(a: int8x16_t) -> uint8x16_t {
 }
 #[doc = "Compare signed greater than zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtz_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmgt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2233,7 +2233,7 @@ pub fn vcgtz_s16(a: int16x4_t) -> uint16x4_t {
 }
 #[doc = "Compare signed greater than zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtzq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmgt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2243,7 +2243,7 @@ pub fn vcgtzq_s16(a: int16x8_t) -> uint16x8_t {
 }
 #[doc = "Compare signed greater than zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtz_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmgt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2253,7 +2253,7 @@ pub fn vcgtz_s32(a: int32x2_t) -> uint32x2_t {
 }
 #[doc = "Compare signed greater than zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtzq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmgt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2263,7 +2263,7 @@ pub fn vcgtzq_s32(a: int32x4_t) -> uint32x4_t {
 }
 #[doc = "Compare signed greater than zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtz_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmgt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2273,7 +2273,7 @@ pub fn vcgtz_s64(a: int64x1_t) -> uint64x1_t {
 }
 #[doc = "Compare signed greater than zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtzq_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmgt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2283,7 +2283,7 @@ pub fn vcgtzq_s64(a: int64x2_t) -> uint64x2_t {
 }
 #[doc = "Floating-point compare greater than zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtzd_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2292,7 +2292,7 @@ pub fn vcgtzd_f64(a: f64) -> u64 {
 }
 #[doc = "Floating-point compare greater than zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtzs_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2301,7 +2301,7 @@ pub fn vcgtzs_f32(a: f32) -> u32 {
 }
 #[doc = "Compare signed greater than zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtzd_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2310,7 +2310,7 @@ pub fn vcgtzd_s64(a: i64) -> u64 {
 }
 #[doc = "Floating-point compare greater than zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtzh_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcmp))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -2320,7 +2320,7 @@ pub fn vcgtzh_f16(a: f16) -> u16 {
 }
 #[doc = "Floating-point compare less than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmge))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2329,7 +2329,7 @@ pub fn vcle_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t {
 }
 #[doc = "Floating-point compare less than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmge))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2338,7 +2338,7 @@ pub fn vcleq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t {
 }
 #[doc = "Compare signed less than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmge))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2347,7 +2347,7 @@ pub fn vcle_s64(a: int64x1_t, b: int64x1_t) -> uint64x1_t {
 }
 #[doc = "Compare signed less than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmge))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2356,7 +2356,7 @@ pub fn vcleq_s64(a: int64x2_t, b: int64x2_t) -> uint64x2_t {
 }
 #[doc = "Compare unsigned less than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmhs))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2365,7 +2365,7 @@ pub fn vcle_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
 }
 #[doc = "Compare unsigned less than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmhs))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2374,7 +2374,7 @@ pub fn vcleq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Floating-point compare less than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcled_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2383,7 +2383,7 @@ pub fn vcled_f64(a: f64, b: f64) -> u64 {
 }
 #[doc = "Floating-point compare less than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcles_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2392,7 +2392,7 @@ pub fn vcles_f32(a: f32, b: f32) -> u32 {
 }
 #[doc = "Compare less than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcled_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2401,7 +2401,7 @@ pub fn vcled_u64(a: u64, b: u64) -> u64 {
 }
 #[doc = "Compare less than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcled_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2410,7 +2410,7 @@ pub fn vcled_s64(a: i64, b: i64) -> u64 {
 }
 #[doc = "Floating-point compare less than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleh_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcmp))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -2420,7 +2420,7 @@ pub fn vcleh_f16(a: f16, b: f16) -> u16 {
 }
 #[doc = "Floating-point compare less than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclez_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmle))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2430,7 +2430,7 @@ pub fn vclez_f32(a: float32x2_t) -> uint32x2_t {
 }
 #[doc = "Floating-point compare less than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmle))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2440,7 +2440,7 @@ pub fn vclezq_f32(a: float32x4_t) -> uint32x4_t {
 }
 #[doc = "Floating-point compare less than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclez_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmle))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2450,7 +2450,7 @@ pub fn vclez_f64(a: float64x1_t) -> uint64x1_t {
 }
 #[doc = "Floating-point compare less than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmle))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2460,7 +2460,7 @@ pub fn vclezq_f64(a: float64x2_t) -> uint64x2_t {
 }
 #[doc = "Compare signed less than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclez_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmle))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2470,7 +2470,7 @@ pub fn vclez_s8(a: int8x8_t) -> uint8x8_t {
 }
 #[doc = "Compare signed less than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmle))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2480,7 +2480,7 @@ pub fn vclezq_s8(a: int8x16_t) -> uint8x16_t {
 }
 #[doc = "Compare signed less than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclez_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmle))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2490,7 +2490,7 @@ pub fn vclez_s16(a: int16x4_t) -> uint16x4_t {
 }
 #[doc = "Compare signed less than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmle))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2500,7 +2500,7 @@ pub fn vclezq_s16(a: int16x8_t) -> uint16x8_t {
 }
 #[doc = "Compare signed less than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclez_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmle))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2510,7 +2510,7 @@ pub fn vclez_s32(a: int32x2_t) -> uint32x2_t {
 }
 #[doc = "Compare signed less than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmle))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2520,7 +2520,7 @@ pub fn vclezq_s32(a: int32x4_t) -> uint32x4_t {
 }
 #[doc = "Compare signed less than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclez_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmle))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2530,7 +2530,7 @@ pub fn vclez_s64(a: int64x1_t) -> uint64x1_t {
 }
 #[doc = "Compare signed less than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezq_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmle))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2540,7 +2540,7 @@ pub fn vclezq_s64(a: int64x2_t) -> uint64x2_t {
 }
 #[doc = "Floating-point compare less than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezd_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2549,7 +2549,7 @@ pub fn vclezd_f64(a: f64) -> u64 {
 }
 #[doc = "Floating-point compare less than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezs_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2558,7 +2558,7 @@ pub fn vclezs_f32(a: f32) -> u32 {
 }
 #[doc = "Compare less than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezd_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2567,7 +2567,7 @@ pub fn vclezd_s64(a: i64) -> u64 {
 }
 #[doc = "Floating-point compare less than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezh_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcmp))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -2577,7 +2577,7 @@ pub fn vclezh_f16(a: f16) -> u16 {
 }
 #[doc = "Floating-point compare less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmgt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2586,7 +2586,7 @@ pub fn vclt_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t {
 }
 #[doc = "Floating-point compare less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmgt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2595,7 +2595,7 @@ pub fn vcltq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t {
 }
 #[doc = "Compare signed less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmgt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2604,7 +2604,7 @@ pub fn vclt_s64(a: int64x1_t, b: int64x1_t) -> uint64x1_t {
 }
 #[doc = "Compare signed less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmgt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2613,7 +2613,7 @@ pub fn vcltq_s64(a: int64x2_t, b: int64x2_t) -> uint64x2_t {
 }
 #[doc = "Compare unsigned less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmhi))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2622,7 +2622,7 @@ pub fn vclt_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
 }
 #[doc = "Compare unsigned less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmhi))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2631,7 +2631,7 @@ pub fn vcltq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Compare less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltd_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2640,7 +2640,7 @@ pub fn vcltd_u64(a: u64, b: u64) -> u64 {
 }
 #[doc = "Compare less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltd_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2649,7 +2649,7 @@ pub fn vcltd_s64(a: i64, b: i64) -> u64 {
 }
 #[doc = "Floating-point compare less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclth_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcmp))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -2659,7 +2659,7 @@ pub fn vclth_f16(a: f16, b: f16) -> u16 {
 }
 #[doc = "Floating-point compare less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclts_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2668,7 +2668,7 @@ pub fn vclts_f32(a: f32, b: f32) -> u32 {
 }
 #[doc = "Floating-point compare less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltd_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2677,7 +2677,7 @@ pub fn vcltd_f64(a: f64, b: f64) -> u64 {
 }
 #[doc = "Floating-point compare less than zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltz_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmlt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2687,7 +2687,7 @@ pub fn vcltz_f32(a: float32x2_t) -> uint32x2_t {
 }
 #[doc = "Floating-point compare less than zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltzq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmlt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2697,7 +2697,7 @@ pub fn vcltzq_f32(a: float32x4_t) -> uint32x4_t {
 }
 #[doc = "Floating-point compare less than zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltz_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmlt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2707,7 +2707,7 @@ pub fn vcltz_f64(a: float64x1_t) -> uint64x1_t {
 }
 #[doc = "Floating-point compare less than zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltzq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmlt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2717,7 +2717,7 @@ pub fn vcltzq_f64(a: float64x2_t) -> uint64x2_t {
 }
 #[doc = "Compare signed less than zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltz_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmlt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2727,7 +2727,7 @@ pub fn vcltz_s8(a: int8x8_t) -> uint8x8_t {
 }
 #[doc = "Compare signed less than zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltzq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmlt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2737,7 +2737,7 @@ pub fn vcltzq_s8(a: int8x16_t) -> uint8x16_t {
 }
 #[doc = "Compare signed less than zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltz_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmlt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2747,7 +2747,7 @@ pub fn vcltz_s16(a: int16x4_t) -> uint16x4_t {
 }
 #[doc = "Compare signed less than zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltzq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmlt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2757,7 +2757,7 @@ pub fn vcltzq_s16(a: int16x8_t) -> uint16x8_t {
 }
 #[doc = "Compare signed less than zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltz_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmlt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2767,7 +2767,7 @@ pub fn vcltz_s32(a: int32x2_t) -> uint32x2_t {
 }
 #[doc = "Compare signed less than zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltzq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmlt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2777,7 +2777,7 @@ pub fn vcltzq_s32(a: int32x4_t) -> uint32x4_t {
 }
 #[doc = "Compare signed less than zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltz_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmlt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2787,7 +2787,7 @@ pub fn vcltz_s64(a: int64x1_t) -> uint64x1_t {
 }
 #[doc = "Compare signed less than zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltzq_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmlt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2797,7 +2797,7 @@ pub fn vcltzq_s64(a: int64x2_t) -> uint64x2_t {
 }
 #[doc = "Floating-point compare less than zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltzd_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2806,7 +2806,7 @@ pub fn vcltzd_f64(a: f64) -> u64 {
 }
 #[doc = "Floating-point compare less than zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltzs_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2815,7 +2815,7 @@ pub fn vcltzs_f32(a: f32) -> u32 {
 }
 #[doc = "Compare less than zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltzd_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(asr))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -2824,7 +2824,7 @@ pub fn vcltzd_s64(a: i64) -> u64 {
 }
 #[doc = "Floating-point compare less than zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltzh_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcmp))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -2834,7 +2834,7 @@ pub fn vcltzh_f16(a: f16) -> u16 {
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
@@ -2852,7 +2852,7 @@ pub fn vcmla_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
@@ -2870,7 +2870,7 @@ pub fn vcmlaq_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> float16x8_t
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
 #[cfg_attr(test, assert_instr(fcmla))]
@@ -2886,7 +2886,7 @@ pub fn vcmla_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
 #[cfg_attr(test, assert_instr(fcmla))]
@@ -2902,7 +2902,7 @@ pub fn vcmlaq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
 #[cfg_attr(test, assert_instr(fcmla))]
@@ -2918,7 +2918,7 @@ pub fn vcmlaq_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_lane_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -2947,7 +2947,7 @@ pub fn vcmla_lane_f16<const LANE: i32>(
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_lane_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -2980,7 +2980,7 @@ pub fn vcmlaq_lane_f16<const LANE: i32>(
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_lane_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -2998,7 +2998,7 @@ pub fn vcmla_lane_f32<const LANE: i32>(
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_lane_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -3025,7 +3025,7 @@ pub fn vcmlaq_lane_f32<const LANE: i32>(
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_laneq_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -3054,7 +3054,7 @@ pub fn vcmla_laneq_f16<const LANE: i32>(
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_laneq_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -3087,7 +3087,7 @@ pub fn vcmlaq_laneq_f16<const LANE: i32>(
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_laneq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -3105,7 +3105,7 @@ pub fn vcmla_laneq_f32<const LANE: i32>(
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_laneq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -3132,7 +3132,7 @@ pub fn vcmlaq_laneq_f32<const LANE: i32>(
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot180_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
@@ -3150,7 +3150,7 @@ pub fn vcmla_rot180_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot180_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
@@ -3168,7 +3168,7 @@ pub fn vcmlaq_rot180_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> floa
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot180_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
 #[cfg_attr(test, assert_instr(fcmla))]
@@ -3184,7 +3184,7 @@ pub fn vcmla_rot180_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot180_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
 #[cfg_attr(test, assert_instr(fcmla))]
@@ -3200,7 +3200,7 @@ pub fn vcmlaq_rot180_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> floa
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot180_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
 #[cfg_attr(test, assert_instr(fcmla))]
@@ -3216,7 +3216,7 @@ pub fn vcmlaq_rot180_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> floa
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot180_lane_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -3245,7 +3245,7 @@ pub fn vcmla_rot180_lane_f16<const LANE: i32>(
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot180_lane_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -3278,7 +3278,7 @@ pub fn vcmlaq_rot180_lane_f16<const LANE: i32>(
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot180_lane_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -3296,7 +3296,7 @@ pub fn vcmla_rot180_lane_f32<const LANE: i32>(
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot180_lane_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -3323,7 +3323,7 @@ pub fn vcmlaq_rot180_lane_f32<const LANE: i32>(
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot180_laneq_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -3352,7 +3352,7 @@ pub fn vcmla_rot180_laneq_f16<const LANE: i32>(
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot180_laneq_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -3385,7 +3385,7 @@ pub fn vcmlaq_rot180_laneq_f16<const LANE: i32>(
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot180_laneq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -3403,7 +3403,7 @@ pub fn vcmla_rot180_laneq_f32<const LANE: i32>(
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot180_laneq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -3430,7 +3430,7 @@ pub fn vcmlaq_rot180_laneq_f32<const LANE: i32>(
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot270_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
@@ -3448,7 +3448,7 @@ pub fn vcmla_rot270_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot270_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
@@ -3466,7 +3466,7 @@ pub fn vcmlaq_rot270_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> floa
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot270_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
 #[cfg_attr(test, assert_instr(fcmla))]
@@ -3482,7 +3482,7 @@ pub fn vcmla_rot270_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot270_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
 #[cfg_attr(test, assert_instr(fcmla))]
@@ -3498,7 +3498,7 @@ pub fn vcmlaq_rot270_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> floa
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot270_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
 #[cfg_attr(test, assert_instr(fcmla))]
@@ -3514,7 +3514,7 @@ pub fn vcmlaq_rot270_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> floa
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot270_lane_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -3543,7 +3543,7 @@ pub fn vcmla_rot270_lane_f16<const LANE: i32>(
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot270_lane_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -3576,7 +3576,7 @@ pub fn vcmlaq_rot270_lane_f16<const LANE: i32>(
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot270_lane_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -3594,7 +3594,7 @@ pub fn vcmla_rot270_lane_f32<const LANE: i32>(
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot270_lane_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -3621,7 +3621,7 @@ pub fn vcmlaq_rot270_lane_f32<const LANE: i32>(
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot270_laneq_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -3650,7 +3650,7 @@ pub fn vcmla_rot270_laneq_f16<const LANE: i32>(
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot270_laneq_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -3683,7 +3683,7 @@ pub fn vcmlaq_rot270_laneq_f16<const LANE: i32>(
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot270_laneq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -3701,7 +3701,7 @@ pub fn vcmla_rot270_laneq_f32<const LANE: i32>(
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot270_laneq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -3728,7 +3728,7 @@ pub fn vcmlaq_rot270_laneq_f32<const LANE: i32>(
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot90_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
@@ -3746,7 +3746,7 @@ pub fn vcmla_rot90_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float1
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot90_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
@@ -3764,7 +3764,7 @@ pub fn vcmlaq_rot90_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> float
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot90_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
 #[cfg_attr(test, assert_instr(fcmla))]
@@ -3780,7 +3780,7 @@ pub fn vcmla_rot90_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float3
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot90_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
 #[cfg_attr(test, assert_instr(fcmla))]
@@ -3796,7 +3796,7 @@ pub fn vcmlaq_rot90_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot90_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[unstable(feature = "stdarch_neon_fcma", issue = "117222")]
 #[cfg_attr(test, assert_instr(fcmla))]
@@ -3812,7 +3812,7 @@ pub fn vcmlaq_rot90_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot90_lane_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -3841,7 +3841,7 @@ pub fn vcmla_rot90_lane_f16<const LANE: i32>(
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot90_lane_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -3874,7 +3874,7 @@ pub fn vcmlaq_rot90_lane_f16<const LANE: i32>(
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot90_lane_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -3892,7 +3892,7 @@ pub fn vcmla_rot90_lane_f32<const LANE: i32>(
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot90_lane_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -3919,7 +3919,7 @@ pub fn vcmlaq_rot90_lane_f32<const LANE: i32>(
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot90_laneq_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -3948,7 +3948,7 @@ pub fn vcmla_rot90_laneq_f16<const LANE: i32>(
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot90_laneq_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -3981,7 +3981,7 @@ pub fn vcmlaq_rot90_laneq_f16<const LANE: i32>(
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot90_laneq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -3999,7 +3999,7 @@ pub fn vcmla_rot90_laneq_f32<const LANE: i32>(
 }
 #[doc = "Floating-point complex multiply accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot90_laneq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fcma")]
 #[cfg_attr(test, assert_instr(fcmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -4026,7 +4026,7 @@ pub fn vcmlaq_rot90_laneq_f32<const LANE: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -4047,7 +4047,7 @@ pub fn vcopy_lane_f32<const LANE1: i32, const LANE2: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -4071,7 +4071,7 @@ pub fn vcopy_lane_s8<const LANE1: i32, const LANE2: i32>(a: int8x8_t, b: int8x8_
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -4091,7 +4091,7 @@ pub fn vcopy_lane_s16<const LANE1: i32, const LANE2: i32>(a: int16x4_t, b: int16
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -4109,7 +4109,7 @@ pub fn vcopy_lane_s32<const LANE1: i32, const LANE2: i32>(a: int32x2_t, b: int32
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -4133,7 +4133,7 @@ pub fn vcopy_lane_u8<const LANE1: i32, const LANE2: i32>(a: uint8x8_t, b: uint8x
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -4156,7 +4156,7 @@ pub fn vcopy_lane_u16<const LANE1: i32, const LANE2: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -4177,7 +4177,7 @@ pub fn vcopy_lane_u32<const LANE1: i32, const LANE2: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -4201,7 +4201,7 @@ pub fn vcopy_lane_p8<const LANE1: i32, const LANE2: i32>(a: poly8x8_t, b: poly8x
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_p16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -4224,7 +4224,7 @@ pub fn vcopy_lane_p16<const LANE1: i32, const LANE2: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -4246,7 +4246,7 @@ pub fn vcopy_laneq_f32<const LANE1: i32, const LANE2: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -4272,7 +4272,7 @@ pub fn vcopy_laneq_s8<const LANE1: i32, const LANE2: i32>(a: int8x8_t, b: int8x1
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -4296,7 +4296,7 @@ pub fn vcopy_laneq_s16<const LANE1: i32, const LANE2: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -4318,7 +4318,7 @@ pub fn vcopy_laneq_s32<const LANE1: i32, const LANE2: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -4347,7 +4347,7 @@ pub fn vcopy_laneq_u8<const LANE1: i32, const LANE2: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -4371,7 +4371,7 @@ pub fn vcopy_laneq_u16<const LANE1: i32, const LANE2: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -4393,7 +4393,7 @@ pub fn vcopy_laneq_u32<const LANE1: i32, const LANE2: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -4422,7 +4422,7 @@ pub fn vcopy_laneq_p8<const LANE1: i32, const LANE2: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_p16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -4446,7 +4446,7 @@ pub fn vcopy_laneq_p16<const LANE1: i32, const LANE2: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 1, LANE2 = 0))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -4470,7 +4470,7 @@ pub fn vcopyq_lane_f32<const LANE1: i32, const LANE2: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 1, LANE2 = 0))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -4492,7 +4492,7 @@ pub fn vcopyq_lane_f64<const LANE1: i32, const LANE2: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 1, LANE2 = 0))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -4514,7 +4514,7 @@ pub fn vcopyq_lane_s64<const LANE1: i32, const LANE2: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 1, LANE2 = 0))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -4536,7 +4536,7 @@ pub fn vcopyq_lane_u64<const LANE1: i32, const LANE2: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_p64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 1, LANE2 = 0))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -4558,7 +4558,7 @@ pub fn vcopyq_lane_p64<const LANE1: i32, const LANE2: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -4928,7 +4928,7 @@ pub fn vcopyq_lane_s8<const LANE1: i32, const LANE2: i32>(a: int8x16_t, b: int8x
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -4956,7 +4956,7 @@ pub fn vcopyq_lane_s16<const LANE1: i32, const LANE2: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -4980,7 +4980,7 @@ pub fn vcopyq_lane_s32<const LANE1: i32, const LANE2: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -5353,7 +5353,7 @@ pub fn vcopyq_lane_u8<const LANE1: i32, const LANE2: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -5381,7 +5381,7 @@ pub fn vcopyq_lane_u16<const LANE1: i32, const LANE2: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -5405,7 +5405,7 @@ pub fn vcopyq_lane_u32<const LANE1: i32, const LANE2: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -5778,7 +5778,7 @@ pub fn vcopyq_lane_p8<const LANE1: i32, const LANE2: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_p16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -5806,7 +5806,7 @@ pub fn vcopyq_lane_p16<const LANE1: i32, const LANE2: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -5829,7 +5829,7 @@ pub fn vcopyq_laneq_f32<const LANE1: i32, const LANE2: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -5850,7 +5850,7 @@ pub fn vcopyq_laneq_f64<const LANE1: i32, const LANE2: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -6221,7 +6221,7 @@ pub fn vcopyq_laneq_s8<const LANE1: i32, const LANE2: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -6248,7 +6248,7 @@ pub fn vcopyq_laneq_s16<const LANE1: i32, const LANE2: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -6271,7 +6271,7 @@ pub fn vcopyq_laneq_s32<const LANE1: i32, const LANE2: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -6292,7 +6292,7 @@ pub fn vcopyq_laneq_s64<const LANE1: i32, const LANE2: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -6663,7 +6663,7 @@ pub fn vcopyq_laneq_u8<const LANE1: i32, const LANE2: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -6690,7 +6690,7 @@ pub fn vcopyq_laneq_u16<const LANE1: i32, const LANE2: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -6713,7 +6713,7 @@ pub fn vcopyq_laneq_u32<const LANE1: i32, const LANE2: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -6734,7 +6734,7 @@ pub fn vcopyq_laneq_u64<const LANE1: i32, const LANE2: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -7105,7 +7105,7 @@ pub fn vcopyq_laneq_p8<const LANE1: i32, const LANE2: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_p16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -7132,7 +7132,7 @@ pub fn vcopyq_laneq_p16<const LANE1: i32, const LANE2: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_p64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
 #[rustc_legacy_const_generics(1, 3)]
@@ -7153,7 +7153,7 @@ pub fn vcopyq_laneq_p64<const LANE1: i32, const LANE2: i32>(
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(nop))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -7162,7 +7162,7 @@ pub fn vcreate_f64(a: u64) -> float64x1_t {
 }
 #[doc = "Floating-point convert"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f32_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtn))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -7171,7 +7171,7 @@ pub fn vcvt_f32_f64(a: float64x2_t) -> float32x2_t {
 }
 #[doc = "Floating-point convert to higher precision long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f64_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -7180,7 +7180,7 @@ pub fn vcvt_f64_f32(a: float32x2_t) -> float64x2_t {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f64_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(scvtf))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -7189,7 +7189,7 @@ pub fn vcvt_f64_s64(a: int64x1_t) -> float64x1_t {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_f64_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(scvtf))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -7198,7 +7198,7 @@ pub fn vcvtq_f64_s64(a: int64x2_t) -> float64x2_t {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f64_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ucvtf))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -7207,7 +7207,7 @@ pub fn vcvt_f64_u64(a: uint64x1_t) -> float64x1_t {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_f64_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ucvtf))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -7216,7 +7216,7 @@ pub fn vcvtq_f64_u64(a: uint64x2_t) -> float64x2_t {
 }
 #[doc = "Floating-point convert to lower precision"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_high_f16_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtn2))]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
@@ -7226,7 +7226,7 @@ pub fn vcvt_high_f16_f32(a: float16x4_t, b: float32x4_t) -> float16x8_t {
 }
 #[doc = "Floating-point convert to higher precision"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_high_f32_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtl2))]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
@@ -7236,7 +7236,7 @@ pub fn vcvt_high_f32_f16(a: float16x8_t) -> float32x4_t {
 }
 #[doc = "Floating-point convert to lower precision narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_high_f32_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtn2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -7245,7 +7245,7 @@ pub fn vcvt_high_f32_f64(a: float32x2_t, b: float64x2_t) -> float32x4_t {
 }
 #[doc = "Floating-point convert to higher precision long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_high_f64_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtl2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -7257,7 +7257,7 @@ pub fn vcvt_high_f64_f32(a: float32x4_t) -> float64x2_t {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_f64_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(scvtf, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -7275,7 +7275,7 @@ pub fn vcvt_n_f64_s64<const N: i32>(a: int64x1_t) -> float64x1_t {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_f64_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(scvtf, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -7293,7 +7293,7 @@ pub fn vcvtq_n_f64_s64<const N: i32>(a: int64x2_t) -> float64x2_t {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_f64_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ucvtf, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -7311,7 +7311,7 @@ pub fn vcvt_n_f64_u64<const N: i32>(a: uint64x1_t) -> float64x1_t {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_f64_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ucvtf, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -7329,7 +7329,7 @@ pub fn vcvtq_n_f64_u64<const N: i32>(a: uint64x2_t) -> float64x2_t {
 }
 #[doc = "Floating-point convert to fixed-point, rounding toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_s64_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtzs, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -7347,7 +7347,7 @@ pub fn vcvt_n_s64_f64<const N: i32>(a: float64x1_t) -> int64x1_t {
 }
 #[doc = "Floating-point convert to fixed-point, rounding toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_s64_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtzs, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -7365,7 +7365,7 @@ pub fn vcvtq_n_s64_f64<const N: i32>(a: float64x2_t) -> int64x2_t {
 }
 #[doc = "Floating-point convert to fixed-point, rounding toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_u64_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtzu, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -7383,7 +7383,7 @@ pub fn vcvt_n_u64_f64<const N: i32>(a: float64x1_t) -> uint64x1_t {
 }
 #[doc = "Floating-point convert to fixed-point, rounding toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_u64_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtzu, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -7401,7 +7401,7 @@ pub fn vcvtq_n_u64_f64<const N: i32>(a: float64x2_t) -> uint64x2_t {
 }
 #[doc = "Floating-point convert to signed fixed-point, rounding toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_s64_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtzs))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -7417,7 +7417,7 @@ pub fn vcvt_s64_f64(a: float64x1_t) -> int64x1_t {
 }
 #[doc = "Floating-point convert to signed fixed-point, rounding toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_s64_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtzs))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -7433,7 +7433,7 @@ pub fn vcvtq_s64_f64(a: float64x2_t) -> int64x2_t {
 }
 #[doc = "Floating-point convert to unsigned fixed-point, rounding toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_u64_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtzu))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -7449,7 +7449,7 @@ pub fn vcvt_u64_f64(a: float64x1_t) -> uint64x1_t {
 }
 #[doc = "Floating-point convert to unsigned fixed-point, rounding toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_u64_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtzu))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -7465,7 +7465,7 @@ pub fn vcvtq_u64_f64(a: float64x2_t) -> uint64x2_t {
 }
 #[doc = "Floating-point convert to signed integer, rounding to nearest with ties to away"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvta_s16_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtas))]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
@@ -7482,7 +7482,7 @@ pub fn vcvta_s16_f16(a: float16x4_t) -> int16x4_t {
 }
 #[doc = "Floating-point convert to signed integer, rounding to nearest with ties to away"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtaq_s16_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtas))]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
@@ -7499,7 +7499,7 @@ pub fn vcvtaq_s16_f16(a: float16x8_t) -> int16x8_t {
 }
 #[doc = "Floating-point convert to signed integer, rounding to nearest with ties to away"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvta_s32_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtas))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -7515,7 +7515,7 @@ pub fn vcvta_s32_f32(a: float32x2_t) -> int32x2_t {
 }
 #[doc = "Floating-point convert to signed integer, rounding to nearest with ties to away"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtaq_s32_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtas))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -7531,7 +7531,7 @@ pub fn vcvtaq_s32_f32(a: float32x4_t) -> int32x4_t {
 }
 #[doc = "Floating-point convert to signed integer, rounding to nearest with ties to away"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvta_s64_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtas))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -7547,7 +7547,7 @@ pub fn vcvta_s64_f64(a: float64x1_t) -> int64x1_t {
 }
 #[doc = "Floating-point convert to signed integer, rounding to nearest with ties to away"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtaq_s64_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtas))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -7563,7 +7563,7 @@ pub fn vcvtaq_s64_f64(a: float64x2_t) -> int64x2_t {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to away"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvta_u16_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtau))]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
@@ -7580,7 +7580,7 @@ pub fn vcvta_u16_f16(a: float16x4_t) -> uint16x4_t {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to away"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtaq_u16_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtau))]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
@@ -7597,7 +7597,7 @@ pub fn vcvtaq_u16_f16(a: float16x8_t) -> uint16x8_t {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to away"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvta_u32_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtau))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -7613,7 +7613,7 @@ pub fn vcvta_u32_f32(a: float32x2_t) -> uint32x2_t {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to away"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtaq_u32_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtau))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -7629,7 +7629,7 @@ pub fn vcvtaq_u32_f32(a: float32x4_t) -> uint32x4_t {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to away"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvta_u64_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtau))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -7645,7 +7645,7 @@ pub fn vcvta_u64_f64(a: float64x1_t) -> uint64x1_t {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to away"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtaq_u64_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtau))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -7661,7 +7661,7 @@ pub fn vcvtaq_u64_f64(a: float64x2_t) -> uint64x2_t {
 }
 #[doc = "Floating-point convert to integer, rounding to nearest with ties to away"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtah_s16_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtas))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -7671,7 +7671,7 @@ pub fn vcvtah_s16_f16(a: f16) -> i16 {
 }
 #[doc = "Floating-point convert to integer, rounding to nearest with ties to away"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtah_s32_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtas))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -7688,7 +7688,7 @@ pub fn vcvtah_s32_f16(a: f16) -> i32 {
 }
 #[doc = "Floating-point convert to integer, rounding to nearest with ties to away"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtah_s64_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtas))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -7705,7 +7705,7 @@ pub fn vcvtah_s64_f16(a: f16) -> i64 {
 }
 #[doc = "Floating-point convert to integer, rounding to nearest with ties to away"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtah_u16_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtau))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -7715,7 +7715,7 @@ pub fn vcvtah_u16_f16(a: f16) -> u16 {
 }
 #[doc = "Floating-point convert to integer, rounding to nearest with ties to away"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtah_u32_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtau))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -7732,7 +7732,7 @@ pub fn vcvtah_u32_f16(a: f16) -> u32 {
 }
 #[doc = "Floating-point convert to integer, rounding to nearest with ties to away"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtah_u64_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtau))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -7749,7 +7749,7 @@ pub fn vcvtah_u64_f16(a: f16) -> u64 {
 }
 #[doc = "Floating-point convert to integer, rounding to nearest with ties to away"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtas_s32_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtas))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -7765,7 +7765,7 @@ pub fn vcvtas_s32_f32(a: f32) -> i32 {
 }
 #[doc = "Floating-point convert to integer, rounding to nearest with ties to away"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtad_s64_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtas))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -7781,7 +7781,7 @@ pub fn vcvtad_s64_f64(a: f64) -> i64 {
 }
 #[doc = "Floating-point convert to integer, rounding to nearest with ties to away"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtas_u32_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtau))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -7797,7 +7797,7 @@ pub fn vcvtas_u32_f32(a: f32) -> u32 {
 }
 #[doc = "Floating-point convert to integer, rounding to nearest with ties to away"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtad_u64_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtau))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -7813,7 +7813,7 @@ pub fn vcvtad_u64_f64(a: f64) -> u64 {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtd_f64_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(scvtf))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -7822,7 +7822,7 @@ pub fn vcvtd_f64_s64(a: i64) -> f64 {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvts_f32_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(scvtf))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -7831,7 +7831,7 @@ pub fn vcvts_f32_s32(a: i32) -> f32 {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_f16_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(scvtf))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -7841,7 +7841,7 @@ pub fn vcvth_f16_s16(a: i16) -> f16 {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_f16_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(scvtf))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -7851,7 +7851,7 @@ pub fn vcvth_f16_s32(a: i32) -> f16 {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_f16_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(scvtf))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -7861,7 +7861,7 @@ pub fn vcvth_f16_s64(a: i64) -> f16 {
 }
 #[doc = "Unsigned fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_f16_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(ucvtf))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -7871,7 +7871,7 @@ pub fn vcvth_f16_u16(a: u16) -> f16 {
 }
 #[doc = "Unsigned fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_f16_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(ucvtf))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -7881,7 +7881,7 @@ pub fn vcvth_f16_u32(a: u32) -> f16 {
 }
 #[doc = "Unsigned fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_f16_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(ucvtf))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -7891,7 +7891,7 @@ pub fn vcvth_f16_u64(a: u64) -> f16 {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_n_f16_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(scvtf, N = 2))]
 #[rustc_legacy_const_generics(1)]
 #[target_feature(enable = "neon,fp16")]
@@ -7903,7 +7903,7 @@ pub fn vcvth_n_f16_s16<const N: i32>(a: i16) -> f16 {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_n_f16_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(scvtf, N = 2))]
 #[rustc_legacy_const_generics(1)]
 #[target_feature(enable = "neon,fp16")]
@@ -7922,7 +7922,7 @@ pub fn vcvth_n_f16_s32<const N: i32>(a: i32) -> f16 {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_n_f16_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(scvtf, N = 2))]
 #[rustc_legacy_const_generics(1)]
 #[target_feature(enable = "neon,fp16")]
@@ -7941,7 +7941,7 @@ pub fn vcvth_n_f16_s64<const N: i32>(a: i64) -> f16 {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_n_f16_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(ucvtf, N = 2))]
 #[rustc_legacy_const_generics(1)]
 #[target_feature(enable = "neon,fp16")]
@@ -7953,7 +7953,7 @@ pub fn vcvth_n_f16_u16<const N: i32>(a: u16) -> f16 {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_n_f16_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(ucvtf, N = 2))]
 #[rustc_legacy_const_generics(1)]
 #[target_feature(enable = "neon,fp16")]
@@ -7972,7 +7972,7 @@ pub fn vcvth_n_f16_u32<const N: i32>(a: u32) -> f16 {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_n_f16_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(ucvtf, N = 2))]
 #[rustc_legacy_const_generics(1)]
 #[target_feature(enable = "neon,fp16")]
@@ -7991,7 +7991,7 @@ pub fn vcvth_n_f16_u64<const N: i32>(a: u64) -> f16 {
 }
 #[doc = "Floating-point convert to fixed-point, rounding toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_n_s16_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtzs, N = 2))]
 #[rustc_legacy_const_generics(1)]
 #[target_feature(enable = "neon,fp16")]
@@ -8003,7 +8003,7 @@ pub fn vcvth_n_s16_f16<const N: i32>(a: f16) -> i16 {
 }
 #[doc = "Floating-point convert to fixed-point, rounding toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_n_s32_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtzs, N = 2))]
 #[rustc_legacy_const_generics(1)]
 #[target_feature(enable = "neon,fp16")]
@@ -8022,7 +8022,7 @@ pub fn vcvth_n_s32_f16<const N: i32>(a: f16) -> i32 {
 }
 #[doc = "Floating-point convert to fixed-point, rounding toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_n_s64_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtzs, N = 2))]
 #[rustc_legacy_const_generics(1)]
 #[target_feature(enable = "neon,fp16")]
@@ -8041,7 +8041,7 @@ pub fn vcvth_n_s64_f16<const N: i32>(a: f16) -> i64 {
 }
 #[doc = "Floating-point convert to fixed-point, rounding toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_n_u16_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtzu, N = 2))]
 #[rustc_legacy_const_generics(1)]
 #[target_feature(enable = "neon,fp16")]
@@ -8053,7 +8053,7 @@ pub fn vcvth_n_u16_f16<const N: i32>(a: f16) -> u16 {
 }
 #[doc = "Floating-point convert to fixed-point, rounding toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_n_u32_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtzu, N = 2))]
 #[rustc_legacy_const_generics(1)]
 #[target_feature(enable = "neon,fp16")]
@@ -8072,7 +8072,7 @@ pub fn vcvth_n_u32_f16<const N: i32>(a: f16) -> u32 {
 }
 #[doc = "Floating-point convert to fixed-point, rounding toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_n_u64_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtzu, N = 2))]
 #[rustc_legacy_const_generics(1)]
 #[target_feature(enable = "neon,fp16")]
@@ -8091,7 +8091,7 @@ pub fn vcvth_n_u64_f16<const N: i32>(a: f16) -> u64 {
 }
 #[doc = "Floating-point convert to signed fixed-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_s16_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtzs))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -8101,7 +8101,7 @@ pub fn vcvth_s16_f16(a: f16) -> i16 {
 }
 #[doc = "Floating-point convert to signed fixed-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_s32_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtzs))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -8111,7 +8111,7 @@ pub fn vcvth_s32_f16(a: f16) -> i32 {
 }
 #[doc = "Floating-point convert to signed fixed-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_s64_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtzs))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -8121,7 +8121,7 @@ pub fn vcvth_s64_f16(a: f16) -> i64 {
 }
 #[doc = "Floating-point convert to unsigned fixed-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_u16_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtzu))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -8131,7 +8131,7 @@ pub fn vcvth_u16_f16(a: f16) -> u16 {
 }
 #[doc = "Floating-point convert to unsigned fixed-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_u32_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtzu))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -8141,7 +8141,7 @@ pub fn vcvth_u32_f16(a: f16) -> u32 {
 }
 #[doc = "Floating-point convert to unsigned fixed-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvth_u64_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtzu))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -8151,7 +8151,7 @@ pub fn vcvth_u64_f16(a: f16) -> u64 {
 }
 #[doc = "Floating-point convert to signed integer, rounding toward minus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtm_s16_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtms))]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
@@ -8168,7 +8168,7 @@ pub fn vcvtm_s16_f16(a: float16x4_t) -> int16x4_t {
 }
 #[doc = "Floating-point convert to signed integer, rounding toward minus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmq_s16_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtms))]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
@@ -8185,7 +8185,7 @@ pub fn vcvtmq_s16_f16(a: float16x8_t) -> int16x8_t {
 }
 #[doc = "Floating-point convert to signed integer, rounding toward minus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtm_s32_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtms))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -8201,7 +8201,7 @@ pub fn vcvtm_s32_f32(a: float32x2_t) -> int32x2_t {
 }
 #[doc = "Floating-point convert to signed integer, rounding toward minus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmq_s32_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtms))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -8217,7 +8217,7 @@ pub fn vcvtmq_s32_f32(a: float32x4_t) -> int32x4_t {
 }
 #[doc = "Floating-point convert to signed integer, rounding toward minus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtm_s64_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtms))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -8233,7 +8233,7 @@ pub fn vcvtm_s64_f64(a: float64x1_t) -> int64x1_t {
 }
 #[doc = "Floating-point convert to signed integer, rounding toward minus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmq_s64_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtms))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -8249,7 +8249,7 @@ pub fn vcvtmq_s64_f64(a: float64x2_t) -> int64x2_t {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding toward minus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtm_u16_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtmu))]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
@@ -8266,7 +8266,7 @@ pub fn vcvtm_u16_f16(a: float16x4_t) -> uint16x4_t {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding toward minus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmq_u16_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtmu))]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
@@ -8283,7 +8283,7 @@ pub fn vcvtmq_u16_f16(a: float16x8_t) -> uint16x8_t {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding toward minus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtm_u32_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtmu))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -8299,7 +8299,7 @@ pub fn vcvtm_u32_f32(a: float32x2_t) -> uint32x2_t {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding toward minus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmq_u32_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtmu))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -8315,7 +8315,7 @@ pub fn vcvtmq_u32_f32(a: float32x4_t) -> uint32x4_t {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding toward minus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtm_u64_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtmu))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -8331,7 +8331,7 @@ pub fn vcvtm_u64_f64(a: float64x1_t) -> uint64x1_t {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding toward minus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmq_u64_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtmu))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -8347,7 +8347,7 @@ pub fn vcvtmq_u64_f64(a: float64x2_t) -> uint64x2_t {
 }
 #[doc = "Floating-point convert to integer, rounding towards minus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmh_s16_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtms))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -8357,7 +8357,7 @@ pub fn vcvtmh_s16_f16(a: f16) -> i16 {
 }
 #[doc = "Floating-point convert to integer, rounding towards minus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmh_s32_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtms))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -8374,7 +8374,7 @@ pub fn vcvtmh_s32_f16(a: f16) -> i32 {
 }
 #[doc = "Floating-point convert to integer, rounding towards minus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmh_s64_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtms))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -8391,7 +8391,7 @@ pub fn vcvtmh_s64_f16(a: f16) -> i64 {
 }
 #[doc = "Floating-point convert to integer, rounding towards minus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmh_u16_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtmu))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -8401,7 +8401,7 @@ pub fn vcvtmh_u16_f16(a: f16) -> u16 {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding towards minus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmh_u32_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtmu))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -8418,7 +8418,7 @@ pub fn vcvtmh_u32_f16(a: f16) -> u32 {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding towards minus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmh_u64_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtmu))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -8435,7 +8435,7 @@ pub fn vcvtmh_u64_f16(a: f16) -> u64 {
 }
 #[doc = "Floating-point convert to signed integer, rounding toward minus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtms_s32_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtms))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -8451,7 +8451,7 @@ pub fn vcvtms_s32_f32(a: f32) -> i32 {
 }
 #[doc = "Floating-point convert to signed integer, rounding toward minus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmd_s64_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtms))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -8467,7 +8467,7 @@ pub fn vcvtmd_s64_f64(a: f64) -> i64 {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding toward minus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtms_u32_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtmu))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -8483,7 +8483,7 @@ pub fn vcvtms_u32_f32(a: f32) -> u32 {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding toward minus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmd_u64_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtmu))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -8499,7 +8499,7 @@ pub fn vcvtmd_u64_f64(a: f64) -> u64 {
 }
 #[doc = "Floating-point convert to signed integer, rounding to nearest with ties to even"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtn_s16_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtns))]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
@@ -8516,7 +8516,7 @@ pub fn vcvtn_s16_f16(a: float16x4_t) -> int16x4_t {
 }
 #[doc = "Floating-point convert to signed integer, rounding to nearest with ties to even"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnq_s16_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtns))]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
@@ -8533,7 +8533,7 @@ pub fn vcvtnq_s16_f16(a: float16x8_t) -> int16x8_t {
 }
 #[doc = "Floating-point convert to signed integer, rounding to nearest with ties to even"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtn_s32_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtns))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -8549,7 +8549,7 @@ pub fn vcvtn_s32_f32(a: float32x2_t) -> int32x2_t {
 }
 #[doc = "Floating-point convert to signed integer, rounding to nearest with ties to even"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnq_s32_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtns))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -8565,7 +8565,7 @@ pub fn vcvtnq_s32_f32(a: float32x4_t) -> int32x4_t {
 }
 #[doc = "Floating-point convert to signed integer, rounding to nearest with ties to even"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtn_s64_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtns))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -8581,7 +8581,7 @@ pub fn vcvtn_s64_f64(a: float64x1_t) -> int64x1_t {
 }
 #[doc = "Floating-point convert to signed integer, rounding to nearest with ties to even"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnq_s64_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtns))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -8597,7 +8597,7 @@ pub fn vcvtnq_s64_f64(a: float64x2_t) -> int64x2_t {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to even"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtn_u16_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtnu))]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
@@ -8614,7 +8614,7 @@ pub fn vcvtn_u16_f16(a: float16x4_t) -> uint16x4_t {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to even"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnq_u16_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtnu))]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
@@ -8631,7 +8631,7 @@ pub fn vcvtnq_u16_f16(a: float16x8_t) -> uint16x8_t {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to even"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtn_u32_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtnu))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -8647,7 +8647,7 @@ pub fn vcvtn_u32_f32(a: float32x2_t) -> uint32x2_t {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to even"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnq_u32_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtnu))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -8663,7 +8663,7 @@ pub fn vcvtnq_u32_f32(a: float32x4_t) -> uint32x4_t {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to even"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtn_u64_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtnu))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -8679,7 +8679,7 @@ pub fn vcvtn_u64_f64(a: float64x1_t) -> uint64x1_t {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to even"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnq_u64_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtnu))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -8695,7 +8695,7 @@ pub fn vcvtnq_u64_f64(a: float64x2_t) -> uint64x2_t {
 }
 #[doc = "Floating-point convert to integer, rounding to nearest with ties to even"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnh_s16_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtns))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -8705,7 +8705,7 @@ pub fn vcvtnh_s16_f16(a: f16) -> i16 {
 }
 #[doc = "Floating-point convert to integer, rounding to nearest with ties to even"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnh_s32_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtns))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -8722,7 +8722,7 @@ pub fn vcvtnh_s32_f16(a: f16) -> i32 {
 }
 #[doc = "Floating-point convert to integer, rounding to nearest with ties to even"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnh_s64_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtns))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -8739,7 +8739,7 @@ pub fn vcvtnh_s64_f16(a: f16) -> i64 {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to even"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnh_u16_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtnu))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -8749,7 +8749,7 @@ pub fn vcvtnh_u16_f16(a: f16) -> u16 {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to even"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnh_u32_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtnu))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -8766,7 +8766,7 @@ pub fn vcvtnh_u32_f16(a: f16) -> u32 {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to even"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnh_u64_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtnu))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -8783,7 +8783,7 @@ pub fn vcvtnh_u64_f16(a: f16) -> u64 {
 }
 #[doc = "Floating-point convert to signed integer, rounding to nearest with ties to even"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtns_s32_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtns))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -8799,7 +8799,7 @@ pub fn vcvtns_s32_f32(a: f32) -> i32 {
 }
 #[doc = "Floating-point convert to signed integer, rounding to nearest with ties to even"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnd_s64_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtns))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -8815,7 +8815,7 @@ pub fn vcvtnd_s64_f64(a: f64) -> i64 {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to even"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtns_u32_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtnu))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -8831,7 +8831,7 @@ pub fn vcvtns_u32_f32(a: f32) -> u32 {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to even"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnd_u64_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtnu))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -8847,7 +8847,7 @@ pub fn vcvtnd_u64_f64(a: f64) -> u64 {
 }
 #[doc = "Floating-point convert to signed integer, rounding to plus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtp_s16_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtps))]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
@@ -8864,7 +8864,7 @@ pub fn vcvtp_s16_f16(a: float16x4_t) -> int16x4_t {
 }
 #[doc = "Floating-point convert to signed integer, rounding to plus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtpq_s16_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtps))]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
@@ -8881,7 +8881,7 @@ pub fn vcvtpq_s16_f16(a: float16x8_t) -> int16x8_t {
 }
 #[doc = "Floating-point convert to signed integer, rounding toward plus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtp_s32_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtps))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -8897,7 +8897,7 @@ pub fn vcvtp_s32_f32(a: float32x2_t) -> int32x2_t {
 }
 #[doc = "Floating-point convert to signed integer, rounding toward plus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtpq_s32_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtps))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -8913,7 +8913,7 @@ pub fn vcvtpq_s32_f32(a: float32x4_t) -> int32x4_t {
 }
 #[doc = "Floating-point convert to signed integer, rounding toward plus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtp_s64_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtps))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -8929,7 +8929,7 @@ pub fn vcvtp_s64_f64(a: float64x1_t) -> int64x1_t {
 }
 #[doc = "Floating-point convert to signed integer, rounding toward plus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtpq_s64_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtps))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -8945,7 +8945,7 @@ pub fn vcvtpq_s64_f64(a: float64x2_t) -> int64x2_t {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding to plus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtp_u16_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtpu))]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
@@ -8962,7 +8962,7 @@ pub fn vcvtp_u16_f16(a: float16x4_t) -> uint16x4_t {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding to plus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtpq_u16_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtpu))]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
@@ -8979,7 +8979,7 @@ pub fn vcvtpq_u16_f16(a: float16x8_t) -> uint16x8_t {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding toward plus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtp_u32_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtpu))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -8995,7 +8995,7 @@ pub fn vcvtp_u32_f32(a: float32x2_t) -> uint32x2_t {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding toward plus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtpq_u32_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtpu))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -9011,7 +9011,7 @@ pub fn vcvtpq_u32_f32(a: float32x4_t) -> uint32x4_t {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding toward plus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtp_u64_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtpu))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -9027,7 +9027,7 @@ pub fn vcvtp_u64_f64(a: float64x1_t) -> uint64x1_t {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding toward plus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtpq_u64_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtpu))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -9043,7 +9043,7 @@ pub fn vcvtpq_u64_f64(a: float64x2_t) -> uint64x2_t {
 }
 #[doc = "Floating-point convert to integer, rounding to plus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtph_s16_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtps))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -9053,7 +9053,7 @@ pub fn vcvtph_s16_f16(a: f16) -> i16 {
 }
 #[doc = "Floating-point convert to integer, rounding to plus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtph_s32_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtps))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -9070,7 +9070,7 @@ pub fn vcvtph_s32_f16(a: f16) -> i32 {
 }
 #[doc = "Floating-point convert to integer, rounding to plus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtph_s64_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtps))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -9087,7 +9087,7 @@ pub fn vcvtph_s64_f16(a: f16) -> i64 {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding to plus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtph_u16_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtpu))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -9097,7 +9097,7 @@ pub fn vcvtph_u16_f16(a: f16) -> u16 {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding to plus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtph_u32_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtpu))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -9114,7 +9114,7 @@ pub fn vcvtph_u32_f16(a: f16) -> u32 {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding to plus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtph_u64_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fcvtpu))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -9131,7 +9131,7 @@ pub fn vcvtph_u64_f16(a: f16) -> u64 {
 }
 #[doc = "Floating-point convert to signed integer, rounding toward plus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtps_s32_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtps))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -9147,7 +9147,7 @@ pub fn vcvtps_s32_f32(a: f32) -> i32 {
 }
 #[doc = "Floating-point convert to signed integer, rounding toward plus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtpd_s64_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtps))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -9163,7 +9163,7 @@ pub fn vcvtpd_s64_f64(a: f64) -> i64 {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding toward plus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtps_u32_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtpu))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -9179,7 +9179,7 @@ pub fn vcvtps_u32_f32(a: f32) -> u32 {
 }
 #[doc = "Floating-point convert to unsigned integer, rounding toward plus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtpd_u64_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtpu))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -9195,7 +9195,7 @@ pub fn vcvtpd_u64_f64(a: f64) -> u64 {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvts_f32_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ucvtf))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -9204,7 +9204,7 @@ pub fn vcvts_f32_u32(a: u32) -> f32 {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtd_f64_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ucvtf))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -9213,7 +9213,7 @@ pub fn vcvtd_f64_u64(a: u64) -> f64 {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvts_n_f32_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(scvtf, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -9231,7 +9231,7 @@ pub fn vcvts_n_f32_s32<const N: i32>(a: i32) -> f32 {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtd_n_f64_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(scvtf, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -9249,7 +9249,7 @@ pub fn vcvtd_n_f64_s64<const N: i32>(a: i64) -> f64 {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvts_n_f32_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ucvtf, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -9267,7 +9267,7 @@ pub fn vcvts_n_f32_u32<const N: i32>(a: u32) -> f32 {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtd_n_f64_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ucvtf, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -9285,7 +9285,7 @@ pub fn vcvtd_n_f64_u64<const N: i32>(a: u64) -> f64 {
 }
 #[doc = "Floating-point convert to fixed-point, rounding toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvts_n_s32_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtzs, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -9303,7 +9303,7 @@ pub fn vcvts_n_s32_f32<const N: i32>(a: f32) -> i32 {
 }
 #[doc = "Floating-point convert to fixed-point, rounding toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtd_n_s64_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtzs, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -9321,7 +9321,7 @@ pub fn vcvtd_n_s64_f64<const N: i32>(a: f64) -> i64 {
 }
 #[doc = "Floating-point convert to fixed-point, rounding toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvts_n_u32_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtzu, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -9339,7 +9339,7 @@ pub fn vcvts_n_u32_f32<const N: i32>(a: f32) -> u32 {
 }
 #[doc = "Floating-point convert to fixed-point, rounding toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtd_n_u64_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtzu, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -9357,7 +9357,7 @@ pub fn vcvtd_n_u64_f64<const N: i32>(a: f64) -> u64 {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvts_s32_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtzs))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -9366,7 +9366,7 @@ pub fn vcvts_s32_f32(a: f32) -> i32 {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtd_s64_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtzs))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -9375,7 +9375,7 @@ pub fn vcvtd_s64_f64(a: f64) -> i64 {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvts_u32_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtzu))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -9384,7 +9384,7 @@ pub fn vcvts_u32_f32(a: f32) -> u32 {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtd_u64_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtzu))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -9393,7 +9393,7 @@ pub fn vcvtd_u64_f64(a: f64) -> u64 {
 }
 #[doc = "Floating-point convert to lower precision narrow, rounding to odd"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtx_f32_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtxn))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -9409,7 +9409,7 @@ pub fn vcvtx_f32_f64(a: float64x2_t) -> float32x2_t {
 }
 #[doc = "Floating-point convert to lower precision narrow, rounding to odd"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtx_high_f32_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtxn2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -9418,7 +9418,7 @@ pub fn vcvtx_high_f32_f64(a: float32x2_t, b: float64x2_t) -> float32x4_t {
 }
 #[doc = "Floating-point convert to lower precision narrow, rounding to odd"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtxd_f32_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fcvtxn))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -9427,7 +9427,7 @@ pub fn vcvtxd_f32_f64(a: f64) -> f32 {
 }
 #[doc = "Divide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdiv_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -9437,7 +9437,7 @@ pub fn vdiv_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 }
 #[doc = "Divide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdivq_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -9447,7 +9447,7 @@ pub fn vdivq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
 }
 #[doc = "Divide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdiv_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fdiv))]
@@ -9456,7 +9456,7 @@ pub fn vdiv_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
 }
 #[doc = "Divide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdivq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fdiv))]
@@ -9465,7 +9465,7 @@ pub fn vdivq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
 }
 #[doc = "Divide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdiv_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fdiv))]
@@ -9474,7 +9474,7 @@ pub fn vdiv_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t {
 }
 #[doc = "Divide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdivq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fdiv))]
@@ -9483,7 +9483,7 @@ pub fn vdivq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
 }
 #[doc = "Divide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdivh_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -9493,7 +9493,7 @@ pub fn vdivh_f16(a: f16, b: f16) -> f16 {
 }
 #[doc = "Dot product arithmetic (indexed)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_laneq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,dotprod")]
 #[cfg_attr(test, assert_instr(sdot, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -9508,7 +9508,7 @@ pub fn vdot_laneq_s32<const LANE: i32>(a: int32x2_t, b: int8x8_t, c: int8x16_t)
 }
 #[doc = "Dot product arithmetic (indexed)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_laneq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,dotprod")]
 #[cfg_attr(test, assert_instr(sdot, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -9524,7 +9524,7 @@ pub fn vdotq_laneq_s32<const LANE: i32>(a: int32x4_t, b: int8x16_t, c: int8x16_t
 }
 #[doc = "Dot product arithmetic (indexed)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_laneq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,dotprod")]
 #[cfg_attr(test, assert_instr(udot, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -9539,7 +9539,7 @@ pub fn vdot_laneq_u32<const LANE: i32>(a: uint32x2_t, b: uint8x8_t, c: uint8x16_
 }
 #[doc = "Dot product arithmetic (indexed)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_laneq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,dotprod")]
 #[cfg_attr(test, assert_instr(udot, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -9555,7 +9555,7 @@ pub fn vdotq_laneq_u32<const LANE: i32>(a: uint32x4_t, b: uint8x16_t, c: uint8x1
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(nop, N = 0))]
 #[rustc_legacy_const_generics(1)]
@@ -9566,7 +9566,7 @@ pub fn vdup_lane_f64<const N: i32>(a: float64x1_t) -> float64x1_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_p64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(nop, N = 0))]
 #[rustc_legacy_const_generics(1)]
@@ -9577,7 +9577,7 @@ pub fn vdup_lane_p64<const N: i32>(a: poly64x1_t) -> poly64x1_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(nop, N = 1))]
 #[rustc_legacy_const_generics(1)]
@@ -9588,7 +9588,7 @@ pub fn vdup_laneq_f64<const N: i32>(a: float64x2_t) -> float64x1_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_p64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(nop, N = 1))]
 #[rustc_legacy_const_generics(1)]
@@ -9599,7 +9599,7 @@ pub fn vdup_laneq_p64<const N: i32>(a: poly64x2_t) -> poly64x1_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupb_lane_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(nop, N = 4))]
 #[rustc_legacy_const_generics(1)]
@@ -9610,7 +9610,7 @@ pub fn vdupb_lane_s8<const N: i32>(a: int8x8_t) -> i8 {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vduph_laneq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(nop, N = 4))]
 #[rustc_legacy_const_generics(1)]
@@ -9621,7 +9621,7 @@ pub fn vduph_laneq_s16<const N: i32>(a: int16x8_t) -> i16 {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupb_lane_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(nop, N = 4))]
 #[rustc_legacy_const_generics(1)]
@@ -9632,7 +9632,7 @@ pub fn vdupb_lane_u8<const N: i32>(a: uint8x8_t) -> u8 {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vduph_laneq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(nop, N = 4))]
 #[rustc_legacy_const_generics(1)]
@@ -9643,7 +9643,7 @@ pub fn vduph_laneq_u16<const N: i32>(a: uint16x8_t) -> u16 {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupb_lane_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(nop, N = 4))]
 #[rustc_legacy_const_generics(1)]
@@ -9654,7 +9654,7 @@ pub fn vdupb_lane_p8<const N: i32>(a: poly8x8_t) -> p8 {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vduph_laneq_p16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(nop, N = 4))]
 #[rustc_legacy_const_generics(1)]
@@ -9665,7 +9665,7 @@ pub fn vduph_laneq_p16<const N: i32>(a: poly16x8_t) -> p16 {
 }
 #[doc = "Extract an element from a vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupb_laneq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(nop, N = 8))]
 #[rustc_legacy_const_generics(1)]
@@ -9676,7 +9676,7 @@ pub fn vdupb_laneq_s8<const N: i32>(a: int8x16_t) -> i8 {
 }
 #[doc = "Extract an element from a vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupb_laneq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(nop, N = 8))]
 #[rustc_legacy_const_generics(1)]
@@ -9687,7 +9687,7 @@ pub fn vdupb_laneq_u8<const N: i32>(a: uint8x16_t) -> u8 {
 }
 #[doc = "Extract an element from a vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupb_laneq_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(nop, N = 8))]
 #[rustc_legacy_const_generics(1)]
@@ -9698,7 +9698,7 @@ pub fn vdupb_laneq_p8<const N: i32>(a: poly8x16_t) -> p8 {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupd_lane_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(nop, N = 0))]
 #[rustc_legacy_const_generics(1)]
@@ -9709,7 +9709,7 @@ pub fn vdupd_lane_f64<const N: i32>(a: float64x1_t) -> f64 {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupd_lane_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(nop, N = 0))]
 #[rustc_legacy_const_generics(1)]
@@ -9720,7 +9720,7 @@ pub fn vdupd_lane_s64<const N: i32>(a: int64x1_t) -> i64 {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupd_lane_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(nop, N = 0))]
 #[rustc_legacy_const_generics(1)]
@@ -9731,7 +9731,7 @@ pub fn vdupd_lane_u64<const N: i32>(a: uint64x1_t) -> u64 {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vduph_lane_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(nop, N = 2))]
 #[rustc_legacy_const_generics(1)]
 #[target_feature(enable = "neon,fp16")]
@@ -9743,7 +9743,7 @@ pub fn vduph_lane_f16<const N: i32>(a: float16x4_t) -> f16 {
 }
 #[doc = "Extract an element from a vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vduph_laneq_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(nop, N = 4))]
 #[rustc_legacy_const_generics(1)]
 #[target_feature(enable = "neon,fp16")]
@@ -9755,7 +9755,7 @@ pub fn vduph_laneq_f16<const N: i32>(a: float16x8_t) -> f16 {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(dup, N = 0))]
 #[rustc_legacy_const_generics(1)]
@@ -9766,7 +9766,7 @@ pub fn vdupq_lane_f64<const N: i32>(a: float64x1_t) -> float64x2_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_p64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(dup, N = 0))]
 #[rustc_legacy_const_generics(1)]
@@ -9777,7 +9777,7 @@ pub fn vdupq_lane_p64<const N: i32>(a: poly64x1_t) -> poly64x2_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(dup, N = 1))]
 #[rustc_legacy_const_generics(1)]
@@ -9788,7 +9788,7 @@ pub fn vdupq_laneq_f64<const N: i32>(a: float64x2_t) -> float64x2_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_p64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(dup, N = 1))]
 #[rustc_legacy_const_generics(1)]
@@ -9799,7 +9799,7 @@ pub fn vdupq_laneq_p64<const N: i32>(a: poly64x2_t) -> poly64x2_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdups_lane_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(nop, N = 1))]
 #[rustc_legacy_const_generics(1)]
@@ -9810,7 +9810,7 @@ pub fn vdups_lane_f32<const N: i32>(a: float32x2_t) -> f32 {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupd_laneq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(nop, N = 1))]
 #[rustc_legacy_const_generics(1)]
@@ -9821,7 +9821,7 @@ pub fn vdupd_laneq_f64<const N: i32>(a: float64x2_t) -> f64 {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdups_lane_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(nop, N = 1))]
 #[rustc_legacy_const_generics(1)]
@@ -9832,7 +9832,7 @@ pub fn vdups_lane_s32<const N: i32>(a: int32x2_t) -> i32 {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupd_laneq_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(nop, N = 1))]
 #[rustc_legacy_const_generics(1)]
@@ -9843,7 +9843,7 @@ pub fn vdupd_laneq_s64<const N: i32>(a: int64x2_t) -> i64 {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdups_lane_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(nop, N = 1))]
 #[rustc_legacy_const_generics(1)]
@@ -9854,7 +9854,7 @@ pub fn vdups_lane_u32<const N: i32>(a: uint32x2_t) -> u32 {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupd_laneq_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(nop, N = 1))]
 #[rustc_legacy_const_generics(1)]
@@ -9865,7 +9865,7 @@ pub fn vdupd_laneq_u64<const N: i32>(a: uint64x2_t) -> u64 {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdups_laneq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(nop, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -9876,7 +9876,7 @@ pub fn vdups_laneq_f32<const N: i32>(a: float32x4_t) -> f32 {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vduph_lane_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(nop, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -9887,7 +9887,7 @@ pub fn vduph_lane_s16<const N: i32>(a: int16x4_t) -> i16 {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdups_laneq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(nop, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -9898,7 +9898,7 @@ pub fn vdups_laneq_s32<const N: i32>(a: int32x4_t) -> i32 {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vduph_lane_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(nop, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -9909,7 +9909,7 @@ pub fn vduph_lane_u16<const N: i32>(a: uint16x4_t) -> u16 {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdups_laneq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(nop, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -9920,7 +9920,7 @@ pub fn vdups_laneq_u32<const N: i32>(a: uint32x4_t) -> u32 {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vduph_lane_p16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(nop, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -9931,7 +9931,7 @@ pub fn vduph_lane_p16<const N: i32>(a: poly16x4_t) -> p16 {
 }
 #[doc = "Three-way exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor3q_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,sha3")]
 #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")]
 #[cfg_attr(test, assert_instr(eor3))]
@@ -9947,7 +9947,7 @@ pub fn veor3q_s8(a: int8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t {
 }
 #[doc = "Three-way exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor3q_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,sha3")]
 #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")]
 #[cfg_attr(test, assert_instr(eor3))]
@@ -9963,7 +9963,7 @@ pub fn veor3q_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t {
 }
 #[doc = "Three-way exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor3q_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,sha3")]
 #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")]
 #[cfg_attr(test, assert_instr(eor3))]
@@ -9979,7 +9979,7 @@ pub fn veor3q_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t {
 }
 #[doc = "Three-way exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor3q_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,sha3")]
 #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")]
 #[cfg_attr(test, assert_instr(eor3))]
@@ -9995,7 +9995,7 @@ pub fn veor3q_s64(a: int64x2_t, b: int64x2_t, c: int64x2_t) -> int64x2_t {
 }
 #[doc = "Three-way exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor3q_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,sha3")]
 #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")]
 #[cfg_attr(test, assert_instr(eor3))]
@@ -10011,7 +10011,7 @@ pub fn veor3q_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Three-way exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor3q_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,sha3")]
 #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")]
 #[cfg_attr(test, assert_instr(eor3))]
@@ -10027,7 +10027,7 @@ pub fn veor3q_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Three-way exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor3q_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,sha3")]
 #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")]
 #[cfg_attr(test, assert_instr(eor3))]
@@ -10043,7 +10043,7 @@ pub fn veor3q_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Three-way exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor3q_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,sha3")]
 #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")]
 #[cfg_attr(test, assert_instr(eor3))]
@@ -10059,7 +10059,7 @@ pub fn veor3q_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Extract vector from pair of vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ext, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -10076,7 +10076,7 @@ pub fn vextq_f64<const N: i32>(a: float64x2_t, b: float64x2_t) -> float64x2_t {
 }
 #[doc = "Extract vector from pair of vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_p64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ext, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -10093,7 +10093,7 @@ pub fn vextq_p64<const N: i32>(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t {
 }
 #[doc = "Floating-point fused Multiply-Add to accumulator(vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fmadd))]
@@ -10102,7 +10102,7 @@ pub fn vfma_f64(a: float64x1_t, b: float64x1_t, c: float64x1_t) -> float64x1_t {
 }
 #[doc = "Floating-point fused multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_lane_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
 #[target_feature(enable = "neon,fp16")]
@@ -10118,7 +10118,7 @@ pub fn vfma_lane_f16<const LANE: i32>(
 }
 #[doc = "Floating-point fused multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_laneq_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
 #[target_feature(enable = "neon,fp16")]
@@ -10134,7 +10134,7 @@ pub fn vfma_laneq_f16<const LANE: i32>(
 }
 #[doc = "Floating-point fused multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_lane_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
 #[target_feature(enable = "neon,fp16")]
@@ -10150,7 +10150,7 @@ pub fn vfmaq_lane_f16<const LANE: i32>(
 }
 #[doc = "Floating-point fused multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_laneq_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
 #[target_feature(enable = "neon,fp16")]
@@ -10166,7 +10166,7 @@ pub fn vfmaq_laneq_f16<const LANE: i32>(
 }
 #[doc = "Floating-point fused multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_lane_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -10181,7 +10181,7 @@ pub fn vfma_lane_f32<const LANE: i32>(
 }
 #[doc = "Floating-point fused multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_laneq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -10196,7 +10196,7 @@ pub fn vfma_laneq_f32<const LANE: i32>(
 }
 #[doc = "Floating-point fused multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_lane_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -10211,7 +10211,7 @@ pub fn vfmaq_lane_f32<const LANE: i32>(
 }
 #[doc = "Floating-point fused multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_laneq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -10226,7 +10226,7 @@ pub fn vfmaq_laneq_f32<const LANE: i32>(
 }
 #[doc = "Floating-point fused multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_laneq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -10241,7 +10241,7 @@ pub fn vfmaq_laneq_f64<const LANE: i32>(
 }
 #[doc = "Floating-point fused multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_lane_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmadd, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -10256,7 +10256,7 @@ pub fn vfma_lane_f64<const LANE: i32>(
 }
 #[doc = "Floating-point fused multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_laneq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmadd, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -10271,7 +10271,7 @@ pub fn vfma_laneq_f64<const LANE: i32>(
 }
 #[doc = "Floating-point fused Multiply-Subtract from accumulator."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_n_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -10281,7 +10281,7 @@ pub fn vfma_n_f16(a: float16x4_t, b: float16x4_t, c: f16) -> float16x4_t {
 }
 #[doc = "Floating-point fused Multiply-Subtract from accumulator."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_n_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -10291,7 +10291,7 @@ pub fn vfmaq_n_f16(a: float16x8_t, b: float16x8_t, c: f16) -> float16x8_t {
 }
 #[doc = "Floating-point fused Multiply-Add to accumulator(vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_n_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fmadd))]
@@ -10300,7 +10300,7 @@ pub fn vfma_n_f64(a: float64x1_t, b: float64x1_t, c: f64) -> float64x1_t {
 }
 #[doc = "Floating-point fused multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmad_lane_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmadd, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -10314,7 +10314,7 @@ pub fn vfmad_lane_f64<const LANE: i32>(a: f64, b: f64, c: float64x1_t) -> f64 {
 }
 #[doc = "Floating-point fused multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmah_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fmadd))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -10324,7 +10324,7 @@ pub fn vfmah_f16(a: f16, b: f16, c: f16) -> f16 {
 }
 #[doc = "Floating-point fused multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmah_lane_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fmadd, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
 #[target_feature(enable = "neon,fp16")]
@@ -10339,7 +10339,7 @@ pub fn vfmah_lane_f16<const LANE: i32>(a: f16, b: f16, v: float16x4_t) -> f16 {
 }
 #[doc = "Floating-point fused multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmah_laneq_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fmadd, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
 #[target_feature(enable = "neon,fp16")]
@@ -10354,7 +10354,7 @@ pub fn vfmah_laneq_f16<const LANE: i32>(a: f16, b: f16, v: float16x8_t) -> f16 {
 }
 #[doc = "Floating-point fused Multiply-Add to accumulator(vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fmla))]
@@ -10363,7 +10363,7 @@ pub fn vfmaq_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t
 }
 #[doc = "Floating-point fused multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_lane_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmla, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -10378,7 +10378,7 @@ pub fn vfmaq_lane_f64<const LANE: i32>(
 }
 #[doc = "Floating-point fused Multiply-Add to accumulator(vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_n_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fmla))]
@@ -10387,7 +10387,7 @@ pub fn vfmaq_n_f64(a: float64x2_t, b: float64x2_t, c: f64) -> float64x2_t {
 }
 #[doc = "Floating-point fused multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmas_lane_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmadd, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -10401,7 +10401,7 @@ pub fn vfmas_lane_f32<const LANE: i32>(a: f32, b: f32, c: float32x2_t) -> f32 {
 }
 #[doc = "Floating-point fused multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmas_laneq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmadd, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -10415,7 +10415,7 @@ pub fn vfmas_laneq_f32<const LANE: i32>(a: f32, b: f32, c: float32x4_t) -> f32 {
 }
 #[doc = "Floating-point fused multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmad_laneq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmadd, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -10429,7 +10429,7 @@ pub fn vfmad_laneq_f64<const LANE: i32>(a: f64, b: f64, c: float64x2_t) -> f64 {
 }
 #[doc = "Floating-point fused Multiply-Add Long to accumulator (vector)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlal_high_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
@@ -10447,7 +10447,7 @@ pub fn vfmlal_high_f16(r: float32x2_t, a: float16x4_t, b: float16x4_t) -> float3
 }
 #[doc = "Floating-point fused Multiply-Add Long to accumulator (vector)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlalq_high_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
@@ -10465,7 +10465,7 @@ pub fn vfmlalq_high_f16(r: float32x4_t, a: float16x8_t, b: float16x8_t) -> float
 }
 #[doc = "Floating-point fused Multiply-Add Long to accumulator (by element)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlal_lane_high_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fmlal2, LANE = 0))]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
@@ -10482,7 +10482,7 @@ pub fn vfmlal_lane_high_f16<const LANE: i32>(
 }
 #[doc = "Floating-point fused Multiply-Add Long to accumulator (by element)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlal_laneq_high_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fmlal2, LANE = 0))]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
@@ -10499,7 +10499,7 @@ pub fn vfmlal_laneq_high_f16<const LANE: i32>(
 }
 #[doc = "Floating-point fused Multiply-Add Long to accumulator (by element)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlalq_lane_high_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fmlal2, LANE = 0))]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
@@ -10516,7 +10516,7 @@ pub fn vfmlalq_lane_high_f16<const LANE: i32>(
 }
 #[doc = "Floating-point fused Multiply-Add Long to accumulator (by element)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlalq_laneq_high_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fmlal2, LANE = 0))]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
@@ -10533,7 +10533,7 @@ pub fn vfmlalq_laneq_high_f16<const LANE: i32>(
 }
 #[doc = "Floating-point fused Multiply-Add Long to accumulator (by element)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlal_lane_low_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fmlal, LANE = 0))]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
@@ -10550,7 +10550,7 @@ pub fn vfmlal_lane_low_f16<const LANE: i32>(
 }
 #[doc = "Floating-point fused Multiply-Add Long to accumulator (by element)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlal_laneq_low_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fmlal, LANE = 0))]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
@@ -10567,7 +10567,7 @@ pub fn vfmlal_laneq_low_f16<const LANE: i32>(
 }
 #[doc = "Floating-point fused Multiply-Add Long to accumulator (by element)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlalq_lane_low_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fmlal, LANE = 0))]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
@@ -10584,7 +10584,7 @@ pub fn vfmlalq_lane_low_f16<const LANE: i32>(
 }
 #[doc = "Floating-point fused Multiply-Add Long to accumulator (by element)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlalq_laneq_low_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fmlal, LANE = 0))]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
@@ -10601,7 +10601,7 @@ pub fn vfmlalq_laneq_low_f16<const LANE: i32>(
 }
 #[doc = "Floating-point fused Multiply-Add Long to accumulator (vector)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlal_low_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
@@ -10619,7 +10619,7 @@ pub fn vfmlal_low_f16(r: float32x2_t, a: float16x4_t, b: float16x4_t) -> float32
 }
 #[doc = "Floating-point fused Multiply-Add Long to accumulator (vector)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlalq_low_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
@@ -10637,7 +10637,7 @@ pub fn vfmlalq_low_f16(r: float32x4_t, a: float16x8_t, b: float16x8_t) -> float3
 }
 #[doc = "Floating-point fused Multiply-Subtract Long from accumulator (vector)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlsl_high_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
@@ -10655,7 +10655,7 @@ pub fn vfmlsl_high_f16(r: float32x2_t, a: float16x4_t, b: float16x4_t) -> float3
 }
 #[doc = "Floating-point fused Multiply-Subtract Long from accumulator (vector)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlslq_high_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
@@ -10673,7 +10673,7 @@ pub fn vfmlslq_high_f16(r: float32x4_t, a: float16x8_t, b: float16x8_t) -> float
 }
 #[doc = "Floating-point fused Multiply-Subtract Long from accumulator (by element)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlsl_lane_high_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fmlsl2, LANE = 0))]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
@@ -10690,7 +10690,7 @@ pub fn vfmlsl_lane_high_f16<const LANE: i32>(
 }
 #[doc = "Floating-point fused Multiply-Subtract Long from accumulator (by element)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlsl_laneq_high_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fmlsl2, LANE = 0))]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
@@ -10707,7 +10707,7 @@ pub fn vfmlsl_laneq_high_f16<const LANE: i32>(
 }
 #[doc = "Floating-point fused Multiply-Subtract Long from accumulator (by element)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlslq_lane_high_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fmlsl2, LANE = 0))]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
@@ -10724,7 +10724,7 @@ pub fn vfmlslq_lane_high_f16<const LANE: i32>(
 }
 #[doc = "Floating-point fused Multiply-Subtract Long from accumulator (by element)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlslq_laneq_high_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fmlsl2, LANE = 0))]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
@@ -10741,7 +10741,7 @@ pub fn vfmlslq_laneq_high_f16<const LANE: i32>(
 }
 #[doc = "Floating-point fused Multiply-Subtract Long from accumulator (by element)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlsl_lane_low_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fmlsl, LANE = 0))]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
@@ -10758,7 +10758,7 @@ pub fn vfmlsl_lane_low_f16<const LANE: i32>(
 }
 #[doc = "Floating-point fused Multiply-Subtract Long from accumulator (by element)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlsl_laneq_low_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fmlsl, LANE = 0))]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
@@ -10775,7 +10775,7 @@ pub fn vfmlsl_laneq_low_f16<const LANE: i32>(
 }
 #[doc = "Floating-point fused Multiply-Subtract Long from accumulator (by element)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlslq_lane_low_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fmlsl, LANE = 0))]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
@@ -10792,7 +10792,7 @@ pub fn vfmlslq_lane_low_f16<const LANE: i32>(
 }
 #[doc = "Floating-point fused Multiply-Subtract Long from accumulator (by element)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlslq_laneq_low_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fmlsl, LANE = 0))]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
@@ -10809,7 +10809,7 @@ pub fn vfmlslq_laneq_low_f16<const LANE: i32>(
 }
 #[doc = "Floating-point fused Multiply-Subtract Long from accumulator (vector)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlsl_low_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
@@ -10827,7 +10827,7 @@ pub fn vfmlsl_low_f16(r: float32x2_t, a: float16x4_t, b: float16x4_t) -> float32
 }
 #[doc = "Floating-point fused Multiply-Subtract Long from accumulator (vector)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmlslq_low_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(not(target_arch = "arm"), target_feature(enable = "fhm"))]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
@@ -10845,7 +10845,7 @@ pub fn vfmlslq_low_f16(r: float32x4_t, a: float16x8_t, b: float16x8_t) -> float3
 }
 #[doc = "Floating-point fused multiply-subtract from accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmsub))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -10857,7 +10857,7 @@ pub fn vfms_f64(a: float64x1_t, b: float64x1_t, c: float64x1_t) -> float64x1_t {
 }
 #[doc = "Floating-point fused multiply-subtract from accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_lane_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fmls, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
 #[target_feature(enable = "neon,fp16")]
@@ -10873,7 +10873,7 @@ pub fn vfms_lane_f16<const LANE: i32>(
 }
 #[doc = "Floating-point fused multiply-subtract from accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_laneq_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fmls, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
 #[target_feature(enable = "neon,fp16")]
@@ -10889,7 +10889,7 @@ pub fn vfms_laneq_f16<const LANE: i32>(
 }
 #[doc = "Floating-point fused multiply-subtract from accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_lane_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fmls, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
 #[target_feature(enable = "neon,fp16")]
@@ -10905,7 +10905,7 @@ pub fn vfmsq_lane_f16<const LANE: i32>(
 }
 #[doc = "Floating-point fused multiply-subtract from accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_laneq_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fmls, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
 #[target_feature(enable = "neon,fp16")]
@@ -10921,7 +10921,7 @@ pub fn vfmsq_laneq_f16<const LANE: i32>(
 }
 #[doc = "Floating-point fused multiply-subtract to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_lane_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmls, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -10936,7 +10936,7 @@ pub fn vfms_lane_f32<const LANE: i32>(
 }
 #[doc = "Floating-point fused multiply-subtract to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_laneq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmls, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -10951,7 +10951,7 @@ pub fn vfms_laneq_f32<const LANE: i32>(
 }
 #[doc = "Floating-point fused multiply-subtract to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_lane_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmls, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -10966,7 +10966,7 @@ pub fn vfmsq_lane_f32<const LANE: i32>(
 }
 #[doc = "Floating-point fused multiply-subtract to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_laneq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmls, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -10981,7 +10981,7 @@ pub fn vfmsq_laneq_f32<const LANE: i32>(
 }
 #[doc = "Floating-point fused multiply-subtract to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_laneq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmls, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -10996,7 +10996,7 @@ pub fn vfmsq_laneq_f64<const LANE: i32>(
 }
 #[doc = "Floating-point fused multiply-subtract to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_lane_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmsub, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -11011,7 +11011,7 @@ pub fn vfms_lane_f64<const LANE: i32>(
 }
 #[doc = "Floating-point fused multiply-subtract to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_laneq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmsub, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -11026,7 +11026,7 @@ pub fn vfms_laneq_f64<const LANE: i32>(
 }
 #[doc = "Floating-point fused Multiply-Subtract from accumulator."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_n_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -11036,7 +11036,7 @@ pub fn vfms_n_f16(a: float16x4_t, b: float16x4_t, c: f16) -> float16x4_t {
 }
 #[doc = "Floating-point fused Multiply-Subtract from accumulator."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_n_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -11046,7 +11046,7 @@ pub fn vfmsq_n_f16(a: float16x8_t, b: float16x8_t, c: f16) -> float16x8_t {
 }
 #[doc = "Floating-point fused Multiply-subtract to accumulator(vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_n_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmsub))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11055,7 +11055,7 @@ pub fn vfms_n_f64(a: float64x1_t, b: float64x1_t, c: f64) -> float64x1_t {
 }
 #[doc = "Floating-point fused multiply-subtract from accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsh_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fmsub))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -11065,7 +11065,7 @@ pub fn vfmsh_f16(a: f16, b: f16, c: f16) -> f16 {
 }
 #[doc = "Floating-point fused multiply-subtract from accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsh_lane_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fmsub, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
 #[target_feature(enable = "neon,fp16")]
@@ -11080,7 +11080,7 @@ pub fn vfmsh_lane_f16<const LANE: i32>(a: f16, b: f16, v: float16x4_t) -> f16 {
 }
 #[doc = "Floating-point fused multiply-subtract from accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsh_laneq_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fmsub, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
 #[target_feature(enable = "neon,fp16")]
@@ -11095,7 +11095,7 @@ pub fn vfmsh_laneq_f16<const LANE: i32>(a: f16, b: f16, v: float16x8_t) -> f16 {
 }
 #[doc = "Floating-point fused multiply-subtract from accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmls))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11107,7 +11107,7 @@ pub fn vfmsq_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t
 }
 #[doc = "Floating-point fused multiply-subtract to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_lane_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmls, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -11122,7 +11122,7 @@ pub fn vfmsq_lane_f64<const LANE: i32>(
 }
 #[doc = "Floating-point fused Multiply-subtract to accumulator(vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_n_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmls))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11131,7 +11131,7 @@ pub fn vfmsq_n_f64(a: float64x2_t, b: float64x2_t, c: f64) -> float64x2_t {
 }
 #[doc = "Floating-point fused multiply-subtract to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmss_lane_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmsub, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -11141,7 +11141,7 @@ pub fn vfmss_lane_f32<const LANE: i32>(a: f32, b: f32, c: float32x2_t) -> f32 {
 }
 #[doc = "Floating-point fused multiply-subtract to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmss_laneq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmsub, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -11151,7 +11151,7 @@ pub fn vfmss_laneq_f32<const LANE: i32>(a: f32, b: f32, c: float32x4_t) -> f32 {
 }
 #[doc = "Floating-point fused multiply-subtract to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsd_lane_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmsub, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -11161,7 +11161,7 @@ pub fn vfmsd_lane_f64<const LANE: i32>(a: f64, b: f64, c: float64x1_t) -> f64 {
 }
 #[doc = "Floating-point fused multiply-subtract to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsd_laneq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmsub, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -11173,7 +11173,7 @@ pub fn vfmsd_laneq_f64<const LANE: i32>(a: f64, b: f64, c: float64x2_t) -> f64 {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(test, assert_instr(ldr))]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -11185,7 +11185,7 @@ pub unsafe fn vld1_f16(ptr: *const f16) -> float16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(test, assert_instr(ldr))]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -11197,7 +11197,7 @@ pub unsafe fn vld1q_f16(ptr: *const f16) -> float16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11208,7 +11208,7 @@ pub unsafe fn vld1_f32(ptr: *const f32) -> float32x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11219,7 +11219,7 @@ pub unsafe fn vld1q_f32(ptr: *const f32) -> float32x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11230,7 +11230,7 @@ pub unsafe fn vld1_f64(ptr: *const f64) -> float64x1_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11241,7 +11241,7 @@ pub unsafe fn vld1q_f64(ptr: *const f64) -> float64x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11252,7 +11252,7 @@ pub unsafe fn vld1_s8(ptr: *const i8) -> int8x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11263,7 +11263,7 @@ pub unsafe fn vld1q_s8(ptr: *const i8) -> int8x16_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11274,7 +11274,7 @@ pub unsafe fn vld1_s16(ptr: *const i16) -> int16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11285,7 +11285,7 @@ pub unsafe fn vld1q_s16(ptr: *const i16) -> int16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11296,7 +11296,7 @@ pub unsafe fn vld1_s32(ptr: *const i32) -> int32x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11307,7 +11307,7 @@ pub unsafe fn vld1q_s32(ptr: *const i32) -> int32x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11318,7 +11318,7 @@ pub unsafe fn vld1_s64(ptr: *const i64) -> int64x1_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11329,7 +11329,7 @@ pub unsafe fn vld1q_s64(ptr: *const i64) -> int64x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11340,7 +11340,7 @@ pub unsafe fn vld1_u8(ptr: *const u8) -> uint8x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11351,7 +11351,7 @@ pub unsafe fn vld1q_u8(ptr: *const u8) -> uint8x16_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11362,7 +11362,7 @@ pub unsafe fn vld1_u16(ptr: *const u16) -> uint16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11373,7 +11373,7 @@ pub unsafe fn vld1q_u16(ptr: *const u16) -> uint16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11384,7 +11384,7 @@ pub unsafe fn vld1_u32(ptr: *const u32) -> uint32x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11395,7 +11395,7 @@ pub unsafe fn vld1q_u32(ptr: *const u32) -> uint32x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11406,7 +11406,7 @@ pub unsafe fn vld1_u64(ptr: *const u64) -> uint64x1_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11417,7 +11417,7 @@ pub unsafe fn vld1q_u64(ptr: *const u64) -> uint64x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11428,7 +11428,7 @@ pub unsafe fn vld1_p8(ptr: *const p8) -> poly8x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11439,7 +11439,7 @@ pub unsafe fn vld1q_p8(ptr: *const p8) -> poly8x16_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11450,7 +11450,7 @@ pub unsafe fn vld1_p16(ptr: *const p16) -> poly16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11461,7 +11461,7 @@ pub unsafe fn vld1q_p16(ptr: *const p16) -> poly16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(test, assert_instr(ldr))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11472,7 +11472,7 @@ pub unsafe fn vld1_p64(ptr: *const p64) -> poly64x1_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(test, assert_instr(ldr))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11483,7 +11483,7 @@ pub unsafe fn vld1q_p64(ptr: *const p64) -> poly64x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f64_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(ld1))]
@@ -11501,7 +11501,7 @@ pub unsafe fn vld1_f64_x2(a: *const f64) -> float64x1x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f64_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(ld1))]
@@ -11519,7 +11519,7 @@ pub unsafe fn vld1_f64_x3(a: *const f64) -> float64x1x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f64_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(ld1))]
@@ -11537,7 +11537,7 @@ pub unsafe fn vld1_f64_x4(a: *const f64) -> float64x1x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f64_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(ld1))]
@@ -11555,7 +11555,7 @@ pub unsafe fn vld1q_f64_x2(a: *const f64) -> float64x2x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f64_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(ld1))]
@@ -11573,7 +11573,7 @@ pub unsafe fn vld1q_f64_x3(a: *const f64) -> float64x2x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f64_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(ld1))]
@@ -11591,7 +11591,7 @@ pub unsafe fn vld1q_f64_x4(a: *const f64) -> float64x2x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(ld2r))]
@@ -11609,7 +11609,7 @@ pub unsafe fn vld2_dup_f64(a: *const f64) -> float64x1x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(ld2r))]
@@ -11627,7 +11627,7 @@ pub unsafe fn vld2q_dup_f64(a: *const f64) -> float64x2x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(ld2r))]
@@ -11645,7 +11645,7 @@ pub unsafe fn vld2q_dup_s64(a: *const i64) -> int64x2x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(nop))]
@@ -11663,7 +11663,7 @@ pub unsafe fn vld2_f64(a: *const f64) -> float64x1x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld2, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -11683,7 +11683,7 @@ pub unsafe fn vld2_lane_f64<const LANE: i32>(a: *const f64, b: float64x1x2_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld2, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -11703,7 +11703,7 @@ pub unsafe fn vld2_lane_s64<const LANE: i32>(a: *const i64, b: int64x1x2_t) -> i
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(test, assert_instr(ld2, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -11716,7 +11716,7 @@ pub unsafe fn vld2_lane_p64<const LANE: i32>(a: *const p64, b: poly64x1x2_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld2, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -11729,7 +11729,7 @@ pub unsafe fn vld2_lane_u64<const LANE: i32>(a: *const u64, b: uint64x1x2_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11741,7 +11741,7 @@ pub unsafe fn vld2q_dup_p64(a: *const p64) -> poly64x2x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11756,7 +11756,7 @@ pub unsafe fn vld2q_dup_p64(a: *const p64) -> poly64x2x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11768,7 +11768,7 @@ pub unsafe fn vld2q_dup_u64(a: *const u64) -> uint64x2x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11783,7 +11783,7 @@ pub unsafe fn vld2q_dup_u64(a: *const u64) -> uint64x2x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(ld2))]
@@ -11801,7 +11801,7 @@ pub unsafe fn vld2q_f64(a: *const f64) -> float64x2x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(ld2))]
@@ -11819,7 +11819,7 @@ pub unsafe fn vld2q_s64(a: *const i64) -> int64x2x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld2, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -11840,7 +11840,7 @@ pub unsafe fn vld2q_lane_f64<const LANE: i32>(a: *const f64, b: float64x2x2_t) -
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld2, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -11860,7 +11860,7 @@ pub unsafe fn vld2q_lane_s8<const LANE: i32>(a: *const i8, b: int8x16x2_t) -> in
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld2, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -11880,7 +11880,7 @@ pub unsafe fn vld2q_lane_s64<const LANE: i32>(a: *const i64, b: int64x2x2_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(test, assert_instr(ld2, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -11893,7 +11893,7 @@ pub unsafe fn vld2q_lane_p64<const LANE: i32>(a: *const p64, b: poly64x2x2_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld2, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -11906,7 +11906,7 @@ pub unsafe fn vld2q_lane_u8<const LANE: i32>(a: *const u8, b: uint8x16x2_t) -> u
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld2, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -11919,7 +11919,7 @@ pub unsafe fn vld2q_lane_u64<const LANE: i32>(a: *const u64, b: uint64x2x2_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld2, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -11932,7 +11932,7 @@ pub unsafe fn vld2q_lane_p8<const LANE: i32>(a: *const p8, b: poly8x16x2_t) -> p
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11944,7 +11944,7 @@ pub unsafe fn vld2q_p64(a: *const p64) -> poly64x2x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11959,7 +11959,7 @@ pub unsafe fn vld2q_p64(a: *const p64) -> poly64x2x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11971,7 +11971,7 @@ pub unsafe fn vld2q_u64(a: *const u64) -> uint64x2x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11986,7 +11986,7 @@ pub unsafe fn vld2q_u64(a: *const u64) -> uint64x2x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(ld3r))]
@@ -12004,7 +12004,7 @@ pub unsafe fn vld3_dup_f64(a: *const f64) -> float64x1x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(ld3r))]
@@ -12022,7 +12022,7 @@ pub unsafe fn vld3q_dup_f64(a: *const f64) -> float64x2x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(ld3r))]
@@ -12040,7 +12040,7 @@ pub unsafe fn vld3q_dup_s64(a: *const i64) -> int64x2x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(nop))]
@@ -12058,7 +12058,7 @@ pub unsafe fn vld3_f64(a: *const f64) -> float64x1x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld3, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -12084,7 +12084,7 @@ pub unsafe fn vld3_lane_f64<const LANE: i32>(a: *const f64, b: float64x1x3_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(test, assert_instr(ld3, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -12097,7 +12097,7 @@ pub unsafe fn vld3_lane_p64<const LANE: i32>(a: *const p64, b: poly64x1x3_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld3, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -12123,7 +12123,7 @@ pub unsafe fn vld3_lane_s64<const LANE: i32>(a: *const i64, b: int64x1x3_t) -> i
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld3, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -12136,7 +12136,7 @@ pub unsafe fn vld3_lane_u64<const LANE: i32>(a: *const u64, b: uint64x1x3_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -12148,7 +12148,7 @@ pub unsafe fn vld3q_dup_p64(a: *const p64) -> poly64x2x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -12164,7 +12164,7 @@ pub unsafe fn vld3q_dup_p64(a: *const p64) -> poly64x2x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -12176,7 +12176,7 @@ pub unsafe fn vld3q_dup_u64(a: *const u64) -> uint64x2x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -12192,7 +12192,7 @@ pub unsafe fn vld3q_dup_u64(a: *const u64) -> uint64x2x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(ld3))]
@@ -12210,7 +12210,7 @@ pub unsafe fn vld3q_f64(a: *const f64) -> float64x2x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(ld3))]
@@ -12228,7 +12228,7 @@ pub unsafe fn vld3q_s64(a: *const i64) -> int64x2x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld3, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -12254,7 +12254,7 @@ pub unsafe fn vld3q_lane_f64<const LANE: i32>(a: *const f64, b: float64x2x3_t) -
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(test, assert_instr(ld3, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -12267,7 +12267,7 @@ pub unsafe fn vld3q_lane_p64<const LANE: i32>(a: *const p64, b: poly64x2x3_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld3, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -12293,7 +12293,7 @@ pub unsafe fn vld3q_lane_s8<const LANE: i32>(a: *const i8, b: int8x16x3_t) -> in
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld3, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -12319,7 +12319,7 @@ pub unsafe fn vld3q_lane_s64<const LANE: i32>(a: *const i64, b: int64x2x3_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld3, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -12332,7 +12332,7 @@ pub unsafe fn vld3q_lane_u8<const LANE: i32>(a: *const u8, b: uint8x16x3_t) -> u
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld3, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -12345,7 +12345,7 @@ pub unsafe fn vld3q_lane_u64<const LANE: i32>(a: *const u64, b: uint64x2x3_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld3, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -12358,7 +12358,7 @@ pub unsafe fn vld3q_lane_p8<const LANE: i32>(a: *const p8, b: poly8x16x3_t) -> p
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -12370,7 +12370,7 @@ pub unsafe fn vld3q_p64(a: *const p64) -> poly64x2x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -12386,7 +12386,7 @@ pub unsafe fn vld3q_p64(a: *const p64) -> poly64x2x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -12398,7 +12398,7 @@ pub unsafe fn vld3q_u64(a: *const u64) -> uint64x2x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -12414,7 +12414,7 @@ pub unsafe fn vld3q_u64(a: *const u64) -> uint64x2x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld4r))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -12432,7 +12432,7 @@ pub unsafe fn vld4_dup_f64(a: *const f64) -> float64x1x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld4r))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -12450,7 +12450,7 @@ pub unsafe fn vld4q_dup_f64(a: *const f64) -> float64x2x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld4r))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -12468,7 +12468,7 @@ pub unsafe fn vld4q_dup_s64(a: *const i64) -> int64x2x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(nop))]
@@ -12486,7 +12486,7 @@ pub unsafe fn vld4_f64(a: *const f64) -> float64x1x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld4, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -12513,7 +12513,7 @@ pub unsafe fn vld4_lane_f64<const LANE: i32>(a: *const f64, b: float64x1x4_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld4, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -12540,7 +12540,7 @@ pub unsafe fn vld4_lane_s64<const LANE: i32>(a: *const i64, b: int64x1x4_t) -> i
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(test, assert_instr(ld4, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -12553,7 +12553,7 @@ pub unsafe fn vld4_lane_p64<const LANE: i32>(a: *const p64, b: poly64x1x4_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld4, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -12566,7 +12566,7 @@ pub unsafe fn vld4_lane_u64<const LANE: i32>(a: *const u64, b: uint64x1x4_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(test, assert_instr(ld4r))]
@@ -12578,7 +12578,7 @@ pub unsafe fn vld4q_dup_p64(a: *const p64) -> poly64x2x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(test, assert_instr(ld4r))]
@@ -12595,7 +12595,7 @@ pub unsafe fn vld4q_dup_p64(a: *const p64) -> poly64x2x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld4r))]
@@ -12607,7 +12607,7 @@ pub unsafe fn vld4q_dup_u64(a: *const u64) -> uint64x2x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld4r))]
@@ -12624,7 +12624,7 @@ pub unsafe fn vld4q_dup_u64(a: *const u64) -> uint64x2x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(ld4))]
@@ -12642,7 +12642,7 @@ pub unsafe fn vld4q_f64(a: *const f64) -> float64x2x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(ld4))]
@@ -12660,7 +12660,7 @@ pub unsafe fn vld4q_s64(a: *const i64) -> int64x2x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld4, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -12687,7 +12687,7 @@ pub unsafe fn vld4q_lane_f64<const LANE: i32>(a: *const f64, b: float64x2x4_t) -
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld4, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -12714,7 +12714,7 @@ pub unsafe fn vld4q_lane_s8<const LANE: i32>(a: *const i8, b: int8x16x4_t) -> in
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld4, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -12741,7 +12741,7 @@ pub unsafe fn vld4q_lane_s64<const LANE: i32>(a: *const i64, b: int64x2x4_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(test, assert_instr(ld4, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -12754,7 +12754,7 @@ pub unsafe fn vld4q_lane_p64<const LANE: i32>(a: *const p64, b: poly64x2x4_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld4, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -12767,7 +12767,7 @@ pub unsafe fn vld4q_lane_u8<const LANE: i32>(a: *const u8, b: uint8x16x4_t) -> u
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld4, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -12780,7 +12780,7 @@ pub unsafe fn vld4q_lane_u64<const LANE: i32>(a: *const u64, b: uint64x2x4_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld4, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -12793,7 +12793,7 @@ pub unsafe fn vld4q_lane_p8<const LANE: i32>(a: *const p8, b: poly8x16x4_t) -> p
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[target_feature(enable = "neon,aes")]
@@ -12805,7 +12805,7 @@ pub unsafe fn vld4q_p64(a: *const p64) -> poly64x2x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[target_feature(enable = "neon,aes")]
@@ -12822,7 +12822,7 @@ pub unsafe fn vld4q_p64(a: *const p64) -> poly64x2x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -12834,7 +12834,7 @@ pub unsafe fn vld4q_u64(a: *const u64) -> uint64x2x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -12851,7 +12851,7 @@ pub unsafe fn vld4q_u64(a: *const u64) -> uint64x2x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, LANE = 1))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -12871,7 +12871,7 @@ pub unsafe fn vluti2_lane_s8<const LANE: i32>(a: int8x8_t, b: uint8x8_t) -> int8
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, LANE = 1))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -12891,7 +12891,7 @@ pub unsafe fn vluti2q_lane_s8<const LANE: i32>(a: int8x16_t, b: uint8x8_t) -> in
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, LANE = 1))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -12911,7 +12911,7 @@ pub unsafe fn vluti2_lane_s16<const LANE: i32>(a: int16x4_t, b: uint8x8_t) -> in
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, LANE = 1))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -12931,7 +12931,7 @@ pub unsafe fn vluti2q_lane_s16<const LANE: i32>(a: int16x8_t, b: uint8x8_t) -> i
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, LANE = 1))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -12944,7 +12944,7 @@ pub unsafe fn vluti2_lane_u8<const LANE: i32>(a: uint8x8_t, b: uint8x8_t) -> uin
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, LANE = 1))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -12957,7 +12957,7 @@ pub unsafe fn vluti2q_lane_u8<const LANE: i32>(a: uint8x16_t, b: uint8x8_t) -> u
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, LANE = 1))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -12970,7 +12970,7 @@ pub unsafe fn vluti2_lane_u16<const LANE: i32>(a: uint16x4_t, b: uint8x8_t) -> u
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, LANE = 1))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -12983,7 +12983,7 @@ pub unsafe fn vluti2q_lane_u16<const LANE: i32>(a: uint16x8_t, b: uint8x8_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, LANE = 1))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -12996,7 +12996,7 @@ pub unsafe fn vluti2_lane_p8<const LANE: i32>(a: poly8x8_t, b: uint8x8_t) -> pol
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, LANE = 1))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -13009,7 +13009,7 @@ pub unsafe fn vluti2q_lane_p8<const LANE: i32>(a: poly8x16_t, b: uint8x8_t) -> p
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, LANE = 1))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -13022,7 +13022,7 @@ pub unsafe fn vluti2_lane_p16<const LANE: i32>(a: poly16x4_t, b: uint8x8_t) -> p
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, LANE = 1))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -13035,7 +13035,7 @@ pub unsafe fn vluti2q_lane_p16<const LANE: i32>(a: poly16x8_t, b: uint8x8_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_lane_f16_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,lut,fp16")]
 #[cfg_attr(test, assert_instr(nop, LANE = 0))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -13048,7 +13048,7 @@ pub unsafe fn vluti4q_lane_f16_x2<const LANE: i32>(a: float16x8x2_t, b: uint8x8_
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_lane_u16_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, LANE = 0))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -13061,7 +13061,7 @@ pub unsafe fn vluti4q_lane_u16_x2<const LANE: i32>(a: uint16x8x2_t, b: uint8x8_t
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_lane_p16_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, LANE = 0))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -13074,7 +13074,7 @@ pub unsafe fn vluti4q_lane_p16_x2<const LANE: i32>(a: poly16x8x2_t, b: uint8x8_t
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_lane_s16_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, LANE = 0))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -13094,7 +13094,7 @@ pub unsafe fn vluti4q_lane_s16_x2<const LANE: i32>(a: int16x8x2_t, b: uint8x8_t)
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_lane_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, LANE = 0))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -13114,7 +13114,7 @@ pub unsafe fn vluti4q_lane_s8<const LANE: i32>(a: int8x16_t, b: uint8x8_t) -> in
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_lane_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, LANE = 0))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -13127,7 +13127,7 @@ pub unsafe fn vluti4q_lane_u8<const LANE: i32>(a: uint8x16_t, b: uint8x8_t) -> u
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_lane_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, LANE = 0))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -13140,7 +13140,7 @@ pub unsafe fn vluti4q_lane_p8<const LANE: i32>(a: poly8x16_t, b: uint8x8_t) -> p
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_laneq_f16_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,lut,fp16")]
 #[cfg_attr(test, assert_instr(nop, LANE = 3))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -13156,7 +13156,7 @@ pub unsafe fn vluti4q_laneq_f16_x2<const LANE: i32>(
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_laneq_u16_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, LANE = 3))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -13169,7 +13169,7 @@ pub unsafe fn vluti4q_laneq_u16_x2<const LANE: i32>(a: uint16x8x2_t, b: uint8x16
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_laneq_p16_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, LANE = 3))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -13182,7 +13182,7 @@ pub unsafe fn vluti4q_laneq_p16_x2<const LANE: i32>(a: poly16x8x2_t, b: uint8x16
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_laneq_s16_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, LANE = 3))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -13202,7 +13202,7 @@ pub unsafe fn vluti4q_laneq_s16_x2<const LANE: i32>(a: int16x8x2_t, b: uint8x16_
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_laneq_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, LANE = 0))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -13222,7 +13222,7 @@ pub unsafe fn vluti4q_laneq_s8<const LANE: i32>(a: int8x16_t, b: uint8x16_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_laneq_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, LANE = 0))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -13235,7 +13235,7 @@ pub unsafe fn vluti4q_laneq_u8<const LANE: i32>(a: uint8x16_t, b: uint8x16_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_laneq_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, LANE = 0))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -13246,7 +13246,7 @@ pub unsafe fn vluti4q_laneq_p8<const LANE: i32>(a: poly8x16_t, b: uint8x16_t) ->
 }
 #[doc = "Maximum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fmax))]
@@ -13262,7 +13262,7 @@ pub fn vmax_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t {
 }
 #[doc = "Maximum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fmax))]
@@ -13278,7 +13278,7 @@ pub fn vmaxq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
 }
 #[doc = "Maximum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxh_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -13295,7 +13295,7 @@ pub fn vmaxh_f16(a: f16, b: f16) -> f16 {
 }
 #[doc = "Floating-point Maximum Number (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnm_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fmaxnm))]
@@ -13304,7 +13304,7 @@ pub fn vmaxnm_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t {
 }
 #[doc = "Floating-point Maximum Number (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fmaxnm))]
@@ -13313,7 +13313,7 @@ pub fn vmaxnmq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
 }
 #[doc = "Floating-point Maximum Number"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmh_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -13323,7 +13323,7 @@ pub fn vmaxnmh_f16(a: f16, b: f16) -> f16 {
 }
 #[doc = "Floating-point maximum number across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmv_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -13333,7 +13333,7 @@ pub fn vmaxnmv_f16(a: float16x4_t) -> f16 {
 }
 #[doc = "Floating-point maximum number across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmvq_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -13343,7 +13343,7 @@ pub fn vmaxnmvq_f16(a: float16x8_t) -> f16 {
 }
 #[doc = "Floating-point maximum number across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmv_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fmaxnmp))]
@@ -13352,7 +13352,7 @@ pub fn vmaxnmv_f32(a: float32x2_t) -> f32 {
 }
 #[doc = "Floating-point maximum number across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmvq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fmaxnmp))]
@@ -13361,7 +13361,7 @@ pub fn vmaxnmvq_f64(a: float64x2_t) -> f64 {
 }
 #[doc = "Floating-point maximum number across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmvq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fmaxnmv))]
@@ -13370,7 +13370,7 @@ pub fn vmaxnmvq_f32(a: float32x4_t) -> f32 {
 }
 #[doc = "Floating-point maximum number across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxv_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -13387,7 +13387,7 @@ pub fn vmaxv_f16(a: float16x4_t) -> f16 {
 }
 #[doc = "Floating-point maximum number across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxvq_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -13404,7 +13404,7 @@ pub fn vmaxvq_f16(a: float16x8_t) -> f16 {
 }
 #[doc = "Horizontal vector max."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxv_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fmaxp))]
@@ -13420,7 +13420,7 @@ pub fn vmaxv_f32(a: float32x2_t) -> f32 {
 }
 #[doc = "Horizontal vector max."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxvq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fmaxv))]
@@ -13436,7 +13436,7 @@ pub fn vmaxvq_f32(a: float32x4_t) -> f32 {
 }
 #[doc = "Horizontal vector max."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxvq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fmaxp))]
@@ -13452,7 +13452,7 @@ pub fn vmaxvq_f64(a: float64x2_t) -> f64 {
 }
 #[doc = "Horizontal vector max."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxv_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(smaxv))]
@@ -13461,7 +13461,7 @@ pub fn vmaxv_s8(a: int8x8_t) -> i8 {
 }
 #[doc = "Horizontal vector max."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxvq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(smaxv))]
@@ -13470,7 +13470,7 @@ pub fn vmaxvq_s8(a: int8x16_t) -> i8 {
 }
 #[doc = "Horizontal vector max."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxv_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(smaxv))]
@@ -13479,7 +13479,7 @@ pub fn vmaxv_s16(a: int16x4_t) -> i16 {
 }
 #[doc = "Horizontal vector max."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxvq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(smaxv))]
@@ -13488,7 +13488,7 @@ pub fn vmaxvq_s16(a: int16x8_t) -> i16 {
 }
 #[doc = "Horizontal vector max."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxv_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(smaxp))]
@@ -13497,7 +13497,7 @@ pub fn vmaxv_s32(a: int32x2_t) -> i32 {
 }
 #[doc = "Horizontal vector max."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxvq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(smaxv))]
@@ -13506,7 +13506,7 @@ pub fn vmaxvq_s32(a: int32x4_t) -> i32 {
 }
 #[doc = "Horizontal vector max."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxv_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(umaxv))]
@@ -13515,7 +13515,7 @@ pub fn vmaxv_u8(a: uint8x8_t) -> u8 {
 }
 #[doc = "Horizontal vector max."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxvq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(umaxv))]
@@ -13524,7 +13524,7 @@ pub fn vmaxvq_u8(a: uint8x16_t) -> u8 {
 }
 #[doc = "Horizontal vector max."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxv_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(umaxv))]
@@ -13533,7 +13533,7 @@ pub fn vmaxv_u16(a: uint16x4_t) -> u16 {
 }
 #[doc = "Horizontal vector max."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxvq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(umaxv))]
@@ -13542,7 +13542,7 @@ pub fn vmaxvq_u16(a: uint16x8_t) -> u16 {
 }
 #[doc = "Horizontal vector max."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxv_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(umaxp))]
@@ -13551,7 +13551,7 @@ pub fn vmaxv_u32(a: uint32x2_t) -> u32 {
 }
 #[doc = "Horizontal vector max."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxvq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(umaxv))]
@@ -13560,7 +13560,7 @@ pub fn vmaxvq_u32(a: uint32x4_t) -> u32 {
 }
 #[doc = "Minimum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fmin))]
@@ -13576,7 +13576,7 @@ pub fn vmin_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t {
 }
 #[doc = "Minimum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fmin))]
@@ -13592,7 +13592,7 @@ pub fn vminq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
 }
 #[doc = "Minimum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminh_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -13609,7 +13609,7 @@ pub fn vminh_f16(a: f16, b: f16) -> f16 {
 }
 #[doc = "Floating-point Minimum Number (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnm_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fminnm))]
@@ -13618,7 +13618,7 @@ pub fn vminnm_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t {
 }
 #[doc = "Floating-point Minimum Number (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fminnm))]
@@ -13627,7 +13627,7 @@ pub fn vminnmq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
 }
 #[doc = "Floating-point Minimum Number"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmh_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -13637,7 +13637,7 @@ pub fn vminnmh_f16(a: f16, b: f16) -> f16 {
 }
 #[doc = "Floating-point minimum number across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmv_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -13647,7 +13647,7 @@ pub fn vminnmv_f16(a: float16x4_t) -> f16 {
 }
 #[doc = "Floating-point minimum number across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmvq_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -13657,7 +13657,7 @@ pub fn vminnmvq_f16(a: float16x8_t) -> f16 {
 }
 #[doc = "Floating-point minimum number across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmv_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fminnmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -13666,7 +13666,7 @@ pub fn vminnmv_f32(a: float32x2_t) -> f32 {
 }
 #[doc = "Floating-point minimum number across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmvq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fminnmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -13675,7 +13675,7 @@ pub fn vminnmvq_f64(a: float64x2_t) -> f64 {
 }
 #[doc = "Floating-point minimum number across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmvq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fminnmv))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -13684,7 +13684,7 @@ pub fn vminnmvq_f32(a: float32x4_t) -> f32 {
 }
 #[doc = "Floating-point minimum number across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminv_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -13701,7 +13701,7 @@ pub fn vminv_f16(a: float16x4_t) -> f16 {
 }
 #[doc = "Floating-point minimum number across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminvq_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -13718,7 +13718,7 @@ pub fn vminvq_f16(a: float16x8_t) -> f16 {
 }
 #[doc = "Horizontal vector min."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminv_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fminp))]
@@ -13734,7 +13734,7 @@ pub fn vminv_f32(a: float32x2_t) -> f32 {
 }
 #[doc = "Horizontal vector min."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminvq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fminv))]
@@ -13750,7 +13750,7 @@ pub fn vminvq_f32(a: float32x4_t) -> f32 {
 }
 #[doc = "Horizontal vector min."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminvq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fminp))]
@@ -13766,7 +13766,7 @@ pub fn vminvq_f64(a: float64x2_t) -> f64 {
 }
 #[doc = "Horizontal vector min."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminv_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sminv))]
@@ -13775,7 +13775,7 @@ pub fn vminv_s8(a: int8x8_t) -> i8 {
 }
 #[doc = "Horizontal vector min."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminvq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sminv))]
@@ -13784,7 +13784,7 @@ pub fn vminvq_s8(a: int8x16_t) -> i8 {
 }
 #[doc = "Horizontal vector min."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminv_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sminv))]
@@ -13793,7 +13793,7 @@ pub fn vminv_s16(a: int16x4_t) -> i16 {
 }
 #[doc = "Horizontal vector min."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminvq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sminv))]
@@ -13802,7 +13802,7 @@ pub fn vminvq_s16(a: int16x8_t) -> i16 {
 }
 #[doc = "Horizontal vector min."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminv_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sminp))]
@@ -13811,7 +13811,7 @@ pub fn vminv_s32(a: int32x2_t) -> i32 {
 }
 #[doc = "Horizontal vector min."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminvq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sminv))]
@@ -13820,7 +13820,7 @@ pub fn vminvq_s32(a: int32x4_t) -> i32 {
 }
 #[doc = "Horizontal vector min."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminv_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(uminv))]
@@ -13829,7 +13829,7 @@ pub fn vminv_u8(a: uint8x8_t) -> u8 {
 }
 #[doc = "Horizontal vector min."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminvq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(uminv))]
@@ -13838,7 +13838,7 @@ pub fn vminvq_u8(a: uint8x16_t) -> u8 {
 }
 #[doc = "Horizontal vector min."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminv_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(uminv))]
@@ -13847,7 +13847,7 @@ pub fn vminv_u16(a: uint16x4_t) -> u16 {
 }
 #[doc = "Horizontal vector min."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminvq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(uminv))]
@@ -13856,7 +13856,7 @@ pub fn vminvq_u16(a: uint16x8_t) -> u16 {
 }
 #[doc = "Horizontal vector min."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminv_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(uminp))]
@@ -13865,7 +13865,7 @@ pub fn vminv_u32(a: uint32x2_t) -> u32 {
 }
 #[doc = "Horizontal vector min."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminvq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(uminv))]
@@ -13874,7 +13874,7 @@ pub fn vminvq_u32(a: uint32x4_t) -> u32 {
 }
 #[doc = "Floating-point multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmul))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -13883,7 +13883,7 @@ pub fn vmla_f64(a: float64x1_t, b: float64x1_t, c: float64x1_t) -> float64x1_t {
 }
 #[doc = "Floating-point multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmul))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -13892,7 +13892,7 @@ pub fn vmlaq_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t
 }
 #[doc = "Multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_lane_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(smlal2, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -13922,7 +13922,7 @@ pub fn vmlal_high_lane_s16<const LANE: i32>(a: int32x4_t, b: int16x8_t, c: int16
 }
 #[doc = "Multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_laneq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(smlal2, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -13956,7 +13956,7 @@ pub fn vmlal_high_laneq_s16<const LANE: i32>(
 }
 #[doc = "Multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_lane_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(smlal2, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -13973,7 +13973,7 @@ pub fn vmlal_high_lane_s32<const LANE: i32>(a: int64x2_t, b: int32x4_t, c: int32
 }
 #[doc = "Multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_laneq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(smlal2, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -13994,7 +13994,7 @@ pub fn vmlal_high_laneq_s32<const LANE: i32>(
 }
 #[doc = "Multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_lane_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(umlal2, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -14028,7 +14028,7 @@ pub fn vmlal_high_lane_u16<const LANE: i32>(
 }
 #[doc = "Multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_laneq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(umlal2, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -14062,7 +14062,7 @@ pub fn vmlal_high_laneq_u16<const LANE: i32>(
 }
 #[doc = "Multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_lane_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(umlal2, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -14083,7 +14083,7 @@ pub fn vmlal_high_lane_u32<const LANE: i32>(
 }
 #[doc = "Multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_laneq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(umlal2, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -14104,7 +14104,7 @@ pub fn vmlal_high_laneq_u32<const LANE: i32>(
 }
 #[doc = "Multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(smlal2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -14113,7 +14113,7 @@ pub fn vmlal_high_n_s16(a: int32x4_t, b: int16x8_t, c: i16) -> int32x4_t {
 }
 #[doc = "Multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(smlal2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -14122,7 +14122,7 @@ pub fn vmlal_high_n_s32(a: int64x2_t, b: int32x4_t, c: i32) -> int64x2_t {
 }
 #[doc = "Multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_n_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(umlal2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -14131,7 +14131,7 @@ pub fn vmlal_high_n_u16(a: uint32x4_t, b: uint16x8_t, c: u16) -> uint32x4_t {
 }
 #[doc = "Multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_n_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(umlal2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -14140,7 +14140,7 @@ pub fn vmlal_high_n_u32(a: uint64x2_t, b: uint32x4_t, c: u32) -> uint64x2_t {
 }
 #[doc = "Signed multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(smlal2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -14153,7 +14153,7 @@ pub fn vmlal_high_s8(a: int16x8_t, b: int8x16_t, c: int8x16_t) -> int16x8_t {
 }
 #[doc = "Signed multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(smlal2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -14166,7 +14166,7 @@ pub fn vmlal_high_s16(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t {
 }
 #[doc = "Signed multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(smlal2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -14179,7 +14179,7 @@ pub fn vmlal_high_s32(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t {
 }
 #[doc = "Unsigned multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(umlal2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -14192,7 +14192,7 @@ pub fn vmlal_high_u8(a: uint16x8_t, b: uint8x16_t, c: uint8x16_t) -> uint16x8_t
 }
 #[doc = "Unsigned multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(umlal2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -14205,7 +14205,7 @@ pub fn vmlal_high_u16(a: uint32x4_t, b: uint16x8_t, c: uint16x8_t) -> uint32x4_t
 }
 #[doc = "Unsigned multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(umlal2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -14218,7 +14218,7 @@ pub fn vmlal_high_u32(a: uint64x2_t, b: uint32x4_t, c: uint32x4_t) -> uint64x2_t
 }
 #[doc = "Floating-point multiply-subtract from accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmul))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -14227,7 +14227,7 @@ pub fn vmls_f64(a: float64x1_t, b: float64x1_t, c: float64x1_t) -> float64x1_t {
 }
 #[doc = "Floating-point multiply-subtract from accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmul))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -14236,7 +14236,7 @@ pub fn vmlsq_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t
 }
 #[doc = "Multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_lane_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(smlsl2, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -14266,7 +14266,7 @@ pub fn vmlsl_high_lane_s16<const LANE: i32>(a: int32x4_t, b: int16x8_t, c: int16
 }
 #[doc = "Multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_laneq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(smlsl2, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -14300,7 +14300,7 @@ pub fn vmlsl_high_laneq_s16<const LANE: i32>(
 }
 #[doc = "Multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_lane_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(smlsl2, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -14317,7 +14317,7 @@ pub fn vmlsl_high_lane_s32<const LANE: i32>(a: int64x2_t, b: int32x4_t, c: int32
 }
 #[doc = "Multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_laneq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(smlsl2, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -14338,7 +14338,7 @@ pub fn vmlsl_high_laneq_s32<const LANE: i32>(
 }
 #[doc = "Multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_lane_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(umlsl2, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -14372,7 +14372,7 @@ pub fn vmlsl_high_lane_u16<const LANE: i32>(
 }
 #[doc = "Multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_laneq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(umlsl2, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -14406,7 +14406,7 @@ pub fn vmlsl_high_laneq_u16<const LANE: i32>(
 }
 #[doc = "Multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_lane_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(umlsl2, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -14427,7 +14427,7 @@ pub fn vmlsl_high_lane_u32<const LANE: i32>(
 }
 #[doc = "Multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_laneq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(umlsl2, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -14448,7 +14448,7 @@ pub fn vmlsl_high_laneq_u32<const LANE: i32>(
 }
 #[doc = "Multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(smlsl2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -14457,7 +14457,7 @@ pub fn vmlsl_high_n_s16(a: int32x4_t, b: int16x8_t, c: i16) -> int32x4_t {
 }
 #[doc = "Multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(smlsl2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -14466,7 +14466,7 @@ pub fn vmlsl_high_n_s32(a: int64x2_t, b: int32x4_t, c: i32) -> int64x2_t {
 }
 #[doc = "Multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_n_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(umlsl2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -14475,7 +14475,7 @@ pub fn vmlsl_high_n_u16(a: uint32x4_t, b: uint16x8_t, c: u16) -> uint32x4_t {
 }
 #[doc = "Multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_n_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(umlsl2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -14484,7 +14484,7 @@ pub fn vmlsl_high_n_u32(a: uint64x2_t, b: uint32x4_t, c: u32) -> uint64x2_t {
 }
 #[doc = "Signed multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(smlsl2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -14497,7 +14497,7 @@ pub fn vmlsl_high_s8(a: int16x8_t, b: int8x16_t, c: int8x16_t) -> int16x8_t {
 }
 #[doc = "Signed multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(smlsl2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -14510,7 +14510,7 @@ pub fn vmlsl_high_s16(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t {
 }
 #[doc = "Signed multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(smlsl2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -14523,7 +14523,7 @@ pub fn vmlsl_high_s32(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t {
 }
 #[doc = "Unsigned multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(umlsl2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -14536,7 +14536,7 @@ pub fn vmlsl_high_u8(a: uint16x8_t, b: uint8x16_t, c: uint8x16_t) -> uint16x8_t
 }
 #[doc = "Unsigned multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(umlsl2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -14549,7 +14549,7 @@ pub fn vmlsl_high_u16(a: uint32x4_t, b: uint16x8_t, c: uint16x8_t) -> uint32x4_t
 }
 #[doc = "Unsigned multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(umlsl2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -14562,7 +14562,7 @@ pub fn vmlsl_high_u32(a: uint64x2_t, b: uint32x4_t, c: uint32x4_t) -> uint64x2_t
 }
 #[doc = "Vector move"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_high_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sxtl2))]
@@ -14574,7 +14574,7 @@ pub fn vmovl_high_s8(a: int8x16_t) -> int16x8_t {
 }
 #[doc = "Vector move"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_high_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sxtl2))]
@@ -14586,7 +14586,7 @@ pub fn vmovl_high_s16(a: int16x8_t) -> int32x4_t {
 }
 #[doc = "Vector move"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_high_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sxtl2))]
@@ -14598,7 +14598,7 @@ pub fn vmovl_high_s32(a: int32x4_t) -> int64x2_t {
 }
 #[doc = "Vector move"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_high_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(uxtl2))]
@@ -14610,7 +14610,7 @@ pub fn vmovl_high_u8(a: uint8x16_t) -> uint16x8_t {
 }
 #[doc = "Vector move"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_high_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(uxtl2))]
@@ -14622,7 +14622,7 @@ pub fn vmovl_high_u16(a: uint16x8_t) -> uint32x4_t {
 }
 #[doc = "Vector move"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_high_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(uxtl2))]
@@ -14634,7 +14634,7 @@ pub fn vmovl_high_u32(a: uint32x4_t) -> uint64x2_t {
 }
 #[doc = "Extract narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_high_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(xtn2))]
@@ -14646,7 +14646,7 @@ pub fn vmovn_high_s16(a: int8x8_t, b: int16x8_t) -> int8x16_t {
 }
 #[doc = "Extract narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_high_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(xtn2))]
@@ -14658,7 +14658,7 @@ pub fn vmovn_high_s32(a: int16x4_t, b: int32x4_t) -> int16x8_t {
 }
 #[doc = "Extract narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_high_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(xtn2))]
@@ -14670,7 +14670,7 @@ pub fn vmovn_high_s64(a: int32x2_t, b: int64x2_t) -> int32x4_t {
 }
 #[doc = "Extract narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_high_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(xtn2))]
@@ -14682,7 +14682,7 @@ pub fn vmovn_high_u16(a: uint8x8_t, b: uint16x8_t) -> uint8x16_t {
 }
 #[doc = "Extract narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_high_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(xtn2))]
@@ -14694,7 +14694,7 @@ pub fn vmovn_high_u32(a: uint16x4_t, b: uint32x4_t) -> uint16x8_t {
 }
 #[doc = "Extract narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_high_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(xtn2))]
@@ -14706,7 +14706,7 @@ pub fn vmovn_high_u64(a: uint32x2_t, b: uint64x2_t) -> uint32x4_t {
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fmul))]
@@ -14715,7 +14715,7 @@ pub fn vmul_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t {
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fmul))]
@@ -14724,7 +14724,7 @@ pub fn vmulq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
 }
 #[doc = "Floating-point multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_lane_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmul, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -14735,7 +14735,7 @@ pub fn vmul_lane_f64<const LANE: i32>(a: float64x1_t, b: float64x1_t) -> float64
 }
 #[doc = "Floating-point multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_laneq_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fmul, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
 #[target_feature(enable = "neon,fp16")]
@@ -14752,7 +14752,7 @@ pub fn vmul_laneq_f16<const LANE: i32>(a: float16x4_t, b: float16x8_t) -> float1
 }
 #[doc = "Floating-point multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fmul, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
 #[target_feature(enable = "neon,fp16")]
@@ -14782,7 +14782,7 @@ pub fn vmulq_laneq_f16<const LANE: i32>(a: float16x8_t, b: float16x8_t) -> float
 }
 #[doc = "Floating-point multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_laneq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmul, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -14793,7 +14793,7 @@ pub fn vmul_laneq_f64<const LANE: i32>(a: float64x1_t, b: float64x2_t) -> float6
 }
 #[doc = "Vector multiply by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_n_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmul))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -14802,7 +14802,7 @@ pub fn vmul_n_f64(a: float64x1_t, b: f64) -> float64x1_t {
 }
 #[doc = "Vector multiply by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_n_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmul))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -14811,7 +14811,7 @@ pub fn vmulq_n_f64(a: float64x2_t, b: f64) -> float64x2_t {
 }
 #[doc = "Floating-point multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmuld_lane_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmul, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -14825,7 +14825,7 @@ pub fn vmuld_lane_f64<const LANE: i32>(a: f64, b: float64x1_t) -> f64 {
 }
 #[doc = "Add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulh_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -14835,7 +14835,7 @@ pub fn vmulh_f16(a: f16, b: f16) -> f16 {
 }
 #[doc = "Floating-point multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulh_lane_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fmul, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
 #[target_feature(enable = "neon,fp16")]
@@ -14850,7 +14850,7 @@ pub fn vmulh_lane_f16<const LANE: i32>(a: f16, b: float16x4_t) -> f16 {
 }
 #[doc = "Floating-point multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulh_laneq_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fmul, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
 #[target_feature(enable = "neon,fp16")]
@@ -14865,7 +14865,7 @@ pub fn vmulh_laneq_f16<const LANE: i32>(a: f16, b: float16x8_t) -> f16 {
 }
 #[doc = "Multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_lane_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(smull2, LANE = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -14894,7 +14894,7 @@ pub fn vmull_high_lane_s16<const LANE: i32>(a: int16x8_t, b: int16x4_t) -> int32
 }
 #[doc = "Multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_laneq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(smull2, LANE = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -14923,7 +14923,7 @@ pub fn vmull_high_laneq_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t) -> int3
 }
 #[doc = "Multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_lane_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(smull2, LANE = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -14939,7 +14939,7 @@ pub fn vmull_high_lane_s32<const LANE: i32>(a: int32x4_t, b: int32x2_t) -> int64
 }
 #[doc = "Multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_laneq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(smull2, LANE = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -14955,7 +14955,7 @@ pub fn vmull_high_laneq_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t) -> int6
 }
 #[doc = "Multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_lane_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(umull2, LANE = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -14984,7 +14984,7 @@ pub fn vmull_high_lane_u16<const LANE: i32>(a: uint16x8_t, b: uint16x4_t) -> uin
 }
 #[doc = "Multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_laneq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(umull2, LANE = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -15013,7 +15013,7 @@ pub fn vmull_high_laneq_u16<const LANE: i32>(a: uint16x8_t, b: uint16x8_t) -> ui
 }
 #[doc = "Multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_lane_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(umull2, LANE = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -15029,7 +15029,7 @@ pub fn vmull_high_lane_u32<const LANE: i32>(a: uint32x4_t, b: uint32x2_t) -> uin
 }
 #[doc = "Multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_laneq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(umull2, LANE = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -15045,7 +15045,7 @@ pub fn vmull_high_laneq_u32<const LANE: i32>(a: uint32x4_t, b: uint32x4_t) -> ui
 }
 #[doc = "Multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(smull2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -15054,7 +15054,7 @@ pub fn vmull_high_n_s16(a: int16x8_t, b: i16) -> int32x4_t {
 }
 #[doc = "Multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(smull2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -15063,7 +15063,7 @@ pub fn vmull_high_n_s32(a: int32x4_t, b: i32) -> int64x2_t {
 }
 #[doc = "Multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_n_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(umull2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -15072,7 +15072,7 @@ pub fn vmull_high_n_u16(a: uint16x8_t, b: u16) -> uint32x4_t {
 }
 #[doc = "Multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_n_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(umull2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -15081,7 +15081,7 @@ pub fn vmull_high_n_u32(a: uint32x4_t, b: u32) -> uint64x2_t {
 }
 #[doc = "Polynomial multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_p64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(pmull2))]
@@ -15090,7 +15090,7 @@ pub fn vmull_high_p64(a: poly64x2_t, b: poly64x2_t) -> p128 {
 }
 #[doc = "Polynomial multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(pmull2))]
@@ -15103,7 +15103,7 @@ pub fn vmull_high_p8(a: poly8x16_t, b: poly8x16_t) -> poly16x8_t {
 }
 #[doc = "Signed multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(smull2))]
@@ -15116,7 +15116,7 @@ pub fn vmull_high_s8(a: int8x16_t, b: int8x16_t) -> int16x8_t {
 }
 #[doc = "Signed multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(smull2))]
@@ -15129,7 +15129,7 @@ pub fn vmull_high_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t {
 }
 #[doc = "Signed multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(smull2))]
@@ -15142,7 +15142,7 @@ pub fn vmull_high_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t {
 }
 #[doc = "Unsigned multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(umull2))]
@@ -15155,7 +15155,7 @@ pub fn vmull_high_u8(a: uint8x16_t, b: uint8x16_t) -> uint16x8_t {
 }
 #[doc = "Unsigned multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(umull2))]
@@ -15168,7 +15168,7 @@ pub fn vmull_high_u16(a: uint16x8_t, b: uint16x8_t) -> uint32x4_t {
 }
 #[doc = "Unsigned multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(umull2))]
@@ -15181,7 +15181,7 @@ pub fn vmull_high_u32(a: uint32x4_t, b: uint32x4_t) -> uint64x2_t {
 }
 #[doc = "Polynomial multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_p64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(pmull))]
@@ -15197,7 +15197,7 @@ pub fn vmull_p64(a: p64, b: p64) -> p128 {
 }
 #[doc = "Floating-point multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_lane_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmul, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -15208,7 +15208,7 @@ pub fn vmulq_lane_f64<const LANE: i32>(a: float64x2_t, b: float64x1_t) -> float6
 }
 #[doc = "Floating-point multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmul, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -15219,7 +15219,7 @@ pub fn vmulq_laneq_f64<const LANE: i32>(a: float64x2_t, b: float64x2_t) -> float
 }
 #[doc = "Floating-point multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmuls_lane_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmul, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -15233,7 +15233,7 @@ pub fn vmuls_lane_f32<const LANE: i32>(a: f32, b: float32x2_t) -> f32 {
 }
 #[doc = "Floating-point multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmuls_laneq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmul, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -15247,7 +15247,7 @@ pub fn vmuls_laneq_f32<const LANE: i32>(a: f32, b: float32x4_t) -> f32 {
 }
 #[doc = "Floating-point multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmuld_laneq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmul, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -15261,7 +15261,7 @@ pub fn vmuld_laneq_f64<const LANE: i32>(a: f64, b: float64x2_t) -> f64 {
 }
 #[doc = "Floating-point multiply extended"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulx_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -15278,7 +15278,7 @@ pub fn vmulx_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 }
 #[doc = "Floating-point multiply extended"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -15295,7 +15295,7 @@ pub fn vmulxq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
 }
 #[doc = "Floating-point multiply extended"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulx_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fmulx))]
@@ -15311,7 +15311,7 @@ pub fn vmulx_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
 }
 #[doc = "Floating-point multiply extended"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fmulx))]
@@ -15327,7 +15327,7 @@ pub fn vmulxq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
 }
 #[doc = "Floating-point multiply extended"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulx_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fmulx))]
@@ -15343,7 +15343,7 @@ pub fn vmulx_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t {
 }
 #[doc = "Floating-point multiply extended"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fmulx))]
@@ -15359,7 +15359,7 @@ pub fn vmulxq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
 }
 #[doc = "Floating-point multiply extended"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulx_lane_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fmulx, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
 #[target_feature(enable = "neon,fp16")]
@@ -15376,7 +15376,7 @@ pub fn vmulx_lane_f16<const LANE: i32>(a: float16x4_t, b: float16x4_t) -> float1
 }
 #[doc = "Floating-point multiply extended"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulx_laneq_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fmulx, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
 #[target_feature(enable = "neon,fp16")]
@@ -15393,7 +15393,7 @@ pub fn vmulx_laneq_f16<const LANE: i32>(a: float16x4_t, b: float16x8_t) -> float
 }
 #[doc = "Floating-point multiply extended"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_lane_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fmulx, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
 #[target_feature(enable = "neon,fp16")]
@@ -15423,7 +15423,7 @@ pub fn vmulxq_lane_f16<const LANE: i32>(a: float16x8_t, b: float16x4_t) -> float
 }
 #[doc = "Floating-point multiply extended"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_laneq_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fmulx, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
 #[target_feature(enable = "neon,fp16")]
@@ -15453,7 +15453,7 @@ pub fn vmulxq_laneq_f16<const LANE: i32>(a: float16x8_t, b: float16x8_t) -> floa
 }
 #[doc = "Floating-point multiply extended"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulx_lane_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmulx, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -15464,7 +15464,7 @@ pub fn vmulx_lane_f32<const LANE: i32>(a: float32x2_t, b: float32x2_t) -> float3
 }
 #[doc = "Floating-point multiply extended"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulx_laneq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmulx, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -15475,7 +15475,7 @@ pub fn vmulx_laneq_f32<const LANE: i32>(a: float32x2_t, b: float32x4_t) -> float
 }
 #[doc = "Floating-point multiply extended"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_lane_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmulx, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -15491,7 +15491,7 @@ pub fn vmulxq_lane_f32<const LANE: i32>(a: float32x4_t, b: float32x2_t) -> float
 }
 #[doc = "Floating-point multiply extended"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_laneq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmulx, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -15507,7 +15507,7 @@ pub fn vmulxq_laneq_f32<const LANE: i32>(a: float32x4_t, b: float32x4_t) -> floa
 }
 #[doc = "Floating-point multiply extended"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_laneq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmulx, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -15518,7 +15518,7 @@ pub fn vmulxq_laneq_f64<const LANE: i32>(a: float64x2_t, b: float64x2_t) -> floa
 }
 #[doc = "Floating-point multiply extended"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulx_lane_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmulx, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -15529,7 +15529,7 @@ pub fn vmulx_lane_f64<const LANE: i32>(a: float64x1_t, b: float64x1_t) -> float6
 }
 #[doc = "Floating-point multiply extended"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulx_laneq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmulx, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -15540,7 +15540,7 @@ pub fn vmulx_laneq_f64<const LANE: i32>(a: float64x1_t, b: float64x2_t) -> float
 }
 #[doc = "Vector multiply by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulx_n_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fmulx))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -15550,7 +15550,7 @@ pub fn vmulx_n_f16(a: float16x4_t, b: f16) -> float16x4_t {
 }
 #[doc = "Vector multiply by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_n_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fmulx))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -15560,7 +15560,7 @@ pub fn vmulxq_n_f16(a: float16x8_t, b: f16) -> float16x8_t {
 }
 #[doc = "Floating-point multiply extended"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxd_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fmulx))]
@@ -15576,7 +15576,7 @@ pub fn vmulxd_f64(a: f64, b: f64) -> f64 {
 }
 #[doc = "Floating-point multiply extended"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxs_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fmulx))]
@@ -15592,7 +15592,7 @@ pub fn vmulxs_f32(a: f32, b: f32) -> f32 {
 }
 #[doc = "Floating-point multiply extended"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxd_lane_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmulx, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -15603,7 +15603,7 @@ pub fn vmulxd_lane_f64<const LANE: i32>(a: f64, b: float64x1_t) -> f64 {
 }
 #[doc = "Floating-point multiply extended"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxd_laneq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmulx, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -15614,7 +15614,7 @@ pub fn vmulxd_laneq_f64<const LANE: i32>(a: f64, b: float64x2_t) -> f64 {
 }
 #[doc = "Floating-point multiply extended"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxs_lane_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmulx, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -15625,7 +15625,7 @@ pub fn vmulxs_lane_f32<const LANE: i32>(a: f32, b: float32x2_t) -> f32 {
 }
 #[doc = "Floating-point multiply extended"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxs_laneq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmulx, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -15636,7 +15636,7 @@ pub fn vmulxs_laneq_f32<const LANE: i32>(a: f32, b: float32x4_t) -> f32 {
 }
 #[doc = "Floating-point multiply extended"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxh_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -15653,7 +15653,7 @@ pub fn vmulxh_f16(a: f16, b: f16) -> f16 {
 }
 #[doc = "Floating-point multiply extended"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxh_lane_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fmulx, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
 #[target_feature(enable = "neon,fp16")]
@@ -15665,7 +15665,7 @@ pub fn vmulxh_lane_f16<const LANE: i32>(a: f16, b: float16x4_t) -> f16 {
 }
 #[doc = "Floating-point multiply extended"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxh_laneq_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fmulx, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
 #[target_feature(enable = "neon,fp16")]
@@ -15677,7 +15677,7 @@ pub fn vmulxh_laneq_f16<const LANE: i32>(a: f16, b: float16x8_t) -> f16 {
 }
 #[doc = "Floating-point multiply extended"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_lane_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmulx, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -15688,7 +15688,7 @@ pub fn vmulxq_lane_f64<const LANE: i32>(a: float64x2_t, b: float64x1_t) -> float
 }
 #[doc = "Negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vneg_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fneg))]
@@ -15697,7 +15697,7 @@ pub fn vneg_f64(a: float64x1_t) -> float64x1_t {
 }
 #[doc = "Negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fneg))]
@@ -15706,7 +15706,7 @@ pub fn vnegq_f64(a: float64x2_t) -> float64x2_t {
 }
 #[doc = "Negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vneg_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(neg))]
@@ -15715,7 +15715,7 @@ pub fn vneg_s64(a: int64x1_t) -> int64x1_t {
 }
 #[doc = "Negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegq_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(neg))]
@@ -15724,7 +15724,7 @@ pub fn vnegq_s64(a: int64x2_t) -> int64x2_t {
 }
 #[doc = "Negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegd_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(neg))]
@@ -15733,7 +15733,7 @@ pub fn vnegd_s64(a: i64) -> i64 {
 }
 #[doc = "Negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegh_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -15743,7 +15743,7 @@ pub fn vnegh_f16(a: f16) -> f16 {
 }
 #[doc = "Floating-point add pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddd_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(nop))]
@@ -15756,7 +15756,7 @@ pub fn vpaddd_f64(a: float64x2_t) -> f64 {
 }
 #[doc = "Floating-point add pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadds_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(nop))]
@@ -15769,7 +15769,7 @@ pub fn vpadds_f32(a: float32x2_t) -> f32 {
 }
 #[doc = "Add pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddd_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(addp))]
@@ -15778,7 +15778,7 @@ pub fn vpaddd_s64(a: int64x2_t) -> i64 {
 }
 #[doc = "Add pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddd_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(addp))]
@@ -15787,7 +15787,7 @@ pub fn vpaddd_u64(a: uint64x2_t) -> u64 {
 }
 #[doc = "Floating-point add pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -15804,7 +15804,7 @@ pub fn vpaddq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
 }
 #[doc = "Floating-point add pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(faddp))]
@@ -15820,7 +15820,7 @@ pub fn vpaddq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
 }
 #[doc = "Floating-point add pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(faddp))]
@@ -15836,7 +15836,7 @@ pub fn vpaddq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
 }
 #[doc = "Add Pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(addp))]
@@ -15852,7 +15852,7 @@ pub fn vpaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Add Pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(addp))]
@@ -15868,7 +15868,7 @@ pub fn vpaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Add Pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(addp))]
@@ -15884,7 +15884,7 @@ pub fn vpaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Add Pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(addp))]
@@ -15900,7 +15900,7 @@ pub fn vpaddq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
 }
 #[doc = "Add Pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -15910,7 +15910,7 @@ pub fn vpaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Add Pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -15931,7 +15931,7 @@ pub fn vpaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Add Pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -15941,7 +15941,7 @@ pub fn vpaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Add Pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -15956,7 +15956,7 @@ pub fn vpaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Add Pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -15966,7 +15966,7 @@ pub fn vpaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Add Pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -15981,7 +15981,7 @@ pub fn vpaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Add Pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -15991,7 +15991,7 @@ pub fn vpaddq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Add Pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -16006,7 +16006,7 @@ pub fn vpaddq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Floating-point add pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -16023,7 +16023,7 @@ pub fn vpmax_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 }
 #[doc = "Floating-point add pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxq_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -16040,7 +16040,7 @@ pub fn vpmaxq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
 }
 #[doc = "Floating-point add pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxnm_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -16057,7 +16057,7 @@ pub fn vpmaxnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 }
 #[doc = "Floating-point add pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxnmq_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -16074,7 +16074,7 @@ pub fn vpmaxnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
 }
 #[doc = "Floating-point Maximum Number Pairwise (vector)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxnm_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmaxnmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -16090,7 +16090,7 @@ pub fn vpmaxnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
 }
 #[doc = "Floating-point Maximum Number Pairwise (vector)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxnmq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmaxnmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -16106,7 +16106,7 @@ pub fn vpmaxnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
 }
 #[doc = "Floating-point Maximum Number Pairwise (vector)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxnmq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmaxnmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -16122,7 +16122,7 @@ pub fn vpmaxnmq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
 }
 #[doc = "Floating-point maximum number pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxnmqd_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmaxnmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -16138,7 +16138,7 @@ pub fn vpmaxnmqd_f64(a: float64x2_t) -> f64 {
 }
 #[doc = "Floating-point maximum number pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxnms_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fmaxnmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -16154,7 +16154,7 @@ pub fn vpmaxnms_f32(a: float32x2_t) -> f32 {
 }
 #[doc = "Folding maximum of adjacent pairs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fmaxp))]
@@ -16170,7 +16170,7 @@ pub fn vpmaxq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
 }
 #[doc = "Folding maximum of adjacent pairs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fmaxp))]
@@ -16186,7 +16186,7 @@ pub fn vpmaxq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
 }
 #[doc = "Folding maximum of adjacent pairs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(smaxp))]
@@ -16202,7 +16202,7 @@ pub fn vpmaxq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Folding maximum of adjacent pairs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(smaxp))]
@@ -16218,7 +16218,7 @@ pub fn vpmaxq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Folding maximum of adjacent pairs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(smaxp))]
@@ -16234,7 +16234,7 @@ pub fn vpmaxq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Folding maximum of adjacent pairs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(umaxp))]
@@ -16250,7 +16250,7 @@ pub fn vpmaxq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Folding maximum of adjacent pairs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(umaxp))]
@@ -16266,7 +16266,7 @@ pub fn vpmaxq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Folding maximum of adjacent pairs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(umaxp))]
@@ -16282,7 +16282,7 @@ pub fn vpmaxq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Floating-point maximum pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxqd_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fmaxp))]
@@ -16298,7 +16298,7 @@ pub fn vpmaxqd_f64(a: float64x2_t) -> f64 {
 }
 #[doc = "Floating-point maximum pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxs_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fmaxp))]
@@ -16314,7 +16314,7 @@ pub fn vpmaxs_f32(a: float32x2_t) -> f32 {
 }
 #[doc = "Floating-point add pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -16331,7 +16331,7 @@ pub fn vpmin_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 }
 #[doc = "Floating-point add pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminq_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -16348,7 +16348,7 @@ pub fn vpminq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
 }
 #[doc = "Floating-point add pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminnm_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -16365,7 +16365,7 @@ pub fn vpminnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 }
 #[doc = "Floating-point add pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminnmq_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -16382,7 +16382,7 @@ pub fn vpminnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
 }
 #[doc = "Floating-point Minimum Number Pairwise (vector)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminnm_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fminnmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -16398,7 +16398,7 @@ pub fn vpminnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
 }
 #[doc = "Floating-point Minimum Number Pairwise (vector)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminnmq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fminnmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -16414,7 +16414,7 @@ pub fn vpminnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
 }
 #[doc = "Floating-point Minimum Number Pairwise (vector)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminnmq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fminnmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -16430,7 +16430,7 @@ pub fn vpminnmq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
 }
 #[doc = "Floating-point minimum number pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminnmqd_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fminnmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -16446,7 +16446,7 @@ pub fn vpminnmqd_f64(a: float64x2_t) -> f64 {
 }
 #[doc = "Floating-point minimum number pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminnms_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fminnmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -16462,7 +16462,7 @@ pub fn vpminnms_f32(a: float32x2_t) -> f32 {
 }
 #[doc = "Folding minimum of adjacent pairs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fminp))]
@@ -16478,7 +16478,7 @@ pub fn vpminq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
 }
 #[doc = "Folding minimum of adjacent pairs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fminp))]
@@ -16494,7 +16494,7 @@ pub fn vpminq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
 }
 #[doc = "Folding minimum of adjacent pairs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sminp))]
@@ -16510,7 +16510,7 @@ pub fn vpminq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Folding minimum of adjacent pairs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sminp))]
@@ -16526,7 +16526,7 @@ pub fn vpminq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Folding minimum of adjacent pairs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sminp))]
@@ -16542,7 +16542,7 @@ pub fn vpminq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Folding minimum of adjacent pairs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(uminp))]
@@ -16558,7 +16558,7 @@ pub fn vpminq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Folding minimum of adjacent pairs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(uminp))]
@@ -16574,7 +16574,7 @@ pub fn vpminq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Folding minimum of adjacent pairs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(uminp))]
@@ -16590,7 +16590,7 @@ pub fn vpminq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Floating-point minimum pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminqd_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fminp))]
@@ -16606,7 +16606,7 @@ pub fn vpminqd_f64(a: float64x2_t) -> f64 {
 }
 #[doc = "Floating-point minimum pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmins_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fminp))]
@@ -16622,7 +16622,7 @@ pub fn vpmins_f32(a: float32x2_t) -> f32 {
 }
 #[doc = "Signed saturating Absolute value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabs_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sqabs))]
@@ -16638,7 +16638,7 @@ pub fn vqabs_s64(a: int64x1_t) -> int64x1_t {
 }
 #[doc = "Signed saturating Absolute value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabsq_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sqabs))]
@@ -16654,7 +16654,7 @@ pub fn vqabsq_s64(a: int64x2_t) -> int64x2_t {
 }
 #[doc = "Signed saturating absolute value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabsb_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sqabs))]
@@ -16663,7 +16663,7 @@ pub fn vqabsb_s8(a: i8) -> i8 {
 }
 #[doc = "Signed saturating absolute value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabsh_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sqabs))]
@@ -16672,7 +16672,7 @@ pub fn vqabsh_s16(a: i16) -> i16 {
 }
 #[doc = "Signed saturating absolute value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabss_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sqabs))]
@@ -16688,7 +16688,7 @@ pub fn vqabss_s32(a: i32) -> i32 {
 }
 #[doc = "Signed saturating absolute value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabsd_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sqabs))]
@@ -16704,7 +16704,7 @@ pub fn vqabsd_s64(a: i64) -> i64 {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddb_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sqadd))]
@@ -16715,7 +16715,7 @@ pub fn vqaddb_s8(a: i8, b: i8) -> i8 {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddh_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sqadd))]
@@ -16726,7 +16726,7 @@ pub fn vqaddh_s16(a: i16, b: i16) -> i16 {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddb_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(uqadd))]
@@ -16737,7 +16737,7 @@ pub fn vqaddb_u8(a: u8, b: u8) -> u8 {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddh_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(uqadd))]
@@ -16748,7 +16748,7 @@ pub fn vqaddh_u16(a: u16, b: u16) -> u16 {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadds_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sqadd))]
@@ -16764,7 +16764,7 @@ pub fn vqadds_s32(a: i32, b: i32) -> i32 {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddd_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sqadd))]
@@ -16780,7 +16780,7 @@ pub fn vqaddd_s64(a: i64, b: i64) -> i64 {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadds_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(uqadd))]
@@ -16796,7 +16796,7 @@ pub fn vqadds_u32(a: u32, b: u32) -> u32 {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddd_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(uqadd))]
@@ -16812,7 +16812,7 @@ pub fn vqaddd_u64(a: u64, b: u64) -> u64 {
 }
 #[doc = "Signed saturating doubling multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_high_lane_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmlal2, N = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -16823,7 +16823,7 @@ pub fn vqdmlal_high_lane_s16<const N: i32>(a: int32x4_t, b: int16x8_t, c: int16x
 }
 #[doc = "Signed saturating doubling multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_high_laneq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmlal2, N = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -16834,7 +16834,7 @@ pub fn vqdmlal_high_laneq_s16<const N: i32>(a: int32x4_t, b: int16x8_t, c: int16
 }
 #[doc = "Signed saturating doubling multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_high_lane_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmlal2, N = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -16845,7 +16845,7 @@ pub fn vqdmlal_high_lane_s32<const N: i32>(a: int64x2_t, b: int32x4_t, c: int32x
 }
 #[doc = "Signed saturating doubling multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_high_laneq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmlal2, N = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -16856,7 +16856,7 @@ pub fn vqdmlal_high_laneq_s32<const N: i32>(a: int64x2_t, b: int32x4_t, c: int32
 }
 #[doc = "Signed saturating doubling multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_high_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmlal2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -16865,7 +16865,7 @@ pub fn vqdmlal_high_n_s16(a: int32x4_t, b: int16x8_t, c: i16) -> int32x4_t {
 }
 #[doc = "Signed saturating doubling multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_high_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmlal2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -16874,7 +16874,7 @@ pub fn vqdmlal_high_s16(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t {
 }
 #[doc = "Signed saturating doubling multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_high_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmlal2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -16883,7 +16883,7 @@ pub fn vqdmlal_high_n_s32(a: int64x2_t, b: int32x4_t, c: i32) -> int64x2_t {
 }
 #[doc = "Signed saturating doubling multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_high_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmlal2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -16892,7 +16892,7 @@ pub fn vqdmlal_high_s32(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t {
 }
 #[doc = "Vector widening saturating doubling multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_laneq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmlal, N = 2))]
 #[rustc_legacy_const_generics(3)]
@@ -16903,7 +16903,7 @@ pub fn vqdmlal_laneq_s16<const N: i32>(a: int32x4_t, b: int16x4_t, c: int16x8_t)
 }
 #[doc = "Vector widening saturating doubling multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_laneq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmlal, N = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -16914,7 +16914,7 @@ pub fn vqdmlal_laneq_s32<const N: i32>(a: int64x2_t, b: int32x2_t, c: int32x4_t)
 }
 #[doc = "Signed saturating doubling multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlalh_lane_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmlal, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -16925,7 +16925,7 @@ pub fn vqdmlalh_lane_s16<const LANE: i32>(a: i32, b: i16, c: int16x4_t) -> i32 {
 }
 #[doc = "Signed saturating doubling multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlalh_laneq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmlal, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -16936,7 +16936,7 @@ pub fn vqdmlalh_laneq_s16<const LANE: i32>(a: i32, b: i16, c: int16x8_t) -> i32
 }
 #[doc = "Signed saturating doubling multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlals_lane_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmlal, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -16947,7 +16947,7 @@ pub fn vqdmlals_lane_s32<const LANE: i32>(a: i64, b: i32, c: int32x2_t) -> i64 {
 }
 #[doc = "Signed saturating doubling multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlals_laneq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmlal, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -16958,7 +16958,7 @@ pub fn vqdmlals_laneq_s32<const LANE: i32>(a: i64, b: i32, c: int32x4_t) -> i64
 }
 #[doc = "Signed saturating doubling multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlalh_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmlal))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -16968,7 +16968,7 @@ pub fn vqdmlalh_s16(a: i32, b: i16, c: i16) -> i32 {
 }
 #[doc = "Signed saturating doubling multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlals_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmlal))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -16978,7 +16978,7 @@ pub fn vqdmlals_s32(a: i64, b: i32, c: i32) -> i64 {
 }
 #[doc = "Signed saturating doubling multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_high_lane_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmlsl2, N = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -16989,7 +16989,7 @@ pub fn vqdmlsl_high_lane_s16<const N: i32>(a: int32x4_t, b: int16x8_t, c: int16x
 }
 #[doc = "Signed saturating doubling multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_high_laneq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmlsl2, N = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -17000,7 +17000,7 @@ pub fn vqdmlsl_high_laneq_s16<const N: i32>(a: int32x4_t, b: int16x8_t, c: int16
 }
 #[doc = "Signed saturating doubling multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_high_lane_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmlsl2, N = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -17011,7 +17011,7 @@ pub fn vqdmlsl_high_lane_s32<const N: i32>(a: int64x2_t, b: int32x4_t, c: int32x
 }
 #[doc = "Signed saturating doubling multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_high_laneq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmlsl2, N = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -17022,7 +17022,7 @@ pub fn vqdmlsl_high_laneq_s32<const N: i32>(a: int64x2_t, b: int32x4_t, c: int32
 }
 #[doc = "Signed saturating doubling multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_high_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmlsl2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -17031,7 +17031,7 @@ pub fn vqdmlsl_high_n_s16(a: int32x4_t, b: int16x8_t, c: i16) -> int32x4_t {
 }
 #[doc = "Signed saturating doubling multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_high_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmlsl2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -17040,7 +17040,7 @@ pub fn vqdmlsl_high_s16(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t {
 }
 #[doc = "Signed saturating doubling multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_high_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmlsl2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -17049,7 +17049,7 @@ pub fn vqdmlsl_high_n_s32(a: int64x2_t, b: int32x4_t, c: i32) -> int64x2_t {
 }
 #[doc = "Signed saturating doubling multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_high_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmlsl2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -17058,7 +17058,7 @@ pub fn vqdmlsl_high_s32(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t {
 }
 #[doc = "Vector widening saturating doubling multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_laneq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmlsl, N = 2))]
 #[rustc_legacy_const_generics(3)]
@@ -17069,7 +17069,7 @@ pub fn vqdmlsl_laneq_s16<const N: i32>(a: int32x4_t, b: int16x4_t, c: int16x8_t)
 }
 #[doc = "Vector widening saturating doubling multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_laneq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmlsl, N = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -17080,7 +17080,7 @@ pub fn vqdmlsl_laneq_s32<const N: i32>(a: int64x2_t, b: int32x2_t, c: int32x4_t)
 }
 #[doc = "Signed saturating doubling multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlslh_lane_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmlsl, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -17091,7 +17091,7 @@ pub fn vqdmlslh_lane_s16<const LANE: i32>(a: i32, b: i16, c: int16x4_t) -> i32 {
 }
 #[doc = "Signed saturating doubling multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlslh_laneq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmlsl, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -17102,7 +17102,7 @@ pub fn vqdmlslh_laneq_s16<const LANE: i32>(a: i32, b: i16, c: int16x8_t) -> i32
 }
 #[doc = "Signed saturating doubling multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsls_lane_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmlsl, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -17113,7 +17113,7 @@ pub fn vqdmlsls_lane_s32<const LANE: i32>(a: i64, b: i32, c: int32x2_t) -> i64 {
 }
 #[doc = "Signed saturating doubling multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsls_laneq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmlsl, LANE = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -17124,7 +17124,7 @@ pub fn vqdmlsls_laneq_s32<const LANE: i32>(a: i64, b: i32, c: int32x4_t) -> i64
 }
 #[doc = "Signed saturating doubling multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlslh_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmlsl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -17134,7 +17134,7 @@ pub fn vqdmlslh_s16(a: i32, b: i16, c: i16) -> i32 {
 }
 #[doc = "Signed saturating doubling multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsls_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmlsl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -17144,7 +17144,7 @@ pub fn vqdmlsls_s32(a: i64, b: i32, c: i32) -> i64 {
 }
 #[doc = "Vector saturating doubling multiply high by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_lane_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmulh, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -17155,7 +17155,7 @@ pub fn vqdmulh_lane_s16<const LANE: i32>(a: int16x4_t, b: int16x4_t) -> int16x4_
 }
 #[doc = "Vector saturating doubling multiply high by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_lane_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmulh, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -17166,7 +17166,7 @@ pub fn vqdmulhq_lane_s16<const LANE: i32>(a: int16x8_t, b: int16x4_t) -> int16x8
 }
 #[doc = "Vector saturating doubling multiply high by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_lane_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmulh, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -17177,7 +17177,7 @@ pub fn vqdmulh_lane_s32<const LANE: i32>(a: int32x2_t, b: int32x2_t) -> int32x2_
 }
 #[doc = "Vector saturating doubling multiply high by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_lane_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmulh, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -17188,7 +17188,7 @@ pub fn vqdmulhq_lane_s32<const LANE: i32>(a: int32x4_t, b: int32x2_t) -> int32x4
 }
 #[doc = "Signed saturating doubling multiply returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhh_lane_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmulh, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -17202,7 +17202,7 @@ pub fn vqdmulhh_lane_s16<const N: i32>(a: i16, b: int16x4_t) -> i16 {
 }
 #[doc = "Signed saturating doubling multiply returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhh_laneq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmulh, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -17216,7 +17216,7 @@ pub fn vqdmulhh_laneq_s16<const N: i32>(a: i16, b: int16x8_t) -> i16 {
 }
 #[doc = "Signed saturating doubling multiply returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhh_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmulh))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -17227,7 +17227,7 @@ pub fn vqdmulhh_s16(a: i16, b: i16) -> i16 {
 }
 #[doc = "Signed saturating doubling multiply returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhs_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmulh))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -17238,7 +17238,7 @@ pub fn vqdmulhs_s32(a: i32, b: i32) -> i32 {
 }
 #[doc = "Signed saturating doubling multiply returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhs_lane_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmulh, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -17252,7 +17252,7 @@ pub fn vqdmulhs_lane_s32<const N: i32>(a: i32, b: int32x2_t) -> i32 {
 }
 #[doc = "Signed saturating doubling multiply returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhs_laneq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmulh, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -17266,7 +17266,7 @@ pub fn vqdmulhs_laneq_s32<const N: i32>(a: i32, b: int32x4_t) -> i32 {
 }
 #[doc = "Signed saturating doubling multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_high_lane_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmull2, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -17281,7 +17281,7 @@ pub fn vqdmull_high_lane_s16<const N: i32>(a: int16x8_t, b: int16x4_t) -> int32x
 }
 #[doc = "Signed saturating doubling multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_high_laneq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmull2, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -17296,7 +17296,7 @@ pub fn vqdmull_high_laneq_s32<const N: i32>(a: int32x4_t, b: int32x4_t) -> int64
 }
 #[doc = "Signed saturating doubling multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_high_lane_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmull2, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -17311,7 +17311,7 @@ pub fn vqdmull_high_lane_s32<const N: i32>(a: int32x4_t, b: int32x2_t) -> int64x
 }
 #[doc = "Signed saturating doubling multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_high_laneq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmull2, N = 4))]
 #[rustc_legacy_const_generics(2)]
@@ -17326,7 +17326,7 @@ pub fn vqdmull_high_laneq_s16<const N: i32>(a: int16x8_t, b: int16x8_t) -> int32
 }
 #[doc = "Signed saturating doubling multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_high_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmull2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -17339,7 +17339,7 @@ pub fn vqdmull_high_n_s16(a: int16x8_t, b: i16) -> int32x4_t {
 }
 #[doc = "Signed saturating doubling multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_high_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmull2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -17352,7 +17352,7 @@ pub fn vqdmull_high_n_s32(a: int32x4_t, b: i32) -> int64x2_t {
 }
 #[doc = "Signed saturating doubling multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_high_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmull2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -17365,7 +17365,7 @@ pub fn vqdmull_high_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t {
 }
 #[doc = "Signed saturating doubling multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_high_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmull2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -17378,7 +17378,7 @@ pub fn vqdmull_high_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t {
 }
 #[doc = "Vector saturating doubling long multiply by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_laneq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmull, N = 4))]
 #[rustc_legacy_const_generics(2)]
@@ -17392,7 +17392,7 @@ pub fn vqdmull_laneq_s16<const N: i32>(a: int16x4_t, b: int16x8_t) -> int32x4_t
 }
 #[doc = "Vector saturating doubling long multiply by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_laneq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmull, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -17406,7 +17406,7 @@ pub fn vqdmull_laneq_s32<const N: i32>(a: int32x2_t, b: int32x4_t) -> int64x2_t
 }
 #[doc = "Signed saturating doubling multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmullh_lane_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmull, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -17420,7 +17420,7 @@ pub fn vqdmullh_lane_s16<const N: i32>(a: i16, b: int16x4_t) -> i32 {
 }
 #[doc = "Signed saturating doubling multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulls_laneq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmull, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -17434,7 +17434,7 @@ pub fn vqdmulls_laneq_s32<const N: i32>(a: i32, b: int32x4_t) -> i64 {
 }
 #[doc = "Signed saturating doubling multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmullh_laneq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmull, N = 4))]
 #[rustc_legacy_const_generics(2)]
@@ -17448,7 +17448,7 @@ pub fn vqdmullh_laneq_s16<const N: i32>(a: i16, b: int16x8_t) -> i32 {
 }
 #[doc = "Signed saturating doubling multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmullh_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmull))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -17459,7 +17459,7 @@ pub fn vqdmullh_s16(a: i16, b: i16) -> i32 {
 }
 #[doc = "Signed saturating doubling multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulls_lane_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmull, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -17473,7 +17473,7 @@ pub fn vqdmulls_lane_s32<const N: i32>(a: i32, b: int32x2_t) -> i64 {
 }
 #[doc = "Signed saturating doubling multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulls_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqdmull))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -17489,7 +17489,7 @@ pub fn vqdmulls_s32(a: i32, b: i32) -> i64 {
 }
 #[doc = "Signed saturating extract narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_high_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqxtn2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -17504,7 +17504,7 @@ pub fn vqmovn_high_s16(a: int8x8_t, b: int16x8_t) -> int8x16_t {
 }
 #[doc = "Signed saturating extract narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_high_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqxtn2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -17513,7 +17513,7 @@ pub fn vqmovn_high_s32(a: int16x4_t, b: int32x4_t) -> int16x8_t {
 }
 #[doc = "Signed saturating extract narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_high_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqxtn2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -17522,7 +17522,7 @@ pub fn vqmovn_high_s64(a: int32x2_t, b: int64x2_t) -> int32x4_t {
 }
 #[doc = "Signed saturating extract narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_high_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(uqxtn2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -17537,7 +17537,7 @@ pub fn vqmovn_high_u16(a: uint8x8_t, b: uint16x8_t) -> uint8x16_t {
 }
 #[doc = "Signed saturating extract narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_high_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(uqxtn2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -17546,7 +17546,7 @@ pub fn vqmovn_high_u32(a: uint16x4_t, b: uint32x4_t) -> uint16x8_t {
 }
 #[doc = "Signed saturating extract narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_high_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(uqxtn2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -17555,7 +17555,7 @@ pub fn vqmovn_high_u64(a: uint32x2_t, b: uint64x2_t) -> uint32x4_t {
 }
 #[doc = "Saturating extract narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovnd_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqxtn))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -17571,7 +17571,7 @@ pub fn vqmovnd_s64(a: i64) -> i32 {
 }
 #[doc = "Saturating extract narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovnd_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(uqxtn))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -17587,7 +17587,7 @@ pub fn vqmovnd_u64(a: u64) -> u32 {
 }
 #[doc = "Saturating extract narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovnh_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqxtn))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -17596,7 +17596,7 @@ pub fn vqmovnh_s16(a: i16) -> i8 {
 }
 #[doc = "Saturating extract narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovns_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqxtn))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -17605,7 +17605,7 @@ pub fn vqmovns_s32(a: i32) -> i16 {
 }
 #[doc = "Saturating extract narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovnh_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(uqxtn))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -17614,7 +17614,7 @@ pub fn vqmovnh_u16(a: u16) -> u8 {
 }
 #[doc = "Saturating extract narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovns_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(uqxtn))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -17623,7 +17623,7 @@ pub fn vqmovns_u32(a: u32) -> u16 {
 }
 #[doc = "Signed saturating extract unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovun_high_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqxtun2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -17638,7 +17638,7 @@ pub fn vqmovun_high_s16(a: uint8x8_t, b: int16x8_t) -> uint8x16_t {
 }
 #[doc = "Signed saturating extract unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovun_high_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqxtun2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -17647,7 +17647,7 @@ pub fn vqmovun_high_s32(a: uint16x4_t, b: int32x4_t) -> uint16x8_t {
 }
 #[doc = "Signed saturating extract unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovun_high_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqxtun2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -17656,7 +17656,7 @@ pub fn vqmovun_high_s64(a: uint32x2_t, b: int64x2_t) -> uint32x4_t {
 }
 #[doc = "Signed saturating extract unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovunh_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqxtun))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -17665,7 +17665,7 @@ pub fn vqmovunh_s16(a: i16) -> u8 {
 }
 #[doc = "Signed saturating extract unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovuns_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqxtun))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -17674,7 +17674,7 @@ pub fn vqmovuns_s32(a: i32) -> u16 {
 }
 #[doc = "Signed saturating extract unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovund_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqxtun))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -17683,7 +17683,7 @@ pub fn vqmovund_s64(a: i64) -> u32 {
 }
 #[doc = "Signed saturating negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqneg_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sqneg))]
@@ -17699,7 +17699,7 @@ pub fn vqneg_s64(a: int64x1_t) -> int64x1_t {
 }
 #[doc = "Signed saturating negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqnegq_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sqneg))]
@@ -17715,7 +17715,7 @@ pub fn vqnegq_s64(a: int64x2_t) -> int64x2_t {
 }
 #[doc = "Signed saturating negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqnegb_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sqneg))]
@@ -17724,7 +17724,7 @@ pub fn vqnegb_s8(a: i8) -> i8 {
 }
 #[doc = "Signed saturating negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqnegh_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sqneg))]
@@ -17733,7 +17733,7 @@ pub fn vqnegh_s16(a: i16) -> i16 {
 }
 #[doc = "Signed saturating negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqnegs_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sqneg))]
@@ -17742,7 +17742,7 @@ pub fn vqnegs_s32(a: i32) -> i32 {
 }
 #[doc = "Signed saturating negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqnegd_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sqneg))]
@@ -17751,7 +17751,7 @@ pub fn vqnegd_s64(a: i64) -> i64 {
 }
 #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlah_lane_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "rdm")]
 #[cfg_attr(test, assert_instr(sqrdmlah, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -17766,7 +17766,7 @@ pub fn vqrdmlah_lane_s16<const LANE: i32>(a: int16x4_t, b: int16x4_t, c: int16x4
 }
 #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlah_lane_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "rdm")]
 #[cfg_attr(test, assert_instr(sqrdmlah, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -17780,7 +17780,7 @@ pub fn vqrdmlah_lane_s32<const LANE: i32>(a: int32x2_t, b: int32x2_t, c: int32x2
 }
 #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlah_laneq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "rdm")]
 #[cfg_attr(test, assert_instr(sqrdmlah, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -17795,7 +17795,7 @@ pub fn vqrdmlah_laneq_s16<const LANE: i32>(a: int16x4_t, b: int16x4_t, c: int16x
 }
 #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlah_laneq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "rdm")]
 #[cfg_attr(test, assert_instr(sqrdmlah, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -17809,7 +17809,7 @@ pub fn vqrdmlah_laneq_s32<const LANE: i32>(a: int32x2_t, b: int32x2_t, c: int32x
 }
 #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahq_lane_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "rdm")]
 #[cfg_attr(test, assert_instr(sqrdmlah, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -17836,7 +17836,7 @@ pub fn vqrdmlahq_lane_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t, c: int16x
 }
 #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahq_lane_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "rdm")]
 #[cfg_attr(test, assert_instr(sqrdmlah, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -17851,7 +17851,7 @@ pub fn vqrdmlahq_lane_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t, c: int32x
 }
 #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahq_laneq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "rdm")]
 #[cfg_attr(test, assert_instr(sqrdmlah, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -17878,7 +17878,7 @@ pub fn vqrdmlahq_laneq_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t, c: int16
 }
 #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahq_laneq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "rdm")]
 #[cfg_attr(test, assert_instr(sqrdmlah, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -17893,7 +17893,7 @@ pub fn vqrdmlahq_laneq_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t, c: int32
 }
 #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlah_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "rdm")]
 #[cfg_attr(test, assert_instr(sqrdmlah))]
 #[stable(feature = "rdm_intrinsics", since = "1.62.0")]
@@ -17909,7 +17909,7 @@ pub fn vqrdmlah_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t {
 }
 #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "rdm")]
 #[cfg_attr(test, assert_instr(sqrdmlah))]
 #[stable(feature = "rdm_intrinsics", since = "1.62.0")]
@@ -17925,7 +17925,7 @@ pub fn vqrdmlahq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t {
 }
 #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlah_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "rdm")]
 #[cfg_attr(test, assert_instr(sqrdmlah))]
 #[stable(feature = "rdm_intrinsics", since = "1.62.0")]
@@ -17941,7 +17941,7 @@ pub fn vqrdmlah_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t {
 }
 #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "rdm")]
 #[cfg_attr(test, assert_instr(sqrdmlah))]
 #[stable(feature = "rdm_intrinsics", since = "1.62.0")]
@@ -17957,7 +17957,7 @@ pub fn vqrdmlahq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t {
 }
 #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahh_lane_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "rdm")]
 #[cfg_attr(test, assert_instr(sqrdmlah, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -17968,7 +17968,7 @@ pub fn vqrdmlahh_lane_s16<const LANE: i32>(a: i16, b: i16, c: int16x4_t) -> i16
 }
 #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahh_laneq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "rdm")]
 #[cfg_attr(test, assert_instr(sqrdmlah, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -17979,7 +17979,7 @@ pub fn vqrdmlahh_laneq_s16<const LANE: i32>(a: i16, b: i16, c: int16x8_t) -> i16
 }
 #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahs_lane_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "rdm")]
 #[cfg_attr(test, assert_instr(sqrdmlah, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -17990,7 +17990,7 @@ pub fn vqrdmlahs_lane_s32<const LANE: i32>(a: i32, b: i32, c: int32x2_t) -> i32
 }
 #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahs_laneq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "rdm")]
 #[cfg_attr(test, assert_instr(sqrdmlah, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -18001,7 +18001,7 @@ pub fn vqrdmlahs_laneq_s32<const LANE: i32>(a: i32, b: i32, c: int32x4_t) -> i32
 }
 #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahh_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "rdm")]
 #[cfg_attr(test, assert_instr(sqrdmlah))]
 #[stable(feature = "rdm_intrinsics", since = "1.62.0")]
@@ -18013,7 +18013,7 @@ pub fn vqrdmlahh_s16(a: i16, b: i16, c: i16) -> i16 {
 }
 #[doc = "Signed saturating rounding doubling multiply accumulate returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahs_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "rdm")]
 #[cfg_attr(test, assert_instr(sqrdmlah))]
 #[stable(feature = "rdm_intrinsics", since = "1.62.0")]
@@ -18025,7 +18025,7 @@ pub fn vqrdmlahs_s32(a: i32, b: i32, c: i32) -> i32 {
 }
 #[doc = "Signed saturating rounding doubling multiply subtract returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlsh_lane_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "rdm")]
 #[cfg_attr(test, assert_instr(sqrdmlsh, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -18040,7 +18040,7 @@ pub fn vqrdmlsh_lane_s16<const LANE: i32>(a: int16x4_t, b: int16x4_t, c: int16x4
 }
 #[doc = "Signed saturating rounding doubling multiply subtract returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlsh_lane_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "rdm")]
 #[cfg_attr(test, assert_instr(sqrdmlsh, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -18054,7 +18054,7 @@ pub fn vqrdmlsh_lane_s32<const LANE: i32>(a: int32x2_t, b: int32x2_t, c: int32x2
 }
 #[doc = "Signed saturating rounding doubling multiply subtract returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlsh_laneq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "rdm")]
 #[cfg_attr(test, assert_instr(sqrdmlsh, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -18069,7 +18069,7 @@ pub fn vqrdmlsh_laneq_s16<const LANE: i32>(a: int16x4_t, b: int16x4_t, c: int16x
 }
 #[doc = "Signed saturating rounding doubling multiply subtract returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlsh_laneq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "rdm")]
 #[cfg_attr(test, assert_instr(sqrdmlsh, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -18083,7 +18083,7 @@ pub fn vqrdmlsh_laneq_s32<const LANE: i32>(a: int32x2_t, b: int32x2_t, c: int32x
 }
 #[doc = "Signed saturating rounding doubling multiply subtract returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshq_lane_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "rdm")]
 #[cfg_attr(test, assert_instr(sqrdmlsh, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -18110,7 +18110,7 @@ pub fn vqrdmlshq_lane_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t, c: int16x
 }
 #[doc = "Signed saturating rounding doubling multiply subtract returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshq_lane_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "rdm")]
 #[cfg_attr(test, assert_instr(sqrdmlsh, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -18125,7 +18125,7 @@ pub fn vqrdmlshq_lane_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t, c: int32x
 }
 #[doc = "Signed saturating rounding doubling multiply subtract returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshq_laneq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "rdm")]
 #[cfg_attr(test, assert_instr(sqrdmlsh, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -18152,7 +18152,7 @@ pub fn vqrdmlshq_laneq_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t, c: int16
 }
 #[doc = "Signed saturating rounding doubling multiply subtract returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshq_laneq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "rdm")]
 #[cfg_attr(test, assert_instr(sqrdmlsh, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -18167,7 +18167,7 @@ pub fn vqrdmlshq_laneq_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t, c: int32
 }
 #[doc = "Signed saturating rounding doubling multiply subtract returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlsh_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "rdm")]
 #[cfg_attr(test, assert_instr(sqrdmlsh))]
 #[stable(feature = "rdm_intrinsics", since = "1.62.0")]
@@ -18183,7 +18183,7 @@ pub fn vqrdmlsh_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t {
 }
 #[doc = "Signed saturating rounding doubling multiply subtract returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "rdm")]
 #[cfg_attr(test, assert_instr(sqrdmlsh))]
 #[stable(feature = "rdm_intrinsics", since = "1.62.0")]
@@ -18199,7 +18199,7 @@ pub fn vqrdmlshq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t {
 }
 #[doc = "Signed saturating rounding doubling multiply subtract returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlsh_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "rdm")]
 #[cfg_attr(test, assert_instr(sqrdmlsh))]
 #[stable(feature = "rdm_intrinsics", since = "1.62.0")]
@@ -18215,7 +18215,7 @@ pub fn vqrdmlsh_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t {
 }
 #[doc = "Signed saturating rounding doubling multiply subtract returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "rdm")]
 #[cfg_attr(test, assert_instr(sqrdmlsh))]
 #[stable(feature = "rdm_intrinsics", since = "1.62.0")]
@@ -18231,7 +18231,7 @@ pub fn vqrdmlshq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t {
 }
 #[doc = "Signed saturating rounding doubling multiply subtract returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshh_lane_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "rdm")]
 #[cfg_attr(test, assert_instr(sqrdmlsh, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -18242,7 +18242,7 @@ pub fn vqrdmlshh_lane_s16<const LANE: i32>(a: i16, b: i16, c: int16x4_t) -> i16
 }
 #[doc = "Signed saturating rounding doubling multiply subtract returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshh_laneq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "rdm")]
 #[cfg_attr(test, assert_instr(sqrdmlsh, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -18253,7 +18253,7 @@ pub fn vqrdmlshh_laneq_s16<const LANE: i32>(a: i16, b: i16, c: int16x8_t) -> i16
 }
 #[doc = "Signed saturating rounding doubling multiply subtract returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshs_lane_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "rdm")]
 #[cfg_attr(test, assert_instr(sqrdmlsh, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -18264,7 +18264,7 @@ pub fn vqrdmlshs_lane_s32<const LANE: i32>(a: i32, b: i32, c: int32x2_t) -> i32
 }
 #[doc = "Signed saturating rounding doubling multiply subtract returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshs_laneq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "rdm")]
 #[cfg_attr(test, assert_instr(sqrdmlsh, LANE = 1))]
 #[rustc_legacy_const_generics(3)]
@@ -18275,7 +18275,7 @@ pub fn vqrdmlshs_laneq_s32<const LANE: i32>(a: i32, b: i32, c: int32x4_t) -> i32
 }
 #[doc = "Signed saturating rounding doubling multiply subtract returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshh_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "rdm")]
 #[cfg_attr(test, assert_instr(sqrdmlsh))]
 #[stable(feature = "rdm_intrinsics", since = "1.62.0")]
@@ -18287,7 +18287,7 @@ pub fn vqrdmlshh_s16(a: i16, b: i16, c: i16) -> i16 {
 }
 #[doc = "Signed saturating rounding doubling multiply subtract returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshs_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "rdm")]
 #[cfg_attr(test, assert_instr(sqrdmlsh))]
 #[stable(feature = "rdm_intrinsics", since = "1.62.0")]
@@ -18299,7 +18299,7 @@ pub fn vqrdmlshs_s32(a: i32, b: i32, c: i32) -> i32 {
 }
 #[doc = "Signed saturating rounding doubling multiply returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhh_lane_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqrdmulh, LANE = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -18310,7 +18310,7 @@ pub fn vqrdmulhh_lane_s16<const LANE: i32>(a: i16, b: int16x4_t) -> i16 {
 }
 #[doc = "Signed saturating rounding doubling multiply returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhh_laneq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqrdmulh, LANE = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -18321,7 +18321,7 @@ pub fn vqrdmulhh_laneq_s16<const LANE: i32>(a: i16, b: int16x8_t) -> i16 {
 }
 #[doc = "Signed saturating rounding doubling multiply returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhs_lane_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqrdmulh, LANE = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -18332,7 +18332,7 @@ pub fn vqrdmulhs_lane_s32<const LANE: i32>(a: i32, b: int32x2_t) -> i32 {
 }
 #[doc = "Signed saturating rounding doubling multiply returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhs_laneq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqrdmulh, LANE = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -18343,7 +18343,7 @@ pub fn vqrdmulhs_laneq_s32<const LANE: i32>(a: i32, b: int32x4_t) -> i32 {
 }
 #[doc = "Signed saturating rounding doubling multiply returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhh_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqrdmulh))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -18352,7 +18352,7 @@ pub fn vqrdmulhh_s16(a: i16, b: i16) -> i16 {
 }
 #[doc = "Signed saturating rounding doubling multiply returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhs_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqrdmulh))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -18361,7 +18361,7 @@ pub fn vqrdmulhs_s32(a: i32, b: i32) -> i32 {
 }
 #[doc = "Signed saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlb_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqrshl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -18372,7 +18372,7 @@ pub fn vqrshlb_s8(a: i8, b: i8) -> i8 {
 }
 #[doc = "Signed saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlh_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqrshl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -18383,7 +18383,7 @@ pub fn vqrshlh_s16(a: i16, b: i16) -> i16 {
 }
 #[doc = "Unsigned signed saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlb_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(uqrshl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -18394,7 +18394,7 @@ pub fn vqrshlb_u8(a: u8, b: i8) -> u8 {
 }
 #[doc = "Unsigned signed saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlh_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(uqrshl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -18405,7 +18405,7 @@ pub fn vqrshlh_u16(a: u16, b: i16) -> u16 {
 }
 #[doc = "Signed saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshld_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqrshl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -18421,7 +18421,7 @@ pub fn vqrshld_s64(a: i64, b: i64) -> i64 {
 }
 #[doc = "Signed saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshls_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqrshl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -18437,7 +18437,7 @@ pub fn vqrshls_s32(a: i32, b: i32) -> i32 {
 }
 #[doc = "Unsigned signed saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshls_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(uqrshl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -18453,7 +18453,7 @@ pub fn vqrshls_u32(a: u32, b: i32) -> u32 {
 }
 #[doc = "Unsigned signed saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshld_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(uqrshl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -18469,7 +18469,7 @@ pub fn vqrshld_u64(a: u64, b: i64) -> u64 {
 }
 #[doc = "Signed saturating rounded shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_high_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqrshrn2, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -18486,7 +18486,7 @@ pub fn vqrshrn_high_n_s16<const N: i32>(a: int8x8_t, b: int16x8_t) -> int8x16_t
 }
 #[doc = "Signed saturating rounded shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_high_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqrshrn2, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -18497,7 +18497,7 @@ pub fn vqrshrn_high_n_s32<const N: i32>(a: int16x4_t, b: int32x4_t) -> int16x8_t
 }
 #[doc = "Signed saturating rounded shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_high_n_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqrshrn2, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -18508,7 +18508,7 @@ pub fn vqrshrn_high_n_s64<const N: i32>(a: int32x2_t, b: int64x2_t) -> int32x4_t
 }
 #[doc = "Unsigned saturating rounded shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_high_n_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(uqrshrn2, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -18525,7 +18525,7 @@ pub fn vqrshrn_high_n_u16<const N: i32>(a: uint8x8_t, b: uint16x8_t) -> uint8x16
 }
 #[doc = "Unsigned saturating rounded shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_high_n_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(uqrshrn2, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -18536,7 +18536,7 @@ pub fn vqrshrn_high_n_u32<const N: i32>(a: uint16x4_t, b: uint32x4_t) -> uint16x
 }
 #[doc = "Unsigned saturating rounded shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_high_n_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(uqrshrn2, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -18547,7 +18547,7 @@ pub fn vqrshrn_high_n_u64<const N: i32>(a: uint32x2_t, b: uint64x2_t) -> uint32x
 }
 #[doc = "Unsigned saturating rounded shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrnd_n_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(uqrshrn, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -18559,7 +18559,7 @@ pub fn vqrshrnd_n_u64<const N: i32>(a: u64) -> u32 {
 }
 #[doc = "Unsigned saturating rounded shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrnh_n_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(uqrshrn, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -18571,7 +18571,7 @@ pub fn vqrshrnh_n_u16<const N: i32>(a: u16) -> u8 {
 }
 #[doc = "Unsigned saturating rounded shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrns_n_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(uqrshrn, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -18583,7 +18583,7 @@ pub fn vqrshrns_n_u32<const N: i32>(a: u32) -> u16 {
 }
 #[doc = "Signed saturating rounded shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrnh_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqrshrn, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -18595,7 +18595,7 @@ pub fn vqrshrnh_n_s16<const N: i32>(a: i16) -> i8 {
 }
 #[doc = "Signed saturating rounded shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrns_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqrshrn, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -18607,7 +18607,7 @@ pub fn vqrshrns_n_s32<const N: i32>(a: i32) -> i16 {
 }
 #[doc = "Signed saturating rounded shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrnd_n_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqrshrn, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -18619,7 +18619,7 @@ pub fn vqrshrnd_n_s64<const N: i32>(a: i64) -> i32 {
 }
 #[doc = "Signed saturating rounded shift right unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_high_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqrshrun2, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -18636,7 +18636,7 @@ pub fn vqrshrun_high_n_s16<const N: i32>(a: uint8x8_t, b: int16x8_t) -> uint8x16
 }
 #[doc = "Signed saturating rounded shift right unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_high_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqrshrun2, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -18647,7 +18647,7 @@ pub fn vqrshrun_high_n_s32<const N: i32>(a: uint16x4_t, b: int32x4_t) -> uint16x
 }
 #[doc = "Signed saturating rounded shift right unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_high_n_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqrshrun2, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -18658,7 +18658,7 @@ pub fn vqrshrun_high_n_s64<const N: i32>(a: uint32x2_t, b: int64x2_t) -> uint32x
 }
 #[doc = "Signed saturating rounded shift right unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrund_n_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqrshrun, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -18670,7 +18670,7 @@ pub fn vqrshrund_n_s64<const N: i32>(a: i64) -> u32 {
 }
 #[doc = "Signed saturating rounded shift right unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrunh_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqrshrun, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -18682,7 +18682,7 @@ pub fn vqrshrunh_n_s16<const N: i32>(a: i16) -> u8 {
 }
 #[doc = "Signed saturating rounded shift right unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshruns_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqrshrun, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -18694,7 +18694,7 @@ pub fn vqrshruns_n_s32<const N: i32>(a: i32) -> u16 {
 }
 #[doc = "Signed saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlb_n_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqshl, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -18705,7 +18705,7 @@ pub fn vqshlb_n_s8<const N: i32>(a: i8) -> i8 {
 }
 #[doc = "Signed saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshld_n_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqshl, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -18716,7 +18716,7 @@ pub fn vqshld_n_s64<const N: i32>(a: i64) -> i64 {
 }
 #[doc = "Signed saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlh_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqshl, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -18727,7 +18727,7 @@ pub fn vqshlh_n_s16<const N: i32>(a: i16) -> i16 {
 }
 #[doc = "Signed saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshls_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqshl, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -18738,7 +18738,7 @@ pub fn vqshls_n_s32<const N: i32>(a: i32) -> i32 {
 }
 #[doc = "Unsigned saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlb_n_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(uqshl, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -18749,7 +18749,7 @@ pub fn vqshlb_n_u8<const N: i32>(a: u8) -> u8 {
 }
 #[doc = "Unsigned saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshld_n_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(uqshl, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -18760,7 +18760,7 @@ pub fn vqshld_n_u64<const N: i32>(a: u64) -> u64 {
 }
 #[doc = "Unsigned saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlh_n_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(uqshl, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -18771,7 +18771,7 @@ pub fn vqshlh_n_u16<const N: i32>(a: u16) -> u16 {
 }
 #[doc = "Unsigned saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshls_n_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(uqshl, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -18782,7 +18782,7 @@ pub fn vqshls_n_u32<const N: i32>(a: u32) -> u32 {
 }
 #[doc = "Signed saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlb_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqshl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -18792,7 +18792,7 @@ pub fn vqshlb_s8(a: i8, b: i8) -> i8 {
 }
 #[doc = "Signed saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlh_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqshl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -18802,7 +18802,7 @@ pub fn vqshlh_s16(a: i16, b: i16) -> i16 {
 }
 #[doc = "Signed saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshls_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqshl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -18812,7 +18812,7 @@ pub fn vqshls_s32(a: i32, b: i32) -> i32 {
 }
 #[doc = "Unsigned saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlb_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(uqshl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -18822,7 +18822,7 @@ pub fn vqshlb_u8(a: u8, b: i8) -> u8 {
 }
 #[doc = "Unsigned saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlh_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(uqshl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -18832,7 +18832,7 @@ pub fn vqshlh_u16(a: u16, b: i16) -> u16 {
 }
 #[doc = "Unsigned saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshls_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(uqshl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -18842,7 +18842,7 @@ pub fn vqshls_u32(a: u32, b: i32) -> u32 {
 }
 #[doc = "Signed saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshld_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqshl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -18858,7 +18858,7 @@ pub fn vqshld_s64(a: i64, b: i64) -> i64 {
 }
 #[doc = "Unsigned saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshld_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(uqshl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -18874,7 +18874,7 @@ pub fn vqshld_u64(a: u64, b: i64) -> u64 {
 }
 #[doc = "Signed saturating shift left unsigned"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlub_n_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqshlu, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -18885,7 +18885,7 @@ pub fn vqshlub_n_s8<const N: i32>(a: i8) -> u8 {
 }
 #[doc = "Signed saturating shift left unsigned"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlud_n_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqshlu, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -18896,7 +18896,7 @@ pub fn vqshlud_n_s64<const N: i32>(a: i64) -> u64 {
 }
 #[doc = "Signed saturating shift left unsigned"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluh_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqshlu, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -18907,7 +18907,7 @@ pub fn vqshluh_n_s16<const N: i32>(a: i16) -> u16 {
 }
 #[doc = "Signed saturating shift left unsigned"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlus_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqshlu, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -18918,7 +18918,7 @@ pub fn vqshlus_n_s32<const N: i32>(a: i32) -> u32 {
 }
 #[doc = "Signed saturating shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_high_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqshrn2, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -18935,7 +18935,7 @@ pub fn vqshrn_high_n_s16<const N: i32>(a: int8x8_t, b: int16x8_t) -> int8x16_t {
 }
 #[doc = "Signed saturating shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_high_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqshrn2, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -18946,7 +18946,7 @@ pub fn vqshrn_high_n_s32<const N: i32>(a: int16x4_t, b: int32x4_t) -> int16x8_t
 }
 #[doc = "Signed saturating shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_high_n_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqshrn2, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -18957,7 +18957,7 @@ pub fn vqshrn_high_n_s64<const N: i32>(a: int32x2_t, b: int64x2_t) -> int32x4_t
 }
 #[doc = "Unsigned saturating shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_high_n_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(uqshrn2, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -18974,7 +18974,7 @@ pub fn vqshrn_high_n_u16<const N: i32>(a: uint8x8_t, b: uint16x8_t) -> uint8x16_
 }
 #[doc = "Unsigned saturating shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_high_n_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(uqshrn2, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -18985,7 +18985,7 @@ pub fn vqshrn_high_n_u32<const N: i32>(a: uint16x4_t, b: uint32x4_t) -> uint16x8
 }
 #[doc = "Unsigned saturating shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_high_n_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(uqshrn2, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -18996,7 +18996,7 @@ pub fn vqshrn_high_n_u64<const N: i32>(a: uint32x2_t, b: uint64x2_t) -> uint32x4
 }
 #[doc = "Signed saturating shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrnd_n_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqshrn, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -19014,7 +19014,7 @@ pub fn vqshrnd_n_s64<const N: i32>(a: i64) -> i32 {
 }
 #[doc = "Unsigned saturating shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrnd_n_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(uqshrn, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -19032,7 +19032,7 @@ pub fn vqshrnd_n_u64<const N: i32>(a: u64) -> u32 {
 }
 #[doc = "Signed saturating shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrnh_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqshrn, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -19043,7 +19043,7 @@ pub fn vqshrnh_n_s16<const N: i32>(a: i16) -> i8 {
 }
 #[doc = "Signed saturating shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrns_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqshrn, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -19054,7 +19054,7 @@ pub fn vqshrns_n_s32<const N: i32>(a: i32) -> i16 {
 }
 #[doc = "Unsigned saturating shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrnh_n_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(uqshrn, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -19065,7 +19065,7 @@ pub fn vqshrnh_n_u16<const N: i32>(a: u16) -> u8 {
 }
 #[doc = "Unsigned saturating shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrns_n_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(uqshrn, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -19076,7 +19076,7 @@ pub fn vqshrns_n_u32<const N: i32>(a: u32) -> u16 {
 }
 #[doc = "Signed saturating shift right unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_high_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqshrun2, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -19093,7 +19093,7 @@ pub fn vqshrun_high_n_s16<const N: i32>(a: uint8x8_t, b: int16x8_t) -> uint8x16_
 }
 #[doc = "Signed saturating shift right unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_high_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqshrun2, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -19104,7 +19104,7 @@ pub fn vqshrun_high_n_s32<const N: i32>(a: uint16x4_t, b: int32x4_t) -> uint16x8
 }
 #[doc = "Signed saturating shift right unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_high_n_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqshrun2, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -19115,7 +19115,7 @@ pub fn vqshrun_high_n_s64<const N: i32>(a: uint32x2_t, b: int64x2_t) -> uint32x4
 }
 #[doc = "Signed saturating shift right unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrund_n_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqshrun, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -19126,7 +19126,7 @@ pub fn vqshrund_n_s64<const N: i32>(a: i64) -> u32 {
 }
 #[doc = "Signed saturating shift right unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrunh_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqshrun, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -19137,7 +19137,7 @@ pub fn vqshrunh_n_s16<const N: i32>(a: i16) -> u8 {
 }
 #[doc = "Signed saturating shift right unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshruns_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sqshrun, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -19148,7 +19148,7 @@ pub fn vqshruns_n_s32<const N: i32>(a: i32) -> u16 {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubb_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sqsub))]
@@ -19159,7 +19159,7 @@ pub fn vqsubb_s8(a: i8, b: i8) -> i8 {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubh_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sqsub))]
@@ -19170,7 +19170,7 @@ pub fn vqsubh_s16(a: i16, b: i16) -> i16 {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubb_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(uqsub))]
@@ -19181,7 +19181,7 @@ pub fn vqsubb_u8(a: u8, b: u8) -> u8 {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubh_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(uqsub))]
@@ -19192,7 +19192,7 @@ pub fn vqsubh_u16(a: u16, b: u16) -> u16 {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubs_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sqsub))]
@@ -19208,7 +19208,7 @@ pub fn vqsubs_s32(a: i32, b: i32) -> i32 {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubd_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sqsub))]
@@ -19224,7 +19224,7 @@ pub fn vqsubd_s64(a: i64, b: i64) -> i64 {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubs_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(uqsub))]
@@ -19240,7 +19240,7 @@ pub fn vqsubs_u32(a: u32, b: u32) -> u32 {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubd_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(uqsub))]
@@ -19256,7 +19256,7 @@ pub fn vqsubd_u64(a: u64, b: u64) -> u64 {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl1)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19272,7 +19272,7 @@ fn vqtbl1(a: int8x16_t, b: uint8x8_t) -> int8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl1q)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19288,7 +19288,7 @@ fn vqtbl1q(a: int8x16_t, b: uint8x16_t) -> int8x16_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl1_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19297,7 +19297,7 @@ pub fn vqtbl1_s8(a: int8x16_t, b: uint8x8_t) -> int8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl1q_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19306,7 +19306,7 @@ pub fn vqtbl1q_s8(a: int8x16_t, b: uint8x16_t) -> int8x16_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl1_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19315,7 +19315,7 @@ pub fn vqtbl1_u8(a: uint8x16_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl1q_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19324,7 +19324,7 @@ pub fn vqtbl1q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl1_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19333,7 +19333,7 @@ pub fn vqtbl1_p8(a: poly8x16_t, b: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl1q_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19342,7 +19342,7 @@ pub fn vqtbl1q_p8(a: poly8x16_t, b: uint8x16_t) -> poly8x16_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl2)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19358,7 +19358,7 @@ fn vqtbl2(a: int8x16_t, b: int8x16_t, c: uint8x8_t) -> int8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl2q)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19374,7 +19374,7 @@ fn vqtbl2q(a: int8x16_t, b: int8x16_t, c: uint8x16_t) -> int8x16_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl2_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19383,7 +19383,7 @@ pub fn vqtbl2_s8(a: int8x16x2_t, b: uint8x8_t) -> int8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl2q_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19392,7 +19392,7 @@ pub fn vqtbl2q_s8(a: int8x16x2_t, b: uint8x16_t) -> int8x16_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl2_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
@@ -19402,7 +19402,7 @@ pub fn vqtbl2_u8(a: uint8x16x2_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl2_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
@@ -19431,7 +19431,7 @@ pub fn vqtbl2_u8(a: uint8x16x2_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl2q_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
@@ -19441,7 +19441,7 @@ pub fn vqtbl2q_u8(a: uint8x16x2_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl2q_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
@@ -19475,7 +19475,7 @@ pub fn vqtbl2q_u8(a: uint8x16x2_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl2_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
@@ -19485,7 +19485,7 @@ pub fn vqtbl2_p8(a: poly8x16x2_t, b: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl2_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
@@ -19514,7 +19514,7 @@ pub fn vqtbl2_p8(a: poly8x16x2_t, b: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl2q_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
@@ -19524,7 +19524,7 @@ pub fn vqtbl2q_p8(a: poly8x16x2_t, b: uint8x16_t) -> poly8x16_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl2q_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
@@ -19558,7 +19558,7 @@ pub fn vqtbl2q_p8(a: poly8x16x2_t, b: uint8x16_t) -> poly8x16_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19574,7 +19574,7 @@ fn vqtbl3(a: int8x16_t, b: int8x16_t, c: int8x16_t, d: uint8x8_t) -> int8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3q)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19590,7 +19590,7 @@ fn vqtbl3q(a: int8x16_t, b: int8x16_t, c: int8x16_t, d: uint8x16_t) -> int8x16_t
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19599,7 +19599,7 @@ pub fn vqtbl3_s8(a: int8x16x3_t, b: uint8x8_t) -> int8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3q_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19608,7 +19608,7 @@ pub fn vqtbl3q_s8(a: int8x16x3_t, b: uint8x16_t) -> int8x16_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
@@ -19618,7 +19618,7 @@ pub fn vqtbl3_u8(a: uint8x16x3_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
@@ -19655,7 +19655,7 @@ pub fn vqtbl3_u8(a: uint8x16x3_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3q_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
@@ -19665,7 +19665,7 @@ pub fn vqtbl3q_u8(a: uint8x16x3_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3q_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
@@ -19707,7 +19707,7 @@ pub fn vqtbl3q_u8(a: uint8x16x3_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
@@ -19717,7 +19717,7 @@ pub fn vqtbl3_p8(a: poly8x16x3_t, b: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
@@ -19754,7 +19754,7 @@ pub fn vqtbl3_p8(a: poly8x16x3_t, b: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3q_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
@@ -19764,7 +19764,7 @@ pub fn vqtbl3q_p8(a: poly8x16x3_t, b: uint8x16_t) -> poly8x16_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl3q_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
@@ -19806,7 +19806,7 @@ pub fn vqtbl3q_p8(a: poly8x16x3_t, b: uint8x16_t) -> poly8x16_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19828,7 +19828,7 @@ fn vqtbl4(a: int8x16_t, b: int8x16_t, c: int8x16_t, d: int8x16_t, e: uint8x8_t)
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4q)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19850,7 +19850,7 @@ fn vqtbl4q(a: int8x16_t, b: int8x16_t, c: int8x16_t, d: int8x16_t, e: uint8x16_t
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19859,7 +19859,7 @@ pub fn vqtbl4_s8(a: int8x16x4_t, b: uint8x8_t) -> int8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4q_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -19868,7 +19868,7 @@ pub fn vqtbl4q_s8(a: int8x16x4_t, b: uint8x16_t) -> int8x16_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
@@ -19886,7 +19886,7 @@ pub fn vqtbl4_u8(a: uint8x16x4_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
@@ -19935,7 +19935,7 @@ pub fn vqtbl4_u8(a: uint8x16x4_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4q_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
@@ -19953,7 +19953,7 @@ pub fn vqtbl4q_u8(a: uint8x16x4_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4q_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
@@ -20007,7 +20007,7 @@ pub fn vqtbl4q_u8(a: uint8x16x4_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
@@ -20025,7 +20025,7 @@ pub fn vqtbl4_p8(a: poly8x16x4_t, b: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
@@ -20074,7 +20074,7 @@ pub fn vqtbl4_p8(a: poly8x16x4_t, b: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4q_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
@@ -20092,7 +20092,7 @@ pub fn vqtbl4q_p8(a: poly8x16x4_t, b: uint8x16_t) -> poly8x16_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbl4q_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
@@ -20146,7 +20146,7 @@ pub fn vqtbl4q_p8(a: poly8x16x4_t, b: uint8x16_t) -> poly8x16_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx1)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20162,7 +20162,7 @@ fn vqtbx1(a: int8x8_t, b: int8x16_t, c: uint8x8_t) -> int8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx1q)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20178,7 +20178,7 @@ fn vqtbx1q(a: int8x16_t, b: int8x16_t, c: uint8x16_t) -> int8x16_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx1_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20187,7 +20187,7 @@ pub fn vqtbx1_s8(a: int8x8_t, b: int8x16_t, c: uint8x8_t) -> int8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx1q_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20196,7 +20196,7 @@ pub fn vqtbx1q_s8(a: int8x16_t, b: int8x16_t, c: uint8x16_t) -> int8x16_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx1_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20205,7 +20205,7 @@ pub fn vqtbx1_u8(a: uint8x8_t, b: uint8x16_t, c: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx1q_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20214,7 +20214,7 @@ pub fn vqtbx1q_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx1_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20223,7 +20223,7 @@ pub fn vqtbx1_p8(a: poly8x8_t, b: poly8x16_t, c: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx1q_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20232,7 +20232,7 @@ pub fn vqtbx1q_p8(a: poly8x16_t, b: poly8x16_t, c: uint8x16_t) -> poly8x16_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20248,7 +20248,7 @@ fn vqtbx2(a: int8x8_t, b: int8x16_t, c: int8x16_t, d: uint8x8_t) -> int8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2q)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20264,7 +20264,7 @@ fn vqtbx2q(a: int8x16_t, b: int8x16_t, c: int8x16_t, d: uint8x16_t) -> int8x16_t
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20273,7 +20273,7 @@ pub fn vqtbx2_s8(a: int8x8_t, b: int8x16x2_t, c: uint8x8_t) -> int8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2q_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20282,7 +20282,7 @@ pub fn vqtbx2q_s8(a: int8x16_t, b: int8x16x2_t, c: uint8x16_t) -> int8x16_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
@@ -20292,7 +20292,7 @@ pub fn vqtbx2_u8(a: uint8x8_t, b: uint8x16x2_t, c: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
@@ -20322,7 +20322,7 @@ pub fn vqtbx2_u8(a: uint8x8_t, b: uint8x16x2_t, c: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2q_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
@@ -20332,7 +20332,7 @@ pub fn vqtbx2q_u8(a: uint8x16_t, b: uint8x16x2_t, c: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2q_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
@@ -20369,7 +20369,7 @@ pub fn vqtbx2q_u8(a: uint8x16_t, b: uint8x16x2_t, c: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
@@ -20379,7 +20379,7 @@ pub fn vqtbx2_p8(a: poly8x8_t, b: poly8x16x2_t, c: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
@@ -20409,7 +20409,7 @@ pub fn vqtbx2_p8(a: poly8x8_t, b: poly8x16x2_t, c: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2q_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
@@ -20419,7 +20419,7 @@ pub fn vqtbx2q_p8(a: poly8x16_t, b: poly8x16x2_t, c: uint8x16_t) -> poly8x16_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx2q_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
@@ -20456,7 +20456,7 @@ pub fn vqtbx2q_p8(a: poly8x16_t, b: poly8x16x2_t, c: uint8x16_t) -> poly8x16_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20473,7 +20473,7 @@ fn vqtbx3(a: int8x8_t, b: int8x16_t, c: int8x16_t, d: int8x16_t, e: uint8x8_t) -
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3q)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20495,7 +20495,7 @@ fn vqtbx3q(a: int8x16_t, b: int8x16_t, c: int8x16_t, d: int8x16_t, e: uint8x16_t
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20504,7 +20504,7 @@ pub fn vqtbx3_s8(a: int8x8_t, b: int8x16x3_t, c: uint8x8_t) -> int8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3q_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20513,7 +20513,7 @@ pub fn vqtbx3q_s8(a: int8x16_t, b: int8x16x3_t, c: uint8x16_t) -> int8x16_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
@@ -20531,7 +20531,7 @@ pub fn vqtbx3_u8(a: uint8x8_t, b: uint8x16x3_t, c: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
@@ -20574,7 +20574,7 @@ pub fn vqtbx3_u8(a: uint8x8_t, b: uint8x16x3_t, c: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3q_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
@@ -20592,7 +20592,7 @@ pub fn vqtbx3q_u8(a: uint8x16_t, b: uint8x16x3_t, c: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3q_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
@@ -20641,7 +20641,7 @@ pub fn vqtbx3q_u8(a: uint8x16_t, b: uint8x16x3_t, c: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
@@ -20659,7 +20659,7 @@ pub fn vqtbx3_p8(a: poly8x8_t, b: poly8x16x3_t, c: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
@@ -20702,7 +20702,7 @@ pub fn vqtbx3_p8(a: poly8x8_t, b: poly8x16x3_t, c: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3q_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
@@ -20720,7 +20720,7 @@ pub fn vqtbx3q_p8(a: poly8x16_t, b: poly8x16x3_t, c: uint8x16_t) -> poly8x16_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx3q_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
@@ -20769,7 +20769,7 @@ pub fn vqtbx3q_p8(a: poly8x16_t, b: poly8x16x3_t, c: uint8x16_t) -> poly8x16_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20799,7 +20799,7 @@ fn vqtbx4(
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4q)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20829,7 +20829,7 @@ fn vqtbx4q(
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20838,7 +20838,7 @@ pub fn vqtbx4_s8(a: int8x8_t, b: int8x16x4_t, c: uint8x8_t) -> int8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4q_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20847,7 +20847,7 @@ pub fn vqtbx4q_s8(a: int8x16_t, b: int8x16x4_t, c: uint8x16_t) -> int8x16_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
@@ -20866,7 +20866,7 @@ pub fn vqtbx4_u8(a: uint8x8_t, b: uint8x16x4_t, c: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
@@ -20917,7 +20917,7 @@ pub fn vqtbx4_u8(a: uint8x8_t, b: uint8x16x4_t, c: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4q_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
@@ -20936,7 +20936,7 @@ pub fn vqtbx4q_u8(a: uint8x16_t, b: uint8x16x4_t, c: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4q_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
@@ -20993,7 +20993,7 @@ pub fn vqtbx4q_u8(a: uint8x16_t, b: uint8x16x4_t, c: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
@@ -21012,7 +21012,7 @@ pub fn vqtbx4_p8(a: poly8x8_t, b: poly8x16x4_t, c: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
@@ -21063,7 +21063,7 @@ pub fn vqtbx4_p8(a: poly8x8_t, b: poly8x16x4_t, c: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4q_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
@@ -21082,7 +21082,7 @@ pub fn vqtbx4q_p8(a: poly8x16_t, b: poly8x16x4_t, c: uint8x16_t) -> poly8x16_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqtbx4q_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
@@ -21139,7 +21139,7 @@ pub fn vqtbx4q_p8(a: poly8x16_t, b: poly8x16x4_t, c: uint8x16_t) -> poly8x16_t {
 }
 #[doc = "Rotate and exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrax1q_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,sha3")]
 #[cfg_attr(test, assert_instr(rax1))]
 #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")]
@@ -21155,7 +21155,7 @@ pub fn vrax1q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Reverse bit order"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrbit_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(rbit))]
@@ -21164,7 +21164,7 @@ pub fn vrbit_s8(a: int8x8_t) -> int8x8_t {
 }
 #[doc = "Reverse bit order"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrbitq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(rbit))]
@@ -21173,7 +21173,7 @@ pub fn vrbitq_s8(a: int8x16_t) -> int8x16_t {
 }
 #[doc = "Reverse bit order"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrbit_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21183,7 +21183,7 @@ pub fn vrbit_u8(a: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Reverse bit order"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrbit_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21197,7 +21197,7 @@ pub fn vrbit_u8(a: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Reverse bit order"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrbitq_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21207,7 +21207,7 @@ pub fn vrbitq_u8(a: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Reverse bit order"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrbitq_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21226,7 +21226,7 @@ pub fn vrbitq_u8(a: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Reverse bit order"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrbit_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21236,7 +21236,7 @@ pub fn vrbit_p8(a: poly8x8_t) -> poly8x8_t {
 }
 #[doc = "Reverse bit order"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrbit_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21250,7 +21250,7 @@ pub fn vrbit_p8(a: poly8x8_t) -> poly8x8_t {
 }
 #[doc = "Reverse bit order"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrbitq_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21260,7 +21260,7 @@ pub fn vrbitq_p8(a: poly8x16_t) -> poly8x16_t {
 }
 #[doc = "Reverse bit order"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrbitq_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21279,7 +21279,7 @@ pub fn vrbitq_p8(a: poly8x16_t) -> poly8x16_t {
 }
 #[doc = "Reciprocal estimate."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpe_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(frecpe))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21295,7 +21295,7 @@ pub fn vrecpe_f64(a: float64x1_t) -> float64x1_t {
 }
 #[doc = "Reciprocal estimate."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpeq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(frecpe))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21311,7 +21311,7 @@ pub fn vrecpeq_f64(a: float64x2_t) -> float64x2_t {
 }
 #[doc = "Reciprocal estimate."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecped_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(frecpe))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21327,7 +21327,7 @@ pub fn vrecped_f64(a: f64) -> f64 {
 }
 #[doc = "Reciprocal estimate."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpes_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(frecpe))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21343,7 +21343,7 @@ pub fn vrecpes_f32(a: f32) -> f32 {
 }
 #[doc = "Reciprocal estimate."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpeh_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(frecpe))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -21360,7 +21360,7 @@ pub fn vrecpeh_f16(a: f16) -> f16 {
 }
 #[doc = "Floating-point reciprocal step"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecps_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(frecps))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21376,7 +21376,7 @@ pub fn vrecps_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t {
 }
 #[doc = "Floating-point reciprocal step"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpsq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(frecps))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21392,7 +21392,7 @@ pub fn vrecpsq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
 }
 #[doc = "Floating-point reciprocal step"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpsd_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(frecps))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21408,7 +21408,7 @@ pub fn vrecpsd_f64(a: f64, b: f64) -> f64 {
 }
 #[doc = "Floating-point reciprocal step"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpss_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(frecps))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21424,7 +21424,7 @@ pub fn vrecpss_f32(a: f32, b: f32) -> f32 {
 }
 #[doc = "Floating-point reciprocal step"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpsh_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(frecps))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -21441,7 +21441,7 @@ pub fn vrecpsh_f16(a: f16, b: f16) -> f16 {
 }
 #[doc = "Floating-point reciprocal exponent"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpxd_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(frecpx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21457,7 +21457,7 @@ pub fn vrecpxd_f64(a: f64) -> f64 {
 }
 #[doc = "Floating-point reciprocal exponent"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpxs_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(frecpx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21473,7 +21473,7 @@ pub fn vrecpxs_f32(a: f32) -> f32 {
 }
 #[doc = "Floating-point reciprocal exponent"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpxh_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(frecpx))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -21490,7 +21490,7 @@ pub fn vrecpxh_f16(a: f16) -> f16 {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
@@ -21501,7 +21501,7 @@ pub fn vreinterpret_f64_f16(a: float16x4_t) -> float64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
@@ -21513,7 +21513,7 @@ pub fn vreinterpret_f64_f16(a: float16x4_t) -> float64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
@@ -21524,7 +21524,7 @@ pub fn vreinterpretq_f64_f16(a: float16x8_t) -> float64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
@@ -21539,7 +21539,7 @@ pub fn vreinterpretq_f64_f16(a: float16x8_t) -> float64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_f64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
@@ -21550,7 +21550,7 @@ pub fn vreinterpret_f16_f64(a: float64x1_t) -> float16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_f64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
@@ -21564,7 +21564,7 @@ pub fn vreinterpret_f16_f64(a: float64x1_t) -> float16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_f64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
@@ -21575,7 +21575,7 @@ pub fn vreinterpretq_f16_f64(a: float64x2_t) -> float16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_f64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
@@ -21590,7 +21590,7 @@ pub fn vreinterpretq_f16_f64(a: float64x2_t) -> float16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_p128)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21600,7 +21600,7 @@ pub fn vreinterpretq_f64_p128(a: p128) -> float64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_p128)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21613,7 +21613,7 @@ pub fn vreinterpretq_f64_p128(a: p128) -> float64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21623,7 +21623,7 @@ pub fn vreinterpret_f64_f32(a: float32x2_t) -> float64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21634,7 +21634,7 @@ pub fn vreinterpret_f64_f32(a: float32x2_t) -> float64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21644,7 +21644,7 @@ pub fn vreinterpret_p64_f32(a: float32x2_t) -> poly64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21655,7 +21655,7 @@ pub fn vreinterpret_p64_f32(a: float32x2_t) -> poly64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21665,7 +21665,7 @@ pub fn vreinterpretq_f64_f32(a: float32x4_t) -> float64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21679,7 +21679,7 @@ pub fn vreinterpretq_f64_f32(a: float32x4_t) -> float64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21689,7 +21689,7 @@ pub fn vreinterpretq_p64_f32(a: float32x4_t) -> poly64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21703,7 +21703,7 @@ pub fn vreinterpretq_p64_f32(a: float32x4_t) -> poly64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_f64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21713,7 +21713,7 @@ pub fn vreinterpret_f32_f64(a: float64x1_t) -> float32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_f64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21726,7 +21726,7 @@ pub fn vreinterpret_f32_f64(a: float64x1_t) -> float32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_f64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21736,7 +21736,7 @@ pub fn vreinterpret_s8_f64(a: float64x1_t) -> int8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_f64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21749,7 +21749,7 @@ pub fn vreinterpret_s8_f64(a: float64x1_t) -> int8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_f64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21759,7 +21759,7 @@ pub fn vreinterpret_s16_f64(a: float64x1_t) -> int16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_f64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21772,7 +21772,7 @@ pub fn vreinterpret_s16_f64(a: float64x1_t) -> int16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_f64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21782,7 +21782,7 @@ pub fn vreinterpret_s32_f64(a: float64x1_t) -> int32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_f64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21795,7 +21795,7 @@ pub fn vreinterpret_s32_f64(a: float64x1_t) -> int32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(nop))]
@@ -21804,7 +21804,7 @@ pub fn vreinterpret_s64_f64(a: float64x1_t) -> int64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_f64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21814,7 +21814,7 @@ pub fn vreinterpret_u8_f64(a: float64x1_t) -> uint8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_f64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21827,7 +21827,7 @@ pub fn vreinterpret_u8_f64(a: float64x1_t) -> uint8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_f64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21837,7 +21837,7 @@ pub fn vreinterpret_u16_f64(a: float64x1_t) -> uint16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_f64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21850,7 +21850,7 @@ pub fn vreinterpret_u16_f64(a: float64x1_t) -> uint16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_f64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21860,7 +21860,7 @@ pub fn vreinterpret_u32_f64(a: float64x1_t) -> uint32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_f64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21873,7 +21873,7 @@ pub fn vreinterpret_u32_f64(a: float64x1_t) -> uint32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(nop))]
@@ -21882,7 +21882,7 @@ pub fn vreinterpret_u64_f64(a: float64x1_t) -> uint64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_f64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21892,7 +21892,7 @@ pub fn vreinterpret_p8_f64(a: float64x1_t) -> poly8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_f64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21905,7 +21905,7 @@ pub fn vreinterpret_p8_f64(a: float64x1_t) -> poly8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_f64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21915,7 +21915,7 @@ pub fn vreinterpret_p16_f64(a: float64x1_t) -> poly16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_f64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21928,7 +21928,7 @@ pub fn vreinterpret_p16_f64(a: float64x1_t) -> poly16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(nop))]
@@ -21937,7 +21937,7 @@ pub fn vreinterpret_p64_f64(a: float64x1_t) -> poly64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_f64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21947,7 +21947,7 @@ pub fn vreinterpretq_p128_f64(a: float64x2_t) -> p128 {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_f64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21958,7 +21958,7 @@ pub fn vreinterpretq_p128_f64(a: float64x2_t) -> p128 {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_f64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21968,7 +21968,7 @@ pub fn vreinterpretq_f32_f64(a: float64x2_t) -> float32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_f64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21982,7 +21982,7 @@ pub fn vreinterpretq_f32_f64(a: float64x2_t) -> float32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_f64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21992,7 +21992,7 @@ pub fn vreinterpretq_s8_f64(a: float64x2_t) -> int8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_f64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22010,7 +22010,7 @@ pub fn vreinterpretq_s8_f64(a: float64x2_t) -> int8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_f64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22020,7 +22020,7 @@ pub fn vreinterpretq_s16_f64(a: float64x2_t) -> int16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_f64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22034,7 +22034,7 @@ pub fn vreinterpretq_s16_f64(a: float64x2_t) -> int16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_f64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22044,7 +22044,7 @@ pub fn vreinterpretq_s32_f64(a: float64x2_t) -> int32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_f64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22058,7 +22058,7 @@ pub fn vreinterpretq_s32_f64(a: float64x2_t) -> int32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_f64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22068,7 +22068,7 @@ pub fn vreinterpretq_s64_f64(a: float64x2_t) -> int64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_f64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22082,7 +22082,7 @@ pub fn vreinterpretq_s64_f64(a: float64x2_t) -> int64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_f64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22092,7 +22092,7 @@ pub fn vreinterpretq_u8_f64(a: float64x2_t) -> uint8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_f64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22110,7 +22110,7 @@ pub fn vreinterpretq_u8_f64(a: float64x2_t) -> uint8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_f64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22120,7 +22120,7 @@ pub fn vreinterpretq_u16_f64(a: float64x2_t) -> uint16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_f64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22134,7 +22134,7 @@ pub fn vreinterpretq_u16_f64(a: float64x2_t) -> uint16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_f64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22144,7 +22144,7 @@ pub fn vreinterpretq_u32_f64(a: float64x2_t) -> uint32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_f64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22158,7 +22158,7 @@ pub fn vreinterpretq_u32_f64(a: float64x2_t) -> uint32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_f64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22168,7 +22168,7 @@ pub fn vreinterpretq_u64_f64(a: float64x2_t) -> uint64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_f64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22182,7 +22182,7 @@ pub fn vreinterpretq_u64_f64(a: float64x2_t) -> uint64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_f64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22192,7 +22192,7 @@ pub fn vreinterpretq_p8_f64(a: float64x2_t) -> poly8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_f64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22210,7 +22210,7 @@ pub fn vreinterpretq_p8_f64(a: float64x2_t) -> poly8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_f64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22220,7 +22220,7 @@ pub fn vreinterpretq_p16_f64(a: float64x2_t) -> poly16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_f64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22234,7 +22234,7 @@ pub fn vreinterpretq_p16_f64(a: float64x2_t) -> poly16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_f64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22244,7 +22244,7 @@ pub fn vreinterpretq_p64_f64(a: float64x2_t) -> poly64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_f64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22258,7 +22258,7 @@ pub fn vreinterpretq_p64_f64(a: float64x2_t) -> poly64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22268,7 +22268,7 @@ pub fn vreinterpret_f64_s8(a: int8x8_t) -> float64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22279,7 +22279,7 @@ pub fn vreinterpret_f64_s8(a: int8x8_t) -> float64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22289,7 +22289,7 @@ pub fn vreinterpretq_f64_s8(a: int8x16_t) -> float64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22304,7 +22304,7 @@ pub fn vreinterpretq_f64_s8(a: int8x16_t) -> float64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22314,7 +22314,7 @@ pub fn vreinterpret_f64_s16(a: int16x4_t) -> float64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22325,7 +22325,7 @@ pub fn vreinterpret_f64_s16(a: int16x4_t) -> float64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22335,7 +22335,7 @@ pub fn vreinterpretq_f64_s16(a: int16x8_t) -> float64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22349,7 +22349,7 @@ pub fn vreinterpretq_f64_s16(a: int16x8_t) -> float64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22359,7 +22359,7 @@ pub fn vreinterpret_f64_s32(a: int32x2_t) -> float64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22370,7 +22370,7 @@ pub fn vreinterpret_f64_s32(a: int32x2_t) -> float64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22380,7 +22380,7 @@ pub fn vreinterpretq_f64_s32(a: int32x4_t) -> float64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22394,7 +22394,7 @@ pub fn vreinterpretq_f64_s32(a: int32x4_t) -> float64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(nop))]
@@ -22403,7 +22403,7 @@ pub fn vreinterpret_f64_s64(a: int64x1_t) -> float64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(nop))]
@@ -22412,7 +22412,7 @@ pub fn vreinterpret_p64_s64(a: int64x1_t) -> poly64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22422,7 +22422,7 @@ pub fn vreinterpretq_f64_s64(a: int64x2_t) -> float64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22436,7 +22436,7 @@ pub fn vreinterpretq_f64_s64(a: int64x2_t) -> float64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22446,7 +22446,7 @@ pub fn vreinterpretq_p64_s64(a: int64x2_t) -> poly64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22460,7 +22460,7 @@ pub fn vreinterpretq_p64_s64(a: int64x2_t) -> poly64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22470,7 +22470,7 @@ pub fn vreinterpret_f64_u8(a: uint8x8_t) -> float64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22481,7 +22481,7 @@ pub fn vreinterpret_f64_u8(a: uint8x8_t) -> float64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22491,7 +22491,7 @@ pub fn vreinterpretq_f64_u8(a: uint8x16_t) -> float64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22506,7 +22506,7 @@ pub fn vreinterpretq_f64_u8(a: uint8x16_t) -> float64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22516,7 +22516,7 @@ pub fn vreinterpret_f64_u16(a: uint16x4_t) -> float64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22527,7 +22527,7 @@ pub fn vreinterpret_f64_u16(a: uint16x4_t) -> float64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22537,7 +22537,7 @@ pub fn vreinterpretq_f64_u16(a: uint16x8_t) -> float64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22551,7 +22551,7 @@ pub fn vreinterpretq_f64_u16(a: uint16x8_t) -> float64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22561,7 +22561,7 @@ pub fn vreinterpret_f64_u32(a: uint32x2_t) -> float64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22572,7 +22572,7 @@ pub fn vreinterpret_f64_u32(a: uint32x2_t) -> float64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22582,7 +22582,7 @@ pub fn vreinterpretq_f64_u32(a: uint32x4_t) -> float64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22596,7 +22596,7 @@ pub fn vreinterpretq_f64_u32(a: uint32x4_t) -> float64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(nop))]
@@ -22605,7 +22605,7 @@ pub fn vreinterpret_f64_u64(a: uint64x1_t) -> float64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(nop))]
@@ -22614,7 +22614,7 @@ pub fn vreinterpret_p64_u64(a: uint64x1_t) -> poly64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22624,7 +22624,7 @@ pub fn vreinterpretq_f64_u64(a: uint64x2_t) -> float64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22638,7 +22638,7 @@ pub fn vreinterpretq_f64_u64(a: uint64x2_t) -> float64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22648,7 +22648,7 @@ pub fn vreinterpretq_p64_u64(a: uint64x2_t) -> poly64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22662,7 +22662,7 @@ pub fn vreinterpretq_p64_u64(a: uint64x2_t) -> poly64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22672,7 +22672,7 @@ pub fn vreinterpret_f64_p8(a: poly8x8_t) -> float64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22683,7 +22683,7 @@ pub fn vreinterpret_f64_p8(a: poly8x8_t) -> float64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22693,7 +22693,7 @@ pub fn vreinterpretq_f64_p8(a: poly8x16_t) -> float64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22708,7 +22708,7 @@ pub fn vreinterpretq_f64_p8(a: poly8x16_t) -> float64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22718,7 +22718,7 @@ pub fn vreinterpret_f64_p16(a: poly16x4_t) -> float64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22729,7 +22729,7 @@ pub fn vreinterpret_f64_p16(a: poly16x4_t) -> float64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22739,7 +22739,7 @@ pub fn vreinterpretq_f64_p16(a: poly16x8_t) -> float64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22753,7 +22753,7 @@ pub fn vreinterpretq_f64_p16(a: poly16x8_t) -> float64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_p64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22763,7 +22763,7 @@ pub fn vreinterpret_f32_p64(a: poly64x1_t) -> float32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_p64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22776,7 +22776,7 @@ pub fn vreinterpret_f32_p64(a: poly64x1_t) -> float32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_p64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(nop))]
@@ -22785,7 +22785,7 @@ pub fn vreinterpret_f64_p64(a: poly64x1_t) -> float64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_p64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(nop))]
@@ -22794,7 +22794,7 @@ pub fn vreinterpret_s64_p64(a: poly64x1_t) -> int64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_p64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(nop))]
@@ -22803,7 +22803,7 @@ pub fn vreinterpret_u64_p64(a: poly64x1_t) -> uint64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22813,7 +22813,7 @@ pub fn vreinterpretq_f32_p64(a: poly64x2_t) -> float32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22827,7 +22827,7 @@ pub fn vreinterpretq_f32_p64(a: poly64x2_t) -> float32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_p64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22837,7 +22837,7 @@ pub fn vreinterpretq_f64_p64(a: poly64x2_t) -> float64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_p64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22851,7 +22851,7 @@ pub fn vreinterpretq_f64_p64(a: poly64x2_t) -> float64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22861,7 +22861,7 @@ pub fn vreinterpretq_s64_p64(a: poly64x2_t) -> int64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22875,7 +22875,7 @@ pub fn vreinterpretq_s64_p64(a: poly64x2_t) -> int64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22885,7 +22885,7 @@ pub fn vreinterpretq_u64_p64(a: poly64x2_t) -> uint64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22899,7 +22899,7 @@ pub fn vreinterpretq_u64_p64(a: poly64x2_t) -> uint64x2_t {
 }
 #[doc = "Floating-point round to 32-bit integer, using current rounding mode"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd32x_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,frintts")]
 #[unstable(feature = "stdarch_neon_ftts", issue = "117227")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint32x))]
@@ -22915,7 +22915,7 @@ pub fn vrnd32x_f32(a: float32x2_t) -> float32x2_t {
 }
 #[doc = "Floating-point round to 32-bit integer, using current rounding mode"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd32xq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,frintts")]
 #[unstable(feature = "stdarch_neon_ftts", issue = "117227")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint32x))]
@@ -22931,7 +22931,7 @@ pub fn vrnd32xq_f32(a: float32x4_t) -> float32x4_t {
 }
 #[doc = "Floating-point round to 32-bit integer, using current rounding mode"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd32xq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,frintts")]
 #[unstable(feature = "stdarch_neon_ftts", issue = "117227")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint32x))]
@@ -22947,7 +22947,7 @@ pub fn vrnd32xq_f64(a: float64x2_t) -> float64x2_t {
 }
 #[doc = "Floating-point round to 32-bit integer, using current rounding mode"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd32x_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,frintts")]
 #[unstable(feature = "stdarch_neon_ftts", issue = "117227")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint32x))]
@@ -22963,7 +22963,7 @@ pub fn vrnd32x_f64(a: float64x1_t) -> float64x1_t {
 }
 #[doc = "Floating-point round to 32-bit integer toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd32z_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,frintts")]
 #[unstable(feature = "stdarch_neon_ftts", issue = "117227")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint32z))]
@@ -22979,7 +22979,7 @@ pub fn vrnd32z_f32(a: float32x2_t) -> float32x2_t {
 }
 #[doc = "Floating-point round to 32-bit integer toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd32zq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,frintts")]
 #[unstable(feature = "stdarch_neon_ftts", issue = "117227")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint32z))]
@@ -22995,7 +22995,7 @@ pub fn vrnd32zq_f32(a: float32x4_t) -> float32x4_t {
 }
 #[doc = "Floating-point round to 32-bit integer toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd32zq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,frintts")]
 #[unstable(feature = "stdarch_neon_ftts", issue = "117227")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint32z))]
@@ -23011,7 +23011,7 @@ pub fn vrnd32zq_f64(a: float64x2_t) -> float64x2_t {
 }
 #[doc = "Floating-point round to 32-bit integer toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd32z_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,frintts")]
 #[unstable(feature = "stdarch_neon_ftts", issue = "117227")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint32z))]
@@ -23027,7 +23027,7 @@ pub fn vrnd32z_f64(a: float64x1_t) -> float64x1_t {
 }
 #[doc = "Floating-point round to 64-bit integer, using current rounding mode"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd64x_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,frintts")]
 #[unstable(feature = "stdarch_neon_ftts", issue = "117227")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint64x))]
@@ -23043,7 +23043,7 @@ pub fn vrnd64x_f32(a: float32x2_t) -> float32x2_t {
 }
 #[doc = "Floating-point round to 64-bit integer, using current rounding mode"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd64xq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,frintts")]
 #[unstable(feature = "stdarch_neon_ftts", issue = "117227")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint64x))]
@@ -23059,7 +23059,7 @@ pub fn vrnd64xq_f32(a: float32x4_t) -> float32x4_t {
 }
 #[doc = "Floating-point round to 64-bit integer, using current rounding mode"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd64xq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,frintts")]
 #[unstable(feature = "stdarch_neon_ftts", issue = "117227")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint64x))]
@@ -23075,7 +23075,7 @@ pub fn vrnd64xq_f64(a: float64x2_t) -> float64x2_t {
 }
 #[doc = "Floating-point round to 64-bit integer, using current rounding mode"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd64x_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,frintts")]
 #[unstable(feature = "stdarch_neon_ftts", issue = "117227")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint64x))]
@@ -23091,7 +23091,7 @@ pub fn vrnd64x_f64(a: float64x1_t) -> float64x1_t {
 }
 #[doc = "Floating-point round to 64-bit integer toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd64z_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,frintts")]
 #[unstable(feature = "stdarch_neon_ftts", issue = "117227")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint64z))]
@@ -23107,7 +23107,7 @@ pub fn vrnd64z_f32(a: float32x2_t) -> float32x2_t {
 }
 #[doc = "Floating-point round to 64-bit integer toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd64zq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,frintts")]
 #[unstable(feature = "stdarch_neon_ftts", issue = "117227")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint64z))]
@@ -23123,7 +23123,7 @@ pub fn vrnd64zq_f32(a: float32x4_t) -> float32x4_t {
 }
 #[doc = "Floating-point round to 64-bit integer toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd64zq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,frintts")]
 #[unstable(feature = "stdarch_neon_ftts", issue = "117227")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint64z))]
@@ -23139,7 +23139,7 @@ pub fn vrnd64zq_f64(a: float64x2_t) -> float64x2_t {
 }
 #[doc = "Floating-point round to 64-bit integer toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd64z_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,frintts")]
 #[unstable(feature = "stdarch_neon_ftts", issue = "117227")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint64z))]
@@ -23155,7 +23155,7 @@ pub fn vrnd64z_f64(a: float64x1_t) -> float64x1_t {
 }
 #[doc = "Floating-point round to integral, toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -23165,7 +23165,7 @@ pub fn vrnd_f16(a: float16x4_t) -> float16x4_t {
 }
 #[doc = "Floating-point round to integral, toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndq_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -23175,7 +23175,7 @@ pub fn vrndq_f16(a: float16x8_t) -> float16x8_t {
 }
 #[doc = "Floating-point round to integral, toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(frintz))]
@@ -23184,7 +23184,7 @@ pub fn vrnd_f32(a: float32x2_t) -> float32x2_t {
 }
 #[doc = "Floating-point round to integral, toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(frintz))]
@@ -23193,7 +23193,7 @@ pub fn vrndq_f32(a: float32x4_t) -> float32x4_t {
 }
 #[doc = "Floating-point round to integral, toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(frintz))]
@@ -23202,7 +23202,7 @@ pub fn vrnd_f64(a: float64x1_t) -> float64x1_t {
 }
 #[doc = "Floating-point round to integral, toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(frintz))]
@@ -23211,7 +23211,7 @@ pub fn vrndq_f64(a: float64x2_t) -> float64x2_t {
 }
 #[doc = "Floating-point round to integral, to nearest with ties to away"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnda_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -23221,7 +23221,7 @@ pub fn vrnda_f16(a: float16x4_t) -> float16x4_t {
 }
 #[doc = "Floating-point round to integral, to nearest with ties to away"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndaq_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -23231,7 +23231,7 @@ pub fn vrndaq_f16(a: float16x8_t) -> float16x8_t {
 }
 #[doc = "Floating-point round to integral, to nearest with ties to away"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnda_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(frinta))]
@@ -23240,7 +23240,7 @@ pub fn vrnda_f32(a: float32x2_t) -> float32x2_t {
 }
 #[doc = "Floating-point round to integral, to nearest with ties to away"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndaq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(frinta))]
@@ -23249,7 +23249,7 @@ pub fn vrndaq_f32(a: float32x4_t) -> float32x4_t {
 }
 #[doc = "Floating-point round to integral, to nearest with ties to away"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnda_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(frinta))]
@@ -23258,7 +23258,7 @@ pub fn vrnda_f64(a: float64x1_t) -> float64x1_t {
 }
 #[doc = "Floating-point round to integral, to nearest with ties to away"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndaq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(frinta))]
@@ -23267,7 +23267,7 @@ pub fn vrndaq_f64(a: float64x2_t) -> float64x2_t {
 }
 #[doc = "Floating-point round to integral, to nearest with ties to away"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndah_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -23277,7 +23277,7 @@ pub fn vrndah_f16(a: f16) -> f16 {
 }
 #[doc = "Floating-point round to integral, to nearest with ties to away"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndh_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -23287,7 +23287,7 @@ pub fn vrndh_f16(a: f16) -> f16 {
 }
 #[doc = "Floating-point round to integral, using current rounding mode"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndi_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -23304,7 +23304,7 @@ pub fn vrndi_f16(a: float16x4_t) -> float16x4_t {
 }
 #[doc = "Floating-point round to integral, using current rounding mode"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndiq_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -23321,7 +23321,7 @@ pub fn vrndiq_f16(a: float16x8_t) -> float16x8_t {
 }
 #[doc = "Floating-point round to integral, using current rounding mode"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndi_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(frinti))]
@@ -23337,7 +23337,7 @@ pub fn vrndi_f32(a: float32x2_t) -> float32x2_t {
 }
 #[doc = "Floating-point round to integral, using current rounding mode"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndiq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(frinti))]
@@ -23353,7 +23353,7 @@ pub fn vrndiq_f32(a: float32x4_t) -> float32x4_t {
 }
 #[doc = "Floating-point round to integral, using current rounding mode"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndi_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(frinti))]
@@ -23369,7 +23369,7 @@ pub fn vrndi_f64(a: float64x1_t) -> float64x1_t {
 }
 #[doc = "Floating-point round to integral, using current rounding mode"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndiq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(frinti))]
@@ -23385,7 +23385,7 @@ pub fn vrndiq_f64(a: float64x2_t) -> float64x2_t {
 }
 #[doc = "Floating-point round to integral, using current rounding mode"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndih_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -23402,7 +23402,7 @@ pub fn vrndih_f16(a: f16) -> f16 {
 }
 #[doc = "Floating-point round to integral, toward minus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndm_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -23412,7 +23412,7 @@ pub fn vrndm_f16(a: float16x4_t) -> float16x4_t {
 }
 #[doc = "Floating-point round to integral, toward minus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndmq_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -23422,7 +23422,7 @@ pub fn vrndmq_f16(a: float16x8_t) -> float16x8_t {
 }
 #[doc = "Floating-point round to integral, toward minus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndm_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(frintm))]
@@ -23431,7 +23431,7 @@ pub fn vrndm_f32(a: float32x2_t) -> float32x2_t {
 }
 #[doc = "Floating-point round to integral, toward minus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndmq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(frintm))]
@@ -23440,7 +23440,7 @@ pub fn vrndmq_f32(a: float32x4_t) -> float32x4_t {
 }
 #[doc = "Floating-point round to integral, toward minus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndm_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(frintm))]
@@ -23449,7 +23449,7 @@ pub fn vrndm_f64(a: float64x1_t) -> float64x1_t {
 }
 #[doc = "Floating-point round to integral, toward minus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndmq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(frintm))]
@@ -23458,7 +23458,7 @@ pub fn vrndmq_f64(a: float64x2_t) -> float64x2_t {
 }
 #[doc = "Floating-point round to integral, toward minus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndmh_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -23468,7 +23468,7 @@ pub fn vrndmh_f16(a: f16) -> f16 {
 }
 #[doc = "Floating-point round to integral, to nearest with ties to even"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndn_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(frintn))]
@@ -23484,7 +23484,7 @@ pub fn vrndn_f64(a: float64x1_t) -> float64x1_t {
 }
 #[doc = "Floating-point round to integral, to nearest with ties to even"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndnq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(frintn))]
@@ -23500,7 +23500,7 @@ pub fn vrndnq_f64(a: float64x2_t) -> float64x2_t {
 }
 #[doc = "Floating-point round to integral, toward minus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndnh_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -23517,7 +23517,7 @@ pub fn vrndnh_f16(a: f16) -> f16 {
 }
 #[doc = "Floating-point round to integral, to nearest with ties to even"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndns_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(frintn))]
@@ -23533,7 +23533,7 @@ pub fn vrndns_f32(a: f32) -> f32 {
 }
 #[doc = "Floating-point round to integral, toward plus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndp_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -23543,7 +23543,7 @@ pub fn vrndp_f16(a: float16x4_t) -> float16x4_t {
 }
 #[doc = "Floating-point round to integral, toward plus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndpq_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -23553,7 +23553,7 @@ pub fn vrndpq_f16(a: float16x8_t) -> float16x8_t {
 }
 #[doc = "Floating-point round to integral, toward plus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndp_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(frintp))]
@@ -23562,7 +23562,7 @@ pub fn vrndp_f32(a: float32x2_t) -> float32x2_t {
 }
 #[doc = "Floating-point round to integral, toward plus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndpq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(frintp))]
@@ -23571,7 +23571,7 @@ pub fn vrndpq_f32(a: float32x4_t) -> float32x4_t {
 }
 #[doc = "Floating-point round to integral, toward plus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndp_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(frintp))]
@@ -23580,7 +23580,7 @@ pub fn vrndp_f64(a: float64x1_t) -> float64x1_t {
 }
 #[doc = "Floating-point round to integral, toward plus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndpq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(frintp))]
@@ -23589,7 +23589,7 @@ pub fn vrndpq_f64(a: float64x2_t) -> float64x2_t {
 }
 #[doc = "Floating-point round to integral, toward plus infinity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndph_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -23599,7 +23599,7 @@ pub fn vrndph_f16(a: f16) -> f16 {
 }
 #[doc = "Floating-point round to integral exact, using current rounding mode"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndx_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -23609,7 +23609,7 @@ pub fn vrndx_f16(a: float16x4_t) -> float16x4_t {
 }
 #[doc = "Floating-point round to integral exact, using current rounding mode"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndxq_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -23619,7 +23619,7 @@ pub fn vrndxq_f16(a: float16x8_t) -> float16x8_t {
 }
 #[doc = "Floating-point round to integral exact, using current rounding mode"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndx_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(frintx))]
@@ -23628,7 +23628,7 @@ pub fn vrndx_f32(a: float32x2_t) -> float32x2_t {
 }
 #[doc = "Floating-point round to integral exact, using current rounding mode"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndxq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(frintx))]
@@ -23637,7 +23637,7 @@ pub fn vrndxq_f32(a: float32x4_t) -> float32x4_t {
 }
 #[doc = "Floating-point round to integral exact, using current rounding mode"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndx_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(frintx))]
@@ -23646,7 +23646,7 @@ pub fn vrndx_f64(a: float64x1_t) -> float64x1_t {
 }
 #[doc = "Floating-point round to integral exact, using current rounding mode"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndxq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(frintx))]
@@ -23655,7 +23655,7 @@ pub fn vrndxq_f64(a: float64x2_t) -> float64x2_t {
 }
 #[doc = "Floating-point round to integral, using current rounding mode"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndxh_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -23665,7 +23665,7 @@ pub fn vrndxh_f16(a: f16) -> f16 {
 }
 #[doc = "Signed rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshld_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(srshl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -23681,7 +23681,7 @@ pub fn vrshld_s64(a: i64, b: i64) -> i64 {
 }
 #[doc = "Unsigned rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshld_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(urshl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -23697,7 +23697,7 @@ pub fn vrshld_u64(a: u64, b: i64) -> u64 {
 }
 #[doc = "Signed rounding shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrd_n_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(srshr, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -23708,7 +23708,7 @@ pub fn vrshrd_n_s64<const N: i32>(a: i64) -> i64 {
 }
 #[doc = "Unsigned rounding shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrd_n_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(urshr, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -23719,7 +23719,7 @@ pub fn vrshrd_n_u64<const N: i32>(a: u64) -> u64 {
 }
 #[doc = "Rounding shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_high_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(rshrn2, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -23736,7 +23736,7 @@ pub fn vrshrn_high_n_s16<const N: i32>(a: int8x8_t, b: int16x8_t) -> int8x16_t {
 }
 #[doc = "Rounding shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_high_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(rshrn2, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -23747,7 +23747,7 @@ pub fn vrshrn_high_n_s32<const N: i32>(a: int16x4_t, b: int32x4_t) -> int16x8_t
 }
 #[doc = "Rounding shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_high_n_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(rshrn2, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -23758,7 +23758,7 @@ pub fn vrshrn_high_n_s64<const N: i32>(a: int32x2_t, b: int64x2_t) -> int32x4_t
 }
 #[doc = "Rounding shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_high_n_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(rshrn2, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -23775,7 +23775,7 @@ pub fn vrshrn_high_n_u16<const N: i32>(a: uint8x8_t, b: uint16x8_t) -> uint8x16_
 }
 #[doc = "Rounding shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_high_n_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(rshrn2, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -23786,7 +23786,7 @@ pub fn vrshrn_high_n_u32<const N: i32>(a: uint16x4_t, b: uint32x4_t) -> uint16x8
 }
 #[doc = "Rounding shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_high_n_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(rshrn2, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -23797,7 +23797,7 @@ pub fn vrshrn_high_n_u64<const N: i32>(a: uint32x2_t, b: uint64x2_t) -> uint32x4
 }
 #[doc = "Reciprocal square-root estimate."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrte_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(frsqrte))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -23813,7 +23813,7 @@ pub fn vrsqrte_f64(a: float64x1_t) -> float64x1_t {
 }
 #[doc = "Reciprocal square-root estimate."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrteq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(frsqrte))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -23829,7 +23829,7 @@ pub fn vrsqrteq_f64(a: float64x2_t) -> float64x2_t {
 }
 #[doc = "Reciprocal square-root estimate."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrted_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(frsqrte))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -23845,7 +23845,7 @@ pub fn vrsqrted_f64(a: f64) -> f64 {
 }
 #[doc = "Reciprocal square-root estimate."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrtes_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(frsqrte))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -23861,7 +23861,7 @@ pub fn vrsqrtes_f32(a: f32) -> f32 {
 }
 #[doc = "Reciprocal square-root estimate."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrteh_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(frsqrte))]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -23878,7 +23878,7 @@ pub fn vrsqrteh_f16(a: f16) -> f16 {
 }
 #[doc = "Floating-point reciprocal square root step"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrts_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(frsqrts))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -23894,7 +23894,7 @@ pub fn vrsqrts_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t {
 }
 #[doc = "Floating-point reciprocal square root step"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrtsq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(frsqrts))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -23910,7 +23910,7 @@ pub fn vrsqrtsq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
 }
 #[doc = "Floating-point reciprocal square root step"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrtsd_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(frsqrts))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -23926,7 +23926,7 @@ pub fn vrsqrtsd_f64(a: f64, b: f64) -> f64 {
 }
 #[doc = "Floating-point reciprocal square root step"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrtss_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(frsqrts))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -23942,7 +23942,7 @@ pub fn vrsqrtss_f32(a: f32, b: f32) -> f32 {
 }
 #[doc = "Floating-point reciprocal square root step"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrtsh_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(test, assert_instr(frsqrts))]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
@@ -23959,7 +23959,7 @@ pub fn vrsqrtsh_f16(a: f16, b: f16) -> f16 {
 }
 #[doc = "Signed rounding shift right and accumulate."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsrad_n_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(srshr, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -23971,7 +23971,7 @@ pub fn vrsrad_n_s64<const N: i32>(a: i64, b: i64) -> i64 {
 }
 #[doc = "Unsigned rounding shift right and accumulate."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsrad_n_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(urshr, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -23983,7 +23983,7 @@ pub fn vrsrad_n_u64<const N: i32>(a: u64, b: u64) -> u64 {
 }
 #[doc = "Rounding subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_high_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_endian = "little")]
 #[cfg_attr(test, assert_instr(rsubhn2))]
@@ -23994,7 +23994,7 @@ pub fn vrsubhn_high_s16(a: int8x8_t, b: int16x8_t, c: int16x8_t) -> int8x16_t {
 }
 #[doc = "Rounding subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_high_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_endian = "little")]
 #[cfg_attr(test, assert_instr(rsubhn2))]
@@ -24005,7 +24005,7 @@ pub fn vrsubhn_high_s32(a: int16x4_t, b: int32x4_t, c: int32x4_t) -> int16x8_t {
 }
 #[doc = "Rounding subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_high_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_endian = "little")]
 #[cfg_attr(test, assert_instr(rsubhn2))]
@@ -24016,7 +24016,7 @@ pub fn vrsubhn_high_s64(a: int32x2_t, b: int64x2_t, c: int64x2_t) -> int32x4_t {
 }
 #[doc = "Rounding subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_high_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_endian = "little")]
 #[cfg_attr(test, assert_instr(rsubhn2))]
@@ -24027,7 +24027,7 @@ pub fn vrsubhn_high_u16(a: uint8x8_t, b: uint16x8_t, c: uint16x8_t) -> uint8x16_
 }
 #[doc = "Rounding subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_high_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_endian = "little")]
 #[cfg_attr(test, assert_instr(rsubhn2))]
@@ -24038,7 +24038,7 @@ pub fn vrsubhn_high_u32(a: uint16x4_t, b: uint32x4_t, c: uint32x4_t) -> uint16x8
 }
 #[doc = "Rounding subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_high_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_endian = "little")]
 #[cfg_attr(test, assert_instr(rsubhn2))]
@@ -24049,7 +24049,7 @@ pub fn vrsubhn_high_u64(a: uint32x2_t, b: uint64x2_t, c: uint64x2_t) -> uint32x4
 }
 #[doc = "Rounding subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_high_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_endian = "big")]
 #[cfg_attr(test, assert_instr(rsubhn))]
@@ -24060,7 +24060,7 @@ pub fn vrsubhn_high_s16(a: int8x8_t, b: int16x8_t, c: int16x8_t) -> int8x16_t {
 }
 #[doc = "Rounding subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_high_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_endian = "big")]
 #[cfg_attr(test, assert_instr(rsubhn))]
@@ -24071,7 +24071,7 @@ pub fn vrsubhn_high_s32(a: int16x4_t, b: int32x4_t, c: int32x4_t) -> int16x8_t {
 }
 #[doc = "Rounding subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_high_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_endian = "big")]
 #[cfg_attr(test, assert_instr(rsubhn))]
@@ -24082,7 +24082,7 @@ pub fn vrsubhn_high_s64(a: int32x2_t, b: int64x2_t, c: int64x2_t) -> int32x4_t {
 }
 #[doc = "Rounding subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_high_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_endian = "big")]
 #[cfg_attr(test, assert_instr(rsubhn))]
@@ -24093,7 +24093,7 @@ pub fn vrsubhn_high_u16(a: uint8x8_t, b: uint16x8_t, c: uint16x8_t) -> uint8x16_
 }
 #[doc = "Rounding subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_high_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_endian = "big")]
 #[cfg_attr(test, assert_instr(rsubhn))]
@@ -24104,7 +24104,7 @@ pub fn vrsubhn_high_u32(a: uint16x4_t, b: uint32x4_t, c: uint32x4_t) -> uint16x8
 }
 #[doc = "Rounding subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_high_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_endian = "big")]
 #[cfg_attr(test, assert_instr(rsubhn))]
@@ -24115,7 +24115,7 @@ pub fn vrsubhn_high_u64(a: uint32x2_t, b: uint64x2_t, c: uint64x2_t) -> uint32x4
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(nop, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -24126,7 +24126,7 @@ pub fn vset_lane_f64<const LANE: i32>(a: f64, b: float64x1_t) -> float64x1_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(nop, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -24137,7 +24137,7 @@ pub fn vsetq_lane_f64<const LANE: i32>(a: f64, b: float64x2_t) -> float64x2_t {
 }
 #[doc = "SHA512 hash update part 2"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha512h2q_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,sha3")]
 #[cfg_attr(test, assert_instr(sha512h2))]
 #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")]
@@ -24153,7 +24153,7 @@ pub fn vsha512h2q_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uint64x2_t
 }
 #[doc = "SHA512 hash update part 1"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha512hq_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,sha3")]
 #[cfg_attr(test, assert_instr(sha512h))]
 #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")]
@@ -24169,7 +24169,7 @@ pub fn vsha512hq_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uint64x2_t
 }
 #[doc = "SHA512 schedule update 0"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha512su0q_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,sha3")]
 #[cfg_attr(test, assert_instr(sha512su0))]
 #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")]
@@ -24185,7 +24185,7 @@ pub fn vsha512su0q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "SHA512 schedule update 1"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha512su1q_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,sha3")]
 #[cfg_attr(test, assert_instr(sha512su1))]
 #[stable(feature = "stdarch_neon_sha3", since = "1.79.0")]
@@ -24201,7 +24201,7 @@ pub fn vsha512su1q_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uint64x2_
 }
 #[doc = "Signed Shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshld_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sshl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -24210,7 +24210,7 @@ pub fn vshld_s64(a: i64, b: i64) -> i64 {
 }
 #[doc = "Unsigned Shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshld_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ushl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -24219,7 +24219,7 @@ pub fn vshld_u64(a: u64, b: i64) -> u64 {
 }
 #[doc = "Signed shift left long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_high_n_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sshll2, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -24233,7 +24233,7 @@ pub fn vshll_high_n_s8<const N: i32>(a: int8x16_t) -> int16x8_t {
 }
 #[doc = "Signed shift left long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_high_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sshll2, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -24247,7 +24247,7 @@ pub fn vshll_high_n_s16<const N: i32>(a: int16x8_t) -> int32x4_t {
 }
 #[doc = "Signed shift left long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_high_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sshll2, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -24261,7 +24261,7 @@ pub fn vshll_high_n_s32<const N: i32>(a: int32x4_t) -> int64x2_t {
 }
 #[doc = "Signed shift left long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_high_n_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ushll2, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -24275,7 +24275,7 @@ pub fn vshll_high_n_u8<const N: i32>(a: uint8x16_t) -> uint16x8_t {
 }
 #[doc = "Signed shift left long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_high_n_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ushll2, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -24289,7 +24289,7 @@ pub fn vshll_high_n_u16<const N: i32>(a: uint16x8_t) -> uint32x4_t {
 }
 #[doc = "Signed shift left long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_high_n_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ushll2, N = 2))]
 #[rustc_legacy_const_generics(1)]
@@ -24303,7 +24303,7 @@ pub fn vshll_high_n_u32<const N: i32>(a: uint32x4_t) -> uint64x2_t {
 }
 #[doc = "Shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_high_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(shrn2, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -24320,7 +24320,7 @@ pub fn vshrn_high_n_s16<const N: i32>(a: int8x8_t, b: int16x8_t) -> int8x16_t {
 }
 #[doc = "Shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_high_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(shrn2, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -24331,7 +24331,7 @@ pub fn vshrn_high_n_s32<const N: i32>(a: int16x4_t, b: int32x4_t) -> int16x8_t {
 }
 #[doc = "Shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_high_n_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(shrn2, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -24342,7 +24342,7 @@ pub fn vshrn_high_n_s64<const N: i32>(a: int32x2_t, b: int64x2_t) -> int32x4_t {
 }
 #[doc = "Shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_high_n_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(shrn2, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -24359,7 +24359,7 @@ pub fn vshrn_high_n_u16<const N: i32>(a: uint8x8_t, b: uint16x8_t) -> uint8x16_t
 }
 #[doc = "Shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_high_n_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(shrn2, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -24370,7 +24370,7 @@ pub fn vshrn_high_n_u32<const N: i32>(a: uint16x4_t, b: uint32x4_t) -> uint16x8_
 }
 #[doc = "Shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_high_n_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(shrn2, N = 2))]
 #[rustc_legacy_const_generics(2)]
@@ -24381,7 +24381,7 @@ pub fn vshrn_high_n_u64<const N: i32>(a: uint32x2_t, b: uint64x2_t) -> uint32x4_
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sli, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -24399,7 +24399,7 @@ pub fn vsli_n_s8<const N: i32>(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sli, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -24417,7 +24417,7 @@ pub fn vsliq_n_s8<const N: i32>(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sli, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -24435,7 +24435,7 @@ pub fn vsli_n_s16<const N: i32>(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sli, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -24453,7 +24453,7 @@ pub fn vsliq_n_s16<const N: i32>(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sli, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -24471,7 +24471,7 @@ pub fn vsli_n_s32<const N: i32>(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sli, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -24489,7 +24489,7 @@ pub fn vsliq_n_s32<const N: i32>(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sli, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -24507,7 +24507,7 @@ pub fn vsli_n_s64<const N: i32>(a: int64x1_t, b: int64x1_t) -> int64x1_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sli, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -24525,7 +24525,7 @@ pub fn vsliq_n_s64<const N: i32>(a: int64x2_t, b: int64x2_t) -> int64x2_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sli, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -24536,7 +24536,7 @@ pub fn vsli_n_u8<const N: i32>(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sli, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -24547,7 +24547,7 @@ pub fn vsliq_n_u8<const N: i32>(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sli, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -24558,7 +24558,7 @@ pub fn vsli_n_u16<const N: i32>(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sli, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -24569,7 +24569,7 @@ pub fn vsliq_n_u16<const N: i32>(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sli, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -24580,7 +24580,7 @@ pub fn vsli_n_u32<const N: i32>(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sli, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -24591,7 +24591,7 @@ pub fn vsliq_n_u32<const N: i32>(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sli, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -24602,7 +24602,7 @@ pub fn vsli_n_u64<const N: i32>(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sli, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -24613,7 +24613,7 @@ pub fn vsliq_n_u64<const N: i32>(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sli, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -24624,7 +24624,7 @@ pub fn vsli_n_p8<const N: i32>(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sli, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -24635,7 +24635,7 @@ pub fn vsliq_n_p8<const N: i32>(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_p16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sli, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -24646,7 +24646,7 @@ pub fn vsli_n_p16<const N: i32>(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_p16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sli, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -24657,7 +24657,7 @@ pub fn vsliq_n_p16<const N: i32>(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_p64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(test, assert_instr(sli, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -24668,7 +24668,7 @@ pub fn vsli_n_p64<const N: i32>(a: poly64x1_t, b: poly64x1_t) -> poly64x1_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_p64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(test, assert_instr(sli, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -24679,7 +24679,7 @@ pub fn vsliq_n_p64<const N: i32>(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t {
 }
 #[doc = "Shift left and insert"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vslid_n_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[rustc_legacy_const_generics(2)]
@@ -24690,7 +24690,7 @@ pub fn vslid_n_s64<const N: i32>(a: i64, b: i64) -> i64 {
 }
 #[doc = "Shift left and insert"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vslid_n_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[rustc_legacy_const_generics(2)]
@@ -24701,7 +24701,7 @@ pub fn vslid_n_u64<const N: i32>(a: u64, b: u64) -> u64 {
 }
 #[doc = "SM3PARTW1"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsm3partw1q_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,sm4")]
 #[cfg_attr(test, assert_instr(sm3partw1))]
 #[unstable(feature = "stdarch_neon_sm4", issue = "117226")]
@@ -24717,7 +24717,7 @@ pub fn vsm3partw1q_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_
 }
 #[doc = "SM3PARTW2"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsm3partw2q_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,sm4")]
 #[cfg_attr(test, assert_instr(sm3partw2))]
 #[unstable(feature = "stdarch_neon_sm4", issue = "117226")]
@@ -24733,7 +24733,7 @@ pub fn vsm3partw2q_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_
 }
 #[doc = "SM3SS1"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsm3ss1q_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,sm4")]
 #[cfg_attr(test, assert_instr(sm3ss1))]
 #[unstable(feature = "stdarch_neon_sm4", issue = "117226")]
@@ -24749,7 +24749,7 @@ pub fn vsm3ss1q_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "SM3TT1A"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsm3tt1aq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,sm4")]
 #[cfg_attr(test, assert_instr(sm3tt1a, IMM2 = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -24767,7 +24767,7 @@ pub fn vsm3tt1aq_u32<const IMM2: i32>(a: uint32x4_t, b: uint32x4_t, c: uint32x4_
 }
 #[doc = "SM3TT1B"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsm3tt1bq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,sm4")]
 #[cfg_attr(test, assert_instr(sm3tt1b, IMM2 = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -24785,7 +24785,7 @@ pub fn vsm3tt1bq_u32<const IMM2: i32>(a: uint32x4_t, b: uint32x4_t, c: uint32x4_
 }
 #[doc = "SM3TT2A"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsm3tt2aq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,sm4")]
 #[cfg_attr(test, assert_instr(sm3tt2a, IMM2 = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -24803,7 +24803,7 @@ pub fn vsm3tt2aq_u32<const IMM2: i32>(a: uint32x4_t, b: uint32x4_t, c: uint32x4_
 }
 #[doc = "SM3TT2B"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsm3tt2bq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,sm4")]
 #[cfg_attr(test, assert_instr(sm3tt2b, IMM2 = 0))]
 #[rustc_legacy_const_generics(3)]
@@ -24821,7 +24821,7 @@ pub fn vsm3tt2bq_u32<const IMM2: i32>(a: uint32x4_t, b: uint32x4_t, c: uint32x4_
 }
 #[doc = "SM4 key"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsm4ekeyq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,sm4")]
 #[cfg_attr(test, assert_instr(sm4ekey))]
 #[unstable(feature = "stdarch_neon_sm4", issue = "117226")]
@@ -24837,7 +24837,7 @@ pub fn vsm4ekeyq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "SM4 encode"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsm4eq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,sm4")]
 #[cfg_attr(test, assert_instr(sm4e))]
 #[unstable(feature = "stdarch_neon_sm4", issue = "117226")]
@@ -24853,7 +24853,7 @@ pub fn vsm4eq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Unsigned saturating Accumulate of Signed value."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqadd_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(usqadd))]
@@ -24869,7 +24869,7 @@ pub fn vsqadd_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t {
 }
 #[doc = "Unsigned saturating Accumulate of Signed value."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqaddq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(usqadd))]
@@ -24885,7 +24885,7 @@ pub fn vsqaddq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t {
 }
 #[doc = "Unsigned saturating Accumulate of Signed value."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqadd_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(usqadd))]
@@ -24901,7 +24901,7 @@ pub fn vsqadd_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t {
 }
 #[doc = "Unsigned saturating Accumulate of Signed value."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqaddq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(usqadd))]
@@ -24917,7 +24917,7 @@ pub fn vsqaddq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t {
 }
 #[doc = "Unsigned saturating Accumulate of Signed value."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqadd_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(usqadd))]
@@ -24933,7 +24933,7 @@ pub fn vsqadd_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t {
 }
 #[doc = "Unsigned saturating Accumulate of Signed value."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqaddq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(usqadd))]
@@ -24949,7 +24949,7 @@ pub fn vsqaddq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t {
 }
 #[doc = "Unsigned saturating Accumulate of Signed value."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqadd_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(usqadd))]
@@ -24965,7 +24965,7 @@ pub fn vsqadd_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t {
 }
 #[doc = "Unsigned saturating Accumulate of Signed value."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqaddq_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(usqadd))]
@@ -24981,7 +24981,7 @@ pub fn vsqaddq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t {
 }
 #[doc = "Unsigned saturating accumulate of signed value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqaddb_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(usqadd))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -24990,7 +24990,7 @@ pub fn vsqaddb_u8(a: u8, b: i8) -> u8 {
 }
 #[doc = "Unsigned saturating accumulate of signed value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqaddh_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(usqadd))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -24999,7 +24999,7 @@ pub fn vsqaddh_u16(a: u16, b: i16) -> u16 {
 }
 #[doc = "Unsigned saturating accumulate of signed value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqaddd_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(usqadd))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -25015,7 +25015,7 @@ pub fn vsqaddd_u64(a: u64, b: i64) -> u64 {
 }
 #[doc = "Unsigned saturating accumulate of signed value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqadds_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(usqadd))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -25031,7 +25031,7 @@ pub fn vsqadds_u32(a: u32, b: i32) -> u32 {
 }
 #[doc = "Calculates the square root of each lane."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqrt_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fsqrt))]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
@@ -25041,7 +25041,7 @@ pub fn vsqrt_f16(a: float16x4_t) -> float16x4_t {
 }
 #[doc = "Calculates the square root of each lane."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqrtq_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(test, assert_instr(fsqrt))]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
@@ -25051,7 +25051,7 @@ pub fn vsqrtq_f16(a: float16x8_t) -> float16x8_t {
 }
 #[doc = "Calculates the square root of each lane."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqrt_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fsqrt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -25060,7 +25060,7 @@ pub fn vsqrt_f32(a: float32x2_t) -> float32x2_t {
 }
 #[doc = "Calculates the square root of each lane."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqrtq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fsqrt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -25069,7 +25069,7 @@ pub fn vsqrtq_f32(a: float32x4_t) -> float32x4_t {
 }
 #[doc = "Calculates the square root of each lane."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqrt_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fsqrt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -25078,7 +25078,7 @@ pub fn vsqrt_f64(a: float64x1_t) -> float64x1_t {
 }
 #[doc = "Calculates the square root of each lane."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqrtq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(fsqrt))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -25087,7 +25087,7 @@ pub fn vsqrtq_f64(a: float64x2_t) -> float64x2_t {
 }
 #[doc = "Floating-point round to integral, using current rounding mode"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqrth_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -25097,7 +25097,7 @@ pub fn vsqrth_f16(a: f16) -> f16 {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sri, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -25115,7 +25115,7 @@ pub fn vsri_n_s8<const N: i32>(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sri, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -25133,7 +25133,7 @@ pub fn vsriq_n_s8<const N: i32>(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sri, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -25151,7 +25151,7 @@ pub fn vsri_n_s16<const N: i32>(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sri, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -25169,7 +25169,7 @@ pub fn vsriq_n_s16<const N: i32>(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sri, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -25187,7 +25187,7 @@ pub fn vsri_n_s32<const N: i32>(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sri, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -25205,7 +25205,7 @@ pub fn vsriq_n_s32<const N: i32>(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sri, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -25223,7 +25223,7 @@ pub fn vsri_n_s64<const N: i32>(a: int64x1_t, b: int64x1_t) -> int64x1_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sri, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -25241,7 +25241,7 @@ pub fn vsriq_n_s64<const N: i32>(a: int64x2_t, b: int64x2_t) -> int64x2_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sri, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -25252,7 +25252,7 @@ pub fn vsri_n_u8<const N: i32>(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sri, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -25263,7 +25263,7 @@ pub fn vsriq_n_u8<const N: i32>(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sri, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -25274,7 +25274,7 @@ pub fn vsri_n_u16<const N: i32>(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sri, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -25285,7 +25285,7 @@ pub fn vsriq_n_u16<const N: i32>(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sri, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -25296,7 +25296,7 @@ pub fn vsri_n_u32<const N: i32>(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sri, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -25307,7 +25307,7 @@ pub fn vsriq_n_u32<const N: i32>(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sri, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -25318,7 +25318,7 @@ pub fn vsri_n_u64<const N: i32>(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sri, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -25329,7 +25329,7 @@ pub fn vsriq_n_u64<const N: i32>(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sri, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -25340,7 +25340,7 @@ pub fn vsri_n_p8<const N: i32>(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sri, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -25351,7 +25351,7 @@ pub fn vsriq_n_p8<const N: i32>(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_p16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sri, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -25362,7 +25362,7 @@ pub fn vsri_n_p16<const N: i32>(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_p16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(sri, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -25373,7 +25373,7 @@ pub fn vsriq_n_p16<const N: i32>(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_p64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(test, assert_instr(sri, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -25384,7 +25384,7 @@ pub fn vsri_n_p64<const N: i32>(a: poly64x1_t, b: poly64x1_t) -> poly64x1_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_p64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(test, assert_instr(sri, N = 1))]
 #[rustc_legacy_const_generics(2)]
@@ -25395,7 +25395,7 @@ pub fn vsriq_n_p64<const N: i32>(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t {
 }
 #[doc = "Shift right and insert"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsrid_n_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[rustc_legacy_const_generics(2)]
@@ -25406,7 +25406,7 @@ pub fn vsrid_n_s64<const N: i32>(a: i64, b: i64) -> i64 {
 }
 #[doc = "Shift right and insert"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsrid_n_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[rustc_legacy_const_generics(2)]
@@ -25419,7 +25419,7 @@ pub fn vsrid_n_u64<const N: i32>(a: u64, b: u64) -> u64 {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(test, assert_instr(str))]
 #[allow(clippy::cast_ptr_alignment)]
@@ -25432,7 +25432,7 @@ pub unsafe fn vst1_f16(ptr: *mut f16, a: float16x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(test, assert_instr(str))]
 #[allow(clippy::cast_ptr_alignment)]
@@ -25445,7 +25445,7 @@ pub unsafe fn vst1q_f16(ptr: *mut f16, a: float16x8_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
 #[allow(clippy::cast_ptr_alignment)]
@@ -25457,7 +25457,7 @@ pub unsafe fn vst1_f32(ptr: *mut f32, a: float32x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
 #[allow(clippy::cast_ptr_alignment)]
@@ -25469,7 +25469,7 @@ pub unsafe fn vst1q_f32(ptr: *mut f32, a: float32x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
 #[allow(clippy::cast_ptr_alignment)]
@@ -25481,7 +25481,7 @@ pub unsafe fn vst1_f64(ptr: *mut f64, a: float64x1_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
 #[allow(clippy::cast_ptr_alignment)]
@@ -25493,7 +25493,7 @@ pub unsafe fn vst1q_f64(ptr: *mut f64, a: float64x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
 #[allow(clippy::cast_ptr_alignment)]
@@ -25505,7 +25505,7 @@ pub unsafe fn vst1_s8(ptr: *mut i8, a: int8x8_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
 #[allow(clippy::cast_ptr_alignment)]
@@ -25517,7 +25517,7 @@ pub unsafe fn vst1q_s8(ptr: *mut i8, a: int8x16_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
 #[allow(clippy::cast_ptr_alignment)]
@@ -25529,7 +25529,7 @@ pub unsafe fn vst1_s16(ptr: *mut i16, a: int16x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
 #[allow(clippy::cast_ptr_alignment)]
@@ -25541,7 +25541,7 @@ pub unsafe fn vst1q_s16(ptr: *mut i16, a: int16x8_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
 #[allow(clippy::cast_ptr_alignment)]
@@ -25553,7 +25553,7 @@ pub unsafe fn vst1_s32(ptr: *mut i32, a: int32x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
 #[allow(clippy::cast_ptr_alignment)]
@@ -25565,7 +25565,7 @@ pub unsafe fn vst1q_s32(ptr: *mut i32, a: int32x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
 #[allow(clippy::cast_ptr_alignment)]
@@ -25577,7 +25577,7 @@ pub unsafe fn vst1_s64(ptr: *mut i64, a: int64x1_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
 #[allow(clippy::cast_ptr_alignment)]
@@ -25589,7 +25589,7 @@ pub unsafe fn vst1q_s64(ptr: *mut i64, a: int64x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
 #[allow(clippy::cast_ptr_alignment)]
@@ -25601,7 +25601,7 @@ pub unsafe fn vst1_u8(ptr: *mut u8, a: uint8x8_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
 #[allow(clippy::cast_ptr_alignment)]
@@ -25613,7 +25613,7 @@ pub unsafe fn vst1q_u8(ptr: *mut u8, a: uint8x16_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
 #[allow(clippy::cast_ptr_alignment)]
@@ -25625,7 +25625,7 @@ pub unsafe fn vst1_u16(ptr: *mut u16, a: uint16x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
 #[allow(clippy::cast_ptr_alignment)]
@@ -25637,7 +25637,7 @@ pub unsafe fn vst1q_u16(ptr: *mut u16, a: uint16x8_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
 #[allow(clippy::cast_ptr_alignment)]
@@ -25649,7 +25649,7 @@ pub unsafe fn vst1_u32(ptr: *mut u32, a: uint32x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
 #[allow(clippy::cast_ptr_alignment)]
@@ -25661,7 +25661,7 @@ pub unsafe fn vst1q_u32(ptr: *mut u32, a: uint32x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
 #[allow(clippy::cast_ptr_alignment)]
@@ -25673,7 +25673,7 @@ pub unsafe fn vst1_u64(ptr: *mut u64, a: uint64x1_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
 #[allow(clippy::cast_ptr_alignment)]
@@ -25685,7 +25685,7 @@ pub unsafe fn vst1q_u64(ptr: *mut u64, a: uint64x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
 #[allow(clippy::cast_ptr_alignment)]
@@ -25697,7 +25697,7 @@ pub unsafe fn vst1_p8(ptr: *mut p8, a: poly8x8_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
 #[allow(clippy::cast_ptr_alignment)]
@@ -25709,7 +25709,7 @@ pub unsafe fn vst1q_p8(ptr: *mut p8, a: poly8x16_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
 #[allow(clippy::cast_ptr_alignment)]
@@ -25721,7 +25721,7 @@ pub unsafe fn vst1_p16(ptr: *mut p16, a: poly16x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
 #[allow(clippy::cast_ptr_alignment)]
@@ -25733,7 +25733,7 @@ pub unsafe fn vst1q_p16(ptr: *mut p16, a: poly16x8_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(test, assert_instr(str))]
 #[allow(clippy::cast_ptr_alignment)]
@@ -25745,7 +25745,7 @@ pub unsafe fn vst1_p64(ptr: *mut p64, a: poly64x1_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(test, assert_instr(str))]
 #[allow(clippy::cast_ptr_alignment)]
@@ -25757,7 +25757,7 @@ pub unsafe fn vst1q_p64(ptr: *mut p64, a: poly64x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f64_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st1))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -25775,7 +25775,7 @@ pub unsafe fn vst1_f64_x2(a: *mut f64, b: float64x1x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f64_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st1))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -25793,7 +25793,7 @@ pub unsafe fn vst1q_f64_x2(a: *mut f64, b: float64x2x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f64_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st1))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -25811,7 +25811,7 @@ pub unsafe fn vst1_f64_x3(a: *mut f64, b: float64x1x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f64_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st1))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -25829,7 +25829,7 @@ pub unsafe fn vst1q_f64_x3(a: *mut f64, b: float64x2x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f64_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st1))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -25853,7 +25853,7 @@ pub unsafe fn vst1_f64_x4(a: *mut f64, b: float64x1x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f64_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st1))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -25877,7 +25877,7 @@ pub unsafe fn vst1q_f64_x4(a: *mut f64, b: float64x2x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(nop, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -25890,7 +25890,7 @@ pub unsafe fn vst1_lane_f64<const LANE: i32>(a: *mut f64, b: float64x1_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(nop, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -25903,7 +25903,7 @@ pub unsafe fn vst1q_lane_f64<const LANE: i32>(a: *mut f64, b: float64x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(st1))]
@@ -25921,7 +25921,7 @@ pub unsafe fn vst2_f64(a: *mut f64, b: float64x1x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st2, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -25941,7 +25941,7 @@ pub unsafe fn vst2_lane_f64<const LANE: i32>(a: *mut f64, b: float64x1x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st2, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -25961,7 +25961,7 @@ pub unsafe fn vst2_lane_s64<const LANE: i32>(a: *mut i64, b: int64x1x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(test, assert_instr(st2, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -25974,7 +25974,7 @@ pub unsafe fn vst2_lane_p64<const LANE: i32>(a: *mut p64, b: poly64x1x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st2, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -25987,7 +25987,7 @@ pub unsafe fn vst2_lane_u64<const LANE: i32>(a: *mut u64, b: uint64x1x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(st2))]
@@ -26005,7 +26005,7 @@ pub unsafe fn vst2q_f64(a: *mut f64, b: float64x2x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(st2))]
@@ -26023,7 +26023,7 @@ pub unsafe fn vst2q_s64(a: *mut i64, b: int64x2x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st2, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -26043,7 +26043,7 @@ pub unsafe fn vst2q_lane_f64<const LANE: i32>(a: *mut f64, b: float64x2x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st2, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -26063,7 +26063,7 @@ pub unsafe fn vst2q_lane_s8<const LANE: i32>(a: *mut i8, b: int8x16x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st2, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -26083,7 +26083,7 @@ pub unsafe fn vst2q_lane_s64<const LANE: i32>(a: *mut i64, b: int64x2x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(test, assert_instr(st2, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -26096,7 +26096,7 @@ pub unsafe fn vst2q_lane_p64<const LANE: i32>(a: *mut p64, b: poly64x2x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st2, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -26109,7 +26109,7 @@ pub unsafe fn vst2q_lane_u8<const LANE: i32>(a: *mut u8, b: uint8x16x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st2, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -26122,7 +26122,7 @@ pub unsafe fn vst2q_lane_u64<const LANE: i32>(a: *mut u64, b: uint64x2x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st2, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -26135,7 +26135,7 @@ pub unsafe fn vst2q_lane_p8<const LANE: i32>(a: *mut p8, b: poly8x16x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(test, assert_instr(st2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -26146,7 +26146,7 @@ pub unsafe fn vst2q_p64(a: *mut p64, b: poly64x2x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(st2))]
@@ -26157,7 +26157,7 @@ pub unsafe fn vst2q_u64(a: *mut u64, b: uint64x2x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(nop))]
@@ -26175,7 +26175,7 @@ pub unsafe fn vst3_f64(a: *mut f64, b: float64x1x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st3, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -26195,7 +26195,7 @@ pub unsafe fn vst3_lane_f64<const LANE: i32>(a: *mut f64, b: float64x1x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st3, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -26215,7 +26215,7 @@ pub unsafe fn vst3_lane_s64<const LANE: i32>(a: *mut i64, b: int64x1x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(test, assert_instr(st3, LANE = 0))]
@@ -26228,7 +26228,7 @@ pub unsafe fn vst3_lane_p64<const LANE: i32>(a: *mut p64, b: poly64x1x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(st3, LANE = 0))]
@@ -26241,7 +26241,7 @@ pub unsafe fn vst3_lane_u64<const LANE: i32>(a: *mut u64, b: uint64x1x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(st3))]
@@ -26259,7 +26259,7 @@ pub unsafe fn vst3q_f64(a: *mut f64, b: float64x2x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(st3))]
@@ -26277,7 +26277,7 @@ pub unsafe fn vst3q_s64(a: *mut i64, b: int64x2x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st3, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -26297,7 +26297,7 @@ pub unsafe fn vst3q_lane_f64<const LANE: i32>(a: *mut f64, b: float64x2x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st3, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -26317,7 +26317,7 @@ pub unsafe fn vst3q_lane_s8<const LANE: i32>(a: *mut i8, b: int8x16x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st3, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -26337,7 +26337,7 @@ pub unsafe fn vst3q_lane_s64<const LANE: i32>(a: *mut i64, b: int64x2x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(test, assert_instr(st3, LANE = 0))]
@@ -26350,7 +26350,7 @@ pub unsafe fn vst3q_lane_p64<const LANE: i32>(a: *mut p64, b: poly64x2x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(st3, LANE = 0))]
@@ -26363,7 +26363,7 @@ pub unsafe fn vst3q_lane_u8<const LANE: i32>(a: *mut u8, b: uint8x16x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(st3, LANE = 0))]
@@ -26376,7 +26376,7 @@ pub unsafe fn vst3q_lane_u64<const LANE: i32>(a: *mut u64, b: uint64x2x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(st3, LANE = 0))]
@@ -26389,7 +26389,7 @@ pub unsafe fn vst3q_lane_p8<const LANE: i32>(a: *mut p8, b: poly8x16x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(test, assert_instr(st3))]
@@ -26400,7 +26400,7 @@ pub unsafe fn vst3q_p64(a: *mut p64, b: poly64x2x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(st3))]
@@ -26411,7 +26411,7 @@ pub unsafe fn vst3q_u64(a: *mut u64, b: uint64x2x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(nop))]
@@ -26429,7 +26429,7 @@ pub unsafe fn vst4_f64(a: *mut f64, b: float64x1x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st4, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -26456,7 +26456,7 @@ pub unsafe fn vst4_lane_f64<const LANE: i32>(a: *mut f64, b: float64x1x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st4, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -26483,7 +26483,7 @@ pub unsafe fn vst4_lane_s64<const LANE: i32>(a: *mut i64, b: int64x1x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(test, assert_instr(st4, LANE = 0))]
@@ -26496,7 +26496,7 @@ pub unsafe fn vst4_lane_p64<const LANE: i32>(a: *mut p64, b: poly64x1x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(st4, LANE = 0))]
@@ -26509,7 +26509,7 @@ pub unsafe fn vst4_lane_u64<const LANE: i32>(a: *mut u64, b: uint64x1x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(st4))]
@@ -26527,7 +26527,7 @@ pub unsafe fn vst4q_f64(a: *mut f64, b: float64x2x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(st4))]
@@ -26545,7 +26545,7 @@ pub unsafe fn vst4q_s64(a: *mut i64, b: int64x2x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st4, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -26572,7 +26572,7 @@ pub unsafe fn vst4q_lane_f64<const LANE: i32>(a: *mut f64, b: float64x2x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st4, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -26599,7 +26599,7 @@ pub unsafe fn vst4q_lane_s8<const LANE: i32>(a: *mut i8, b: int8x16x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st4, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -26626,7 +26626,7 @@ pub unsafe fn vst4q_lane_s64<const LANE: i32>(a: *mut i64, b: int64x2x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(test, assert_instr(st4, LANE = 0))]
@@ -26639,7 +26639,7 @@ pub unsafe fn vst4q_lane_p64<const LANE: i32>(a: *mut p64, b: poly64x2x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(st4, LANE = 0))]
@@ -26652,7 +26652,7 @@ pub unsafe fn vst4q_lane_u8<const LANE: i32>(a: *mut u8, b: uint8x16x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(st4, LANE = 0))]
@@ -26665,7 +26665,7 @@ pub unsafe fn vst4q_lane_u64<const LANE: i32>(a: *mut u64, b: uint64x2x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(st4, LANE = 0))]
@@ -26678,7 +26678,7 @@ pub unsafe fn vst4q_lane_p8<const LANE: i32>(a: *mut p8, b: poly8x16x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(test, assert_instr(st4))]
@@ -26689,7 +26689,7 @@ pub unsafe fn vst4q_p64(a: *mut p64, b: poly64x2x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(st4))]
@@ -26698,7 +26698,7 @@ pub unsafe fn vst4q_u64(a: *mut u64, b: uint64x2x4_t) {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fsub))]
@@ -26707,7 +26707,7 @@ pub fn vsub_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fsub))]
@@ -26716,7 +26716,7 @@ pub fn vsubq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubd_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sub))]
@@ -26725,7 +26725,7 @@ pub fn vsubd_s64(a: i64, b: i64) -> i64 {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubd_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sub))]
@@ -26734,7 +26734,7 @@ pub fn vsubd_u64(a: u64, b: u64) -> u64 {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubh_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -26744,7 +26744,7 @@ pub fn vsubh_f16(a: f16, b: f16) -> f16 {
 }
 #[doc = "Signed Subtract Long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_high_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(ssubl2))]
@@ -26759,7 +26759,7 @@ pub fn vsubl_high_s8(a: int8x16_t, b: int8x16_t) -> int16x8_t {
 }
 #[doc = "Signed Subtract Long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_high_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(ssubl2))]
@@ -26774,7 +26774,7 @@ pub fn vsubl_high_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t {
 }
 #[doc = "Signed Subtract Long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_high_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(ssubl2))]
@@ -26789,7 +26789,7 @@ pub fn vsubl_high_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t {
 }
 #[doc = "Unsigned Subtract Long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_high_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(usubl2))]
@@ -26804,7 +26804,7 @@ pub fn vsubl_high_u8(a: uint8x16_t, b: uint8x16_t) -> uint16x8_t {
 }
 #[doc = "Unsigned Subtract Long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_high_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(usubl2))]
@@ -26819,7 +26819,7 @@ pub fn vsubl_high_u16(a: uint16x8_t, b: uint16x8_t) -> uint32x4_t {
 }
 #[doc = "Unsigned Subtract Long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_high_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(usubl2))]
@@ -26834,7 +26834,7 @@ pub fn vsubl_high_u32(a: uint32x4_t, b: uint32x4_t) -> uint64x2_t {
 }
 #[doc = "Signed Subtract Wide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_high_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(ssubw2))]
@@ -26846,7 +26846,7 @@ pub fn vsubw_high_s8(a: int16x8_t, b: int8x16_t) -> int16x8_t {
 }
 #[doc = "Signed Subtract Wide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_high_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(ssubw2))]
@@ -26858,7 +26858,7 @@ pub fn vsubw_high_s16(a: int32x4_t, b: int16x8_t) -> int32x4_t {
 }
 #[doc = "Signed Subtract Wide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_high_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(ssubw2))]
@@ -26870,7 +26870,7 @@ pub fn vsubw_high_s32(a: int64x2_t, b: int32x4_t) -> int64x2_t {
 }
 #[doc = "Unsigned Subtract Wide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_high_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(usubw2))]
@@ -26882,7 +26882,7 @@ pub fn vsubw_high_u8(a: uint16x8_t, b: uint8x16_t) -> uint16x8_t {
 }
 #[doc = "Unsigned Subtract Wide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_high_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(usubw2))]
@@ -26894,7 +26894,7 @@ pub fn vsubw_high_u16(a: uint32x4_t, b: uint16x8_t) -> uint32x4_t {
 }
 #[doc = "Unsigned Subtract Wide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_high_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(usubw2))]
@@ -26906,7 +26906,7 @@ pub fn vsubw_high_u32(a: uint64x2_t, b: uint32x4_t) -> uint64x2_t {
 }
 #[doc = "Dot product index form with signed and unsigned integers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsudot_laneq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,i8mm")]
 #[cfg_attr(test, assert_instr(sudot, LANE = 3))]
 #[rustc_legacy_const_generics(3)]
@@ -26921,7 +26921,7 @@ pub fn vsudot_laneq_s32<const LANE: i32>(a: int32x2_t, b: int8x8_t, c: uint8x16_
 }
 #[doc = "Dot product index form with signed and unsigned integers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsudotq_laneq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,i8mm")]
 #[cfg_attr(test, assert_instr(sudot, LANE = 3))]
 #[rustc_legacy_const_generics(3)]
@@ -26937,7 +26937,7 @@ pub fn vsudotq_laneq_s32<const LANE: i32>(a: int32x4_t, b: int8x16_t, c: uint8x1
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl1_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -26950,7 +26950,7 @@ pub fn vtbl1_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl1_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -26959,7 +26959,7 @@ pub fn vtbl1_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl1_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -26968,7 +26968,7 @@ pub fn vtbl1_p8(a: poly8x8_t, b: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -26977,7 +26977,7 @@ pub fn vtbl2_s8(a: int8x8x2_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
@@ -26987,7 +26987,7 @@ pub fn vtbl2_u8(a: uint8x8x2_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
@@ -27004,7 +27004,7 @@ pub fn vtbl2_u8(a: uint8x8x2_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
@@ -27014,7 +27014,7 @@ pub fn vtbl2_p8(a: poly8x8x2_t, b: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
@@ -27031,7 +27031,7 @@ pub fn vtbl2_p8(a: poly8x8x2_t, b: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -27044,7 +27044,7 @@ pub fn vtbl3_s8(a: int8x8x3_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
@@ -27058,7 +27058,7 @@ pub fn vtbl3_u8(a: uint8x8x3_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
@@ -27080,7 +27080,7 @@ pub fn vtbl3_u8(a: uint8x8x3_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
@@ -27094,7 +27094,7 @@ pub fn vtbl3_p8(a: poly8x8x3_t, b: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
@@ -27116,7 +27116,7 @@ pub fn vtbl3_p8(a: poly8x8x3_t, b: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -27126,7 +27126,7 @@ pub fn vtbl4_s8(a: int8x8x4_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
@@ -27137,7 +27137,7 @@ pub fn vtbl4_u8(a: uint8x8x4_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
@@ -27157,7 +27157,7 @@ pub fn vtbl4_u8(a: uint8x8x4_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
@@ -27168,7 +27168,7 @@ pub fn vtbl4_p8(a: poly8x8x4_t, b: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbl))]
@@ -27188,7 +27188,7 @@ pub fn vtbl4_p8(a: poly8x8x4_t, b: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx1_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -27207,7 +27207,7 @@ pub fn vtbx1_s8(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx1_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -27226,7 +27226,7 @@ pub fn vtbx1_u8(a: uint8x8_t, b: uint8x8_t, c: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx1_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -27245,7 +27245,7 @@ pub fn vtbx1_p8(a: poly8x8_t, b: poly8x8_t, c: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -27254,7 +27254,7 @@ pub fn vtbx2_s8(a: int8x8_t, b: int8x8x2_t, c: int8x8_t) -> int8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
@@ -27264,7 +27264,7 @@ pub fn vtbx2_u8(a: uint8x8_t, b: uint8x8x2_t, c: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
@@ -27283,7 +27283,7 @@ pub fn vtbx2_u8(a: uint8x8_t, b: uint8x8x2_t, c: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
@@ -27293,7 +27293,7 @@ pub fn vtbx2_p8(a: poly8x8_t, b: poly8x8x2_t, c: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
@@ -27312,7 +27312,7 @@ pub fn vtbx2_p8(a: poly8x8_t, b: poly8x8x2_t, c: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -27336,7 +27336,7 @@ pub fn vtbx3_s8(a: int8x8_t, b: int8x8x3_t, c: int8x8_t) -> int8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
@@ -27356,7 +27356,7 @@ pub fn vtbx3_u8(a: uint8x8_t, b: uint8x8x3_t, c: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
@@ -27383,7 +27383,7 @@ pub fn vtbx3_u8(a: uint8x8_t, b: uint8x8x3_t, c: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
@@ -27403,7 +27403,7 @@ pub fn vtbx3_p8(a: poly8x8_t, b: poly8x8x3_t, c: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
@@ -27430,7 +27430,7 @@ pub fn vtbx3_p8(a: poly8x8_t, b: poly8x8x3_t, c: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -27446,7 +27446,7 @@ pub fn vtbx4_s8(a: int8x8_t, b: int8x8x4_t, c: int8x8_t) -> int8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
@@ -27463,7 +27463,7 @@ pub fn vtbx4_u8(a: uint8x8_t, b: uint8x8x4_t, c: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
@@ -27488,7 +27488,7 @@ pub fn vtbx4_u8(a: uint8x8_t, b: uint8x8x4_t, c: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
@@ -27505,7 +27505,7 @@ pub fn vtbx4_p8(a: poly8x8_t, b: poly8x8x4_t, c: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tbx))]
@@ -27530,7 +27530,7 @@ pub fn vtbx4_p8(a: poly8x8_t, b: poly8x8x4_t, c: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -27540,7 +27540,7 @@ pub fn vtrn1_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -27550,7 +27550,7 @@ pub fn vtrn1q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
@@ -27559,7 +27559,7 @@ pub fn vtrn1_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
@@ -27568,7 +27568,7 @@ pub fn vtrn1q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
@@ -27577,7 +27577,7 @@ pub fn vtrn1_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
@@ -27586,7 +27586,7 @@ pub fn vtrn1q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
@@ -27595,7 +27595,7 @@ pub fn vtrn1_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
@@ -27604,7 +27604,7 @@ pub fn vtrn1q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_p64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
@@ -27613,7 +27613,7 @@ pub fn vtrn1q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))]
@@ -27622,7 +27622,7 @@ pub fn vtrn1q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))]
@@ -27631,7 +27631,7 @@ pub fn vtrn1_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))]
@@ -27646,7 +27646,7 @@ pub fn vtrn1q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))]
@@ -27655,7 +27655,7 @@ pub fn vtrn1_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))]
@@ -27664,7 +27664,7 @@ pub fn vtrn1q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))]
@@ -27673,7 +27673,7 @@ pub fn vtrn1q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))]
@@ -27682,7 +27682,7 @@ pub fn vtrn1_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))]
@@ -27697,7 +27697,7 @@ pub fn vtrn1q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))]
@@ -27706,7 +27706,7 @@ pub fn vtrn1_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))]
@@ -27715,7 +27715,7 @@ pub fn vtrn1q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))]
@@ -27724,7 +27724,7 @@ pub fn vtrn1q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))]
@@ -27733,7 +27733,7 @@ pub fn vtrn1_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))]
@@ -27748,7 +27748,7 @@ pub fn vtrn1q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_p16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))]
@@ -27757,7 +27757,7 @@ pub fn vtrn1_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_p16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))]
@@ -27766,7 +27766,7 @@ pub fn vtrn1q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -27776,7 +27776,7 @@ pub fn vtrn2_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -27786,7 +27786,7 @@ pub fn vtrn2q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
@@ -27795,7 +27795,7 @@ pub fn vtrn2_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
@@ -27804,7 +27804,7 @@ pub fn vtrn2q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
@@ -27813,7 +27813,7 @@ pub fn vtrn2_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
@@ -27822,7 +27822,7 @@ pub fn vtrn2q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
@@ -27831,7 +27831,7 @@ pub fn vtrn2_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
@@ -27840,7 +27840,7 @@ pub fn vtrn2q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_p64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
@@ -27849,7 +27849,7 @@ pub fn vtrn2q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))]
@@ -27858,7 +27858,7 @@ pub fn vtrn2q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))]
@@ -27867,7 +27867,7 @@ pub fn vtrn2_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))]
@@ -27882,7 +27882,7 @@ pub fn vtrn2q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))]
@@ -27891,7 +27891,7 @@ pub fn vtrn2_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))]
@@ -27900,7 +27900,7 @@ pub fn vtrn2q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))]
@@ -27909,7 +27909,7 @@ pub fn vtrn2q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))]
@@ -27918,7 +27918,7 @@ pub fn vtrn2_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))]
@@ -27933,7 +27933,7 @@ pub fn vtrn2q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))]
@@ -27942,7 +27942,7 @@ pub fn vtrn2_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))]
@@ -27951,7 +27951,7 @@ pub fn vtrn2q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))]
@@ -27960,7 +27960,7 @@ pub fn vtrn2q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))]
@@ -27969,7 +27969,7 @@ pub fn vtrn2_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))]
@@ -27984,7 +27984,7 @@ pub fn vtrn2q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_p16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))]
@@ -27993,7 +27993,7 @@ pub fn vtrn2_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t {
 }
 #[doc = "Transpose vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_p16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))]
@@ -28002,7 +28002,7 @@ pub fn vtrn2q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t {
 }
 #[doc = "Signed compare bitwise Test bits nonzero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmtst))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -28015,7 +28015,7 @@ pub fn vtst_s64(a: int64x1_t, b: int64x1_t) -> uint64x1_t {
 }
 #[doc = "Signed compare bitwise Test bits nonzero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmtst))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -28028,7 +28028,7 @@ pub fn vtstq_s64(a: int64x2_t, b: int64x2_t) -> uint64x2_t {
 }
 #[doc = "Signed compare bitwise Test bits nonzero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_p64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmtst))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -28041,7 +28041,7 @@ pub fn vtst_p64(a: poly64x1_t, b: poly64x1_t) -> uint64x1_t {
 }
 #[doc = "Signed compare bitwise Test bits nonzero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_p64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmtst))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -28054,7 +28054,7 @@ pub fn vtstq_p64(a: poly64x2_t, b: poly64x2_t) -> uint64x2_t {
 }
 #[doc = "Unsigned compare bitwise Test bits nonzero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmtst))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -28067,7 +28067,7 @@ pub fn vtst_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
 }
 #[doc = "Unsigned compare bitwise Test bits nonzero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(cmtst))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -28080,7 +28080,7 @@ pub fn vtstq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Compare bitwise test bits nonzero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstd_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tst))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -28089,7 +28089,7 @@ pub fn vtstd_s64(a: i64, b: i64) -> u64 {
 }
 #[doc = "Compare bitwise test bits nonzero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstd_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(tst))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -28098,7 +28098,7 @@ pub fn vtstd_u64(a: u64, b: u64) -> u64 {
 }
 #[doc = "Signed saturating Accumulate of Unsigned value."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuqadd_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(suqadd))]
@@ -28114,7 +28114,7 @@ pub fn vuqadd_s8(a: int8x8_t, b: uint8x8_t) -> int8x8_t {
 }
 #[doc = "Signed saturating Accumulate of Unsigned value."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuqaddq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(suqadd))]
@@ -28130,7 +28130,7 @@ pub fn vuqaddq_s8(a: int8x16_t, b: uint8x16_t) -> int8x16_t {
 }
 #[doc = "Signed saturating Accumulate of Unsigned value."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuqadd_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(suqadd))]
@@ -28146,7 +28146,7 @@ pub fn vuqadd_s16(a: int16x4_t, b: uint16x4_t) -> int16x4_t {
 }
 #[doc = "Signed saturating Accumulate of Unsigned value."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuqaddq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(suqadd))]
@@ -28162,7 +28162,7 @@ pub fn vuqaddq_s16(a: int16x8_t, b: uint16x8_t) -> int16x8_t {
 }
 #[doc = "Signed saturating Accumulate of Unsigned value."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuqadd_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(suqadd))]
@@ -28178,7 +28178,7 @@ pub fn vuqadd_s32(a: int32x2_t, b: uint32x2_t) -> int32x2_t {
 }
 #[doc = "Signed saturating Accumulate of Unsigned value."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuqaddq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(suqadd))]
@@ -28194,7 +28194,7 @@ pub fn vuqaddq_s32(a: int32x4_t, b: uint32x4_t) -> int32x4_t {
 }
 #[doc = "Signed saturating Accumulate of Unsigned value."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuqadd_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(suqadd))]
@@ -28210,7 +28210,7 @@ pub fn vuqadd_s64(a: int64x1_t, b: uint64x1_t) -> int64x1_t {
 }
 #[doc = "Signed saturating Accumulate of Unsigned value."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuqaddq_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(suqadd))]
@@ -28226,7 +28226,7 @@ pub fn vuqaddq_s64(a: int64x2_t, b: uint64x2_t) -> int64x2_t {
 }
 #[doc = "Signed saturating accumulate of unsigned value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuqaddb_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(suqadd))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -28235,7 +28235,7 @@ pub fn vuqaddb_s8(a: i8, b: u8) -> i8 {
 }
 #[doc = "Signed saturating accumulate of unsigned value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuqaddh_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(suqadd))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -28244,7 +28244,7 @@ pub fn vuqaddh_s16(a: i16, b: u16) -> i16 {
 }
 #[doc = "Signed saturating accumulate of unsigned value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuqaddd_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(suqadd))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -28260,7 +28260,7 @@ pub fn vuqaddd_s64(a: i64, b: u64) -> i64 {
 }
 #[doc = "Signed saturating accumulate of unsigned value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuqadds_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(suqadd))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -28276,7 +28276,7 @@ pub fn vuqadds_s32(a: i32, b: u32) -> i32 {
 }
 #[doc = "Dot product index form with unsigned and signed integers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdot_laneq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,i8mm")]
 #[cfg_attr(test, assert_instr(usdot, LANE = 3))]
 #[rustc_legacy_const_generics(3)]
@@ -28291,7 +28291,7 @@ pub fn vusdot_laneq_s32<const LANE: i32>(a: int32x2_t, b: uint8x8_t, c: int8x16_
 }
 #[doc = "Dot product index form with unsigned and signed integers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdotq_laneq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,i8mm")]
 #[cfg_attr(test, assert_instr(usdot, LANE = 3))]
 #[rustc_legacy_const_generics(3)]
@@ -28307,7 +28307,7 @@ pub fn vusdotq_laneq_s32<const LANE: i32>(a: int32x4_t, b: uint8x16_t, c: int8x1
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -28317,7 +28317,7 @@ pub fn vuzp1_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -28327,7 +28327,7 @@ pub fn vuzp1q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
@@ -28336,7 +28336,7 @@ pub fn vuzp1_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
@@ -28345,7 +28345,7 @@ pub fn vuzp1q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
@@ -28354,7 +28354,7 @@ pub fn vuzp1_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
@@ -28363,7 +28363,7 @@ pub fn vuzp1q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
@@ -28372,7 +28372,7 @@ pub fn vuzp1_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
@@ -28381,7 +28381,7 @@ pub fn vuzp1q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_p64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
@@ -28390,7 +28390,7 @@ pub fn vuzp1q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))]
@@ -28399,7 +28399,7 @@ pub fn vuzp1q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))]
@@ -28408,7 +28408,7 @@ pub fn vuzp1_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))]
@@ -28423,7 +28423,7 @@ pub fn vuzp1q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))]
@@ -28432,7 +28432,7 @@ pub fn vuzp1_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))]
@@ -28441,7 +28441,7 @@ pub fn vuzp1q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))]
@@ -28450,7 +28450,7 @@ pub fn vuzp1q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))]
@@ -28459,7 +28459,7 @@ pub fn vuzp1_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))]
@@ -28474,7 +28474,7 @@ pub fn vuzp1q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))]
@@ -28483,7 +28483,7 @@ pub fn vuzp1_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))]
@@ -28492,7 +28492,7 @@ pub fn vuzp1q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))]
@@ -28501,7 +28501,7 @@ pub fn vuzp1q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))]
@@ -28510,7 +28510,7 @@ pub fn vuzp1_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))]
@@ -28525,7 +28525,7 @@ pub fn vuzp1q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_p16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))]
@@ -28534,7 +28534,7 @@ pub fn vuzp1_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_p16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))]
@@ -28543,7 +28543,7 @@ pub fn vuzp1q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -28553,7 +28553,7 @@ pub fn vuzp2_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -28563,7 +28563,7 @@ pub fn vuzp2q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
@@ -28572,7 +28572,7 @@ pub fn vuzp2_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
@@ -28581,7 +28581,7 @@ pub fn vuzp2q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
@@ -28590,7 +28590,7 @@ pub fn vuzp2_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
@@ -28599,7 +28599,7 @@ pub fn vuzp2q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
@@ -28608,7 +28608,7 @@ pub fn vuzp2_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
@@ -28617,7 +28617,7 @@ pub fn vuzp2q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_p64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
@@ -28626,7 +28626,7 @@ pub fn vuzp2q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))]
@@ -28635,7 +28635,7 @@ pub fn vuzp2q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))]
@@ -28644,7 +28644,7 @@ pub fn vuzp2_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))]
@@ -28659,7 +28659,7 @@ pub fn vuzp2q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))]
@@ -28668,7 +28668,7 @@ pub fn vuzp2_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))]
@@ -28677,7 +28677,7 @@ pub fn vuzp2q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))]
@@ -28686,7 +28686,7 @@ pub fn vuzp2q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))]
@@ -28695,7 +28695,7 @@ pub fn vuzp2_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))]
@@ -28710,7 +28710,7 @@ pub fn vuzp2q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))]
@@ -28719,7 +28719,7 @@ pub fn vuzp2_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))]
@@ -28728,7 +28728,7 @@ pub fn vuzp2q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))]
@@ -28737,7 +28737,7 @@ pub fn vuzp2q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))]
@@ -28746,7 +28746,7 @@ pub fn vuzp2_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))]
@@ -28761,7 +28761,7 @@ pub fn vuzp2q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_p16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))]
@@ -28770,7 +28770,7 @@ pub fn vuzp2_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_p16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))]
@@ -28779,7 +28779,7 @@ pub fn vuzp2q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t {
 }
 #[doc = "Exclusive OR and rotate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vxarq_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,sha3")]
 #[cfg_attr(test, assert_instr(xar, IMM6 = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -28797,7 +28797,7 @@ pub fn vxarq_u64<const IMM6: i32>(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -28807,7 +28807,7 @@ pub fn vzip1_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -28817,7 +28817,7 @@ pub fn vzip1q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
@@ -28826,7 +28826,7 @@ pub fn vzip1_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
@@ -28835,7 +28835,7 @@ pub fn vzip1q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
@@ -28844,7 +28844,7 @@ pub fn vzip1q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
@@ -28853,7 +28853,7 @@ pub fn vzip1_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
@@ -28868,7 +28868,7 @@ pub fn vzip1q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
@@ -28877,7 +28877,7 @@ pub fn vzip1_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
@@ -28886,7 +28886,7 @@ pub fn vzip1q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
@@ -28895,7 +28895,7 @@ pub fn vzip1_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
@@ -28904,7 +28904,7 @@ pub fn vzip1q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
@@ -28913,7 +28913,7 @@ pub fn vzip1q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
@@ -28922,7 +28922,7 @@ pub fn vzip1_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
@@ -28937,7 +28937,7 @@ pub fn vzip1q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
@@ -28946,7 +28946,7 @@ pub fn vzip1_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
@@ -28955,7 +28955,7 @@ pub fn vzip1q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
@@ -28964,7 +28964,7 @@ pub fn vzip1_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
@@ -28973,7 +28973,7 @@ pub fn vzip1q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
@@ -28982,7 +28982,7 @@ pub fn vzip1q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
@@ -28991,7 +28991,7 @@ pub fn vzip1_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
@@ -29006,7 +29006,7 @@ pub fn vzip1q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_p16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
@@ -29015,7 +29015,7 @@ pub fn vzip1_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_p16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
@@ -29024,7 +29024,7 @@ pub fn vzip1q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_p64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))]
@@ -29033,7 +29033,7 @@ pub fn vzip1q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -29043,7 +29043,7 @@ pub fn vzip2_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")]
 #[cfg(not(target_arch = "arm64ec"))]
@@ -29053,7 +29053,7 @@ pub fn vzip2q_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
@@ -29062,7 +29062,7 @@ pub fn vzip2_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
@@ -29071,7 +29071,7 @@ pub fn vzip2q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
@@ -29080,7 +29080,7 @@ pub fn vzip2q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
@@ -29089,7 +29089,7 @@ pub fn vzip2_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
@@ -29104,7 +29104,7 @@ pub fn vzip2q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
@@ -29113,7 +29113,7 @@ pub fn vzip2_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
@@ -29122,7 +29122,7 @@ pub fn vzip2q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
@@ -29131,7 +29131,7 @@ pub fn vzip2_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
@@ -29140,7 +29140,7 @@ pub fn vzip2q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
@@ -29149,7 +29149,7 @@ pub fn vzip2q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
@@ -29158,7 +29158,7 @@ pub fn vzip2_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
@@ -29173,7 +29173,7 @@ pub fn vzip2q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
@@ -29182,7 +29182,7 @@ pub fn vzip2_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
@@ -29191,7 +29191,7 @@ pub fn vzip2q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
@@ -29200,7 +29200,7 @@ pub fn vzip2_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
@@ -29209,7 +29209,7 @@ pub fn vzip2q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
@@ -29218,7 +29218,7 @@ pub fn vzip2q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
@@ -29227,7 +29227,7 @@ pub fn vzip2_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
@@ -29242,7 +29242,7 @@ pub fn vzip2q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_p16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
@@ -29251,7 +29251,7 @@ pub fn vzip2_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_p16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
@@ -29260,7 +29260,7 @@ pub fn vzip2q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_p64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))]
diff --git a/library/stdarch/crates/core_arch/src/arm_shared/neon/generated.rs b/library/stdarch/crates/core_arch/src/arm_shared/neon/generated.rs
index 0aeb740efcd0..324ff73f62a1 100644
--- a/library/stdarch/crates/core_arch/src/arm_shared/neon/generated.rs
+++ b/library/stdarch/crates/core_arch/src/arm_shared/neon/generated.rs
@@ -14,7 +14,7 @@ use super::*;
 
 #[doc = "CRC32 single round checksum for bytes (8 bits)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32b)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "crc")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(test, assert_instr(crc32b))]
@@ -39,7 +39,7 @@ pub fn __crc32b(crc: u32, data: u8) -> u32 {
 }
 #[doc = "CRC32-C single round checksum for bytes (8 bits)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32cb)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "crc")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(test, assert_instr(crc32cb))]
@@ -64,7 +64,7 @@ pub fn __crc32cb(crc: u32, data: u8) -> u32 {
 }
 #[doc = "CRC32-C single round checksum for quad words (64 bits)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32cd)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "crc")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(test, assert_instr(crc32cw))]
@@ -83,7 +83,7 @@ pub fn __crc32cd(crc: u32, data: u64) -> u32 {
 }
 #[doc = "CRC32-C single round checksum for bytes (16 bits)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32ch)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "crc")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(test, assert_instr(crc32ch))]
@@ -108,7 +108,7 @@ pub fn __crc32ch(crc: u32, data: u16) -> u32 {
 }
 #[doc = "CRC32-C single round checksum for bytes (32 bits)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32cw)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "crc")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(test, assert_instr(crc32cw))]
@@ -133,7 +133,7 @@ pub fn __crc32cw(crc: u32, data: u32) -> u32 {
 }
 #[doc = "CRC32 single round checksum for quad words (64 bits)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32d)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "crc")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(test, assert_instr(crc32w))]
@@ -152,7 +152,7 @@ pub fn __crc32d(crc: u32, data: u64) -> u32 {
 }
 #[doc = "CRC32 single round checksum for bytes (16 bits)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32h)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "crc")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(test, assert_instr(crc32h))]
@@ -177,7 +177,7 @@ pub fn __crc32h(crc: u32, data: u16) -> u32 {
 }
 #[doc = "CRC32 single round checksum for bytes (32 bits)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32w)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "crc")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(test, assert_instr(crc32w))]
@@ -202,7 +202,7 @@ pub fn __crc32w(crc: u32, data: u32) -> u32 {
 }
 #[doc = "Signed Add and Accumulate Long Pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadal_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -220,7 +220,7 @@ fn priv_vpadal_s8(a: int16x4_t, b: int8x8_t) -> int16x4_t {
 }
 #[doc = "Signed Add and Accumulate Long Pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadalq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -238,7 +238,7 @@ fn priv_vpadalq_s8(a: int16x8_t, b: int8x16_t) -> int16x8_t {
 }
 #[doc = "Signed Add and Accumulate Long Pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadal_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -256,7 +256,7 @@ fn priv_vpadal_s16(a: int32x2_t, b: int16x4_t) -> int32x2_t {
 }
 #[doc = "Signed Add and Accumulate Long Pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadalq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -274,7 +274,7 @@ fn priv_vpadalq_s16(a: int32x4_t, b: int16x8_t) -> int32x4_t {
 }
 #[doc = "Signed Add and Accumulate Long Pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadal_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -292,7 +292,7 @@ fn priv_vpadal_s32(a: int64x1_t, b: int32x2_t) -> int64x1_t {
 }
 #[doc = "Signed Add and Accumulate Long Pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadalq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -310,7 +310,7 @@ fn priv_vpadalq_s32(a: int64x2_t, b: int32x4_t) -> int64x2_t {
 }
 #[doc = "Signed Add and Accumulate Long Pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadal_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -328,7 +328,7 @@ fn priv_vpadal_u8(a: uint16x4_t, b: uint8x8_t) -> uint16x4_t {
 }
 #[doc = "Signed Add and Accumulate Long Pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadalq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -346,7 +346,7 @@ fn priv_vpadalq_u8(a: uint16x8_t, b: uint8x16_t) -> uint16x8_t {
 }
 #[doc = "Signed Add and Accumulate Long Pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadal_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -364,7 +364,7 @@ fn priv_vpadal_u16(a: uint32x2_t, b: uint16x4_t) -> uint32x2_t {
 }
 #[doc = "Signed Add and Accumulate Long Pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadalq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -382,7 +382,7 @@ fn priv_vpadalq_u16(a: uint32x4_t, b: uint16x8_t) -> uint32x4_t {
 }
 #[doc = "Signed Add and Accumulate Long Pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadal_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -400,7 +400,7 @@ fn priv_vpadal_u32(a: uint64x1_t, b: uint32x2_t) -> uint64x1_t {
 }
 #[doc = "Signed Add and Accumulate Long Pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadalq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -418,7 +418,7 @@ fn priv_vpadalq_u32(a: uint64x2_t, b: uint32x4_t) -> uint64x2_t {
 }
 #[doc = "Absolute difference and accumulate (64-bit)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaba_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vaba.s16"))]
@@ -439,7 +439,7 @@ pub fn vaba_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t {
 }
 #[doc = "Absolute difference and accumulate (64-bit)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaba_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vaba.s32"))]
@@ -460,7 +460,7 @@ pub fn vaba_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t {
 }
 #[doc = "Absolute difference and accumulate (64-bit)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaba_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vaba.s8"))]
@@ -481,7 +481,7 @@ pub fn vaba_s8(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t {
 }
 #[doc = "Absolute difference and accumulate (64-bit)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaba_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vaba.u16"))]
@@ -502,7 +502,7 @@ pub fn vaba_u16(a: uint16x4_t, b: uint16x4_t, c: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Absolute difference and accumulate (64-bit)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaba_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vaba.u32"))]
@@ -523,7 +523,7 @@ pub fn vaba_u32(a: uint32x2_t, b: uint32x2_t, c: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Absolute difference and accumulate (64-bit)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaba_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vaba.u8"))]
@@ -544,7 +544,7 @@ pub fn vaba_u8(a: uint8x8_t, b: uint8x8_t, c: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Signed Absolute difference and Accumulate Long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabal.s8"))]
@@ -569,7 +569,7 @@ pub fn vabal_s8(a: int16x8_t, b: int8x8_t, c: int8x8_t) -> int16x8_t {
 }
 #[doc = "Signed Absolute difference and Accumulate Long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabal.s16"))]
@@ -594,7 +594,7 @@ pub fn vabal_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t {
 }
 #[doc = "Signed Absolute difference and Accumulate Long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabal.s32"))]
@@ -619,7 +619,7 @@ pub fn vabal_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t {
 }
 #[doc = "Unsigned Absolute difference and Accumulate Long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabal.u8"))]
@@ -641,7 +641,7 @@ pub fn vabal_u8(a: uint16x8_t, b: uint8x8_t, c: uint8x8_t) -> uint16x8_t {
 }
 #[doc = "Unsigned Absolute difference and Accumulate Long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabal.u16"))]
@@ -663,7 +663,7 @@ pub fn vabal_u16(a: uint32x4_t, b: uint16x4_t, c: uint16x4_t) -> uint32x4_t {
 }
 #[doc = "Unsigned Absolute difference and Accumulate Long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabal.u32"))]
@@ -685,7 +685,7 @@ pub fn vabal_u32(a: uint64x2_t, b: uint32x2_t, c: uint32x2_t) -> uint64x2_t {
 }
 #[doc = "Absolute difference and accumulate (128-bit)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabaq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vaba.s16"))]
@@ -706,7 +706,7 @@ pub fn vabaq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t {
 }
 #[doc = "Absolute difference and accumulate (128-bit)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabaq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vaba.s32"))]
@@ -727,7 +727,7 @@ pub fn vabaq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t {
 }
 #[doc = "Absolute difference and accumulate (128-bit)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabaq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vaba.s8"))]
@@ -748,7 +748,7 @@ pub fn vabaq_s8(a: int8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t {
 }
 #[doc = "Absolute difference and accumulate (128-bit)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabaq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vaba.u16"))]
@@ -769,7 +769,7 @@ pub fn vabaq_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Absolute difference and accumulate (128-bit)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabaq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vaba.u32"))]
@@ -790,7 +790,7 @@ pub fn vabaq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Absolute difference and accumulate (128-bit)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabaq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vaba.u8"))]
@@ -811,7 +811,7 @@ pub fn vabaq_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Absolute difference between the arguments of Floating"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.f16"))]
 #[cfg_attr(
@@ -841,7 +841,7 @@ pub fn vabd_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 }
 #[doc = "Absolute difference between the arguments of Floating"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.f16"))]
 #[cfg_attr(
@@ -871,7 +871,7 @@ pub fn vabdq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
 }
 #[doc = "Absolute difference between the arguments of Floating"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.f32"))]
@@ -900,7 +900,7 @@ pub fn vabd_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
 }
 #[doc = "Absolute difference between the arguments of Floating"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.f32"))]
@@ -929,7 +929,7 @@ pub fn vabdq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
 }
 #[doc = "Absolute difference between the arguments"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.s8"))]
@@ -958,7 +958,7 @@ pub fn vabd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Absolute difference between the arguments"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.s8"))]
@@ -987,7 +987,7 @@ pub fn vabdq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Absolute difference between the arguments"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.s16"))]
@@ -1016,7 +1016,7 @@ pub fn vabd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Absolute difference between the arguments"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.s16"))]
@@ -1045,7 +1045,7 @@ pub fn vabdq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Absolute difference between the arguments"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.s32"))]
@@ -1074,7 +1074,7 @@ pub fn vabd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Absolute difference between the arguments"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.s32"))]
@@ -1103,7 +1103,7 @@ pub fn vabdq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Absolute difference between the arguments"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.u8"))]
@@ -1132,7 +1132,7 @@ pub fn vabd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Absolute difference between the arguments"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.u8"))]
@@ -1161,7 +1161,7 @@ pub fn vabdq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Absolute difference between the arguments"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.u16"))]
@@ -1190,7 +1190,7 @@ pub fn vabd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Absolute difference between the arguments"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.u16"))]
@@ -1219,7 +1219,7 @@ pub fn vabdq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Absolute difference between the arguments"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.u32"))]
@@ -1248,7 +1248,7 @@ pub fn vabd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Absolute difference between the arguments"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.u32"))]
@@ -1277,7 +1277,7 @@ pub fn vabdq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Signed Absolute difference Long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabdl.s8"))]
@@ -1301,7 +1301,7 @@ pub fn vabdl_s8(a: int8x8_t, b: int8x8_t) -> int16x8_t {
 }
 #[doc = "Signed Absolute difference Long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabdl.s16"))]
@@ -1325,7 +1325,7 @@ pub fn vabdl_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t {
 }
 #[doc = "Signed Absolute difference Long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabdl.s32"))]
@@ -1349,7 +1349,7 @@ pub fn vabdl_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t {
 }
 #[doc = "Unsigned Absolute difference Long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabdl.u8"))]
@@ -1370,7 +1370,7 @@ pub fn vabdl_u8(a: uint8x8_t, b: uint8x8_t) -> uint16x8_t {
 }
 #[doc = "Unsigned Absolute difference Long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabdl.u16"))]
@@ -1391,7 +1391,7 @@ pub fn vabdl_u16(a: uint16x4_t, b: uint16x4_t) -> uint32x4_t {
 }
 #[doc = "Unsigned Absolute difference Long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabdl.u32"))]
@@ -1412,7 +1412,7 @@ pub fn vabdl_u32(a: uint32x2_t, b: uint32x2_t) -> uint64x2_t {
 }
 #[doc = "Floating-point absolute value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabs_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))]
 #[cfg_attr(
@@ -1434,7 +1434,7 @@ pub fn vabs_f16(a: float16x4_t) -> float16x4_t {
 }
 #[doc = "Floating-point absolute value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabsq_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))]
 #[cfg_attr(
@@ -1456,7 +1456,7 @@ pub fn vabsq_f16(a: float16x8_t) -> float16x8_t {
 }
 #[doc = "Floating-point absolute value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabs_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))]
@@ -1477,7 +1477,7 @@ pub fn vabs_f32(a: float32x2_t) -> float32x2_t {
 }
 #[doc = "Floating-point absolute value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabsq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))]
@@ -1498,7 +1498,7 @@ pub fn vabsq_f32(a: float32x4_t) -> float32x4_t {
 }
 #[doc = "Absolute value (wrapping)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabs_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))]
@@ -1523,7 +1523,7 @@ pub fn vabs_s8(a: int8x8_t) -> int8x8_t {
 }
 #[doc = "Absolute value (wrapping)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabsq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))]
@@ -1548,7 +1548,7 @@ pub fn vabsq_s8(a: int8x16_t) -> int8x16_t {
 }
 #[doc = "Absolute value (wrapping)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabs_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))]
@@ -1573,7 +1573,7 @@ pub fn vabs_s16(a: int16x4_t) -> int16x4_t {
 }
 #[doc = "Absolute value (wrapping)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabsq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))]
@@ -1598,7 +1598,7 @@ pub fn vabsq_s16(a: int16x8_t) -> int16x8_t {
 }
 #[doc = "Absolute value (wrapping)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabs_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))]
@@ -1623,7 +1623,7 @@ pub fn vabs_s32(a: int32x2_t) -> int32x2_t {
 }
 #[doc = "Absolute value (wrapping)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabsq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))]
@@ -1648,7 +1648,7 @@ pub fn vabsq_s32(a: int32x4_t) -> int32x4_t {
 }
 #[doc = "Floating-point absolute value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabsh_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))]
 #[cfg_attr(
@@ -1663,7 +1663,7 @@ pub fn vabsh_f16(a: f16) -> f16 {
 }
 #[doc = "Floating-point Add (vector)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vadd.f16"))]
 #[cfg_attr(
@@ -1685,7 +1685,7 @@ pub fn vadd_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 }
 #[doc = "Floating-point Add (vector)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vadd.f16"))]
 #[cfg_attr(
@@ -1707,7 +1707,7 @@ pub fn vaddq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
 }
 #[doc = "Vector add."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
@@ -1728,7 +1728,7 @@ pub fn vadd_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
 }
 #[doc = "Vector add."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
@@ -1749,7 +1749,7 @@ pub fn vadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Vector add."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
@@ -1770,7 +1770,7 @@ pub fn vadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Vector add."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
@@ -1791,7 +1791,7 @@ pub fn vadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Vector add."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
@@ -1812,7 +1812,7 @@ pub fn vadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Vector add."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
@@ -1833,7 +1833,7 @@ pub fn vadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Vector add."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
@@ -1854,7 +1854,7 @@ pub fn vadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Vector add."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
@@ -1875,7 +1875,7 @@ pub fn vaddq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
 }
 #[doc = "Vector add."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
@@ -1896,7 +1896,7 @@ pub fn vaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Vector add."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
@@ -1917,7 +1917,7 @@ pub fn vaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Vector add."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
@@ -1938,7 +1938,7 @@ pub fn vaddq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
 }
 #[doc = "Vector add."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
@@ -1959,7 +1959,7 @@ pub fn vaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Vector add."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
@@ -1980,7 +1980,7 @@ pub fn vaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Vector add."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
@@ -2001,7 +2001,7 @@ pub fn vaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Vector add."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
@@ -2022,7 +2022,7 @@ pub fn vaddq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Vector add."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vadd))]
@@ -2043,7 +2043,7 @@ pub fn vaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Bitwise exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -2064,7 +2064,7 @@ pub fn vadd_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
 }
 #[doc = "Bitwise exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -2085,7 +2085,7 @@ pub fn vaddq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t {
 }
 #[doc = "Bitwise exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_p16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -2106,7 +2106,7 @@ pub fn vadd_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t {
 }
 #[doc = "Bitwise exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_p16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -2127,7 +2127,7 @@ pub fn vaddq_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t {
 }
 #[doc = "Bitwise exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_p64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -2148,7 +2148,7 @@ pub fn vadd_p64(a: poly64x1_t, b: poly64x1_t) -> poly64x1_t {
 }
 #[doc = "Bitwise exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_p64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -2169,7 +2169,7 @@ pub fn vaddq_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t {
 }
 #[doc = "Add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddh_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vadd.f16"))]
 #[cfg_attr(
@@ -2184,7 +2184,7 @@ pub fn vaddh_f16(a: f16, b: f16) -> f16 {
 }
 #[doc = "Add returning High Narrow (high half)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_high_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))]
@@ -2208,7 +2208,7 @@ pub fn vaddhn_high_s16(r: int8x8_t, a: int16x8_t, b: int16x8_t) -> int8x16_t {
 }
 #[doc = "Add returning High Narrow (high half)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_high_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))]
@@ -2232,7 +2232,7 @@ pub fn vaddhn_high_s32(r: int16x4_t, a: int32x4_t, b: int32x4_t) -> int16x8_t {
 }
 #[doc = "Add returning High Narrow (high half)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_high_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))]
@@ -2256,7 +2256,7 @@ pub fn vaddhn_high_s64(r: int32x2_t, a: int64x2_t, b: int64x2_t) -> int32x4_t {
 }
 #[doc = "Add returning High Narrow (high half)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_high_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))]
@@ -2280,7 +2280,7 @@ pub fn vaddhn_high_u16(r: uint8x8_t, a: uint16x8_t, b: uint16x8_t) -> uint8x16_t
 }
 #[doc = "Add returning High Narrow (high half)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_high_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))]
@@ -2304,7 +2304,7 @@ pub fn vaddhn_high_u32(r: uint16x4_t, a: uint32x4_t, b: uint32x4_t) -> uint16x8_
 }
 #[doc = "Add returning High Narrow (high half)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_high_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))]
@@ -2328,7 +2328,7 @@ pub fn vaddhn_high_u64(r: uint32x2_t, a: uint64x2_t, b: uint64x2_t) -> uint32x4_
 }
 #[doc = "Add returning High Narrow."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))]
@@ -2349,7 +2349,7 @@ pub fn vaddhn_s16(a: int16x8_t, b: int16x8_t) -> int8x8_t {
 }
 #[doc = "Add returning High Narrow."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))]
@@ -2370,7 +2370,7 @@ pub fn vaddhn_s32(a: int32x4_t, b: int32x4_t) -> int16x4_t {
 }
 #[doc = "Add returning High Narrow."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))]
@@ -2391,7 +2391,7 @@ pub fn vaddhn_s64(a: int64x2_t, b: int64x2_t) -> int32x2_t {
 }
 #[doc = "Add returning High Narrow."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))]
@@ -2412,7 +2412,7 @@ pub fn vaddhn_u16(a: uint16x8_t, b: uint16x8_t) -> uint8x8_t {
 }
 #[doc = "Add returning High Narrow."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))]
@@ -2433,7 +2433,7 @@ pub fn vaddhn_u32(a: uint32x4_t, b: uint32x4_t) -> uint16x4_t {
 }
 #[doc = "Add returning High Narrow."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddhn))]
@@ -2454,7 +2454,7 @@ pub fn vaddhn_u64(a: uint64x2_t, b: uint64x2_t) -> uint32x2_t {
 }
 #[doc = "Signed Add Long (vector, high half)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_high_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))]
@@ -2481,7 +2481,7 @@ pub fn vaddl_high_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t {
 }
 #[doc = "Signed Add Long (vector, high half)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_high_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))]
@@ -2508,7 +2508,7 @@ pub fn vaddl_high_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t {
 }
 #[doc = "Signed Add Long (vector, high half)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_high_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))]
@@ -2535,7 +2535,7 @@ pub fn vaddl_high_s8(a: int8x16_t, b: int8x16_t) -> int16x8_t {
 }
 #[doc = "Signed Add Long (vector, high half)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_high_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))]
@@ -2562,7 +2562,7 @@ pub fn vaddl_high_u16(a: uint16x8_t, b: uint16x8_t) -> uint32x4_t {
 }
 #[doc = "Signed Add Long (vector, high half)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_high_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))]
@@ -2589,7 +2589,7 @@ pub fn vaddl_high_u32(a: uint32x4_t, b: uint32x4_t) -> uint64x2_t {
 }
 #[doc = "Signed Add Long (vector, high half)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_high_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))]
@@ -2616,7 +2616,7 @@ pub fn vaddl_high_u8(a: uint8x16_t, b: uint8x16_t) -> uint16x8_t {
 }
 #[doc = "Add Long (vector)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))]
@@ -2641,7 +2641,7 @@ pub fn vaddl_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t {
 }
 #[doc = "Add Long (vector)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))]
@@ -2666,7 +2666,7 @@ pub fn vaddl_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t {
 }
 #[doc = "Add Long (vector)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))]
@@ -2691,7 +2691,7 @@ pub fn vaddl_s8(a: int8x8_t, b: int8x8_t) -> int16x8_t {
 }
 #[doc = "Add Long (vector)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))]
@@ -2716,7 +2716,7 @@ pub fn vaddl_u16(a: uint16x4_t, b: uint16x4_t) -> uint32x4_t {
 }
 #[doc = "Add Long (vector)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))]
@@ -2741,7 +2741,7 @@ pub fn vaddl_u32(a: uint32x2_t, b: uint32x2_t) -> uint64x2_t {
 }
 #[doc = "Add Long (vector)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddl))]
@@ -2766,7 +2766,7 @@ pub fn vaddl_u8(a: uint8x8_t, b: uint8x8_t) -> uint16x8_t {
 }
 #[doc = "Bitwise exclusive OR"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_p128)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -2787,7 +2787,7 @@ pub fn vaddq_p128(a: p128, b: p128) -> p128 {
 }
 #[doc = "Add Wide (high half)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_high_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))]
@@ -2812,7 +2812,7 @@ pub fn vaddw_high_s16(a: int32x4_t, b: int16x8_t) -> int32x4_t {
 }
 #[doc = "Add Wide (high half)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_high_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))]
@@ -2837,7 +2837,7 @@ pub fn vaddw_high_s32(a: int64x2_t, b: int32x4_t) -> int64x2_t {
 }
 #[doc = "Add Wide (high half)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_high_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))]
@@ -2862,7 +2862,7 @@ pub fn vaddw_high_s8(a: int16x8_t, b: int8x16_t) -> int16x8_t {
 }
 #[doc = "Add Wide (high half)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_high_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))]
@@ -2887,7 +2887,7 @@ pub fn vaddw_high_u16(a: uint32x4_t, b: uint16x8_t) -> uint32x4_t {
 }
 #[doc = "Add Wide (high half)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_high_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))]
@@ -2912,7 +2912,7 @@ pub fn vaddw_high_u32(a: uint64x2_t, b: uint32x4_t) -> uint64x2_t {
 }
 #[doc = "Add Wide (high half)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_high_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))]
@@ -2937,7 +2937,7 @@ pub fn vaddw_high_u8(a: uint16x8_t, b: uint8x16_t) -> uint16x8_t {
 }
 #[doc = "Add Wide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))]
@@ -2961,7 +2961,7 @@ pub fn vaddw_s16(a: int32x4_t, b: int16x4_t) -> int32x4_t {
 }
 #[doc = "Add Wide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))]
@@ -2985,7 +2985,7 @@ pub fn vaddw_s32(a: int64x2_t, b: int32x2_t) -> int64x2_t {
 }
 #[doc = "Add Wide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))]
@@ -3009,7 +3009,7 @@ pub fn vaddw_s8(a: int16x8_t, b: int8x8_t) -> int16x8_t {
 }
 #[doc = "Add Wide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))]
@@ -3033,7 +3033,7 @@ pub fn vaddw_u16(a: uint32x4_t, b: uint16x4_t) -> uint32x4_t {
 }
 #[doc = "Add Wide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))]
@@ -3057,7 +3057,7 @@ pub fn vaddw_u32(a: uint64x2_t, b: uint32x2_t) -> uint64x2_t {
 }
 #[doc = "Add Wide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vaddw))]
@@ -3081,7 +3081,7 @@ pub fn vaddw_u8(a: uint16x8_t, b: uint8x8_t) -> uint16x8_t {
 }
 #[doc = "AES single round encryption."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaesdq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(test, assert_instr(aesd))]
@@ -3106,7 +3106,7 @@ pub fn vaesdq_u8(data: uint8x16_t, key: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "AES single round encryption."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaeseq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(test, assert_instr(aese))]
@@ -3131,7 +3131,7 @@ pub fn vaeseq_u8(data: uint8x16_t, key: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "AES inverse mix columns."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaesimcq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(test, assert_instr(aesimc))]
@@ -3156,7 +3156,7 @@ pub fn vaesimcq_u8(data: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "AES mix columns."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaesmcq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(test, assert_instr(aesmc))]
@@ -3181,7 +3181,7 @@ pub fn vaesmcq_u8(data: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Vector bitwise and"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
@@ -3202,7 +3202,7 @@ pub fn vand_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Vector bitwise and"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
@@ -3223,7 +3223,7 @@ pub fn vandq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Vector bitwise and"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
@@ -3244,7 +3244,7 @@ pub fn vand_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Vector bitwise and"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
@@ -3265,7 +3265,7 @@ pub fn vandq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Vector bitwise and"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
@@ -3286,7 +3286,7 @@ pub fn vand_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Vector bitwise and"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
@@ -3307,7 +3307,7 @@ pub fn vandq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Vector bitwise and"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
@@ -3328,7 +3328,7 @@ pub fn vand_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t {
 }
 #[doc = "Vector bitwise and"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
@@ -3349,7 +3349,7 @@ pub fn vandq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
 }
 #[doc = "Vector bitwise and"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
@@ -3370,7 +3370,7 @@ pub fn vand_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Vector bitwise and"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
@@ -3391,7 +3391,7 @@ pub fn vandq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Vector bitwise and"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
@@ -3412,7 +3412,7 @@ pub fn vand_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Vector bitwise and"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
@@ -3433,7 +3433,7 @@ pub fn vandq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Vector bitwise and"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
@@ -3454,7 +3454,7 @@ pub fn vand_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Vector bitwise and"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
@@ -3475,7 +3475,7 @@ pub fn vandq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Vector bitwise and"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
@@ -3496,7 +3496,7 @@ pub fn vand_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
 }
 #[doc = "Vector bitwise and"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))]
@@ -3517,7 +3517,7 @@ pub fn vandq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Vector bitwise bit clear."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbic_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))]
@@ -3539,7 +3539,7 @@ pub fn vbic_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Vector bitwise bit clear."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbic_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))]
@@ -3561,7 +3561,7 @@ pub fn vbic_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Vector bitwise bit clear."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbic_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))]
@@ -3583,7 +3583,7 @@ pub fn vbic_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t {
 }
 #[doc = "Vector bitwise bit clear."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbic_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))]
@@ -3605,7 +3605,7 @@ pub fn vbic_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Vector bitwise bit clear."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbicq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))]
@@ -3627,7 +3627,7 @@ pub fn vbicq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Vector bitwise bit clear."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbicq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))]
@@ -3649,7 +3649,7 @@ pub fn vbicq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Vector bitwise bit clear."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbicq_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))]
@@ -3671,7 +3671,7 @@ pub fn vbicq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
 }
 #[doc = "Vector bitwise bit clear."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbicq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))]
@@ -3693,7 +3693,7 @@ pub fn vbicq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Vector bitwise bit clear."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbic_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))]
@@ -3715,7 +3715,7 @@ pub fn vbic_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Vector bitwise bit clear."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbic_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))]
@@ -3737,7 +3737,7 @@ pub fn vbic_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Vector bitwise bit clear."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbic_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))]
@@ -3759,7 +3759,7 @@ pub fn vbic_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
 }
 #[doc = "Vector bitwise bit clear."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbic_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))]
@@ -3781,7 +3781,7 @@ pub fn vbic_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Vector bitwise bit clear."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbicq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))]
@@ -3803,7 +3803,7 @@ pub fn vbicq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Vector bitwise bit clear."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbicq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))]
@@ -3825,7 +3825,7 @@ pub fn vbicq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Vector bitwise bit clear."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbicq_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))]
@@ -3847,7 +3847,7 @@ pub fn vbicq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Vector bitwise bit clear."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbicq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbic))]
@@ -3869,7 +3869,7 @@ pub fn vbicq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Bitwise Select."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
@@ -3897,7 +3897,7 @@ pub fn vbsl_f16(a: uint16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t {
 }
 #[doc = "Bitwise Select."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
@@ -3925,7 +3925,7 @@ pub fn vbslq_f16(a: uint16x8_t, b: float16x8_t, c: float16x8_t) -> float16x8_t {
 }
 #[doc = "Bitwise Select."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
@@ -3952,7 +3952,7 @@ pub fn vbsl_f32(a: uint32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t {
 }
 #[doc = "Bitwise Select."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_p16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
@@ -3979,7 +3979,7 @@ pub fn vbsl_p16(a: uint16x4_t, b: poly16x4_t, c: poly16x4_t) -> poly16x4_t {
 }
 #[doc = "Bitwise Select."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
@@ -4006,7 +4006,7 @@ pub fn vbsl_p8(a: uint8x8_t, b: poly8x8_t, c: poly8x8_t) -> poly8x8_t {
 }
 #[doc = "Bitwise Select."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
@@ -4033,7 +4033,7 @@ pub fn vbsl_s16(a: uint16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t {
 }
 #[doc = "Bitwise Select."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
@@ -4060,7 +4060,7 @@ pub fn vbsl_s32(a: uint32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t {
 }
 #[doc = "Bitwise Select."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
@@ -4087,7 +4087,7 @@ pub fn vbsl_s64(a: uint64x1_t, b: int64x1_t, c: int64x1_t) -> int64x1_t {
 }
 #[doc = "Bitwise Select."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
@@ -4114,7 +4114,7 @@ pub fn vbsl_s8(a: uint8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t {
 }
 #[doc = "Bitwise Select."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
@@ -4141,7 +4141,7 @@ pub fn vbslq_f32(a: uint32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t {
 }
 #[doc = "Bitwise Select."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_p16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
@@ -4168,7 +4168,7 @@ pub fn vbslq_p16(a: uint16x8_t, b: poly16x8_t, c: poly16x8_t) -> poly16x8_t {
 }
 #[doc = "Bitwise Select."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
@@ -4195,7 +4195,7 @@ pub fn vbslq_p8(a: uint8x16_t, b: poly8x16_t, c: poly8x16_t) -> poly8x16_t {
 }
 #[doc = "Bitwise Select."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
@@ -4222,7 +4222,7 @@ pub fn vbslq_s16(a: uint16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t {
 }
 #[doc = "Bitwise Select."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
@@ -4249,7 +4249,7 @@ pub fn vbslq_s32(a: uint32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t {
 }
 #[doc = "Bitwise Select."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
@@ -4276,7 +4276,7 @@ pub fn vbslq_s64(a: uint64x2_t, b: int64x2_t, c: int64x2_t) -> int64x2_t {
 }
 #[doc = "Bitwise Select."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
@@ -4303,7 +4303,7 @@ pub fn vbslq_s8(a: uint8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t {
 }
 #[doc = "Bitwise Select."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
@@ -4330,7 +4330,7 @@ pub fn vbsl_u16(a: uint16x4_t, b: uint16x4_t, c: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Bitwise Select."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
@@ -4357,7 +4357,7 @@ pub fn vbsl_u32(a: uint32x2_t, b: uint32x2_t, c: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Bitwise Select."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
@@ -4384,7 +4384,7 @@ pub fn vbsl_u64(a: uint64x1_t, b: uint64x1_t, c: uint64x1_t) -> uint64x1_t {
 }
 #[doc = "Bitwise Select."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
@@ -4411,7 +4411,7 @@ pub fn vbsl_u8(a: uint8x8_t, b: uint8x8_t, c: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Bitwise Select."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
@@ -4438,7 +4438,7 @@ pub fn vbslq_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Bitwise Select."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
@@ -4465,7 +4465,7 @@ pub fn vbslq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Bitwise Select."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
@@ -4492,7 +4492,7 @@ pub fn vbslq_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Bitwise Select."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vbsl))]
@@ -4519,7 +4519,7 @@ pub fn vbslq_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Floating-point absolute compare greater than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcage_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacge.f16"))]
 #[cfg_attr(
@@ -4549,7 +4549,7 @@ pub fn vcage_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t {
 }
 #[doc = "Floating-point absolute compare greater than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcageq_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacge.f16"))]
 #[cfg_attr(
@@ -4579,7 +4579,7 @@ pub fn vcageq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t {
 }
 #[doc = "Floating-point absolute compare greater than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcage_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacge.f32"))]
@@ -4608,7 +4608,7 @@ pub fn vcage_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t {
 }
 #[doc = "Floating-point absolute compare greater than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcageq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacge.f32"))]
@@ -4637,7 +4637,7 @@ pub fn vcageq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t {
 }
 #[doc = "Floating-point absolute compare greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcagt_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacgt.f16"))]
 #[cfg_attr(
@@ -4667,7 +4667,7 @@ pub fn vcagt_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t {
 }
 #[doc = "Floating-point absolute compare greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcagtq_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacgt.f16"))]
 #[cfg_attr(
@@ -4697,7 +4697,7 @@ pub fn vcagtq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t {
 }
 #[doc = "Floating-point absolute compare greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcagt_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacgt.f32"))]
@@ -4726,7 +4726,7 @@ pub fn vcagt_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t {
 }
 #[doc = "Floating-point absolute compare greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcagtq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacgt.f32"))]
@@ -4755,7 +4755,7 @@ pub fn vcagtq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t {
 }
 #[doc = "Floating-point absolute compare less than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcale_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacge.f16"))]
 #[cfg_attr(
@@ -4777,7 +4777,7 @@ pub fn vcale_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t {
 }
 #[doc = "Floating-point absolute compare less than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaleq_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacge.f16"))]
 #[cfg_attr(
@@ -4799,7 +4799,7 @@ pub fn vcaleq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t {
 }
 #[doc = "Floating-point absolute compare less than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcale_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacge.f32"))]
@@ -4820,7 +4820,7 @@ pub fn vcale_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t {
 }
 #[doc = "Floating-point absolute compare less than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaleq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacge.f32"))]
@@ -4841,7 +4841,7 @@ pub fn vcaleq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t {
 }
 #[doc = "Floating-point absolute compare less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcalt_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacgt.f16"))]
 #[cfg_attr(
@@ -4863,7 +4863,7 @@ pub fn vcalt_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t {
 }
 #[doc = "Floating-point absolute compare less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaltq_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacgt.f16"))]
 #[cfg_attr(
@@ -4885,7 +4885,7 @@ pub fn vcaltq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t {
 }
 #[doc = "Floating-point absolute compare less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcalt_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacgt.f32"))]
@@ -4906,7 +4906,7 @@ pub fn vcalt_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t {
 }
 #[doc = "Floating-point absolute compare less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaltq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacgt.f32"))]
@@ -4927,7 +4927,7 @@ pub fn vcaltq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t {
 }
 #[doc = "Floating-point compare equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.f16"))]
 #[cfg_attr(
@@ -4949,7 +4949,7 @@ pub fn vceq_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t {
 }
 #[doc = "Floating-point compare equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.f16"))]
 #[cfg_attr(
@@ -4971,7 +4971,7 @@ pub fn vceqq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t {
 }
 #[doc = "Floating-point compare equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.f32"))]
@@ -4992,7 +4992,7 @@ pub fn vceq_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t {
 }
 #[doc = "Floating-point compare equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.f32"))]
@@ -5013,7 +5013,7 @@ pub fn vceqq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t {
 }
 #[doc = "Compare bitwise Equal (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i8"))]
@@ -5034,7 +5034,7 @@ pub fn vceq_s8(a: int8x8_t, b: int8x8_t) -> uint8x8_t {
 }
 #[doc = "Compare bitwise Equal (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i8"))]
@@ -5055,7 +5055,7 @@ pub fn vceqq_s8(a: int8x16_t, b: int8x16_t) -> uint8x16_t {
 }
 #[doc = "Compare bitwise Equal (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i16"))]
@@ -5076,7 +5076,7 @@ pub fn vceq_s16(a: int16x4_t, b: int16x4_t) -> uint16x4_t {
 }
 #[doc = "Compare bitwise Equal (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i16"))]
@@ -5097,7 +5097,7 @@ pub fn vceqq_s16(a: int16x8_t, b: int16x8_t) -> uint16x8_t {
 }
 #[doc = "Compare bitwise Equal (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i32"))]
@@ -5118,7 +5118,7 @@ pub fn vceq_s32(a: int32x2_t, b: int32x2_t) -> uint32x2_t {
 }
 #[doc = "Compare bitwise Equal (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i32"))]
@@ -5139,7 +5139,7 @@ pub fn vceqq_s32(a: int32x4_t, b: int32x4_t) -> uint32x4_t {
 }
 #[doc = "Compare bitwise Equal (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i8"))]
@@ -5160,7 +5160,7 @@ pub fn vceq_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Compare bitwise Equal (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i8"))]
@@ -5181,7 +5181,7 @@ pub fn vceqq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Compare bitwise Equal (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i16"))]
@@ -5202,7 +5202,7 @@ pub fn vceq_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Compare bitwise Equal (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i16"))]
@@ -5223,7 +5223,7 @@ pub fn vceqq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Compare bitwise Equal (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i32"))]
@@ -5244,7 +5244,7 @@ pub fn vceq_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Compare bitwise Equal (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i32"))]
@@ -5265,7 +5265,7 @@ pub fn vceqq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Compare bitwise Equal (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i8"))]
@@ -5286,7 +5286,7 @@ pub fn vceq_p8(a: poly8x8_t, b: poly8x8_t) -> uint8x8_t {
 }
 #[doc = "Compare bitwise Equal (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i8"))]
@@ -5307,7 +5307,7 @@ pub fn vceqq_p8(a: poly8x16_t, b: poly8x16_t) -> uint8x16_t {
 }
 #[doc = "Floating-point compare greater than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f16"))]
 #[cfg_attr(
@@ -5329,7 +5329,7 @@ pub fn vcge_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t {
 }
 #[doc = "Floating-point compare greater than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f16"))]
 #[cfg_attr(
@@ -5351,7 +5351,7 @@ pub fn vcgeq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t {
 }
 #[doc = "Floating-point compare greater than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f32"))]
@@ -5372,7 +5372,7 @@ pub fn vcge_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t {
 }
 #[doc = "Floating-point compare greater than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f32"))]
@@ -5393,7 +5393,7 @@ pub fn vcgeq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t {
 }
 #[doc = "Compare signed greater than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s8"))]
@@ -5414,7 +5414,7 @@ pub fn vcge_s8(a: int8x8_t, b: int8x8_t) -> uint8x8_t {
 }
 #[doc = "Compare signed greater than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s8"))]
@@ -5435,7 +5435,7 @@ pub fn vcgeq_s8(a: int8x16_t, b: int8x16_t) -> uint8x16_t {
 }
 #[doc = "Compare signed greater than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s16"))]
@@ -5456,7 +5456,7 @@ pub fn vcge_s16(a: int16x4_t, b: int16x4_t) -> uint16x4_t {
 }
 #[doc = "Compare signed greater than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s16"))]
@@ -5477,7 +5477,7 @@ pub fn vcgeq_s16(a: int16x8_t, b: int16x8_t) -> uint16x8_t {
 }
 #[doc = "Compare signed greater than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s32"))]
@@ -5498,7 +5498,7 @@ pub fn vcge_s32(a: int32x2_t, b: int32x2_t) -> uint32x2_t {
 }
 #[doc = "Compare signed greater than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s32"))]
@@ -5519,7 +5519,7 @@ pub fn vcgeq_s32(a: int32x4_t, b: int32x4_t) -> uint32x4_t {
 }
 #[doc = "Compare unsigned greater than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u8"))]
@@ -5540,7 +5540,7 @@ pub fn vcge_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Compare unsigned greater than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u8"))]
@@ -5561,7 +5561,7 @@ pub fn vcgeq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Compare unsigned greater than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u16"))]
@@ -5582,7 +5582,7 @@ pub fn vcge_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Compare unsigned greater than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u16"))]
@@ -5603,7 +5603,7 @@ pub fn vcgeq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Compare unsigned greater than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u32"))]
@@ -5624,7 +5624,7 @@ pub fn vcge_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Compare unsigned greater than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u32"))]
@@ -5645,7 +5645,7 @@ pub fn vcgeq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Floating-point compare greater than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgez_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f16"))]
 #[cfg_attr(
@@ -5668,7 +5668,7 @@ pub fn vcgez_f16(a: float16x4_t) -> uint16x4_t {
 }
 #[doc = "Floating-point compare greater than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezq_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f16"))]
 #[cfg_attr(
@@ -5691,7 +5691,7 @@ pub fn vcgezq_f16(a: float16x8_t) -> uint16x8_t {
 }
 #[doc = "Floating-point compare greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f16"))]
 #[cfg_attr(
@@ -5713,7 +5713,7 @@ pub fn vcgt_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t {
 }
 #[doc = "Floating-point compare greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f16"))]
 #[cfg_attr(
@@ -5735,7 +5735,7 @@ pub fn vcgtq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t {
 }
 #[doc = "Floating-point compare greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f32"))]
@@ -5756,7 +5756,7 @@ pub fn vcgt_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t {
 }
 #[doc = "Floating-point compare greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f32"))]
@@ -5777,7 +5777,7 @@ pub fn vcgtq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t {
 }
 #[doc = "Compare signed greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s8"))]
@@ -5798,7 +5798,7 @@ pub fn vcgt_s8(a: int8x8_t, b: int8x8_t) -> uint8x8_t {
 }
 #[doc = "Compare signed greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s8"))]
@@ -5819,7 +5819,7 @@ pub fn vcgtq_s8(a: int8x16_t, b: int8x16_t) -> uint8x16_t {
 }
 #[doc = "Compare signed greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s16"))]
@@ -5840,7 +5840,7 @@ pub fn vcgt_s16(a: int16x4_t, b: int16x4_t) -> uint16x4_t {
 }
 #[doc = "Compare signed greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s16"))]
@@ -5861,7 +5861,7 @@ pub fn vcgtq_s16(a: int16x8_t, b: int16x8_t) -> uint16x8_t {
 }
 #[doc = "Compare signed greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s32"))]
@@ -5882,7 +5882,7 @@ pub fn vcgt_s32(a: int32x2_t, b: int32x2_t) -> uint32x2_t {
 }
 #[doc = "Compare signed greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s32"))]
@@ -5903,7 +5903,7 @@ pub fn vcgtq_s32(a: int32x4_t, b: int32x4_t) -> uint32x4_t {
 }
 #[doc = "Compare unsigned greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u8"))]
@@ -5924,7 +5924,7 @@ pub fn vcgt_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Compare unsigned greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u8"))]
@@ -5945,7 +5945,7 @@ pub fn vcgtq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Compare unsigned greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u16"))]
@@ -5966,7 +5966,7 @@ pub fn vcgt_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Compare unsigned greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u16"))]
@@ -5987,7 +5987,7 @@ pub fn vcgtq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Compare unsigned greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u32"))]
@@ -6008,7 +6008,7 @@ pub fn vcgt_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Compare unsigned greater than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u32"))]
@@ -6029,7 +6029,7 @@ pub fn vcgtq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Floating-point compare greater than zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtz_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f16"))]
 #[cfg_attr(
@@ -6052,7 +6052,7 @@ pub fn vcgtz_f16(a: float16x4_t) -> uint16x4_t {
 }
 #[doc = "Floating-point compare greater than zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtzq_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f16"))]
 #[cfg_attr(
@@ -6075,7 +6075,7 @@ pub fn vcgtzq_f16(a: float16x8_t) -> uint16x8_t {
 }
 #[doc = "Floating-point compare less than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f16"))]
 #[cfg_attr(
@@ -6097,7 +6097,7 @@ pub fn vcle_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t {
 }
 #[doc = "Floating-point compare less than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f16"))]
 #[cfg_attr(
@@ -6119,7 +6119,7 @@ pub fn vcleq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t {
 }
 #[doc = "Floating-point compare less than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f32"))]
@@ -6140,7 +6140,7 @@ pub fn vcle_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t {
 }
 #[doc = "Floating-point compare less than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f32"))]
@@ -6161,7 +6161,7 @@ pub fn vcleq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t {
 }
 #[doc = "Compare signed less than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s8"))]
@@ -6182,7 +6182,7 @@ pub fn vcle_s8(a: int8x8_t, b: int8x8_t) -> uint8x8_t {
 }
 #[doc = "Compare signed less than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s8"))]
@@ -6203,7 +6203,7 @@ pub fn vcleq_s8(a: int8x16_t, b: int8x16_t) -> uint8x16_t {
 }
 #[doc = "Compare signed less than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s16"))]
@@ -6224,7 +6224,7 @@ pub fn vcle_s16(a: int16x4_t, b: int16x4_t) -> uint16x4_t {
 }
 #[doc = "Compare signed less than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s16"))]
@@ -6245,7 +6245,7 @@ pub fn vcleq_s16(a: int16x8_t, b: int16x8_t) -> uint16x8_t {
 }
 #[doc = "Compare signed less than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s32"))]
@@ -6266,7 +6266,7 @@ pub fn vcle_s32(a: int32x2_t, b: int32x2_t) -> uint32x2_t {
 }
 #[doc = "Compare signed less than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s32"))]
@@ -6287,7 +6287,7 @@ pub fn vcleq_s32(a: int32x4_t, b: int32x4_t) -> uint32x4_t {
 }
 #[doc = "Compare unsigned less than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u8"))]
@@ -6308,7 +6308,7 @@ pub fn vcle_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Compare unsigned less than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u8"))]
@@ -6329,7 +6329,7 @@ pub fn vcleq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Compare unsigned less than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u16"))]
@@ -6350,7 +6350,7 @@ pub fn vcle_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Compare unsigned less than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u16"))]
@@ -6371,7 +6371,7 @@ pub fn vcleq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Compare unsigned less than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u32"))]
@@ -6392,7 +6392,7 @@ pub fn vcle_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Compare unsigned less than or equal"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u32"))]
@@ -6413,7 +6413,7 @@ pub fn vcleq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Floating-point compare less than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclez_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcle.f16"))]
 #[cfg_attr(
@@ -6436,7 +6436,7 @@ pub fn vclez_f16(a: float16x4_t) -> uint16x4_t {
 }
 #[doc = "Floating-point compare less than or equal to zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezq_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcle.f16"))]
 #[cfg_attr(
@@ -6459,7 +6459,7 @@ pub fn vclezq_f16(a: float16x8_t) -> uint16x8_t {
 }
 #[doc = "Count leading sign bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcls_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcls.s8"))]
@@ -6488,7 +6488,7 @@ pub fn vcls_s8(a: int8x8_t) -> int8x8_t {
 }
 #[doc = "Count leading sign bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclsq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcls.s8"))]
@@ -6517,7 +6517,7 @@ pub fn vclsq_s8(a: int8x16_t) -> int8x16_t {
 }
 #[doc = "Count leading sign bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcls_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcls.s16"))]
@@ -6546,7 +6546,7 @@ pub fn vcls_s16(a: int16x4_t) -> int16x4_t {
 }
 #[doc = "Count leading sign bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclsq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcls.s16"))]
@@ -6575,7 +6575,7 @@ pub fn vclsq_s16(a: int16x8_t) -> int16x8_t {
 }
 #[doc = "Count leading sign bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcls_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcls.s32"))]
@@ -6604,7 +6604,7 @@ pub fn vcls_s32(a: int32x2_t) -> int32x2_t {
 }
 #[doc = "Count leading sign bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclsq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcls.s32"))]
@@ -6633,7 +6633,7 @@ pub fn vclsq_s32(a: int32x4_t) -> int32x4_t {
 }
 #[doc = "Count leading sign bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcls_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcls))]
@@ -6654,7 +6654,7 @@ pub fn vcls_u8(a: uint8x8_t) -> int8x8_t {
 }
 #[doc = "Count leading sign bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclsq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcls))]
@@ -6675,7 +6675,7 @@ pub fn vclsq_u8(a: uint8x16_t) -> int8x16_t {
 }
 #[doc = "Count leading sign bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcls_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcls))]
@@ -6696,7 +6696,7 @@ pub fn vcls_u16(a: uint16x4_t) -> int16x4_t {
 }
 #[doc = "Count leading sign bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclsq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcls))]
@@ -6717,7 +6717,7 @@ pub fn vclsq_u16(a: uint16x8_t) -> int16x8_t {
 }
 #[doc = "Count leading sign bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcls_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcls))]
@@ -6738,7 +6738,7 @@ pub fn vcls_u32(a: uint32x2_t) -> int32x2_t {
 }
 #[doc = "Count leading sign bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclsq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcls))]
@@ -6759,7 +6759,7 @@ pub fn vclsq_u32(a: uint32x4_t) -> int32x4_t {
 }
 #[doc = "Floating-point compare less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f16"))]
 #[cfg_attr(
@@ -6781,7 +6781,7 @@ pub fn vclt_f16(a: float16x4_t, b: float16x4_t) -> uint16x4_t {
 }
 #[doc = "Floating-point compare less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f16"))]
 #[cfg_attr(
@@ -6803,7 +6803,7 @@ pub fn vcltq_f16(a: float16x8_t, b: float16x8_t) -> uint16x8_t {
 }
 #[doc = "Floating-point compare less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f32"))]
@@ -6824,7 +6824,7 @@ pub fn vclt_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t {
 }
 #[doc = "Floating-point compare less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f32"))]
@@ -6845,7 +6845,7 @@ pub fn vcltq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t {
 }
 #[doc = "Compare signed less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s8"))]
@@ -6866,7 +6866,7 @@ pub fn vclt_s8(a: int8x8_t, b: int8x8_t) -> uint8x8_t {
 }
 #[doc = "Compare signed less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s8"))]
@@ -6887,7 +6887,7 @@ pub fn vcltq_s8(a: int8x16_t, b: int8x16_t) -> uint8x16_t {
 }
 #[doc = "Compare signed less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s16"))]
@@ -6908,7 +6908,7 @@ pub fn vclt_s16(a: int16x4_t, b: int16x4_t) -> uint16x4_t {
 }
 #[doc = "Compare signed less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s16"))]
@@ -6929,7 +6929,7 @@ pub fn vcltq_s16(a: int16x8_t, b: int16x8_t) -> uint16x8_t {
 }
 #[doc = "Compare signed less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s32"))]
@@ -6950,7 +6950,7 @@ pub fn vclt_s32(a: int32x2_t, b: int32x2_t) -> uint32x2_t {
 }
 #[doc = "Compare signed less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s32"))]
@@ -6971,7 +6971,7 @@ pub fn vcltq_s32(a: int32x4_t, b: int32x4_t) -> uint32x4_t {
 }
 #[doc = "Compare unsigned less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u8"))]
@@ -6992,7 +6992,7 @@ pub fn vclt_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Compare unsigned less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u8"))]
@@ -7013,7 +7013,7 @@ pub fn vcltq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Compare unsigned less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u16"))]
@@ -7034,7 +7034,7 @@ pub fn vclt_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Compare unsigned less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u16"))]
@@ -7055,7 +7055,7 @@ pub fn vcltq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Compare unsigned less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u32"))]
@@ -7076,7 +7076,7 @@ pub fn vclt_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Compare unsigned less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u32"))]
@@ -7097,7 +7097,7 @@ pub fn vcltq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Floating-point compare less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltz_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclt.f16"))]
 #[cfg_attr(
@@ -7120,7 +7120,7 @@ pub fn vcltz_f16(a: float16x4_t) -> uint16x4_t {
 }
 #[doc = "Floating-point compare less than"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltzq_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclt.f16"))]
 #[cfg_attr(
@@ -7143,7 +7143,7 @@ pub fn vcltzq_f16(a: float16x8_t) -> uint16x8_t {
 }
 #[doc = "Count leading zero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i8"))]
@@ -7164,7 +7164,7 @@ pub fn vclz_s8(a: int8x8_t) -> int8x8_t {
 }
 #[doc = "Count leading zero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i8"))]
@@ -7185,7 +7185,7 @@ pub fn vclzq_s8(a: int8x16_t) -> int8x16_t {
 }
 #[doc = "Count leading zero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i16"))]
@@ -7206,7 +7206,7 @@ pub fn vclz_s16(a: int16x4_t) -> int16x4_t {
 }
 #[doc = "Count leading zero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i16"))]
@@ -7227,7 +7227,7 @@ pub fn vclzq_s16(a: int16x8_t) -> int16x8_t {
 }
 #[doc = "Count leading zero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i32"))]
@@ -7248,7 +7248,7 @@ pub fn vclz_s32(a: int32x2_t) -> int32x2_t {
 }
 #[doc = "Count leading zero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i32"))]
@@ -7269,7 +7269,7 @@ pub fn vclzq_s32(a: int32x4_t) -> int32x4_t {
 }
 #[doc = "Count leading zero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -7291,7 +7291,7 @@ pub fn vclz_u16(a: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Count leading zero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -7317,7 +7317,7 @@ pub fn vclz_u16(a: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Count leading zero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -7339,7 +7339,7 @@ pub fn vclzq_u16(a: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Count leading zero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -7365,7 +7365,7 @@ pub fn vclzq_u16(a: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Count leading zero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -7387,7 +7387,7 @@ pub fn vclz_u32(a: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Count leading zero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -7413,7 +7413,7 @@ pub fn vclz_u32(a: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Count leading zero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -7435,7 +7435,7 @@ pub fn vclzq_u32(a: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Count leading zero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -7461,7 +7461,7 @@ pub fn vclzq_u32(a: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Count leading zero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -7483,7 +7483,7 @@ pub fn vclz_u8(a: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Count leading zero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -7509,7 +7509,7 @@ pub fn vclz_u8(a: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Count leading zero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -7531,7 +7531,7 @@ pub fn vclzq_u8(a: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Count leading zero bits"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -7562,7 +7562,7 @@ pub fn vclzq_u8(a: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Population count per byte."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcnt_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcnt))]
@@ -7583,7 +7583,7 @@ pub fn vcnt_s8(a: int8x8_t) -> int8x8_t {
 }
 #[doc = "Population count per byte."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcntq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcnt))]
@@ -7604,7 +7604,7 @@ pub fn vcntq_s8(a: int8x16_t) -> int8x16_t {
 }
 #[doc = "Population count per byte."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcnt_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -7626,7 +7626,7 @@ pub fn vcnt_u8(a: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Population count per byte."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcnt_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -7652,7 +7652,7 @@ pub fn vcnt_u8(a: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Population count per byte."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcntq_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -7674,7 +7674,7 @@ pub fn vcntq_u8(a: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Population count per byte."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcntq_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -7705,7 +7705,7 @@ pub fn vcntq_u8(a: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Population count per byte."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcnt_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -7727,7 +7727,7 @@ pub fn vcnt_p8(a: poly8x8_t) -> poly8x8_t {
 }
 #[doc = "Population count per byte."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcnt_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -7753,7 +7753,7 @@ pub fn vcnt_p8(a: poly8x8_t) -> poly8x8_t {
 }
 #[doc = "Population count per byte."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcntq_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -7775,7 +7775,7 @@ pub fn vcntq_p8(a: poly8x16_t) -> poly8x16_t {
 }
 #[doc = "Population count per byte."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcntq_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -7806,7 +7806,7 @@ pub fn vcntq_p8(a: poly8x16_t) -> poly8x16_t {
 }
 #[doc = "Join two smaller vectors into a single larger vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
@@ -7825,7 +7825,7 @@ pub fn vcombine_f16(a: float16x4_t, b: float16x4_t) -> float16x8_t {
 }
 #[doc = "Join two smaller vectors into a single larger vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -7842,7 +7842,7 @@ pub fn vcombine_f32(a: float32x2_t, b: float32x2_t) -> float32x4_t {
 }
 #[doc = "Join two smaller vectors into a single larger vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -7859,7 +7859,7 @@ pub fn vcombine_s8(a: int8x8_t, b: int8x8_t) -> int8x16_t {
 }
 #[doc = "Join two smaller vectors into a single larger vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -7876,7 +7876,7 @@ pub fn vcombine_s16(a: int16x4_t, b: int16x4_t) -> int16x8_t {
 }
 #[doc = "Join two smaller vectors into a single larger vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -7893,7 +7893,7 @@ pub fn vcombine_s32(a: int32x2_t, b: int32x2_t) -> int32x4_t {
 }
 #[doc = "Join two smaller vectors into a single larger vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -7910,7 +7910,7 @@ pub fn vcombine_s64(a: int64x1_t, b: int64x1_t) -> int64x2_t {
 }
 #[doc = "Join two smaller vectors into a single larger vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -7927,7 +7927,7 @@ pub fn vcombine_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x16_t {
 }
 #[doc = "Join two smaller vectors into a single larger vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -7944,7 +7944,7 @@ pub fn vcombine_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x8_t {
 }
 #[doc = "Join two smaller vectors into a single larger vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -7961,7 +7961,7 @@ pub fn vcombine_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x4_t {
 }
 #[doc = "Join two smaller vectors into a single larger vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -7978,7 +7978,7 @@ pub fn vcombine_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x2_t {
 }
 #[doc = "Join two smaller vectors into a single larger vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -7995,7 +7995,7 @@ pub fn vcombine_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x16_t {
 }
 #[doc = "Join two smaller vectors into a single larger vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_p16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -8012,7 +8012,7 @@ pub fn vcombine_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x8_t {
 }
 #[doc = "Join two smaller vectors into a single larger vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_p64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -8029,7 +8029,7 @@ pub fn vcombine_p64(a: poly64x1_t, b: poly64x1_t) -> poly64x2_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -8053,7 +8053,7 @@ pub fn vcreate_f16(a: u64) -> float16x4_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -8080,7 +8080,7 @@ pub fn vcreate_f16(a: u64) -> float16x4_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -8102,7 +8102,7 @@ pub fn vcreate_f32(a: u64) -> float32x2_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -8127,7 +8127,7 @@ pub fn vcreate_f32(a: u64) -> float32x2_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -8149,7 +8149,7 @@ pub fn vcreate_s8(a: u64) -> int8x8_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -8174,7 +8174,7 @@ pub fn vcreate_s8(a: u64) -> int8x8_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -8196,7 +8196,7 @@ pub fn vcreate_s16(a: u64) -> int16x4_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -8221,7 +8221,7 @@ pub fn vcreate_s16(a: u64) -> int16x4_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -8243,7 +8243,7 @@ pub fn vcreate_s32(a: u64) -> int32x2_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -8268,7 +8268,7 @@ pub fn vcreate_s32(a: u64) -> int32x2_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -8289,7 +8289,7 @@ pub fn vcreate_s64(a: u64) -> int64x1_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -8311,7 +8311,7 @@ pub fn vcreate_u8(a: u64) -> uint8x8_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -8336,7 +8336,7 @@ pub fn vcreate_u8(a: u64) -> uint8x8_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -8358,7 +8358,7 @@ pub fn vcreate_u16(a: u64) -> uint16x4_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -8383,7 +8383,7 @@ pub fn vcreate_u16(a: u64) -> uint16x4_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -8405,7 +8405,7 @@ pub fn vcreate_u32(a: u64) -> uint32x2_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -8430,7 +8430,7 @@ pub fn vcreate_u32(a: u64) -> uint32x2_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -8451,7 +8451,7 @@ pub fn vcreate_u64(a: u64) -> uint64x1_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -8473,7 +8473,7 @@ pub fn vcreate_p8(a: u64) -> poly8x8_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -8498,7 +8498,7 @@ pub fn vcreate_p8(a: u64) -> poly8x8_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -8520,7 +8520,7 @@ pub fn vcreate_p16(a: u64) -> poly16x4_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -8545,7 +8545,7 @@ pub fn vcreate_p16(a: u64) -> poly16x4_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_p64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -8566,7 +8566,7 @@ pub fn vcreate_p64(a: u64) -> poly64x1_t {
 }
 #[doc = "Floating-point convert to lower precision narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f16_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
@@ -8589,7 +8589,7 @@ pub fn vcvt_f16_f32(a: float32x4_t) -> float16x4_t {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f16_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
 #[cfg_attr(
@@ -8611,7 +8611,7 @@ pub fn vcvt_f16_s16(a: int16x4_t) -> float16x4_t {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_f16_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
 #[cfg_attr(
@@ -8633,7 +8633,7 @@ pub fn vcvtq_f16_s16(a: int16x8_t) -> float16x8_t {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f16_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
 #[cfg_attr(
@@ -8655,7 +8655,7 @@ pub fn vcvt_f16_u16(a: uint16x4_t) -> float16x4_t {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_f16_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
 #[cfg_attr(
@@ -8677,7 +8677,7 @@ pub fn vcvtq_f16_u16(a: uint16x8_t) -> float16x8_t {
 }
 #[doc = "Floating-point convert to higher precision long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f32_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
@@ -8700,7 +8700,7 @@ pub fn vcvt_f32_f16(a: float16x4_t) -> float32x4_t {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f32_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
@@ -8721,7 +8721,7 @@ pub fn vcvt_f32_s32(a: int32x2_t) -> float32x2_t {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_f32_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
@@ -8742,7 +8742,7 @@ pub fn vcvtq_f32_s32(a: int32x4_t) -> float32x4_t {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f32_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
@@ -8763,7 +8763,7 @@ pub fn vcvt_f32_u32(a: uint32x2_t) -> float32x2_t {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_f32_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
@@ -8784,7 +8784,7 @@ pub fn vcvtq_f32_u32(a: uint32x4_t) -> float32x4_t {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_f16_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcvt", N = 1))]
 #[cfg_attr(
@@ -8819,7 +8819,7 @@ pub fn vcvt_n_f16_s16<const N: i32>(a: int16x4_t) -> float16x4_t {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_f16_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcvt", N = 1))]
 #[cfg_attr(
@@ -8854,7 +8854,7 @@ pub fn vcvtq_n_f16_s16<const N: i32>(a: int16x8_t) -> float16x8_t {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_f16_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcvt", N = 1))]
 #[cfg_attr(
@@ -8889,7 +8889,7 @@ pub fn vcvt_n_f16_u16<const N: i32>(a: uint16x4_t) -> float16x4_t {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_f16_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcvt", N = 1))]
 #[cfg_attr(
@@ -8924,7 +8924,7 @@ pub fn vcvtq_n_f16_u16<const N: i32>(a: uint16x8_t) -> float16x8_t {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_f32_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vcvt, N = 2))]
@@ -8943,7 +8943,7 @@ pub fn vcvt_n_f32_s32<const N: i32>(a: int32x2_t) -> float32x2_t {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_f32_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vcvt, N = 2))]
@@ -8962,7 +8962,7 @@ pub fn vcvtq_n_f32_s32<const N: i32>(a: int32x4_t) -> float32x4_t {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_f32_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(scvtf, N = 2))]
@@ -8981,7 +8981,7 @@ pub fn vcvt_n_f32_s32<const N: i32>(a: int32x2_t) -> float32x2_t {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_f32_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(scvtf, N = 2))]
@@ -9000,7 +9000,7 @@ pub fn vcvtq_n_f32_s32<const N: i32>(a: int32x4_t) -> float32x4_t {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_f32_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vcvt, N = 2))]
@@ -9019,7 +9019,7 @@ pub fn vcvt_n_f32_u32<const N: i32>(a: uint32x2_t) -> float32x2_t {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_f32_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vcvt, N = 2))]
@@ -9038,7 +9038,7 @@ pub fn vcvtq_n_f32_u32<const N: i32>(a: uint32x4_t) -> float32x4_t {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_f32_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(ucvtf, N = 2))]
@@ -9057,7 +9057,7 @@ pub fn vcvt_n_f32_u32<const N: i32>(a: uint32x2_t) -> float32x2_t {
 }
 #[doc = "Fixed-point convert to floating-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_f32_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(ucvtf, N = 2))]
@@ -9076,7 +9076,7 @@ pub fn vcvtq_n_f32_u32<const N: i32>(a: uint32x4_t) -> float32x4_t {
 }
 #[doc = "Floating-point convert to signed fixed-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_s16_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcvt", N = 1))]
 #[cfg_attr(
@@ -9111,7 +9111,7 @@ pub fn vcvt_n_s16_f16<const N: i32>(a: float16x4_t) -> int16x4_t {
 }
 #[doc = "Floating-point convert to signed fixed-point"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_s16_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcvt", N = 1))]
 #[cfg_attr(
@@ -9146,7 +9146,7 @@ pub fn vcvtq_n_s16_f16<const N: i32>(a: float16x8_t) -> int16x8_t {
 }
 #[doc = "Floating-point convert to fixed-point, rounding toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_s32_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vcvt, N = 2))]
@@ -9165,7 +9165,7 @@ pub fn vcvt_n_s32_f32<const N: i32>(a: float32x2_t) -> int32x2_t {
 }
 #[doc = "Floating-point convert to fixed-point, rounding toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_s32_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vcvt, N = 2))]
@@ -9184,7 +9184,7 @@ pub fn vcvtq_n_s32_f32<const N: i32>(a: float32x4_t) -> int32x4_t {
 }
 #[doc = "Floating-point convert to fixed-point, rounding toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_s32_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(fcvtzs, N = 2))]
@@ -9203,7 +9203,7 @@ pub fn vcvt_n_s32_f32<const N: i32>(a: float32x2_t) -> int32x2_t {
 }
 #[doc = "Floating-point convert to fixed-point, rounding toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_s32_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(fcvtzs, N = 2))]
@@ -9222,7 +9222,7 @@ pub fn vcvtq_n_s32_f32<const N: i32>(a: float32x4_t) -> int32x4_t {
 }
 #[doc = "Fixed-point convert to unsigned fixed-point, rounding toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_u16_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcvt", N = 1))]
 #[cfg_attr(
@@ -9257,7 +9257,7 @@ pub fn vcvt_n_u16_f16<const N: i32>(a: float16x4_t) -> uint16x4_t {
 }
 #[doc = "Fixed-point convert to unsigned fixed-point, rounding toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_u16_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcvt", N = 1))]
 #[cfg_attr(
@@ -9292,7 +9292,7 @@ pub fn vcvtq_n_u16_f16<const N: i32>(a: float16x8_t) -> uint16x8_t {
 }
 #[doc = "Floating-point convert to fixed-point, rounding toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_u32_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vcvt, N = 2))]
@@ -9311,7 +9311,7 @@ pub fn vcvt_n_u32_f32<const N: i32>(a: float32x2_t) -> uint32x2_t {
 }
 #[doc = "Floating-point convert to fixed-point, rounding toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_u32_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vcvt, N = 2))]
@@ -9330,7 +9330,7 @@ pub fn vcvtq_n_u32_f32<const N: i32>(a: float32x4_t) -> uint32x4_t {
 }
 #[doc = "Floating-point convert to fixed-point, rounding toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_u32_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(fcvtzu, N = 2))]
@@ -9349,7 +9349,7 @@ pub fn vcvt_n_u32_f32<const N: i32>(a: float32x2_t) -> uint32x2_t {
 }
 #[doc = "Floating-point convert to fixed-point, rounding toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_u32_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(fcvtzu, N = 2))]
@@ -9368,7 +9368,7 @@ pub fn vcvtq_n_u32_f32<const N: i32>(a: float32x4_t) -> uint32x4_t {
 }
 #[doc = "Floating-point convert to signed fixed-point, rounding toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_s16_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
 #[cfg_attr(
@@ -9390,7 +9390,7 @@ pub fn vcvt_s16_f16(a: float16x4_t) -> int16x4_t {
 }
 #[doc = "Floating-point convert to signed fixed-point, rounding toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_s16_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
 #[cfg_attr(
@@ -9412,7 +9412,7 @@ pub fn vcvtq_s16_f16(a: float16x8_t) -> int16x8_t {
 }
 #[doc = "Floating-point convert to signed fixed-point, rounding toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_s32_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
@@ -9441,7 +9441,7 @@ pub fn vcvt_s32_f32(a: float32x2_t) -> int32x2_t {
 }
 #[doc = "Floating-point convert to signed fixed-point, rounding toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_s32_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
@@ -9470,7 +9470,7 @@ pub fn vcvtq_s32_f32(a: float32x4_t) -> int32x4_t {
 }
 #[doc = "Floating-point convert to unsigned fixed-point, rounding toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_u16_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
 #[cfg_attr(
@@ -9492,7 +9492,7 @@ pub fn vcvt_u16_f16(a: float16x4_t) -> uint16x4_t {
 }
 #[doc = "Floating-point convert to unsigned fixed-point, rounding toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_u16_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
 #[cfg_attr(
@@ -9514,7 +9514,7 @@ pub fn vcvtq_u16_f16(a: float16x8_t) -> uint16x8_t {
 }
 #[doc = "Floating-point convert to unsigned fixed-point, rounding toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_u32_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
@@ -9543,7 +9543,7 @@ pub fn vcvt_u32_f32(a: float32x2_t) -> uint32x2_t {
 }
 #[doc = "Floating-point convert to unsigned fixed-point, rounding toward zero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_u32_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))]
@@ -9572,7 +9572,7 @@ pub fn vcvtq_u32_f32(a: float32x4_t) -> uint32x4_t {
 }
 #[doc = "Dot product arithmetic (indexed)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_lane_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[target_feature(enable = "neon,dotprod")]
@@ -9600,7 +9600,7 @@ pub fn vdot_lane_s32<const LANE: i32>(a: int32x2_t, b: int8x8_t, c: int8x8_t) ->
 }
 #[doc = "Dot product arithmetic (indexed)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_lane_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[target_feature(enable = "neon,dotprod")]
@@ -9632,7 +9632,7 @@ pub fn vdot_lane_s32<const LANE: i32>(a: int32x2_t, b: int8x8_t, c: int8x8_t) ->
 }
 #[doc = "Dot product arithmetic (indexed)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_lane_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[target_feature(enable = "neon,dotprod")]
@@ -9661,7 +9661,7 @@ pub fn vdotq_lane_s32<const LANE: i32>(a: int32x4_t, b: int8x16_t, c: int8x8_t)
 }
 #[doc = "Dot product arithmetic (indexed)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_lane_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[target_feature(enable = "neon,dotprod")]
@@ -9695,7 +9695,7 @@ pub fn vdotq_lane_s32<const LANE: i32>(a: int32x4_t, b: int8x16_t, c: int8x8_t)
 }
 #[doc = "Dot product arithmetic (indexed)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_lane_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[target_feature(enable = "neon,dotprod")]
@@ -9723,7 +9723,7 @@ pub fn vdot_lane_u32<const LANE: i32>(a: uint32x2_t, b: uint8x8_t, c: uint8x8_t)
 }
 #[doc = "Dot product arithmetic (indexed)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_lane_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[target_feature(enable = "neon,dotprod")]
@@ -9755,7 +9755,7 @@ pub fn vdot_lane_u32<const LANE: i32>(a: uint32x2_t, b: uint8x8_t, c: uint8x8_t)
 }
 #[doc = "Dot product arithmetic (indexed)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_lane_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[target_feature(enable = "neon,dotprod")]
@@ -9784,7 +9784,7 @@ pub fn vdotq_lane_u32<const LANE: i32>(a: uint32x4_t, b: uint8x16_t, c: uint8x8_
 }
 #[doc = "Dot product arithmetic (indexed)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_lane_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[target_feature(enable = "neon,dotprod")]
@@ -9818,7 +9818,7 @@ pub fn vdotq_lane_u32<const LANE: i32>(a: uint32x4_t, b: uint8x16_t, c: uint8x8_
 }
 #[doc = "Dot product arithmetic (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[target_feature(enable = "neon,dotprod")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsdot))]
@@ -9847,7 +9847,7 @@ pub fn vdot_s32(a: int32x2_t, b: int8x8_t, c: int8x8_t) -> int32x2_t {
 }
 #[doc = "Dot product arithmetic (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[target_feature(enable = "neon,dotprod")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsdot))]
@@ -9876,7 +9876,7 @@ pub fn vdotq_s32(a: int32x4_t, b: int8x16_t, c: int8x16_t) -> int32x4_t {
 }
 #[doc = "Dot product arithmetic (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[target_feature(enable = "neon,dotprod")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vudot))]
@@ -9905,7 +9905,7 @@ pub fn vdot_u32(a: uint32x2_t, b: uint8x8_t, c: uint8x8_t) -> uint32x2_t {
 }
 #[doc = "Dot product arithmetic (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[target_feature(enable = "neon,dotprod")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vudot))]
@@ -9934,7 +9934,7 @@ pub fn vdotq_u32(a: uint32x4_t, b: uint8x16_t, c: uint8x16_t) -> uint32x4_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))]
@@ -9959,7 +9959,7 @@ pub fn vdup_lane_f16<const N: i32>(a: float16x4_t) -> float16x4_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))]
@@ -9990,7 +9990,7 @@ pub fn vdupq_lane_f16<const N: i32>(a: float16x4_t) -> float16x8_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 1))]
@@ -10013,7 +10013,7 @@ pub fn vdup_lane_f32<const N: i32>(a: float32x2_t) -> float32x2_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 1))]
@@ -10036,7 +10036,7 @@ pub fn vdup_lane_s32<const N: i32>(a: int32x2_t) -> int32x2_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 1))]
@@ -10059,7 +10059,7 @@ pub fn vdup_lane_u32<const N: i32>(a: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 1))]
@@ -10082,7 +10082,7 @@ pub fn vdupq_lane_f32<const N: i32>(a: float32x2_t) -> float32x4_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 1))]
@@ -10105,7 +10105,7 @@ pub fn vdupq_lane_s32<const N: i32>(a: int32x2_t) -> int32x4_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 1))]
@@ -10128,7 +10128,7 @@ pub fn vdupq_lane_u32<const N: i32>(a: uint32x2_t) -> uint32x4_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_p16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))]
@@ -10151,7 +10151,7 @@ pub fn vdup_lane_p16<const N: i32>(a: poly16x4_t) -> poly16x4_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))]
@@ -10174,7 +10174,7 @@ pub fn vdup_lane_s16<const N: i32>(a: int16x4_t) -> int16x4_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))]
@@ -10197,7 +10197,7 @@ pub fn vdup_lane_u16<const N: i32>(a: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_p16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))]
@@ -10226,7 +10226,7 @@ pub fn vdupq_lane_p16<const N: i32>(a: poly16x4_t) -> poly16x8_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))]
@@ -10255,7 +10255,7 @@ pub fn vdupq_lane_s16<const N: i32>(a: int16x4_t) -> int16x8_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))]
@@ -10284,7 +10284,7 @@ pub fn vdupq_lane_u16<const N: i32>(a: uint16x4_t) -> uint16x8_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 4))]
@@ -10313,7 +10313,7 @@ pub fn vdup_lane_p8<const N: i32>(a: poly8x8_t) -> poly8x8_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 4))]
@@ -10342,7 +10342,7 @@ pub fn vdup_lane_s8<const N: i32>(a: int8x8_t) -> int8x8_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 4))]
@@ -10371,7 +10371,7 @@ pub fn vdup_lane_u8<const N: i32>(a: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 4))]
@@ -10403,7 +10403,7 @@ pub fn vdupq_lane_p8<const N: i32>(a: poly8x8_t) -> poly8x16_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 4))]
@@ -10435,7 +10435,7 @@ pub fn vdupq_lane_s8<const N: i32>(a: int8x8_t) -> int8x16_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 4))]
@@ -10467,7 +10467,7 @@ pub fn vdupq_lane_u8<const N: i32>(a: uint8x8_t) -> uint8x16_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, N = 0))]
@@ -10490,7 +10490,7 @@ pub fn vdup_lane_s64<const N: i32>(a: int64x1_t) -> int64x1_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, N = 0))]
@@ -10513,7 +10513,7 @@ pub fn vdup_lane_u64<const N: i32>(a: uint64x1_t) -> uint64x1_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))]
@@ -10538,7 +10538,7 @@ pub fn vdup_laneq_f16<const N: i32>(a: float16x8_t) -> float16x4_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))]
@@ -10569,7 +10569,7 @@ pub fn vdupq_laneq_f16<const N: i32>(a: float16x8_t) -> float16x8_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 2))]
@@ -10592,7 +10592,7 @@ pub fn vdup_laneq_f32<const N: i32>(a: float32x4_t) -> float32x2_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 2))]
@@ -10615,7 +10615,7 @@ pub fn vdup_laneq_s32<const N: i32>(a: int32x4_t) -> int32x2_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 2))]
@@ -10638,7 +10638,7 @@ pub fn vdup_laneq_u32<const N: i32>(a: uint32x4_t) -> uint32x2_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 2))]
@@ -10661,7 +10661,7 @@ pub fn vdupq_laneq_f32<const N: i32>(a: float32x4_t) -> float32x4_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 2))]
@@ -10684,7 +10684,7 @@ pub fn vdupq_laneq_s32<const N: i32>(a: int32x4_t) -> int32x4_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 2))]
@@ -10707,7 +10707,7 @@ pub fn vdupq_laneq_u32<const N: i32>(a: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_p16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))]
@@ -10730,7 +10730,7 @@ pub fn vdup_laneq_p16<const N: i32>(a: poly16x8_t) -> poly16x4_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))]
@@ -10753,7 +10753,7 @@ pub fn vdup_laneq_s16<const N: i32>(a: int16x8_t) -> int16x4_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))]
@@ -10776,7 +10776,7 @@ pub fn vdup_laneq_u16<const N: i32>(a: uint16x8_t) -> uint16x4_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_p16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))]
@@ -10805,7 +10805,7 @@ pub fn vdupq_laneq_p16<const N: i32>(a: poly16x8_t) -> poly16x8_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))]
@@ -10834,7 +10834,7 @@ pub fn vdupq_laneq_s16<const N: i32>(a: int16x8_t) -> int16x8_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))]
@@ -10863,7 +10863,7 @@ pub fn vdupq_laneq_u16<const N: i32>(a: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 8))]
@@ -10892,7 +10892,7 @@ pub fn vdup_laneq_p8<const N: i32>(a: poly8x16_t) -> poly8x8_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 8))]
@@ -10921,7 +10921,7 @@ pub fn vdup_laneq_s8<const N: i32>(a: int8x16_t) -> int8x8_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 8))]
@@ -10950,7 +10950,7 @@ pub fn vdup_laneq_u8<const N: i32>(a: uint8x16_t) -> uint8x8_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 8))]
@@ -10982,7 +10982,7 @@ pub fn vdupq_laneq_p8<const N: i32>(a: poly8x16_t) -> poly8x16_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 8))]
@@ -11014,7 +11014,7 @@ pub fn vdupq_laneq_s8<const N: i32>(a: int8x16_t) -> int8x16_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 8))]
@@ -11046,7 +11046,7 @@ pub fn vdupq_laneq_u8<const N: i32>(a: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 1))]
@@ -11069,7 +11069,7 @@ pub fn vdup_laneq_s64<const N: i32>(a: int64x2_t) -> int64x1_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 1))]
@@ -11092,7 +11092,7 @@ pub fn vdup_laneq_u64<const N: i32>(a: uint64x2_t) -> uint64x1_t {
 }
 #[doc = "Create a new vector with all lanes set to a value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
@@ -11108,7 +11108,7 @@ pub fn vdup_n_f16(a: f16) -> float16x4_t {
 }
 #[doc = "Create a new vector with all lanes set to a value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
@@ -11124,7 +11124,7 @@ pub fn vdupq_n_f16(a: f16) -> float16x8_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))]
@@ -11145,7 +11145,7 @@ pub fn vdup_n_f32(value: f32) -> float32x2_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_p16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
@@ -11166,7 +11166,7 @@ pub fn vdup_n_p16(value: p16) -> poly16x4_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))]
@@ -11187,7 +11187,7 @@ pub fn vdup_n_p8(value: p8) -> poly8x8_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
@@ -11208,7 +11208,7 @@ pub fn vdup_n_s16(value: i16) -> int16x4_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))]
@@ -11229,7 +11229,7 @@ pub fn vdup_n_s32(value: i32) -> int32x2_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
@@ -11250,7 +11250,7 @@ pub fn vdup_n_s64(value: i64) -> int64x1_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))]
@@ -11271,7 +11271,7 @@ pub fn vdup_n_s8(value: i8) -> int8x8_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
@@ -11292,7 +11292,7 @@ pub fn vdup_n_u16(value: u16) -> uint16x4_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))]
@@ -11313,7 +11313,7 @@ pub fn vdup_n_u32(value: u32) -> uint32x2_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
@@ -11334,7 +11334,7 @@ pub fn vdup_n_u64(value: u64) -> uint64x1_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))]
@@ -11355,7 +11355,7 @@ pub fn vdup_n_u8(value: u8) -> uint8x8_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))]
@@ -11376,7 +11376,7 @@ pub fn vdupq_n_f32(value: f32) -> float32x4_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_p16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
@@ -11397,7 +11397,7 @@ pub fn vdupq_n_p16(value: p16) -> poly16x8_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))]
@@ -11418,7 +11418,7 @@ pub fn vdupq_n_p8(value: p8) -> poly8x16_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
@@ -11439,7 +11439,7 @@ pub fn vdupq_n_s16(value: i16) -> int16x8_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))]
@@ -11460,7 +11460,7 @@ pub fn vdupq_n_s32(value: i32) -> int32x4_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
@@ -11481,7 +11481,7 @@ pub fn vdupq_n_s64(value: i64) -> int64x2_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))]
@@ -11502,7 +11502,7 @@ pub fn vdupq_n_s8(value: i8) -> int8x16_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
@@ -11523,7 +11523,7 @@ pub fn vdupq_n_u16(value: u16) -> uint16x8_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))]
@@ -11544,7 +11544,7 @@ pub fn vdupq_n_u32(value: u32) -> uint32x4_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
@@ -11565,7 +11565,7 @@ pub fn vdupq_n_u64(value: u64) -> uint64x2_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))]
@@ -11586,7 +11586,7 @@ pub fn vdupq_n_u8(value: u8) -> uint8x16_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_f32_vfp4)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))]
@@ -11607,7 +11607,7 @@ fn vdup_n_f32_vfp4(value: f32) -> float32x2_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_f32_vfp4)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))]
@@ -11628,7 +11628,7 @@ fn vdupq_n_f32_vfp4(value: f32) -> float32x4_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 0))]
@@ -11651,7 +11651,7 @@ pub fn vdupq_lane_s64<const N: i32>(a: int64x1_t) -> int64x2_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 0))]
@@ -11674,7 +11674,7 @@ pub fn vdupq_lane_u64<const N: i32>(a: uint64x1_t) -> uint64x2_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 1))]
@@ -11697,7 +11697,7 @@ pub fn vdupq_laneq_s64<const N: i32>(a: int64x2_t) -> int64x2_t {
 }
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 1))]
@@ -11720,7 +11720,7 @@ pub fn vdupq_laneq_u64<const N: i32>(a: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Vector bitwise exclusive or (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
@@ -11741,7 +11741,7 @@ pub fn veor_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Vector bitwise exclusive or (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
@@ -11762,7 +11762,7 @@ pub fn veorq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Vector bitwise exclusive or (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
@@ -11783,7 +11783,7 @@ pub fn veor_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Vector bitwise exclusive or (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
@@ -11804,7 +11804,7 @@ pub fn veorq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Vector bitwise exclusive or (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
@@ -11825,7 +11825,7 @@ pub fn veor_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Vector bitwise exclusive or (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
@@ -11846,7 +11846,7 @@ pub fn veorq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Vector bitwise exclusive or (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
@@ -11867,7 +11867,7 @@ pub fn veor_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t {
 }
 #[doc = "Vector bitwise exclusive or (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
@@ -11888,7 +11888,7 @@ pub fn veorq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
 }
 #[doc = "Vector bitwise exclusive or (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
@@ -11909,7 +11909,7 @@ pub fn veor_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Vector bitwise exclusive or (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
@@ -11930,7 +11930,7 @@ pub fn veorq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Vector bitwise exclusive or (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
@@ -11951,7 +11951,7 @@ pub fn veor_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Vector bitwise exclusive or (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
@@ -11972,7 +11972,7 @@ pub fn veorq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Vector bitwise exclusive or (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
@@ -11993,7 +11993,7 @@ pub fn veor_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Vector bitwise exclusive or (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
@@ -12014,7 +12014,7 @@ pub fn veorq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Vector bitwise exclusive or (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
@@ -12035,7 +12035,7 @@ pub fn veor_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
 }
 #[doc = "Vector bitwise exclusive or (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))]
@@ -12056,7 +12056,7 @@ pub fn veorq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Extract vector from pair of vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))]
 #[cfg_attr(
@@ -12088,7 +12088,7 @@ pub fn vext_f16<const N: i32>(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 }
 #[doc = "Extract vector from pair of vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 1))]
@@ -12117,7 +12117,7 @@ pub fn vext_f32<const N: i32>(a: float32x2_t, b: float32x2_t) -> float32x2_t {
 }
 #[doc = "Extract vector from pair of vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 1))]
@@ -12146,7 +12146,7 @@ pub fn vext_s32<const N: i32>(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Extract vector from pair of vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 1))]
@@ -12177,7 +12177,7 @@ pub fn vext_u32<const N: i32>(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, N = 0))]
@@ -12202,7 +12202,7 @@ pub unsafe fn vext_s64<const N: i32>(a: int64x1_t, _b: int64x1_t) -> int64x1_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, N = 0))]
@@ -12225,7 +12225,7 @@ pub unsafe fn vext_u64<const N: i32>(a: uint64x1_t, _b: uint64x1_t) -> uint64x1_
 }
 #[doc = "Extract vector from pair of vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))]
@@ -12260,7 +12260,7 @@ pub fn vext_s8<const N: i32>(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Extract vector from pair of vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))]
@@ -12295,7 +12295,7 @@ pub fn vextq_s16<const N: i32>(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Extract vector from pair of vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))]
@@ -12330,7 +12330,7 @@ pub fn vext_u8<const N: i32>(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Extract vector from pair of vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))]
@@ -12365,7 +12365,7 @@ pub fn vextq_u16<const N: i32>(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Extract vector from pair of vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))]
@@ -12400,7 +12400,7 @@ pub fn vext_p8<const N: i32>(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
 }
 #[doc = "Extract vector from pair of vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_p16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))]
@@ -12435,7 +12435,7 @@ pub fn vextq_p16<const N: i32>(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t {
 }
 #[doc = "Extract vector from pair of vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))]
 #[cfg_attr(
@@ -12471,7 +12471,7 @@ pub fn vextq_f16<const N: i32>(a: float16x8_t, b: float16x8_t) -> float16x8_t {
 }
 #[doc = "Extract vector from pair of vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))]
@@ -12502,7 +12502,7 @@ pub fn vextq_f32<const N: i32>(a: float32x4_t, b: float32x4_t) -> float32x4_t {
 }
 #[doc = "Extract vector from pair of vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))]
@@ -12533,7 +12533,7 @@ pub fn vext_s16<const N: i32>(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Extract vector from pair of vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))]
@@ -12564,7 +12564,7 @@ pub fn vextq_s32<const N: i32>(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Extract vector from pair of vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))]
@@ -12595,7 +12595,7 @@ pub fn vext_u16<const N: i32>(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Extract vector from pair of vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))]
@@ -12626,7 +12626,7 @@ pub fn vextq_u32<const N: i32>(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Extract vector from pair of vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_p16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))]
@@ -12657,7 +12657,7 @@ pub fn vext_p16<const N: i32>(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t {
 }
 #[doc = "Extract vector from pair of vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 1))]
@@ -12686,7 +12686,7 @@ pub fn vextq_s64<const N: i32>(a: int64x2_t, b: int64x2_t) -> int64x2_t {
 }
 #[doc = "Extract vector from pair of vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 1))]
@@ -12715,7 +12715,7 @@ pub fn vextq_u64<const N: i32>(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Extract vector from pair of vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 15))]
@@ -12818,7 +12818,7 @@ pub fn vextq_s8<const N: i32>(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Extract vector from pair of vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 15))]
@@ -12921,7 +12921,7 @@ pub fn vextq_u8<const N: i32>(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Extract vector from pair of vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 15))]
@@ -13024,7 +13024,7 @@ pub fn vextq_p8<const N: i32>(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t {
 }
 #[doc = "Floating-point fused Multiply-Add to accumulator (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfma))]
 #[cfg_attr(
@@ -13046,7 +13046,7 @@ pub fn vfma_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t {
 }
 #[doc = "Floating-point fused Multiply-Add to accumulator (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfma))]
 #[cfg_attr(
@@ -13068,7 +13068,7 @@ pub fn vfmaq_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> float16x8_t
 }
 #[doc = "Floating-point fused Multiply-Add to accumulator(vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfma))]
@@ -13089,7 +13089,7 @@ pub fn vfma_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t {
 }
 #[doc = "Floating-point fused Multiply-Add to accumulator(vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfma))]
@@ -13110,7 +13110,7 @@ pub fn vfmaq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t
 }
 #[doc = "Floating-point fused Multiply-Add to accumulator(vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_n_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfma))]
@@ -13131,7 +13131,7 @@ pub fn vfma_n_f32(a: float32x2_t, b: float32x2_t, c: f32) -> float32x2_t {
 }
 #[doc = "Floating-point fused Multiply-Add to accumulator(vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_n_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfma))]
@@ -13152,7 +13152,7 @@ pub fn vfmaq_n_f32(a: float32x4_t, b: float32x4_t, c: f32) -> float32x4_t {
 }
 #[doc = "Floating-point fused multiply-subtract from accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -13178,7 +13178,7 @@ pub fn vfms_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t {
 }
 #[doc = "Floating-point fused multiply-subtract from accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -13204,7 +13204,7 @@ pub fn vfmsq_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> float16x8_t
 }
 #[doc = "Floating-point fused multiply-subtract from accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfms))]
@@ -13228,7 +13228,7 @@ pub fn vfms_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t {
 }
 #[doc = "Floating-point fused multiply-subtract from accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfms))]
@@ -13252,7 +13252,7 @@ pub fn vfmsq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t
 }
 #[doc = "Floating-point fused Multiply-subtract to accumulator(vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_n_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfms))]
@@ -13273,7 +13273,7 @@ pub fn vfms_n_f32(a: float32x2_t, b: float32x2_t, c: f32) -> float32x2_t {
 }
 #[doc = "Floating-point fused Multiply-subtract to accumulator(vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_n_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfms))]
@@ -13294,7 +13294,7 @@ pub fn vfmsq_n_f32(a: float32x4_t, b: float32x4_t, c: f32) -> float32x4_t {
 }
 #[doc = "Duplicate vector element to vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
@@ -13313,7 +13313,7 @@ pub fn vget_high_f16(a: float16x8_t) -> float16x4_t {
 }
 #[doc = "Duplicate vector element to vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
@@ -13332,7 +13332,7 @@ pub fn vget_low_f16(a: float16x8_t) -> float16x4_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
@@ -13353,7 +13353,7 @@ pub fn vget_high_f32(a: float32x4_t) -> float32x2_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_p16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
@@ -13374,7 +13374,7 @@ pub fn vget_high_p16(a: poly16x8_t) -> poly16x4_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
@@ -13395,7 +13395,7 @@ pub fn vget_high_p8(a: poly8x16_t) -> poly8x8_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
@@ -13416,7 +13416,7 @@ pub fn vget_high_s16(a: int16x8_t) -> int16x4_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
@@ -13437,7 +13437,7 @@ pub fn vget_high_s32(a: int32x4_t) -> int32x2_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
@@ -13458,7 +13458,7 @@ pub fn vget_high_s8(a: int8x16_t) -> int8x8_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
@@ -13479,7 +13479,7 @@ pub fn vget_high_u16(a: uint16x8_t) -> uint16x4_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
@@ -13500,7 +13500,7 @@ pub fn vget_high_u32(a: uint32x4_t) -> uint32x2_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
@@ -13521,7 +13521,7 @@ pub fn vget_high_u8(a: uint8x16_t) -> uint8x8_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
@@ -13542,7 +13542,7 @@ pub fn vget_high_s64(a: int64x2_t) -> int64x1_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
@@ -13563,7 +13563,7 @@ pub fn vget_high_u64(a: uint64x2_t) -> uint64x1_t {
 }
 #[doc = "Duplicate vector element to scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -13581,7 +13581,7 @@ pub fn vget_lane_f16<const LANE: i32>(a: float16x4_t) -> f16 {
 }
 #[doc = "Duplicate vector element to scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -13599,7 +13599,7 @@ pub fn vgetq_lane_f16<const LANE: i32>(a: float16x8_t) -> f16 {
 }
 #[doc = "Move vector element to general-purpose register"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(1)]
@@ -13618,7 +13618,7 @@ pub fn vget_lane_f32<const IMM5: i32>(v: float32x2_t) -> f32 {
 }
 #[doc = "Move vector element to general-purpose register"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_p16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(1)]
@@ -13637,7 +13637,7 @@ pub fn vget_lane_p16<const IMM5: i32>(v: poly16x4_t) -> p16 {
 }
 #[doc = "Move vector element to general-purpose register"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(1)]
@@ -13656,7 +13656,7 @@ pub fn vget_lane_p8<const IMM5: i32>(v: poly8x8_t) -> p8 {
 }
 #[doc = "Move vector element to general-purpose register"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(1)]
@@ -13675,7 +13675,7 @@ pub fn vget_lane_s16<const IMM5: i32>(v: int16x4_t) -> i16 {
 }
 #[doc = "Move vector element to general-purpose register"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(1)]
@@ -13694,7 +13694,7 @@ pub fn vget_lane_s32<const IMM5: i32>(v: int32x2_t) -> i32 {
 }
 #[doc = "Move vector element to general-purpose register"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(1)]
@@ -13713,7 +13713,7 @@ pub fn vget_lane_s8<const IMM5: i32>(v: int8x8_t) -> i8 {
 }
 #[doc = "Move vector element to general-purpose register"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(1)]
@@ -13732,7 +13732,7 @@ pub fn vget_lane_u16<const IMM5: i32>(v: uint16x4_t) -> u16 {
 }
 #[doc = "Move vector element to general-purpose register"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(1)]
@@ -13751,7 +13751,7 @@ pub fn vget_lane_u32<const IMM5: i32>(v: uint32x2_t) -> u32 {
 }
 #[doc = "Move vector element to general-purpose register"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(1)]
@@ -13770,7 +13770,7 @@ pub fn vget_lane_u8<const IMM5: i32>(v: uint8x8_t) -> u8 {
 }
 #[doc = "Move vector element to general-purpose register"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(1)]
@@ -13789,7 +13789,7 @@ pub fn vgetq_lane_f32<const IMM5: i32>(v: float32x4_t) -> f32 {
 }
 #[doc = "Move vector element to general-purpose register"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_p16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(1)]
@@ -13808,7 +13808,7 @@ pub fn vgetq_lane_p16<const IMM5: i32>(v: poly16x8_t) -> p16 {
 }
 #[doc = "Move vector element to general-purpose register"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_p64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(1)]
@@ -13827,7 +13827,7 @@ pub fn vgetq_lane_p64<const IMM5: i32>(v: poly64x2_t) -> p64 {
 }
 #[doc = "Move vector element to general-purpose register"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(1)]
@@ -13846,7 +13846,7 @@ pub fn vgetq_lane_p8<const IMM5: i32>(v: poly8x16_t) -> p8 {
 }
 #[doc = "Move vector element to general-purpose register"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(1)]
@@ -13865,7 +13865,7 @@ pub fn vgetq_lane_s16<const IMM5: i32>(v: int16x8_t) -> i16 {
 }
 #[doc = "Move vector element to general-purpose register"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(1)]
@@ -13884,7 +13884,7 @@ pub fn vgetq_lane_s32<const IMM5: i32>(v: int32x4_t) -> i32 {
 }
 #[doc = "Move vector element to general-purpose register"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(1)]
@@ -13903,7 +13903,7 @@ pub fn vgetq_lane_s64<const IMM5: i32>(v: int64x2_t) -> i64 {
 }
 #[doc = "Move vector element to general-purpose register"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(1)]
@@ -13922,7 +13922,7 @@ pub fn vgetq_lane_s8<const IMM5: i32>(v: int8x16_t) -> i8 {
 }
 #[doc = "Move vector element to general-purpose register"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(1)]
@@ -13941,7 +13941,7 @@ pub fn vgetq_lane_u16<const IMM5: i32>(v: uint16x8_t) -> u16 {
 }
 #[doc = "Move vector element to general-purpose register"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(1)]
@@ -13960,7 +13960,7 @@ pub fn vgetq_lane_u32<const IMM5: i32>(v: uint32x4_t) -> u32 {
 }
 #[doc = "Move vector element to general-purpose register"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(1)]
@@ -13979,7 +13979,7 @@ pub fn vgetq_lane_u64<const IMM5: i32>(v: uint64x2_t) -> u64 {
 }
 #[doc = "Move vector element to general-purpose register"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(1)]
@@ -13998,7 +13998,7 @@ pub fn vgetq_lane_u8<const IMM5: i32>(v: uint8x16_t) -> u8 {
 }
 #[doc = "Move vector element to general-purpose register"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_p64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(1)]
@@ -14017,7 +14017,7 @@ pub fn vget_lane_p64<const IMM5: i32>(v: poly64x1_t) -> p64 {
 }
 #[doc = "Move vector element to general-purpose register"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(1)]
@@ -14036,7 +14036,7 @@ pub fn vget_lane_s64<const IMM5: i32>(v: int64x1_t) -> i64 {
 }
 #[doc = "Move vector element to general-purpose register"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(1)]
@@ -14055,7 +14055,7 @@ pub fn vget_lane_u64<const IMM5: i32>(v: uint64x1_t) -> u64 {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(test, assert_instr(nop))]
@@ -14072,7 +14072,7 @@ pub fn vget_low_f32(a: float32x4_t) -> float32x2_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_p16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(test, assert_instr(nop))]
@@ -14089,7 +14089,7 @@ pub fn vget_low_p16(a: poly16x8_t) -> poly16x4_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(test, assert_instr(nop))]
@@ -14106,7 +14106,7 @@ pub fn vget_low_p8(a: poly8x16_t) -> poly8x8_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(test, assert_instr(nop))]
@@ -14123,7 +14123,7 @@ pub fn vget_low_s16(a: int16x8_t) -> int16x4_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(test, assert_instr(nop))]
@@ -14140,7 +14140,7 @@ pub fn vget_low_s32(a: int32x4_t) -> int32x2_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(test, assert_instr(nop))]
@@ -14157,7 +14157,7 @@ pub fn vget_low_s8(a: int8x16_t) -> int8x8_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(test, assert_instr(nop))]
@@ -14174,7 +14174,7 @@ pub fn vget_low_u16(a: uint16x8_t) -> uint16x4_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(test, assert_instr(nop))]
@@ -14191,7 +14191,7 @@ pub fn vget_low_u32(a: uint32x4_t) -> uint32x2_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(test, assert_instr(nop))]
@@ -14208,7 +14208,7 @@ pub fn vget_low_u8(a: uint8x16_t) -> uint8x8_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(test, assert_instr(nop))]
@@ -14225,7 +14225,7 @@ pub fn vget_low_s64(a: int64x2_t) -> int64x1_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(test, assert_instr(nop))]
@@ -14242,7 +14242,7 @@ pub fn vget_low_u64(a: uint64x2_t) -> uint64x1_t {
 }
 #[doc = "Halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhadd_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.s8"))]
@@ -14271,7 +14271,7 @@ pub fn vhadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhaddq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.s8"))]
@@ -14300,7 +14300,7 @@ pub fn vhaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhadd_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.s16"))]
@@ -14329,7 +14329,7 @@ pub fn vhadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhaddq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.s16"))]
@@ -14358,7 +14358,7 @@ pub fn vhaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhadd_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.s32"))]
@@ -14387,7 +14387,7 @@ pub fn vhadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhaddq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.s32"))]
@@ -14416,7 +14416,7 @@ pub fn vhaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhadd_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.u8"))]
@@ -14445,7 +14445,7 @@ pub fn vhadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhaddq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.u8"))]
@@ -14474,7 +14474,7 @@ pub fn vhaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhadd_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.u16"))]
@@ -14503,7 +14503,7 @@ pub fn vhadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhaddq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.u16"))]
@@ -14532,7 +14532,7 @@ pub fn vhaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhadd_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.u32"))]
@@ -14561,7 +14561,7 @@ pub fn vhadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhaddq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.u32"))]
@@ -14590,7 +14590,7 @@ pub fn vhaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Signed halving subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsub_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.s16"))]
@@ -14619,7 +14619,7 @@ pub fn vhsub_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Signed halving subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsubq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.s16"))]
@@ -14648,7 +14648,7 @@ pub fn vhsubq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Signed halving subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsub_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.s32"))]
@@ -14677,7 +14677,7 @@ pub fn vhsub_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Signed halving subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsubq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.s32"))]
@@ -14706,7 +14706,7 @@ pub fn vhsubq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Signed halving subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsub_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.s8"))]
@@ -14735,7 +14735,7 @@ pub fn vhsub_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Signed halving subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsubq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.s8"))]
@@ -14764,7 +14764,7 @@ pub fn vhsubq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Signed halving subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsub_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.u8"))]
@@ -14793,7 +14793,7 @@ pub fn vhsub_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Signed halving subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsubq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.u8"))]
@@ -14822,7 +14822,7 @@ pub fn vhsubq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Signed halving subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsub_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.u16"))]
@@ -14851,7 +14851,7 @@ pub fn vhsub_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Signed halving subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsubq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.u16"))]
@@ -14880,7 +14880,7 @@ pub fn vhsubq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Signed halving subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsub_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.u32"))]
@@ -14909,7 +14909,7 @@ pub fn vhsub_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Signed halving subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsubq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.u32"))]
@@ -14940,7 +14940,7 @@ pub fn vhsubq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -14959,7 +14959,7 @@ pub unsafe fn vld1_dup_f16(ptr: *const f16) -> float16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -14978,7 +14978,7 @@ pub unsafe fn vld1q_dup_f16(ptr: *const f16) -> float16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32"))]
@@ -15001,7 +15001,7 @@ pub unsafe fn vld1_dup_f32(ptr: *const f32) -> float32x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
@@ -15024,7 +15024,7 @@ pub unsafe fn vld1_dup_p16(ptr: *const p16) -> poly16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))]
@@ -15047,7 +15047,7 @@ pub unsafe fn vld1_dup_p8(ptr: *const p8) -> poly8x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
@@ -15070,7 +15070,7 @@ pub unsafe fn vld1_dup_s16(ptr: *const i16) -> int16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32"))]
@@ -15093,7 +15093,7 @@ pub unsafe fn vld1_dup_s32(ptr: *const i32) -> int32x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))]
@@ -15116,7 +15116,7 @@ pub unsafe fn vld1_dup_s8(ptr: *const i8) -> int8x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
@@ -15139,7 +15139,7 @@ pub unsafe fn vld1_dup_u16(ptr: *const u16) -> uint16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32"))]
@@ -15162,7 +15162,7 @@ pub unsafe fn vld1_dup_u32(ptr: *const u32) -> uint32x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))]
@@ -15185,7 +15185,7 @@ pub unsafe fn vld1_dup_u8(ptr: *const u8) -> uint8x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32"))]
@@ -15208,7 +15208,7 @@ pub unsafe fn vld1q_dup_f32(ptr: *const f32) -> float32x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
@@ -15231,7 +15231,7 @@ pub unsafe fn vld1q_dup_p16(ptr: *const p16) -> poly16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))]
@@ -15254,7 +15254,7 @@ pub unsafe fn vld1q_dup_p8(ptr: *const p8) -> poly8x16_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
@@ -15277,7 +15277,7 @@ pub unsafe fn vld1q_dup_s16(ptr: *const i16) -> int16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32"))]
@@ -15300,7 +15300,7 @@ pub unsafe fn vld1q_dup_s32(ptr: *const i32) -> int32x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vldr"))]
@@ -15323,7 +15323,7 @@ pub unsafe fn vld1q_dup_s64(ptr: *const i64) -> int64x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))]
@@ -15346,7 +15346,7 @@ pub unsafe fn vld1q_dup_s8(ptr: *const i8) -> int8x16_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.16"))]
@@ -15369,7 +15369,7 @@ pub unsafe fn vld1q_dup_u16(ptr: *const u16) -> uint16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.32"))]
@@ -15392,7 +15392,7 @@ pub unsafe fn vld1q_dup_u32(ptr: *const u32) -> uint32x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vldr"))]
@@ -15415,7 +15415,7 @@ pub unsafe fn vld1q_dup_u64(ptr: *const u64) -> uint64x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vld1.8"))]
@@ -15438,7 +15438,7 @@ pub unsafe fn vld1q_dup_u8(ptr: *const u8) -> uint8x16_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))]
@@ -15470,7 +15470,7 @@ pub unsafe fn vld1_dup_p64(ptr: *const p64) -> poly64x1_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))]
@@ -15502,7 +15502,7 @@ pub unsafe fn vld1_dup_s64(ptr: *const i64) -> int64x1_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))]
@@ -15534,7 +15534,7 @@ pub unsafe fn vld1_dup_u64(ptr: *const u64) -> uint64x1_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -15552,7 +15552,7 @@ pub unsafe fn vld1_f16(ptr: *const f16) -> float16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -15571,7 +15571,7 @@ pub unsafe fn vld1_f16(ptr: *const f16) -> float16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -15589,7 +15589,7 @@ pub unsafe fn vld1q_f16(ptr: *const f16) -> float16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -15608,7 +15608,7 @@ pub unsafe fn vld1q_f16(ptr: *const f16) -> float16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f16_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -15634,7 +15634,7 @@ pub unsafe fn vld1_f16_x2(a: *const f16) -> float16x4x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f16_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -15660,7 +15660,7 @@ pub unsafe fn vld1_f16_x3(a: *const f16) -> float16x4x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f16_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -15686,7 +15686,7 @@ pub unsafe fn vld1_f16_x4(a: *const f16) -> float16x4x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f16_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -15712,7 +15712,7 @@ pub unsafe fn vld1q_f16_x2(a: *const f16) -> float16x8x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f16_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -15738,7 +15738,7 @@ pub unsafe fn vld1q_f16_x3(a: *const f16) -> float16x8x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f16_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -15764,7 +15764,7 @@ pub unsafe fn vld1q_f16_x4(a: *const f16) -> float16x8x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -15777,7 +15777,7 @@ pub unsafe fn vld1_f32(ptr: *const f32) -> float32x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -15790,7 +15790,7 @@ pub unsafe fn vld1q_f32(ptr: *const f32) -> float32x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -15803,7 +15803,7 @@ pub unsafe fn vld1_u8(ptr: *const u8) -> uint8x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -15816,7 +15816,7 @@ pub unsafe fn vld1q_u8(ptr: *const u8) -> uint8x16_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -15829,7 +15829,7 @@ pub unsafe fn vld1_u16(ptr: *const u16) -> uint16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -15842,7 +15842,7 @@ pub unsafe fn vld1q_u16(ptr: *const u16) -> uint16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -15855,7 +15855,7 @@ pub unsafe fn vld1_u32(ptr: *const u32) -> uint32x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -15868,7 +15868,7 @@ pub unsafe fn vld1q_u32(ptr: *const u32) -> uint32x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -15881,7 +15881,7 @@ pub unsafe fn vld1_u64(ptr: *const u64) -> uint64x1_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -15894,7 +15894,7 @@ pub unsafe fn vld1q_u64(ptr: *const u64) -> uint64x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -15907,7 +15907,7 @@ pub unsafe fn vld1_p8(ptr: *const p8) -> poly8x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -15920,7 +15920,7 @@ pub unsafe fn vld1q_p8(ptr: *const p8) -> poly8x16_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -15933,7 +15933,7 @@ pub unsafe fn vld1_p16(ptr: *const p16) -> poly16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -15946,7 +15946,7 @@ pub unsafe fn vld1q_p16(ptr: *const p16) -> poly16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,aes")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -15959,7 +15959,7 @@ pub unsafe fn vld1q_p64(ptr: *const p64) -> poly64x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f32_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -15990,7 +15990,7 @@ pub unsafe fn vld1_f32_x2(a: *const f32) -> float32x2x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f32_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -16021,7 +16021,7 @@ pub unsafe fn vld1_f32_x3(a: *const f32) -> float32x2x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f32_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -16052,7 +16052,7 @@ pub unsafe fn vld1_f32_x4(a: *const f32) -> float32x2x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f32_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -16083,7 +16083,7 @@ pub unsafe fn vld1q_f32_x2(a: *const f32) -> float32x4x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f32_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -16114,7 +16114,7 @@ pub unsafe fn vld1q_f32_x3(a: *const f32) -> float32x4x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f32_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -16145,7 +16145,7 @@ pub unsafe fn vld1q_f32_x4(a: *const f32) -> float32x4x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1, LANE = 0))]
@@ -16165,7 +16165,7 @@ pub unsafe fn vld1_lane_f16<const LANE: i32>(ptr: *const f16, src: float16x4_t)
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1, LANE = 0))]
@@ -16185,7 +16185,7 @@ pub unsafe fn vld1q_lane_f16<const LANE: i32>(ptr: *const f16, src: float16x8_t)
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(2)]
@@ -16210,7 +16210,7 @@ pub unsafe fn vld1_lane_f32<const LANE: i32>(ptr: *const f32, src: float32x2_t)
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(2)]
@@ -16235,7 +16235,7 @@ pub unsafe fn vld1_lane_p16<const LANE: i32>(ptr: *const p16, src: poly16x4_t) -
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(2)]
@@ -16260,7 +16260,7 @@ pub unsafe fn vld1_lane_p8<const LANE: i32>(ptr: *const p8, src: poly8x8_t) -> p
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(2)]
@@ -16285,7 +16285,7 @@ pub unsafe fn vld1_lane_s16<const LANE: i32>(ptr: *const i16, src: int16x4_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(2)]
@@ -16310,7 +16310,7 @@ pub unsafe fn vld1_lane_s32<const LANE: i32>(ptr: *const i32, src: int32x2_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(2)]
@@ -16335,7 +16335,7 @@ pub unsafe fn vld1_lane_s64<const LANE: i32>(ptr: *const i64, src: int64x1_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(2)]
@@ -16360,7 +16360,7 @@ pub unsafe fn vld1_lane_s8<const LANE: i32>(ptr: *const i8, src: int8x8_t) -> in
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(2)]
@@ -16385,7 +16385,7 @@ pub unsafe fn vld1_lane_u16<const LANE: i32>(ptr: *const u16, src: uint16x4_t) -
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(2)]
@@ -16410,7 +16410,7 @@ pub unsafe fn vld1_lane_u32<const LANE: i32>(ptr: *const u32, src: uint32x2_t) -
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(2)]
@@ -16435,7 +16435,7 @@ pub unsafe fn vld1_lane_u64<const LANE: i32>(ptr: *const u64, src: uint64x1_t) -
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(2)]
@@ -16460,7 +16460,7 @@ pub unsafe fn vld1_lane_u8<const LANE: i32>(ptr: *const u8, src: uint8x8_t) -> u
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(2)]
@@ -16485,7 +16485,7 @@ pub unsafe fn vld1q_lane_f32<const LANE: i32>(ptr: *const f32, src: float32x4_t)
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(2)]
@@ -16510,7 +16510,7 @@ pub unsafe fn vld1q_lane_p16<const LANE: i32>(ptr: *const p16, src: poly16x8_t)
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(2)]
@@ -16535,7 +16535,7 @@ pub unsafe fn vld1q_lane_p8<const LANE: i32>(ptr: *const p8, src: poly8x16_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(2)]
@@ -16560,7 +16560,7 @@ pub unsafe fn vld1q_lane_s16<const LANE: i32>(ptr: *const i16, src: int16x8_t) -
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(2)]
@@ -16585,7 +16585,7 @@ pub unsafe fn vld1q_lane_s32<const LANE: i32>(ptr: *const i32, src: int32x4_t) -
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(2)]
@@ -16610,7 +16610,7 @@ pub unsafe fn vld1q_lane_s64<const LANE: i32>(ptr: *const i64, src: int64x2_t) -
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(2)]
@@ -16635,7 +16635,7 @@ pub unsafe fn vld1q_lane_s8<const LANE: i32>(ptr: *const i8, src: int8x16_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(2)]
@@ -16660,7 +16660,7 @@ pub unsafe fn vld1q_lane_u16<const LANE: i32>(ptr: *const u16, src: uint16x8_t)
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(2)]
@@ -16685,7 +16685,7 @@ pub unsafe fn vld1q_lane_u32<const LANE: i32>(ptr: *const u32, src: uint32x4_t)
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(2)]
@@ -16710,7 +16710,7 @@ pub unsafe fn vld1q_lane_u64<const LANE: i32>(ptr: *const u64, src: uint64x2_t)
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(2)]
@@ -16735,7 +16735,7 @@ pub unsafe fn vld1q_lane_u8<const LANE: i32>(ptr: *const u8, src: uint8x16_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(2)]
@@ -16760,7 +16760,7 @@ pub unsafe fn vld1_lane_p64<const LANE: i32>(ptr: *const p64, src: poly64x1_t) -
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[rustc_legacy_const_generics(2)]
@@ -16785,7 +16785,7 @@ pub unsafe fn vld1q_lane_p64<const LANE: i32>(ptr: *const p64, src: poly64x2_t)
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,aes")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -16803,7 +16803,7 @@ pub unsafe fn vld1_p64(ptr: *const p64) -> poly64x1_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p64_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -16826,7 +16826,7 @@ pub unsafe fn vld1_p64_x2(a: *const p64) -> poly64x1x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p64_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -16849,7 +16849,7 @@ pub unsafe fn vld1_p64_x3(a: *const p64) -> poly64x1x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p64_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -16872,7 +16872,7 @@ pub unsafe fn vld1_p64_x4(a: *const p64) -> poly64x1x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -16896,7 +16896,7 @@ pub unsafe fn vld1q_p64_x2(a: *const p64) -> poly64x2x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -16923,7 +16923,7 @@ pub unsafe fn vld1q_p64_x2(a: *const p64) -> poly64x2x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -16947,7 +16947,7 @@ pub unsafe fn vld1q_p64_x3(a: *const p64) -> poly64x2x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -16975,7 +16975,7 @@ pub unsafe fn vld1q_p64_x3(a: *const p64) -> poly64x2x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -16999,7 +16999,7 @@ pub unsafe fn vld1q_p64_x4(a: *const p64) -> poly64x2x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -17028,7 +17028,7 @@ pub unsafe fn vld1q_p64_x4(a: *const p64) -> poly64x2x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -17041,7 +17041,7 @@ pub unsafe fn vld1_s8(ptr: *const i8) -> int8x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -17054,7 +17054,7 @@ pub unsafe fn vld1q_s8(ptr: *const i8) -> int8x16_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -17067,7 +17067,7 @@ pub unsafe fn vld1_s16(ptr: *const i16) -> int16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -17080,7 +17080,7 @@ pub unsafe fn vld1q_s16(ptr: *const i16) -> int16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -17093,7 +17093,7 @@ pub unsafe fn vld1_s32(ptr: *const i32) -> int32x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -17106,7 +17106,7 @@ pub unsafe fn vld1q_s32(ptr: *const i32) -> int32x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -17119,7 +17119,7 @@ pub unsafe fn vld1_s64(ptr: *const i64) -> int64x1_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -17132,7 +17132,7 @@ pub unsafe fn vld1q_s64(ptr: *const i64) -> int64x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s8_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -17163,7 +17163,7 @@ pub unsafe fn vld1_s8_x2(a: *const i8) -> int8x8x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s8_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -17194,7 +17194,7 @@ pub unsafe fn vld1_s8_x3(a: *const i8) -> int8x8x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s8_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -17225,7 +17225,7 @@ pub unsafe fn vld1_s8_x4(a: *const i8) -> int8x8x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s8_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -17256,7 +17256,7 @@ pub unsafe fn vld1q_s8_x2(a: *const i8) -> int8x16x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s8_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -17287,7 +17287,7 @@ pub unsafe fn vld1q_s8_x3(a: *const i8) -> int8x16x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s8_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -17318,7 +17318,7 @@ pub unsafe fn vld1q_s8_x4(a: *const i8) -> int8x16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s16_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -17349,7 +17349,7 @@ pub unsafe fn vld1_s16_x2(a: *const i16) -> int16x4x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s16_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -17380,7 +17380,7 @@ pub unsafe fn vld1_s16_x3(a: *const i16) -> int16x4x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s16_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -17411,7 +17411,7 @@ pub unsafe fn vld1_s16_x4(a: *const i16) -> int16x4x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s16_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -17442,7 +17442,7 @@ pub unsafe fn vld1q_s16_x2(a: *const i16) -> int16x8x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s16_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -17473,7 +17473,7 @@ pub unsafe fn vld1q_s16_x3(a: *const i16) -> int16x8x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s16_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -17504,7 +17504,7 @@ pub unsafe fn vld1q_s16_x4(a: *const i16) -> int16x8x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s32_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -17535,7 +17535,7 @@ pub unsafe fn vld1_s32_x2(a: *const i32) -> int32x2x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s32_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -17566,7 +17566,7 @@ pub unsafe fn vld1_s32_x3(a: *const i32) -> int32x2x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s32_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -17597,7 +17597,7 @@ pub unsafe fn vld1_s32_x4(a: *const i32) -> int32x2x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s32_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -17628,7 +17628,7 @@ pub unsafe fn vld1q_s32_x2(a: *const i32) -> int32x4x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s32_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -17659,7 +17659,7 @@ pub unsafe fn vld1q_s32_x3(a: *const i32) -> int32x4x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s32_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -17690,7 +17690,7 @@ pub unsafe fn vld1q_s32_x4(a: *const i32) -> int32x4x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s64_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -17721,7 +17721,7 @@ pub unsafe fn vld1_s64_x2(a: *const i64) -> int64x1x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s64_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -17752,7 +17752,7 @@ pub unsafe fn vld1_s64_x3(a: *const i64) -> int64x1x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s64_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -17783,7 +17783,7 @@ pub unsafe fn vld1_s64_x4(a: *const i64) -> int64x1x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s64_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -17814,7 +17814,7 @@ pub unsafe fn vld1q_s64_x2(a: *const i64) -> int64x2x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s64_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -17845,7 +17845,7 @@ pub unsafe fn vld1q_s64_x3(a: *const i64) -> int64x2x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s64_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -17876,7 +17876,7 @@ pub unsafe fn vld1q_s64_x4(a: *const i64) -> int64x2x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -17900,7 +17900,7 @@ pub unsafe fn vld1_u8_x2(a: *const u8) -> uint8x8x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -17927,7 +17927,7 @@ pub unsafe fn vld1_u8_x2(a: *const u8) -> uint8x8x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -17951,7 +17951,7 @@ pub unsafe fn vld1_u8_x3(a: *const u8) -> uint8x8x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -17979,7 +17979,7 @@ pub unsafe fn vld1_u8_x3(a: *const u8) -> uint8x8x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -18003,7 +18003,7 @@ pub unsafe fn vld1_u8_x4(a: *const u8) -> uint8x8x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -18032,7 +18032,7 @@ pub unsafe fn vld1_u8_x4(a: *const u8) -> uint8x8x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -18056,7 +18056,7 @@ pub unsafe fn vld1q_u8_x2(a: *const u8) -> uint8x16x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -18095,7 +18095,7 @@ pub unsafe fn vld1q_u8_x2(a: *const u8) -> uint8x16x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -18119,7 +18119,7 @@ pub unsafe fn vld1q_u8_x3(a: *const u8) -> uint8x16x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -18165,7 +18165,7 @@ pub unsafe fn vld1q_u8_x3(a: *const u8) -> uint8x16x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -18189,7 +18189,7 @@ pub unsafe fn vld1q_u8_x4(a: *const u8) -> uint8x16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -18242,7 +18242,7 @@ pub unsafe fn vld1q_u8_x4(a: *const u8) -> uint8x16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -18266,7 +18266,7 @@ pub unsafe fn vld1_u16_x2(a: *const u16) -> uint16x4x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -18293,7 +18293,7 @@ pub unsafe fn vld1_u16_x2(a: *const u16) -> uint16x4x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -18317,7 +18317,7 @@ pub unsafe fn vld1_u16_x3(a: *const u16) -> uint16x4x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -18345,7 +18345,7 @@ pub unsafe fn vld1_u16_x3(a: *const u16) -> uint16x4x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -18369,7 +18369,7 @@ pub unsafe fn vld1_u16_x4(a: *const u16) -> uint16x4x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -18398,7 +18398,7 @@ pub unsafe fn vld1_u16_x4(a: *const u16) -> uint16x4x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -18422,7 +18422,7 @@ pub unsafe fn vld1q_u16_x2(a: *const u16) -> uint16x8x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -18449,7 +18449,7 @@ pub unsafe fn vld1q_u16_x2(a: *const u16) -> uint16x8x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -18473,7 +18473,7 @@ pub unsafe fn vld1q_u16_x3(a: *const u16) -> uint16x8x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -18501,7 +18501,7 @@ pub unsafe fn vld1q_u16_x3(a: *const u16) -> uint16x8x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -18525,7 +18525,7 @@ pub unsafe fn vld1q_u16_x4(a: *const u16) -> uint16x8x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -18554,7 +18554,7 @@ pub unsafe fn vld1q_u16_x4(a: *const u16) -> uint16x8x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -18578,7 +18578,7 @@ pub unsafe fn vld1_u32_x2(a: *const u32) -> uint32x2x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -18605,7 +18605,7 @@ pub unsafe fn vld1_u32_x2(a: *const u32) -> uint32x2x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -18629,7 +18629,7 @@ pub unsafe fn vld1_u32_x3(a: *const u32) -> uint32x2x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -18657,7 +18657,7 @@ pub unsafe fn vld1_u32_x3(a: *const u32) -> uint32x2x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -18681,7 +18681,7 @@ pub unsafe fn vld1_u32_x4(a: *const u32) -> uint32x2x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -18710,7 +18710,7 @@ pub unsafe fn vld1_u32_x4(a: *const u32) -> uint32x2x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -18734,7 +18734,7 @@ pub unsafe fn vld1q_u32_x2(a: *const u32) -> uint32x4x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -18761,7 +18761,7 @@ pub unsafe fn vld1q_u32_x2(a: *const u32) -> uint32x4x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -18785,7 +18785,7 @@ pub unsafe fn vld1q_u32_x3(a: *const u32) -> uint32x4x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -18813,7 +18813,7 @@ pub unsafe fn vld1q_u32_x3(a: *const u32) -> uint32x4x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -18837,7 +18837,7 @@ pub unsafe fn vld1q_u32_x4(a: *const u32) -> uint32x4x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -18866,7 +18866,7 @@ pub unsafe fn vld1q_u32_x4(a: *const u32) -> uint32x4x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u64_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -18889,7 +18889,7 @@ pub unsafe fn vld1_u64_x2(a: *const u64) -> uint64x1x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u64_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -18912,7 +18912,7 @@ pub unsafe fn vld1_u64_x3(a: *const u64) -> uint64x1x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u64_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))]
@@ -18935,7 +18935,7 @@ pub unsafe fn vld1_u64_x4(a: *const u64) -> uint64x1x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -18959,7 +18959,7 @@ pub unsafe fn vld1q_u64_x2(a: *const u64) -> uint64x2x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -18986,7 +18986,7 @@ pub unsafe fn vld1q_u64_x2(a: *const u64) -> uint64x2x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -19010,7 +19010,7 @@ pub unsafe fn vld1q_u64_x3(a: *const u64) -> uint64x2x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -19038,7 +19038,7 @@ pub unsafe fn vld1q_u64_x3(a: *const u64) -> uint64x2x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -19062,7 +19062,7 @@ pub unsafe fn vld1q_u64_x4(a: *const u64) -> uint64x2x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -19091,7 +19091,7 @@ pub unsafe fn vld1q_u64_x4(a: *const u64) -> uint64x2x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -19115,7 +19115,7 @@ pub unsafe fn vld1_p8_x2(a: *const p8) -> poly8x8x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -19142,7 +19142,7 @@ pub unsafe fn vld1_p8_x2(a: *const p8) -> poly8x8x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -19166,7 +19166,7 @@ pub unsafe fn vld1_p8_x3(a: *const p8) -> poly8x8x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -19194,7 +19194,7 @@ pub unsafe fn vld1_p8_x3(a: *const p8) -> poly8x8x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -19218,7 +19218,7 @@ pub unsafe fn vld1_p8_x4(a: *const p8) -> poly8x8x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -19247,7 +19247,7 @@ pub unsafe fn vld1_p8_x4(a: *const p8) -> poly8x8x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -19271,7 +19271,7 @@ pub unsafe fn vld1q_p8_x2(a: *const p8) -> poly8x16x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -19310,7 +19310,7 @@ pub unsafe fn vld1q_p8_x2(a: *const p8) -> poly8x16x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -19334,7 +19334,7 @@ pub unsafe fn vld1q_p8_x3(a: *const p8) -> poly8x16x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -19380,7 +19380,7 @@ pub unsafe fn vld1q_p8_x3(a: *const p8) -> poly8x16x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -19404,7 +19404,7 @@ pub unsafe fn vld1q_p8_x4(a: *const p8) -> poly8x16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -19457,7 +19457,7 @@ pub unsafe fn vld1q_p8_x4(a: *const p8) -> poly8x16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -19481,7 +19481,7 @@ pub unsafe fn vld1_p16_x2(a: *const p16) -> poly16x4x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -19508,7 +19508,7 @@ pub unsafe fn vld1_p16_x2(a: *const p16) -> poly16x4x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -19532,7 +19532,7 @@ pub unsafe fn vld1_p16_x3(a: *const p16) -> poly16x4x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -19560,7 +19560,7 @@ pub unsafe fn vld1_p16_x3(a: *const p16) -> poly16x4x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -19584,7 +19584,7 @@ pub unsafe fn vld1_p16_x4(a: *const p16) -> poly16x4x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -19613,7 +19613,7 @@ pub unsafe fn vld1_p16_x4(a: *const p16) -> poly16x4x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -19637,7 +19637,7 @@ pub unsafe fn vld1q_p16_x2(a: *const p16) -> poly16x8x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -19664,7 +19664,7 @@ pub unsafe fn vld1q_p16_x2(a: *const p16) -> poly16x8x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -19688,7 +19688,7 @@ pub unsafe fn vld1q_p16_x3(a: *const p16) -> poly16x8x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -19716,7 +19716,7 @@ pub unsafe fn vld1q_p16_x3(a: *const p16) -> poly16x8x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -19740,7 +19740,7 @@ pub unsafe fn vld1q_p16_x4(a: *const p16) -> poly16x8x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -19765,7 +19765,7 @@ pub unsafe fn vld1q_p16_x4(a: *const p16) -> poly16x8x4_t {
     ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [7, 6, 5, 4, 3, 2, 1, 0]) };
     ret_val
 }
-#[inline]
+#[inline(always)]
 #[rustc_legacy_const_generics(1)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -19778,7 +19778,7 @@ unsafe fn vld1_v1i64<const ALIGN: i32>(a: *const i8) -> int64x1_t {
     }
     _vld1_v1i64(a, ALIGN)
 }
-#[inline]
+#[inline(always)]
 #[rustc_legacy_const_generics(1)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -19791,7 +19791,7 @@ unsafe fn vld1_v2f32<const ALIGN: i32>(a: *const i8) -> float32x2_t {
     }
     _vld1_v2f32(a, ALIGN)
 }
-#[inline]
+#[inline(always)]
 #[rustc_legacy_const_generics(1)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -19804,7 +19804,7 @@ unsafe fn vld1_v2i32<const ALIGN: i32>(a: *const i8) -> int32x2_t {
     }
     _vld1_v2i32(a, ALIGN)
 }
-#[inline]
+#[inline(always)]
 #[rustc_legacy_const_generics(1)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -19817,7 +19817,7 @@ unsafe fn vld1_v4i16<const ALIGN: i32>(a: *const i8) -> int16x4_t {
     }
     _vld1_v4i16(a, ALIGN)
 }
-#[inline]
+#[inline(always)]
 #[rustc_legacy_const_generics(1)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -19830,7 +19830,7 @@ unsafe fn vld1_v8i8<const ALIGN: i32>(a: *const i8) -> int8x8_t {
     }
     _vld1_v8i8(a, ALIGN)
 }
-#[inline]
+#[inline(always)]
 #[rustc_legacy_const_generics(1)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -19843,7 +19843,7 @@ unsafe fn vld1q_v16i8<const ALIGN: i32>(a: *const i8) -> int8x16_t {
     }
     _vld1q_v16i8(a, ALIGN)
 }
-#[inline]
+#[inline(always)]
 #[rustc_legacy_const_generics(1)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -19856,7 +19856,7 @@ unsafe fn vld1q_v2i64<const ALIGN: i32>(a: *const i8) -> int64x2_t {
     }
     _vld1q_v2i64(a, ALIGN)
 }
-#[inline]
+#[inline(always)]
 #[rustc_legacy_const_generics(1)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -19869,7 +19869,7 @@ unsafe fn vld1q_v4f32<const ALIGN: i32>(a: *const i8) -> float32x4_t {
     }
     _vld1q_v4f32(a, ALIGN)
 }
-#[inline]
+#[inline(always)]
 #[rustc_legacy_const_generics(1)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -19882,7 +19882,7 @@ unsafe fn vld1q_v4i32<const ALIGN: i32>(a: *const i8) -> int32x4_t {
     }
     _vld1q_v4i32(a, ALIGN)
 }
-#[inline]
+#[inline(always)]
 #[rustc_legacy_const_generics(1)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -19895,7 +19895,7 @@ unsafe fn vld1q_v8i16<const ALIGN: i32>(a: *const i8) -> int16x8_t {
     }
     _vld1q_v8i16(a, ALIGN)
 }
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -19909,7 +19909,7 @@ unsafe fn vld1_v4f16(a: *const i8, b: i32) -> float16x4_t {
     }
     _vld1_v4f16(a, b)
 }
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -19927,7 +19927,7 @@ unsafe fn vld1q_v8f16(a: *const i8, b: i32) -> float16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vldr))]
@@ -19951,7 +19951,7 @@ pub unsafe fn vld1q_dup_p64(ptr: *const p64) -> poly64x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg(target_arch = "arm")]
@@ -19970,7 +19970,7 @@ pub unsafe fn vld2_dup_f16(a: *const f16) -> float16x4x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg(target_arch = "arm")]
@@ -19989,7 +19989,7 @@ pub unsafe fn vld2q_dup_f16(a: *const f16) -> float16x8x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(
@@ -20013,7 +20013,7 @@ pub unsafe fn vld2_dup_f16(a: *const f16) -> float16x4x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(
@@ -20037,7 +20037,7 @@ pub unsafe fn vld2q_dup_f16(a: *const f16) -> float16x8x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -20053,7 +20053,7 @@ pub unsafe fn vld2_dup_f32(a: *const f32) -> float32x2x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -20069,7 +20069,7 @@ pub unsafe fn vld2q_dup_f32(a: *const f32) -> float32x4x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -20085,7 +20085,7 @@ pub unsafe fn vld2_dup_s8(a: *const i8) -> int8x8x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -20101,7 +20101,7 @@ pub unsafe fn vld2q_dup_s8(a: *const i8) -> int8x16x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -20117,7 +20117,7 @@ pub unsafe fn vld2_dup_s16(a: *const i16) -> int16x4x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -20133,7 +20133,7 @@ pub unsafe fn vld2q_dup_s16(a: *const i16) -> int16x8x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -20149,7 +20149,7 @@ pub unsafe fn vld2_dup_s32(a: *const i32) -> int32x2x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -20165,7 +20165,7 @@ pub unsafe fn vld2q_dup_s32(a: *const i32) -> int32x4x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20184,7 +20184,7 @@ pub unsafe fn vld2_dup_f32(a: *const f32) -> float32x2x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20203,7 +20203,7 @@ pub unsafe fn vld2q_dup_f32(a: *const f32) -> float32x4x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20222,7 +20222,7 @@ pub unsafe fn vld2_dup_s8(a: *const i8) -> int8x8x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20241,7 +20241,7 @@ pub unsafe fn vld2q_dup_s8(a: *const i8) -> int8x16x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20260,7 +20260,7 @@ pub unsafe fn vld2_dup_s16(a: *const i16) -> int16x4x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20279,7 +20279,7 @@ pub unsafe fn vld2q_dup_s16(a: *const i16) -> int16x8x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20298,7 +20298,7 @@ pub unsafe fn vld2_dup_s32(a: *const i32) -> int32x2x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20317,7 +20317,7 @@ pub unsafe fn vld2q_dup_s32(a: *const i32) -> int32x4x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -20340,7 +20340,7 @@ pub unsafe fn vld2_dup_p64(a: *const p64) -> poly64x1x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -20356,7 +20356,7 @@ pub unsafe fn vld2_dup_s64(a: *const i64) -> int64x1x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -20375,7 +20375,7 @@ pub unsafe fn vld2_dup_s64(a: *const i64) -> int64x1x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -20398,7 +20398,7 @@ pub unsafe fn vld2_dup_u64(a: *const u64) -> uint64x1x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -20422,7 +20422,7 @@ pub unsafe fn vld2_dup_u8(a: *const u8) -> uint8x8x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -20449,7 +20449,7 @@ pub unsafe fn vld2_dup_u8(a: *const u8) -> uint8x8x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -20473,7 +20473,7 @@ pub unsafe fn vld2q_dup_u8(a: *const u8) -> uint8x16x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -20512,7 +20512,7 @@ pub unsafe fn vld2q_dup_u8(a: *const u8) -> uint8x16x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -20536,7 +20536,7 @@ pub unsafe fn vld2_dup_u16(a: *const u16) -> uint16x4x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -20563,7 +20563,7 @@ pub unsafe fn vld2_dup_u16(a: *const u16) -> uint16x4x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -20587,7 +20587,7 @@ pub unsafe fn vld2q_dup_u16(a: *const u16) -> uint16x8x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -20614,7 +20614,7 @@ pub unsafe fn vld2q_dup_u16(a: *const u16) -> uint16x8x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -20638,7 +20638,7 @@ pub unsafe fn vld2_dup_u32(a: *const u32) -> uint32x2x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -20665,7 +20665,7 @@ pub unsafe fn vld2_dup_u32(a: *const u32) -> uint32x2x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -20689,7 +20689,7 @@ pub unsafe fn vld2q_dup_u32(a: *const u32) -> uint32x4x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -20716,7 +20716,7 @@ pub unsafe fn vld2q_dup_u32(a: *const u32) -> uint32x4x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -20740,7 +20740,7 @@ pub unsafe fn vld2_dup_p8(a: *const p8) -> poly8x8x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -20767,7 +20767,7 @@ pub unsafe fn vld2_dup_p8(a: *const p8) -> poly8x8x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -20791,7 +20791,7 @@ pub unsafe fn vld2q_dup_p8(a: *const p8) -> poly8x16x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -20830,7 +20830,7 @@ pub unsafe fn vld2q_dup_p8(a: *const p8) -> poly8x16x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -20854,7 +20854,7 @@ pub unsafe fn vld2_dup_p16(a: *const p16) -> poly16x4x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -20881,7 +20881,7 @@ pub unsafe fn vld2_dup_p16(a: *const p16) -> poly16x4x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -20905,7 +20905,7 @@ pub unsafe fn vld2q_dup_p16(a: *const p16) -> poly16x8x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -20932,7 +20932,7 @@ pub unsafe fn vld2q_dup_p16(a: *const p16) -> poly16x8x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg(target_arch = "arm")]
@@ -20951,7 +20951,7 @@ pub unsafe fn vld2_f16(a: *const f16) -> float16x4x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg(target_arch = "arm")]
@@ -20970,7 +20970,7 @@ pub unsafe fn vld2q_f16(a: *const f16) -> float16x8x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(
@@ -20994,7 +20994,7 @@ pub unsafe fn vld2_f16(a: *const f16) -> float16x4x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(
@@ -21018,7 +21018,7 @@ pub unsafe fn vld2q_f16(a: *const f16) -> float16x8x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -21034,7 +21034,7 @@ pub unsafe fn vld2_f32(a: *const f32) -> float32x2x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -21050,7 +21050,7 @@ pub unsafe fn vld2q_f32(a: *const f32) -> float32x4x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -21066,7 +21066,7 @@ pub unsafe fn vld2_s8(a: *const i8) -> int8x8x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -21082,7 +21082,7 @@ pub unsafe fn vld2q_s8(a: *const i8) -> int8x16x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -21098,7 +21098,7 @@ pub unsafe fn vld2_s16(a: *const i16) -> int16x4x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -21114,7 +21114,7 @@ pub unsafe fn vld2q_s16(a: *const i16) -> int16x8x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -21130,7 +21130,7 @@ pub unsafe fn vld2_s32(a: *const i32) -> int32x2x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -21146,7 +21146,7 @@ pub unsafe fn vld2q_s32(a: *const i32) -> int32x4x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21165,7 +21165,7 @@ pub unsafe fn vld2_f32(a: *const f32) -> float32x2x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21184,7 +21184,7 @@ pub unsafe fn vld2q_f32(a: *const f32) -> float32x4x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21203,7 +21203,7 @@ pub unsafe fn vld2_s8(a: *const i8) -> int8x8x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21222,7 +21222,7 @@ pub unsafe fn vld2q_s8(a: *const i8) -> int8x16x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21241,7 +21241,7 @@ pub unsafe fn vld2_s16(a: *const i16) -> int16x4x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21260,7 +21260,7 @@ pub unsafe fn vld2q_s16(a: *const i16) -> int16x8x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21279,7 +21279,7 @@ pub unsafe fn vld2_s32(a: *const i32) -> int32x2x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21298,7 +21298,7 @@ pub unsafe fn vld2q_s32(a: *const i32) -> int32x4x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))]
@@ -21324,7 +21324,7 @@ pub unsafe fn vld2_lane_f16<const LANE: i32>(a: *const f16, b: float16x4x2_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))]
@@ -21350,7 +21350,7 @@ pub unsafe fn vld2q_lane_f16<const LANE: i32>(a: *const f16, b: float16x8x2_t) -
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(
@@ -21377,7 +21377,7 @@ pub unsafe fn vld2_lane_f16<const LANE: i32>(a: *const f16, b: float16x4x2_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(
@@ -21408,7 +21408,7 @@ pub unsafe fn vld2q_lane_f16<const LANE: i32>(a: *const f16, b: float16x8x2_t) -
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(ld2, LANE = 0))]
@@ -21429,7 +21429,7 @@ pub unsafe fn vld2_lane_f32<const LANE: i32>(a: *const f32, b: float32x2x2_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(ld2, LANE = 0))]
@@ -21451,7 +21451,7 @@ pub unsafe fn vld2q_lane_f32<const LANE: i32>(a: *const f32, b: float32x4x2_t) -
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(ld2, LANE = 0))]
@@ -21472,7 +21472,7 @@ pub unsafe fn vld2_lane_s8<const LANE: i32>(a: *const i8, b: int8x8x2_t) -> int8
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(ld2, LANE = 0))]
@@ -21493,7 +21493,7 @@ pub unsafe fn vld2_lane_s16<const LANE: i32>(a: *const i16, b: int16x4x2_t) -> i
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(ld2, LANE = 0))]
@@ -21514,7 +21514,7 @@ pub unsafe fn vld2q_lane_s16<const LANE: i32>(a: *const i16, b: int16x8x2_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(ld2, LANE = 0))]
@@ -21535,7 +21535,7 @@ pub unsafe fn vld2_lane_s32<const LANE: i32>(a: *const i32, b: int32x2x2_t) -> i
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(ld2, LANE = 0))]
@@ -21556,7 +21556,7 @@ pub unsafe fn vld2q_lane_s32<const LANE: i32>(a: *const i32, b: int32x4x2_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(test, assert_instr(vld2, LANE = 0))]
@@ -21580,7 +21580,7 @@ pub unsafe fn vld2_lane_f32<const LANE: i32>(a: *const f32, b: float32x2x2_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(test, assert_instr(vld2, LANE = 0))]
@@ -21604,7 +21604,7 @@ pub unsafe fn vld2q_lane_f32<const LANE: i32>(a: *const f32, b: float32x4x2_t) -
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(test, assert_instr(vld2, LANE = 0))]
@@ -21628,7 +21628,7 @@ pub unsafe fn vld2q_lane_s16<const LANE: i32>(a: *const i16, b: int16x8x2_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(test, assert_instr(vld2, LANE = 0))]
@@ -21652,7 +21652,7 @@ pub unsafe fn vld2q_lane_s32<const LANE: i32>(a: *const i32, b: int32x4x2_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(test, assert_instr(vld2, LANE = 0))]
@@ -21671,7 +21671,7 @@ pub unsafe fn vld2_lane_s8<const LANE: i32>(a: *const i8, b: int8x8x2_t) -> int8
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(test, assert_instr(vld2, LANE = 0))]
@@ -21695,7 +21695,7 @@ pub unsafe fn vld2_lane_s16<const LANE: i32>(a: *const i16, b: int16x4x2_t) -> i
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(test, assert_instr(vld2, LANE = 0))]
@@ -21719,7 +21719,7 @@ pub unsafe fn vld2_lane_s32<const LANE: i32>(a: *const i32, b: int32x2x2_t) -> i
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))]
@@ -21744,7 +21744,7 @@ pub unsafe fn vld2_lane_u8<const LANE: i32>(a: *const u8, b: uint8x8x2_t) -> uin
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))]
@@ -21769,7 +21769,7 @@ pub unsafe fn vld2_lane_u16<const LANE: i32>(a: *const u16, b: uint16x4x2_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))]
@@ -21794,7 +21794,7 @@ pub unsafe fn vld2q_lane_u16<const LANE: i32>(a: *const u16, b: uint16x8x2_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))]
@@ -21819,7 +21819,7 @@ pub unsafe fn vld2_lane_u32<const LANE: i32>(a: *const u32, b: uint32x2x2_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))]
@@ -21844,7 +21844,7 @@ pub unsafe fn vld2q_lane_u32<const LANE: i32>(a: *const u32, b: uint32x4x2_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))]
@@ -21869,7 +21869,7 @@ pub unsafe fn vld2_lane_p8<const LANE: i32>(a: *const p8, b: poly8x8x2_t) -> pol
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))]
@@ -21894,7 +21894,7 @@ pub unsafe fn vld2_lane_p16<const LANE: i32>(a: *const p16, b: poly16x4x2_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))]
@@ -21919,7 +21919,7 @@ pub unsafe fn vld2q_lane_p16<const LANE: i32>(a: *const p16, b: poly16x8x2_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -21942,7 +21942,7 @@ pub unsafe fn vld2_p64(a: *const p64) -> poly64x1x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -21958,7 +21958,7 @@ pub unsafe fn vld2_s64(a: *const i64) -> int64x1x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -21977,7 +21977,7 @@ pub unsafe fn vld2_s64(a: *const i64) -> int64x1x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -22000,7 +22000,7 @@ pub unsafe fn vld2_u64(a: *const u64) -> uint64x1x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -22024,7 +22024,7 @@ pub unsafe fn vld2_u8(a: *const u8) -> uint8x8x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -22051,7 +22051,7 @@ pub unsafe fn vld2_u8(a: *const u8) -> uint8x8x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -22075,7 +22075,7 @@ pub unsafe fn vld2q_u8(a: *const u8) -> uint8x16x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -22114,7 +22114,7 @@ pub unsafe fn vld2q_u8(a: *const u8) -> uint8x16x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -22138,7 +22138,7 @@ pub unsafe fn vld2_u16(a: *const u16) -> uint16x4x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -22165,7 +22165,7 @@ pub unsafe fn vld2_u16(a: *const u16) -> uint16x4x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -22189,7 +22189,7 @@ pub unsafe fn vld2q_u16(a: *const u16) -> uint16x8x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -22216,7 +22216,7 @@ pub unsafe fn vld2q_u16(a: *const u16) -> uint16x8x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -22240,7 +22240,7 @@ pub unsafe fn vld2_u32(a: *const u32) -> uint32x2x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -22267,7 +22267,7 @@ pub unsafe fn vld2_u32(a: *const u32) -> uint32x2x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -22291,7 +22291,7 @@ pub unsafe fn vld2q_u32(a: *const u32) -> uint32x4x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -22318,7 +22318,7 @@ pub unsafe fn vld2q_u32(a: *const u32) -> uint32x4x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -22342,7 +22342,7 @@ pub unsafe fn vld2_p8(a: *const p8) -> poly8x8x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -22369,7 +22369,7 @@ pub unsafe fn vld2_p8(a: *const p8) -> poly8x8x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -22393,7 +22393,7 @@ pub unsafe fn vld2q_p8(a: *const p8) -> poly8x16x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -22432,7 +22432,7 @@ pub unsafe fn vld2q_p8(a: *const p8) -> poly8x16x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -22456,7 +22456,7 @@ pub unsafe fn vld2_p16(a: *const p16) -> poly16x4x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -22483,7 +22483,7 @@ pub unsafe fn vld2_p16(a: *const p16) -> poly16x4x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -22507,7 +22507,7 @@ pub unsafe fn vld2q_p16(a: *const p16) -> poly16x8x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -22534,7 +22534,7 @@ pub unsafe fn vld2q_p16(a: *const p16) -> poly16x8x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg(target_arch = "arm")]
@@ -22553,7 +22553,7 @@ pub unsafe fn vld3_dup_f16(a: *const f16) -> float16x4x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg(target_arch = "arm")]
@@ -22572,7 +22572,7 @@ pub unsafe fn vld3q_dup_f16(a: *const f16) -> float16x8x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(
@@ -22596,7 +22596,7 @@ pub unsafe fn vld3_dup_f16(a: *const f16) -> float16x4x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(
@@ -22620,7 +22620,7 @@ pub unsafe fn vld3q_dup_f16(a: *const f16) -> float16x8x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22639,7 +22639,7 @@ pub unsafe fn vld3_dup_f32(a: *const f32) -> float32x2x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22658,7 +22658,7 @@ pub unsafe fn vld3q_dup_f32(a: *const f32) -> float32x4x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22677,7 +22677,7 @@ pub unsafe fn vld3_dup_s8(a: *const i8) -> int8x8x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22696,7 +22696,7 @@ pub unsafe fn vld3q_dup_s8(a: *const i8) -> int8x16x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22715,7 +22715,7 @@ pub unsafe fn vld3_dup_s16(a: *const i16) -> int16x4x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22734,7 +22734,7 @@ pub unsafe fn vld3q_dup_s16(a: *const i16) -> int16x8x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22753,7 +22753,7 @@ pub unsafe fn vld3_dup_s32(a: *const i32) -> int32x2x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22772,7 +22772,7 @@ pub unsafe fn vld3q_dup_s32(a: *const i32) -> int32x4x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -22791,7 +22791,7 @@ pub unsafe fn vld3_dup_s64(a: *const i64) -> int64x1x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -22807,7 +22807,7 @@ pub unsafe fn vld3_dup_f32(a: *const f32) -> float32x2x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -22823,7 +22823,7 @@ pub unsafe fn vld3q_dup_f32(a: *const f32) -> float32x4x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -22839,7 +22839,7 @@ pub unsafe fn vld3_dup_s8(a: *const i8) -> int8x8x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -22855,7 +22855,7 @@ pub unsafe fn vld3q_dup_s8(a: *const i8) -> int8x16x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -22871,7 +22871,7 @@ pub unsafe fn vld3_dup_s16(a: *const i16) -> int16x4x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -22887,7 +22887,7 @@ pub unsafe fn vld3q_dup_s16(a: *const i16) -> int16x8x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -22903,7 +22903,7 @@ pub unsafe fn vld3_dup_s32(a: *const i32) -> int32x2x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -22919,7 +22919,7 @@ pub unsafe fn vld3q_dup_s32(a: *const i32) -> int32x4x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -22942,7 +22942,7 @@ pub unsafe fn vld3_dup_p64(a: *const p64) -> poly64x1x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -22958,7 +22958,7 @@ pub unsafe fn vld3_dup_s64(a: *const i64) -> int64x1x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -22981,7 +22981,7 @@ pub unsafe fn vld3_dup_u64(a: *const u64) -> uint64x1x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -23005,7 +23005,7 @@ pub unsafe fn vld3_dup_u8(a: *const u8) -> uint8x8x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -23033,7 +23033,7 @@ pub unsafe fn vld3_dup_u8(a: *const u8) -> uint8x8x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -23057,7 +23057,7 @@ pub unsafe fn vld3q_dup_u8(a: *const u8) -> uint8x16x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -23103,7 +23103,7 @@ pub unsafe fn vld3q_dup_u8(a: *const u8) -> uint8x16x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -23127,7 +23127,7 @@ pub unsafe fn vld3_dup_u16(a: *const u16) -> uint16x4x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -23155,7 +23155,7 @@ pub unsafe fn vld3_dup_u16(a: *const u16) -> uint16x4x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -23179,7 +23179,7 @@ pub unsafe fn vld3q_dup_u16(a: *const u16) -> uint16x8x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -23207,7 +23207,7 @@ pub unsafe fn vld3q_dup_u16(a: *const u16) -> uint16x8x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -23231,7 +23231,7 @@ pub unsafe fn vld3_dup_u32(a: *const u32) -> uint32x2x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -23259,7 +23259,7 @@ pub unsafe fn vld3_dup_u32(a: *const u32) -> uint32x2x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -23283,7 +23283,7 @@ pub unsafe fn vld3q_dup_u32(a: *const u32) -> uint32x4x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -23311,7 +23311,7 @@ pub unsafe fn vld3q_dup_u32(a: *const u32) -> uint32x4x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -23335,7 +23335,7 @@ pub unsafe fn vld3_dup_p8(a: *const p8) -> poly8x8x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -23363,7 +23363,7 @@ pub unsafe fn vld3_dup_p8(a: *const p8) -> poly8x8x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -23387,7 +23387,7 @@ pub unsafe fn vld3q_dup_p8(a: *const p8) -> poly8x16x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -23433,7 +23433,7 @@ pub unsafe fn vld3q_dup_p8(a: *const p8) -> poly8x16x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -23457,7 +23457,7 @@ pub unsafe fn vld3_dup_p16(a: *const p16) -> poly16x4x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -23485,7 +23485,7 @@ pub unsafe fn vld3_dup_p16(a: *const p16) -> poly16x4x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -23509,7 +23509,7 @@ pub unsafe fn vld3q_dup_p16(a: *const p16) -> poly16x8x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -23537,7 +23537,7 @@ pub unsafe fn vld3q_dup_p16(a: *const p16) -> poly16x8x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg(target_arch = "arm")]
@@ -23556,7 +23556,7 @@ pub unsafe fn vld3_f16(a: *const f16) -> float16x4x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg(target_arch = "arm")]
@@ -23575,7 +23575,7 @@ pub unsafe fn vld3q_f16(a: *const f16) -> float16x8x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(
@@ -23599,7 +23599,7 @@ pub unsafe fn vld3_f16(a: *const f16) -> float16x4x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(
@@ -23623,7 +23623,7 @@ pub unsafe fn vld3q_f16(a: *const f16) -> float16x8x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg(not(target_arch = "arm"))]
@@ -23642,7 +23642,7 @@ pub unsafe fn vld3_f32(a: *const f32) -> float32x2x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg(not(target_arch = "arm"))]
@@ -23661,7 +23661,7 @@ pub unsafe fn vld3q_f32(a: *const f32) -> float32x4x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg(not(target_arch = "arm"))]
@@ -23680,7 +23680,7 @@ pub unsafe fn vld3_s8(a: *const i8) -> int8x8x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg(not(target_arch = "arm"))]
@@ -23699,7 +23699,7 @@ pub unsafe fn vld3q_s8(a: *const i8) -> int8x16x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg(not(target_arch = "arm"))]
@@ -23718,7 +23718,7 @@ pub unsafe fn vld3_s16(a: *const i16) -> int16x4x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg(not(target_arch = "arm"))]
@@ -23737,7 +23737,7 @@ pub unsafe fn vld3q_s16(a: *const i16) -> int16x8x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg(not(target_arch = "arm"))]
@@ -23756,7 +23756,7 @@ pub unsafe fn vld3_s32(a: *const i32) -> int32x2x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg(not(target_arch = "arm"))]
@@ -23775,7 +23775,7 @@ pub unsafe fn vld3q_s32(a: *const i32) -> int32x4x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -23791,7 +23791,7 @@ pub unsafe fn vld3_f32(a: *const f32) -> float32x2x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -23807,7 +23807,7 @@ pub unsafe fn vld3q_f32(a: *const f32) -> float32x4x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -23823,7 +23823,7 @@ pub unsafe fn vld3_s8(a: *const i8) -> int8x8x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -23839,7 +23839,7 @@ pub unsafe fn vld3q_s8(a: *const i8) -> int8x16x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -23855,7 +23855,7 @@ pub unsafe fn vld3_s16(a: *const i16) -> int16x4x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -23871,7 +23871,7 @@ pub unsafe fn vld3q_s16(a: *const i16) -> int16x8x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -23887,7 +23887,7 @@ pub unsafe fn vld3_s32(a: *const i32) -> int32x2x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -23903,7 +23903,7 @@ pub unsafe fn vld3q_s32(a: *const i32) -> int32x4x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))]
@@ -23930,7 +23930,7 @@ pub unsafe fn vld3_lane_f16<const LANE: i32>(a: *const f16, b: float16x4x3_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))]
@@ -23957,7 +23957,7 @@ pub unsafe fn vld3q_lane_f16<const LANE: i32>(a: *const f16, b: float16x8x3_t) -
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(
@@ -23989,7 +23989,7 @@ pub unsafe fn vld3_lane_f16<const LANE: i32>(a: *const f16, b: float16x4x3_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(
@@ -24021,7 +24021,7 @@ pub unsafe fn vld3q_lane_f16<const LANE: i32>(a: *const f16, b: float16x8x3_t) -
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(ld3, LANE = 0))]
@@ -24048,7 +24048,7 @@ pub unsafe fn vld3_lane_f32<const LANE: i32>(a: *const f32, b: float32x2x3_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(ld3, LANE = 0))]
@@ -24075,7 +24075,7 @@ pub unsafe fn vld3q_lane_f32<const LANE: i32>(a: *const f32, b: float32x4x3_t) -
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vld3, LANE = 0))]
@@ -24100,7 +24100,7 @@ pub unsafe fn vld3_lane_f32<const LANE: i32>(a: *const f32, b: float32x2x3_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(ld3, LANE = 0))]
@@ -24127,7 +24127,7 @@ pub unsafe fn vld3_lane_s8<const LANE: i32>(a: *const i8, b: int8x8x3_t) -> int8
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(ld3, LANE = 0))]
@@ -24154,7 +24154,7 @@ pub unsafe fn vld3_lane_s16<const LANE: i32>(a: *const i16, b: int16x4x3_t) -> i
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(ld3, LANE = 0))]
@@ -24181,7 +24181,7 @@ pub unsafe fn vld3q_lane_s16<const LANE: i32>(a: *const i16, b: int16x8x3_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(ld3, LANE = 0))]
@@ -24208,7 +24208,7 @@ pub unsafe fn vld3_lane_s32<const LANE: i32>(a: *const i32, b: int32x2x3_t) -> i
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(ld3, LANE = 0))]
@@ -24235,7 +24235,7 @@ pub unsafe fn vld3q_lane_s32<const LANE: i32>(a: *const i32, b: int32x4x3_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vld3, LANE = 0))]
@@ -24260,7 +24260,7 @@ pub unsafe fn vld3_lane_s8<const LANE: i32>(a: *const i8, b: int8x8x3_t) -> int8
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vld3, LANE = 0))]
@@ -24285,7 +24285,7 @@ pub unsafe fn vld3_lane_s16<const LANE: i32>(a: *const i16, b: int16x4x3_t) -> i
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vld3, LANE = 0))]
@@ -24310,7 +24310,7 @@ pub unsafe fn vld3q_lane_s16<const LANE: i32>(a: *const i16, b: int16x8x3_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vld3, LANE = 0))]
@@ -24335,7 +24335,7 @@ pub unsafe fn vld3_lane_s32<const LANE: i32>(a: *const i32, b: int32x2x3_t) -> i
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vld3, LANE = 0))]
@@ -24360,7 +24360,7 @@ pub unsafe fn vld3q_lane_s32<const LANE: i32>(a: *const i32, b: int32x4x3_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))]
@@ -24385,7 +24385,7 @@ pub unsafe fn vld3_lane_u8<const LANE: i32>(a: *const u8, b: uint8x8x3_t) -> uin
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))]
@@ -24410,7 +24410,7 @@ pub unsafe fn vld3_lane_u16<const LANE: i32>(a: *const u16, b: uint16x4x3_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))]
@@ -24435,7 +24435,7 @@ pub unsafe fn vld3q_lane_u16<const LANE: i32>(a: *const u16, b: uint16x8x3_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))]
@@ -24460,7 +24460,7 @@ pub unsafe fn vld3_lane_u32<const LANE: i32>(a: *const u32, b: uint32x2x3_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))]
@@ -24485,7 +24485,7 @@ pub unsafe fn vld3q_lane_u32<const LANE: i32>(a: *const u32, b: uint32x4x3_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))]
@@ -24510,7 +24510,7 @@ pub unsafe fn vld3_lane_p8<const LANE: i32>(a: *const p8, b: poly8x8x3_t) -> pol
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))]
@@ -24535,7 +24535,7 @@ pub unsafe fn vld3_lane_p16<const LANE: i32>(a: *const p16, b: poly16x4x3_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))]
@@ -24560,7 +24560,7 @@ pub unsafe fn vld3q_lane_p16<const LANE: i32>(a: *const p16, b: poly16x8x3_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -24583,7 +24583,7 @@ pub unsafe fn vld3_p64(a: *const p64) -> poly64x1x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg(not(target_arch = "arm"))]
@@ -24602,7 +24602,7 @@ pub unsafe fn vld3_s64(a: *const i64) -> int64x1x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -24618,7 +24618,7 @@ pub unsafe fn vld3_s64(a: *const i64) -> int64x1x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -24641,7 +24641,7 @@ pub unsafe fn vld3_u64(a: *const u64) -> uint64x1x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -24665,7 +24665,7 @@ pub unsafe fn vld3_u8(a: *const u8) -> uint8x8x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -24693,7 +24693,7 @@ pub unsafe fn vld3_u8(a: *const u8) -> uint8x8x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -24717,7 +24717,7 @@ pub unsafe fn vld3q_u8(a: *const u8) -> uint8x16x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -24763,7 +24763,7 @@ pub unsafe fn vld3q_u8(a: *const u8) -> uint8x16x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -24787,7 +24787,7 @@ pub unsafe fn vld3_u16(a: *const u16) -> uint16x4x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -24815,7 +24815,7 @@ pub unsafe fn vld3_u16(a: *const u16) -> uint16x4x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -24839,7 +24839,7 @@ pub unsafe fn vld3q_u16(a: *const u16) -> uint16x8x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -24867,7 +24867,7 @@ pub unsafe fn vld3q_u16(a: *const u16) -> uint16x8x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -24891,7 +24891,7 @@ pub unsafe fn vld3_u32(a: *const u32) -> uint32x2x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -24919,7 +24919,7 @@ pub unsafe fn vld3_u32(a: *const u32) -> uint32x2x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -24943,7 +24943,7 @@ pub unsafe fn vld3q_u32(a: *const u32) -> uint32x4x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -24971,7 +24971,7 @@ pub unsafe fn vld3q_u32(a: *const u32) -> uint32x4x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -24995,7 +24995,7 @@ pub unsafe fn vld3_p8(a: *const p8) -> poly8x8x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -25023,7 +25023,7 @@ pub unsafe fn vld3_p8(a: *const p8) -> poly8x8x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -25047,7 +25047,7 @@ pub unsafe fn vld3q_p8(a: *const p8) -> poly8x16x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -25093,7 +25093,7 @@ pub unsafe fn vld3q_p8(a: *const p8) -> poly8x16x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -25117,7 +25117,7 @@ pub unsafe fn vld3_p16(a: *const p16) -> poly16x4x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -25145,7 +25145,7 @@ pub unsafe fn vld3_p16(a: *const p16) -> poly16x4x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -25169,7 +25169,7 @@ pub unsafe fn vld3q_p16(a: *const p16) -> poly16x8x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -25197,7 +25197,7 @@ pub unsafe fn vld3q_p16(a: *const p16) -> poly16x8x3_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vld3, LANE = 0))]
@@ -25222,7 +25222,7 @@ pub unsafe fn vld3q_lane_f32<const LANE: i32>(a: *const f32, b: float32x4x3_t) -
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
@@ -25240,7 +25240,7 @@ pub unsafe fn vld4_dup_f16(a: *const f16) -> float16x4x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
@@ -25258,7 +25258,7 @@ pub unsafe fn vld4q_dup_f16(a: *const f16) -> float16x8x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -25281,7 +25281,7 @@ pub unsafe fn vld4_dup_f16(a: *const f16) -> float16x4x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -25304,7 +25304,7 @@ pub unsafe fn vld4q_dup_f16(a: *const f16) -> float16x8x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vld4))]
@@ -25320,7 +25320,7 @@ pub unsafe fn vld4_dup_f32(a: *const f32) -> float32x2x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vld4))]
@@ -25336,7 +25336,7 @@ pub unsafe fn vld4q_dup_f32(a: *const f32) -> float32x4x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vld4))]
@@ -25352,7 +25352,7 @@ pub unsafe fn vld4_dup_s8(a: *const i8) -> int8x8x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vld4))]
@@ -25368,7 +25368,7 @@ pub unsafe fn vld4q_dup_s8(a: *const i8) -> int8x16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vld4))]
@@ -25384,7 +25384,7 @@ pub unsafe fn vld4_dup_s16(a: *const i16) -> int16x4x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vld4))]
@@ -25400,7 +25400,7 @@ pub unsafe fn vld4q_dup_s16(a: *const i16) -> int16x8x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vld4))]
@@ -25416,7 +25416,7 @@ pub unsafe fn vld4_dup_s32(a: *const i32) -> int32x2x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vld4))]
@@ -25432,7 +25432,7 @@ pub unsafe fn vld4q_dup_s32(a: *const i32) -> int32x4x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(ld4r))]
@@ -25451,7 +25451,7 @@ pub unsafe fn vld4_dup_f32(a: *const f32) -> float32x2x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(ld4r))]
@@ -25470,7 +25470,7 @@ pub unsafe fn vld4q_dup_f32(a: *const f32) -> float32x4x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(ld4r))]
@@ -25489,7 +25489,7 @@ pub unsafe fn vld4_dup_s8(a: *const i8) -> int8x8x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(ld4r))]
@@ -25508,7 +25508,7 @@ pub unsafe fn vld4q_dup_s8(a: *const i8) -> int8x16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(ld4r))]
@@ -25527,7 +25527,7 @@ pub unsafe fn vld4_dup_s16(a: *const i16) -> int16x4x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(ld4r))]
@@ -25546,7 +25546,7 @@ pub unsafe fn vld4q_dup_s16(a: *const i16) -> int16x8x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(ld4r))]
@@ -25565,7 +25565,7 @@ pub unsafe fn vld4_dup_s32(a: *const i32) -> int32x2x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(ld4r))]
@@ -25584,7 +25584,7 @@ pub unsafe fn vld4q_dup_s32(a: *const i32) -> int32x4x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(ld4r))]
@@ -25603,7 +25603,7 @@ pub unsafe fn vld4_dup_s64(a: *const i64) -> int64x1x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -25626,7 +25626,7 @@ pub unsafe fn vld4_dup_p64(a: *const p64) -> poly64x1x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(nop))]
@@ -25642,7 +25642,7 @@ pub unsafe fn vld4_dup_s64(a: *const i64) -> int64x1x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -25665,7 +25665,7 @@ pub unsafe fn vld4_dup_u64(a: *const u64) -> uint64x1x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -25689,7 +25689,7 @@ pub unsafe fn vld4_dup_u8(a: *const u8) -> uint8x8x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -25718,7 +25718,7 @@ pub unsafe fn vld4_dup_u8(a: *const u8) -> uint8x8x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -25742,7 +25742,7 @@ pub unsafe fn vld4q_dup_u8(a: *const u8) -> uint8x16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -25795,7 +25795,7 @@ pub unsafe fn vld4q_dup_u8(a: *const u8) -> uint8x16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -25819,7 +25819,7 @@ pub unsafe fn vld4_dup_u16(a: *const u16) -> uint16x4x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -25848,7 +25848,7 @@ pub unsafe fn vld4_dup_u16(a: *const u16) -> uint16x4x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -25872,7 +25872,7 @@ pub unsafe fn vld4q_dup_u16(a: *const u16) -> uint16x8x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -25901,7 +25901,7 @@ pub unsafe fn vld4q_dup_u16(a: *const u16) -> uint16x8x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -25925,7 +25925,7 @@ pub unsafe fn vld4_dup_u32(a: *const u32) -> uint32x2x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -25954,7 +25954,7 @@ pub unsafe fn vld4_dup_u32(a: *const u32) -> uint32x2x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -25978,7 +25978,7 @@ pub unsafe fn vld4q_dup_u32(a: *const u32) -> uint32x4x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -26007,7 +26007,7 @@ pub unsafe fn vld4q_dup_u32(a: *const u32) -> uint32x4x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -26031,7 +26031,7 @@ pub unsafe fn vld4_dup_p8(a: *const p8) -> poly8x8x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -26060,7 +26060,7 @@ pub unsafe fn vld4_dup_p8(a: *const p8) -> poly8x8x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -26084,7 +26084,7 @@ pub unsafe fn vld4q_dup_p8(a: *const p8) -> poly8x16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -26137,7 +26137,7 @@ pub unsafe fn vld4q_dup_p8(a: *const p8) -> poly8x16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -26161,7 +26161,7 @@ pub unsafe fn vld4_dup_p16(a: *const p16) -> poly16x4x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -26190,7 +26190,7 @@ pub unsafe fn vld4_dup_p16(a: *const p16) -> poly16x4x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -26214,7 +26214,7 @@ pub unsafe fn vld4q_dup_p16(a: *const p16) -> poly16x8x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -26243,7 +26243,7 @@ pub unsafe fn vld4q_dup_p16(a: *const p16) -> poly16x8x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
@@ -26261,7 +26261,7 @@ pub unsafe fn vld4_f16(a: *const f16) -> float16x4x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))]
@@ -26279,7 +26279,7 @@ pub unsafe fn vld4q_f16(a: *const f16) -> float16x8x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -26302,7 +26302,7 @@ pub unsafe fn vld4_f16(a: *const f16) -> float16x4x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -26325,7 +26325,7 @@ pub unsafe fn vld4q_f16(a: *const f16) -> float16x8x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -26344,7 +26344,7 @@ pub unsafe fn vld4_f32(a: *const f32) -> float32x2x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -26363,7 +26363,7 @@ pub unsafe fn vld4q_f32(a: *const f32) -> float32x4x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -26382,7 +26382,7 @@ pub unsafe fn vld4_s8(a: *const i8) -> int8x8x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -26401,7 +26401,7 @@ pub unsafe fn vld4q_s8(a: *const i8) -> int8x16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -26420,7 +26420,7 @@ pub unsafe fn vld4_s16(a: *const i16) -> int16x4x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -26439,7 +26439,7 @@ pub unsafe fn vld4q_s16(a: *const i16) -> int16x8x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -26458,7 +26458,7 @@ pub unsafe fn vld4_s32(a: *const i32) -> int32x2x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -26477,7 +26477,7 @@ pub unsafe fn vld4q_s32(a: *const i32) -> int32x4x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -26493,7 +26493,7 @@ pub unsafe fn vld4_f32(a: *const f32) -> float32x2x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -26509,7 +26509,7 @@ pub unsafe fn vld4q_f32(a: *const f32) -> float32x4x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -26525,7 +26525,7 @@ pub unsafe fn vld4_s8(a: *const i8) -> int8x8x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -26541,7 +26541,7 @@ pub unsafe fn vld4q_s8(a: *const i8) -> int8x16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -26557,7 +26557,7 @@ pub unsafe fn vld4_s16(a: *const i16) -> int16x4x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -26573,7 +26573,7 @@ pub unsafe fn vld4q_s16(a: *const i16) -> int16x8x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -26589,7 +26589,7 @@ pub unsafe fn vld4_s32(a: *const i32) -> int32x2x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -26605,7 +26605,7 @@ pub unsafe fn vld4q_s32(a: *const i32) -> int32x4x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))]
@@ -26633,7 +26633,7 @@ pub unsafe fn vld4_lane_f16<const LANE: i32>(a: *const f16, b: float16x4x4_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))]
@@ -26661,7 +26661,7 @@ pub unsafe fn vld4q_lane_f16<const LANE: i32>(a: *const f16, b: float16x8x4_t) -
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -26693,7 +26693,7 @@ pub unsafe fn vld4_lane_f16<const LANE: i32>(a: *const f16, b: float16x4x4_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
@@ -26725,7 +26725,7 @@ pub unsafe fn vld4q_lane_f16<const LANE: i32>(a: *const f16, b: float16x8x4_t) -
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(ld4, LANE = 0))]
@@ -26753,7 +26753,7 @@ pub unsafe fn vld4_lane_f32<const LANE: i32>(a: *const f32, b: float32x2x4_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(ld4, LANE = 0))]
@@ -26781,7 +26781,7 @@ pub unsafe fn vld4q_lane_f32<const LANE: i32>(a: *const f32, b: float32x4x4_t) -
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(ld4, LANE = 0))]
@@ -26809,7 +26809,7 @@ pub unsafe fn vld4_lane_s8<const LANE: i32>(a: *const i8, b: int8x8x4_t) -> int8
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(ld4, LANE = 0))]
@@ -26837,7 +26837,7 @@ pub unsafe fn vld4_lane_s16<const LANE: i32>(a: *const i16, b: int16x4x4_t) -> i
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(ld4, LANE = 0))]
@@ -26865,7 +26865,7 @@ pub unsafe fn vld4q_lane_s16<const LANE: i32>(a: *const i16, b: int16x8x4_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(ld4, LANE = 0))]
@@ -26893,7 +26893,7 @@ pub unsafe fn vld4_lane_s32<const LANE: i32>(a: *const i32, b: int32x2x4_t) -> i
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(ld4, LANE = 0))]
@@ -26921,7 +26921,7 @@ pub unsafe fn vld4q_lane_s32<const LANE: i32>(a: *const i32, b: int32x4x4_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(test, assert_instr(vld4, LANE = 0))]
@@ -26947,7 +26947,7 @@ pub unsafe fn vld4_lane_f32<const LANE: i32>(a: *const f32, b: float32x2x4_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(test, assert_instr(vld4, LANE = 0))]
@@ -26973,7 +26973,7 @@ pub unsafe fn vld4q_lane_f32<const LANE: i32>(a: *const f32, b: float32x4x4_t) -
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(test, assert_instr(vld4, LANE = 0))]
@@ -26999,7 +26999,7 @@ pub unsafe fn vld4_lane_s8<const LANE: i32>(a: *const i8, b: int8x8x4_t) -> int8
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(test, assert_instr(vld4, LANE = 0))]
@@ -27025,7 +27025,7 @@ pub unsafe fn vld4_lane_s16<const LANE: i32>(a: *const i16, b: int16x4x4_t) -> i
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(test, assert_instr(vld4, LANE = 0))]
@@ -27051,7 +27051,7 @@ pub unsafe fn vld4q_lane_s16<const LANE: i32>(a: *const i16, b: int16x8x4_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(test, assert_instr(vld4, LANE = 0))]
@@ -27077,7 +27077,7 @@ pub unsafe fn vld4_lane_s32<const LANE: i32>(a: *const i32, b: int32x2x4_t) -> i
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(test, assert_instr(vld4, LANE = 0))]
@@ -27103,7 +27103,7 @@ pub unsafe fn vld4q_lane_s32<const LANE: i32>(a: *const i32, b: int32x4x4_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))]
@@ -27128,7 +27128,7 @@ pub unsafe fn vld4_lane_u8<const LANE: i32>(a: *const u8, b: uint8x8x4_t) -> uin
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))]
@@ -27153,7 +27153,7 @@ pub unsafe fn vld4_lane_u16<const LANE: i32>(a: *const u16, b: uint16x4x4_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))]
@@ -27178,7 +27178,7 @@ pub unsafe fn vld4q_lane_u16<const LANE: i32>(a: *const u16, b: uint16x8x4_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))]
@@ -27203,7 +27203,7 @@ pub unsafe fn vld4_lane_u32<const LANE: i32>(a: *const u32, b: uint32x2x4_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))]
@@ -27228,7 +27228,7 @@ pub unsafe fn vld4q_lane_u32<const LANE: i32>(a: *const u32, b: uint32x4x4_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))]
@@ -27253,7 +27253,7 @@ pub unsafe fn vld4_lane_p8<const LANE: i32>(a: *const p8, b: poly8x8x4_t) -> pol
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))]
@@ -27278,7 +27278,7 @@ pub unsafe fn vld4_lane_p16<const LANE: i32>(a: *const p16, b: poly16x4x4_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))]
@@ -27303,7 +27303,7 @@ pub unsafe fn vld4q_lane_p16<const LANE: i32>(a: *const p16, b: poly16x8x4_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -27326,7 +27326,7 @@ pub unsafe fn vld4_p64(a: *const p64) -> poly64x1x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -27345,7 +27345,7 @@ pub unsafe fn vld4_s64(a: *const i64) -> int64x1x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -27361,7 +27361,7 @@ pub unsafe fn vld4_s64(a: *const i64) -> int64x1x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -27384,7 +27384,7 @@ pub unsafe fn vld4_u64(a: *const u64) -> uint64x1x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -27408,7 +27408,7 @@ pub unsafe fn vld4_u8(a: *const u8) -> uint8x8x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -27437,7 +27437,7 @@ pub unsafe fn vld4_u8(a: *const u8) -> uint8x8x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -27461,7 +27461,7 @@ pub unsafe fn vld4q_u8(a: *const u8) -> uint8x16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -27514,7 +27514,7 @@ pub unsafe fn vld4q_u8(a: *const u8) -> uint8x16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -27538,7 +27538,7 @@ pub unsafe fn vld4_u16(a: *const u16) -> uint16x4x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -27567,7 +27567,7 @@ pub unsafe fn vld4_u16(a: *const u16) -> uint16x4x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -27591,7 +27591,7 @@ pub unsafe fn vld4q_u16(a: *const u16) -> uint16x8x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -27620,7 +27620,7 @@ pub unsafe fn vld4q_u16(a: *const u16) -> uint16x8x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -27644,7 +27644,7 @@ pub unsafe fn vld4_u32(a: *const u32) -> uint32x2x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -27673,7 +27673,7 @@ pub unsafe fn vld4_u32(a: *const u32) -> uint32x2x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -27697,7 +27697,7 @@ pub unsafe fn vld4q_u32(a: *const u32) -> uint32x4x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -27726,7 +27726,7 @@ pub unsafe fn vld4q_u32(a: *const u32) -> uint32x4x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -27750,7 +27750,7 @@ pub unsafe fn vld4_p8(a: *const p8) -> poly8x8x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -27779,7 +27779,7 @@ pub unsafe fn vld4_p8(a: *const p8) -> poly8x8x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -27803,7 +27803,7 @@ pub unsafe fn vld4q_p8(a: *const p8) -> poly8x16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -27856,7 +27856,7 @@ pub unsafe fn vld4q_p8(a: *const p8) -> poly8x16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -27880,7 +27880,7 @@ pub unsafe fn vld4_p16(a: *const p16) -> poly16x4x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -27909,7 +27909,7 @@ pub unsafe fn vld4_p16(a: *const p16) -> poly16x4x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -27933,7 +27933,7 @@ pub unsafe fn vld4q_p16(a: *const p16) -> poly16x8x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -27962,7 +27962,7 @@ pub unsafe fn vld4q_p16(a: *const p16) -> poly16x8x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldrq_p128)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -27983,7 +27983,7 @@ pub unsafe fn vldrq_p128(a: *const p128) -> p128 {
 }
 #[doc = "Maximum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
 #[cfg_attr(
@@ -28013,7 +28013,7 @@ pub fn vmax_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 }
 #[doc = "Maximum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
 #[cfg_attr(
@@ -28043,7 +28043,7 @@ pub fn vmaxq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
 }
 #[doc = "Maximum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
@@ -28072,7 +28072,7 @@ pub fn vmax_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
 }
 #[doc = "Maximum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
@@ -28101,7 +28101,7 @@ pub fn vmaxq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
 }
 #[doc = "Maximum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
@@ -28125,7 +28125,7 @@ pub fn vmax_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Maximum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
@@ -28149,7 +28149,7 @@ pub fn vmaxq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Maximum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
@@ -28173,7 +28173,7 @@ pub fn vmax_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Maximum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
@@ -28197,7 +28197,7 @@ pub fn vmaxq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Maximum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
@@ -28221,7 +28221,7 @@ pub fn vmax_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Maximum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
@@ -28245,7 +28245,7 @@ pub fn vmaxq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Maximum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
@@ -28269,7 +28269,7 @@ pub fn vmax_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Maximum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
@@ -28293,7 +28293,7 @@ pub fn vmaxq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Maximum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
@@ -28317,7 +28317,7 @@ pub fn vmax_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Maximum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
@@ -28341,7 +28341,7 @@ pub fn vmaxq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Maximum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
@@ -28365,7 +28365,7 @@ pub fn vmax_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Maximum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))]
@@ -28389,7 +28389,7 @@ pub fn vmaxq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Floating-point Maximum Number (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnm_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmaxnm))]
 #[cfg_attr(
@@ -28411,7 +28411,7 @@ pub fn vmaxnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 }
 #[doc = "Floating-point Maximum Number (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmq_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmaxnm))]
 #[cfg_attr(
@@ -28433,7 +28433,7 @@ pub fn vmaxnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
 }
 #[doc = "Floating-point Maximum Number (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnm_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmaxnm))]
@@ -28454,7 +28454,7 @@ pub fn vmaxnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
 }
 #[doc = "Floating-point Maximum Number (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmaxnm))]
@@ -28475,7 +28475,7 @@ pub fn vmaxnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
 }
 #[doc = "Minimum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
 #[cfg_attr(
@@ -28505,7 +28505,7 @@ pub fn vmin_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 }
 #[doc = "Minimum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
 #[cfg_attr(
@@ -28535,7 +28535,7 @@ pub fn vminq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
 }
 #[doc = "Minimum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
@@ -28564,7 +28564,7 @@ pub fn vmin_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
 }
 #[doc = "Minimum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
@@ -28593,7 +28593,7 @@ pub fn vminq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
 }
 #[doc = "Minimum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
@@ -28617,7 +28617,7 @@ pub fn vmin_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Minimum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
@@ -28641,7 +28641,7 @@ pub fn vminq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Minimum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
@@ -28665,7 +28665,7 @@ pub fn vmin_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Minimum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
@@ -28689,7 +28689,7 @@ pub fn vminq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Minimum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
@@ -28713,7 +28713,7 @@ pub fn vmin_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Minimum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
@@ -28737,7 +28737,7 @@ pub fn vminq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Minimum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
@@ -28761,7 +28761,7 @@ pub fn vmin_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Minimum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
@@ -28785,7 +28785,7 @@ pub fn vminq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Minimum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
@@ -28809,7 +28809,7 @@ pub fn vmin_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Minimum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
@@ -28833,7 +28833,7 @@ pub fn vminq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Minimum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
@@ -28857,7 +28857,7 @@ pub fn vmin_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Minimum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))]
@@ -28881,7 +28881,7 @@ pub fn vminq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Floating-point Minimum Number (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnm_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vminnm))]
 #[cfg_attr(
@@ -28903,7 +28903,7 @@ pub fn vminnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 }
 #[doc = "Floating-point Minimum Number (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmq_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vminnm))]
 #[cfg_attr(
@@ -28925,7 +28925,7 @@ pub fn vminnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
 }
 #[doc = "Floating-point Minimum Number (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnm_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vminnm))]
@@ -28946,7 +28946,7 @@ pub fn vminnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
 }
 #[doc = "Floating-point Minimum Number (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vminnm))]
@@ -28967,7 +28967,7 @@ pub fn vminnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
 }
 #[doc = "Floating-point multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.f32"))]
@@ -28988,7 +28988,7 @@ pub fn vmla_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t {
 }
 #[doc = "Floating-point multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.f32"))]
@@ -29009,7 +29009,7 @@ pub fn vmlaq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t
 }
 #[doc = "Vector multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_lane_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.f32", LANE = 1))]
@@ -29036,7 +29036,7 @@ pub fn vmla_lane_f32<const LANE: i32>(
 }
 #[doc = "Vector multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_laneq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.f32", LANE = 1))]
@@ -29063,7 +29063,7 @@ pub fn vmla_laneq_f32<const LANE: i32>(
 }
 #[doc = "Vector multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_lane_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.f32", LANE = 1))]
@@ -29096,7 +29096,7 @@ pub fn vmlaq_lane_f32<const LANE: i32>(
 }
 #[doc = "Vector multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_laneq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.f32", LANE = 1))]
@@ -29129,7 +29129,7 @@ pub fn vmlaq_laneq_f32<const LANE: i32>(
 }
 #[doc = "Vector multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_lane_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))]
@@ -29158,7 +29158,7 @@ pub fn vmla_lane_s16<const LANE: i32>(a: int16x4_t, b: int16x4_t, c: int16x4_t)
 }
 #[doc = "Vector multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_lane_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))]
@@ -29187,7 +29187,7 @@ pub fn vmla_lane_u16<const LANE: i32>(a: uint16x4_t, b: uint16x4_t, c: uint16x4_
 }
 #[doc = "Vector multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_laneq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))]
@@ -29216,7 +29216,7 @@ pub fn vmla_laneq_s16<const LANE: i32>(a: int16x4_t, b: int16x4_t, c: int16x8_t)
 }
 #[doc = "Vector multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_laneq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))]
@@ -29245,7 +29245,7 @@ pub fn vmla_laneq_u16<const LANE: i32>(a: uint16x4_t, b: uint16x4_t, c: uint16x8
 }
 #[doc = "Vector multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_lane_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))]
@@ -29287,7 +29287,7 @@ pub fn vmlaq_lane_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t, c: int16x4_t)
 }
 #[doc = "Vector multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_lane_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))]
@@ -29329,7 +29329,7 @@ pub fn vmlaq_lane_u16<const LANE: i32>(a: uint16x8_t, b: uint16x8_t, c: uint16x4
 }
 #[doc = "Vector multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_laneq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))]
@@ -29371,7 +29371,7 @@ pub fn vmlaq_laneq_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t, c: int16x8_t
 }
 #[doc = "Vector multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_laneq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))]
@@ -29413,7 +29413,7 @@ pub fn vmlaq_laneq_u16<const LANE: i32>(a: uint16x8_t, b: uint16x8_t, c: uint16x
 }
 #[doc = "Vector multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_lane_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))]
@@ -29436,7 +29436,7 @@ pub fn vmla_lane_s32<const LANE: i32>(a: int32x2_t, b: int32x2_t, c: int32x2_t)
 }
 #[doc = "Vector multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_lane_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))]
@@ -29459,7 +29459,7 @@ pub fn vmla_lane_u32<const LANE: i32>(a: uint32x2_t, b: uint32x2_t, c: uint32x2_
 }
 #[doc = "Vector multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_laneq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))]
@@ -29482,7 +29482,7 @@ pub fn vmla_laneq_s32<const LANE: i32>(a: int32x2_t, b: int32x2_t, c: int32x4_t)
 }
 #[doc = "Vector multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_laneq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))]
@@ -29505,7 +29505,7 @@ pub fn vmla_laneq_u32<const LANE: i32>(a: uint32x2_t, b: uint32x2_t, c: uint32x4
 }
 #[doc = "Vector multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_lane_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))]
@@ -29534,7 +29534,7 @@ pub fn vmlaq_lane_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t, c: int32x2_t)
 }
 #[doc = "Vector multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_lane_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))]
@@ -29563,7 +29563,7 @@ pub fn vmlaq_lane_u32<const LANE: i32>(a: uint32x4_t, b: uint32x4_t, c: uint32x2
 }
 #[doc = "Vector multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_laneq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))]
@@ -29592,7 +29592,7 @@ pub fn vmlaq_laneq_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t, c: int32x4_t
 }
 #[doc = "Vector multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_laneq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))]
@@ -29621,7 +29621,7 @@ pub fn vmlaq_laneq_u32<const LANE: i32>(a: uint32x4_t, b: uint32x4_t, c: uint32x
 }
 #[doc = "Vector multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_n_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.f32"))]
@@ -29642,7 +29642,7 @@ pub fn vmla_n_f32(a: float32x2_t, b: float32x2_t, c: f32) -> float32x2_t {
 }
 #[doc = "Vector multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_n_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.f32"))]
@@ -29663,7 +29663,7 @@ pub fn vmlaq_n_f32(a: float32x4_t, b: float32x4_t, c: f32) -> float32x4_t {
 }
 #[doc = "Vector multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16"))]
@@ -29684,7 +29684,7 @@ pub fn vmla_n_s16(a: int16x4_t, b: int16x4_t, c: i16) -> int16x4_t {
 }
 #[doc = "Vector multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16"))]
@@ -29705,7 +29705,7 @@ pub fn vmlaq_n_s16(a: int16x8_t, b: int16x8_t, c: i16) -> int16x8_t {
 }
 #[doc = "Vector multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_n_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16"))]
@@ -29726,7 +29726,7 @@ pub fn vmla_n_u16(a: uint16x4_t, b: uint16x4_t, c: u16) -> uint16x4_t {
 }
 #[doc = "Vector multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_n_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16"))]
@@ -29747,7 +29747,7 @@ pub fn vmlaq_n_u16(a: uint16x8_t, b: uint16x8_t, c: u16) -> uint16x8_t {
 }
 #[doc = "Vector multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32"))]
@@ -29768,7 +29768,7 @@ pub fn vmla_n_s32(a: int32x2_t, b: int32x2_t, c: i32) -> int32x2_t {
 }
 #[doc = "Vector multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32"))]
@@ -29789,7 +29789,7 @@ pub fn vmlaq_n_s32(a: int32x4_t, b: int32x4_t, c: i32) -> int32x4_t {
 }
 #[doc = "Vector multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_n_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32"))]
@@ -29810,7 +29810,7 @@ pub fn vmla_n_u32(a: uint32x2_t, b: uint32x2_t, c: u32) -> uint32x2_t {
 }
 #[doc = "Vector multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_n_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32"))]
@@ -29831,7 +29831,7 @@ pub fn vmlaq_n_u32(a: uint32x4_t, b: uint32x4_t, c: u32) -> uint32x4_t {
 }
 #[doc = "Multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i8"))]
@@ -29852,7 +29852,7 @@ pub fn vmla_s8(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t {
 }
 #[doc = "Multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i8"))]
@@ -29873,7 +29873,7 @@ pub fn vmlaq_s8(a: int8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t {
 }
 #[doc = "Multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16"))]
@@ -29894,7 +29894,7 @@ pub fn vmla_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t {
 }
 #[doc = "Multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16"))]
@@ -29915,7 +29915,7 @@ pub fn vmlaq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t {
 }
 #[doc = "Multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32"))]
@@ -29936,7 +29936,7 @@ pub fn vmla_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t {
 }
 #[doc = "Multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32"))]
@@ -29957,7 +29957,7 @@ pub fn vmlaq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t {
 }
 #[doc = "Multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i8"))]
@@ -29978,7 +29978,7 @@ pub fn vmla_u8(a: uint8x8_t, b: uint8x8_t, c: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i8"))]
@@ -29999,7 +29999,7 @@ pub fn vmlaq_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16"))]
@@ -30020,7 +30020,7 @@ pub fn vmla_u16(a: uint16x4_t, b: uint16x4_t, c: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16"))]
@@ -30041,7 +30041,7 @@ pub fn vmlaq_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32"))]
@@ -30062,7 +30062,7 @@ pub fn vmla_u32(a: uint32x2_t, b: uint32x2_t, c: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32"))]
@@ -30083,7 +30083,7 @@ pub fn vmlaq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Vector widening multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_lane_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s16", LANE = 1))]
@@ -30112,7 +30112,7 @@ pub fn vmlal_lane_s16<const LANE: i32>(a: int32x4_t, b: int16x4_t, c: int16x4_t)
 }
 #[doc = "Vector widening multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_laneq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s16", LANE = 1))]
@@ -30141,7 +30141,7 @@ pub fn vmlal_laneq_s16<const LANE: i32>(a: int32x4_t, b: int16x4_t, c: int16x8_t
 }
 #[doc = "Vector widening multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_lane_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s32", LANE = 1))]
@@ -30164,7 +30164,7 @@ pub fn vmlal_lane_s32<const LANE: i32>(a: int64x2_t, b: int32x2_t, c: int32x2_t)
 }
 #[doc = "Vector widening multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_laneq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s32", LANE = 1))]
@@ -30187,7 +30187,7 @@ pub fn vmlal_laneq_s32<const LANE: i32>(a: int64x2_t, b: int32x2_t, c: int32x4_t
 }
 #[doc = "Vector widening multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_lane_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u16", LANE = 1))]
@@ -30216,7 +30216,7 @@ pub fn vmlal_lane_u16<const LANE: i32>(a: uint32x4_t, b: uint16x4_t, c: uint16x4
 }
 #[doc = "Vector widening multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_laneq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u16", LANE = 1))]
@@ -30245,7 +30245,7 @@ pub fn vmlal_laneq_u16<const LANE: i32>(a: uint32x4_t, b: uint16x4_t, c: uint16x
 }
 #[doc = "Vector widening multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_lane_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u32", LANE = 1))]
@@ -30268,7 +30268,7 @@ pub fn vmlal_lane_u32<const LANE: i32>(a: uint64x2_t, b: uint32x2_t, c: uint32x2
 }
 #[doc = "Vector widening multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_laneq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u32", LANE = 1))]
@@ -30291,7 +30291,7 @@ pub fn vmlal_laneq_u32<const LANE: i32>(a: uint64x2_t, b: uint32x2_t, c: uint32x
 }
 #[doc = "Vector widening multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s16"))]
@@ -30312,7 +30312,7 @@ pub fn vmlal_n_s16(a: int32x4_t, b: int16x4_t, c: i16) -> int32x4_t {
 }
 #[doc = "Vector widening multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s32"))]
@@ -30333,7 +30333,7 @@ pub fn vmlal_n_s32(a: int64x2_t, b: int32x2_t, c: i32) -> int64x2_t {
 }
 #[doc = "Vector widening multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_n_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u16"))]
@@ -30354,7 +30354,7 @@ pub fn vmlal_n_u16(a: uint32x4_t, b: uint16x4_t, c: u16) -> uint32x4_t {
 }
 #[doc = "Vector widening multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_n_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u32"))]
@@ -30375,7 +30375,7 @@ pub fn vmlal_n_u32(a: uint64x2_t, b: uint32x2_t, c: u32) -> uint64x2_t {
 }
 #[doc = "Signed multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s8"))]
@@ -30396,7 +30396,7 @@ pub fn vmlal_s8(a: int16x8_t, b: int8x8_t, c: int8x8_t) -> int16x8_t {
 }
 #[doc = "Signed multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s16"))]
@@ -30417,7 +30417,7 @@ pub fn vmlal_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t {
 }
 #[doc = "Signed multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s32"))]
@@ -30438,7 +30438,7 @@ pub fn vmlal_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t {
 }
 #[doc = "Unsigned multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u8"))]
@@ -30459,7 +30459,7 @@ pub fn vmlal_u8(a: uint16x8_t, b: uint8x8_t, c: uint8x8_t) -> uint16x8_t {
 }
 #[doc = "Unsigned multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u16"))]
@@ -30480,7 +30480,7 @@ pub fn vmlal_u16(a: uint32x4_t, b: uint16x4_t, c: uint16x4_t) -> uint32x4_t {
 }
 #[doc = "Unsigned multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u32"))]
@@ -30501,7 +30501,7 @@ pub fn vmlal_u32(a: uint64x2_t, b: uint32x2_t, c: uint32x2_t) -> uint64x2_t {
 }
 #[doc = "Floating-point multiply-subtract from accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.f32"))]
@@ -30522,7 +30522,7 @@ pub fn vmls_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t {
 }
 #[doc = "Floating-point multiply-subtract from accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.f32"))]
@@ -30543,7 +30543,7 @@ pub fn vmlsq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t
 }
 #[doc = "Vector multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_lane_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.f32", LANE = 1))]
@@ -30570,7 +30570,7 @@ pub fn vmls_lane_f32<const LANE: i32>(
 }
 #[doc = "Vector multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_laneq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.f32", LANE = 1))]
@@ -30597,7 +30597,7 @@ pub fn vmls_laneq_f32<const LANE: i32>(
 }
 #[doc = "Vector multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_lane_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.f32", LANE = 1))]
@@ -30630,7 +30630,7 @@ pub fn vmlsq_lane_f32<const LANE: i32>(
 }
 #[doc = "Vector multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_laneq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.f32", LANE = 1))]
@@ -30663,7 +30663,7 @@ pub fn vmlsq_laneq_f32<const LANE: i32>(
 }
 #[doc = "Vector multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_lane_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16", LANE = 1))]
@@ -30692,7 +30692,7 @@ pub fn vmls_lane_s16<const LANE: i32>(a: int16x4_t, b: int16x4_t, c: int16x4_t)
 }
 #[doc = "Vector multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_lane_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16", LANE = 1))]
@@ -30721,7 +30721,7 @@ pub fn vmls_lane_u16<const LANE: i32>(a: uint16x4_t, b: uint16x4_t, c: uint16x4_
 }
 #[doc = "Vector multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_laneq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16", LANE = 1))]
@@ -30750,7 +30750,7 @@ pub fn vmls_laneq_s16<const LANE: i32>(a: int16x4_t, b: int16x4_t, c: int16x8_t)
 }
 #[doc = "Vector multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_laneq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16", LANE = 1))]
@@ -30779,7 +30779,7 @@ pub fn vmls_laneq_u16<const LANE: i32>(a: uint16x4_t, b: uint16x4_t, c: uint16x8
 }
 #[doc = "Vector multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_lane_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16", LANE = 1))]
@@ -30821,7 +30821,7 @@ pub fn vmlsq_lane_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t, c: int16x4_t)
 }
 #[doc = "Vector multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_lane_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16", LANE = 1))]
@@ -30863,7 +30863,7 @@ pub fn vmlsq_lane_u16<const LANE: i32>(a: uint16x8_t, b: uint16x8_t, c: uint16x4
 }
 #[doc = "Vector multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_laneq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16", LANE = 1))]
@@ -30905,7 +30905,7 @@ pub fn vmlsq_laneq_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t, c: int16x8_t
 }
 #[doc = "Vector multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_laneq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16", LANE = 1))]
@@ -30947,7 +30947,7 @@ pub fn vmlsq_laneq_u16<const LANE: i32>(a: uint16x8_t, b: uint16x8_t, c: uint16x
 }
 #[doc = "Vector multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_lane_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32", LANE = 1))]
@@ -30970,7 +30970,7 @@ pub fn vmls_lane_s32<const LANE: i32>(a: int32x2_t, b: int32x2_t, c: int32x2_t)
 }
 #[doc = "Vector multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_lane_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32", LANE = 1))]
@@ -30993,7 +30993,7 @@ pub fn vmls_lane_u32<const LANE: i32>(a: uint32x2_t, b: uint32x2_t, c: uint32x2_
 }
 #[doc = "Vector multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_laneq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32", LANE = 1))]
@@ -31016,7 +31016,7 @@ pub fn vmls_laneq_s32<const LANE: i32>(a: int32x2_t, b: int32x2_t, c: int32x4_t)
 }
 #[doc = "Vector multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_laneq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32", LANE = 1))]
@@ -31039,7 +31039,7 @@ pub fn vmls_laneq_u32<const LANE: i32>(a: uint32x2_t, b: uint32x2_t, c: uint32x4
 }
 #[doc = "Vector multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_lane_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32", LANE = 1))]
@@ -31068,7 +31068,7 @@ pub fn vmlsq_lane_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t, c: int32x2_t)
 }
 #[doc = "Vector multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_lane_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32", LANE = 1))]
@@ -31097,7 +31097,7 @@ pub fn vmlsq_lane_u32<const LANE: i32>(a: uint32x4_t, b: uint32x4_t, c: uint32x2
 }
 #[doc = "Vector multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_laneq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32", LANE = 1))]
@@ -31126,7 +31126,7 @@ pub fn vmlsq_laneq_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t, c: int32x4_t
 }
 #[doc = "Vector multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_laneq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32", LANE = 1))]
@@ -31155,7 +31155,7 @@ pub fn vmlsq_laneq_u32<const LANE: i32>(a: uint32x4_t, b: uint32x4_t, c: uint32x
 }
 #[doc = "Vector multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_n_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.f32"))]
@@ -31176,7 +31176,7 @@ pub fn vmls_n_f32(a: float32x2_t, b: float32x2_t, c: f32) -> float32x2_t {
 }
 #[doc = "Vector multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_n_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.f32"))]
@@ -31197,7 +31197,7 @@ pub fn vmlsq_n_f32(a: float32x4_t, b: float32x4_t, c: f32) -> float32x4_t {
 }
 #[doc = "Vector multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16"))]
@@ -31218,7 +31218,7 @@ pub fn vmls_n_s16(a: int16x4_t, b: int16x4_t, c: i16) -> int16x4_t {
 }
 #[doc = "Vector multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16"))]
@@ -31239,7 +31239,7 @@ pub fn vmlsq_n_s16(a: int16x8_t, b: int16x8_t, c: i16) -> int16x8_t {
 }
 #[doc = "Vector multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_n_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16"))]
@@ -31260,7 +31260,7 @@ pub fn vmls_n_u16(a: uint16x4_t, b: uint16x4_t, c: u16) -> uint16x4_t {
 }
 #[doc = "Vector multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_n_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16"))]
@@ -31281,7 +31281,7 @@ pub fn vmlsq_n_u16(a: uint16x8_t, b: uint16x8_t, c: u16) -> uint16x8_t {
 }
 #[doc = "Vector multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32"))]
@@ -31302,7 +31302,7 @@ pub fn vmls_n_s32(a: int32x2_t, b: int32x2_t, c: i32) -> int32x2_t {
 }
 #[doc = "Vector multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32"))]
@@ -31323,7 +31323,7 @@ pub fn vmlsq_n_s32(a: int32x4_t, b: int32x4_t, c: i32) -> int32x4_t {
 }
 #[doc = "Vector multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_n_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32"))]
@@ -31344,7 +31344,7 @@ pub fn vmls_n_u32(a: uint32x2_t, b: uint32x2_t, c: u32) -> uint32x2_t {
 }
 #[doc = "Vector multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_n_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32"))]
@@ -31365,7 +31365,7 @@ pub fn vmlsq_n_u32(a: uint32x4_t, b: uint32x4_t, c: u32) -> uint32x4_t {
 }
 #[doc = "Multiply-subtract from accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i8"))]
@@ -31386,7 +31386,7 @@ pub fn vmls_s8(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t {
 }
 #[doc = "Multiply-subtract from accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i8"))]
@@ -31407,7 +31407,7 @@ pub fn vmlsq_s8(a: int8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t {
 }
 #[doc = "Multiply-subtract from accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16"))]
@@ -31428,7 +31428,7 @@ pub fn vmls_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t {
 }
 #[doc = "Multiply-subtract from accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16"))]
@@ -31449,7 +31449,7 @@ pub fn vmlsq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t {
 }
 #[doc = "Multiply-subtract from accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32"))]
@@ -31470,7 +31470,7 @@ pub fn vmls_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t {
 }
 #[doc = "Multiply-subtract from accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32"))]
@@ -31491,7 +31491,7 @@ pub fn vmlsq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t {
 }
 #[doc = "Multiply-subtract from accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i8"))]
@@ -31512,7 +31512,7 @@ pub fn vmls_u8(a: uint8x8_t, b: uint8x8_t, c: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Multiply-subtract from accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i8"))]
@@ -31533,7 +31533,7 @@ pub fn vmlsq_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Multiply-subtract from accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16"))]
@@ -31554,7 +31554,7 @@ pub fn vmls_u16(a: uint16x4_t, b: uint16x4_t, c: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Multiply-subtract from accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16"))]
@@ -31575,7 +31575,7 @@ pub fn vmlsq_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Multiply-subtract from accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32"))]
@@ -31596,7 +31596,7 @@ pub fn vmls_u32(a: uint32x2_t, b: uint32x2_t, c: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Multiply-subtract from accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32"))]
@@ -31617,7 +31617,7 @@ pub fn vmlsq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Vector widening multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_lane_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s16", LANE = 1))]
@@ -31646,7 +31646,7 @@ pub fn vmlsl_lane_s16<const LANE: i32>(a: int32x4_t, b: int16x4_t, c: int16x4_t)
 }
 #[doc = "Vector widening multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_laneq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s16", LANE = 1))]
@@ -31675,7 +31675,7 @@ pub fn vmlsl_laneq_s16<const LANE: i32>(a: int32x4_t, b: int16x4_t, c: int16x8_t
 }
 #[doc = "Vector widening multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_lane_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s32", LANE = 1))]
@@ -31698,7 +31698,7 @@ pub fn vmlsl_lane_s32<const LANE: i32>(a: int64x2_t, b: int32x2_t, c: int32x2_t)
 }
 #[doc = "Vector widening multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_laneq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s32", LANE = 1))]
@@ -31721,7 +31721,7 @@ pub fn vmlsl_laneq_s32<const LANE: i32>(a: int64x2_t, b: int32x2_t, c: int32x4_t
 }
 #[doc = "Vector widening multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_lane_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u16", LANE = 1))]
@@ -31750,7 +31750,7 @@ pub fn vmlsl_lane_u16<const LANE: i32>(a: uint32x4_t, b: uint16x4_t, c: uint16x4
 }
 #[doc = "Vector widening multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_laneq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u16", LANE = 1))]
@@ -31779,7 +31779,7 @@ pub fn vmlsl_laneq_u16<const LANE: i32>(a: uint32x4_t, b: uint16x4_t, c: uint16x
 }
 #[doc = "Vector widening multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_lane_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u32", LANE = 1))]
@@ -31802,7 +31802,7 @@ pub fn vmlsl_lane_u32<const LANE: i32>(a: uint64x2_t, b: uint32x2_t, c: uint32x2
 }
 #[doc = "Vector widening multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_laneq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u32", LANE = 1))]
@@ -31825,7 +31825,7 @@ pub fn vmlsl_laneq_u32<const LANE: i32>(a: uint64x2_t, b: uint32x2_t, c: uint32x
 }
 #[doc = "Vector widening multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s16"))]
@@ -31846,7 +31846,7 @@ pub fn vmlsl_n_s16(a: int32x4_t, b: int16x4_t, c: i16) -> int32x4_t {
 }
 #[doc = "Vector widening multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s32"))]
@@ -31867,7 +31867,7 @@ pub fn vmlsl_n_s32(a: int64x2_t, b: int32x2_t, c: i32) -> int64x2_t {
 }
 #[doc = "Vector widening multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_n_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u16"))]
@@ -31888,7 +31888,7 @@ pub fn vmlsl_n_u16(a: uint32x4_t, b: uint16x4_t, c: u16) -> uint32x4_t {
 }
 #[doc = "Vector widening multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_n_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u32"))]
@@ -31909,7 +31909,7 @@ pub fn vmlsl_n_u32(a: uint64x2_t, b: uint32x2_t, c: u32) -> uint64x2_t {
 }
 #[doc = "Signed multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s8"))]
@@ -31930,7 +31930,7 @@ pub fn vmlsl_s8(a: int16x8_t, b: int8x8_t, c: int8x8_t) -> int16x8_t {
 }
 #[doc = "Signed multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s16"))]
@@ -31951,7 +31951,7 @@ pub fn vmlsl_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t {
 }
 #[doc = "Signed multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s32"))]
@@ -31972,7 +31972,7 @@ pub fn vmlsl_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t {
 }
 #[doc = "Unsigned multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u8"))]
@@ -31993,7 +31993,7 @@ pub fn vmlsl_u8(a: uint16x8_t, b: uint8x8_t, c: uint8x8_t) -> uint16x8_t {
 }
 #[doc = "Unsigned multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u16"))]
@@ -32014,7 +32014,7 @@ pub fn vmlsl_u16(a: uint32x4_t, b: uint16x4_t, c: uint16x4_t) -> uint32x4_t {
 }
 #[doc = "Unsigned multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u32"))]
@@ -32035,7 +32035,7 @@ pub fn vmlsl_u32(a: uint64x2_t, b: uint32x2_t, c: uint32x2_t) -> uint64x2_t {
 }
 #[doc = "8-bit integer matrix multiply-accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmmlaq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,i8mm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -32064,7 +32064,7 @@ pub fn vmmlaq_s32(a: int32x4_t, b: int8x16_t, c: int8x16_t) -> int32x4_t {
 }
 #[doc = "8-bit integer matrix multiply-accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmmlaq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,i8mm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -32093,7 +32093,7 @@ pub fn vmmlaq_u32(a: uint32x4_t, b: uint8x16_t, c: uint8x16_t) -> uint32x4_t {
 }
 #[doc = "Duplicate element to vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
@@ -32109,7 +32109,7 @@ pub fn vmov_n_f16(a: f16) -> float16x4_t {
 }
 #[doc = "Duplicate element to vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
@@ -32125,7 +32125,7 @@ pub fn vmovq_n_f16(a: f16) -> float16x8_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))]
@@ -32146,7 +32146,7 @@ pub fn vmov_n_f32(value: f32) -> float32x2_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_p16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
@@ -32167,7 +32167,7 @@ pub fn vmov_n_p16(value: p16) -> poly16x4_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))]
@@ -32188,7 +32188,7 @@ pub fn vmov_n_p8(value: p8) -> poly8x8_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
@@ -32209,7 +32209,7 @@ pub fn vmov_n_s16(value: i16) -> int16x4_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))]
@@ -32230,7 +32230,7 @@ pub fn vmov_n_s32(value: i32) -> int32x2_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
@@ -32251,7 +32251,7 @@ pub fn vmov_n_s64(value: i64) -> int64x1_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))]
@@ -32272,7 +32272,7 @@ pub fn vmov_n_s8(value: i8) -> int8x8_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
@@ -32293,7 +32293,7 @@ pub fn vmov_n_u16(value: u16) -> uint16x4_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))]
@@ -32314,7 +32314,7 @@ pub fn vmov_n_u32(value: u32) -> uint32x2_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
@@ -32335,7 +32335,7 @@ pub fn vmov_n_u64(value: u64) -> uint64x1_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))]
@@ -32356,7 +32356,7 @@ pub fn vmov_n_u8(value: u8) -> uint8x8_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))]
@@ -32377,7 +32377,7 @@ pub fn vmovq_n_f32(value: f32) -> float32x4_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_p16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
@@ -32398,7 +32398,7 @@ pub fn vmovq_n_p16(value: p16) -> poly16x8_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))]
@@ -32419,7 +32419,7 @@ pub fn vmovq_n_p8(value: p8) -> poly8x16_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
@@ -32440,7 +32440,7 @@ pub fn vmovq_n_s16(value: i16) -> int16x8_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))]
@@ -32461,7 +32461,7 @@ pub fn vmovq_n_s32(value: i32) -> int32x4_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
@@ -32482,7 +32482,7 @@ pub fn vmovq_n_s64(value: i64) -> int64x2_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))]
@@ -32503,7 +32503,7 @@ pub fn vmovq_n_s8(value: i8) -> int8x16_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16"))]
@@ -32524,7 +32524,7 @@ pub fn vmovq_n_u16(value: u16) -> uint16x8_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32"))]
@@ -32545,7 +32545,7 @@ pub fn vmovq_n_u32(value: u32) -> uint32x4_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
@@ -32566,7 +32566,7 @@ pub fn vmovq_n_u64(value: u64) -> uint64x2_t {
 }
 #[doc = "Duplicate vector element to vector or scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8"))]
@@ -32587,7 +32587,7 @@ pub fn vmovq_n_u8(value: u8) -> uint8x16_t {
 }
 #[doc = "Vector long move."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovl))]
@@ -32608,7 +32608,7 @@ pub fn vmovl_s16(a: int16x4_t) -> int32x4_t {
 }
 #[doc = "Vector long move."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovl))]
@@ -32629,7 +32629,7 @@ pub fn vmovl_s32(a: int32x2_t) -> int64x2_t {
 }
 #[doc = "Vector long move."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovl))]
@@ -32650,7 +32650,7 @@ pub fn vmovl_s8(a: int8x8_t) -> int16x8_t {
 }
 #[doc = "Vector long move."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovl))]
@@ -32671,7 +32671,7 @@ pub fn vmovl_u16(a: uint16x4_t) -> uint32x4_t {
 }
 #[doc = "Vector long move."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovl))]
@@ -32692,7 +32692,7 @@ pub fn vmovl_u32(a: uint32x2_t) -> uint64x2_t {
 }
 #[doc = "Vector long move."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovl))]
@@ -32713,7 +32713,7 @@ pub fn vmovl_u8(a: uint8x8_t) -> uint16x8_t {
 }
 #[doc = "Vector narrow integer."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovn))]
@@ -32734,7 +32734,7 @@ pub fn vmovn_s16(a: int16x8_t) -> int8x8_t {
 }
 #[doc = "Vector narrow integer."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovn))]
@@ -32755,7 +32755,7 @@ pub fn vmovn_s32(a: int32x4_t) -> int16x4_t {
 }
 #[doc = "Vector narrow integer."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovn))]
@@ -32776,7 +32776,7 @@ pub fn vmovn_s64(a: int64x2_t) -> int32x2_t {
 }
 #[doc = "Vector narrow integer."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovn))]
@@ -32797,7 +32797,7 @@ pub fn vmovn_u16(a: uint16x8_t) -> uint8x8_t {
 }
 #[doc = "Vector narrow integer."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovn))]
@@ -32818,7 +32818,7 @@ pub fn vmovn_u32(a: uint32x4_t) -> uint16x4_t {
 }
 #[doc = "Vector narrow integer."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmovn))]
@@ -32839,7 +32839,7 @@ pub fn vmovn_u64(a: uint64x2_t) -> uint32x2_t {
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.f16"))]
 #[cfg_attr(
@@ -32861,7 +32861,7 @@ pub fn vmul_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.f16"))]
 #[cfg_attr(
@@ -32883,7 +32883,7 @@ pub fn vmulq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.f32"))]
@@ -32904,7 +32904,7 @@ pub fn vmul_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.f32"))]
@@ -32925,7 +32925,7 @@ pub fn vmulq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_lane_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
 #[cfg_attr(
@@ -32954,7 +32954,7 @@ pub fn vmul_lane_f16<const LANE: i32>(a: float16x4_t, v: float16x4_t) -> float16
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_lane_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
 #[cfg_attr(
@@ -32996,7 +32996,7 @@ pub fn vmulq_lane_f16<const LANE: i32>(a: float16x8_t, v: float16x4_t) -> float1
 }
 #[doc = "Floating-point multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_lane_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 0))]
@@ -33019,7 +33019,7 @@ pub fn vmul_lane_f32<const LANE: i32>(a: float32x2_t, b: float32x2_t) -> float32
 }
 #[doc = "Floating-point multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_laneq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 0))]
@@ -33042,7 +33042,7 @@ pub fn vmul_laneq_f32<const LANE: i32>(a: float32x2_t, b: float32x4_t) -> float3
 }
 #[doc = "Floating-point multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_lane_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 0))]
@@ -33070,7 +33070,7 @@ pub fn vmulq_lane_f32<const LANE: i32>(a: float32x4_t, b: float32x2_t) -> float3
 }
 #[doc = "Floating-point multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 0))]
@@ -33098,7 +33098,7 @@ pub fn vmulq_laneq_f32<const LANE: i32>(a: float32x4_t, b: float32x4_t) -> float
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_lane_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
@@ -33126,7 +33126,7 @@ pub fn vmul_lane_s16<const LANE: i32>(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_lane_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
@@ -33167,7 +33167,7 @@ pub fn vmulq_lane_s16<const LANE: i32>(a: int16x8_t, b: int16x4_t) -> int16x8_t
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_lane_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
@@ -33190,7 +33190,7 @@ pub fn vmul_lane_s32<const LANE: i32>(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_lane_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
@@ -33218,7 +33218,7 @@ pub fn vmulq_lane_s32<const LANE: i32>(a: int32x4_t, b: int32x2_t) -> int32x4_t
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_lane_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
@@ -33246,7 +33246,7 @@ pub fn vmul_lane_u16<const LANE: i32>(a: uint16x4_t, b: uint16x4_t) -> uint16x4_
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_lane_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
@@ -33287,7 +33287,7 @@ pub fn vmulq_lane_u16<const LANE: i32>(a: uint16x8_t, b: uint16x4_t) -> uint16x8
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_lane_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
@@ -33310,7 +33310,7 @@ pub fn vmul_lane_u32<const LANE: i32>(a: uint32x2_t, b: uint32x2_t) -> uint32x2_
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_lane_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
@@ -33338,7 +33338,7 @@ pub fn vmulq_lane_u32<const LANE: i32>(a: uint32x4_t, b: uint32x2_t) -> uint32x4
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_laneq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
@@ -33366,7 +33366,7 @@ pub fn vmul_laneq_s16<const LANE: i32>(a: int16x4_t, b: int16x8_t) -> int16x4_t
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
@@ -33407,7 +33407,7 @@ pub fn vmulq_laneq_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t) -> int16x8_t
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_laneq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
@@ -33430,7 +33430,7 @@ pub fn vmul_laneq_s32<const LANE: i32>(a: int32x2_t, b: int32x4_t) -> int32x2_t
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
@@ -33458,7 +33458,7 @@ pub fn vmulq_laneq_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t) -> int32x4_t
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_laneq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
@@ -33486,7 +33486,7 @@ pub fn vmul_laneq_u16<const LANE: i32>(a: uint16x4_t, b: uint16x8_t) -> uint16x4
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
@@ -33527,7 +33527,7 @@ pub fn vmulq_laneq_u16<const LANE: i32>(a: uint16x8_t, b: uint16x8_t) -> uint16x
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_laneq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
@@ -33550,7 +33550,7 @@ pub fn vmul_laneq_u32<const LANE: i32>(a: uint32x2_t, b: uint32x4_t) -> uint32x2
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
@@ -33578,7 +33578,7 @@ pub fn vmulq_laneq_u32<const LANE: i32>(a: uint32x4_t, b: uint32x4_t) -> uint32x
 }
 #[doc = "Vector multiply by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_n_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
 #[cfg_attr(
@@ -33593,7 +33593,7 @@ pub fn vmul_n_f16(a: float16x4_t, b: f16) -> float16x4_t {
 }
 #[doc = "Vector multiply by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_n_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
 #[cfg_attr(
@@ -33608,7 +33608,7 @@ pub fn vmulq_n_f16(a: float16x8_t, b: f16) -> float16x8_t {
 }
 #[doc = "Vector multiply by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_n_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
@@ -33629,7 +33629,7 @@ pub fn vmul_n_f32(a: float32x2_t, b: f32) -> float32x2_t {
 }
 #[doc = "Vector multiply by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_n_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
@@ -33650,7 +33650,7 @@ pub fn vmulq_n_f32(a: float32x4_t, b: f32) -> float32x4_t {
 }
 #[doc = "Vector multiply by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
@@ -33671,7 +33671,7 @@ pub fn vmul_n_s16(a: int16x4_t, b: i16) -> int16x4_t {
 }
 #[doc = "Vector multiply by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
@@ -33692,7 +33692,7 @@ pub fn vmulq_n_s16(a: int16x8_t, b: i16) -> int16x8_t {
 }
 #[doc = "Vector multiply by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
@@ -33713,7 +33713,7 @@ pub fn vmul_n_s32(a: int32x2_t, b: i32) -> int32x2_t {
 }
 #[doc = "Vector multiply by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
@@ -33734,7 +33734,7 @@ pub fn vmulq_n_s32(a: int32x4_t, b: i32) -> int32x4_t {
 }
 #[doc = "Vector multiply by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_n_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
@@ -33755,7 +33755,7 @@ pub fn vmul_n_u16(a: uint16x4_t, b: u16) -> uint16x4_t {
 }
 #[doc = "Vector multiply by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_n_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
@@ -33776,7 +33776,7 @@ pub fn vmulq_n_u16(a: uint16x8_t, b: u16) -> uint16x8_t {
 }
 #[doc = "Vector multiply by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_n_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
@@ -33797,7 +33797,7 @@ pub fn vmul_n_u32(a: uint32x2_t, b: u32) -> uint32x2_t {
 }
 #[doc = "Vector multiply by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_n_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
@@ -33818,7 +33818,7 @@ pub fn vmulq_n_u32(a: uint32x4_t, b: u32) -> uint32x4_t {
 }
 #[doc = "Polynomial multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
@@ -33847,7 +33847,7 @@ pub fn vmul_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
 }
 #[doc = "Polynomial multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
@@ -33876,7 +33876,7 @@ pub fn vmulq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t {
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i16"))]
@@ -33897,7 +33897,7 @@ pub fn vmul_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i16"))]
@@ -33918,7 +33918,7 @@ pub fn vmulq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i16"))]
@@ -33939,7 +33939,7 @@ pub fn vmul_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i16"))]
@@ -33960,7 +33960,7 @@ pub fn vmulq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i32"))]
@@ -33981,7 +33981,7 @@ pub fn vmul_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i32"))]
@@ -34002,7 +34002,7 @@ pub fn vmulq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i32"))]
@@ -34023,7 +34023,7 @@ pub fn vmul_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i32"))]
@@ -34044,7 +34044,7 @@ pub fn vmulq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i8"))]
@@ -34065,7 +34065,7 @@ pub fn vmul_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i8"))]
@@ -34086,7 +34086,7 @@ pub fn vmulq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i8"))]
@@ -34107,7 +34107,7 @@ pub fn vmul_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Multiply"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i8"))]
@@ -34128,7 +34128,7 @@ pub fn vmulq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Vector long multiply by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_lane_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull, LANE = 1))]
@@ -34156,7 +34156,7 @@ pub fn vmull_lane_s16<const LANE: i32>(a: int16x4_t, b: int16x4_t) -> int32x4_t
 }
 #[doc = "Vector long multiply by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_laneq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull, LANE = 1))]
@@ -34184,7 +34184,7 @@ pub fn vmull_laneq_s16<const LANE: i32>(a: int16x4_t, b: int16x8_t) -> int32x4_t
 }
 #[doc = "Vector long multiply by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_lane_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull, LANE = 1))]
@@ -34207,7 +34207,7 @@ pub fn vmull_lane_s32<const LANE: i32>(a: int32x2_t, b: int32x2_t) -> int64x2_t
 }
 #[doc = "Vector long multiply by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_laneq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull, LANE = 1))]
@@ -34230,7 +34230,7 @@ pub fn vmull_laneq_s32<const LANE: i32>(a: int32x2_t, b: int32x4_t) -> int64x2_t
 }
 #[doc = "Vector long multiply by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_lane_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull, LANE = 1))]
@@ -34258,7 +34258,7 @@ pub fn vmull_lane_u16<const LANE: i32>(a: uint16x4_t, b: uint16x4_t) -> uint32x4
 }
 #[doc = "Vector long multiply by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_laneq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull, LANE = 1))]
@@ -34286,7 +34286,7 @@ pub fn vmull_laneq_u16<const LANE: i32>(a: uint16x4_t, b: uint16x8_t) -> uint32x
 }
 #[doc = "Vector long multiply by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_lane_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull, LANE = 1))]
@@ -34309,7 +34309,7 @@ pub fn vmull_lane_u32<const LANE: i32>(a: uint32x2_t, b: uint32x2_t) -> uint64x2
 }
 #[doc = "Vector long multiply by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_laneq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull, LANE = 1))]
@@ -34332,7 +34332,7 @@ pub fn vmull_laneq_u32<const LANE: i32>(a: uint32x2_t, b: uint32x4_t) -> uint64x
 }
 #[doc = "Vector long multiply with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull))]
@@ -34353,7 +34353,7 @@ pub fn vmull_n_s16(a: int16x4_t, b: i16) -> int32x4_t {
 }
 #[doc = "Vector long multiply with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull))]
@@ -34374,7 +34374,7 @@ pub fn vmull_n_s32(a: int32x2_t, b: i32) -> int64x2_t {
 }
 #[doc = "Vector long multiply with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_n_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull))]
@@ -34395,7 +34395,7 @@ pub fn vmull_n_u16(a: uint16x4_t, b: u16) -> uint32x4_t {
 }
 #[doc = "Vector long multiply with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_n_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull))]
@@ -34416,7 +34416,7 @@ pub fn vmull_n_u32(a: uint32x2_t, b: u32) -> uint64x2_t {
 }
 #[doc = "Polynomial multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmull.p8"))]
@@ -34445,7 +34445,7 @@ pub fn vmull_p8(a: poly8x8_t, b: poly8x8_t) -> poly16x8_t {
 }
 #[doc = "Signed multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmull.s16"))]
@@ -34474,7 +34474,7 @@ pub fn vmull_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t {
 }
 #[doc = "Signed multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmull.s32"))]
@@ -34503,7 +34503,7 @@ pub fn vmull_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t {
 }
 #[doc = "Signed multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmull.s8"))]
@@ -34532,7 +34532,7 @@ pub fn vmull_s8(a: int8x8_t, b: int8x8_t) -> int16x8_t {
 }
 #[doc = "Unsigned multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmull.u8"))]
@@ -34561,7 +34561,7 @@ pub fn vmull_u8(a: uint8x8_t, b: uint8x8_t) -> uint16x8_t {
 }
 #[doc = "Unsigned multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmull.u16"))]
@@ -34590,7 +34590,7 @@ pub fn vmull_u16(a: uint16x4_t, b: uint16x4_t) -> uint32x4_t {
 }
 #[doc = "Unsigned multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmull.u32"))]
@@ -34619,7 +34619,7 @@ pub fn vmull_u32(a: uint32x2_t, b: uint32x2_t) -> uint64x2_t {
 }
 #[doc = "Vector bitwise not."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvn_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
@@ -34641,7 +34641,7 @@ pub fn vmvn_p8(a: poly8x8_t) -> poly8x8_t {
 }
 #[doc = "Vector bitwise not."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvn_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
@@ -34663,7 +34663,7 @@ pub fn vmvn_s16(a: int16x4_t) -> int16x4_t {
 }
 #[doc = "Vector bitwise not."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvn_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
@@ -34685,7 +34685,7 @@ pub fn vmvn_s32(a: int32x2_t) -> int32x2_t {
 }
 #[doc = "Vector bitwise not."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvn_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
@@ -34707,7 +34707,7 @@ pub fn vmvn_s8(a: int8x8_t) -> int8x8_t {
 }
 #[doc = "Vector bitwise not."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvn_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
@@ -34729,7 +34729,7 @@ pub fn vmvn_u16(a: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Vector bitwise not."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvn_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
@@ -34751,7 +34751,7 @@ pub fn vmvn_u32(a: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Vector bitwise not."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvn_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
@@ -34773,7 +34773,7 @@ pub fn vmvn_u8(a: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Vector bitwise not."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvnq_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
@@ -34795,7 +34795,7 @@ pub fn vmvnq_p8(a: poly8x16_t) -> poly8x16_t {
 }
 #[doc = "Vector bitwise not."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvnq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
@@ -34817,7 +34817,7 @@ pub fn vmvnq_s16(a: int16x8_t) -> int16x8_t {
 }
 #[doc = "Vector bitwise not."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvnq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
@@ -34839,7 +34839,7 @@ pub fn vmvnq_s32(a: int32x4_t) -> int32x4_t {
 }
 #[doc = "Vector bitwise not."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvnq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
@@ -34861,7 +34861,7 @@ pub fn vmvnq_s8(a: int8x16_t) -> int8x16_t {
 }
 #[doc = "Vector bitwise not."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvnq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
@@ -34883,7 +34883,7 @@ pub fn vmvnq_u16(a: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Vector bitwise not."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvnq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
@@ -34905,7 +34905,7 @@ pub fn vmvnq_u32(a: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Vector bitwise not."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvnq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmvn))]
@@ -34927,7 +34927,7 @@ pub fn vmvnq_u8(a: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vneg_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.f16"))]
 #[cfg_attr(
@@ -34949,7 +34949,7 @@ pub fn vneg_f16(a: float16x4_t) -> float16x4_t {
 }
 #[doc = "Negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegq_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.f16"))]
 #[cfg_attr(
@@ -34971,7 +34971,7 @@ pub fn vnegq_f16(a: float16x8_t) -> float16x8_t {
 }
 #[doc = "Negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vneg_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.f32"))]
@@ -34992,7 +34992,7 @@ pub fn vneg_f32(a: float32x2_t) -> float32x2_t {
 }
 #[doc = "Negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.f32"))]
@@ -35013,7 +35013,7 @@ pub fn vnegq_f32(a: float32x4_t) -> float32x4_t {
 }
 #[doc = "Negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vneg_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.s8"))]
@@ -35034,7 +35034,7 @@ pub fn vneg_s8(a: int8x8_t) -> int8x8_t {
 }
 #[doc = "Negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.s8"))]
@@ -35055,7 +35055,7 @@ pub fn vnegq_s8(a: int8x16_t) -> int8x16_t {
 }
 #[doc = "Negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vneg_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.s16"))]
@@ -35076,7 +35076,7 @@ pub fn vneg_s16(a: int16x4_t) -> int16x4_t {
 }
 #[doc = "Negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.s16"))]
@@ -35097,7 +35097,7 @@ pub fn vnegq_s16(a: int16x8_t) -> int16x8_t {
 }
 #[doc = "Negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vneg_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.s32"))]
@@ -35118,7 +35118,7 @@ pub fn vneg_s32(a: int32x2_t) -> int32x2_t {
 }
 #[doc = "Negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.s32"))]
@@ -35139,7 +35139,7 @@ pub fn vnegq_s32(a: int32x4_t) -> int32x4_t {
 }
 #[doc = "Vector bitwise inclusive OR NOT"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorn_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))]
@@ -35161,7 +35161,7 @@ pub fn vorn_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Vector bitwise inclusive OR NOT"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorn_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))]
@@ -35183,7 +35183,7 @@ pub fn vorn_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Vector bitwise inclusive OR NOT"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorn_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))]
@@ -35205,7 +35205,7 @@ pub fn vorn_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t {
 }
 #[doc = "Vector bitwise inclusive OR NOT"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorn_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))]
@@ -35227,7 +35227,7 @@ pub fn vorn_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Vector bitwise inclusive OR NOT"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vornq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))]
@@ -35249,7 +35249,7 @@ pub fn vornq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Vector bitwise inclusive OR NOT"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vornq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))]
@@ -35271,7 +35271,7 @@ pub fn vornq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Vector bitwise inclusive OR NOT"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vornq_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))]
@@ -35293,7 +35293,7 @@ pub fn vornq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
 }
 #[doc = "Vector bitwise inclusive OR NOT"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vornq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))]
@@ -35315,7 +35315,7 @@ pub fn vornq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Vector bitwise inclusive OR NOT"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorn_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))]
@@ -35337,7 +35337,7 @@ pub fn vorn_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Vector bitwise inclusive OR NOT"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorn_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))]
@@ -35359,7 +35359,7 @@ pub fn vorn_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Vector bitwise inclusive OR NOT"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorn_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))]
@@ -35381,7 +35381,7 @@ pub fn vorn_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
 }
 #[doc = "Vector bitwise inclusive OR NOT"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorn_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))]
@@ -35403,7 +35403,7 @@ pub fn vorn_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Vector bitwise inclusive OR NOT"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vornq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))]
@@ -35425,7 +35425,7 @@ pub fn vornq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Vector bitwise inclusive OR NOT"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vornq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))]
@@ -35447,7 +35447,7 @@ pub fn vornq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Vector bitwise inclusive OR NOT"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vornq_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))]
@@ -35469,7 +35469,7 @@ pub fn vornq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Vector bitwise inclusive OR NOT"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vornq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorn))]
@@ -35491,7 +35491,7 @@ pub fn vornq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Vector bitwise or (immediate, inclusive)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
@@ -35512,7 +35512,7 @@ pub fn vorr_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Vector bitwise or (immediate, inclusive)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
@@ -35533,7 +35533,7 @@ pub fn vorrq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Vector bitwise or (immediate, inclusive)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
@@ -35554,7 +35554,7 @@ pub fn vorr_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Vector bitwise or (immediate, inclusive)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
@@ -35575,7 +35575,7 @@ pub fn vorrq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Vector bitwise or (immediate, inclusive)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
@@ -35596,7 +35596,7 @@ pub fn vorr_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Vector bitwise or (immediate, inclusive)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
@@ -35617,7 +35617,7 @@ pub fn vorrq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Vector bitwise or (immediate, inclusive)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
@@ -35638,7 +35638,7 @@ pub fn vorr_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t {
 }
 #[doc = "Vector bitwise or (immediate, inclusive)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
@@ -35659,7 +35659,7 @@ pub fn vorrq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
 }
 #[doc = "Vector bitwise or (immediate, inclusive)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
@@ -35680,7 +35680,7 @@ pub fn vorr_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Vector bitwise or (immediate, inclusive)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
@@ -35701,7 +35701,7 @@ pub fn vorrq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Vector bitwise or (immediate, inclusive)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
@@ -35722,7 +35722,7 @@ pub fn vorr_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Vector bitwise or (immediate, inclusive)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
@@ -35743,7 +35743,7 @@ pub fn vorrq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Vector bitwise or (immediate, inclusive)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
@@ -35764,7 +35764,7 @@ pub fn vorr_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Vector bitwise or (immediate, inclusive)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
@@ -35785,7 +35785,7 @@ pub fn vorrq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Vector bitwise or (immediate, inclusive)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
@@ -35806,7 +35806,7 @@ pub fn vorr_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
 }
 #[doc = "Vector bitwise or (immediate, inclusive)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
@@ -35827,7 +35827,7 @@ pub fn vorrq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Signed Add and Accumulate Long Pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadal_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.s8"))]
@@ -35857,7 +35857,7 @@ pub fn vpadal_s8(a: int16x4_t, b: int8x8_t) -> int16x4_t {
 }
 #[doc = "Signed Add and Accumulate Long Pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadalq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.s8"))]
@@ -35887,7 +35887,7 @@ pub fn vpadalq_s8(a: int16x8_t, b: int8x16_t) -> int16x8_t {
 }
 #[doc = "Signed Add and Accumulate Long Pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadal_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.s16"))]
@@ -35917,7 +35917,7 @@ pub fn vpadal_s16(a: int32x2_t, b: int16x4_t) -> int32x2_t {
 }
 #[doc = "Signed Add and Accumulate Long Pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadalq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.s16"))]
@@ -35947,7 +35947,7 @@ pub fn vpadalq_s16(a: int32x4_t, b: int16x8_t) -> int32x4_t {
 }
 #[doc = "Signed Add and Accumulate Long Pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadal_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.s32"))]
@@ -35977,7 +35977,7 @@ pub fn vpadal_s32(a: int64x1_t, b: int32x2_t) -> int64x1_t {
 }
 #[doc = "Signed Add and Accumulate Long Pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadalq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.s32"))]
@@ -36007,7 +36007,7 @@ pub fn vpadalq_s32(a: int64x2_t, b: int32x4_t) -> int64x2_t {
 }
 #[doc = "Unsigned Add and Accumulate Long Pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadal_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.u8"))]
@@ -36037,7 +36037,7 @@ pub fn vpadal_u8(a: uint16x4_t, b: uint8x8_t) -> uint16x4_t {
 }
 #[doc = "Unsigned Add and Accumulate Long Pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadalq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.u8"))]
@@ -36067,7 +36067,7 @@ pub fn vpadalq_u8(a: uint16x8_t, b: uint8x16_t) -> uint16x8_t {
 }
 #[doc = "Unsigned Add and Accumulate Long Pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadal_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.u16"))]
@@ -36097,7 +36097,7 @@ pub fn vpadal_u16(a: uint32x2_t, b: uint16x4_t) -> uint32x2_t {
 }
 #[doc = "Unsigned Add and Accumulate Long Pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadalq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.u16"))]
@@ -36127,7 +36127,7 @@ pub fn vpadalq_u16(a: uint32x4_t, b: uint16x8_t) -> uint32x4_t {
 }
 #[doc = "Unsigned Add and Accumulate Long Pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadal_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.u32"))]
@@ -36157,7 +36157,7 @@ pub fn vpadal_u32(a: uint64x1_t, b: uint32x2_t) -> uint64x1_t {
 }
 #[doc = "Unsigned Add and Accumulate Long Pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadalq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.u32"))]
@@ -36187,7 +36187,7 @@ pub fn vpadalq_u32(a: uint64x2_t, b: uint32x4_t) -> uint64x2_t {
 }
 #[doc = "Floating-point add pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))]
 #[cfg_attr(
@@ -36217,7 +36217,7 @@ pub fn vpadd_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 }
 #[doc = "Floating-point add pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))]
@@ -36246,7 +36246,7 @@ pub fn vpadd_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
 }
 #[doc = "Add pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))]
@@ -36275,7 +36275,7 @@ pub fn vpadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Add pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))]
@@ -36304,7 +36304,7 @@ pub fn vpadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Add pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))]
@@ -36333,7 +36333,7 @@ pub fn vpadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Add pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -36355,7 +36355,7 @@ pub fn vpadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Add pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -36382,7 +36382,7 @@ pub fn vpadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Add pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -36404,7 +36404,7 @@ pub fn vpadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Add pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -36431,7 +36431,7 @@ pub fn vpadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Add pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -36453,7 +36453,7 @@ pub fn vpadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Add pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -36480,7 +36480,7 @@ pub fn vpadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Signed Add and Accumulate Long Pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddl_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.s8"))]
@@ -36509,7 +36509,7 @@ pub fn vpaddl_s8(a: int8x8_t) -> int16x4_t {
 }
 #[doc = "Signed Add and Accumulate Long Pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddlq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.s8"))]
@@ -36538,7 +36538,7 @@ pub fn vpaddlq_s8(a: int8x16_t) -> int16x8_t {
 }
 #[doc = "Signed Add and Accumulate Long Pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddl_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.s16"))]
@@ -36567,7 +36567,7 @@ pub fn vpaddl_s16(a: int16x4_t) -> int32x2_t {
 }
 #[doc = "Signed Add and Accumulate Long Pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddlq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.s16"))]
@@ -36596,7 +36596,7 @@ pub fn vpaddlq_s16(a: int16x8_t) -> int32x4_t {
 }
 #[doc = "Signed Add and Accumulate Long Pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddl_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.s32"))]
@@ -36625,7 +36625,7 @@ pub fn vpaddl_s32(a: int32x2_t) -> int64x1_t {
 }
 #[doc = "Signed Add and Accumulate Long Pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddlq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.s32"))]
@@ -36654,7 +36654,7 @@ pub fn vpaddlq_s32(a: int32x4_t) -> int64x2_t {
 }
 #[doc = "Unsigned Add and Accumulate Long Pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddl_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.u8"))]
@@ -36683,7 +36683,7 @@ pub fn vpaddl_u8(a: uint8x8_t) -> uint16x4_t {
 }
 #[doc = "Unsigned Add and Accumulate Long Pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddlq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.u8"))]
@@ -36712,7 +36712,7 @@ pub fn vpaddlq_u8(a: uint8x16_t) -> uint16x8_t {
 }
 #[doc = "Unsigned Add and Accumulate Long Pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddl_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.u16"))]
@@ -36741,7 +36741,7 @@ pub fn vpaddl_u16(a: uint16x4_t) -> uint32x2_t {
 }
 #[doc = "Unsigned Add and Accumulate Long Pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddlq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.u16"))]
@@ -36770,7 +36770,7 @@ pub fn vpaddlq_u16(a: uint16x8_t) -> uint32x4_t {
 }
 #[doc = "Unsigned Add and Accumulate Long Pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddl_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.u32"))]
@@ -36799,7 +36799,7 @@ pub fn vpaddl_u32(a: uint32x2_t) -> uint64x1_t {
 }
 #[doc = "Unsigned Add and Accumulate Long Pairwise."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddlq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpaddl.u32"))]
@@ -36828,7 +36828,7 @@ pub fn vpaddlq_u32(a: uint32x4_t) -> uint64x2_t {
 }
 #[doc = "Folding maximum of adjacent pairs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmax))]
@@ -36857,7 +36857,7 @@ pub fn vpmax_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
 }
 #[doc = "Folding maximum of adjacent pairs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmax))]
@@ -36886,7 +36886,7 @@ pub fn vpmax_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Folding maximum of adjacent pairs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmax))]
@@ -36915,7 +36915,7 @@ pub fn vpmax_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Folding maximum of adjacent pairs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmax))]
@@ -36944,7 +36944,7 @@ pub fn vpmax_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Folding maximum of adjacent pairs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmax))]
@@ -36973,7 +36973,7 @@ pub fn vpmax_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Folding maximum of adjacent pairs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmax))]
@@ -37002,7 +37002,7 @@ pub fn vpmax_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Folding maximum of adjacent pairs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmax))]
@@ -37031,7 +37031,7 @@ pub fn vpmax_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Folding minimum of adjacent pairs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmin))]
@@ -37060,7 +37060,7 @@ pub fn vpmin_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
 }
 #[doc = "Folding minimum of adjacent pairs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmin))]
@@ -37089,7 +37089,7 @@ pub fn vpmin_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Folding minimum of adjacent pairs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmin))]
@@ -37118,7 +37118,7 @@ pub fn vpmin_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Folding minimum of adjacent pairs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmin))]
@@ -37147,7 +37147,7 @@ pub fn vpmin_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Folding minimum of adjacent pairs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmin))]
@@ -37176,7 +37176,7 @@ pub fn vpmin_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Folding minimum of adjacent pairs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmin))]
@@ -37205,7 +37205,7 @@ pub fn vpmin_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Folding minimum of adjacent pairs"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpmin))]
@@ -37234,7 +37234,7 @@ pub fn vpmin_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Signed saturating Absolute value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabs_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqabs.s8"))]
@@ -37263,7 +37263,7 @@ pub fn vqabs_s8(a: int8x8_t) -> int8x8_t {
 }
 #[doc = "Signed saturating Absolute value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabsq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqabs.s8"))]
@@ -37292,7 +37292,7 @@ pub fn vqabsq_s8(a: int8x16_t) -> int8x16_t {
 }
 #[doc = "Signed saturating Absolute value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabs_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqabs.s16"))]
@@ -37321,7 +37321,7 @@ pub fn vqabs_s16(a: int16x4_t) -> int16x4_t {
 }
 #[doc = "Signed saturating Absolute value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabsq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqabs.s16"))]
@@ -37350,7 +37350,7 @@ pub fn vqabsq_s16(a: int16x8_t) -> int16x8_t {
 }
 #[doc = "Signed saturating Absolute value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabs_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqabs.s32"))]
@@ -37379,7 +37379,7 @@ pub fn vqabs_s32(a: int32x2_t) -> int32x2_t {
 }
 #[doc = "Signed saturating Absolute value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabsq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqabs.s32"))]
@@ -37408,7 +37408,7 @@ pub fn vqabsq_s32(a: int32x4_t) -> int32x4_t {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.s8"))]
@@ -37429,7 +37429,7 @@ pub fn vqadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.s8"))]
@@ -37450,7 +37450,7 @@ pub fn vqaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.s16"))]
@@ -37471,7 +37471,7 @@ pub fn vqadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.s16"))]
@@ -37492,7 +37492,7 @@ pub fn vqaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.s32"))]
@@ -37513,7 +37513,7 @@ pub fn vqadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.s32"))]
@@ -37534,7 +37534,7 @@ pub fn vqaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.s64"))]
@@ -37555,7 +37555,7 @@ pub fn vqadd_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.s64"))]
@@ -37576,7 +37576,7 @@ pub fn vqaddq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.u8"))]
@@ -37597,7 +37597,7 @@ pub fn vqadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.u8"))]
@@ -37618,7 +37618,7 @@ pub fn vqaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.u16"))]
@@ -37639,7 +37639,7 @@ pub fn vqadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.u16"))]
@@ -37660,7 +37660,7 @@ pub fn vqaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.u32"))]
@@ -37681,7 +37681,7 @@ pub fn vqadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.u32"))]
@@ -37702,7 +37702,7 @@ pub fn vqaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.u64"))]
@@ -37723,7 +37723,7 @@ pub fn vqadd_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
 }
 #[doc = "Saturating add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.u64"))]
@@ -37744,7 +37744,7 @@ pub fn vqaddq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Vector widening saturating doubling multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_lane_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlal, N = 2))]
@@ -37767,7 +37767,7 @@ pub fn vqdmlal_lane_s16<const N: i32>(a: int32x4_t, b: int16x4_t, c: int16x4_t)
 }
 #[doc = "Vector widening saturating doubling multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_lane_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlal, N = 1))]
@@ -37790,7 +37790,7 @@ pub fn vqdmlal_lane_s32<const N: i32>(a: int64x2_t, b: int32x2_t, c: int32x2_t)
 }
 #[doc = "Vector widening saturating doubling multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlal))]
@@ -37811,7 +37811,7 @@ pub fn vqdmlal_n_s16(a: int32x4_t, b: int16x4_t, c: i16) -> int32x4_t {
 }
 #[doc = "Vector widening saturating doubling multiply accumulate with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlal))]
@@ -37832,7 +37832,7 @@ pub fn vqdmlal_n_s32(a: int64x2_t, b: int32x2_t, c: i32) -> int64x2_t {
 }
 #[doc = "Signed saturating doubling multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlal))]
@@ -37853,7 +37853,7 @@ pub fn vqdmlal_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t {
 }
 #[doc = "Signed saturating doubling multiply-add long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlal))]
@@ -37874,7 +37874,7 @@ pub fn vqdmlal_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t {
 }
 #[doc = "Vector widening saturating doubling multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_lane_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlsl, N = 2))]
@@ -37897,7 +37897,7 @@ pub fn vqdmlsl_lane_s16<const N: i32>(a: int32x4_t, b: int16x4_t, c: int16x4_t)
 }
 #[doc = "Vector widening saturating doubling multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_lane_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlsl, N = 1))]
@@ -37920,7 +37920,7 @@ pub fn vqdmlsl_lane_s32<const N: i32>(a: int64x2_t, b: int32x2_t, c: int32x2_t)
 }
 #[doc = "Vector widening saturating doubling multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlsl))]
@@ -37941,7 +37941,7 @@ pub fn vqdmlsl_n_s16(a: int32x4_t, b: int16x4_t, c: i16) -> int32x4_t {
 }
 #[doc = "Vector widening saturating doubling multiply subtract with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlsl))]
@@ -37962,7 +37962,7 @@ pub fn vqdmlsl_n_s32(a: int64x2_t, b: int32x2_t, c: i32) -> int64x2_t {
 }
 #[doc = "Signed saturating doubling multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlsl))]
@@ -37983,7 +37983,7 @@ pub fn vqdmlsl_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t {
 }
 #[doc = "Signed saturating doubling multiply-subtract long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlsl))]
@@ -38004,7 +38004,7 @@ pub fn vqdmlsl_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t {
 }
 #[doc = "Vector saturating doubling multiply high by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_laneq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh, LANE = 0))]
@@ -38027,7 +38027,7 @@ pub fn vqdmulh_laneq_s16<const LANE: i32>(a: int16x4_t, b: int16x8_t) -> int16x4
 }
 #[doc = "Vector saturating doubling multiply high by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_laneq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh, LANE = 0))]
@@ -38050,7 +38050,7 @@ pub fn vqdmulhq_laneq_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t) -> int16x
 }
 #[doc = "Vector saturating doubling multiply high by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_laneq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh, LANE = 0))]
@@ -38073,7 +38073,7 @@ pub fn vqdmulh_laneq_s32<const LANE: i32>(a: int32x2_t, b: int32x4_t) -> int32x2
 }
 #[doc = "Vector saturating doubling multiply high by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_laneq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh, LANE = 0))]
@@ -38096,7 +38096,7 @@ pub fn vqdmulhq_laneq_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t) -> int32x
 }
 #[doc = "Vector saturating doubling multiply high with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh))]
@@ -38118,7 +38118,7 @@ pub fn vqdmulh_n_s16(a: int16x4_t, b: i16) -> int16x4_t {
 }
 #[doc = "Vector saturating doubling multiply high with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh))]
@@ -38140,7 +38140,7 @@ pub fn vqdmulhq_n_s16(a: int16x8_t, b: i16) -> int16x8_t {
 }
 #[doc = "Vector saturating doubling multiply high with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh))]
@@ -38162,7 +38162,7 @@ pub fn vqdmulh_n_s32(a: int32x2_t, b: i32) -> int32x2_t {
 }
 #[doc = "Vector saturating doubling multiply high with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh))]
@@ -38184,7 +38184,7 @@ pub fn vqdmulhq_n_s32(a: int32x4_t, b: i32) -> int32x4_t {
 }
 #[doc = "Signed saturating doubling multiply returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh))]
@@ -38213,7 +38213,7 @@ pub fn vqdmulh_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Signed saturating doubling multiply returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh))]
@@ -38242,7 +38242,7 @@ pub fn vqdmulhq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Signed saturating doubling multiply returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh))]
@@ -38271,7 +38271,7 @@ pub fn vqdmulh_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Signed saturating doubling multiply returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh))]
@@ -38300,7 +38300,7 @@ pub fn vqdmulhq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Vector saturating doubling long multiply by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_lane_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmull, N = 2))]
@@ -38326,7 +38326,7 @@ pub fn vqdmull_lane_s16<const N: i32>(a: int16x4_t, b: int16x4_t) -> int32x4_t {
 }
 #[doc = "Vector saturating doubling long multiply by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_lane_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmull, N = 1))]
@@ -38352,7 +38352,7 @@ pub fn vqdmull_lane_s32<const N: i32>(a: int32x2_t, b: int32x2_t) -> int64x2_t {
 }
 #[doc = "Vector saturating doubling long multiply with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmull))]
@@ -38373,7 +38373,7 @@ pub fn vqdmull_n_s16(a: int16x4_t, b: i16) -> int32x4_t {
 }
 #[doc = "Vector saturating doubling long multiply with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmull))]
@@ -38394,7 +38394,7 @@ pub fn vqdmull_n_s32(a: int32x2_t, b: i32) -> int64x2_t {
 }
 #[doc = "Signed saturating doubling multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmull))]
@@ -38423,7 +38423,7 @@ pub fn vqdmull_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t {
 }
 #[doc = "Signed saturating doubling multiply long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmull))]
@@ -38452,7 +38452,7 @@ pub fn vqdmull_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t {
 }
 #[doc = "Signed saturating extract narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovn))]
@@ -38481,7 +38481,7 @@ pub fn vqmovn_s16(a: int16x8_t) -> int8x8_t {
 }
 #[doc = "Signed saturating extract narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovn))]
@@ -38510,7 +38510,7 @@ pub fn vqmovn_s32(a: int32x4_t) -> int16x4_t {
 }
 #[doc = "Signed saturating extract narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovn))]
@@ -38539,7 +38539,7 @@ pub fn vqmovn_s64(a: int64x2_t) -> int32x2_t {
 }
 #[doc = "Unsigned saturating extract narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovn))]
@@ -38568,7 +38568,7 @@ pub fn vqmovn_u16(a: uint16x8_t) -> uint8x8_t {
 }
 #[doc = "Unsigned saturating extract narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovn))]
@@ -38597,7 +38597,7 @@ pub fn vqmovn_u32(a: uint32x4_t) -> uint16x4_t {
 }
 #[doc = "Unsigned saturating extract narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovn))]
@@ -38626,7 +38626,7 @@ pub fn vqmovn_u64(a: uint64x2_t) -> uint32x2_t {
 }
 #[doc = "Signed saturating extract unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovun_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovun))]
@@ -38655,7 +38655,7 @@ pub fn vqmovun_s16(a: int16x8_t) -> uint8x8_t {
 }
 #[doc = "Signed saturating extract unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovun_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovun))]
@@ -38684,7 +38684,7 @@ pub fn vqmovun_s32(a: int32x4_t) -> uint16x4_t {
 }
 #[doc = "Signed saturating extract unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovun_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovun))]
@@ -38713,7 +38713,7 @@ pub fn vqmovun_s64(a: int64x2_t) -> uint32x2_t {
 }
 #[doc = "Signed saturating negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqneg_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqneg.s8"))]
@@ -38742,7 +38742,7 @@ pub fn vqneg_s8(a: int8x8_t) -> int8x8_t {
 }
 #[doc = "Signed saturating negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqnegq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqneg.s8"))]
@@ -38771,7 +38771,7 @@ pub fn vqnegq_s8(a: int8x16_t) -> int8x16_t {
 }
 #[doc = "Signed saturating negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqneg_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqneg.s16"))]
@@ -38800,7 +38800,7 @@ pub fn vqneg_s16(a: int16x4_t) -> int16x4_t {
 }
 #[doc = "Signed saturating negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqnegq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqneg.s16"))]
@@ -38829,7 +38829,7 @@ pub fn vqnegq_s16(a: int16x8_t) -> int16x8_t {
 }
 #[doc = "Signed saturating negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqneg_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqneg.s32"))]
@@ -38858,7 +38858,7 @@ pub fn vqneg_s32(a: int32x2_t) -> int32x2_t {
 }
 #[doc = "Signed saturating negate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqnegq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqneg.s32"))]
@@ -38887,7 +38887,7 @@ pub fn vqnegq_s32(a: int32x4_t) -> int32x4_t {
 }
 #[doc = "Vector rounding saturating doubling multiply high by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_lane_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh, LANE = 1))]
@@ -38914,7 +38914,7 @@ pub fn vqrdmulh_lane_s16<const LANE: i32>(a: int16x4_t, b: int16x4_t) -> int16x4
 }
 #[doc = "Vector rounding saturating doubling multiply high by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_lane_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh, LANE = 1))]
@@ -38940,7 +38940,7 @@ pub fn vqrdmulh_lane_s32<const LANE: i32>(a: int32x2_t, b: int32x2_t) -> int32x2
 }
 #[doc = "Vector rounding saturating doubling multiply high by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_laneq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh, LANE = 1))]
@@ -38967,7 +38967,7 @@ pub fn vqrdmulh_laneq_s16<const LANE: i32>(a: int16x4_t, b: int16x8_t) -> int16x
 }
 #[doc = "Vector rounding saturating doubling multiply high by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_laneq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh, LANE = 1))]
@@ -38993,7 +38993,7 @@ pub fn vqrdmulh_laneq_s32<const LANE: i32>(a: int32x2_t, b: int32x4_t) -> int32x
 }
 #[doc = "Vector rounding saturating doubling multiply high by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_lane_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh, LANE = 1))]
@@ -39032,7 +39032,7 @@ pub fn vqrdmulhq_lane_s16<const LANE: i32>(a: int16x8_t, b: int16x4_t) -> int16x
 }
 #[doc = "Vector rounding saturating doubling multiply high by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_lane_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh, LANE = 1))]
@@ -39059,7 +39059,7 @@ pub fn vqrdmulhq_lane_s32<const LANE: i32>(a: int32x4_t, b: int32x2_t) -> int32x
 }
 #[doc = "Vector rounding saturating doubling multiply high by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_laneq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh, LANE = 1))]
@@ -39098,7 +39098,7 @@ pub fn vqrdmulhq_laneq_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t) -> int16
 }
 #[doc = "Vector rounding saturating doubling multiply high by scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_laneq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh, LANE = 1))]
@@ -39125,7 +39125,7 @@ pub fn vqrdmulhq_laneq_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t) -> int32
 }
 #[doc = "Vector saturating rounding doubling multiply high with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh))]
@@ -39146,7 +39146,7 @@ pub fn vqrdmulh_n_s16(a: int16x4_t, b: i16) -> int16x4_t {
 }
 #[doc = "Vector saturating rounding doubling multiply high with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh))]
@@ -39167,7 +39167,7 @@ pub fn vqrdmulhq_n_s16(a: int16x8_t, b: i16) -> int16x8_t {
 }
 #[doc = "Vector saturating rounding doubling multiply high with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh))]
@@ -39188,7 +39188,7 @@ pub fn vqrdmulh_n_s32(a: int32x2_t, b: i32) -> int32x2_t {
 }
 #[doc = "Vector saturating rounding doubling multiply high with scalar"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh))]
@@ -39209,7 +39209,7 @@ pub fn vqrdmulhq_n_s32(a: int32x4_t, b: i32) -> int32x4_t {
 }
 #[doc = "Signed saturating rounding doubling multiply returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh))]
@@ -39238,7 +39238,7 @@ pub fn vqrdmulh_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Signed saturating rounding doubling multiply returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh))]
@@ -39267,7 +39267,7 @@ pub fn vqrdmulhq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Signed saturating rounding doubling multiply returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh))]
@@ -39296,7 +39296,7 @@ pub fn vqrdmulh_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Signed saturating rounding doubling multiply returning high half"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh))]
@@ -39325,7 +39325,7 @@ pub fn vqrdmulhq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Signed saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
@@ -39354,7 +39354,7 @@ pub fn vqrshl_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Signed saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
@@ -39383,7 +39383,7 @@ pub fn vqrshlq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Signed saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
@@ -39412,7 +39412,7 @@ pub fn vqrshl_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Signed saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
@@ -39441,7 +39441,7 @@ pub fn vqrshlq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Signed saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
@@ -39470,7 +39470,7 @@ pub fn vqrshl_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Signed saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
@@ -39499,7 +39499,7 @@ pub fn vqrshlq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Signed saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
@@ -39528,7 +39528,7 @@ pub fn vqrshl_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t {
 }
 #[doc = "Signed saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
@@ -39557,7 +39557,7 @@ pub fn vqrshlq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
 }
 #[doc = "Unsigned signed saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
@@ -39586,7 +39586,7 @@ pub fn vqrshl_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t {
 }
 #[doc = "Unsigned signed saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
@@ -39615,7 +39615,7 @@ pub fn vqrshlq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t {
 }
 #[doc = "Unsigned signed saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
@@ -39644,7 +39644,7 @@ pub fn vqrshl_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t {
 }
 #[doc = "Unsigned signed saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
@@ -39673,7 +39673,7 @@ pub fn vqrshlq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t {
 }
 #[doc = "Unsigned signed saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
@@ -39702,7 +39702,7 @@ pub fn vqrshl_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t {
 }
 #[doc = "Unsigned signed saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
@@ -39731,7 +39731,7 @@ pub fn vqrshlq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t {
 }
 #[doc = "Unsigned signed saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
@@ -39760,7 +39760,7 @@ pub fn vqrshl_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t {
 }
 #[doc = "Unsigned signed saturating rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))]
@@ -39789,7 +39789,7 @@ pub fn vqrshlq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t {
 }
 #[doc = "Signed saturating rounded shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vqrshrn, N = 2))]
@@ -39805,7 +39805,7 @@ pub fn vqrshrn_n_s16<const N: i32>(a: int16x8_t) -> int8x8_t {
 }
 #[doc = "Signed saturating rounded shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vqrshrn, N = 2))]
@@ -39821,7 +39821,7 @@ pub fn vqrshrn_n_s32<const N: i32>(a: int32x4_t) -> int16x4_t {
 }
 #[doc = "Signed saturating rounded shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vqrshrn, N = 2))]
@@ -39837,7 +39837,7 @@ pub fn vqrshrn_n_s64<const N: i32>(a: int64x2_t) -> int32x2_t {
 }
 #[doc = "Signed saturating rounded shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(sqrshrn, N = 2))]
@@ -39856,7 +39856,7 @@ pub fn vqrshrn_n_s16<const N: i32>(a: int16x8_t) -> int8x8_t {
 }
 #[doc = "Signed saturating rounded shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(sqrshrn, N = 2))]
@@ -39875,7 +39875,7 @@ pub fn vqrshrn_n_s32<const N: i32>(a: int32x4_t) -> int16x4_t {
 }
 #[doc = "Signed saturating rounded shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(sqrshrn, N = 2))]
@@ -39894,7 +39894,7 @@ pub fn vqrshrn_n_s64<const N: i32>(a: int64x2_t) -> int32x2_t {
 }
 #[doc = "Unsigned signed saturating rounded shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vqrshrn, N = 2))]
@@ -39920,7 +39920,7 @@ pub fn vqrshrn_n_u16<const N: i32>(a: uint16x8_t) -> uint8x8_t {
 }
 #[doc = "Unsigned signed saturating rounded shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vqrshrn, N = 2))]
@@ -39941,7 +39941,7 @@ pub fn vqrshrn_n_u32<const N: i32>(a: uint32x4_t) -> uint16x4_t {
 }
 #[doc = "Unsigned signed saturating rounded shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vqrshrn, N = 2))]
@@ -39957,7 +39957,7 @@ pub fn vqrshrn_n_u64<const N: i32>(a: uint64x2_t) -> uint32x2_t {
 }
 #[doc = "Unsigned signed saturating rounded shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(uqrshrn, N = 2))]
@@ -39976,7 +39976,7 @@ pub fn vqrshrn_n_u16<const N: i32>(a: uint16x8_t) -> uint8x8_t {
 }
 #[doc = "Unsigned signed saturating rounded shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(uqrshrn, N = 2))]
@@ -39995,7 +39995,7 @@ pub fn vqrshrn_n_u32<const N: i32>(a: uint32x4_t) -> uint16x4_t {
 }
 #[doc = "Unsigned signed saturating rounded shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(uqrshrn, N = 2))]
@@ -40014,7 +40014,7 @@ pub fn vqrshrn_n_u64<const N: i32>(a: uint64x2_t) -> uint32x2_t {
 }
 #[doc = "Signed saturating rounded shift right unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_n_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vqrshrun, N = 2))]
@@ -40030,7 +40030,7 @@ pub fn vqrshrun_n_s16<const N: i32>(a: int16x8_t) -> uint8x8_t {
 }
 #[doc = "Signed saturating rounded shift right unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_n_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vqrshrun, N = 2))]
@@ -40046,7 +40046,7 @@ pub fn vqrshrun_n_s32<const N: i32>(a: int32x4_t) -> uint16x4_t {
 }
 #[doc = "Signed saturating rounded shift right unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_n_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vqrshrun, N = 2))]
@@ -40062,7 +40062,7 @@ pub fn vqrshrun_n_s64<const N: i32>(a: int64x2_t) -> uint32x2_t {
 }
 #[doc = "Signed saturating rounded shift right unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(sqrshrun, N = 2))]
@@ -40081,7 +40081,7 @@ pub fn vqrshrun_n_s16<const N: i32>(a: int16x8_t) -> uint8x8_t {
 }
 #[doc = "Signed saturating rounded shift right unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(sqrshrun, N = 2))]
@@ -40100,7 +40100,7 @@ pub fn vqrshrun_n_s32<const N: i32>(a: int32x4_t) -> uint16x4_t {
 }
 #[doc = "Signed saturating rounded shift right unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_n_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(sqrshrun, N = 2))]
@@ -40119,7 +40119,7 @@ pub fn vqrshrun_n_s64<const N: i32>(a: int64x2_t) -> uint32x2_t {
 }
 #[doc = "Signed saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
@@ -40142,7 +40142,7 @@ pub fn vqshl_n_s8<const N: i32>(a: int8x8_t) -> int8x8_t {
 }
 #[doc = "Signed saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
@@ -40165,7 +40165,7 @@ pub fn vqshlq_n_s8<const N: i32>(a: int8x16_t) -> int8x16_t {
 }
 #[doc = "Signed saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
@@ -40188,7 +40188,7 @@ pub fn vqshl_n_s16<const N: i32>(a: int16x4_t) -> int16x4_t {
 }
 #[doc = "Signed saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
@@ -40211,7 +40211,7 @@ pub fn vqshlq_n_s16<const N: i32>(a: int16x8_t) -> int16x8_t {
 }
 #[doc = "Signed saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
@@ -40234,7 +40234,7 @@ pub fn vqshl_n_s32<const N: i32>(a: int32x2_t) -> int32x2_t {
 }
 #[doc = "Signed saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
@@ -40257,7 +40257,7 @@ pub fn vqshlq_n_s32<const N: i32>(a: int32x4_t) -> int32x4_t {
 }
 #[doc = "Signed saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
@@ -40280,7 +40280,7 @@ pub fn vqshl_n_s64<const N: i32>(a: int64x1_t) -> int64x1_t {
 }
 #[doc = "Signed saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
@@ -40303,7 +40303,7 @@ pub fn vqshlq_n_s64<const N: i32>(a: int64x2_t) -> int64x2_t {
 }
 #[doc = "Unsigned saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
@@ -40326,7 +40326,7 @@ pub fn vqshl_n_u8<const N: i32>(a: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Unsigned saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
@@ -40349,7 +40349,7 @@ pub fn vqshlq_n_u8<const N: i32>(a: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Unsigned saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
@@ -40372,7 +40372,7 @@ pub fn vqshl_n_u16<const N: i32>(a: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Unsigned saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
@@ -40395,7 +40395,7 @@ pub fn vqshlq_n_u16<const N: i32>(a: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Unsigned saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
@@ -40418,7 +40418,7 @@ pub fn vqshl_n_u32<const N: i32>(a: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Unsigned saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
@@ -40441,7 +40441,7 @@ pub fn vqshlq_n_u32<const N: i32>(a: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Unsigned saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
@@ -40464,7 +40464,7 @@ pub fn vqshl_n_u64<const N: i32>(a: uint64x1_t) -> uint64x1_t {
 }
 #[doc = "Unsigned saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))]
@@ -40487,7 +40487,7 @@ pub fn vqshlq_n_u64<const N: i32>(a: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Signed saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
@@ -40516,7 +40516,7 @@ pub fn vqshl_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Signed saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
@@ -40545,7 +40545,7 @@ pub fn vqshlq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Signed saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
@@ -40574,7 +40574,7 @@ pub fn vqshl_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Signed saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
@@ -40603,7 +40603,7 @@ pub fn vqshlq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Signed saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
@@ -40632,7 +40632,7 @@ pub fn vqshl_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Signed saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
@@ -40661,7 +40661,7 @@ pub fn vqshlq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Signed saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
@@ -40690,7 +40690,7 @@ pub fn vqshl_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t {
 }
 #[doc = "Signed saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
@@ -40719,7 +40719,7 @@ pub fn vqshlq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
 }
 #[doc = "Unsigned saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
@@ -40748,7 +40748,7 @@ pub fn vqshl_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t {
 }
 #[doc = "Unsigned saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
@@ -40777,7 +40777,7 @@ pub fn vqshlq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t {
 }
 #[doc = "Unsigned saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
@@ -40806,7 +40806,7 @@ pub fn vqshl_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t {
 }
 #[doc = "Unsigned saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
@@ -40835,7 +40835,7 @@ pub fn vqshlq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t {
 }
 #[doc = "Unsigned saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
@@ -40864,7 +40864,7 @@ pub fn vqshl_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t {
 }
 #[doc = "Unsigned saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
@@ -40893,7 +40893,7 @@ pub fn vqshlq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t {
 }
 #[doc = "Unsigned saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
@@ -40922,7 +40922,7 @@ pub fn vqshl_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t {
 }
 #[doc = "Unsigned saturating shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))]
@@ -40951,7 +40951,7 @@ pub fn vqshlq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t {
 }
 #[doc = "Signed saturating shift left unsigned"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vqshlu, N = 2))]
@@ -40967,7 +40967,7 @@ pub fn vqshlu_n_s8<const N: i32>(a: int8x8_t) -> uint8x8_t {
 }
 #[doc = "Signed saturating shift left unsigned"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vqshlu, N = 2))]
@@ -40983,7 +40983,7 @@ pub fn vqshluq_n_s8<const N: i32>(a: int8x16_t) -> uint8x16_t {
 }
 #[doc = "Signed saturating shift left unsigned"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vqshlu, N = 2))]
@@ -40999,7 +40999,7 @@ pub fn vqshlu_n_s16<const N: i32>(a: int16x4_t) -> uint16x4_t {
 }
 #[doc = "Signed saturating shift left unsigned"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vqshlu, N = 2))]
@@ -41015,7 +41015,7 @@ pub fn vqshluq_n_s16<const N: i32>(a: int16x8_t) -> uint16x8_t {
 }
 #[doc = "Signed saturating shift left unsigned"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vqshlu, N = 2))]
@@ -41031,7 +41031,7 @@ pub fn vqshlu_n_s32<const N: i32>(a: int32x2_t) -> uint32x2_t {
 }
 #[doc = "Signed saturating shift left unsigned"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vqshlu, N = 2))]
@@ -41047,7 +41047,7 @@ pub fn vqshluq_n_s32<const N: i32>(a: int32x4_t) -> uint32x4_t {
 }
 #[doc = "Signed saturating shift left unsigned"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vqshlu, N = 2))]
@@ -41063,7 +41063,7 @@ pub fn vqshlu_n_s64<const N: i32>(a: int64x1_t) -> uint64x1_t {
 }
 #[doc = "Signed saturating shift left unsigned"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vqshlu, N = 2))]
@@ -41079,7 +41079,7 @@ pub fn vqshluq_n_s64<const N: i32>(a: int64x2_t) -> uint64x2_t {
 }
 #[doc = "Signed saturating shift left unsigned"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(sqshlu, N = 2))]
@@ -41098,7 +41098,7 @@ pub fn vqshlu_n_s8<const N: i32>(a: int8x8_t) -> uint8x8_t {
 }
 #[doc = "Signed saturating shift left unsigned"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(sqshlu, N = 2))]
@@ -41117,7 +41117,7 @@ pub fn vqshluq_n_s8<const N: i32>(a: int8x16_t) -> uint8x16_t {
 }
 #[doc = "Signed saturating shift left unsigned"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(sqshlu, N = 2))]
@@ -41136,7 +41136,7 @@ pub fn vqshlu_n_s16<const N: i32>(a: int16x4_t) -> uint16x4_t {
 }
 #[doc = "Signed saturating shift left unsigned"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(sqshlu, N = 2))]
@@ -41155,7 +41155,7 @@ pub fn vqshluq_n_s16<const N: i32>(a: int16x8_t) -> uint16x8_t {
 }
 #[doc = "Signed saturating shift left unsigned"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(sqshlu, N = 2))]
@@ -41174,7 +41174,7 @@ pub fn vqshlu_n_s32<const N: i32>(a: int32x2_t) -> uint32x2_t {
 }
 #[doc = "Signed saturating shift left unsigned"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(sqshlu, N = 2))]
@@ -41193,7 +41193,7 @@ pub fn vqshluq_n_s32<const N: i32>(a: int32x4_t) -> uint32x4_t {
 }
 #[doc = "Signed saturating shift left unsigned"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(sqshlu, N = 2))]
@@ -41212,7 +41212,7 @@ pub fn vqshlu_n_s64<const N: i32>(a: int64x1_t) -> uint64x1_t {
 }
 #[doc = "Signed saturating shift left unsigned"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(sqshlu, N = 2))]
@@ -41231,7 +41231,7 @@ pub fn vqshluq_n_s64<const N: i32>(a: int64x2_t) -> uint64x2_t {
 }
 #[doc = "Signed saturating shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vqshrn, N = 2))]
@@ -41247,7 +41247,7 @@ pub fn vqshrn_n_s16<const N: i32>(a: int16x8_t) -> int8x8_t {
 }
 #[doc = "Signed saturating shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vqshrn, N = 2))]
@@ -41263,7 +41263,7 @@ pub fn vqshrn_n_s32<const N: i32>(a: int32x4_t) -> int16x4_t {
 }
 #[doc = "Signed saturating shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vqshrn, N = 2))]
@@ -41279,7 +41279,7 @@ pub fn vqshrn_n_s64<const N: i32>(a: int64x2_t) -> int32x2_t {
 }
 #[doc = "Signed saturating shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(sqshrn, N = 2))]
@@ -41298,7 +41298,7 @@ pub fn vqshrn_n_s16<const N: i32>(a: int16x8_t) -> int8x8_t {
 }
 #[doc = "Signed saturating shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(sqshrn, N = 2))]
@@ -41317,7 +41317,7 @@ pub fn vqshrn_n_s32<const N: i32>(a: int32x4_t) -> int16x4_t {
 }
 #[doc = "Signed saturating shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(sqshrn, N = 2))]
@@ -41336,7 +41336,7 @@ pub fn vqshrn_n_s64<const N: i32>(a: int64x2_t) -> int32x2_t {
 }
 #[doc = "Unsigned saturating shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vqshrn, N = 2))]
@@ -41362,7 +41362,7 @@ pub fn vqshrn_n_u16<const N: i32>(a: uint16x8_t) -> uint8x8_t {
 }
 #[doc = "Unsigned saturating shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vqshrn, N = 2))]
@@ -41383,7 +41383,7 @@ pub fn vqshrn_n_u32<const N: i32>(a: uint32x4_t) -> uint16x4_t {
 }
 #[doc = "Unsigned saturating shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vqshrn, N = 2))]
@@ -41399,7 +41399,7 @@ pub fn vqshrn_n_u64<const N: i32>(a: uint64x2_t) -> uint32x2_t {
 }
 #[doc = "Unsigned saturating shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(uqshrn, N = 2))]
@@ -41418,7 +41418,7 @@ pub fn vqshrn_n_u16<const N: i32>(a: uint16x8_t) -> uint8x8_t {
 }
 #[doc = "Unsigned saturating shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(uqshrn, N = 2))]
@@ -41437,7 +41437,7 @@ pub fn vqshrn_n_u32<const N: i32>(a: uint32x4_t) -> uint16x4_t {
 }
 #[doc = "Unsigned saturating shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(uqshrn, N = 2))]
@@ -41456,7 +41456,7 @@ pub fn vqshrn_n_u64<const N: i32>(a: uint64x2_t) -> uint32x2_t {
 }
 #[doc = "Signed saturating shift right unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_n_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vqshrun, N = 2))]
@@ -41472,7 +41472,7 @@ pub fn vqshrun_n_s16<const N: i32>(a: int16x8_t) -> uint8x8_t {
 }
 #[doc = "Signed saturating shift right unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_n_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vqshrun, N = 2))]
@@ -41488,7 +41488,7 @@ pub fn vqshrun_n_s32<const N: i32>(a: int32x4_t) -> uint16x4_t {
 }
 #[doc = "Signed saturating shift right unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_n_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vqshrun, N = 2))]
@@ -41504,7 +41504,7 @@ pub fn vqshrun_n_s64<const N: i32>(a: int64x2_t) -> uint32x2_t {
 }
 #[doc = "Signed saturating shift right unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(sqshrun, N = 2))]
@@ -41523,7 +41523,7 @@ pub fn vqshrun_n_s16<const N: i32>(a: int16x8_t) -> uint8x8_t {
 }
 #[doc = "Signed saturating shift right unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(sqshrun, N = 2))]
@@ -41542,7 +41542,7 @@ pub fn vqshrun_n_s32<const N: i32>(a: int32x4_t) -> uint16x4_t {
 }
 #[doc = "Signed saturating shift right unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_n_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(sqshrun, N = 2))]
@@ -41561,7 +41561,7 @@ pub fn vqshrun_n_s64<const N: i32>(a: int64x2_t) -> uint32x2_t {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.s8"))]
@@ -41582,7 +41582,7 @@ pub fn vqsub_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.s8"))]
@@ -41603,7 +41603,7 @@ pub fn vqsubq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.s16"))]
@@ -41624,7 +41624,7 @@ pub fn vqsub_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.s16"))]
@@ -41645,7 +41645,7 @@ pub fn vqsubq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.s32"))]
@@ -41666,7 +41666,7 @@ pub fn vqsub_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.s32"))]
@@ -41687,7 +41687,7 @@ pub fn vqsubq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.s64"))]
@@ -41708,7 +41708,7 @@ pub fn vqsub_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.s64"))]
@@ -41729,7 +41729,7 @@ pub fn vqsubq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.u8"))]
@@ -41750,7 +41750,7 @@ pub fn vqsub_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.u8"))]
@@ -41771,7 +41771,7 @@ pub fn vqsubq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.u16"))]
@@ -41792,7 +41792,7 @@ pub fn vqsub_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.u16"))]
@@ -41813,7 +41813,7 @@ pub fn vqsubq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.u32"))]
@@ -41834,7 +41834,7 @@ pub fn vqsub_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.u32"))]
@@ -41855,7 +41855,7 @@ pub fn vqsubq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.u64"))]
@@ -41876,7 +41876,7 @@ pub fn vqsub_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
 }
 #[doc = "Saturating subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.u64"))]
@@ -41897,7 +41897,7 @@ pub fn vqsubq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Rounding Add returning High Narrow (high half)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_high_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i16"))]
@@ -41919,7 +41919,7 @@ pub fn vraddhn_high_s16(a: int8x8_t, b: int16x8_t, c: int16x8_t) -> int8x16_t {
 }
 #[doc = "Rounding Add returning High Narrow (high half)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_high_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i32"))]
@@ -41941,7 +41941,7 @@ pub fn vraddhn_high_s32(a: int16x4_t, b: int32x4_t, c: int32x4_t) -> int16x8_t {
 }
 #[doc = "Rounding Add returning High Narrow (high half)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_high_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i64"))]
@@ -41963,7 +41963,7 @@ pub fn vraddhn_high_s64(a: int32x2_t, b: int64x2_t, c: int64x2_t) -> int32x4_t {
 }
 #[doc = "Rounding Add returning High Narrow (high half)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_high_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i16"))]
@@ -41987,7 +41987,7 @@ pub fn vraddhn_high_u16(a: uint8x8_t, b: uint16x8_t, c: uint16x8_t) -> uint8x16_
 }
 #[doc = "Rounding Add returning High Narrow (high half)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_high_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i32"))]
@@ -42011,7 +42011,7 @@ pub fn vraddhn_high_u32(a: uint16x4_t, b: uint32x4_t, c: uint32x4_t) -> uint16x8
 }
 #[doc = "Rounding Add returning High Narrow (high half)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_high_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i64"))]
@@ -42035,7 +42035,7 @@ pub fn vraddhn_high_u64(a: uint32x2_t, b: uint64x2_t, c: uint64x2_t) -> uint32x4
 }
 #[doc = "Rounding Add returning High Narrow."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i16"))]
@@ -42064,7 +42064,7 @@ pub fn vraddhn_s16(a: int16x8_t, b: int16x8_t) -> int8x8_t {
 }
 #[doc = "Rounding Add returning High Narrow."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i32"))]
@@ -42093,7 +42093,7 @@ pub fn vraddhn_s32(a: int32x4_t, b: int32x4_t) -> int16x4_t {
 }
 #[doc = "Rounding Add returning High Narrow."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vraddhn.i64"))]
@@ -42122,7 +42122,7 @@ pub fn vraddhn_s64(a: int64x2_t, b: int64x2_t) -> int32x2_t {
 }
 #[doc = "Rounding Add returning High Narrow."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -42144,7 +42144,7 @@ pub fn vraddhn_u16(a: uint16x8_t, b: uint16x8_t) -> uint8x8_t {
 }
 #[doc = "Rounding Add returning High Narrow."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -42171,7 +42171,7 @@ pub fn vraddhn_u16(a: uint16x8_t, b: uint16x8_t) -> uint8x8_t {
 }
 #[doc = "Rounding Add returning High Narrow."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -42193,7 +42193,7 @@ pub fn vraddhn_u32(a: uint32x4_t, b: uint32x4_t) -> uint16x4_t {
 }
 #[doc = "Rounding Add returning High Narrow."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -42220,7 +42220,7 @@ pub fn vraddhn_u32(a: uint32x4_t, b: uint32x4_t) -> uint16x4_t {
 }
 #[doc = "Rounding Add returning High Narrow."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -42242,7 +42242,7 @@ pub fn vraddhn_u64(a: uint64x2_t, b: uint64x2_t) -> uint32x2_t {
 }
 #[doc = "Rounding Add returning High Narrow."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -42269,7 +42269,7 @@ pub fn vraddhn_u64(a: uint64x2_t, b: uint64x2_t) -> uint32x2_t {
 }
 #[doc = "Reciprocal estimate."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpe_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecpe))]
 #[cfg_attr(
@@ -42299,7 +42299,7 @@ pub fn vrecpe_f16(a: float16x4_t) -> float16x4_t {
 }
 #[doc = "Reciprocal estimate."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpeq_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecpe))]
 #[cfg_attr(
@@ -42329,7 +42329,7 @@ pub fn vrecpeq_f16(a: float16x8_t) -> float16x8_t {
 }
 #[doc = "Reciprocal estimate."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpe_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecpe))]
@@ -42358,7 +42358,7 @@ pub fn vrecpe_f32(a: float32x2_t) -> float32x2_t {
 }
 #[doc = "Reciprocal estimate."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpeq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecpe))]
@@ -42387,7 +42387,7 @@ pub fn vrecpeq_f32(a: float32x4_t) -> float32x4_t {
 }
 #[doc = "Unsigned reciprocal estimate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpe_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecpe))]
@@ -42416,7 +42416,7 @@ pub fn vrecpe_u32(a: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Unsigned reciprocal estimate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpeq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecpe))]
@@ -42445,7 +42445,7 @@ pub fn vrecpeq_u32(a: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Floating-point reciprocal step"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecps_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecps))]
 #[cfg_attr(
@@ -42475,7 +42475,7 @@ pub fn vrecps_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 }
 #[doc = "Floating-point reciprocal step"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpsq_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecps))]
 #[cfg_attr(
@@ -42505,7 +42505,7 @@ pub fn vrecpsq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
 }
 #[doc = "Floating-point reciprocal step"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecps_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecps))]
@@ -42534,7 +42534,7 @@ pub fn vrecps_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
 }
 #[doc = "Floating-point reciprocal step"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpsq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecps))]
@@ -42563,7 +42563,7 @@ pub fn vrecpsq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -42586,7 +42586,7 @@ pub fn vreinterpret_f32_f16(a: float16x4_t) -> float32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -42613,7 +42613,7 @@ pub fn vreinterpret_f32_f16(a: float16x4_t) -> float32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -42636,7 +42636,7 @@ pub fn vreinterpret_s8_f16(a: float16x4_t) -> int8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -42663,7 +42663,7 @@ pub fn vreinterpret_s8_f16(a: float16x4_t) -> int8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -42686,7 +42686,7 @@ pub fn vreinterpret_s16_f16(a: float16x4_t) -> int16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -42713,7 +42713,7 @@ pub fn vreinterpret_s16_f16(a: float16x4_t) -> int16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -42736,7 +42736,7 @@ pub fn vreinterpret_s32_f16(a: float16x4_t) -> int32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -42763,7 +42763,7 @@ pub fn vreinterpret_s32_f16(a: float16x4_t) -> int32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -42786,7 +42786,7 @@ pub fn vreinterpret_s64_f16(a: float16x4_t) -> int64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -42810,7 +42810,7 @@ pub fn vreinterpret_s64_f16(a: float16x4_t) -> int64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -42833,7 +42833,7 @@ pub fn vreinterpret_u8_f16(a: float16x4_t) -> uint8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -42860,7 +42860,7 @@ pub fn vreinterpret_u8_f16(a: float16x4_t) -> uint8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -42883,7 +42883,7 @@ pub fn vreinterpret_u16_f16(a: float16x4_t) -> uint16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -42910,7 +42910,7 @@ pub fn vreinterpret_u16_f16(a: float16x4_t) -> uint16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -42933,7 +42933,7 @@ pub fn vreinterpret_u32_f16(a: float16x4_t) -> uint32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -42960,7 +42960,7 @@ pub fn vreinterpret_u32_f16(a: float16x4_t) -> uint32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -42983,7 +42983,7 @@ pub fn vreinterpret_u64_f16(a: float16x4_t) -> uint64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -43007,7 +43007,7 @@ pub fn vreinterpret_u64_f16(a: float16x4_t) -> uint64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -43030,7 +43030,7 @@ pub fn vreinterpret_p8_f16(a: float16x4_t) -> poly8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -43057,7 +43057,7 @@ pub fn vreinterpret_p8_f16(a: float16x4_t) -> poly8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -43080,7 +43080,7 @@ pub fn vreinterpret_p16_f16(a: float16x4_t) -> poly16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -43107,7 +43107,7 @@ pub fn vreinterpret_p16_f16(a: float16x4_t) -> poly16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -43130,7 +43130,7 @@ pub fn vreinterpretq_f32_f16(a: float16x8_t) -> float32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -43157,7 +43157,7 @@ pub fn vreinterpretq_f32_f16(a: float16x8_t) -> float32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -43180,7 +43180,7 @@ pub fn vreinterpretq_s8_f16(a: float16x8_t) -> int8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -43211,7 +43211,7 @@ pub fn vreinterpretq_s8_f16(a: float16x8_t) -> int8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -43234,7 +43234,7 @@ pub fn vreinterpretq_s16_f16(a: float16x8_t) -> int16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -43261,7 +43261,7 @@ pub fn vreinterpretq_s16_f16(a: float16x8_t) -> int16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -43284,7 +43284,7 @@ pub fn vreinterpretq_s32_f16(a: float16x8_t) -> int32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -43311,7 +43311,7 @@ pub fn vreinterpretq_s32_f16(a: float16x8_t) -> int32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -43334,7 +43334,7 @@ pub fn vreinterpretq_s64_f16(a: float16x8_t) -> int64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -43361,7 +43361,7 @@ pub fn vreinterpretq_s64_f16(a: float16x8_t) -> int64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -43384,7 +43384,7 @@ pub fn vreinterpretq_u8_f16(a: float16x8_t) -> uint8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -43415,7 +43415,7 @@ pub fn vreinterpretq_u8_f16(a: float16x8_t) -> uint8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -43438,7 +43438,7 @@ pub fn vreinterpretq_u16_f16(a: float16x8_t) -> uint16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -43465,7 +43465,7 @@ pub fn vreinterpretq_u16_f16(a: float16x8_t) -> uint16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -43488,7 +43488,7 @@ pub fn vreinterpretq_u32_f16(a: float16x8_t) -> uint32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -43515,7 +43515,7 @@ pub fn vreinterpretq_u32_f16(a: float16x8_t) -> uint32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -43538,7 +43538,7 @@ pub fn vreinterpretq_u64_f16(a: float16x8_t) -> uint64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -43565,7 +43565,7 @@ pub fn vreinterpretq_u64_f16(a: float16x8_t) -> uint64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -43588,7 +43588,7 @@ pub fn vreinterpretq_p8_f16(a: float16x8_t) -> poly8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -43619,7 +43619,7 @@ pub fn vreinterpretq_p8_f16(a: float16x8_t) -> poly8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -43642,7 +43642,7 @@ pub fn vreinterpretq_p16_f16(a: float16x8_t) -> poly16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -43669,7 +43669,7 @@ pub fn vreinterpretq_p16_f16(a: float16x8_t) -> poly16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -43692,7 +43692,7 @@ pub fn vreinterpret_f16_f32(a: float32x2_t) -> float16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -43719,7 +43719,7 @@ pub fn vreinterpret_f16_f32(a: float32x2_t) -> float16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -43742,7 +43742,7 @@ pub fn vreinterpretq_f16_f32(a: float32x4_t) -> float16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -43769,7 +43769,7 @@ pub fn vreinterpretq_f16_f32(a: float32x4_t) -> float16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -43792,7 +43792,7 @@ pub fn vreinterpret_f16_s8(a: int8x8_t) -> float16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -43819,7 +43819,7 @@ pub fn vreinterpret_f16_s8(a: int8x8_t) -> float16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -43842,7 +43842,7 @@ pub fn vreinterpretq_f16_s8(a: int8x16_t) -> float16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -43870,7 +43870,7 @@ pub fn vreinterpretq_f16_s8(a: int8x16_t) -> float16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -43893,7 +43893,7 @@ pub fn vreinterpret_f16_s16(a: int16x4_t) -> float16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -43920,7 +43920,7 @@ pub fn vreinterpret_f16_s16(a: int16x4_t) -> float16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -43943,7 +43943,7 @@ pub fn vreinterpretq_f16_s16(a: int16x8_t) -> float16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -43970,7 +43970,7 @@ pub fn vreinterpretq_f16_s16(a: int16x8_t) -> float16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -43993,7 +43993,7 @@ pub fn vreinterpret_f16_s32(a: int32x2_t) -> float16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -44020,7 +44020,7 @@ pub fn vreinterpret_f16_s32(a: int32x2_t) -> float16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -44043,7 +44043,7 @@ pub fn vreinterpretq_f16_s32(a: int32x4_t) -> float16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -44070,7 +44070,7 @@ pub fn vreinterpretq_f16_s32(a: int32x4_t) -> float16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -44093,7 +44093,7 @@ pub fn vreinterpret_f16_s64(a: int64x1_t) -> float16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -44119,7 +44119,7 @@ pub fn vreinterpret_f16_s64(a: int64x1_t) -> float16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -44142,7 +44142,7 @@ pub fn vreinterpretq_f16_s64(a: int64x2_t) -> float16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -44169,7 +44169,7 @@ pub fn vreinterpretq_f16_s64(a: int64x2_t) -> float16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -44192,7 +44192,7 @@ pub fn vreinterpret_f16_u8(a: uint8x8_t) -> float16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -44219,7 +44219,7 @@ pub fn vreinterpret_f16_u8(a: uint8x8_t) -> float16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -44242,7 +44242,7 @@ pub fn vreinterpretq_f16_u8(a: uint8x16_t) -> float16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -44270,7 +44270,7 @@ pub fn vreinterpretq_f16_u8(a: uint8x16_t) -> float16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -44293,7 +44293,7 @@ pub fn vreinterpret_f16_u16(a: uint16x4_t) -> float16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -44320,7 +44320,7 @@ pub fn vreinterpret_f16_u16(a: uint16x4_t) -> float16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -44343,7 +44343,7 @@ pub fn vreinterpretq_f16_u16(a: uint16x8_t) -> float16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -44370,7 +44370,7 @@ pub fn vreinterpretq_f16_u16(a: uint16x8_t) -> float16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -44393,7 +44393,7 @@ pub fn vreinterpret_f16_u32(a: uint32x2_t) -> float16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -44420,7 +44420,7 @@ pub fn vreinterpret_f16_u32(a: uint32x2_t) -> float16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -44443,7 +44443,7 @@ pub fn vreinterpretq_f16_u32(a: uint32x4_t) -> float16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -44470,7 +44470,7 @@ pub fn vreinterpretq_f16_u32(a: uint32x4_t) -> float16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -44493,7 +44493,7 @@ pub fn vreinterpret_f16_u64(a: uint64x1_t) -> float16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -44519,7 +44519,7 @@ pub fn vreinterpret_f16_u64(a: uint64x1_t) -> float16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -44542,7 +44542,7 @@ pub fn vreinterpretq_f16_u64(a: uint64x2_t) -> float16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -44569,7 +44569,7 @@ pub fn vreinterpretq_f16_u64(a: uint64x2_t) -> float16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -44592,7 +44592,7 @@ pub fn vreinterpret_f16_p8(a: poly8x8_t) -> float16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -44619,7 +44619,7 @@ pub fn vreinterpret_f16_p8(a: poly8x8_t) -> float16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -44642,7 +44642,7 @@ pub fn vreinterpretq_f16_p8(a: poly8x16_t) -> float16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -44670,7 +44670,7 @@ pub fn vreinterpretq_f16_p8(a: poly8x16_t) -> float16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -44693,7 +44693,7 @@ pub fn vreinterpret_f16_p16(a: poly16x4_t) -> float16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -44720,7 +44720,7 @@ pub fn vreinterpret_f16_p16(a: poly16x4_t) -> float16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -44743,7 +44743,7 @@ pub fn vreinterpretq_f16_p16(a: poly16x8_t) -> float16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -44770,7 +44770,7 @@ pub fn vreinterpretq_f16_p16(a: poly16x8_t) -> float16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p128)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -44793,7 +44793,7 @@ pub fn vreinterpretq_f16_p128(a: p128) -> float16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p128)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -44819,7 +44819,7 @@ pub fn vreinterpretq_f16_p128(a: p128) -> float16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -44842,7 +44842,7 @@ pub fn vreinterpret_p64_f16(a: float16x4_t) -> poly64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -44866,7 +44866,7 @@ pub fn vreinterpret_p64_f16(a: float16x4_t) -> poly64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -44889,7 +44889,7 @@ pub fn vreinterpretq_p128_f16(a: float16x8_t) -> p128 {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -44913,7 +44913,7 @@ pub fn vreinterpretq_p128_f16(a: float16x8_t) -> p128 {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -44936,7 +44936,7 @@ pub fn vreinterpretq_p64_f16(a: float16x8_t) -> poly64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -44963,7 +44963,7 @@ pub fn vreinterpretq_p64_f16(a: float16x8_t) -> poly64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_p64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -44986,7 +44986,7 @@ pub fn vreinterpret_f16_p64(a: poly64x1_t) -> float16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_p64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -45012,7 +45012,7 @@ pub fn vreinterpret_f16_p64(a: poly64x1_t) -> float16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -45035,7 +45035,7 @@ pub fn vreinterpretq_f16_p64(a: poly64x2_t) -> float16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -45062,7 +45062,7 @@ pub fn vreinterpretq_f16_p64(a: poly64x2_t) -> float16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p128)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45084,7 +45084,7 @@ pub fn vreinterpretq_f32_p128(a: p128) -> float32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p128)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45109,7 +45109,7 @@ pub fn vreinterpretq_f32_p128(a: p128) -> float32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45131,7 +45131,7 @@ pub fn vreinterpret_s8_f32(a: float32x2_t) -> int8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45157,7 +45157,7 @@ pub fn vreinterpret_s8_f32(a: float32x2_t) -> int8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45179,7 +45179,7 @@ pub fn vreinterpret_s16_f32(a: float32x2_t) -> int16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45205,7 +45205,7 @@ pub fn vreinterpret_s16_f32(a: float32x2_t) -> int16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45227,7 +45227,7 @@ pub fn vreinterpret_s32_f32(a: float32x2_t) -> int32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45253,7 +45253,7 @@ pub fn vreinterpret_s32_f32(a: float32x2_t) -> int32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45275,7 +45275,7 @@ pub fn vreinterpret_s64_f32(a: float32x2_t) -> int64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45298,7 +45298,7 @@ pub fn vreinterpret_s64_f32(a: float32x2_t) -> int64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45320,7 +45320,7 @@ pub fn vreinterpret_u8_f32(a: float32x2_t) -> uint8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45346,7 +45346,7 @@ pub fn vreinterpret_u8_f32(a: float32x2_t) -> uint8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45368,7 +45368,7 @@ pub fn vreinterpret_u16_f32(a: float32x2_t) -> uint16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45394,7 +45394,7 @@ pub fn vreinterpret_u16_f32(a: float32x2_t) -> uint16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45416,7 +45416,7 @@ pub fn vreinterpret_u32_f32(a: float32x2_t) -> uint32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45442,7 +45442,7 @@ pub fn vreinterpret_u32_f32(a: float32x2_t) -> uint32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45464,7 +45464,7 @@ pub fn vreinterpret_u64_f32(a: float32x2_t) -> uint64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45487,7 +45487,7 @@ pub fn vreinterpret_u64_f32(a: float32x2_t) -> uint64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45509,7 +45509,7 @@ pub fn vreinterpret_p8_f32(a: float32x2_t) -> poly8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45535,7 +45535,7 @@ pub fn vreinterpret_p8_f32(a: float32x2_t) -> poly8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45557,7 +45557,7 @@ pub fn vreinterpret_p16_f32(a: float32x2_t) -> poly16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45583,7 +45583,7 @@ pub fn vreinterpret_p16_f32(a: float32x2_t) -> poly16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45605,7 +45605,7 @@ pub fn vreinterpretq_p128_f32(a: float32x4_t) -> p128 {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45628,7 +45628,7 @@ pub fn vreinterpretq_p128_f32(a: float32x4_t) -> p128 {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45650,7 +45650,7 @@ pub fn vreinterpretq_s8_f32(a: float32x4_t) -> int8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45680,7 +45680,7 @@ pub fn vreinterpretq_s8_f32(a: float32x4_t) -> int8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45702,7 +45702,7 @@ pub fn vreinterpretq_s16_f32(a: float32x4_t) -> int16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45728,7 +45728,7 @@ pub fn vreinterpretq_s16_f32(a: float32x4_t) -> int16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45750,7 +45750,7 @@ pub fn vreinterpretq_s32_f32(a: float32x4_t) -> int32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45776,7 +45776,7 @@ pub fn vreinterpretq_s32_f32(a: float32x4_t) -> int32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45798,7 +45798,7 @@ pub fn vreinterpretq_s64_f32(a: float32x4_t) -> int64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45824,7 +45824,7 @@ pub fn vreinterpretq_s64_f32(a: float32x4_t) -> int64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45846,7 +45846,7 @@ pub fn vreinterpretq_u8_f32(a: float32x4_t) -> uint8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45876,7 +45876,7 @@ pub fn vreinterpretq_u8_f32(a: float32x4_t) -> uint8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45898,7 +45898,7 @@ pub fn vreinterpretq_u16_f32(a: float32x4_t) -> uint16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45924,7 +45924,7 @@ pub fn vreinterpretq_u16_f32(a: float32x4_t) -> uint16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45946,7 +45946,7 @@ pub fn vreinterpretq_u32_f32(a: float32x4_t) -> uint32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45972,7 +45972,7 @@ pub fn vreinterpretq_u32_f32(a: float32x4_t) -> uint32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -45994,7 +45994,7 @@ pub fn vreinterpretq_u64_f32(a: float32x4_t) -> uint64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46020,7 +46020,7 @@ pub fn vreinterpretq_u64_f32(a: float32x4_t) -> uint64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46042,7 +46042,7 @@ pub fn vreinterpretq_p8_f32(a: float32x4_t) -> poly8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46072,7 +46072,7 @@ pub fn vreinterpretq_p8_f32(a: float32x4_t) -> poly8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46094,7 +46094,7 @@ pub fn vreinterpretq_p16_f32(a: float32x4_t) -> poly16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_f32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46120,7 +46120,7 @@ pub fn vreinterpretq_p16_f32(a: float32x4_t) -> poly16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46142,7 +46142,7 @@ pub fn vreinterpret_f32_s8(a: int8x8_t) -> float32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46168,7 +46168,7 @@ pub fn vreinterpret_f32_s8(a: int8x8_t) -> float32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46190,7 +46190,7 @@ pub fn vreinterpret_s16_s8(a: int8x8_t) -> int16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46216,7 +46216,7 @@ pub fn vreinterpret_s16_s8(a: int8x8_t) -> int16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46238,7 +46238,7 @@ pub fn vreinterpret_s32_s8(a: int8x8_t) -> int32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46264,7 +46264,7 @@ pub fn vreinterpret_s32_s8(a: int8x8_t) -> int32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46286,7 +46286,7 @@ pub fn vreinterpret_s64_s8(a: int8x8_t) -> int64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46309,7 +46309,7 @@ pub fn vreinterpret_s64_s8(a: int8x8_t) -> int64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46331,7 +46331,7 @@ pub fn vreinterpret_u8_s8(a: int8x8_t) -> uint8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46357,7 +46357,7 @@ pub fn vreinterpret_u8_s8(a: int8x8_t) -> uint8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46379,7 +46379,7 @@ pub fn vreinterpret_u16_s8(a: int8x8_t) -> uint16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46405,7 +46405,7 @@ pub fn vreinterpret_u16_s8(a: int8x8_t) -> uint16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46427,7 +46427,7 @@ pub fn vreinterpret_u32_s8(a: int8x8_t) -> uint32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46453,7 +46453,7 @@ pub fn vreinterpret_u32_s8(a: int8x8_t) -> uint32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46475,7 +46475,7 @@ pub fn vreinterpret_u64_s8(a: int8x8_t) -> uint64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46498,7 +46498,7 @@ pub fn vreinterpret_u64_s8(a: int8x8_t) -> uint64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46520,7 +46520,7 @@ pub fn vreinterpret_p8_s8(a: int8x8_t) -> poly8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46546,7 +46546,7 @@ pub fn vreinterpret_p8_s8(a: int8x8_t) -> poly8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46568,7 +46568,7 @@ pub fn vreinterpret_p16_s8(a: int8x8_t) -> poly16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46594,7 +46594,7 @@ pub fn vreinterpret_p16_s8(a: int8x8_t) -> poly16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46616,7 +46616,7 @@ pub fn vreinterpretq_f32_s8(a: int8x16_t) -> float32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46643,7 +46643,7 @@ pub fn vreinterpretq_f32_s8(a: int8x16_t) -> float32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46665,7 +46665,7 @@ pub fn vreinterpretq_s16_s8(a: int8x16_t) -> int16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46692,7 +46692,7 @@ pub fn vreinterpretq_s16_s8(a: int8x16_t) -> int16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46714,7 +46714,7 @@ pub fn vreinterpretq_s32_s8(a: int8x16_t) -> int32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46741,7 +46741,7 @@ pub fn vreinterpretq_s32_s8(a: int8x16_t) -> int32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46763,7 +46763,7 @@ pub fn vreinterpretq_s64_s8(a: int8x16_t) -> int64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46790,7 +46790,7 @@ pub fn vreinterpretq_s64_s8(a: int8x16_t) -> int64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46812,7 +46812,7 @@ pub fn vreinterpretq_u8_s8(a: int8x16_t) -> uint8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46843,7 +46843,7 @@ pub fn vreinterpretq_u8_s8(a: int8x16_t) -> uint8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46865,7 +46865,7 @@ pub fn vreinterpretq_u16_s8(a: int8x16_t) -> uint16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46892,7 +46892,7 @@ pub fn vreinterpretq_u16_s8(a: int8x16_t) -> uint16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46914,7 +46914,7 @@ pub fn vreinterpretq_u32_s8(a: int8x16_t) -> uint32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46941,7 +46941,7 @@ pub fn vreinterpretq_u32_s8(a: int8x16_t) -> uint32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46963,7 +46963,7 @@ pub fn vreinterpretq_u64_s8(a: int8x16_t) -> uint64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -46990,7 +46990,7 @@ pub fn vreinterpretq_u64_s8(a: int8x16_t) -> uint64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47012,7 +47012,7 @@ pub fn vreinterpretq_p8_s8(a: int8x16_t) -> poly8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47043,7 +47043,7 @@ pub fn vreinterpretq_p8_s8(a: int8x16_t) -> poly8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47065,7 +47065,7 @@ pub fn vreinterpretq_p16_s8(a: int8x16_t) -> poly16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47092,7 +47092,7 @@ pub fn vreinterpretq_p16_s8(a: int8x16_t) -> poly16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47114,7 +47114,7 @@ pub fn vreinterpret_f32_s16(a: int16x4_t) -> float32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47140,7 +47140,7 @@ pub fn vreinterpret_f32_s16(a: int16x4_t) -> float32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47162,7 +47162,7 @@ pub fn vreinterpret_s8_s16(a: int16x4_t) -> int8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47188,7 +47188,7 @@ pub fn vreinterpret_s8_s16(a: int16x4_t) -> int8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47210,7 +47210,7 @@ pub fn vreinterpret_s32_s16(a: int16x4_t) -> int32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47236,7 +47236,7 @@ pub fn vreinterpret_s32_s16(a: int16x4_t) -> int32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47258,7 +47258,7 @@ pub fn vreinterpret_s64_s16(a: int16x4_t) -> int64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47281,7 +47281,7 @@ pub fn vreinterpret_s64_s16(a: int16x4_t) -> int64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47303,7 +47303,7 @@ pub fn vreinterpret_u8_s16(a: int16x4_t) -> uint8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47329,7 +47329,7 @@ pub fn vreinterpret_u8_s16(a: int16x4_t) -> uint8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47351,7 +47351,7 @@ pub fn vreinterpret_u16_s16(a: int16x4_t) -> uint16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47377,7 +47377,7 @@ pub fn vreinterpret_u16_s16(a: int16x4_t) -> uint16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47399,7 +47399,7 @@ pub fn vreinterpret_u32_s16(a: int16x4_t) -> uint32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47425,7 +47425,7 @@ pub fn vreinterpret_u32_s16(a: int16x4_t) -> uint32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47447,7 +47447,7 @@ pub fn vreinterpret_u64_s16(a: int16x4_t) -> uint64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47470,7 +47470,7 @@ pub fn vreinterpret_u64_s16(a: int16x4_t) -> uint64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47492,7 +47492,7 @@ pub fn vreinterpret_p8_s16(a: int16x4_t) -> poly8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47518,7 +47518,7 @@ pub fn vreinterpret_p8_s16(a: int16x4_t) -> poly8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47540,7 +47540,7 @@ pub fn vreinterpret_p16_s16(a: int16x4_t) -> poly16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47566,7 +47566,7 @@ pub fn vreinterpret_p16_s16(a: int16x4_t) -> poly16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47588,7 +47588,7 @@ pub fn vreinterpretq_f32_s16(a: int16x8_t) -> float32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47614,7 +47614,7 @@ pub fn vreinterpretq_f32_s16(a: int16x8_t) -> float32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47636,7 +47636,7 @@ pub fn vreinterpretq_s8_s16(a: int16x8_t) -> int8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47666,7 +47666,7 @@ pub fn vreinterpretq_s8_s16(a: int16x8_t) -> int8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47688,7 +47688,7 @@ pub fn vreinterpretq_s32_s16(a: int16x8_t) -> int32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47714,7 +47714,7 @@ pub fn vreinterpretq_s32_s16(a: int16x8_t) -> int32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47736,7 +47736,7 @@ pub fn vreinterpretq_s64_s16(a: int16x8_t) -> int64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47762,7 +47762,7 @@ pub fn vreinterpretq_s64_s16(a: int16x8_t) -> int64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47784,7 +47784,7 @@ pub fn vreinterpretq_u8_s16(a: int16x8_t) -> uint8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47814,7 +47814,7 @@ pub fn vreinterpretq_u8_s16(a: int16x8_t) -> uint8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47836,7 +47836,7 @@ pub fn vreinterpretq_u16_s16(a: int16x8_t) -> uint16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47862,7 +47862,7 @@ pub fn vreinterpretq_u16_s16(a: int16x8_t) -> uint16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47884,7 +47884,7 @@ pub fn vreinterpretq_u32_s16(a: int16x8_t) -> uint32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47910,7 +47910,7 @@ pub fn vreinterpretq_u32_s16(a: int16x8_t) -> uint32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47932,7 +47932,7 @@ pub fn vreinterpretq_u64_s16(a: int16x8_t) -> uint64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47958,7 +47958,7 @@ pub fn vreinterpretq_u64_s16(a: int16x8_t) -> uint64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -47980,7 +47980,7 @@ pub fn vreinterpretq_p8_s16(a: int16x8_t) -> poly8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48010,7 +48010,7 @@ pub fn vreinterpretq_p8_s16(a: int16x8_t) -> poly8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48032,7 +48032,7 @@ pub fn vreinterpretq_p16_s16(a: int16x8_t) -> poly16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48058,7 +48058,7 @@ pub fn vreinterpretq_p16_s16(a: int16x8_t) -> poly16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48080,7 +48080,7 @@ pub fn vreinterpret_f32_s32(a: int32x2_t) -> float32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48106,7 +48106,7 @@ pub fn vreinterpret_f32_s32(a: int32x2_t) -> float32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48128,7 +48128,7 @@ pub fn vreinterpret_s8_s32(a: int32x2_t) -> int8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48154,7 +48154,7 @@ pub fn vreinterpret_s8_s32(a: int32x2_t) -> int8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48176,7 +48176,7 @@ pub fn vreinterpret_s16_s32(a: int32x2_t) -> int16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48202,7 +48202,7 @@ pub fn vreinterpret_s16_s32(a: int32x2_t) -> int16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48224,7 +48224,7 @@ pub fn vreinterpret_s64_s32(a: int32x2_t) -> int64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48247,7 +48247,7 @@ pub fn vreinterpret_s64_s32(a: int32x2_t) -> int64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48269,7 +48269,7 @@ pub fn vreinterpret_u8_s32(a: int32x2_t) -> uint8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48295,7 +48295,7 @@ pub fn vreinterpret_u8_s32(a: int32x2_t) -> uint8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48317,7 +48317,7 @@ pub fn vreinterpret_u16_s32(a: int32x2_t) -> uint16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48343,7 +48343,7 @@ pub fn vreinterpret_u16_s32(a: int32x2_t) -> uint16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48365,7 +48365,7 @@ pub fn vreinterpret_u32_s32(a: int32x2_t) -> uint32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48391,7 +48391,7 @@ pub fn vreinterpret_u32_s32(a: int32x2_t) -> uint32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48413,7 +48413,7 @@ pub fn vreinterpret_u64_s32(a: int32x2_t) -> uint64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48436,7 +48436,7 @@ pub fn vreinterpret_u64_s32(a: int32x2_t) -> uint64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48458,7 +48458,7 @@ pub fn vreinterpret_p8_s32(a: int32x2_t) -> poly8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48484,7 +48484,7 @@ pub fn vreinterpret_p8_s32(a: int32x2_t) -> poly8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48506,7 +48506,7 @@ pub fn vreinterpret_p16_s32(a: int32x2_t) -> poly16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48532,7 +48532,7 @@ pub fn vreinterpret_p16_s32(a: int32x2_t) -> poly16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48554,7 +48554,7 @@ pub fn vreinterpretq_f32_s32(a: int32x4_t) -> float32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48580,7 +48580,7 @@ pub fn vreinterpretq_f32_s32(a: int32x4_t) -> float32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48602,7 +48602,7 @@ pub fn vreinterpretq_s8_s32(a: int32x4_t) -> int8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48632,7 +48632,7 @@ pub fn vreinterpretq_s8_s32(a: int32x4_t) -> int8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48654,7 +48654,7 @@ pub fn vreinterpretq_s16_s32(a: int32x4_t) -> int16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48680,7 +48680,7 @@ pub fn vreinterpretq_s16_s32(a: int32x4_t) -> int16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48702,7 +48702,7 @@ pub fn vreinterpretq_s64_s32(a: int32x4_t) -> int64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48728,7 +48728,7 @@ pub fn vreinterpretq_s64_s32(a: int32x4_t) -> int64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48750,7 +48750,7 @@ pub fn vreinterpretq_u8_s32(a: int32x4_t) -> uint8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48780,7 +48780,7 @@ pub fn vreinterpretq_u8_s32(a: int32x4_t) -> uint8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48802,7 +48802,7 @@ pub fn vreinterpretq_u16_s32(a: int32x4_t) -> uint16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48828,7 +48828,7 @@ pub fn vreinterpretq_u16_s32(a: int32x4_t) -> uint16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48850,7 +48850,7 @@ pub fn vreinterpretq_u32_s32(a: int32x4_t) -> uint32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48876,7 +48876,7 @@ pub fn vreinterpretq_u32_s32(a: int32x4_t) -> uint32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48898,7 +48898,7 @@ pub fn vreinterpretq_u64_s32(a: int32x4_t) -> uint64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48924,7 +48924,7 @@ pub fn vreinterpretq_u64_s32(a: int32x4_t) -> uint64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48946,7 +48946,7 @@ pub fn vreinterpretq_p8_s32(a: int32x4_t) -> poly8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48976,7 +48976,7 @@ pub fn vreinterpretq_p8_s32(a: int32x4_t) -> poly8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -48998,7 +48998,7 @@ pub fn vreinterpretq_p16_s32(a: int32x4_t) -> poly16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49024,7 +49024,7 @@ pub fn vreinterpretq_p16_s32(a: int32x4_t) -> poly16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49046,7 +49046,7 @@ pub fn vreinterpret_f32_s64(a: int64x1_t) -> float32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49071,7 +49071,7 @@ pub fn vreinterpret_f32_s64(a: int64x1_t) -> float32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49093,7 +49093,7 @@ pub fn vreinterpret_s8_s64(a: int64x1_t) -> int8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49118,7 +49118,7 @@ pub fn vreinterpret_s8_s64(a: int64x1_t) -> int8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49140,7 +49140,7 @@ pub fn vreinterpret_s16_s64(a: int64x1_t) -> int16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49165,7 +49165,7 @@ pub fn vreinterpret_s16_s64(a: int64x1_t) -> int16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49187,7 +49187,7 @@ pub fn vreinterpret_s32_s64(a: int64x1_t) -> int32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49212,7 +49212,7 @@ pub fn vreinterpret_s32_s64(a: int64x1_t) -> int32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49234,7 +49234,7 @@ pub fn vreinterpret_u8_s64(a: int64x1_t) -> uint8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49259,7 +49259,7 @@ pub fn vreinterpret_u8_s64(a: int64x1_t) -> uint8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49281,7 +49281,7 @@ pub fn vreinterpret_u16_s64(a: int64x1_t) -> uint16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49306,7 +49306,7 @@ pub fn vreinterpret_u16_s64(a: int64x1_t) -> uint16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49328,7 +49328,7 @@ pub fn vreinterpret_u32_s64(a: int64x1_t) -> uint32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49353,7 +49353,7 @@ pub fn vreinterpret_u32_s64(a: int64x1_t) -> uint32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -49374,7 +49374,7 @@ pub fn vreinterpret_u64_s64(a: int64x1_t) -> uint64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49396,7 +49396,7 @@ pub fn vreinterpret_p8_s64(a: int64x1_t) -> poly8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49421,7 +49421,7 @@ pub fn vreinterpret_p8_s64(a: int64x1_t) -> poly8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49443,7 +49443,7 @@ pub fn vreinterpret_p16_s64(a: int64x1_t) -> poly16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49468,7 +49468,7 @@ pub fn vreinterpret_p16_s64(a: int64x1_t) -> poly16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49490,7 +49490,7 @@ pub fn vreinterpretq_f32_s64(a: int64x2_t) -> float32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49516,7 +49516,7 @@ pub fn vreinterpretq_f32_s64(a: int64x2_t) -> float32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49538,7 +49538,7 @@ pub fn vreinterpretq_s8_s64(a: int64x2_t) -> int8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49568,7 +49568,7 @@ pub fn vreinterpretq_s8_s64(a: int64x2_t) -> int8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49590,7 +49590,7 @@ pub fn vreinterpretq_s16_s64(a: int64x2_t) -> int16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49616,7 +49616,7 @@ pub fn vreinterpretq_s16_s64(a: int64x2_t) -> int16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49638,7 +49638,7 @@ pub fn vreinterpretq_s32_s64(a: int64x2_t) -> int32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49664,7 +49664,7 @@ pub fn vreinterpretq_s32_s64(a: int64x2_t) -> int32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49686,7 +49686,7 @@ pub fn vreinterpretq_u8_s64(a: int64x2_t) -> uint8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49716,7 +49716,7 @@ pub fn vreinterpretq_u8_s64(a: int64x2_t) -> uint8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49738,7 +49738,7 @@ pub fn vreinterpretq_u16_s64(a: int64x2_t) -> uint16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49764,7 +49764,7 @@ pub fn vreinterpretq_u16_s64(a: int64x2_t) -> uint16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49786,7 +49786,7 @@ pub fn vreinterpretq_u32_s64(a: int64x2_t) -> uint32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49812,7 +49812,7 @@ pub fn vreinterpretq_u32_s64(a: int64x2_t) -> uint32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49834,7 +49834,7 @@ pub fn vreinterpretq_u64_s64(a: int64x2_t) -> uint64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49860,7 +49860,7 @@ pub fn vreinterpretq_u64_s64(a: int64x2_t) -> uint64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49882,7 +49882,7 @@ pub fn vreinterpretq_p8_s64(a: int64x2_t) -> poly8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49912,7 +49912,7 @@ pub fn vreinterpretq_p8_s64(a: int64x2_t) -> poly8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49934,7 +49934,7 @@ pub fn vreinterpretq_p16_s64(a: int64x2_t) -> poly16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49960,7 +49960,7 @@ pub fn vreinterpretq_p16_s64(a: int64x2_t) -> poly16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -49982,7 +49982,7 @@ pub fn vreinterpret_f32_u8(a: uint8x8_t) -> float32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50008,7 +50008,7 @@ pub fn vreinterpret_f32_u8(a: uint8x8_t) -> float32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50030,7 +50030,7 @@ pub fn vreinterpret_s8_u8(a: uint8x8_t) -> int8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50056,7 +50056,7 @@ pub fn vreinterpret_s8_u8(a: uint8x8_t) -> int8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50078,7 +50078,7 @@ pub fn vreinterpret_s16_u8(a: uint8x8_t) -> int16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50104,7 +50104,7 @@ pub fn vreinterpret_s16_u8(a: uint8x8_t) -> int16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50126,7 +50126,7 @@ pub fn vreinterpret_s32_u8(a: uint8x8_t) -> int32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50152,7 +50152,7 @@ pub fn vreinterpret_s32_u8(a: uint8x8_t) -> int32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50174,7 +50174,7 @@ pub fn vreinterpret_s64_u8(a: uint8x8_t) -> int64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50197,7 +50197,7 @@ pub fn vreinterpret_s64_u8(a: uint8x8_t) -> int64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50219,7 +50219,7 @@ pub fn vreinterpret_u16_u8(a: uint8x8_t) -> uint16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50245,7 +50245,7 @@ pub fn vreinterpret_u16_u8(a: uint8x8_t) -> uint16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50267,7 +50267,7 @@ pub fn vreinterpret_u32_u8(a: uint8x8_t) -> uint32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50293,7 +50293,7 @@ pub fn vreinterpret_u32_u8(a: uint8x8_t) -> uint32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50315,7 +50315,7 @@ pub fn vreinterpret_u64_u8(a: uint8x8_t) -> uint64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50338,7 +50338,7 @@ pub fn vreinterpret_u64_u8(a: uint8x8_t) -> uint64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50360,7 +50360,7 @@ pub fn vreinterpret_p8_u8(a: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50386,7 +50386,7 @@ pub fn vreinterpret_p8_u8(a: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50408,7 +50408,7 @@ pub fn vreinterpret_p16_u8(a: uint8x8_t) -> poly16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50434,7 +50434,7 @@ pub fn vreinterpret_p16_u8(a: uint8x8_t) -> poly16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50456,7 +50456,7 @@ pub fn vreinterpretq_f32_u8(a: uint8x16_t) -> float32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50483,7 +50483,7 @@ pub fn vreinterpretq_f32_u8(a: uint8x16_t) -> float32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50505,7 +50505,7 @@ pub fn vreinterpretq_s8_u8(a: uint8x16_t) -> int8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50536,7 +50536,7 @@ pub fn vreinterpretq_s8_u8(a: uint8x16_t) -> int8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50558,7 +50558,7 @@ pub fn vreinterpretq_s16_u8(a: uint8x16_t) -> int16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50585,7 +50585,7 @@ pub fn vreinterpretq_s16_u8(a: uint8x16_t) -> int16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50607,7 +50607,7 @@ pub fn vreinterpretq_s32_u8(a: uint8x16_t) -> int32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50634,7 +50634,7 @@ pub fn vreinterpretq_s32_u8(a: uint8x16_t) -> int32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50656,7 +50656,7 @@ pub fn vreinterpretq_s64_u8(a: uint8x16_t) -> int64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50683,7 +50683,7 @@ pub fn vreinterpretq_s64_u8(a: uint8x16_t) -> int64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50705,7 +50705,7 @@ pub fn vreinterpretq_u16_u8(a: uint8x16_t) -> uint16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50732,7 +50732,7 @@ pub fn vreinterpretq_u16_u8(a: uint8x16_t) -> uint16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50754,7 +50754,7 @@ pub fn vreinterpretq_u32_u8(a: uint8x16_t) -> uint32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50781,7 +50781,7 @@ pub fn vreinterpretq_u32_u8(a: uint8x16_t) -> uint32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50803,7 +50803,7 @@ pub fn vreinterpretq_u64_u8(a: uint8x16_t) -> uint64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50830,7 +50830,7 @@ pub fn vreinterpretq_u64_u8(a: uint8x16_t) -> uint64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50852,7 +50852,7 @@ pub fn vreinterpretq_p8_u8(a: uint8x16_t) -> poly8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50883,7 +50883,7 @@ pub fn vreinterpretq_p8_u8(a: uint8x16_t) -> poly8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50905,7 +50905,7 @@ pub fn vreinterpretq_p16_u8(a: uint8x16_t) -> poly16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50932,7 +50932,7 @@ pub fn vreinterpretq_p16_u8(a: uint8x16_t) -> poly16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50954,7 +50954,7 @@ pub fn vreinterpret_f32_u16(a: uint16x4_t) -> float32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -50980,7 +50980,7 @@ pub fn vreinterpret_f32_u16(a: uint16x4_t) -> float32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51002,7 +51002,7 @@ pub fn vreinterpret_s8_u16(a: uint16x4_t) -> int8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51028,7 +51028,7 @@ pub fn vreinterpret_s8_u16(a: uint16x4_t) -> int8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51050,7 +51050,7 @@ pub fn vreinterpret_s16_u16(a: uint16x4_t) -> int16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51076,7 +51076,7 @@ pub fn vreinterpret_s16_u16(a: uint16x4_t) -> int16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51098,7 +51098,7 @@ pub fn vreinterpret_s32_u16(a: uint16x4_t) -> int32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51124,7 +51124,7 @@ pub fn vreinterpret_s32_u16(a: uint16x4_t) -> int32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51146,7 +51146,7 @@ pub fn vreinterpret_s64_u16(a: uint16x4_t) -> int64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51169,7 +51169,7 @@ pub fn vreinterpret_s64_u16(a: uint16x4_t) -> int64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51191,7 +51191,7 @@ pub fn vreinterpret_u8_u16(a: uint16x4_t) -> uint8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51217,7 +51217,7 @@ pub fn vreinterpret_u8_u16(a: uint16x4_t) -> uint8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51239,7 +51239,7 @@ pub fn vreinterpret_u32_u16(a: uint16x4_t) -> uint32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51265,7 +51265,7 @@ pub fn vreinterpret_u32_u16(a: uint16x4_t) -> uint32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51287,7 +51287,7 @@ pub fn vreinterpret_u64_u16(a: uint16x4_t) -> uint64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51310,7 +51310,7 @@ pub fn vreinterpret_u64_u16(a: uint16x4_t) -> uint64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51332,7 +51332,7 @@ pub fn vreinterpret_p8_u16(a: uint16x4_t) -> poly8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51358,7 +51358,7 @@ pub fn vreinterpret_p8_u16(a: uint16x4_t) -> poly8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51380,7 +51380,7 @@ pub fn vreinterpret_p16_u16(a: uint16x4_t) -> poly16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51406,7 +51406,7 @@ pub fn vreinterpret_p16_u16(a: uint16x4_t) -> poly16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51428,7 +51428,7 @@ pub fn vreinterpretq_f32_u16(a: uint16x8_t) -> float32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51454,7 +51454,7 @@ pub fn vreinterpretq_f32_u16(a: uint16x8_t) -> float32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51476,7 +51476,7 @@ pub fn vreinterpretq_s8_u16(a: uint16x8_t) -> int8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51506,7 +51506,7 @@ pub fn vreinterpretq_s8_u16(a: uint16x8_t) -> int8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51528,7 +51528,7 @@ pub fn vreinterpretq_s16_u16(a: uint16x8_t) -> int16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51554,7 +51554,7 @@ pub fn vreinterpretq_s16_u16(a: uint16x8_t) -> int16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51576,7 +51576,7 @@ pub fn vreinterpretq_s32_u16(a: uint16x8_t) -> int32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51602,7 +51602,7 @@ pub fn vreinterpretq_s32_u16(a: uint16x8_t) -> int32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51624,7 +51624,7 @@ pub fn vreinterpretq_s64_u16(a: uint16x8_t) -> int64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51650,7 +51650,7 @@ pub fn vreinterpretq_s64_u16(a: uint16x8_t) -> int64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51672,7 +51672,7 @@ pub fn vreinterpretq_u8_u16(a: uint16x8_t) -> uint8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51702,7 +51702,7 @@ pub fn vreinterpretq_u8_u16(a: uint16x8_t) -> uint8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51724,7 +51724,7 @@ pub fn vreinterpretq_u32_u16(a: uint16x8_t) -> uint32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51750,7 +51750,7 @@ pub fn vreinterpretq_u32_u16(a: uint16x8_t) -> uint32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51772,7 +51772,7 @@ pub fn vreinterpretq_u64_u16(a: uint16x8_t) -> uint64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51798,7 +51798,7 @@ pub fn vreinterpretq_u64_u16(a: uint16x8_t) -> uint64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51820,7 +51820,7 @@ pub fn vreinterpretq_p8_u16(a: uint16x8_t) -> poly8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51850,7 +51850,7 @@ pub fn vreinterpretq_p8_u16(a: uint16x8_t) -> poly8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51872,7 +51872,7 @@ pub fn vreinterpretq_p16_u16(a: uint16x8_t) -> poly16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51898,7 +51898,7 @@ pub fn vreinterpretq_p16_u16(a: uint16x8_t) -> poly16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51920,7 +51920,7 @@ pub fn vreinterpret_f32_u32(a: uint32x2_t) -> float32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51946,7 +51946,7 @@ pub fn vreinterpret_f32_u32(a: uint32x2_t) -> float32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51968,7 +51968,7 @@ pub fn vreinterpret_s8_u32(a: uint32x2_t) -> int8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -51994,7 +51994,7 @@ pub fn vreinterpret_s8_u32(a: uint32x2_t) -> int8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52016,7 +52016,7 @@ pub fn vreinterpret_s16_u32(a: uint32x2_t) -> int16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52042,7 +52042,7 @@ pub fn vreinterpret_s16_u32(a: uint32x2_t) -> int16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52064,7 +52064,7 @@ pub fn vreinterpret_s32_u32(a: uint32x2_t) -> int32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52090,7 +52090,7 @@ pub fn vreinterpret_s32_u32(a: uint32x2_t) -> int32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52112,7 +52112,7 @@ pub fn vreinterpret_s64_u32(a: uint32x2_t) -> int64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52135,7 +52135,7 @@ pub fn vreinterpret_s64_u32(a: uint32x2_t) -> int64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52157,7 +52157,7 @@ pub fn vreinterpret_u8_u32(a: uint32x2_t) -> uint8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52183,7 +52183,7 @@ pub fn vreinterpret_u8_u32(a: uint32x2_t) -> uint8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52205,7 +52205,7 @@ pub fn vreinterpret_u16_u32(a: uint32x2_t) -> uint16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52231,7 +52231,7 @@ pub fn vreinterpret_u16_u32(a: uint32x2_t) -> uint16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52253,7 +52253,7 @@ pub fn vreinterpret_u64_u32(a: uint32x2_t) -> uint64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52276,7 +52276,7 @@ pub fn vreinterpret_u64_u32(a: uint32x2_t) -> uint64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52298,7 +52298,7 @@ pub fn vreinterpret_p8_u32(a: uint32x2_t) -> poly8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52324,7 +52324,7 @@ pub fn vreinterpret_p8_u32(a: uint32x2_t) -> poly8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52346,7 +52346,7 @@ pub fn vreinterpret_p16_u32(a: uint32x2_t) -> poly16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52372,7 +52372,7 @@ pub fn vreinterpret_p16_u32(a: uint32x2_t) -> poly16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52394,7 +52394,7 @@ pub fn vreinterpretq_f32_u32(a: uint32x4_t) -> float32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52420,7 +52420,7 @@ pub fn vreinterpretq_f32_u32(a: uint32x4_t) -> float32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52442,7 +52442,7 @@ pub fn vreinterpretq_s8_u32(a: uint32x4_t) -> int8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52472,7 +52472,7 @@ pub fn vreinterpretq_s8_u32(a: uint32x4_t) -> int8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52494,7 +52494,7 @@ pub fn vreinterpretq_s16_u32(a: uint32x4_t) -> int16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52520,7 +52520,7 @@ pub fn vreinterpretq_s16_u32(a: uint32x4_t) -> int16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52542,7 +52542,7 @@ pub fn vreinterpretq_s32_u32(a: uint32x4_t) -> int32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52568,7 +52568,7 @@ pub fn vreinterpretq_s32_u32(a: uint32x4_t) -> int32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52590,7 +52590,7 @@ pub fn vreinterpretq_s64_u32(a: uint32x4_t) -> int64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52616,7 +52616,7 @@ pub fn vreinterpretq_s64_u32(a: uint32x4_t) -> int64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52638,7 +52638,7 @@ pub fn vreinterpretq_u8_u32(a: uint32x4_t) -> uint8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52668,7 +52668,7 @@ pub fn vreinterpretq_u8_u32(a: uint32x4_t) -> uint8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52690,7 +52690,7 @@ pub fn vreinterpretq_u16_u32(a: uint32x4_t) -> uint16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52716,7 +52716,7 @@ pub fn vreinterpretq_u16_u32(a: uint32x4_t) -> uint16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52738,7 +52738,7 @@ pub fn vreinterpretq_u64_u32(a: uint32x4_t) -> uint64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52764,7 +52764,7 @@ pub fn vreinterpretq_u64_u32(a: uint32x4_t) -> uint64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52786,7 +52786,7 @@ pub fn vreinterpretq_p8_u32(a: uint32x4_t) -> poly8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52816,7 +52816,7 @@ pub fn vreinterpretq_p8_u32(a: uint32x4_t) -> poly8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52838,7 +52838,7 @@ pub fn vreinterpretq_p16_u32(a: uint32x4_t) -> poly16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52864,7 +52864,7 @@ pub fn vreinterpretq_p16_u32(a: uint32x4_t) -> poly16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52886,7 +52886,7 @@ pub fn vreinterpret_f32_u64(a: uint64x1_t) -> float32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52911,7 +52911,7 @@ pub fn vreinterpret_f32_u64(a: uint64x1_t) -> float32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52933,7 +52933,7 @@ pub fn vreinterpret_s8_u64(a: uint64x1_t) -> int8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52958,7 +52958,7 @@ pub fn vreinterpret_s8_u64(a: uint64x1_t) -> int8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -52980,7 +52980,7 @@ pub fn vreinterpret_s16_u64(a: uint64x1_t) -> int16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -53005,7 +53005,7 @@ pub fn vreinterpret_s16_u64(a: uint64x1_t) -> int16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -53027,7 +53027,7 @@ pub fn vreinterpret_s32_u64(a: uint64x1_t) -> int32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -53052,7 +53052,7 @@ pub fn vreinterpret_s32_u64(a: uint64x1_t) -> int32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -53073,7 +53073,7 @@ pub fn vreinterpret_s64_u64(a: uint64x1_t) -> int64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -53095,7 +53095,7 @@ pub fn vreinterpret_u8_u64(a: uint64x1_t) -> uint8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -53120,7 +53120,7 @@ pub fn vreinterpret_u8_u64(a: uint64x1_t) -> uint8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -53142,7 +53142,7 @@ pub fn vreinterpret_u16_u64(a: uint64x1_t) -> uint16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -53167,7 +53167,7 @@ pub fn vreinterpret_u16_u64(a: uint64x1_t) -> uint16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -53189,7 +53189,7 @@ pub fn vreinterpret_u32_u64(a: uint64x1_t) -> uint32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -53214,7 +53214,7 @@ pub fn vreinterpret_u32_u64(a: uint64x1_t) -> uint32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -53236,7 +53236,7 @@ pub fn vreinterpret_p8_u64(a: uint64x1_t) -> poly8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -53261,7 +53261,7 @@ pub fn vreinterpret_p8_u64(a: uint64x1_t) -> poly8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -53283,7 +53283,7 @@ pub fn vreinterpret_p16_u64(a: uint64x1_t) -> poly16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -53308,7 +53308,7 @@ pub fn vreinterpret_p16_u64(a: uint64x1_t) -> poly16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -53330,7 +53330,7 @@ pub fn vreinterpretq_f32_u64(a: uint64x2_t) -> float32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -53356,7 +53356,7 @@ pub fn vreinterpretq_f32_u64(a: uint64x2_t) -> float32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -53378,7 +53378,7 @@ pub fn vreinterpretq_s8_u64(a: uint64x2_t) -> int8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -53408,7 +53408,7 @@ pub fn vreinterpretq_s8_u64(a: uint64x2_t) -> int8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -53430,7 +53430,7 @@ pub fn vreinterpretq_s16_u64(a: uint64x2_t) -> int16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -53456,7 +53456,7 @@ pub fn vreinterpretq_s16_u64(a: uint64x2_t) -> int16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -53478,7 +53478,7 @@ pub fn vreinterpretq_s32_u64(a: uint64x2_t) -> int32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -53504,7 +53504,7 @@ pub fn vreinterpretq_s32_u64(a: uint64x2_t) -> int32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -53526,7 +53526,7 @@ pub fn vreinterpretq_s64_u64(a: uint64x2_t) -> int64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -53552,7 +53552,7 @@ pub fn vreinterpretq_s64_u64(a: uint64x2_t) -> int64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -53574,7 +53574,7 @@ pub fn vreinterpretq_u8_u64(a: uint64x2_t) -> uint8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -53604,7 +53604,7 @@ pub fn vreinterpretq_u8_u64(a: uint64x2_t) -> uint8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -53626,7 +53626,7 @@ pub fn vreinterpretq_u16_u64(a: uint64x2_t) -> uint16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -53652,7 +53652,7 @@ pub fn vreinterpretq_u16_u64(a: uint64x2_t) -> uint16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -53674,7 +53674,7 @@ pub fn vreinterpretq_u32_u64(a: uint64x2_t) -> uint32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -53700,7 +53700,7 @@ pub fn vreinterpretq_u32_u64(a: uint64x2_t) -> uint32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -53722,7 +53722,7 @@ pub fn vreinterpretq_p8_u64(a: uint64x2_t) -> poly8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -53752,7 +53752,7 @@ pub fn vreinterpretq_p8_u64(a: uint64x2_t) -> poly8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -53774,7 +53774,7 @@ pub fn vreinterpretq_p16_u64(a: uint64x2_t) -> poly16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -53800,7 +53800,7 @@ pub fn vreinterpretq_p16_u64(a: uint64x2_t) -> poly16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -53822,7 +53822,7 @@ pub fn vreinterpret_f32_p8(a: poly8x8_t) -> float32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -53848,7 +53848,7 @@ pub fn vreinterpret_f32_p8(a: poly8x8_t) -> float32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -53870,7 +53870,7 @@ pub fn vreinterpret_s8_p8(a: poly8x8_t) -> int8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -53896,7 +53896,7 @@ pub fn vreinterpret_s8_p8(a: poly8x8_t) -> int8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -53918,7 +53918,7 @@ pub fn vreinterpret_s16_p8(a: poly8x8_t) -> int16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -53944,7 +53944,7 @@ pub fn vreinterpret_s16_p8(a: poly8x8_t) -> int16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -53966,7 +53966,7 @@ pub fn vreinterpret_s32_p8(a: poly8x8_t) -> int32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -53992,7 +53992,7 @@ pub fn vreinterpret_s32_p8(a: poly8x8_t) -> int32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -54014,7 +54014,7 @@ pub fn vreinterpret_s64_p8(a: poly8x8_t) -> int64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -54037,7 +54037,7 @@ pub fn vreinterpret_s64_p8(a: poly8x8_t) -> int64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -54059,7 +54059,7 @@ pub fn vreinterpret_u8_p8(a: poly8x8_t) -> uint8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -54085,7 +54085,7 @@ pub fn vreinterpret_u8_p8(a: poly8x8_t) -> uint8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -54107,7 +54107,7 @@ pub fn vreinterpret_u16_p8(a: poly8x8_t) -> uint16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -54133,7 +54133,7 @@ pub fn vreinterpret_u16_p8(a: poly8x8_t) -> uint16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -54155,7 +54155,7 @@ pub fn vreinterpret_u32_p8(a: poly8x8_t) -> uint32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -54181,7 +54181,7 @@ pub fn vreinterpret_u32_p8(a: poly8x8_t) -> uint32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -54203,7 +54203,7 @@ pub fn vreinterpret_u64_p8(a: poly8x8_t) -> uint64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -54226,7 +54226,7 @@ pub fn vreinterpret_u64_p8(a: poly8x8_t) -> uint64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -54248,7 +54248,7 @@ pub fn vreinterpret_p16_p8(a: poly8x8_t) -> poly16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -54274,7 +54274,7 @@ pub fn vreinterpret_p16_p8(a: poly8x8_t) -> poly16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -54296,7 +54296,7 @@ pub fn vreinterpretq_f32_p8(a: poly8x16_t) -> float32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -54323,7 +54323,7 @@ pub fn vreinterpretq_f32_p8(a: poly8x16_t) -> float32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -54345,7 +54345,7 @@ pub fn vreinterpretq_s8_p8(a: poly8x16_t) -> int8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -54376,7 +54376,7 @@ pub fn vreinterpretq_s8_p8(a: poly8x16_t) -> int8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -54398,7 +54398,7 @@ pub fn vreinterpretq_s16_p8(a: poly8x16_t) -> int16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -54425,7 +54425,7 @@ pub fn vreinterpretq_s16_p8(a: poly8x16_t) -> int16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -54447,7 +54447,7 @@ pub fn vreinterpretq_s32_p8(a: poly8x16_t) -> int32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -54474,7 +54474,7 @@ pub fn vreinterpretq_s32_p8(a: poly8x16_t) -> int32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -54496,7 +54496,7 @@ pub fn vreinterpretq_s64_p8(a: poly8x16_t) -> int64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -54523,7 +54523,7 @@ pub fn vreinterpretq_s64_p8(a: poly8x16_t) -> int64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -54545,7 +54545,7 @@ pub fn vreinterpretq_u8_p8(a: poly8x16_t) -> uint8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -54576,7 +54576,7 @@ pub fn vreinterpretq_u8_p8(a: poly8x16_t) -> uint8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -54598,7 +54598,7 @@ pub fn vreinterpretq_u16_p8(a: poly8x16_t) -> uint16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -54625,7 +54625,7 @@ pub fn vreinterpretq_u16_p8(a: poly8x16_t) -> uint16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -54647,7 +54647,7 @@ pub fn vreinterpretq_u32_p8(a: poly8x16_t) -> uint32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -54674,7 +54674,7 @@ pub fn vreinterpretq_u32_p8(a: poly8x16_t) -> uint32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -54696,7 +54696,7 @@ pub fn vreinterpretq_u64_p8(a: poly8x16_t) -> uint64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -54723,7 +54723,7 @@ pub fn vreinterpretq_u64_p8(a: poly8x16_t) -> uint64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -54745,7 +54745,7 @@ pub fn vreinterpretq_p16_p8(a: poly8x16_t) -> poly16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -54772,7 +54772,7 @@ pub fn vreinterpretq_p16_p8(a: poly8x16_t) -> poly16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -54794,7 +54794,7 @@ pub fn vreinterpret_f32_p16(a: poly16x4_t) -> float32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -54820,7 +54820,7 @@ pub fn vreinterpret_f32_p16(a: poly16x4_t) -> float32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -54842,7 +54842,7 @@ pub fn vreinterpret_s8_p16(a: poly16x4_t) -> int8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -54868,7 +54868,7 @@ pub fn vreinterpret_s8_p16(a: poly16x4_t) -> int8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -54890,7 +54890,7 @@ pub fn vreinterpret_s16_p16(a: poly16x4_t) -> int16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -54916,7 +54916,7 @@ pub fn vreinterpret_s16_p16(a: poly16x4_t) -> int16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -54938,7 +54938,7 @@ pub fn vreinterpret_s32_p16(a: poly16x4_t) -> int32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -54964,7 +54964,7 @@ pub fn vreinterpret_s32_p16(a: poly16x4_t) -> int32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -54986,7 +54986,7 @@ pub fn vreinterpret_s64_p16(a: poly16x4_t) -> int64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -55009,7 +55009,7 @@ pub fn vreinterpret_s64_p16(a: poly16x4_t) -> int64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -55031,7 +55031,7 @@ pub fn vreinterpret_u8_p16(a: poly16x4_t) -> uint8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -55057,7 +55057,7 @@ pub fn vreinterpret_u8_p16(a: poly16x4_t) -> uint8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -55079,7 +55079,7 @@ pub fn vreinterpret_u16_p16(a: poly16x4_t) -> uint16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -55105,7 +55105,7 @@ pub fn vreinterpret_u16_p16(a: poly16x4_t) -> uint16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -55127,7 +55127,7 @@ pub fn vreinterpret_u32_p16(a: poly16x4_t) -> uint32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -55153,7 +55153,7 @@ pub fn vreinterpret_u32_p16(a: poly16x4_t) -> uint32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -55175,7 +55175,7 @@ pub fn vreinterpret_u64_p16(a: poly16x4_t) -> uint64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -55198,7 +55198,7 @@ pub fn vreinterpret_u64_p16(a: poly16x4_t) -> uint64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -55220,7 +55220,7 @@ pub fn vreinterpret_p8_p16(a: poly16x4_t) -> poly8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -55246,7 +55246,7 @@ pub fn vreinterpret_p8_p16(a: poly16x4_t) -> poly8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -55268,7 +55268,7 @@ pub fn vreinterpretq_f32_p16(a: poly16x8_t) -> float32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -55294,7 +55294,7 @@ pub fn vreinterpretq_f32_p16(a: poly16x8_t) -> float32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -55316,7 +55316,7 @@ pub fn vreinterpretq_s8_p16(a: poly16x8_t) -> int8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -55346,7 +55346,7 @@ pub fn vreinterpretq_s8_p16(a: poly16x8_t) -> int8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -55368,7 +55368,7 @@ pub fn vreinterpretq_s16_p16(a: poly16x8_t) -> int16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -55394,7 +55394,7 @@ pub fn vreinterpretq_s16_p16(a: poly16x8_t) -> int16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -55416,7 +55416,7 @@ pub fn vreinterpretq_s32_p16(a: poly16x8_t) -> int32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -55442,7 +55442,7 @@ pub fn vreinterpretq_s32_p16(a: poly16x8_t) -> int32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -55464,7 +55464,7 @@ pub fn vreinterpretq_s64_p16(a: poly16x8_t) -> int64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -55490,7 +55490,7 @@ pub fn vreinterpretq_s64_p16(a: poly16x8_t) -> int64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -55512,7 +55512,7 @@ pub fn vreinterpretq_u8_p16(a: poly16x8_t) -> uint8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -55542,7 +55542,7 @@ pub fn vreinterpretq_u8_p16(a: poly16x8_t) -> uint8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -55564,7 +55564,7 @@ pub fn vreinterpretq_u16_p16(a: poly16x8_t) -> uint16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -55590,7 +55590,7 @@ pub fn vreinterpretq_u16_p16(a: poly16x8_t) -> uint16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -55612,7 +55612,7 @@ pub fn vreinterpretq_u32_p16(a: poly16x8_t) -> uint32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -55638,7 +55638,7 @@ pub fn vreinterpretq_u32_p16(a: poly16x8_t) -> uint32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -55660,7 +55660,7 @@ pub fn vreinterpretq_u64_p16(a: poly16x8_t) -> uint64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -55686,7 +55686,7 @@ pub fn vreinterpretq_u64_p16(a: poly16x8_t) -> uint64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -55708,7 +55708,7 @@ pub fn vreinterpretq_p8_p16(a: poly16x8_t) -> poly8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -55738,7 +55738,7 @@ pub fn vreinterpretq_p8_p16(a: poly16x8_t) -> poly8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p128)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -55760,7 +55760,7 @@ pub fn vreinterpretq_s8_p128(a: p128) -> int8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p128)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -55789,7 +55789,7 @@ pub fn vreinterpretq_s8_p128(a: p128) -> int8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p128)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -55811,7 +55811,7 @@ pub fn vreinterpretq_s16_p128(a: p128) -> int16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p128)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -55836,7 +55836,7 @@ pub fn vreinterpretq_s16_p128(a: p128) -> int16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p128)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -55858,7 +55858,7 @@ pub fn vreinterpretq_s32_p128(a: p128) -> int32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p128)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -55883,7 +55883,7 @@ pub fn vreinterpretq_s32_p128(a: p128) -> int32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p128)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -55905,7 +55905,7 @@ pub fn vreinterpretq_s64_p128(a: p128) -> int64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p128)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -55930,7 +55930,7 @@ pub fn vreinterpretq_s64_p128(a: p128) -> int64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p128)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -55952,7 +55952,7 @@ pub fn vreinterpretq_u8_p128(a: p128) -> uint8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p128)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -55981,7 +55981,7 @@ pub fn vreinterpretq_u8_p128(a: p128) -> uint8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p128)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -56003,7 +56003,7 @@ pub fn vreinterpretq_u16_p128(a: p128) -> uint16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p128)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -56028,7 +56028,7 @@ pub fn vreinterpretq_u16_p128(a: p128) -> uint16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p128)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -56050,7 +56050,7 @@ pub fn vreinterpretq_u32_p128(a: p128) -> uint32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p128)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -56075,7 +56075,7 @@ pub fn vreinterpretq_u32_p128(a: p128) -> uint32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p128)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -56097,7 +56097,7 @@ pub fn vreinterpretq_u64_p128(a: p128) -> uint64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p128)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -56122,7 +56122,7 @@ pub fn vreinterpretq_u64_p128(a: p128) -> uint64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_p128)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -56144,7 +56144,7 @@ pub fn vreinterpretq_p8_p128(a: p128) -> poly8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_p128)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -56173,7 +56173,7 @@ pub fn vreinterpretq_p8_p128(a: p128) -> poly8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_p128)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -56195,7 +56195,7 @@ pub fn vreinterpretq_p16_p128(a: p128) -> poly16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_p128)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -56220,7 +56220,7 @@ pub fn vreinterpretq_p16_p128(a: p128) -> poly16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_p128)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -56242,7 +56242,7 @@ pub fn vreinterpretq_p64_p128(a: p128) -> poly64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_p128)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -56267,7 +56267,7 @@ pub fn vreinterpretq_p64_p128(a: p128) -> poly64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -56289,7 +56289,7 @@ pub fn vreinterpret_p64_s8(a: int8x8_t) -> poly64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -56312,7 +56312,7 @@ pub fn vreinterpret_p64_s8(a: int8x8_t) -> poly64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -56334,7 +56334,7 @@ pub fn vreinterpretq_p128_s8(a: int8x16_t) -> p128 {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -56358,7 +56358,7 @@ pub fn vreinterpretq_p128_s8(a: int8x16_t) -> p128 {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -56380,7 +56380,7 @@ pub fn vreinterpretq_p64_s8(a: int8x16_t) -> poly64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -56407,7 +56407,7 @@ pub fn vreinterpretq_p64_s8(a: int8x16_t) -> poly64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -56429,7 +56429,7 @@ pub fn vreinterpret_p64_s16(a: int16x4_t) -> poly64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -56452,7 +56452,7 @@ pub fn vreinterpret_p64_s16(a: int16x4_t) -> poly64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -56474,7 +56474,7 @@ pub fn vreinterpretq_p128_s16(a: int16x8_t) -> p128 {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -56497,7 +56497,7 @@ pub fn vreinterpretq_p128_s16(a: int16x8_t) -> p128 {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -56519,7 +56519,7 @@ pub fn vreinterpretq_p64_s16(a: int16x8_t) -> poly64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -56545,7 +56545,7 @@ pub fn vreinterpretq_p64_s16(a: int16x8_t) -> poly64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -56567,7 +56567,7 @@ pub fn vreinterpret_p64_s32(a: int32x2_t) -> poly64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -56590,7 +56590,7 @@ pub fn vreinterpret_p64_s32(a: int32x2_t) -> poly64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -56612,7 +56612,7 @@ pub fn vreinterpretq_p128_s32(a: int32x4_t) -> p128 {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -56635,7 +56635,7 @@ pub fn vreinterpretq_p128_s32(a: int32x4_t) -> p128 {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -56657,7 +56657,7 @@ pub fn vreinterpretq_p64_s32(a: int32x4_t) -> poly64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -56683,7 +56683,7 @@ pub fn vreinterpretq_p64_s32(a: int32x4_t) -> poly64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -56705,7 +56705,7 @@ pub fn vreinterpretq_p128_s64(a: int64x2_t) -> p128 {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -56728,7 +56728,7 @@ pub fn vreinterpretq_p128_s64(a: int64x2_t) -> p128 {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -56750,7 +56750,7 @@ pub fn vreinterpret_p64_u8(a: uint8x8_t) -> poly64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -56773,7 +56773,7 @@ pub fn vreinterpret_p64_u8(a: uint8x8_t) -> poly64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -56795,7 +56795,7 @@ pub fn vreinterpretq_p128_u8(a: uint8x16_t) -> p128 {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -56819,7 +56819,7 @@ pub fn vreinterpretq_p128_u8(a: uint8x16_t) -> p128 {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -56841,7 +56841,7 @@ pub fn vreinterpretq_p64_u8(a: uint8x16_t) -> poly64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -56868,7 +56868,7 @@ pub fn vreinterpretq_p64_u8(a: uint8x16_t) -> poly64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -56890,7 +56890,7 @@ pub fn vreinterpret_p64_u16(a: uint16x4_t) -> poly64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -56913,7 +56913,7 @@ pub fn vreinterpret_p64_u16(a: uint16x4_t) -> poly64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -56935,7 +56935,7 @@ pub fn vreinterpretq_p128_u16(a: uint16x8_t) -> p128 {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -56958,7 +56958,7 @@ pub fn vreinterpretq_p128_u16(a: uint16x8_t) -> p128 {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -56980,7 +56980,7 @@ pub fn vreinterpretq_p64_u16(a: uint16x8_t) -> poly64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -57006,7 +57006,7 @@ pub fn vreinterpretq_p64_u16(a: uint16x8_t) -> poly64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -57028,7 +57028,7 @@ pub fn vreinterpret_p64_u32(a: uint32x2_t) -> poly64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -57051,7 +57051,7 @@ pub fn vreinterpret_p64_u32(a: uint32x2_t) -> poly64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -57073,7 +57073,7 @@ pub fn vreinterpretq_p128_u32(a: uint32x4_t) -> p128 {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -57096,7 +57096,7 @@ pub fn vreinterpretq_p128_u32(a: uint32x4_t) -> p128 {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -57118,7 +57118,7 @@ pub fn vreinterpretq_p64_u32(a: uint32x4_t) -> poly64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -57144,7 +57144,7 @@ pub fn vreinterpretq_p64_u32(a: uint32x4_t) -> poly64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -57166,7 +57166,7 @@ pub fn vreinterpretq_p128_u64(a: uint64x2_t) -> p128 {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -57189,7 +57189,7 @@ pub fn vreinterpretq_p128_u64(a: uint64x2_t) -> p128 {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -57211,7 +57211,7 @@ pub fn vreinterpret_p64_p8(a: poly8x8_t) -> poly64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -57234,7 +57234,7 @@ pub fn vreinterpret_p64_p8(a: poly8x8_t) -> poly64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -57256,7 +57256,7 @@ pub fn vreinterpretq_p128_p8(a: poly8x16_t) -> p128 {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -57280,7 +57280,7 @@ pub fn vreinterpretq_p128_p8(a: poly8x16_t) -> p128 {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -57302,7 +57302,7 @@ pub fn vreinterpretq_p64_p8(a: poly8x16_t) -> poly64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -57329,7 +57329,7 @@ pub fn vreinterpretq_p64_p8(a: poly8x16_t) -> poly64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -57351,7 +57351,7 @@ pub fn vreinterpret_p64_p16(a: poly16x4_t) -> poly64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -57374,7 +57374,7 @@ pub fn vreinterpret_p64_p16(a: poly16x4_t) -> poly64x1_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -57396,7 +57396,7 @@ pub fn vreinterpretq_p128_p16(a: poly16x8_t) -> p128 {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -57419,7 +57419,7 @@ pub fn vreinterpretq_p128_p16(a: poly16x8_t) -> p128 {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -57441,7 +57441,7 @@ pub fn vreinterpretq_p64_p16(a: poly16x8_t) -> poly64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -57467,7 +57467,7 @@ pub fn vreinterpretq_p64_p16(a: poly16x8_t) -> poly64x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_p64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -57489,7 +57489,7 @@ pub fn vreinterpret_s8_p64(a: poly64x1_t) -> int8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_p64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -57514,7 +57514,7 @@ pub fn vreinterpret_s8_p64(a: poly64x1_t) -> int8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_p64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -57536,7 +57536,7 @@ pub fn vreinterpret_s16_p64(a: poly64x1_t) -> int16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_p64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -57561,7 +57561,7 @@ pub fn vreinterpret_s16_p64(a: poly64x1_t) -> int16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_p64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -57583,7 +57583,7 @@ pub fn vreinterpret_s32_p64(a: poly64x1_t) -> int32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_p64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -57608,7 +57608,7 @@ pub fn vreinterpret_s32_p64(a: poly64x1_t) -> int32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_p64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -57630,7 +57630,7 @@ pub fn vreinterpret_u8_p64(a: poly64x1_t) -> uint8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_p64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -57655,7 +57655,7 @@ pub fn vreinterpret_u8_p64(a: poly64x1_t) -> uint8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_p64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -57677,7 +57677,7 @@ pub fn vreinterpret_u16_p64(a: poly64x1_t) -> uint16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_p64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -57702,7 +57702,7 @@ pub fn vreinterpret_u16_p64(a: poly64x1_t) -> uint16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_p64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -57724,7 +57724,7 @@ pub fn vreinterpret_u32_p64(a: poly64x1_t) -> uint32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_p64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -57749,7 +57749,7 @@ pub fn vreinterpret_u32_p64(a: poly64x1_t) -> uint32x2_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_p64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -57771,7 +57771,7 @@ pub fn vreinterpret_p8_p64(a: poly64x1_t) -> poly8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_p64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -57796,7 +57796,7 @@ pub fn vreinterpret_p8_p64(a: poly64x1_t) -> poly8x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_p64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -57818,7 +57818,7 @@ pub fn vreinterpret_p16_p64(a: poly64x1_t) -> poly16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_p64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -57843,7 +57843,7 @@ pub fn vreinterpret_p16_p64(a: poly64x1_t) -> poly16x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_p64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -57865,7 +57865,7 @@ pub fn vreinterpretq_p128_p64(a: poly64x2_t) -> p128 {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_p64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -57888,7 +57888,7 @@ pub fn vreinterpretq_p128_p64(a: poly64x2_t) -> p128 {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -57910,7 +57910,7 @@ pub fn vreinterpretq_s8_p64(a: poly64x2_t) -> int8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -57940,7 +57940,7 @@ pub fn vreinterpretq_s8_p64(a: poly64x2_t) -> int8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -57962,7 +57962,7 @@ pub fn vreinterpretq_s16_p64(a: poly64x2_t) -> int16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -57988,7 +57988,7 @@ pub fn vreinterpretq_s16_p64(a: poly64x2_t) -> int16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -58010,7 +58010,7 @@ pub fn vreinterpretq_s32_p64(a: poly64x2_t) -> int32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -58036,7 +58036,7 @@ pub fn vreinterpretq_s32_p64(a: poly64x2_t) -> int32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -58058,7 +58058,7 @@ pub fn vreinterpretq_u8_p64(a: poly64x2_t) -> uint8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -58088,7 +58088,7 @@ pub fn vreinterpretq_u8_p64(a: poly64x2_t) -> uint8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -58110,7 +58110,7 @@ pub fn vreinterpretq_u16_p64(a: poly64x2_t) -> uint16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -58136,7 +58136,7 @@ pub fn vreinterpretq_u16_p64(a: poly64x2_t) -> uint16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -58158,7 +58158,7 @@ pub fn vreinterpretq_u32_p64(a: poly64x2_t) -> uint32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -58184,7 +58184,7 @@ pub fn vreinterpretq_u32_p64(a: poly64x2_t) -> uint32x4_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_p64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -58206,7 +58206,7 @@ pub fn vreinterpretq_p8_p64(a: poly64x2_t) -> poly8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_p64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -58236,7 +58236,7 @@ pub fn vreinterpretq_p8_p64(a: poly64x2_t) -> poly8x16_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_p64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -58258,7 +58258,7 @@ pub fn vreinterpretq_p16_p64(a: poly64x2_t) -> poly16x8_t {
 }
 #[doc = "Vector reinterpret cast operation"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_p64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -58284,7 +58284,7 @@ pub fn vreinterpretq_p16_p64(a: poly64x2_t) -> poly16x8_t {
 }
 #[doc = "Reversing vector elements (swap endianness)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev16_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev16.8"))]
@@ -58305,7 +58305,7 @@ pub fn vrev16_p8(a: poly8x8_t) -> poly8x8_t {
 }
 #[doc = "Reversing vector elements (swap endianness)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev16_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev16.8"))]
@@ -58326,7 +58326,7 @@ pub fn vrev16_s8(a: int8x8_t) -> int8x8_t {
 }
 #[doc = "Reversing vector elements (swap endianness)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev16_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev16.8"))]
@@ -58347,7 +58347,7 @@ pub fn vrev16_u8(a: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Reversing vector elements (swap endianness)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev16q_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev16.8"))]
@@ -58368,7 +58368,7 @@ pub fn vrev16q_p8(a: poly8x16_t) -> poly8x16_t {
 }
 #[doc = "Reversing vector elements (swap endianness)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev16q_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev16.8"))]
@@ -58389,7 +58389,7 @@ pub fn vrev16q_s8(a: int8x16_t) -> int8x16_t {
 }
 #[doc = "Reversing vector elements (swap endianness)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev16q_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev16.8"))]
@@ -58410,7 +58410,7 @@ pub fn vrev16q_u8(a: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Reversing vector elements (swap endianness)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32_p16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.16"))]
@@ -58431,7 +58431,7 @@ pub fn vrev32_p16(a: poly16x4_t) -> poly16x4_t {
 }
 #[doc = "Reversing vector elements (swap endianness)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.8"))]
@@ -58452,7 +58452,7 @@ pub fn vrev32_p8(a: poly8x8_t) -> poly8x8_t {
 }
 #[doc = "Reversing vector elements (swap endianness)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.16"))]
@@ -58473,7 +58473,7 @@ pub fn vrev32_s16(a: int16x4_t) -> int16x4_t {
 }
 #[doc = "Reversing vector elements (swap endianness)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.8"))]
@@ -58494,7 +58494,7 @@ pub fn vrev32_s8(a: int8x8_t) -> int8x8_t {
 }
 #[doc = "Reversing vector elements (swap endianness)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.16"))]
@@ -58515,7 +58515,7 @@ pub fn vrev32_u16(a: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Reversing vector elements (swap endianness)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.8"))]
@@ -58536,7 +58536,7 @@ pub fn vrev32_u8(a: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Reversing vector elements (swap endianness)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32q_p16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.16"))]
@@ -58557,7 +58557,7 @@ pub fn vrev32q_p16(a: poly16x8_t) -> poly16x8_t {
 }
 #[doc = "Reversing vector elements (swap endianness)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32q_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.8"))]
@@ -58578,7 +58578,7 @@ pub fn vrev32q_p8(a: poly8x16_t) -> poly8x16_t {
 }
 #[doc = "Reversing vector elements (swap endianness)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32q_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.16"))]
@@ -58599,7 +58599,7 @@ pub fn vrev32q_s16(a: int16x8_t) -> int16x8_t {
 }
 #[doc = "Reversing vector elements (swap endianness)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32q_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.8"))]
@@ -58620,7 +58620,7 @@ pub fn vrev32q_s8(a: int8x16_t) -> int8x16_t {
 }
 #[doc = "Reversing vector elements (swap endianness)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32q_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.16"))]
@@ -58641,7 +58641,7 @@ pub fn vrev32q_u16(a: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Reversing vector elements (swap endianness)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev32q_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev32.8"))]
@@ -58662,7 +58662,7 @@ pub fn vrev32q_u8(a: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Reversing vector elements (swap endianness)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.32"))]
@@ -58683,7 +58683,7 @@ pub fn vrev64_f32(a: float32x2_t) -> float32x2_t {
 }
 #[doc = "Reversing vector elements (swap endianness)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_p16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.16"))]
@@ -58704,7 +58704,7 @@ pub fn vrev64_p16(a: poly16x4_t) -> poly16x4_t {
 }
 #[doc = "Reversing vector elements (swap endianness)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.8"))]
@@ -58725,7 +58725,7 @@ pub fn vrev64_p8(a: poly8x8_t) -> poly8x8_t {
 }
 #[doc = "Reversing vector elements (swap endianness)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.16"))]
@@ -58746,7 +58746,7 @@ pub fn vrev64_s16(a: int16x4_t) -> int16x4_t {
 }
 #[doc = "Reversing vector elements (swap endianness)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.32"))]
@@ -58767,7 +58767,7 @@ pub fn vrev64_s32(a: int32x2_t) -> int32x2_t {
 }
 #[doc = "Reversing vector elements (swap endianness)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.8"))]
@@ -58788,7 +58788,7 @@ pub fn vrev64_s8(a: int8x8_t) -> int8x8_t {
 }
 #[doc = "Reversing vector elements (swap endianness)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.16"))]
@@ -58809,7 +58809,7 @@ pub fn vrev64_u16(a: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Reversing vector elements (swap endianness)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.32"))]
@@ -58830,7 +58830,7 @@ pub fn vrev64_u32(a: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Reversing vector elements (swap endianness)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.8"))]
@@ -58851,7 +58851,7 @@ pub fn vrev64_u8(a: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Reversing vector elements (swap endianness)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.32"))]
@@ -58872,7 +58872,7 @@ pub fn vrev64q_f32(a: float32x4_t) -> float32x4_t {
 }
 #[doc = "Reversing vector elements (swap endianness)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_p16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.16"))]
@@ -58893,7 +58893,7 @@ pub fn vrev64q_p16(a: poly16x8_t) -> poly16x8_t {
 }
 #[doc = "Reversing vector elements (swap endianness)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.8"))]
@@ -58914,7 +58914,7 @@ pub fn vrev64q_p8(a: poly8x16_t) -> poly8x16_t {
 }
 #[doc = "Reversing vector elements (swap endianness)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.16"))]
@@ -58935,7 +58935,7 @@ pub fn vrev64q_s16(a: int16x8_t) -> int16x8_t {
 }
 #[doc = "Reversing vector elements (swap endianness)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.32"))]
@@ -58956,7 +58956,7 @@ pub fn vrev64q_s32(a: int32x4_t) -> int32x4_t {
 }
 #[doc = "Reversing vector elements (swap endianness)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.8"))]
@@ -58977,7 +58977,7 @@ pub fn vrev64q_s8(a: int8x16_t) -> int8x16_t {
 }
 #[doc = "Reversing vector elements (swap endianness)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.16"))]
@@ -58998,7 +58998,7 @@ pub fn vrev64q_u16(a: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Reversing vector elements (swap endianness)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.32"))]
@@ -59019,7 +59019,7 @@ pub fn vrev64q_u32(a: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Reversing vector elements (swap endianness)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrev64.8"))]
@@ -59040,7 +59040,7 @@ pub fn vrev64q_u8(a: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Reverse elements in 64-bit doublewords"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrev64))]
 #[cfg_attr(
@@ -59062,7 +59062,7 @@ pub fn vrev64_f16(a: float16x4_t) -> float16x4_t {
 }
 #[doc = "Reverse elements in 64-bit doublewords"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrev64q_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrev64))]
 #[cfg_attr(
@@ -59084,7 +59084,7 @@ pub fn vrev64q_f16(a: float16x8_t) -> float16x8_t {
 }
 #[doc = "Rounding halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhadd_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.s8"))]
@@ -59113,7 +59113,7 @@ pub fn vrhadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Rounding halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhaddq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.s8"))]
@@ -59142,7 +59142,7 @@ pub fn vrhaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Rounding halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhadd_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.s16"))]
@@ -59171,7 +59171,7 @@ pub fn vrhadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Rounding halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhaddq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.s16"))]
@@ -59200,7 +59200,7 @@ pub fn vrhaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Rounding halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhadd_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.s32"))]
@@ -59229,7 +59229,7 @@ pub fn vrhadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Rounding halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhaddq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.s32"))]
@@ -59258,7 +59258,7 @@ pub fn vrhaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Rounding halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhadd_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.u8"))]
@@ -59287,7 +59287,7 @@ pub fn vrhadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Rounding halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhaddq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.u8"))]
@@ -59316,7 +59316,7 @@ pub fn vrhaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Rounding halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhadd_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.u16"))]
@@ -59345,7 +59345,7 @@ pub fn vrhadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Rounding halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhaddq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.u16"))]
@@ -59374,7 +59374,7 @@ pub fn vrhaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Rounding halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhadd_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.u32"))]
@@ -59403,7 +59403,7 @@ pub fn vrhadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Rounding halving add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhaddq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.u32"))]
@@ -59432,7 +59432,7 @@ pub fn vrhaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Floating-point round to integral, to nearest with ties to even"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndn_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrintn))]
 #[cfg_attr(
@@ -59461,7 +59461,7 @@ pub fn vrndn_f16(a: float16x4_t) -> float16x4_t {
 }
 #[doc = "Floating-point round to integral, to nearest with ties to even"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndnq_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrintn))]
 #[cfg_attr(
@@ -59490,7 +59490,7 @@ pub fn vrndnq_f16(a: float16x8_t) -> float16x8_t {
 }
 #[doc = "Floating-point round to integral, to nearest with ties to even"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndn_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrintn))]
@@ -59518,7 +59518,7 @@ pub fn vrndn_f32(a: float32x2_t) -> float32x2_t {
 }
 #[doc = "Floating-point round to integral, to nearest with ties to even"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndnq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrintn))]
@@ -59546,7 +59546,7 @@ pub fn vrndnq_f32(a: float32x4_t) -> float32x4_t {
 }
 #[doc = "Signed rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
@@ -59575,7 +59575,7 @@ pub fn vrshl_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Signed rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
@@ -59604,7 +59604,7 @@ pub fn vrshlq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Signed rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
@@ -59633,7 +59633,7 @@ pub fn vrshl_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Signed rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
@@ -59662,7 +59662,7 @@ pub fn vrshlq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Signed rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
@@ -59691,7 +59691,7 @@ pub fn vrshl_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Signed rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
@@ -59720,7 +59720,7 @@ pub fn vrshlq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Signed rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
@@ -59749,7 +59749,7 @@ pub fn vrshl_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t {
 }
 #[doc = "Signed rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
@@ -59778,7 +59778,7 @@ pub fn vrshlq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
 }
 #[doc = "Unsigned rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
@@ -59807,7 +59807,7 @@ pub fn vrshl_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t {
 }
 #[doc = "Unsigned rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
@@ -59836,7 +59836,7 @@ pub fn vrshlq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t {
 }
 #[doc = "Unsigned rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
@@ -59865,7 +59865,7 @@ pub fn vrshl_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t {
 }
 #[doc = "Unsigned rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
@@ -59894,7 +59894,7 @@ pub fn vrshlq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t {
 }
 #[doc = "Unsigned rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
@@ -59923,7 +59923,7 @@ pub fn vrshl_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t {
 }
 #[doc = "Unsigned rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
@@ -59952,7 +59952,7 @@ pub fn vrshlq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t {
 }
 #[doc = "Unsigned rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
@@ -59981,7 +59981,7 @@ pub fn vrshl_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t {
 }
 #[doc = "Unsigned rounding shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))]
@@ -60010,7 +60010,7 @@ pub fn vrshlq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t {
 }
 #[doc = "Signed rounding shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
@@ -60033,7 +60033,7 @@ pub fn vrshr_n_s8<const N: i32>(a: int8x8_t) -> int8x8_t {
 }
 #[doc = "Signed rounding shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
@@ -60056,7 +60056,7 @@ pub fn vrshrq_n_s8<const N: i32>(a: int8x16_t) -> int8x16_t {
 }
 #[doc = "Signed rounding shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
@@ -60079,7 +60079,7 @@ pub fn vrshr_n_s16<const N: i32>(a: int16x4_t) -> int16x4_t {
 }
 #[doc = "Signed rounding shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
@@ -60102,7 +60102,7 @@ pub fn vrshrq_n_s16<const N: i32>(a: int16x8_t) -> int16x8_t {
 }
 #[doc = "Signed rounding shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
@@ -60125,7 +60125,7 @@ pub fn vrshr_n_s32<const N: i32>(a: int32x2_t) -> int32x2_t {
 }
 #[doc = "Signed rounding shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
@@ -60148,7 +60148,7 @@ pub fn vrshrq_n_s32<const N: i32>(a: int32x4_t) -> int32x4_t {
 }
 #[doc = "Signed rounding shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
@@ -60171,7 +60171,7 @@ pub fn vrshr_n_s64<const N: i32>(a: int64x1_t) -> int64x1_t {
 }
 #[doc = "Signed rounding shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
@@ -60194,7 +60194,7 @@ pub fn vrshrq_n_s64<const N: i32>(a: int64x2_t) -> int64x2_t {
 }
 #[doc = "Unsigned rounding shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
@@ -60217,7 +60217,7 @@ pub fn vrshr_n_u8<const N: i32>(a: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Unsigned rounding shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
@@ -60240,7 +60240,7 @@ pub fn vrshrq_n_u8<const N: i32>(a: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Unsigned rounding shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
@@ -60263,7 +60263,7 @@ pub fn vrshr_n_u16<const N: i32>(a: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Unsigned rounding shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
@@ -60286,7 +60286,7 @@ pub fn vrshrq_n_u16<const N: i32>(a: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Unsigned rounding shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
@@ -60309,7 +60309,7 @@ pub fn vrshr_n_u32<const N: i32>(a: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Unsigned rounding shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
@@ -60332,7 +60332,7 @@ pub fn vrshrq_n_u32<const N: i32>(a: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Unsigned rounding shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
@@ -60355,7 +60355,7 @@ pub fn vrshr_n_u64<const N: i32>(a: uint64x1_t) -> uint64x1_t {
 }
 #[doc = "Unsigned rounding shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))]
@@ -60378,7 +60378,7 @@ pub fn vrshrq_n_u64<const N: i32>(a: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Rounding shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vrshrn, N = 2))]
@@ -60394,7 +60394,7 @@ pub fn vrshrn_n_s16<const N: i32>(a: int16x8_t) -> int8x8_t {
 }
 #[doc = "Rounding shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vrshrn, N = 2))]
@@ -60410,7 +60410,7 @@ pub fn vrshrn_n_s32<const N: i32>(a: int32x4_t) -> int16x4_t {
 }
 #[doc = "Rounding shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vrshrn, N = 2))]
@@ -60426,7 +60426,7 @@ pub fn vrshrn_n_s64<const N: i32>(a: int64x2_t) -> int32x2_t {
 }
 #[doc = "Rounding shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(rshrn, N = 2))]
@@ -60445,7 +60445,7 @@ pub fn vrshrn_n_s16<const N: i32>(a: int16x8_t) -> int8x8_t {
 }
 #[doc = "Rounding shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(rshrn, N = 2))]
@@ -60464,7 +60464,7 @@ pub fn vrshrn_n_s32<const N: i32>(a: int32x4_t) -> int16x4_t {
 }
 #[doc = "Rounding shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(rshrn, N = 2))]
@@ -60483,7 +60483,7 @@ pub fn vrshrn_n_s64<const N: i32>(a: int64x2_t) -> int32x2_t {
 }
 #[doc = "Rounding shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshrn, N = 2))]
@@ -60506,7 +60506,7 @@ pub fn vrshrn_n_u16<const N: i32>(a: uint16x8_t) -> uint8x8_t {
 }
 #[doc = "Rounding shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshrn, N = 2))]
@@ -60529,7 +60529,7 @@ pub fn vrshrn_n_u32<const N: i32>(a: uint32x4_t) -> uint16x4_t {
 }
 #[doc = "Rounding shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshrn, N = 2))]
@@ -60552,7 +60552,7 @@ pub fn vrshrn_n_u64<const N: i32>(a: uint64x2_t) -> uint32x2_t {
 }
 #[doc = "Reciprocal square-root estimate."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrte_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrte))]
@@ -60582,7 +60582,7 @@ pub fn vrsqrte_f16(a: float16x4_t) -> float16x4_t {
 }
 #[doc = "Reciprocal square-root estimate."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrteq_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrte))]
@@ -60612,7 +60612,7 @@ pub fn vrsqrteq_f16(a: float16x8_t) -> float16x8_t {
 }
 #[doc = "Reciprocal square-root estimate."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrte_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrte))]
@@ -60641,7 +60641,7 @@ pub fn vrsqrte_f32(a: float32x2_t) -> float32x2_t {
 }
 #[doc = "Reciprocal square-root estimate."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrteq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrte))]
@@ -60670,7 +60670,7 @@ pub fn vrsqrteq_f32(a: float32x4_t) -> float32x4_t {
 }
 #[doc = "Unsigned reciprocal square root estimate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrte_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrte))]
@@ -60699,7 +60699,7 @@ pub fn vrsqrte_u32(a: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Unsigned reciprocal square root estimate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrteq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrte))]
@@ -60728,7 +60728,7 @@ pub fn vrsqrteq_u32(a: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Floating-point reciprocal square root step"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrts_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrts))]
@@ -60758,7 +60758,7 @@ pub fn vrsqrts_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 }
 #[doc = "Floating-point reciprocal square root step"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrtsq_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrts))]
@@ -60788,7 +60788,7 @@ pub fn vrsqrtsq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
 }
 #[doc = "Floating-point reciprocal square root step"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrts_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrts))]
@@ -60817,7 +60817,7 @@ pub fn vrsqrts_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
 }
 #[doc = "Floating-point reciprocal square root step"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrtsq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrts))]
@@ -60846,7 +60846,7 @@ pub fn vrsqrtsq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
 }
 #[doc = "Signed rounding shift right and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
@@ -60869,7 +60869,7 @@ pub fn vrsra_n_s8<const N: i32>(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Signed rounding shift right and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
@@ -60892,7 +60892,7 @@ pub fn vrsraq_n_s8<const N: i32>(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Signed rounding shift right and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
@@ -60915,7 +60915,7 @@ pub fn vrsra_n_s16<const N: i32>(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Signed rounding shift right and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
@@ -60938,7 +60938,7 @@ pub fn vrsraq_n_s16<const N: i32>(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Signed rounding shift right and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
@@ -60961,7 +60961,7 @@ pub fn vrsra_n_s32<const N: i32>(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Signed rounding shift right and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
@@ -60984,7 +60984,7 @@ pub fn vrsraq_n_s32<const N: i32>(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Signed rounding shift right and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
@@ -61007,7 +61007,7 @@ pub fn vrsra_n_s64<const N: i32>(a: int64x1_t, b: int64x1_t) -> int64x1_t {
 }
 #[doc = "Signed rounding shift right and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
@@ -61030,7 +61030,7 @@ pub fn vrsraq_n_s64<const N: i32>(a: int64x2_t, b: int64x2_t) -> int64x2_t {
 }
 #[doc = "Unsigned rounding shift right and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
@@ -61053,7 +61053,7 @@ pub fn vrsra_n_u8<const N: i32>(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Unsigned rounding shift right and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
@@ -61076,7 +61076,7 @@ pub fn vrsraq_n_u8<const N: i32>(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Unsigned rounding shift right and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
@@ -61099,7 +61099,7 @@ pub fn vrsra_n_u16<const N: i32>(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Unsigned rounding shift right and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
@@ -61122,7 +61122,7 @@ pub fn vrsraq_n_u16<const N: i32>(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Unsigned rounding shift right and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
@@ -61145,7 +61145,7 @@ pub fn vrsra_n_u32<const N: i32>(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Unsigned rounding shift right and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
@@ -61168,7 +61168,7 @@ pub fn vrsraq_n_u32<const N: i32>(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Unsigned rounding shift right and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
@@ -61191,7 +61191,7 @@ pub fn vrsra_n_u64<const N: i32>(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
 }
 #[doc = "Unsigned rounding shift right and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))]
@@ -61214,7 +61214,7 @@ pub fn vrsraq_n_u64<const N: i32>(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Rounding subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsubhn))]
@@ -61243,7 +61243,7 @@ pub fn vrsubhn_s16(a: int16x8_t, b: int16x8_t) -> int8x8_t {
 }
 #[doc = "Rounding subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsubhn))]
@@ -61272,7 +61272,7 @@ pub fn vrsubhn_s32(a: int32x4_t, b: int32x4_t) -> int16x4_t {
 }
 #[doc = "Rounding subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsubhn))]
@@ -61301,7 +61301,7 @@ pub fn vrsubhn_s64(a: int64x2_t, b: int64x2_t) -> int32x2_t {
 }
 #[doc = "Rounding subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -61323,7 +61323,7 @@ pub fn vrsubhn_u16(a: uint16x8_t, b: uint16x8_t) -> uint8x8_t {
 }
 #[doc = "Rounding subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -61350,7 +61350,7 @@ pub fn vrsubhn_u16(a: uint16x8_t, b: uint16x8_t) -> uint8x8_t {
 }
 #[doc = "Rounding subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -61372,7 +61372,7 @@ pub fn vrsubhn_u32(a: uint32x4_t, b: uint32x4_t) -> uint16x4_t {
 }
 #[doc = "Rounding subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -61399,7 +61399,7 @@ pub fn vrsubhn_u32(a: uint32x4_t, b: uint32x4_t) -> uint16x4_t {
 }
 #[doc = "Rounding subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -61421,7 +61421,7 @@ pub fn vrsubhn_u64(a: uint64x2_t, b: uint64x2_t) -> uint32x2_t {
 }
 #[doc = "Rounding subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -61448,7 +61448,7 @@ pub fn vrsubhn_u64(a: uint64x2_t, b: uint64x2_t) -> uint32x2_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
 #[cfg_attr(
@@ -61465,7 +61465,7 @@ pub fn vset_lane_f16<const LANE: i32>(a: f16, b: float16x4_t) -> float16x4_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
 #[cfg_attr(
@@ -61482,7 +61482,7 @@ pub fn vsetq_lane_f16<const LANE: i32>(a: f16, b: float16x8_t) -> float16x8_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -61505,7 +61505,7 @@ pub fn vset_lane_f32<const LANE: i32>(a: f32, b: float32x2_t) -> float32x2_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -61528,7 +61528,7 @@ pub fn vsetq_lane_f32<const LANE: i32>(a: f32, b: float32x4_t) -> float32x4_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -61551,7 +61551,7 @@ pub fn vset_lane_s8<const LANE: i32>(a: i8, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -61574,7 +61574,7 @@ pub fn vsetq_lane_s8<const LANE: i32>(a: i8, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -61597,7 +61597,7 @@ pub fn vset_lane_s16<const LANE: i32>(a: i16, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -61620,7 +61620,7 @@ pub fn vsetq_lane_s16<const LANE: i32>(a: i16, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -61643,7 +61643,7 @@ pub fn vset_lane_s32<const LANE: i32>(a: i32, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -61666,7 +61666,7 @@ pub fn vsetq_lane_s32<const LANE: i32>(a: i32, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -61689,7 +61689,7 @@ pub fn vsetq_lane_s64<const LANE: i32>(a: i64, b: int64x2_t) -> int64x2_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -61712,7 +61712,7 @@ pub fn vset_lane_u8<const LANE: i32>(a: u8, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -61735,7 +61735,7 @@ pub fn vsetq_lane_u8<const LANE: i32>(a: u8, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -61758,7 +61758,7 @@ pub fn vset_lane_u16<const LANE: i32>(a: u16, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -61781,7 +61781,7 @@ pub fn vsetq_lane_u16<const LANE: i32>(a: u16, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -61804,7 +61804,7 @@ pub fn vset_lane_u32<const LANE: i32>(a: u32, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -61827,7 +61827,7 @@ pub fn vsetq_lane_u32<const LANE: i32>(a: u32, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -61850,7 +61850,7 @@ pub fn vsetq_lane_u64<const LANE: i32>(a: u64, b: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -61873,7 +61873,7 @@ pub fn vset_lane_p8<const LANE: i32>(a: p8, b: poly8x8_t) -> poly8x8_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -61896,7 +61896,7 @@ pub fn vsetq_lane_p8<const LANE: i32>(a: p8, b: poly8x16_t) -> poly8x16_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_p16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -61919,7 +61919,7 @@ pub fn vset_lane_p16<const LANE: i32>(a: p16, b: poly16x4_t) -> poly16x4_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_p16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -61942,7 +61942,7 @@ pub fn vsetq_lane_p16<const LANE: i32>(a: p16, b: poly16x8_t) -> poly16x8_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_p64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -61965,7 +61965,7 @@ pub fn vset_lane_p64<const LANE: i32>(a: p64, b: poly64x1_t) -> poly64x1_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -61988,7 +61988,7 @@ pub fn vset_lane_s64<const LANE: i32>(a: i64, b: int64x1_t) -> int64x1_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -62011,7 +62011,7 @@ pub fn vset_lane_u64<const LANE: i32>(a: u64, b: uint64x1_t) -> uint64x1_t {
 }
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_p64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -62034,7 +62034,7 @@ pub fn vsetq_lane_p64<const LANE: i32>(a: p64, b: poly64x2_t) -> poly64x2_t {
 }
 #[doc = "SHA1 hash update accelerator, choose."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha1cq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "sha2")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(test, assert_instr(sha1c))]
@@ -62059,7 +62059,7 @@ pub fn vsha1cq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32
 }
 #[doc = "SHA1 fixed rotate."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha1h_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "sha2")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(test, assert_instr(sha1h))]
@@ -62084,7 +62084,7 @@ pub fn vsha1h_u32(hash_e: u32) -> u32 {
 }
 #[doc = "SHA1 hash update accelerator, majority"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha1mq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "sha2")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(test, assert_instr(sha1m))]
@@ -62109,7 +62109,7 @@ pub fn vsha1mq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32
 }
 #[doc = "SHA1 hash update accelerator, parity"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha1pq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "sha2")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(test, assert_instr(sha1p))]
@@ -62134,7 +62134,7 @@ pub fn vsha1pq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32
 }
 #[doc = "SHA1 schedule update accelerator, first part."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha1su0q_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "sha2")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(test, assert_instr(sha1su0))]
@@ -62159,7 +62159,7 @@ pub fn vsha1su0q_u32(w0_3: uint32x4_t, w4_7: uint32x4_t, w8_11: uint32x4_t) -> u
 }
 #[doc = "SHA1 schedule update accelerator, second part."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha1su1q_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "sha2")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(test, assert_instr(sha1su1))]
@@ -62184,7 +62184,7 @@ pub fn vsha1su1q_u32(tw0_3: uint32x4_t, w12_15: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "SHA1 schedule update accelerator, upper part."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha256h2q_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "sha2")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(test, assert_instr(sha256h2))]
@@ -62213,7 +62213,7 @@ pub fn vsha256h2q_u32(hash_abcd: uint32x4_t, hash_efgh: uint32x4_t, wk: uint32x4
 }
 #[doc = "SHA1 schedule update accelerator, first part."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha256hq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "sha2")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(test, assert_instr(sha256h))]
@@ -62242,7 +62242,7 @@ pub fn vsha256hq_u32(hash_abcd: uint32x4_t, hash_efgh: uint32x4_t, wk: uint32x4_
 }
 #[doc = "SHA256 schedule update accelerator, first part."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha256su0q_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "sha2")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(test, assert_instr(sha256su0))]
@@ -62267,7 +62267,7 @@ pub fn vsha256su0q_u32(w0_3: uint32x4_t, w4_7: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "SHA256 schedule update accelerator, second part."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha256su1q_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "sha2")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(test, assert_instr(sha256su1))]
@@ -62291,7 +62291,7 @@ pub fn vsha256su1q_u32(tw0_3: uint32x4_t, w8_11: uint32x4_t, w12_15: uint32x4_t)
     }
     unsafe { _vsha256su1q_u32(tw0_3, w8_11, w12_15) }
 }
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -62304,7 +62304,7 @@ fn vshiftlins_v16i8<const N: i32>(a: int8x16_t, b: int8x16_t) -> int8x16_t {
     }
     unsafe { _vshiftlins_v16i8(a, b, const { int8x16_t([N as i8; 16]) }) }
 }
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -62317,7 +62317,7 @@ fn vshiftlins_v1i64<const N: i32>(a: int64x1_t, b: int64x1_t) -> int64x1_t {
     }
     unsafe { _vshiftlins_v1i64(a, b, const { int64x1_t([N as i64; 1]) }) }
 }
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -62330,7 +62330,7 @@ fn vshiftlins_v2i32<const N: i32>(a: int32x2_t, b: int32x2_t) -> int32x2_t {
     }
     unsafe { _vshiftlins_v2i32(a, b, const { int32x2_t([N; 2]) }) }
 }
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -62343,7 +62343,7 @@ fn vshiftlins_v2i64<const N: i32>(a: int64x2_t, b: int64x2_t) -> int64x2_t {
     }
     unsafe { _vshiftlins_v2i64(a, b, const { int64x2_t([N as i64; 2]) }) }
 }
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -62356,7 +62356,7 @@ fn vshiftlins_v4i16<const N: i32>(a: int16x4_t, b: int16x4_t) -> int16x4_t {
     }
     unsafe { _vshiftlins_v4i16(a, b, const { int16x4_t([N as i16; 4]) }) }
 }
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -62369,7 +62369,7 @@ fn vshiftlins_v4i32<const N: i32>(a: int32x4_t, b: int32x4_t) -> int32x4_t {
     }
     unsafe { _vshiftlins_v4i32(a, b, const { int32x4_t([N; 4]) }) }
 }
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -62382,7 +62382,7 @@ fn vshiftlins_v8i16<const N: i32>(a: int16x8_t, b: int16x8_t) -> int16x8_t {
     }
     unsafe { _vshiftlins_v8i16(a, b, const { int16x8_t([N as i16; 8]) }) }
 }
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -62397,7 +62397,7 @@ fn vshiftlins_v8i8<const N: i32>(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftrins_v16i8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -62412,7 +62412,7 @@ fn vshiftrins_v16i8<const N: i32>(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftrins_v1i64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -62427,7 +62427,7 @@ fn vshiftrins_v1i64<const N: i32>(a: int64x1_t, b: int64x1_t) -> int64x1_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftrins_v2i32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -62442,7 +62442,7 @@ fn vshiftrins_v2i32<const N: i32>(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftrins_v2i64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -62457,7 +62457,7 @@ fn vshiftrins_v2i64<const N: i32>(a: int64x2_t, b: int64x2_t) -> int64x2_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftrins_v4i16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -62472,7 +62472,7 @@ fn vshiftrins_v4i16<const N: i32>(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftrins_v4i32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -62487,7 +62487,7 @@ fn vshiftrins_v4i32<const N: i32>(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftrins_v8i16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -62502,7 +62502,7 @@ fn vshiftrins_v8i16<const N: i32>(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshiftrins_v8i8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -62517,7 +62517,7 @@ fn vshiftrins_v8i8<const N: i32>(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
@@ -62540,7 +62540,7 @@ pub fn vshl_n_s8<const N: i32>(a: int8x8_t) -> int8x8_t {
 }
 #[doc = "Shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
@@ -62563,7 +62563,7 @@ pub fn vshlq_n_s8<const N: i32>(a: int8x16_t) -> int8x16_t {
 }
 #[doc = "Shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
@@ -62586,7 +62586,7 @@ pub fn vshl_n_s16<const N: i32>(a: int16x4_t) -> int16x4_t {
 }
 #[doc = "Shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
@@ -62609,7 +62609,7 @@ pub fn vshlq_n_s16<const N: i32>(a: int16x8_t) -> int16x8_t {
 }
 #[doc = "Shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
@@ -62632,7 +62632,7 @@ pub fn vshl_n_s32<const N: i32>(a: int32x2_t) -> int32x2_t {
 }
 #[doc = "Shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
@@ -62655,7 +62655,7 @@ pub fn vshlq_n_s32<const N: i32>(a: int32x4_t) -> int32x4_t {
 }
 #[doc = "Shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
@@ -62678,7 +62678,7 @@ pub fn vshl_n_s64<const N: i32>(a: int64x1_t) -> int64x1_t {
 }
 #[doc = "Shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
@@ -62701,7 +62701,7 @@ pub fn vshlq_n_s64<const N: i32>(a: int64x2_t) -> int64x2_t {
 }
 #[doc = "Shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
@@ -62724,7 +62724,7 @@ pub fn vshl_n_u8<const N: i32>(a: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
@@ -62747,7 +62747,7 @@ pub fn vshlq_n_u8<const N: i32>(a: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
@@ -62770,7 +62770,7 @@ pub fn vshl_n_u16<const N: i32>(a: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
@@ -62793,7 +62793,7 @@ pub fn vshlq_n_u16<const N: i32>(a: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
@@ -62816,7 +62816,7 @@ pub fn vshl_n_u32<const N: i32>(a: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
@@ -62839,7 +62839,7 @@ pub fn vshlq_n_u32<const N: i32>(a: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
@@ -62862,7 +62862,7 @@ pub fn vshl_n_u64<const N: i32>(a: uint64x1_t) -> uint64x1_t {
 }
 #[doc = "Shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))]
@@ -62885,7 +62885,7 @@ pub fn vshlq_n_u64<const N: i32>(a: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Signed Shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
@@ -62914,7 +62914,7 @@ pub fn vshl_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Signed Shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
@@ -62943,7 +62943,7 @@ pub fn vshlq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Signed Shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
@@ -62972,7 +62972,7 @@ pub fn vshl_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Signed Shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
@@ -63001,7 +63001,7 @@ pub fn vshlq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Signed Shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
@@ -63030,7 +63030,7 @@ pub fn vshl_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Signed Shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
@@ -63059,7 +63059,7 @@ pub fn vshlq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Signed Shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
@@ -63088,7 +63088,7 @@ pub fn vshl_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t {
 }
 #[doc = "Signed Shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
@@ -63117,7 +63117,7 @@ pub fn vshlq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
 }
 #[doc = "Unsigned Shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
@@ -63146,7 +63146,7 @@ pub fn vshl_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t {
 }
 #[doc = "Unsigned Shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
@@ -63175,7 +63175,7 @@ pub fn vshlq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t {
 }
 #[doc = "Unsigned Shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
@@ -63204,7 +63204,7 @@ pub fn vshl_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t {
 }
 #[doc = "Unsigned Shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
@@ -63233,7 +63233,7 @@ pub fn vshlq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t {
 }
 #[doc = "Unsigned Shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
@@ -63262,7 +63262,7 @@ pub fn vshl_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t {
 }
 #[doc = "Unsigned Shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
@@ -63291,7 +63291,7 @@ pub fn vshlq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t {
 }
 #[doc = "Unsigned Shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
@@ -63320,7 +63320,7 @@ pub fn vshl_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t {
 }
 #[doc = "Unsigned Shift left"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))]
@@ -63349,7 +63349,7 @@ pub fn vshlq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t {
 }
 #[doc = "Signed shift left long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshll.s16", N = 2))]
@@ -63372,7 +63372,7 @@ pub fn vshll_n_s16<const N: i32>(a: int16x4_t) -> int32x4_t {
 }
 #[doc = "Signed shift left long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshll.s32", N = 2))]
@@ -63395,7 +63395,7 @@ pub fn vshll_n_s32<const N: i32>(a: int32x2_t) -> int64x2_t {
 }
 #[doc = "Signed shift left long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_n_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshll.s8", N = 2))]
@@ -63418,7 +63418,7 @@ pub fn vshll_n_s8<const N: i32>(a: int8x8_t) -> int16x8_t {
 }
 #[doc = "Signed shift left long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_n_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshll.u16", N = 2))]
@@ -63441,7 +63441,7 @@ pub fn vshll_n_u16<const N: i32>(a: uint16x4_t) -> uint32x4_t {
 }
 #[doc = "Signed shift left long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_n_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshll.u32", N = 2))]
@@ -63464,7 +63464,7 @@ pub fn vshll_n_u32<const N: i32>(a: uint32x2_t) -> uint64x2_t {
 }
 #[doc = "Signed shift left long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_n_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshll.u8", N = 2))]
@@ -63487,7 +63487,7 @@ pub fn vshll_n_u8<const N: i32>(a: uint8x8_t) -> uint16x8_t {
 }
 #[doc = "Shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.s8", N = 2))]
@@ -63511,7 +63511,7 @@ pub fn vshr_n_s8<const N: i32>(a: int8x8_t) -> int8x8_t {
 }
 #[doc = "Shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.s8", N = 2))]
@@ -63535,7 +63535,7 @@ pub fn vshrq_n_s8<const N: i32>(a: int8x16_t) -> int8x16_t {
 }
 #[doc = "Shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.s16", N = 2))]
@@ -63559,7 +63559,7 @@ pub fn vshr_n_s16<const N: i32>(a: int16x4_t) -> int16x4_t {
 }
 #[doc = "Shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.s16", N = 2))]
@@ -63583,7 +63583,7 @@ pub fn vshrq_n_s16<const N: i32>(a: int16x8_t) -> int16x8_t {
 }
 #[doc = "Shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.s32", N = 2))]
@@ -63607,7 +63607,7 @@ pub fn vshr_n_s32<const N: i32>(a: int32x2_t) -> int32x2_t {
 }
 #[doc = "Shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.s32", N = 2))]
@@ -63631,7 +63631,7 @@ pub fn vshrq_n_s32<const N: i32>(a: int32x4_t) -> int32x4_t {
 }
 #[doc = "Shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.s64", N = 2))]
@@ -63655,7 +63655,7 @@ pub fn vshr_n_s64<const N: i32>(a: int64x1_t) -> int64x1_t {
 }
 #[doc = "Shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.s64", N = 2))]
@@ -63679,7 +63679,7 @@ pub fn vshrq_n_s64<const N: i32>(a: int64x2_t) -> int64x2_t {
 }
 #[doc = "Shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.u8", N = 2))]
@@ -63707,7 +63707,7 @@ pub fn vshr_n_u8<const N: i32>(a: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.u8", N = 2))]
@@ -63735,7 +63735,7 @@ pub fn vshrq_n_u8<const N: i32>(a: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.u16", N = 2))]
@@ -63763,7 +63763,7 @@ pub fn vshr_n_u16<const N: i32>(a: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.u16", N = 2))]
@@ -63791,7 +63791,7 @@ pub fn vshrq_n_u16<const N: i32>(a: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.u32", N = 2))]
@@ -63819,7 +63819,7 @@ pub fn vshr_n_u32<const N: i32>(a: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.u32", N = 2))]
@@ -63847,7 +63847,7 @@ pub fn vshrq_n_u32<const N: i32>(a: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.u64", N = 2))]
@@ -63875,7 +63875,7 @@ pub fn vshr_n_u64<const N: i32>(a: uint64x1_t) -> uint64x1_t {
 }
 #[doc = "Shift right"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.u64", N = 2))]
@@ -63903,7 +63903,7 @@ pub fn vshrq_n_u64<const N: i32>(a: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshrn.i16", N = 2))]
@@ -63926,7 +63926,7 @@ pub fn vshrn_n_s16<const N: i32>(a: int16x8_t) -> int8x8_t {
 }
 #[doc = "Shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshrn.i32", N = 2))]
@@ -63949,7 +63949,7 @@ pub fn vshrn_n_s32<const N: i32>(a: int32x4_t) -> int16x4_t {
 }
 #[doc = "Shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_n_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshrn.i64", N = 2))]
@@ -63972,7 +63972,7 @@ pub fn vshrn_n_s64<const N: i32>(a: int64x2_t) -> int32x2_t {
 }
 #[doc = "Shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_n_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshrn.i16", N = 2))]
@@ -63995,7 +63995,7 @@ pub fn vshrn_n_u16<const N: i32>(a: uint16x8_t) -> uint8x8_t {
 }
 #[doc = "Shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_n_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshrn.i32", N = 2))]
@@ -64018,7 +64018,7 @@ pub fn vshrn_n_u32<const N: i32>(a: uint32x4_t) -> uint16x4_t {
 }
 #[doc = "Shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_n_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshrn.i64", N = 2))]
@@ -64041,7 +64041,7 @@ pub fn vshrn_n_u64<const N: i32>(a: uint64x2_t) -> uint32x2_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -64053,7 +64053,7 @@ pub fn vsli_n_s8<const N: i32>(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -64065,7 +64065,7 @@ pub fn vsliq_n_s8<const N: i32>(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -64077,7 +64077,7 @@ pub fn vsli_n_s16<const N: i32>(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_s16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -64089,7 +64089,7 @@ pub fn vsliq_n_s16<const N: i32>(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -64101,7 +64101,7 @@ pub fn vsli_n_s32<const N: i32>(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -64113,7 +64113,7 @@ pub fn vsliq_n_s32<const N: i32>(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -64125,7 +64125,7 @@ pub fn vsli_n_s64<const N: i32>(a: int64x1_t, b: int64x1_t) -> int64x1_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_s64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -64137,7 +64137,7 @@ pub fn vsliq_n_s64<const N: i32>(a: int64x2_t, b: int64x2_t) -> int64x2_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -64149,7 +64149,7 @@ pub fn vsli_n_u8<const N: i32>(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -64161,7 +64161,7 @@ pub fn vsliq_n_u8<const N: i32>(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -64173,7 +64173,7 @@ pub fn vsli_n_u16<const N: i32>(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -64185,7 +64185,7 @@ pub fn vsliq_n_u16<const N: i32>(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -64197,7 +64197,7 @@ pub fn vsli_n_u32<const N: i32>(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -64209,7 +64209,7 @@ pub fn vsliq_n_u32<const N: i32>(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -64221,7 +64221,7 @@ pub fn vsli_n_u64<const N: i32>(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -64233,7 +64233,7 @@ pub fn vsliq_n_u64<const N: i32>(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -64245,7 +64245,7 @@ pub fn vsli_n_p8<const N: i32>(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -64257,7 +64257,7 @@ pub fn vsliq_n_p8<const N: i32>(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsli_n_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -64269,7 +64269,7 @@ pub fn vsli_n_p16<const N: i32>(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t {
 }
 #[doc = "Shift Left and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsliq_n_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -64281,7 +64281,7 @@ pub fn vsliq_n_p16<const N: i32>(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t {
 }
 #[doc = "Signed shift right and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
@@ -64304,7 +64304,7 @@ pub fn vsra_n_s8<const N: i32>(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Signed shift right and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
@@ -64327,7 +64327,7 @@ pub fn vsraq_n_s8<const N: i32>(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Signed shift right and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
@@ -64350,7 +64350,7 @@ pub fn vsra_n_s16<const N: i32>(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Signed shift right and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
@@ -64373,7 +64373,7 @@ pub fn vsraq_n_s16<const N: i32>(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Signed shift right and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
@@ -64396,7 +64396,7 @@ pub fn vsra_n_s32<const N: i32>(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Signed shift right and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
@@ -64419,7 +64419,7 @@ pub fn vsraq_n_s32<const N: i32>(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Signed shift right and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
@@ -64442,7 +64442,7 @@ pub fn vsra_n_s64<const N: i32>(a: int64x1_t, b: int64x1_t) -> int64x1_t {
 }
 #[doc = "Signed shift right and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
@@ -64465,7 +64465,7 @@ pub fn vsraq_n_s64<const N: i32>(a: int64x2_t, b: int64x2_t) -> int64x2_t {
 }
 #[doc = "Unsigned shift right and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
@@ -64488,7 +64488,7 @@ pub fn vsra_n_u8<const N: i32>(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Unsigned shift right and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
@@ -64511,7 +64511,7 @@ pub fn vsraq_n_u8<const N: i32>(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Unsigned shift right and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
@@ -64534,7 +64534,7 @@ pub fn vsra_n_u16<const N: i32>(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Unsigned shift right and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
@@ -64557,7 +64557,7 @@ pub fn vsraq_n_u16<const N: i32>(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Unsigned shift right and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
@@ -64580,7 +64580,7 @@ pub fn vsra_n_u32<const N: i32>(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Unsigned shift right and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
@@ -64603,7 +64603,7 @@ pub fn vsraq_n_u32<const N: i32>(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Unsigned shift right and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
@@ -64626,7 +64626,7 @@ pub fn vsra_n_u64<const N: i32>(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
 }
 #[doc = "Unsigned shift right and accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))]
@@ -64649,7 +64649,7 @@ pub fn vsraq_n_u64<const N: i32>(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -64661,7 +64661,7 @@ pub fn vsri_n_s8<const N: i32>(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -64673,7 +64673,7 @@ pub fn vsriq_n_s8<const N: i32>(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -64685,7 +64685,7 @@ pub fn vsri_n_s16<const N: i32>(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -64697,7 +64697,7 @@ pub fn vsriq_n_s16<const N: i32>(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -64709,7 +64709,7 @@ pub fn vsri_n_s32<const N: i32>(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -64721,7 +64721,7 @@ pub fn vsriq_n_s32<const N: i32>(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -64733,7 +64733,7 @@ pub fn vsri_n_s64<const N: i32>(a: int64x1_t, b: int64x1_t) -> int64x1_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -64745,7 +64745,7 @@ pub fn vsriq_n_s64<const N: i32>(a: int64x2_t, b: int64x2_t) -> int64x2_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -64757,7 +64757,7 @@ pub fn vsri_n_u8<const N: i32>(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -64769,7 +64769,7 @@ pub fn vsriq_n_u8<const N: i32>(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -64781,7 +64781,7 @@ pub fn vsri_n_u16<const N: i32>(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_u16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -64793,7 +64793,7 @@ pub fn vsriq_n_u16<const N: i32>(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -64805,7 +64805,7 @@ pub fn vsri_n_u32<const N: i32>(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_u32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -64817,7 +64817,7 @@ pub fn vsriq_n_u32<const N: i32>(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -64829,7 +64829,7 @@ pub fn vsri_n_u64<const N: i32>(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_u64)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -64841,7 +64841,7 @@ pub fn vsriq_n_u64<const N: i32>(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -64853,7 +64853,7 @@ pub fn vsri_n_p8<const N: i32>(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -64865,7 +64865,7 @@ pub fn vsriq_n_p8<const N: i32>(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -64877,7 +64877,7 @@ pub fn vsri_n_p16<const N: i32>(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t {
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_p16)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -64891,7 +64891,7 @@ pub fn vsriq_n_p16<const N: i32>(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[target_feature(enable = "neon,fp16")]
@@ -64909,7 +64909,7 @@ pub unsafe fn vst1_f16(ptr: *mut f16, a: float16x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[target_feature(enable = "neon,fp16")]
@@ -64927,7 +64927,7 @@ pub unsafe fn vst1q_f16(ptr: *mut f16, a: float16x8_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f16_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(test, assert_instr(vst1))]
@@ -64945,7 +64945,7 @@ pub unsafe fn vst1_f16_x2(a: *mut f16, b: float16x4x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f16_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(test, assert_instr(vst1))]
@@ -64963,7 +64963,7 @@ pub unsafe fn vst1q_f16_x2(a: *mut f16, b: float16x8x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f16_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(st1))]
 #[target_feature(enable = "neon,fp16")]
@@ -64983,7 +64983,7 @@ pub unsafe fn vst1_f16_x2(a: *mut f16, b: float16x4x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f16_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(st1))]
 #[target_feature(enable = "neon,fp16")]
@@ -65003,7 +65003,7 @@ pub unsafe fn vst1q_f16_x2(a: *mut f16, b: float16x8x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f16_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(test, assert_instr(vst1))]
@@ -65021,7 +65021,7 @@ pub unsafe fn vst1_f16_x3(a: *mut f16, b: float16x4x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f16_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(test, assert_instr(vst1))]
@@ -65039,7 +65039,7 @@ pub unsafe fn vst1q_f16_x3(a: *mut f16, b: float16x8x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f16_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(st1))]
 #[target_feature(enable = "neon,fp16")]
@@ -65059,7 +65059,7 @@ pub unsafe fn vst1_f16_x3(a: *mut f16, b: float16x4x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f16_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(st1))]
 #[target_feature(enable = "neon,fp16")]
@@ -65079,7 +65079,7 @@ pub unsafe fn vst1q_f16_x3(a: *mut f16, b: float16x8x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f16_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -65104,7 +65104,7 @@ pub unsafe fn vst1_f16_x4(a: *mut f16, b: float16x4x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f16_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -65129,7 +65129,7 @@ pub unsafe fn vst1q_f16_x4(a: *mut f16, b: float16x8x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f16_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(st1))]
 #[target_feature(enable = "neon,fp16")]
@@ -65155,7 +65155,7 @@ pub unsafe fn vst1_f16_x4(a: *mut f16, b: float16x4x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f16_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(st1))]
 #[target_feature(enable = "neon,fp16")]
@@ -65181,7 +65181,7 @@ pub unsafe fn vst1q_f16_x4(a: *mut f16, b: float16x8x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -65195,7 +65195,7 @@ pub unsafe fn vst1_f32(ptr: *mut f32, a: float32x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -65209,7 +65209,7 @@ pub unsafe fn vst1q_f32(ptr: *mut f32, a: float32x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -65223,7 +65223,7 @@ pub unsafe fn vst1_s8(ptr: *mut i8, a: int8x8_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -65237,7 +65237,7 @@ pub unsafe fn vst1q_s8(ptr: *mut i8, a: int8x16_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -65251,7 +65251,7 @@ pub unsafe fn vst1_s16(ptr: *mut i16, a: int16x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -65265,7 +65265,7 @@ pub unsafe fn vst1q_s16(ptr: *mut i16, a: int16x8_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -65279,7 +65279,7 @@ pub unsafe fn vst1_s32(ptr: *mut i32, a: int32x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -65293,7 +65293,7 @@ pub unsafe fn vst1q_s32(ptr: *mut i32, a: int32x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -65307,7 +65307,7 @@ pub unsafe fn vst1_s64(ptr: *mut i64, a: int64x1_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -65321,7 +65321,7 @@ pub unsafe fn vst1q_s64(ptr: *mut i64, a: int64x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -65335,7 +65335,7 @@ pub unsafe fn vst1_u8(ptr: *mut u8, a: uint8x8_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -65349,7 +65349,7 @@ pub unsafe fn vst1q_u8(ptr: *mut u8, a: uint8x16_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -65363,7 +65363,7 @@ pub unsafe fn vst1_u16(ptr: *mut u16, a: uint16x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -65377,7 +65377,7 @@ pub unsafe fn vst1q_u16(ptr: *mut u16, a: uint16x8_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -65391,7 +65391,7 @@ pub unsafe fn vst1_u32(ptr: *mut u32, a: uint32x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -65405,7 +65405,7 @@ pub unsafe fn vst1q_u32(ptr: *mut u32, a: uint32x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -65419,7 +65419,7 @@ pub unsafe fn vst1_u64(ptr: *mut u64, a: uint64x1_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -65433,7 +65433,7 @@ pub unsafe fn vst1q_u64(ptr: *mut u64, a: uint64x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -65447,7 +65447,7 @@ pub unsafe fn vst1_p8(ptr: *mut p8, a: poly8x8_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -65461,7 +65461,7 @@ pub unsafe fn vst1q_p8(ptr: *mut p8, a: poly8x16_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -65475,7 +65475,7 @@ pub unsafe fn vst1_p16(ptr: *mut p16, a: poly16x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -65489,7 +65489,7 @@ pub unsafe fn vst1q_p16(ptr: *mut p16, a: poly16x8_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -65503,7 +65503,7 @@ pub unsafe fn vst1_p64(ptr: *mut p64, a: poly64x1_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -65517,7 +65517,7 @@ pub unsafe fn vst1q_p64(ptr: *mut p64, a: poly64x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vst1))]
@@ -65533,7 +65533,7 @@ pub unsafe fn vst1_f32_x2(a: *mut f32, b: float32x2x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vst1))]
@@ -65549,7 +65549,7 @@ pub unsafe fn vst1q_f32_x2(a: *mut f32, b: float32x4x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(st1))]
@@ -65568,7 +65568,7 @@ pub unsafe fn vst1_f32_x2(a: *mut f32, b: float32x2x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(st1))]
@@ -65587,7 +65587,7 @@ pub unsafe fn vst1q_f32_x2(a: *mut f32, b: float32x4x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(st1))]
@@ -65606,7 +65606,7 @@ pub unsafe fn vst1_f32_x3(a: *mut f32, b: float32x2x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(st1))]
@@ -65625,7 +65625,7 @@ pub unsafe fn vst1q_f32_x3(a: *mut f32, b: float32x4x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -65647,7 +65647,7 @@ pub unsafe fn vst1_f32_x4(a: *mut f32, b: float32x2x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -65669,7 +65669,7 @@ pub unsafe fn vst1q_f32_x4(a: *mut f32, b: float32x4x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(st1))]
@@ -65694,7 +65694,7 @@ pub unsafe fn vst1_f32_x4(a: *mut f32, b: float32x2x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(st1))]
@@ -65719,7 +65719,7 @@ pub unsafe fn vst1q_f32_x4(a: *mut f32, b: float32x4x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -65739,7 +65739,7 @@ pub unsafe fn vst1_lane_f16<const LANE: i32>(a: *mut f16, b: float16x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -65759,7 +65759,7 @@ pub unsafe fn vst1q_lane_f16<const LANE: i32>(a: *mut f16, b: float16x8_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -65784,7 +65784,7 @@ pub unsafe fn vst1_lane_f32<const LANE: i32>(a: *mut f32, b: float32x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -65809,7 +65809,7 @@ pub unsafe fn vst1q_lane_f32<const LANE: i32>(a: *mut f32, b: float32x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -65834,7 +65834,7 @@ pub unsafe fn vst1_lane_s8<const LANE: i32>(a: *mut i8, b: int8x8_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -65859,7 +65859,7 @@ pub unsafe fn vst1q_lane_s8<const LANE: i32>(a: *mut i8, b: int8x16_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -65884,7 +65884,7 @@ pub unsafe fn vst1_lane_s16<const LANE: i32>(a: *mut i16, b: int16x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -65909,7 +65909,7 @@ pub unsafe fn vst1q_lane_s16<const LANE: i32>(a: *mut i16, b: int16x8_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -65934,7 +65934,7 @@ pub unsafe fn vst1_lane_s32<const LANE: i32>(a: *mut i32, b: int32x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -65959,7 +65959,7 @@ pub unsafe fn vst1q_lane_s32<const LANE: i32>(a: *mut i32, b: int32x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -65984,7 +65984,7 @@ pub unsafe fn vst1q_lane_s64<const LANE: i32>(a: *mut i64, b: int64x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -66009,7 +66009,7 @@ pub unsafe fn vst1_lane_u8<const LANE: i32>(a: *mut u8, b: uint8x8_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -66034,7 +66034,7 @@ pub unsafe fn vst1q_lane_u8<const LANE: i32>(a: *mut u8, b: uint8x16_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -66059,7 +66059,7 @@ pub unsafe fn vst1_lane_u16<const LANE: i32>(a: *mut u16, b: uint16x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -66084,7 +66084,7 @@ pub unsafe fn vst1q_lane_u16<const LANE: i32>(a: *mut u16, b: uint16x8_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -66109,7 +66109,7 @@ pub unsafe fn vst1_lane_u32<const LANE: i32>(a: *mut u32, b: uint32x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -66134,7 +66134,7 @@ pub unsafe fn vst1q_lane_u32<const LANE: i32>(a: *mut u32, b: uint32x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -66159,7 +66159,7 @@ pub unsafe fn vst1q_lane_u64<const LANE: i32>(a: *mut u64, b: uint64x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -66184,7 +66184,7 @@ pub unsafe fn vst1_lane_p8<const LANE: i32>(a: *mut p8, b: poly8x8_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -66209,7 +66209,7 @@ pub unsafe fn vst1q_lane_p8<const LANE: i32>(a: *mut p8, b: poly8x16_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -66234,7 +66234,7 @@ pub unsafe fn vst1_lane_p16<const LANE: i32>(a: *mut p16, b: poly16x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -66259,7 +66259,7 @@ pub unsafe fn vst1q_lane_p16<const LANE: i32>(a: *mut p16, b: poly16x8_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -66284,7 +66284,7 @@ pub unsafe fn vst1_lane_p64<const LANE: i32>(a: *mut p64, b: poly64x1_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -66309,7 +66309,7 @@ pub unsafe fn vst1_lane_s64<const LANE: i32>(a: *mut i64, b: int64x1_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -66334,7 +66334,7 @@ pub unsafe fn vst1_lane_u64<const LANE: i32>(a: *mut u64, b: uint64x1_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p64_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
@@ -66357,7 +66357,7 @@ pub unsafe fn vst1_p64_x2(a: *mut p64, b: poly64x1x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p64_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -66380,7 +66380,7 @@ pub unsafe fn vst1_p64_x3(a: *mut p64, b: poly64x1x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p64_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -66403,7 +66403,7 @@ pub unsafe fn vst1_p64_x4(a: *mut p64, b: poly64x1x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p64_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -66426,7 +66426,7 @@ pub unsafe fn vst1q_p64_x2(a: *mut p64, b: poly64x2x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p64_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -66449,7 +66449,7 @@ pub unsafe fn vst1q_p64_x3(a: *mut p64, b: poly64x2x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p64_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -66472,7 +66472,7 @@ pub unsafe fn vst1q_p64_x4(a: *mut p64, b: poly64x2x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -66491,7 +66491,7 @@ pub unsafe fn vst1_s8_x2(a: *mut i8, b: int8x8x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -66510,7 +66510,7 @@ pub unsafe fn vst1q_s8_x2(a: *mut i8, b: int8x16x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -66529,7 +66529,7 @@ pub unsafe fn vst1_s16_x2(a: *mut i16, b: int16x4x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -66548,7 +66548,7 @@ pub unsafe fn vst1q_s16_x2(a: *mut i16, b: int16x8x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -66567,7 +66567,7 @@ pub unsafe fn vst1_s32_x2(a: *mut i32, b: int32x2x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -66586,7 +66586,7 @@ pub unsafe fn vst1q_s32_x2(a: *mut i32, b: int32x4x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -66605,7 +66605,7 @@ pub unsafe fn vst1_s64_x2(a: *mut i64, b: int64x1x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -66624,7 +66624,7 @@ pub unsafe fn vst1q_s64_x2(a: *mut i64, b: int64x2x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -66640,7 +66640,7 @@ pub unsafe fn vst1_s8_x2(a: *mut i8, b: int8x8x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -66656,7 +66656,7 @@ pub unsafe fn vst1q_s8_x2(a: *mut i8, b: int8x16x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -66672,7 +66672,7 @@ pub unsafe fn vst1_s16_x2(a: *mut i16, b: int16x4x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -66688,7 +66688,7 @@ pub unsafe fn vst1q_s16_x2(a: *mut i16, b: int16x8x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -66704,7 +66704,7 @@ pub unsafe fn vst1_s32_x2(a: *mut i32, b: int32x2x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -66720,7 +66720,7 @@ pub unsafe fn vst1q_s32_x2(a: *mut i32, b: int32x4x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -66736,7 +66736,7 @@ pub unsafe fn vst1_s64_x2(a: *mut i64, b: int64x1x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -66752,7 +66752,7 @@ pub unsafe fn vst1q_s64_x2(a: *mut i64, b: int64x2x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -66771,7 +66771,7 @@ pub unsafe fn vst1_s8_x3(a: *mut i8, b: int8x8x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -66790,7 +66790,7 @@ pub unsafe fn vst1q_s8_x3(a: *mut i8, b: int8x16x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -66809,7 +66809,7 @@ pub unsafe fn vst1_s16_x3(a: *mut i16, b: int16x4x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -66828,7 +66828,7 @@ pub unsafe fn vst1q_s16_x3(a: *mut i16, b: int16x8x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -66847,7 +66847,7 @@ pub unsafe fn vst1_s32_x3(a: *mut i32, b: int32x2x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -66866,7 +66866,7 @@ pub unsafe fn vst1q_s32_x3(a: *mut i32, b: int32x4x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -66885,7 +66885,7 @@ pub unsafe fn vst1_s64_x3(a: *mut i64, b: int64x1x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -66904,7 +66904,7 @@ pub unsafe fn vst1q_s64_x3(a: *mut i64, b: int64x2x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -66920,7 +66920,7 @@ pub unsafe fn vst1_s8_x3(a: *mut i8, b: int8x8x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -66936,7 +66936,7 @@ pub unsafe fn vst1q_s8_x3(a: *mut i8, b: int8x16x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -66952,7 +66952,7 @@ pub unsafe fn vst1_s16_x3(a: *mut i16, b: int16x4x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -66968,7 +66968,7 @@ pub unsafe fn vst1q_s16_x3(a: *mut i16, b: int16x8x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -66984,7 +66984,7 @@ pub unsafe fn vst1_s32_x3(a: *mut i32, b: int32x2x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -67000,7 +67000,7 @@ pub unsafe fn vst1q_s32_x3(a: *mut i32, b: int32x4x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -67016,7 +67016,7 @@ pub unsafe fn vst1_s64_x3(a: *mut i64, b: int64x1x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -67032,7 +67032,7 @@ pub unsafe fn vst1q_s64_x3(a: *mut i64, b: int64x2x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -67051,7 +67051,7 @@ pub unsafe fn vst1_s8_x4(a: *mut i8, b: int8x8x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -67070,7 +67070,7 @@ pub unsafe fn vst1q_s8_x4(a: *mut i8, b: int8x16x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -67089,7 +67089,7 @@ pub unsafe fn vst1_s16_x4(a: *mut i16, b: int16x4x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -67108,7 +67108,7 @@ pub unsafe fn vst1q_s16_x4(a: *mut i16, b: int16x8x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -67127,7 +67127,7 @@ pub unsafe fn vst1_s32_x4(a: *mut i32, b: int32x2x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -67146,7 +67146,7 @@ pub unsafe fn vst1q_s32_x4(a: *mut i32, b: int32x4x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -67165,7 +67165,7 @@ pub unsafe fn vst1_s64_x4(a: *mut i64, b: int64x1x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -67184,7 +67184,7 @@ pub unsafe fn vst1q_s64_x4(a: *mut i64, b: int64x2x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -67200,7 +67200,7 @@ pub unsafe fn vst1_s8_x4(a: *mut i8, b: int8x8x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -67216,7 +67216,7 @@ pub unsafe fn vst1q_s8_x4(a: *mut i8, b: int8x16x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -67232,7 +67232,7 @@ pub unsafe fn vst1_s16_x4(a: *mut i16, b: int16x4x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -67248,7 +67248,7 @@ pub unsafe fn vst1q_s16_x4(a: *mut i16, b: int16x8x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -67264,7 +67264,7 @@ pub unsafe fn vst1_s32_x4(a: *mut i32, b: int32x2x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -67280,7 +67280,7 @@ pub unsafe fn vst1q_s32_x4(a: *mut i32, b: int32x4x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -67296,7 +67296,7 @@ pub unsafe fn vst1_s64_x4(a: *mut i64, b: int64x1x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -67312,7 +67312,7 @@ pub unsafe fn vst1q_s64_x4(a: *mut i64, b: int64x2x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u8_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
@@ -67335,7 +67335,7 @@ pub unsafe fn vst1_u8_x2(a: *mut u8, b: uint8x8x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u8_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
@@ -67358,7 +67358,7 @@ pub unsafe fn vst1_u8_x3(a: *mut u8, b: uint8x8x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u8_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
@@ -67381,7 +67381,7 @@ pub unsafe fn vst1_u8_x4(a: *mut u8, b: uint8x8x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u8_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
@@ -67404,7 +67404,7 @@ pub unsafe fn vst1q_u8_x2(a: *mut u8, b: uint8x16x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u8_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
@@ -67427,7 +67427,7 @@ pub unsafe fn vst1q_u8_x3(a: *mut u8, b: uint8x16x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u8_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
@@ -67450,7 +67450,7 @@ pub unsafe fn vst1q_u8_x4(a: *mut u8, b: uint8x16x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u16_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
@@ -67473,7 +67473,7 @@ pub unsafe fn vst1_u16_x2(a: *mut u16, b: uint16x4x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u16_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
@@ -67496,7 +67496,7 @@ pub unsafe fn vst1_u16_x3(a: *mut u16, b: uint16x4x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u16_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
@@ -67519,7 +67519,7 @@ pub unsafe fn vst1_u16_x4(a: *mut u16, b: uint16x4x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u16_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
@@ -67542,7 +67542,7 @@ pub unsafe fn vst1q_u16_x2(a: *mut u16, b: uint16x8x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u16_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
@@ -67565,7 +67565,7 @@ pub unsafe fn vst1q_u16_x3(a: *mut u16, b: uint16x8x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u16_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
@@ -67588,7 +67588,7 @@ pub unsafe fn vst1q_u16_x4(a: *mut u16, b: uint16x8x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u32_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
@@ -67611,7 +67611,7 @@ pub unsafe fn vst1_u32_x2(a: *mut u32, b: uint32x2x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u32_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
@@ -67634,7 +67634,7 @@ pub unsafe fn vst1_u32_x3(a: *mut u32, b: uint32x2x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u32_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
@@ -67657,7 +67657,7 @@ pub unsafe fn vst1_u32_x4(a: *mut u32, b: uint32x2x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u32_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
@@ -67680,7 +67680,7 @@ pub unsafe fn vst1q_u32_x2(a: *mut u32, b: uint32x4x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u32_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
@@ -67703,7 +67703,7 @@ pub unsafe fn vst1q_u32_x3(a: *mut u32, b: uint32x4x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u32_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
@@ -67726,7 +67726,7 @@ pub unsafe fn vst1q_u32_x4(a: *mut u32, b: uint32x4x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u64_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
@@ -67749,7 +67749,7 @@ pub unsafe fn vst1_u64_x2(a: *mut u64, b: uint64x1x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u64_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
@@ -67772,7 +67772,7 @@ pub unsafe fn vst1_u64_x3(a: *mut u64, b: uint64x1x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u64_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
@@ -67795,7 +67795,7 @@ pub unsafe fn vst1_u64_x4(a: *mut u64, b: uint64x1x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u64_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
@@ -67818,7 +67818,7 @@ pub unsafe fn vst1q_u64_x2(a: *mut u64, b: uint64x2x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u64_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
@@ -67841,7 +67841,7 @@ pub unsafe fn vst1q_u64_x3(a: *mut u64, b: uint64x2x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u64_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
@@ -67864,7 +67864,7 @@ pub unsafe fn vst1q_u64_x4(a: *mut u64, b: uint64x2x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p8_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
@@ -67887,7 +67887,7 @@ pub unsafe fn vst1_p8_x2(a: *mut p8, b: poly8x8x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p8_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
@@ -67910,7 +67910,7 @@ pub unsafe fn vst1_p8_x3(a: *mut p8, b: poly8x8x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p8_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
@@ -67933,7 +67933,7 @@ pub unsafe fn vst1_p8_x4(a: *mut p8, b: poly8x8x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p8_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
@@ -67956,7 +67956,7 @@ pub unsafe fn vst1q_p8_x2(a: *mut p8, b: poly8x16x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p8_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
@@ -67979,7 +67979,7 @@ pub unsafe fn vst1q_p8_x3(a: *mut p8, b: poly8x16x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p8_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
@@ -68002,7 +68002,7 @@ pub unsafe fn vst1q_p8_x4(a: *mut p8, b: poly8x16x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p16_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
@@ -68025,7 +68025,7 @@ pub unsafe fn vst1_p16_x2(a: *mut p16, b: poly16x4x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p16_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
@@ -68048,7 +68048,7 @@ pub unsafe fn vst1_p16_x3(a: *mut p16, b: poly16x4x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p16_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
@@ -68071,7 +68071,7 @@ pub unsafe fn vst1_p16_x4(a: *mut p16, b: poly16x4x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p16_x2)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
@@ -68094,7 +68094,7 @@ pub unsafe fn vst1q_p16_x2(a: *mut p16, b: poly16x8x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p16_x3)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
@@ -68117,7 +68117,7 @@ pub unsafe fn vst1q_p16_x3(a: *mut p16, b: poly16x8x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p16_x4)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))]
@@ -68136,7 +68136,7 @@ pub unsafe fn vst1q_p16_x3(a: *mut p16, b: poly16x8x3_t) {
 pub unsafe fn vst1q_p16_x4(a: *mut p16, b: poly16x8x4_t) {
     vst1q_s16_x4(transmute(a), transmute(b))
 }
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -68150,7 +68150,7 @@ unsafe fn vst1_v1i64<const ALIGN: i32>(addr: *const i8, val: int64x1_t) {
     }
     _vst1_v1i64(addr, val, ALIGN)
 }
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -68164,7 +68164,7 @@ unsafe fn vst1_v2f32<const ALIGN: i32>(addr: *const i8, val: float32x2_t) {
     }
     _vst1_v2f32(addr, val, ALIGN)
 }
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -68178,7 +68178,7 @@ unsafe fn vst1_v2i32<const ALIGN: i32>(addr: *const i8, val: int32x2_t) {
     }
     _vst1_v2i32(addr, val, ALIGN)
 }
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -68192,7 +68192,7 @@ unsafe fn vst1_v4i16<const ALIGN: i32>(addr: *const i8, val: int16x4_t) {
     }
     _vst1_v4i16(addr, val, ALIGN)
 }
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -68206,7 +68206,7 @@ unsafe fn vst1_v8i8<const ALIGN: i32>(addr: *const i8, val: int8x8_t) {
     }
     _vst1_v8i8(addr, val, ALIGN)
 }
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -68220,7 +68220,7 @@ unsafe fn vst1q_v16i8<const ALIGN: i32>(addr: *const i8, val: int8x16_t) {
     }
     _vst1q_v16i8(addr, val, ALIGN)
 }
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -68234,7 +68234,7 @@ unsafe fn vst1q_v2i64<const ALIGN: i32>(addr: *const i8, val: int64x2_t) {
     }
     _vst1q_v2i64(addr, val, ALIGN)
 }
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -68248,7 +68248,7 @@ unsafe fn vst1q_v4f32<const ALIGN: i32>(addr: *const i8, val: float32x4_t) {
     }
     _vst1q_v4f32(addr, val, ALIGN)
 }
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -68262,7 +68262,7 @@ unsafe fn vst1q_v4i32<const ALIGN: i32>(addr: *const i8, val: int32x4_t) {
     }
     _vst1q_v4i32(addr, val, ALIGN)
 }
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -68280,7 +68280,7 @@ unsafe fn vst1q_v8i16<const ALIGN: i32>(addr: *const i8, val: int16x8_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_v4f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[target_feature(enable = "neon,fp16")]
@@ -68298,7 +68298,7 @@ unsafe fn vst1_v4f16(addr: *const i8, val: float16x4_t, align: i32) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_v8f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[target_feature(enable = "neon,fp16")]
@@ -68316,7 +68316,7 @@ unsafe fn vst1q_v8f16(addr: *const i8, val: float16x8_t, align: i32) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))]
@@ -68341,7 +68341,7 @@ pub unsafe fn vst1q_lane_p64<const LANE: i32>(a: *mut p64, b: poly64x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
@@ -68362,7 +68362,7 @@ pub unsafe fn vst2_f16(a: *mut f16, b: float16x4x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
@@ -68383,7 +68383,7 @@ pub unsafe fn vst2q_f16(a: *mut f16, b: float16x8x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -68402,7 +68402,7 @@ pub unsafe fn vst2_f16(a: *mut f16, b: float16x4x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -68421,7 +68421,7 @@ pub unsafe fn vst2q_f16(a: *mut f16, b: float16x8x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -68440,7 +68440,7 @@ pub unsafe fn vst2_f32(a: *mut f32, b: float32x2x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -68459,7 +68459,7 @@ pub unsafe fn vst2q_f32(a: *mut f32, b: float32x4x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -68478,7 +68478,7 @@ pub unsafe fn vst2_s8(a: *mut i8, b: int8x8x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -68497,7 +68497,7 @@ pub unsafe fn vst2q_s8(a: *mut i8, b: int8x16x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -68516,7 +68516,7 @@ pub unsafe fn vst2_s16(a: *mut i16, b: int16x4x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -68535,7 +68535,7 @@ pub unsafe fn vst2q_s16(a: *mut i16, b: int16x8x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -68554,7 +68554,7 @@ pub unsafe fn vst2_s32(a: *mut i32, b: int32x2x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -68573,7 +68573,7 @@ pub unsafe fn vst2q_s32(a: *mut i32, b: int32x4x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -68589,7 +68589,7 @@ pub unsafe fn vst2_f32(a: *mut f32, b: float32x2x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -68605,7 +68605,7 @@ pub unsafe fn vst2q_f32(a: *mut f32, b: float32x4x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -68621,7 +68621,7 @@ pub unsafe fn vst2_s8(a: *mut i8, b: int8x8x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -68637,7 +68637,7 @@ pub unsafe fn vst2q_s8(a: *mut i8, b: int8x16x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -68653,7 +68653,7 @@ pub unsafe fn vst2_s16(a: *mut i16, b: int16x4x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -68669,7 +68669,7 @@ pub unsafe fn vst2q_s16(a: *mut i16, b: int16x8x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -68685,7 +68685,7 @@ pub unsafe fn vst2_s32(a: *mut i32, b: int32x2x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -68701,7 +68701,7 @@ pub unsafe fn vst2q_s32(a: *mut i32, b: int32x4x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[rustc_legacy_const_generics(2)]
@@ -68724,7 +68724,7 @@ pub unsafe fn vst2_lane_f16<const LANE: i32>(a: *mut f16, b: float16x4x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[rustc_legacy_const_generics(2)]
@@ -68747,7 +68747,7 @@ pub unsafe fn vst2q_lane_f16<const LANE: i32>(a: *mut f16, b: float16x8x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -68768,7 +68768,7 @@ pub unsafe fn vst2_lane_f16<const LANE: i32>(a: *mut f16, b: float16x4x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -68789,7 +68789,7 @@ pub unsafe fn vst2q_lane_f16<const LANE: i32>(a: *mut f16, b: float16x8x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[rustc_legacy_const_generics(2)]
@@ -68810,7 +68810,7 @@ pub unsafe fn vst2_lane_f32<const LANE: i32>(a: *mut f32, b: float32x2x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[rustc_legacy_const_generics(2)]
@@ -68831,7 +68831,7 @@ pub unsafe fn vst2q_lane_f32<const LANE: i32>(a: *mut f32, b: float32x4x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[rustc_legacy_const_generics(2)]
@@ -68852,7 +68852,7 @@ pub unsafe fn vst2_lane_s8<const LANE: i32>(a: *mut i8, b: int8x8x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[rustc_legacy_const_generics(2)]
@@ -68873,7 +68873,7 @@ pub unsafe fn vst2_lane_s16<const LANE: i32>(a: *mut i16, b: int16x4x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[rustc_legacy_const_generics(2)]
@@ -68894,7 +68894,7 @@ pub unsafe fn vst2q_lane_s16<const LANE: i32>(a: *mut i16, b: int16x8x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[rustc_legacy_const_generics(2)]
@@ -68915,7 +68915,7 @@ pub unsafe fn vst2_lane_s32<const LANE: i32>(a: *mut i32, b: int32x2x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[rustc_legacy_const_generics(2)]
@@ -68936,7 +68936,7 @@ pub unsafe fn vst2q_lane_s32<const LANE: i32>(a: *mut i32, b: int32x4x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vst2, LANE = 0))]
@@ -68954,7 +68954,7 @@ pub unsafe fn vst2_lane_f32<const LANE: i32>(a: *mut f32, b: float32x2x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vst2, LANE = 0))]
@@ -68972,7 +68972,7 @@ pub unsafe fn vst2q_lane_f32<const LANE: i32>(a: *mut f32, b: float32x4x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vst2, LANE = 0))]
@@ -68990,7 +68990,7 @@ pub unsafe fn vst2_lane_s8<const LANE: i32>(a: *mut i8, b: int8x8x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vst2, LANE = 0))]
@@ -69008,7 +69008,7 @@ pub unsafe fn vst2_lane_s16<const LANE: i32>(a: *mut i16, b: int16x4x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vst2, LANE = 0))]
@@ -69026,7 +69026,7 @@ pub unsafe fn vst2q_lane_s16<const LANE: i32>(a: *mut i16, b: int16x8x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vst2, LANE = 0))]
@@ -69044,7 +69044,7 @@ pub unsafe fn vst2_lane_s32<const LANE: i32>(a: *mut i32, b: int32x2x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vst2, LANE = 0))]
@@ -69062,7 +69062,7 @@ pub unsafe fn vst2q_lane_s32<const LANE: i32>(a: *mut i32, b: int32x4x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2, LANE = 0))]
@@ -69087,7 +69087,7 @@ pub unsafe fn vst2_lane_u8<const LANE: i32>(a: *mut u8, b: uint8x8x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2, LANE = 0))]
@@ -69112,7 +69112,7 @@ pub unsafe fn vst2_lane_u16<const LANE: i32>(a: *mut u16, b: uint16x4x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2, LANE = 0))]
@@ -69137,7 +69137,7 @@ pub unsafe fn vst2q_lane_u16<const LANE: i32>(a: *mut u16, b: uint16x8x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2, LANE = 0))]
@@ -69162,7 +69162,7 @@ pub unsafe fn vst2_lane_u32<const LANE: i32>(a: *mut u32, b: uint32x2x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2, LANE = 0))]
@@ -69187,7 +69187,7 @@ pub unsafe fn vst2q_lane_u32<const LANE: i32>(a: *mut u32, b: uint32x4x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2, LANE = 0))]
@@ -69212,7 +69212,7 @@ pub unsafe fn vst2_lane_p8<const LANE: i32>(a: *mut p8, b: poly8x8x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2, LANE = 0))]
@@ -69237,7 +69237,7 @@ pub unsafe fn vst2_lane_p16<const LANE: i32>(a: *mut p16, b: poly16x4x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2, LANE = 0))]
@@ -69262,7 +69262,7 @@ pub unsafe fn vst2q_lane_p16<const LANE: i32>(a: *mut p16, b: poly16x8x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -69285,7 +69285,7 @@ pub unsafe fn vst2_p64(a: *mut p64, b: poly64x1x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -69301,7 +69301,7 @@ pub unsafe fn vst2_s64(a: *mut i64, b: int64x1x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -69320,7 +69320,7 @@ pub unsafe fn vst2_s64(a: *mut i64, b: int64x1x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -69343,7 +69343,7 @@ pub unsafe fn vst2_u64(a: *mut u64, b: uint64x1x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))]
@@ -69366,7 +69366,7 @@ pub unsafe fn vst2_u8(a: *mut u8, b: uint8x8x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))]
@@ -69389,7 +69389,7 @@ pub unsafe fn vst2q_u8(a: *mut u8, b: uint8x16x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))]
@@ -69412,7 +69412,7 @@ pub unsafe fn vst2_u16(a: *mut u16, b: uint16x4x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))]
@@ -69435,7 +69435,7 @@ pub unsafe fn vst2q_u16(a: *mut u16, b: uint16x8x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))]
@@ -69458,7 +69458,7 @@ pub unsafe fn vst2_u32(a: *mut u32, b: uint32x2x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))]
@@ -69481,7 +69481,7 @@ pub unsafe fn vst2q_u32(a: *mut u32, b: uint32x4x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))]
@@ -69504,7 +69504,7 @@ pub unsafe fn vst2_p8(a: *mut p8, b: poly8x8x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))]
@@ -69527,7 +69527,7 @@ pub unsafe fn vst2q_p8(a: *mut p8, b: poly8x16x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))]
@@ -69550,7 +69550,7 @@ pub unsafe fn vst2_p16(a: *mut p16, b: poly16x4x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))]
@@ -69573,7 +69573,7 @@ pub unsafe fn vst2q_p16(a: *mut p16, b: poly16x8x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -69592,7 +69592,7 @@ pub unsafe fn vst3_f16(a: *mut f16, b: float16x4x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -69611,7 +69611,7 @@ pub unsafe fn vst3q_f16(a: *mut f16, b: float16x8x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
@@ -69632,7 +69632,7 @@ pub unsafe fn vst3_f16(a: *mut f16, b: float16x4x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
@@ -69653,7 +69653,7 @@ pub unsafe fn vst3q_f16(a: *mut f16, b: float16x8x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -69669,7 +69669,7 @@ pub unsafe fn vst3_f32(a: *mut f32, b: float32x2x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -69685,7 +69685,7 @@ pub unsafe fn vst3q_f32(a: *mut f32, b: float32x4x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -69701,7 +69701,7 @@ pub unsafe fn vst3_s8(a: *mut i8, b: int8x8x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -69717,7 +69717,7 @@ pub unsafe fn vst3q_s8(a: *mut i8, b: int8x16x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -69733,7 +69733,7 @@ pub unsafe fn vst3_s16(a: *mut i16, b: int16x4x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -69749,7 +69749,7 @@ pub unsafe fn vst3q_s16(a: *mut i16, b: int16x8x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -69765,7 +69765,7 @@ pub unsafe fn vst3_s32(a: *mut i32, b: int32x2x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -69781,7 +69781,7 @@ pub unsafe fn vst3q_s32(a: *mut i32, b: int32x4x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -69800,7 +69800,7 @@ pub unsafe fn vst3_f32(a: *mut f32, b: float32x2x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -69819,7 +69819,7 @@ pub unsafe fn vst3q_f32(a: *mut f32, b: float32x4x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -69838,7 +69838,7 @@ pub unsafe fn vst3_s8(a: *mut i8, b: int8x8x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -69857,7 +69857,7 @@ pub unsafe fn vst3q_s8(a: *mut i8, b: int8x16x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -69876,7 +69876,7 @@ pub unsafe fn vst3_s16(a: *mut i16, b: int16x4x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -69895,7 +69895,7 @@ pub unsafe fn vst3q_s16(a: *mut i16, b: int16x8x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -69914,7 +69914,7 @@ pub unsafe fn vst3_s32(a: *mut i32, b: int32x2x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -69933,7 +69933,7 @@ pub unsafe fn vst3q_s32(a: *mut i32, b: int32x4x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -69961,7 +69961,7 @@ pub unsafe fn vst3_lane_f16<const LANE: i32>(a: *mut f16, b: float16x4x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -69989,7 +69989,7 @@ pub unsafe fn vst3q_lane_f16<const LANE: i32>(a: *mut f16, b: float16x8x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[rustc_legacy_const_generics(2)]
@@ -70012,7 +70012,7 @@ pub unsafe fn vst3_lane_f16<const LANE: i32>(a: *mut f16, b: float16x4x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[rustc_legacy_const_generics(2)]
@@ -70035,7 +70035,7 @@ pub unsafe fn vst3q_lane_f16<const LANE: i32>(a: *mut f16, b: float16x8x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vst3, LANE = 0))]
@@ -70060,7 +70060,7 @@ pub unsafe fn vst3_lane_f32<const LANE: i32>(a: *mut f32, b: float32x2x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vst3, LANE = 0))]
@@ -70085,7 +70085,7 @@ pub unsafe fn vst3q_lane_f32<const LANE: i32>(a: *mut f32, b: float32x4x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vst3, LANE = 0))]
@@ -70103,7 +70103,7 @@ pub unsafe fn vst3_lane_s8<const LANE: i32>(a: *mut i8, b: int8x8x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vst3, LANE = 0))]
@@ -70128,7 +70128,7 @@ pub unsafe fn vst3_lane_s16<const LANE: i32>(a: *mut i16, b: int16x4x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vst3, LANE = 0))]
@@ -70153,7 +70153,7 @@ pub unsafe fn vst3q_lane_s16<const LANE: i32>(a: *mut i16, b: int16x8x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vst3, LANE = 0))]
@@ -70178,7 +70178,7 @@ pub unsafe fn vst3_lane_s32<const LANE: i32>(a: *mut i32, b: int32x2x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vst3, LANE = 0))]
@@ -70203,7 +70203,7 @@ pub unsafe fn vst3q_lane_s32<const LANE: i32>(a: *mut i32, b: int32x4x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[rustc_legacy_const_generics(2)]
@@ -70224,7 +70224,7 @@ pub unsafe fn vst3_lane_f32<const LANE: i32>(a: *mut f32, b: float32x2x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[rustc_legacy_const_generics(2)]
@@ -70245,7 +70245,7 @@ pub unsafe fn vst3q_lane_f32<const LANE: i32>(a: *mut f32, b: float32x4x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[rustc_legacy_const_generics(2)]
@@ -70266,7 +70266,7 @@ pub unsafe fn vst3_lane_s8<const LANE: i32>(a: *mut i8, b: int8x8x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[rustc_legacy_const_generics(2)]
@@ -70287,7 +70287,7 @@ pub unsafe fn vst3_lane_s16<const LANE: i32>(a: *mut i16, b: int16x4x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[rustc_legacy_const_generics(2)]
@@ -70308,7 +70308,7 @@ pub unsafe fn vst3q_lane_s16<const LANE: i32>(a: *mut i16, b: int16x8x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[rustc_legacy_const_generics(2)]
@@ -70329,7 +70329,7 @@ pub unsafe fn vst3_lane_s32<const LANE: i32>(a: *mut i32, b: int32x2x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[rustc_legacy_const_generics(2)]
@@ -70350,7 +70350,7 @@ pub unsafe fn vst3q_lane_s32<const LANE: i32>(a: *mut i32, b: int32x4x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3, LANE = 0))]
@@ -70375,7 +70375,7 @@ pub unsafe fn vst3_lane_u8<const LANE: i32>(a: *mut u8, b: uint8x8x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3, LANE = 0))]
@@ -70400,7 +70400,7 @@ pub unsafe fn vst3_lane_u16<const LANE: i32>(a: *mut u16, b: uint16x4x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3, LANE = 0))]
@@ -70425,7 +70425,7 @@ pub unsafe fn vst3q_lane_u16<const LANE: i32>(a: *mut u16, b: uint16x8x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3, LANE = 0))]
@@ -70450,7 +70450,7 @@ pub unsafe fn vst3_lane_u32<const LANE: i32>(a: *mut u32, b: uint32x2x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3, LANE = 0))]
@@ -70475,7 +70475,7 @@ pub unsafe fn vst3q_lane_u32<const LANE: i32>(a: *mut u32, b: uint32x4x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3, LANE = 0))]
@@ -70500,7 +70500,7 @@ pub unsafe fn vst3_lane_p8<const LANE: i32>(a: *mut p8, b: poly8x8x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3, LANE = 0))]
@@ -70525,7 +70525,7 @@ pub unsafe fn vst3_lane_p16<const LANE: i32>(a: *mut p16, b: poly16x4x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3, LANE = 0))]
@@ -70550,7 +70550,7 @@ pub unsafe fn vst3q_lane_p16<const LANE: i32>(a: *mut p16, b: poly16x8x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -70573,7 +70573,7 @@ pub unsafe fn vst3_p64(a: *mut p64, b: poly64x1x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -70592,7 +70592,7 @@ pub unsafe fn vst3_s64(a: *mut i64, b: int64x1x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -70608,7 +70608,7 @@ pub unsafe fn vst3_s64(a: *mut i64, b: int64x1x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -70631,7 +70631,7 @@ pub unsafe fn vst3_u64(a: *mut u64, b: uint64x1x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))]
@@ -70654,7 +70654,7 @@ pub unsafe fn vst3_u8(a: *mut u8, b: uint8x8x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))]
@@ -70677,7 +70677,7 @@ pub unsafe fn vst3q_u8(a: *mut u8, b: uint8x16x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))]
@@ -70700,7 +70700,7 @@ pub unsafe fn vst3_u16(a: *mut u16, b: uint16x4x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))]
@@ -70723,7 +70723,7 @@ pub unsafe fn vst3q_u16(a: *mut u16, b: uint16x8x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))]
@@ -70746,7 +70746,7 @@ pub unsafe fn vst3_u32(a: *mut u32, b: uint32x2x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))]
@@ -70769,7 +70769,7 @@ pub unsafe fn vst3q_u32(a: *mut u32, b: uint32x4x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))]
@@ -70792,7 +70792,7 @@ pub unsafe fn vst3_p8(a: *mut p8, b: poly8x8x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))]
@@ -70815,7 +70815,7 @@ pub unsafe fn vst3q_p8(a: *mut p8, b: poly8x16x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))]
@@ -70838,7 +70838,7 @@ pub unsafe fn vst3_p16(a: *mut p16, b: poly16x4x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))]
@@ -70861,7 +70861,7 @@ pub unsafe fn vst3q_p16(a: *mut p16, b: poly16x8x3_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -70887,7 +70887,7 @@ pub unsafe fn vst4_f16(a: *mut f16, b: float16x4x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -70913,7 +70913,7 @@ pub unsafe fn vst4q_f16(a: *mut f16, b: float16x8x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
@@ -70934,7 +70934,7 @@ pub unsafe fn vst4_f16(a: *mut f16, b: float16x4x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
@@ -70955,7 +70955,7 @@ pub unsafe fn vst4q_f16(a: *mut f16, b: float16x8x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -70978,7 +70978,7 @@ pub unsafe fn vst4_f32(a: *mut f32, b: float32x2x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -71001,7 +71001,7 @@ pub unsafe fn vst4q_f32(a: *mut f32, b: float32x4x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -71017,7 +71017,7 @@ pub unsafe fn vst4_s8(a: *mut i8, b: int8x8x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -71040,7 +71040,7 @@ pub unsafe fn vst4q_s8(a: *mut i8, b: int8x16x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -71063,7 +71063,7 @@ pub unsafe fn vst4_s16(a: *mut i16, b: int16x4x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -71086,7 +71086,7 @@ pub unsafe fn vst4q_s16(a: *mut i16, b: int16x8x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -71109,7 +71109,7 @@ pub unsafe fn vst4_s32(a: *mut i32, b: int32x2x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -71132,7 +71132,7 @@ pub unsafe fn vst4q_s32(a: *mut i32, b: int32x4x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -71151,7 +71151,7 @@ pub unsafe fn vst4_f32(a: *mut f32, b: float32x2x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -71170,7 +71170,7 @@ pub unsafe fn vst4q_f32(a: *mut f32, b: float32x4x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -71189,7 +71189,7 @@ pub unsafe fn vst4_s8(a: *mut i8, b: int8x8x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -71208,7 +71208,7 @@ pub unsafe fn vst4q_s8(a: *mut i8, b: int8x16x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -71227,7 +71227,7 @@ pub unsafe fn vst4_s16(a: *mut i16, b: int16x4x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -71246,7 +71246,7 @@ pub unsafe fn vst4q_s16(a: *mut i16, b: int16x8x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -71265,7 +71265,7 @@ pub unsafe fn vst4_s32(a: *mut i32, b: int32x2x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -71284,7 +71284,7 @@ pub unsafe fn vst4q_s32(a: *mut i32, b: int32x4x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -71313,7 +71313,7 @@ pub unsafe fn vst4_lane_f16<const LANE: i32>(a: *mut f16, b: float16x4x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -71342,7 +71342,7 @@ pub unsafe fn vst4q_lane_f16<const LANE: i32>(a: *mut f16, b: float16x8x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[rustc_legacy_const_generics(2)]
@@ -71372,7 +71372,7 @@ pub unsafe fn vst4_lane_f16<const LANE: i32>(a: *mut f16, b: float16x4x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[rustc_legacy_const_generics(2)]
@@ -71402,7 +71402,7 @@ pub unsafe fn vst4q_lane_f16<const LANE: i32>(a: *mut f16, b: float16x8x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vst4, LANE = 0))]
@@ -71428,7 +71428,7 @@ pub unsafe fn vst4_lane_f32<const LANE: i32>(a: *mut f32, b: float32x2x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vst4, LANE = 0))]
@@ -71454,7 +71454,7 @@ pub unsafe fn vst4q_lane_f32<const LANE: i32>(a: *mut f32, b: float32x4x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vst4, LANE = 0))]
@@ -71480,7 +71480,7 @@ pub unsafe fn vst4_lane_s8<const LANE: i32>(a: *mut i8, b: int8x8x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vst4, LANE = 0))]
@@ -71506,7 +71506,7 @@ pub unsafe fn vst4_lane_s16<const LANE: i32>(a: *mut i16, b: int16x4x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vst4, LANE = 0))]
@@ -71532,7 +71532,7 @@ pub unsafe fn vst4q_lane_s16<const LANE: i32>(a: *mut i16, b: int16x8x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vst4, LANE = 0))]
@@ -71558,7 +71558,7 @@ pub unsafe fn vst4_lane_s32<const LANE: i32>(a: *mut i32, b: int32x2x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[cfg_attr(test, assert_instr(vst4, LANE = 0))]
@@ -71584,7 +71584,7 @@ pub unsafe fn vst4q_lane_s32<const LANE: i32>(a: *mut i32, b: int32x4x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[rustc_legacy_const_generics(2)]
@@ -71612,7 +71612,7 @@ pub unsafe fn vst4_lane_f32<const LANE: i32>(a: *mut f32, b: float32x2x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_f32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[rustc_legacy_const_generics(2)]
@@ -71640,7 +71640,7 @@ pub unsafe fn vst4q_lane_f32<const LANE: i32>(a: *mut f32, b: float32x4x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[rustc_legacy_const_generics(2)]
@@ -71661,7 +71661,7 @@ pub unsafe fn vst4_lane_s8<const LANE: i32>(a: *mut i8, b: int8x8x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[rustc_legacy_const_generics(2)]
@@ -71689,7 +71689,7 @@ pub unsafe fn vst4_lane_s16<const LANE: i32>(a: *mut i16, b: int16x4x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[rustc_legacy_const_generics(2)]
@@ -71717,7 +71717,7 @@ pub unsafe fn vst4q_lane_s16<const LANE: i32>(a: *mut i16, b: int16x8x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[rustc_legacy_const_generics(2)]
@@ -71745,7 +71745,7 @@ pub unsafe fn vst4_lane_s32<const LANE: i32>(a: *mut i32, b: int32x2x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_s32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[rustc_legacy_const_generics(2)]
@@ -71773,7 +71773,7 @@ pub unsafe fn vst4q_lane_s32<const LANE: i32>(a: *mut i32, b: int32x4x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4, LANE = 0))]
@@ -71798,7 +71798,7 @@ pub unsafe fn vst4_lane_u8<const LANE: i32>(a: *mut u8, b: uint8x8x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4, LANE = 0))]
@@ -71823,7 +71823,7 @@ pub unsafe fn vst4_lane_u16<const LANE: i32>(a: *mut u16, b: uint16x4x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4, LANE = 0))]
@@ -71848,7 +71848,7 @@ pub unsafe fn vst4q_lane_u16<const LANE: i32>(a: *mut u16, b: uint16x8x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4, LANE = 0))]
@@ -71873,7 +71873,7 @@ pub unsafe fn vst4_lane_u32<const LANE: i32>(a: *mut u32, b: uint32x2x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4, LANE = 0))]
@@ -71898,7 +71898,7 @@ pub unsafe fn vst4q_lane_u32<const LANE: i32>(a: *mut u32, b: uint32x4x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4, LANE = 0))]
@@ -71923,7 +71923,7 @@ pub unsafe fn vst4_lane_p8<const LANE: i32>(a: *mut p8, b: poly8x8x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4, LANE = 0))]
@@ -71948,7 +71948,7 @@ pub unsafe fn vst4_lane_p16<const LANE: i32>(a: *mut p16, b: poly16x4x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4, LANE = 0))]
@@ -71973,7 +71973,7 @@ pub unsafe fn vst4q_lane_p16<const LANE: i32>(a: *mut p16, b: poly16x8x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -71996,7 +71996,7 @@ pub unsafe fn vst4_p64(a: *mut p64, b: poly64x1x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -72019,7 +72019,7 @@ pub unsafe fn vst4_s64(a: *mut i64, b: int64x1x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -72038,7 +72038,7 @@ pub unsafe fn vst4_s64(a: *mut i64, b: int64x1x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -72061,7 +72061,7 @@ pub unsafe fn vst4_u64(a: *mut u64, b: uint64x1x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))]
@@ -72084,7 +72084,7 @@ pub unsafe fn vst4_u8(a: *mut u8, b: uint8x8x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))]
@@ -72107,7 +72107,7 @@ pub unsafe fn vst4q_u8(a: *mut u8, b: uint8x16x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))]
@@ -72130,7 +72130,7 @@ pub unsafe fn vst4_u16(a: *mut u16, b: uint16x4x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))]
@@ -72153,7 +72153,7 @@ pub unsafe fn vst4q_u16(a: *mut u16, b: uint16x8x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))]
@@ -72176,7 +72176,7 @@ pub unsafe fn vst4_u32(a: *mut u32, b: uint32x2x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_u32)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))]
@@ -72199,7 +72199,7 @@ pub unsafe fn vst4q_u32(a: *mut u32, b: uint32x4x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))]
@@ -72222,7 +72222,7 @@ pub unsafe fn vst4_p8(a: *mut p8, b: poly8x8x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))]
@@ -72245,7 +72245,7 @@ pub unsafe fn vst4q_p8(a: *mut p8, b: poly8x16x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))]
@@ -72268,7 +72268,7 @@ pub unsafe fn vst4_p16(a: *mut p16, b: poly16x4x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))]
@@ -72291,7 +72291,7 @@ pub unsafe fn vst4q_p16(a: *mut p16, b: poly16x8x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstrq_p128)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -72312,7 +72312,7 @@ pub unsafe fn vstrq_p128(a: *mut p128, b: p128) {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.f16"))]
 #[cfg_attr(
@@ -72334,7 +72334,7 @@ pub fn vsub_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.f16"))]
 #[cfg_attr(
@@ -72356,7 +72356,7 @@ pub fn vsubq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.f32"))]
@@ -72377,7 +72377,7 @@ pub fn vsub_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.f32"))]
@@ -72398,7 +72398,7 @@ pub fn vsubq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i16"))]
@@ -72419,7 +72419,7 @@ pub fn vsub_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i16"))]
@@ -72440,7 +72440,7 @@ pub fn vsubq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i16"))]
@@ -72461,7 +72461,7 @@ pub fn vsub_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i16"))]
@@ -72482,7 +72482,7 @@ pub fn vsubq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i32"))]
@@ -72503,7 +72503,7 @@ pub fn vsub_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i32"))]
@@ -72524,7 +72524,7 @@ pub fn vsubq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i32"))]
@@ -72545,7 +72545,7 @@ pub fn vsub_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i32"))]
@@ -72566,7 +72566,7 @@ pub fn vsubq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i64"))]
@@ -72587,7 +72587,7 @@ pub fn vsub_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i64"))]
@@ -72608,7 +72608,7 @@ pub fn vsubq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i64"))]
@@ -72629,7 +72629,7 @@ pub fn vsub_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i64"))]
@@ -72650,7 +72650,7 @@ pub fn vsubq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i8"))]
@@ -72671,7 +72671,7 @@ pub fn vsub_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i8"))]
@@ -72692,7 +72692,7 @@ pub fn vsubq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i8"))]
@@ -72713,7 +72713,7 @@ pub fn vsub_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i8"))]
@@ -72734,7 +72734,7 @@ pub fn vsubq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_high_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))]
@@ -72756,7 +72756,7 @@ pub fn vsubhn_high_s16(a: int8x8_t, b: int16x8_t, c: int16x8_t) -> int8x16_t {
 }
 #[doc = "Subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_high_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))]
@@ -72778,7 +72778,7 @@ pub fn vsubhn_high_s32(a: int16x4_t, b: int32x4_t, c: int32x4_t) -> int16x8_t {
 }
 #[doc = "Subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_high_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))]
@@ -72800,7 +72800,7 @@ pub fn vsubhn_high_s64(a: int32x2_t, b: int64x2_t, c: int64x2_t) -> int32x4_t {
 }
 #[doc = "Subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_high_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))]
@@ -72822,7 +72822,7 @@ pub fn vsubhn_high_u16(a: uint8x8_t, b: uint16x8_t, c: uint16x8_t) -> uint8x16_t
 }
 #[doc = "Subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_high_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))]
@@ -72844,7 +72844,7 @@ pub fn vsubhn_high_u32(a: uint16x4_t, b: uint32x4_t, c: uint32x4_t) -> uint16x8_
 }
 #[doc = "Subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_high_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))]
@@ -72866,7 +72866,7 @@ pub fn vsubhn_high_u64(a: uint32x2_t, b: uint64x2_t, c: uint64x2_t) -> uint32x4_
 }
 #[doc = "Subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))]
@@ -72888,7 +72888,7 @@ pub fn vsubhn_s16(a: int16x8_t, b: int16x8_t) -> int8x8_t {
 }
 #[doc = "Subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))]
@@ -72910,7 +72910,7 @@ pub fn vsubhn_s32(a: int32x4_t, b: int32x4_t) -> int16x4_t {
 }
 #[doc = "Subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))]
@@ -72932,7 +72932,7 @@ pub fn vsubhn_s64(a: int64x2_t, b: int64x2_t) -> int32x2_t {
 }
 #[doc = "Subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))]
@@ -72954,7 +72954,7 @@ pub fn vsubhn_u16(a: uint16x8_t, b: uint16x8_t) -> uint8x8_t {
 }
 #[doc = "Subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))]
@@ -72976,7 +72976,7 @@ pub fn vsubhn_u32(a: uint32x4_t, b: uint32x4_t) -> uint16x4_t {
 }
 #[doc = "Subtract returning high narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))]
@@ -72998,7 +72998,7 @@ pub fn vsubhn_u64(a: uint64x2_t, b: uint64x2_t) -> uint32x2_t {
 }
 #[doc = "Signed Subtract Long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubl))]
@@ -73023,7 +73023,7 @@ pub fn vsubl_s8(a: int8x8_t, b: int8x8_t) -> int16x8_t {
 }
 #[doc = "Signed Subtract Long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubl))]
@@ -73048,7 +73048,7 @@ pub fn vsubl_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t {
 }
 #[doc = "Signed Subtract Long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubl))]
@@ -73073,7 +73073,7 @@ pub fn vsubl_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t {
 }
 #[doc = "Unsigned Subtract Long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubl))]
@@ -73098,7 +73098,7 @@ pub fn vsubl_u8(a: uint8x8_t, b: uint8x8_t) -> uint16x8_t {
 }
 #[doc = "Unsigned Subtract Long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubl))]
@@ -73123,7 +73123,7 @@ pub fn vsubl_u16(a: uint16x4_t, b: uint16x4_t) -> uint32x4_t {
 }
 #[doc = "Unsigned Subtract Long"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubl))]
@@ -73148,7 +73148,7 @@ pub fn vsubl_u32(a: uint32x2_t, b: uint32x2_t) -> uint64x2_t {
 }
 #[doc = "Signed Subtract Wide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubw))]
@@ -73169,7 +73169,7 @@ pub fn vsubw_s8(a: int16x8_t, b: int8x8_t) -> int16x8_t {
 }
 #[doc = "Signed Subtract Wide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubw))]
@@ -73190,7 +73190,7 @@ pub fn vsubw_s16(a: int32x4_t, b: int16x4_t) -> int32x4_t {
 }
 #[doc = "Signed Subtract Wide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubw))]
@@ -73211,7 +73211,7 @@ pub fn vsubw_s32(a: int64x2_t, b: int32x2_t) -> int64x2_t {
 }
 #[doc = "Unsigned Subtract Wide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubw))]
@@ -73232,7 +73232,7 @@ pub fn vsubw_u8(a: uint16x8_t, b: uint8x8_t) -> uint16x8_t {
 }
 #[doc = "Unsigned Subtract Wide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubw))]
@@ -73253,7 +73253,7 @@ pub fn vsubw_u16(a: uint32x4_t, b: uint16x4_t) -> uint32x4_t {
 }
 #[doc = "Unsigned Subtract Wide"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubw))]
@@ -73274,7 +73274,7 @@ pub fn vsubw_u32(a: uint64x2_t, b: uint32x2_t) -> uint64x2_t {
 }
 #[doc = "Dot product index form with signed and unsigned integers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsudot_lane_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,i8mm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -73302,7 +73302,7 @@ pub fn vsudot_lane_s32<const LANE: i32>(a: int32x2_t, b: int8x8_t, c: uint8x8_t)
 }
 #[doc = "Dot product index form with signed and unsigned integers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsudot_lane_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,i8mm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -73334,7 +73334,7 @@ pub fn vsudot_lane_s32<const LANE: i32>(a: int32x2_t, b: int8x8_t, c: uint8x8_t)
 }
 #[doc = "Dot product index form with signed and unsigned integers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsudotq_lane_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,i8mm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -73363,7 +73363,7 @@ pub fn vsudotq_lane_s32<const LANE: i32>(a: int32x4_t, b: int8x16_t, c: uint8x8_
 }
 #[doc = "Dot product index form with signed and unsigned integers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsudotq_lane_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,i8mm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -73397,7 +73397,7 @@ pub fn vsudotq_lane_s32<const LANE: i32>(a: int32x4_t, b: int8x16_t, c: uint8x8_
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl1)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -73412,7 +73412,7 @@ fn vtbl1(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl1_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -73423,7 +73423,7 @@ pub fn vtbl1_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl1_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -73435,7 +73435,7 @@ pub fn vtbl1_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl1_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -73452,7 +73452,7 @@ pub fn vtbl1_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl1_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -73464,7 +73464,7 @@ pub fn vtbl1_p8(a: poly8x8_t, b: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl1_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -73481,7 +73481,7 @@ pub fn vtbl1_p8(a: poly8x8_t, b: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -73496,7 +73496,7 @@ fn vtbl2(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -73507,7 +73507,7 @@ pub fn vtbl2_s8(a: int8x8x2_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -73519,7 +73519,7 @@ pub fn vtbl2_u8(a: uint8x8x2_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -73538,7 +73538,7 @@ pub fn vtbl2_u8(a: uint8x8x2_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -73550,7 +73550,7 @@ pub fn vtbl2_p8(a: poly8x8x2_t, b: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl2_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -73569,7 +73569,7 @@ pub fn vtbl2_p8(a: poly8x8x2_t, b: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -73584,7 +73584,7 @@ fn vtbl3(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t) -> int8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -73595,7 +73595,7 @@ pub fn vtbl3_s8(a: int8x8x3_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -73614,7 +73614,7 @@ pub fn vtbl3_u8(a: uint8x8x3_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -73639,7 +73639,7 @@ pub fn vtbl3_u8(a: uint8x8x3_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -73658,7 +73658,7 @@ pub fn vtbl3_p8(a: poly8x8x3_t, b: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl3_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -73683,7 +73683,7 @@ pub fn vtbl3_p8(a: poly8x8x3_t, b: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -73698,7 +73698,7 @@ fn vtbl4(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t, e: int8x8_t) -> int
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -73709,7 +73709,7 @@ pub fn vtbl4_s8(a: int8x8x4_t, b: int8x8_t) -> int8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -73729,7 +73729,7 @@ pub fn vtbl4_u8(a: uint8x8x4_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -73756,7 +73756,7 @@ pub fn vtbl4_u8(a: uint8x8x4_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -73776,7 +73776,7 @@ pub fn vtbl4_p8(a: poly8x8x4_t, b: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl4_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -73803,7 +73803,7 @@ pub fn vtbl4_p8(a: poly8x8x4_t, b: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx1)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -73817,7 +73817,7 @@ fn vtbx1(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx1_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -73827,7 +73827,7 @@ pub fn vtbx1_s8(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx1_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -73838,7 +73838,7 @@ pub fn vtbx1_u8(a: uint8x8_t, b: uint8x8_t, c: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx1_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -73855,7 +73855,7 @@ pub fn vtbx1_u8(a: uint8x8_t, b: uint8x8_t, c: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx1_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -73866,7 +73866,7 @@ pub fn vtbx1_p8(a: poly8x8_t, b: poly8x8_t, c: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx1_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -73883,7 +73883,7 @@ pub fn vtbx1_p8(a: poly8x8_t, b: poly8x8_t, c: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -73897,7 +73897,7 @@ fn vtbx2(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t) -> int8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -73907,7 +73907,7 @@ pub fn vtbx2_s8(a: int8x8_t, b: int8x8x2_t, c: int8x8_t) -> int8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -73925,7 +73925,7 @@ pub fn vtbx2_u8(a: uint8x8_t, b: uint8x8x2_t, c: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -73949,7 +73949,7 @@ pub fn vtbx2_u8(a: uint8x8_t, b: uint8x8x2_t, c: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -73967,7 +73967,7 @@ pub fn vtbx2_p8(a: poly8x8_t, b: poly8x8x2_t, c: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx2_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -73991,7 +73991,7 @@ pub fn vtbx2_p8(a: poly8x8_t, b: poly8x8x2_t, c: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -74005,7 +74005,7 @@ fn vtbx3(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t, e: int8x8_t) -> int
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -74015,7 +74015,7 @@ pub fn vtbx3_s8(a: int8x8_t, b: int8x8x3_t, c: int8x8_t) -> int8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -74034,7 +74034,7 @@ pub fn vtbx3_u8(a: uint8x8_t, b: uint8x8x3_t, c: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -74060,7 +74060,7 @@ pub fn vtbx3_u8(a: uint8x8_t, b: uint8x8x3_t, c: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -74079,7 +74079,7 @@ pub fn vtbx3_p8(a: poly8x8_t, b: poly8x8x3_t, c: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx3_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -74105,7 +74105,7 @@ pub fn vtbx3_p8(a: poly8x8_t, b: poly8x8x3_t, c: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
 #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
@@ -74126,7 +74126,7 @@ fn vtbx4(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t, e: int8x8_t, f: int
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -74146,7 +74146,7 @@ pub fn vtbx4_s8(a: int8x8_t, b: int8x8x4_t, c: int8x8_t) -> int8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_s8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -74174,7 +74174,7 @@ pub fn vtbx4_s8(a: int8x8_t, b: int8x8x4_t, c: int8x8_t) -> int8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -74194,7 +74194,7 @@ pub fn vtbx4_u8(a: uint8x8_t, b: uint8x8x4_t, c: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_u8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -74222,7 +74222,7 @@ pub fn vtbx4_u8(a: uint8x8_t, b: uint8x8x4_t, c: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -74242,7 +74242,7 @@ pub fn vtbx4_p8(a: poly8x8_t, b: poly8x8x4_t, c: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Extended table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbx4_p8)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -74270,7 +74270,7 @@ pub fn vtbx4_p8(a: poly8x8_t, b: poly8x8x4_t, c: uint8x8_t) -> poly8x8_t {
 }
 #[doc = "Transpose elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
 #[cfg_attr(
@@ -74300,7 +74300,7 @@ pub fn vtrn_f16(a: float16x4_t, b: float16x4_t) -> float16x4x2_t {
 }
 #[doc = "Transpose elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
 #[cfg_attr(
@@ -74330,7 +74330,7 @@ pub fn vtrnq_f16(a: float16x8_t, b: float16x8_t) -> float16x8x2_t {
 }
 #[doc = "Transpose elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
@@ -74359,7 +74359,7 @@ pub fn vtrn_f32(a: float32x2_t, b: float32x2_t) -> float32x2x2_t {
 }
 #[doc = "Transpose elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
@@ -74388,7 +74388,7 @@ pub fn vtrn_s32(a: int32x2_t, b: int32x2_t) -> int32x2x2_t {
 }
 #[doc = "Transpose elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
@@ -74417,7 +74417,7 @@ pub fn vtrn_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2x2_t {
 }
 #[doc = "Transpose elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
@@ -74446,7 +74446,7 @@ pub fn vtrnq_f32(a: float32x4_t, b: float32x4_t) -> float32x4x2_t {
 }
 #[doc = "Transpose elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
@@ -74475,7 +74475,7 @@ pub fn vtrn_s8(a: int8x8_t, b: int8x8_t) -> int8x8x2_t {
 }
 #[doc = "Transpose elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
@@ -74512,7 +74512,7 @@ pub fn vtrnq_s8(a: int8x16_t, b: int8x16_t) -> int8x16x2_t {
 }
 #[doc = "Transpose elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
@@ -74541,7 +74541,7 @@ pub fn vtrn_s16(a: int16x4_t, b: int16x4_t) -> int16x4x2_t {
 }
 #[doc = "Transpose elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
@@ -74570,7 +74570,7 @@ pub fn vtrnq_s16(a: int16x8_t, b: int16x8_t) -> int16x8x2_t {
 }
 #[doc = "Transpose elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
@@ -74599,7 +74599,7 @@ pub fn vtrnq_s32(a: int32x4_t, b: int32x4_t) -> int32x4x2_t {
 }
 #[doc = "Transpose elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
@@ -74628,7 +74628,7 @@ pub fn vtrn_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8x2_t {
 }
 #[doc = "Transpose elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
@@ -74665,7 +74665,7 @@ pub fn vtrnq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16x2_t {
 }
 #[doc = "Transpose elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
@@ -74694,7 +74694,7 @@ pub fn vtrn_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4x2_t {
 }
 #[doc = "Transpose elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
@@ -74723,7 +74723,7 @@ pub fn vtrnq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8x2_t {
 }
 #[doc = "Transpose elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
@@ -74752,7 +74752,7 @@ pub fn vtrnq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4x2_t {
 }
 #[doc = "Transpose elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
@@ -74781,7 +74781,7 @@ pub fn vtrn_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8x2_t {
 }
 #[doc = "Transpose elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
@@ -74818,7 +74818,7 @@ pub fn vtrnq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16x2_t {
 }
 #[doc = "Transpose elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_p16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
@@ -74847,7 +74847,7 @@ pub fn vtrn_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4x2_t {
 }
 #[doc = "Transpose elements"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_p16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
@@ -74876,7 +74876,7 @@ pub fn vtrnq_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8x2_t {
 }
 #[doc = "Signed compare bitwise Test bits nonzero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
@@ -74901,7 +74901,7 @@ pub fn vtst_s8(a: int8x8_t, b: int8x8_t) -> uint8x8_t {
 }
 #[doc = "Signed compare bitwise Test bits nonzero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
@@ -74926,7 +74926,7 @@ pub fn vtstq_s8(a: int8x16_t, b: int8x16_t) -> uint8x16_t {
 }
 #[doc = "Signed compare bitwise Test bits nonzero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
@@ -74951,7 +74951,7 @@ pub fn vtst_s16(a: int16x4_t, b: int16x4_t) -> uint16x4_t {
 }
 #[doc = "Signed compare bitwise Test bits nonzero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
@@ -74976,7 +74976,7 @@ pub fn vtstq_s16(a: int16x8_t, b: int16x8_t) -> uint16x8_t {
 }
 #[doc = "Signed compare bitwise Test bits nonzero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
@@ -75001,7 +75001,7 @@ pub fn vtst_s32(a: int32x2_t, b: int32x2_t) -> uint32x2_t {
 }
 #[doc = "Signed compare bitwise Test bits nonzero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
@@ -75026,7 +75026,7 @@ pub fn vtstq_s32(a: int32x4_t, b: int32x4_t) -> uint32x4_t {
 }
 #[doc = "Signed compare bitwise Test bits nonzero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
@@ -75051,7 +75051,7 @@ pub fn vtst_p8(a: poly8x8_t, b: poly8x8_t) -> uint8x8_t {
 }
 #[doc = "Signed compare bitwise Test bits nonzero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
@@ -75076,7 +75076,7 @@ pub fn vtstq_p8(a: poly8x16_t, b: poly8x16_t) -> uint8x16_t {
 }
 #[doc = "Signed compare bitwise Test bits nonzero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_p16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
@@ -75101,7 +75101,7 @@ pub fn vtst_p16(a: poly16x4_t, b: poly16x4_t) -> uint16x4_t {
 }
 #[doc = "Signed compare bitwise Test bits nonzero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_p16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
@@ -75126,7 +75126,7 @@ pub fn vtstq_p16(a: poly16x8_t, b: poly16x8_t) -> uint16x8_t {
 }
 #[doc = "Unsigned compare bitwise Test bits nonzero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
@@ -75151,7 +75151,7 @@ pub fn vtst_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
 }
 #[doc = "Unsigned compare bitwise Test bits nonzero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
@@ -75176,7 +75176,7 @@ pub fn vtstq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
 }
 #[doc = "Unsigned compare bitwise Test bits nonzero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
@@ -75201,7 +75201,7 @@ pub fn vtst_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
 }
 #[doc = "Unsigned compare bitwise Test bits nonzero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
@@ -75226,7 +75226,7 @@ pub fn vtstq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
 }
 #[doc = "Unsigned compare bitwise Test bits nonzero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
@@ -75251,7 +75251,7 @@ pub fn vtst_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 }
 #[doc = "Unsigned compare bitwise Test bits nonzero"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))]
@@ -75276,7 +75276,7 @@ pub fn vtstq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 }
 #[doc = "Dot product index form with unsigned and signed integers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdot_lane_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,i8mm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -75304,7 +75304,7 @@ pub fn vusdot_lane_s32<const LANE: i32>(a: int32x2_t, b: uint8x8_t, c: int8x8_t)
 }
 #[doc = "Dot product index form with unsigned and signed integers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdot_lane_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,i8mm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -75336,7 +75336,7 @@ pub fn vusdot_lane_s32<const LANE: i32>(a: int32x2_t, b: uint8x8_t, c: int8x8_t)
 }
 #[doc = "Dot product index form with unsigned and signed integers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdotq_lane_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,i8mm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -75365,7 +75365,7 @@ pub fn vusdotq_lane_s32<const LANE: i32>(a: int32x4_t, b: uint8x16_t, c: int8x8_
 }
 #[doc = "Dot product index form with unsigned and signed integers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdotq_lane_s32)"]
-#[inline]
+#[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,i8mm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -75399,7 +75399,7 @@ pub fn vusdotq_lane_s32<const LANE: i32>(a: int32x4_t, b: uint8x16_t, c: int8x8_
 }
 #[doc = "Dot product vector form with unsigned and signed integers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdot_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,i8mm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vusdot))]
@@ -75428,7 +75428,7 @@ pub fn vusdot_s32(a: int32x2_t, b: uint8x8_t, c: int8x8_t) -> int32x2_t {
 }
 #[doc = "Dot product vector form with unsigned and signed integers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdotq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,i8mm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vusdot))]
@@ -75457,7 +75457,7 @@ pub fn vusdotq_s32(a: int32x4_t, b: uint8x16_t, c: int8x16_t) -> int32x4_t {
 }
 #[doc = "Unsigned and signed 8-bit integer matrix multiply-accumulate"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusmmlaq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,i8mm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
@@ -75486,7 +75486,7 @@ pub fn vusmmlaq_s32(a: int32x4_t, b: uint8x16_t, c: int8x16_t) -> int32x4_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
 #[cfg_attr(
@@ -75516,7 +75516,7 @@ pub fn vuzp_f16(a: float16x4_t, b: float16x4_t) -> float16x4x2_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
 #[cfg_attr(
@@ -75546,7 +75546,7 @@ pub fn vuzpq_f16(a: float16x8_t, b: float16x8_t) -> float16x8x2_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
@@ -75575,7 +75575,7 @@ pub fn vuzp_f32(a: float32x2_t, b: float32x2_t) -> float32x2x2_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
@@ -75604,7 +75604,7 @@ pub fn vuzp_s32(a: int32x2_t, b: int32x2_t) -> int32x2x2_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
@@ -75633,7 +75633,7 @@ pub fn vuzp_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2x2_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
@@ -75662,7 +75662,7 @@ pub fn vuzpq_f32(a: float32x4_t, b: float32x4_t) -> float32x4x2_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
@@ -75691,7 +75691,7 @@ pub fn vuzp_s8(a: int8x8_t, b: int8x8_t) -> int8x8x2_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
@@ -75728,7 +75728,7 @@ pub fn vuzpq_s8(a: int8x16_t, b: int8x16_t) -> int8x16x2_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
@@ -75757,7 +75757,7 @@ pub fn vuzp_s16(a: int16x4_t, b: int16x4_t) -> int16x4x2_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
@@ -75786,7 +75786,7 @@ pub fn vuzpq_s16(a: int16x8_t, b: int16x8_t) -> int16x8x2_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
@@ -75815,7 +75815,7 @@ pub fn vuzpq_s32(a: int32x4_t, b: int32x4_t) -> int32x4x2_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
@@ -75844,7 +75844,7 @@ pub fn vuzp_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8x2_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
@@ -75881,7 +75881,7 @@ pub fn vuzpq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16x2_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
@@ -75910,7 +75910,7 @@ pub fn vuzp_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4x2_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
@@ -75939,7 +75939,7 @@ pub fn vuzpq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8x2_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
@@ -75968,7 +75968,7 @@ pub fn vuzpq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4x2_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
@@ -75997,7 +75997,7 @@ pub fn vuzp_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8x2_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
@@ -76034,7 +76034,7 @@ pub fn vuzpq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16x2_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_p16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
@@ -76063,7 +76063,7 @@ pub fn vuzp_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4x2_t {
 }
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_p16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
@@ -76092,7 +76092,7 @@ pub fn vuzpq_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8x2_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vzip.16"))]
 #[cfg_attr(
@@ -76122,7 +76122,7 @@ pub fn vzip_f16(a: float16x4_t, b: float16x4_t) -> float16x4x2_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_f16)"]
-#[inline]
+#[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vzip.16"))]
 #[cfg_attr(
@@ -76152,7 +76152,7 @@ pub fn vzipq_f16(a: float16x8_t, b: float16x8_t) -> float16x8x2_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
@@ -76181,7 +76181,7 @@ pub fn vzip_f32(a: float32x2_t, b: float32x2_t) -> float32x2x2_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
@@ -76210,7 +76210,7 @@ pub fn vzip_s32(a: int32x2_t, b: int32x2_t) -> int32x2x2_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
@@ -76239,7 +76239,7 @@ pub fn vzip_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2x2_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))]
@@ -76268,7 +76268,7 @@ pub fn vzip_s8(a: int8x8_t, b: int8x8_t) -> int8x8x2_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))]
@@ -76297,7 +76297,7 @@ pub fn vzip_s16(a: int16x4_t, b: int16x4_t) -> int16x4x2_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))]
@@ -76326,7 +76326,7 @@ pub fn vzip_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8x2_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))]
@@ -76355,7 +76355,7 @@ pub fn vzip_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4x2_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))]
@@ -76384,7 +76384,7 @@ pub fn vzip_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8x2_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_p16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))]
@@ -76413,7 +76413,7 @@ pub fn vzip_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4x2_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_f32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
@@ -76442,7 +76442,7 @@ pub fn vzipq_f32(a: float32x4_t, b: float32x4_t) -> float32x4x2_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_s8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
@@ -76479,7 +76479,7 @@ pub fn vzipq_s8(a: int8x16_t, b: int8x16_t) -> int8x16x2_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_s16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
@@ -76508,7 +76508,7 @@ pub fn vzipq_s16(a: int16x8_t, b: int16x8_t) -> int16x8x2_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_s32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
@@ -76537,7 +76537,7 @@ pub fn vzipq_s32(a: int32x4_t, b: int32x4_t) -> int32x4x2_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_u8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
@@ -76574,7 +76574,7 @@ pub fn vzipq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16x2_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_u16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
@@ -76603,7 +76603,7 @@ pub fn vzipq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8x2_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_u32)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
@@ -76632,7 +76632,7 @@ pub fn vzipq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4x2_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_p8)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
@@ -76669,7 +76669,7 @@ pub fn vzipq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16x2_t {
 }
 #[doc = "Zip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_p16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
diff --git a/library/stdarch/crates/core_arch/src/lib.rs b/library/stdarch/crates/core_arch/src/lib.rs
index d69089b95b0c..3992eaee30fd 100644
--- a/library/stdarch/crates/core_arch/src/lib.rs
+++ b/library/stdarch/crates/core_arch/src/lib.rs
@@ -32,6 +32,7 @@
     x86_amx_intrinsics,
     f16,
     aarch64_unstable_target_feature,
+    target_feature_inline_always,
     bigint_helper_methods,
     funnel_shifts,
     avx10_target_feature,
diff --git a/library/stdarch/crates/stdarch-gen-arm/src/intrinsic.rs b/library/stdarch/crates/stdarch-gen-arm/src/intrinsic.rs
index 0cdff6ff6c39..71301c5ba6ce 100644
--- a/library/stdarch/crates/stdarch-gen-arm/src/intrinsic.rs
+++ b/library/stdarch/crates/stdarch-gen-arm/src/intrinsic.rs
@@ -1736,7 +1736,7 @@ fn create_tokens(intrinsic: &Intrinsic, endianness: Endianness, tokens: &mut Tok
         );
     }
 
-    tokens.append_all(quote! { #[inline] });
+    tokens.append_all(quote! { #[inline(always)] });
 
     match endianness {
         Endianness::Little => tokens.append_all(quote! { #[cfg(target_endian = "little")] }),

From 9a5aa90516602b288de34dd65161d90f2db202a6 Mon Sep 17 00:00:00 2001
From: Eric Huss <eric@huss.org>
Date: Mon, 12 Jan 2026 09:34:11 -0800
Subject: [PATCH 14/97] Add some clarifications and fixes for fmt syntax

This tries to clarify a few things regarding fmt syntax:

- The comment on `Parser::word` seems to be wrong, as that
  underscore-prefixed words are just fine. This was changed in
  https://github.com/rust-lang/rust/pull/66847.
- I struggled to follow the description of the width argument. It
  referred to a "second argument", but I don't know what second argument
  it is referring to (which is the first?). Either way, I rewrote the
  paragraph to try to be a little more explicit, and to use shorter
  sentences.
- The description of the precision argument wasn't really clear about
  the distinction of an Nth argument and a named argument. I added
  a sentence to try to emphasize the difference.
- `IDENTIFIER_OR_KEYWORD` was changed recently in
  https://github.com/rust-lang/reference/pull/2049 to include bare `_`.
  But fmt named arguments are not allowed to be a bare `_`.
---
 compiler/rustc_parse_format/src/lib.rs |  2 +-
 library/alloc/src/fmt.rs               | 15 ++++++++++-----
 2 files changed, 11 insertions(+), 6 deletions(-)

diff --git a/compiler/rustc_parse_format/src/lib.rs b/compiler/rustc_parse_format/src/lib.rs
index 86326fc6536c..a687a45480dc 100644
--- a/compiler/rustc_parse_format/src/lib.rs
+++ b/compiler/rustc_parse_format/src/lib.rs
@@ -753,7 +753,7 @@ impl<'input> Parser<'input> {
     }
 
     /// Parses a word starting at the current position. A word is the same as a
-    /// Rust identifier, except that it can't start with `_` character.
+    /// Rust identifier or keyword, except that it can't be a bare `_` character.
     fn word(&mut self) -> &'input str {
         let index = self.input_vec_index;
         match self.peek() {
diff --git a/library/alloc/src/fmt.rs b/library/alloc/src/fmt.rs
index 3d7c580be8c9..e3ff2ba51aba 100644
--- a/library/alloc/src/fmt.rs
+++ b/library/alloc/src/fmt.rs
@@ -136,9 +136,10 @@
 //! padding specified by fill/alignment will be used to take up the required
 //! space (see below).
 //!
-//! The value for the width can also be provided as a [`usize`] in the list of
-//! parameters by adding a postfix `$`, indicating that the second argument is
-//! a [`usize`] specifying the width.
+//! The width can also be provided dynamically by referencing another argument
+//! with a `$` suffix. Use `{:N$}` to reference the Nth positional argument
+//! (where N is an integer), or `{:name$}` to reference a named argument. The
+//! referenced argument must be of type [`usize`].
 //!
 //! Referring to an argument with the dollar syntax does not affect the "next
 //! argument" counter, so it's usually a good idea to refer to arguments by
@@ -236,7 +237,8 @@
 //!
 //! 2. An integer or name followed by dollar sign `.N$`:
 //!
-//!    use format *argument* `N` (which must be a `usize`) as the precision.
+//!    use the value of format *argument* `N` (which must be a `usize`) as the precision.
+//!    An integer refers to a positional argument, and a name refers to a named argument.
 //!
 //! 3. An asterisk `.*`:
 //!
@@ -363,7 +365,10 @@
 //! - `ws` is any character for which [`char::is_whitespace`] returns `true`, has no semantic
 //!   meaning and is completely optional,
 //! - `integer` is a decimal integer that may contain leading zeroes and must fit into an `usize` and
-//! - `identifier` is an `IDENTIFIER_OR_KEYWORD` (not an `IDENTIFIER`) as defined by the [Rust language reference](https://doc.rust-lang.org/reference/identifiers.html).
+//! - `identifier` is an `IDENTIFIER_OR_KEYWORD` (not an `IDENTIFIER`) as
+//!   defined by the [Rust language
+//!   reference](https://doc.rust-lang.org/reference/identifiers.html), except
+//!   for a bare `_`.
 //!
 //! # Formatting traits
 //!

From 3777ebc6ca156092e47318a20c9c2ae40d9813e2 Mon Sep 17 00:00:00 2001
From: Moulins <arthur.heuillard@orange.fr>
Date: Thu, 18 Dec 2025 19:23:37 +0100
Subject: [PATCH 15/97] Don't expose redundant information in `rustc_public`'s
 `LayoutShape`

Enum variant layouts don't need to store a full `LayoutShape`; just storing
the fields offsets is enough and all other information can be inferred from
the parent layout:
- size, align and ABI don't make much sense for individual variants and
  should generally be taken from the parent layout instead;
- variants always have `fields: FieldsShape::Arbitrary { .. }` and
  `variant: VariantShape::Single { .. }`.
---
 compiler/rustc_public/src/abi.rs              | 19 ++++++++++++++++++-
 .../src/unstable/convert/stable/abi.rs        | 12 ++++++++++--
 2 files changed, 28 insertions(+), 3 deletions(-)

diff --git a/compiler/rustc_public/src/abi.rs b/compiler/rustc_public/src/abi.rs
index aced39059f6b..413bc835e50a 100644
--- a/compiler/rustc_public/src/abi.rs
+++ b/compiler/rustc_public/src/abi.rs
@@ -188,10 +188,27 @@ pub enum VariantsShape {
         tag: Scalar,
         tag_encoding: TagEncoding,
         tag_field: usize,
-        variants: Vec<LayoutShape>,
+        variants: Vec<VariantFields>,
     },
 }
 
+#[derive(Clone, Debug, PartialEq, Eq, Hash, Serialize)]
+pub struct VariantFields {
+    /// Offsets for the first byte of each field,
+    /// ordered to match the source definition order.
+    /// I.e.: It follows the same order as [super::ty::VariantDef::fields()].
+    /// This vector does not go in increasing order.
+    pub offsets: Vec<Size>,
+}
+
+impl VariantFields {
+    pub fn fields_by_offset_order(&self) -> Vec<FieldIdx> {
+        let mut indices = (0..self.offsets.len()).collect::<Vec<_>>();
+        indices.sort_by_key(|idx| self.offsets[*idx]);
+        indices
+    }
+}
+
 #[derive(Clone, Debug, PartialEq, Eq, Hash, Serialize)]
 pub enum TagEncoding {
     /// The tag directly stores the discriminant, but possibly with a smaller layout
diff --git a/compiler/rustc_public/src/unstable/convert/stable/abi.rs b/compiler/rustc_public/src/unstable/convert/stable/abi.rs
index 03328d084ee9..f6b750f75aea 100644
--- a/compiler/rustc_public/src/unstable/convert/stable/abi.rs
+++ b/compiler/rustc_public/src/unstable/convert/stable/abi.rs
@@ -11,7 +11,7 @@ use rustc_target::callconv;
 use crate::abi::{
     AddressSpace, ArgAbi, CallConvention, FieldsShape, FloatLength, FnAbi, IntegerLength,
     IntegerType, Layout, LayoutShape, PassMode, Primitive, ReprFlags, ReprOptions, Scalar,
-    TagEncoding, TyAndLayout, ValueAbi, VariantsShape, WrappingRange,
+    TagEncoding, TyAndLayout, ValueAbi, VariantFields, VariantsShape, WrappingRange,
 };
 use crate::compiler_interface::BridgeTys;
 use crate::target::MachineSize as Size;
@@ -212,7 +212,15 @@ impl<'tcx> Stable<'tcx> for rustc_abi::Variants<rustc_abi::FieldIdx, rustc_abi::
                     tag: tag.stable(tables, cx),
                     tag_encoding: tag_encoding.stable(tables, cx),
                     tag_field: tag_field.stable(tables, cx),
-                    variants: variants.iter().as_slice().stable(tables, cx),
+                    variants: variants
+                        .iter()
+                        .map(|v| match &v.fields {
+                            rustc_abi::FieldsShape::Arbitrary { offsets, .. } => VariantFields {
+                                offsets: offsets.iter().as_slice().stable(tables, cx),
+                            },
+                            _ => panic!("variant layout should be Arbitrary"),
+                        })
+                        .collect(),
                 }
             }
         }

From f09b0bc2cb7b7f43ecd6e0adee5e7b3dbc2c1290 Mon Sep 17 00:00:00 2001
From: reucru01 <reuben.cruise@arm.com>
Date: Mon, 22 Dec 2025 10:31:05 +0000
Subject: [PATCH 16/97] Creates README for stdarch-gen-arm

---
 .../stdarch/crates/stdarch-gen-arm/README.md  | 300 ++++++++++++++++++
 1 file changed, 300 insertions(+)
 create mode 100644 library/stdarch/crates/stdarch-gen-arm/README.md

diff --git a/library/stdarch/crates/stdarch-gen-arm/README.md b/library/stdarch/crates/stdarch-gen-arm/README.md
new file mode 100644
index 000000000000..4da14bcbb6c9
--- /dev/null
+++ b/library/stdarch/crates/stdarch-gen-arm/README.md
@@ -0,0 +1,300 @@
+# stdarch-gen-arm generator guide
+## Running the generator
+- Run: `cargo run --bin=stdarch-gen-arm -- crates/stdarch-gen-arm/spec`
+```
+$ cargo run --bin=stdarch-gen-arm -- crates/stdarch-gen-arm/spec
+    Finished `dev` profile [unoptimized + debuginfo] target(s) in 0.18s
+     Running `target/debug/stdarch-gen-arm crates/stdarch-gen-arm/spec`
+```
+## Input/Output
+### Input files (intrinsic YAML definitions)
+ - `crates/stdarch-gen-arm/spec/<feature>/*.spec.yml`
+### Output files
+ - Generated intrinsics:
+	 - `crates/core_arch/src/<arch>/<feature>/generated.rs`
+ - Generated load/store tests:
+	 - `crates/core_arch/src/<arch>/<feature>/ld_st_tests_<arch>.rs`
+	 - Only generated when `test: { load: <idx> }` or `test: { store: <idx> }` is set for SVE/SVE2 intrinsics.
+## `.spec.yml` file anatomy
+```
+---
+Configs
+---
+Variable definitions
+---
+
+Intrinsic definitions
+
+---
+```
+- If you're new to YAML syntax, consider [reviewing](https://quickref.me/yaml.html) some of the less obvious syntax and features.
+- For example, mapping an attribute to a sequence can be done in two different ways:
+```yaml
+attribute: [item_a, item_b, item_c]
+```
+or
+```yaml
+attribute:
+    - item_a
+    - item_b
+    - item_c
+``` 
+## Configs
+- Mappings defining top-level settings applied to all intrinsics:
+- `arch_cfgs`
+    - Sequence of mappings specifying `arch_name`, `target_feature` (sequence), and `llvm_prefix`.
+- `uses_neon_types`(_Optional_)
+    - A boolean specifying whether to emit NEON type imports in generated code.
+- `auto_big_endian`(_Optional_)
+    - A boolean specifying whether to auto-generate big-endian shuffles when possible.
+- `auto_llvm_sign_conversion`(_Optional_)
+    - A boolean specifying whether to auto-convert LLVM wrapper args to signed types.
+## Variable definitions
+- Defines YAML anchors/variables to avoid repetition.
+- Commonly used for stability attributes, cfgs and target features.
+## Intrinsic definitions
+### Example
+```yaml
+    - name: "vtst{neon_type[0].no}"
+      doc: "Signed compare bitwise Test bits nonzero"
+      arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"]
+      return_type: "{neon_type[1]}"
+      attr:
+        - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmtst]]}]]
+        - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
+      safety: safe
+      types:
+        - [int64x1_t, uint64x1_t, 'i64x1', 'i64x1::new(0)']
+        - [int64x2_t, uint64x2_t, 'i64x2', 'i64x2::new(0, 0)']
+        - [poly64x1_t, uint64x1_t, 'i64x1', 'i64x1::new(0)']
+        - [poly64x2_t, uint64x2_t, 'i64x2', 'i64x2::new(0, 0)']
+      compose:
+        - Let: [c, "{neon_type[0]}", {FnCall: [simd_and, [a, b]]}]
+        - Let: [d, "{type[2]}", "{type[3]}"]
+        - FnCall: [simd_ne, [c, {FnCall: [transmute, [d]]}]]
+```
+
+### Explanation of fields
+- `name`
+    - The name of the intrinsic
+    - Often built from a base name followed by a type suffix
+- `doc` (_Optional_)
+    - A string explaining the purpose of the intrinsic
+- `static_defs` (_Optional_)
+    - A sequence of const generics of the format `"const <NAME>: <type>"`
+- `arguments`
+    - A sequence of strings in the format `"<argname>: <argtype>"`
+- `return_type` (_Optional_)
+    - A string specifying the return type. If omitted, the intrinsic returns `()`.
+- `attr` (_Optional_)
+    - A sequence of items defining the attributes to be applied to the intrinsic. Often stability attributes, target features, or `assert_instr` tests. At least one of `attr` or `assert_instr` must be set.
+- `target_features` (_Optional_)
+    - A sequence of target features to enable for this intrinsic (merged with any global `arch_cfgs` settings).
+- `assert_instr` (_Optional_)
+    - A sequence of strings expected to be found in the assembly. Required if `attr` is not set.
+- `safety` (_Optional_)
+    - Use `safe`, or map `unsafe:` to a sequence of unsafety comments:
+        - `custom: "<string>"`
+        - `uninitialized`
+        - `pointer_offset`, `pointer_offset_vnum`, or `dereference` (optionally qualified with `predicated`, `predicated_non_faulting`, or `predicated_first_faulting`)
+        - `unpredictable_on_fault`
+        - `non_temporal`
+        - `neon`
+        - `no_provenance: "<string>"`
+- `substitutions` (_Optional_)
+    - Mappings of custom wildcard names to either `MatchSize` or `MatchKind` expressions
+- `types`
+    - A sequence or sequence of sequences specifying the types to use when producing each intrinsic variant. These sequences can then be indexed by wildcards.
+- `constraints` (_Optional_)
+    - A sequence of mappings. Each specifies a variable and a constraint. The available mappings are:
+    - Assert a variable's value exists in a sequence of i32's
+        - Usage: `{ variable: <name>, any_values: [<i32>,...] }`
+    - Assert a variable's value exists in a range (inclusive)
+        - Usage: `{ variable: <name>, range: [<i32>, <i32>] }`
+    - Assert a variable's value exists in a range via a match (inclusive)
+        - Usage: `{ variable: <name>, range: <MatchSize returning [i32,i32]> }`
+    - Assert a variable's value does not exceed the number of elements in a SVE type `<type>`.
+        - Usage: `{ variable: <name>, sve_max_elems_type: <type> }`
+    - Assert a variable's value does not exceed the number of elements in a vector type `<type>`.
+        - Usage: `{ variable: <name>, vec_max_elems_type: <type> }`
+- `predication_methods` (_Optional_)
+    - Configuration for predicate-form variants. Only used when the intrinsic name includes an `_m*_` wildcard (e.g., `{_mx}`, `{_mxz}`).
+    - `zeroing_method`: Required when requesting `_z`; either `{ drop: <arg> }` to remove an argument and replace it with a zero initialiser, or `{ select: <predicate_var> }` to select zeros into a predicate.
+    - `dont_care_method`: How `_x` should be implemented (`inferred`, `as_zeroing`, or `as_merging`).
+- `compose`
+    - A sequence of expressions that make up the body of the intrinsic
+- `big_endian_inverse` (_Optional_)
+    - A boolean, default false. If true, generates two implementations of each intrinsic variant, one for each endianness, and attempts to automatically generate the required bit swizzles
+- `visibility` (_Optional_)
+    - Function visibility. One of `public` (default) or `private`.
+- `n_variant_op` (_Optional_)
+    - Enables generation of an `_n` variant when the intrinsic name includes the `{_n}` wildcard. Set to the operand name that should be splattered for the `_n` form.
+- `test` (_Optional_)
+	- When set, load/store tests are automatically generated.
+    - A mapping of either `load` or `store` to a number that indexes `types` to specify the type that the test should be addressing in memory. 
+### Expressions
+#### Common
+- `Let`
+    - Defines a variable
+    - Usage: `Let: [<variable>, <type(optional)>, <expression>]`
+- `Const`
+    - Defines a const
+    - Usage: `Const: [<variable>, <type>, <expression>]`
+- `Assign`
+    - Performs variable assignment
+    - Usage: `Assign: [<variable>, <expression>]`
+- `FnCall`
+    - Performs a function call
+    - Usage: `FnCall: [<function pointer: expression>, [<argument: expression>, ... ], [<turbofish argument: expression>, ...](optional), <unsafe wrapper(optional): bool>]`
+- `MacroCall`
+    - Performs a macro call
+    - Usage: `MacroCall: [<macro name>, <token stream>]`
+- `MethodCall`
+    - Performs a method call
+    - Usage: `MethodCall: [<object: expression>, <method name>, [<argument: expression>, ... ]]`
+- `LLVMLink`
+    - Creates an LLVM link and stores the function's name in the wildcard `{llvm_link}` for later use in subsequent expressions.
+    - If left unset, the arguments and return type inherit from the intrinsic's signature by default. The links will also be set automatically if unset.
+    - Usage:
+```yaml
+LLVMLink:
+    name: <name>
+    arguments: [<expression>, ... ](optional)
+    return_type: <return type>(optional)
+    links: (optional)
+        - link: <link>
+          arch: <arch>
+        - ...
+```
+- `Identifier`
+    - Emits a symbol. Prepend with a `$` to treat it as a scope variable, which engages variable tracking and enables inference. For example, `my_function_name` for a generic symbol or `$my_variable` for a variable.
+    - Usage `Identifier: [<symbol name>, <Variable|Symbol>]`
+- `CastAs`
+    - Casts an expression to an unchecked type
+    - Usage: `CastAs: [<expression>, <type>]`
+- `MatchSize`
+    - Allows for conditional generation depending on the size of a specified type
+    - Usage:
+```yaml
+MatchSize:
+    - <type>
+    - default: <expression>
+      byte(optional): <expression>
+      halfword(optional): <expression>
+      doubleword(optional): <expression>
+```
+- `MatchKind`
+    - Allows for conditional generation depending on the kind of a specified type
+```yaml
+MatchKind:
+    - <type>
+    - default: <expression>
+      float(optional): <expression>
+      unsigned(optional): <expression>
+```
+#### Rarely Used
+- `IntConstant`
+    - Constant signed integer expression
+    - Usage: `IntConstant: <i32>`
+- `FloatConstant`
+    - Constant floating-point expression
+    - Usage: `FloatConstant: <f32>`
+- `BoolConstant`
+    - Constant boolean expression
+    - Usage: `BoolConstant: <bool>`
+- `Array`
+    - An array of expressions
+    - Usage: `Array: [<expression>, ...]`
+- `SvUndef`
+    - Returns the LLVM `undef` symbol
+    - Usage: `SvUndef`
+- `Multiply`
+    - Simply `*`
+    - Usage: `Multiply: [<expression>, <expression>]`
+- `Xor`
+    - Simply `^`
+    - Usage: `Xor: [<expression>, <expression>]`
+- `ConvertConst`
+    - Converts the specified constant to the specified type's kind
+    - Usage: `ConvertConst: [<type>, <i32>]`
+- `Type`
+    - Yields the given type in the Rust representation
+    - Usage: `Type: [<type>]`
+
+### Wildstrings
+- Wildstrings let you take advantage of wildcards.
+- For example, they are often used in intrinsic names `name: "vtst{neon_type[0].no}"`
+- As shown above, wildcards are identified by the surrounding curly brackets.
+- Double curly brackets can be used to escape wildcard functionality if you need literal curly brackets in the generated intrinsic.
+### Wildcards
+Wildcards are heavily used in the spec. They let you write generalised definitions for a group of intrinsics that generate multiple variants. The wildcard itself is replaced with the relevant string in each variant.
+Ignoring endianness, for each row in the `types` field of an intrinsic in the spec, a variant of the intrinsic will be generated. That row's contents can be indexed by the wildcards. Below is the behaviour of each wildcard.
+- `type[<index: usize>]`
+    - Replaced in each variant with the value in the indexed position in the relevant row of the `types` field.
+    - For unnested sequences of `types` (i.e., `types` is a sequence where each element is a single item, not another sequence), the square brackets can be omitted. Simply: `type`
+- `neon_type[<index: usize>]`
+    - Extends the behaviour of `type` with some NEON-specific features and inference.
+    - Tuples: This wildcard can also be written as `neon_type_x<n>` where `n` is in the set `{2,3,4}`. This generates the `n`-tuple variant of the (inferred) NEON type.
+    - Suffixes: These modify the behaviour of the wildcard from simple substitution.
+	    - `no` -  normal behaviour. Tries to do as much work as it can for you, inferring when to emit:
+            - Regular type-size suffixes: `_s8`, `_u16`, `_f32`, ...
+            - `q` variants for double-width (128b) vector types: `q_s8`, `q_u16`, `q_f32`, ...
+            - `_x<n>` variants for tuple vector types: `_s8_x2`, `_u32_x3`, `_f64_x4`, ...
+            - As well as any combination of the above: `q_s16_x16` ...
+    - Most of the other suffixes modify the normal behaviour by disabling features or adding new ones. (See table below)
+- `sve_type[<index: usize>]`
+    - Similar to `neon_type`, but without the suffixes.
+- `size[<index: usize>]`
+    - The size (in bits) of the indexed type.
+- `size_minus_one[<index: usize>]`
+    - Emits the size (in bits) of the indexed type minus one.
+- `size_literal[<index: usize>]`
+    - The literal representation of the indexed type.
+    - `b`: byte, `h`: halfword, `w`: word, or `d`: double.
+- `type_kind[<index: usize>]`
+    - The literal representation of the indexed type's kind.
+    - `f`: float, `s`: signed, `u`: unsigned, `p`: polynomial, `b`: boolean.
+- `size_in_bytes_log2[<index: usize>]`
+    - Log2 of the size of the indexed type in *bytes*.
+- `predicate[<index: usize>]`
+    - SVE predicate vector type inferred from the indexed type.
+- `max_predicate`
+    - The same as predicate, but uses the largest type in the relevant `types` sequence/row.
+- `_n`
+    - Emits the current N-variant suffix when `n_variant_op` is configured.
+- `<wildcard> as <type>`
+    - If `<wildcard>` evaluates to a vector, it produces a vector of the same shape, but with `<type>` as the base type.
+- `llvm_link`
+    - If the `LLVMLink` mapping has been set for an intrinsic, this will give the name of the link.
+- `_m*`
+    - Predicate form masks. Use wildcards such as `{_mx}` or `{_mxz}` to expand merging/don't-care/zeroing variants according to the mask.
+- `<custom>`
+    - You may simply call upon wildcards defined under `substitutions`.
+### neon_type suffixes
+
+| suffix            | implication                                   |
+| ----------------- | --------------------------------------------- |
+| `.no`             | Normal                                        |
+| `.noq`            | Never include `q`s                            |
+| `.nox`            | Never include `_x<n>`s                        |
+| `.N`              | Include `_n_`, e.g., `_n_s8`                  |
+| `.noq_N`          | Include `_n_`, but never `q`s                 |
+| `.dup`            | Include `_dup_`, e.g., `_dup_s8`              |
+| `.dup_nox`        | Include `_dup_` but never `_x<n>`s            |
+| `.lane`           | Include `_lane_`, e.g., `_lane_s8`            |
+| `.lane_nox`       | Include `_lane_`, but never `_x<n>`s          |
+| `.rot90`          | Include `_rot90_`, e.g., `_rot90_s8`          |
+| `.rot180`         | Include `_rot180_`, e.g., `_rot180_s8`        |
+| `.rot270`         | Include `_rot270_`, e.g., `_rot270_s8`        |
+| `.rot90_lane`     | Include `_rot90_lane_`                        |
+| `.rot180_lane`    | Include `_rot180_lane_`                       |
+| `.rot270_lane`    | Include `_rot270_lane_`                       |
+| `.rot90_laneq`    | Include `_rot90_laneq_`                       |
+| `.rot180_laneq`   | Include `_rot180_laneq_`                      |
+| `.rot270_laneq`   | Include `_rot270_laneq_`                      |
+| `.base`           | Produce only the size, e.g., `8`, `16`        |
+| `.u`              | Produce the type's unsigned equivalent        |
+| `.laneq_nox`      | Include `_laneq_`, but never `_x<n>`s         |
+| `.tuple`          | Produce only the size of the tuple, e.g., `3` |
+| `.base_byte_size` | Produce only the size in bytes.               |
+ 

From 5bf9ca7b00c5074d984e836dcd9bef68fc9284cb Mon Sep 17 00:00:00 2001
From: Folkert de Vries <folkert@folkertdev.nl>
Date: Tue, 13 Jan 2026 12:11:18 +0100
Subject: [PATCH 17/97] stabilize `__jscvt`

---
 .../stdarch/crates/core_arch/src/aarch64/neon/generated.rs  | 2 +-
 .../crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml       | 6 +++---
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/library/stdarch/crates/core_arch/src/aarch64/neon/generated.rs b/library/stdarch/crates/core_arch/src/aarch64/neon/generated.rs
index 7743e52f4fe1..90dba4409ed4 100644
--- a/library/stdarch/crates/core_arch/src/aarch64/neon/generated.rs
+++ b/library/stdarch/crates/core_arch/src/aarch64/neon/generated.rs
@@ -49,7 +49,7 @@ pub fn __crc32d(crc: u32, data: u64) -> u32 {
 #[inline]
 #[target_feature(enable = "jsconv")]
 #[cfg_attr(test, assert_instr(fjcvtzs))]
-#[unstable(feature = "stdarch_aarch64_jscvt", issue = "147555")]
+#[stable(feature = "stdarch_aarch64_jscvt", since = "CURRENT_RUSTC_VERSION")]
 pub fn __jcvt(a: f64) -> i32 {
     unsafe extern "unadjusted" {
         #[cfg_attr(
diff --git a/library/stdarch/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml b/library/stdarch/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
index 8f36c525fae9..a951343e0183 100644
--- a/library/stdarch/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
+++ b/library/stdarch/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
@@ -63,8 +63,8 @@ neon-unstable-f16: &neon-unstable-f16
 neon-unstable-feat-lut: &neon-unstable-feat-lut
   FnCall: [unstable, ['feature = "stdarch_neon_feat_lut"', 'issue = "138050"']]
 
-aarch64-unstable-jscvt: &aarch64-unstable-jscvt
-  FnCall: [unstable, ['feature = "stdarch_aarch64_jscvt"', 'issue = "147555"']]
+aarch64-stable-jscvt: &aarch64-stable-jscvt
+  FnCall: [stable, ['feature = "stdarch_aarch64_jscvt"', 'since = "CURRENT_RUSTC_VERSION"']]
 
 # #[cfg(target_endian = "little")]
 little-endian: &little-endian
@@ -14275,7 +14275,7 @@ intrinsics:
     attr:
       - FnCall: [target_feature, ['enable = "jsconv"']]
       - FnCall: [cfg_attr, [test, { FnCall: [assert_instr, ["fjcvtzs"]] }]]
-      - *aarch64-unstable-jscvt
+      - *aarch64-stable-jscvt
     safety: safe
     types:
       - f64

From a1a944880f89b275745d1c5838463433980b3f72 Mon Sep 17 00:00:00 2001
From: Piotr Osiewicz <24362066+osiewicz@users.noreply.github.com>
Date: Wed, 14 Jan 2026 21:16:54 +0100
Subject: [PATCH 18/97] checksum-freshness: Add binary file inclusion to
 integration test

---
 tests/run-make/checksum-freshness/binary_file | 1 +
 tests/run-make/checksum-freshness/expected.d  | 6 ++++--
 tests/run-make/checksum-freshness/lib.rs      | 3 ++-
 3 files changed, 7 insertions(+), 3 deletions(-)
 create mode 100644 tests/run-make/checksum-freshness/binary_file

diff --git a/tests/run-make/checksum-freshness/binary_file b/tests/run-make/checksum-freshness/binary_file
new file mode 100644
index 000000000000..45f1873fb781
--- /dev/null
+++ b/tests/run-make/checksum-freshness/binary_file
@@ -0,0 +1 @@
+binaryÿ
\ No newline at end of file
diff --git a/tests/run-make/checksum-freshness/expected.d b/tests/run-make/checksum-freshness/expected.d
index 51467af53a20..4554c509e36e 100644
--- a/tests/run-make/checksum-freshness/expected.d
+++ b/tests/run-make/checksum-freshness/expected.d
@@ -1,6 +1,8 @@
-lib.d: lib.rs foo.rs
+lib.d: lib.rs foo.rs binary_file
 
 lib.rs:
 foo.rs:
-# checksum:blake3=94af75ee4ed805434484c3de51c9025278e5c3ada2315e2592052e102168a503 file_len:120 lib.rs
+binary_file:
+# checksum:blake3=4ac56f3f877798fb762d714c7bcb72e70133f4cc585f80dbd99c07755ae2c7f6 file_len:222 lib.rs
 # checksum:blake3=2720e17bfda4f3b2a5c96bb61b7e76ed8ebe3359b34128c0e5d8032c090a4f1a file_len:119 foo.rs
+# checksum:blake3=119a5db8711914922c5b1c1908be4958175c5afa95c08888de594725329b5439 file_len:7 binary_file
diff --git a/tests/run-make/checksum-freshness/lib.rs b/tests/run-make/checksum-freshness/lib.rs
index 7bc6757959b1..0cd4243423de 100644
--- a/tests/run-make/checksum-freshness/lib.rs
+++ b/tests/run-make/checksum-freshness/lib.rs
@@ -1,7 +1,8 @@
 // A basic library to be used in tests with no real purpose.
 
 mod foo;
-
+// Binary file with invalid UTF-8 sequence.
+static BINARY_FILE: &[u8] = include_bytes!("binary_file");
 pub fn sum(a: i32, b: i32) -> i32 {
     a + b
 }

From f548a19d49576cc6bd33dbf8ef6cce4c9a21c472 Mon Sep 17 00:00:00 2001
From: cyrgani <ansgar.w.zielke@gmail.com>
Date: Mon, 19 Jan 2026 21:22:14 +0000
Subject: [PATCH 19/97] remove `reason = "newly added"` from `#[unstable(...)]`

---
 library/core/src/result.rs    | 4 ++--
 library/core/src/slice/mod.rs | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/library/core/src/result.rs b/library/core/src/result.rs
index 9afa71ec0f11..52f3d43dfd6d 100644
--- a/library/core/src/result.rs
+++ b/library/core/src/result.rs
@@ -1354,7 +1354,7 @@ impl<T, E> Result<T, E> {
     /// let s: String = only_good_news().into_ok();
     /// println!("{s}");
     /// ```
-    #[unstable(feature = "unwrap_infallible", reason = "newly added", issue = "61695")]
+    #[unstable(feature = "unwrap_infallible", issue = "61695")]
     #[inline]
     #[rustc_allow_const_fn_unstable(const_precise_live_drops)]
     #[rustc_const_unstable(feature = "const_convert", issue = "143773")]
@@ -1391,7 +1391,7 @@ impl<T, E> Result<T, E> {
     /// let error: String = only_bad_news().into_err();
     /// println!("{error}");
     /// ```
-    #[unstable(feature = "unwrap_infallible", reason = "newly added", issue = "61695")]
+    #[unstable(feature = "unwrap_infallible", issue = "61695")]
     #[inline]
     #[rustc_allow_const_fn_unstable(const_precise_live_drops)]
     #[rustc_const_unstable(feature = "const_convert", issue = "143773")]
diff --git a/library/core/src/slice/mod.rs b/library/core/src/slice/mod.rs
index a2d3fa401b62..bbf8b0595206 100644
--- a/library/core/src/slice/mod.rs
+++ b/library/core/src/slice/mod.rs
@@ -2520,7 +2520,7 @@ impl<T> [T] {
     /// )));
     /// assert_eq!(s.split_once(|&x| x == 0), None);
     /// ```
-    #[unstable(feature = "slice_split_once", reason = "newly added", issue = "112811")]
+    #[unstable(feature = "slice_split_once", issue = "112811")]
     #[inline]
     pub fn split_once<F>(&self, pred: F) -> Option<(&[T], &[T])>
     where
@@ -2548,7 +2548,7 @@ impl<T> [T] {
     /// )));
     /// assert_eq!(s.rsplit_once(|&x| x == 0), None);
     /// ```
-    #[unstable(feature = "slice_split_once", reason = "newly added", issue = "112811")]
+    #[unstable(feature = "slice_split_once", issue = "112811")]
     #[inline]
     pub fn rsplit_once<F>(&self, pred: F) -> Option<(&[T], &[T])>
     where

From 0adf24ac20c978c53ba67ed91963090e5e9ee17b Mon Sep 17 00:00:00 2001
From: cyrgani <ansgar.w.zielke@gmail.com>
Date: Mon, 19 Jan 2026 21:24:36 +0000
Subject: [PATCH 20/97] remove `#[deprecated]` from unstable & internal
 `SipHasher13&24`

---
 library/alloctests/tests/c_str2.rs |  6 +-----
 library/core/src/hash/mod.rs       |  1 -
 library/core/src/hash/sip.rs       | 13 ++++++-------
 library/std/src/hash/random.rs     |  4 ----
 4 files changed, 7 insertions(+), 17 deletions(-)

diff --git a/library/alloctests/tests/c_str2.rs b/library/alloctests/tests/c_str2.rs
index fe7686bd1c59..87c303de2ed4 100644
--- a/library/alloctests/tests/c_str2.rs
+++ b/library/alloctests/tests/c_str2.rs
@@ -3,9 +3,7 @@ use alloc::rc::Rc;
 use alloc::sync::Arc;
 use core::assert_matches::assert_matches;
 use core::ffi::{CStr, FromBytesUntilNulError, c_char};
-#[allow(deprecated)]
-use core::hash::SipHasher13 as DefaultHasher;
-use core::hash::{Hash, Hasher};
+use core::hash::{Hash, Hasher, SipHasher13 as DefaultHasher};
 
 #[test]
 fn c_to_rust() {
@@ -57,11 +55,9 @@ fn equal_hash() {
     let ptr = data.as_ptr() as *const c_char;
     let cstr: &'static CStr = unsafe { CStr::from_ptr(ptr) };
 
-    #[allow(deprecated)]
     let mut s = DefaultHasher::new();
     cstr.hash(&mut s);
     let cstr_hash = s.finish();
-    #[allow(deprecated)]
     let mut s = DefaultHasher::new();
     CString::new(&data[..data.len() - 1]).unwrap().hash(&mut s);
     let cstring_hash = s.finish();
diff --git a/library/core/src/hash/mod.rs b/library/core/src/hash/mod.rs
index a800e1b41fbe..eea611857120 100644
--- a/library/core/src/hash/mod.rs
+++ b/library/core/src/hash/mod.rs
@@ -87,7 +87,6 @@
 #[allow(deprecated)]
 pub use self::sip::SipHasher;
 #[unstable(feature = "hashmap_internals", issue = "none")]
-#[allow(deprecated)]
 #[doc(hidden)]
 pub use self::sip::SipHasher13;
 use crate::{fmt, marker};
diff --git a/library/core/src/hash/sip.rs b/library/core/src/hash/sip.rs
index 4569c7da035d..eed1044bd2a9 100644
--- a/library/core/src/hash/sip.rs
+++ b/library/core/src/hash/sip.rs
@@ -11,8 +11,11 @@ use crate::{cmp, ptr};
 /// (e.g., `collections::HashMap` uses it by default).
 ///
 /// See: <https://github.com/veorq/SipHash>
-#[unstable(feature = "hashmap_internals", issue = "none")]
-#[deprecated(since = "1.13.0", note = "use `std::hash::DefaultHasher` instead")]
+#[unstable(
+    feature = "hashmap_internals",
+    issue = "none",
+    reason = "use `std::hash::DefaultHasher` instead"
+)]
 #[derive(Debug, Clone, Default)]
 #[doc(hidden)]
 pub struct SipHasher13 {
@@ -23,7 +26,6 @@ pub struct SipHasher13 {
 ///
 /// See: <https://github.com/veorq/SipHash>
 #[unstable(feature = "hashmap_internals", issue = "none")]
-#[deprecated(since = "1.13.0", note = "use `std::hash::DefaultHasher` instead")]
 #[derive(Debug, Clone, Default)]
 struct SipHasher24 {
     hasher: Hasher<Sip24Rounds>,
@@ -137,8 +139,7 @@ unsafe fn u8to64_le(buf: &[u8], start: usize, len: usize) -> u64 {
         out |= (unsafe { *buf.get_unchecked(start + i) } as u64) << (i * 8);
         i += 1;
     }
-    //FIXME(fee1-dead): use debug_assert_eq
-    debug_assert!(i == len);
+    debug_assert_eq!(i, len);
     out
 }
 
@@ -167,7 +168,6 @@ impl SipHasher13 {
     #[inline]
     #[unstable(feature = "hashmap_internals", issue = "none")]
     #[rustc_const_unstable(feature = "const_default", issue = "143894")]
-    #[deprecated(since = "1.13.0", note = "use `std::hash::DefaultHasher` instead")]
     pub const fn new() -> SipHasher13 {
         SipHasher13::new_with_keys(0, 0)
     }
@@ -176,7 +176,6 @@ impl SipHasher13 {
     #[inline]
     #[unstable(feature = "hashmap_internals", issue = "none")]
     #[rustc_const_unstable(feature = "const_default", issue = "143894")]
-    #[deprecated(since = "1.13.0", note = "use `std::hash::DefaultHasher` instead")]
     pub const fn new_with_keys(key0: u64, key1: u64) -> SipHasher13 {
         SipHasher13 { hasher: Hasher::new_with_keys(key0, key1) }
     }
diff --git a/library/std/src/hash/random.rs b/library/std/src/hash/random.rs
index fab090e31f03..3c1b21eec975 100644
--- a/library/std/src/hash/random.rs
+++ b/library/std/src/hash/random.rs
@@ -7,7 +7,6 @@
 //!
 //! [`collections`]: crate::collections
 
-#[allow(deprecated)]
 use super::{BuildHasher, Hasher, SipHasher13};
 use crate::cell::Cell;
 use crate::fmt;
@@ -81,7 +80,6 @@ impl RandomState {
 impl BuildHasher for RandomState {
     type Hasher = DefaultHasher;
     #[inline]
-    #[allow(deprecated)]
     fn build_hasher(&self) -> DefaultHasher {
         DefaultHasher(SipHasher13::new_with_keys(self.k0, self.k1))
     }
@@ -91,7 +89,6 @@ impl BuildHasher for RandomState {
 ///
 /// The internal algorithm is not specified, and so it and its hashes should
 /// not be relied upon over releases.
-#[allow(deprecated)]
 #[derive(Clone, Debug)]
 #[stable(feature = "hashmap_build_hasher", since = "1.7.0")]
 pub struct DefaultHasher(SipHasher13);
@@ -104,7 +101,6 @@ impl DefaultHasher {
     /// instances created through `new` or `default`.
     #[stable(feature = "hashmap_default_hasher", since = "1.13.0")]
     #[inline]
-    #[allow(deprecated)]
     #[rustc_const_unstable(feature = "const_default", issue = "143894")]
     #[must_use]
     pub const fn new() -> DefaultHasher {

From a175d05e8503458ad57849e1a9ea0607c67f28b9 Mon Sep 17 00:00:00 2001
From: cyrgani <ansgar.w.zielke@gmail.com>
Date: Mon, 19 Jan 2026 21:25:32 +0000
Subject: [PATCH 21/97] remove old `#[allow(deprecated)]` for `env::home_dir`
 calls

---
 library/std/tests/env_modify.rs            | 1 -
 library/test/src/term/terminfo/searcher.rs | 1 -
 2 files changed, 2 deletions(-)

diff --git a/library/std/tests/env_modify.rs b/library/std/tests/env_modify.rs
index fe0ae68806e9..4cd87bf7a002 100644
--- a/library/std/tests/env_modify.rs
+++ b/library/std/tests/env_modify.rs
@@ -99,7 +99,6 @@ fn test_env_set_var() {
 
 #[test]
 #[cfg_attr(not(any(unix, windows)), ignore, allow(unused))]
-#[allow(deprecated)]
 fn env_home_dir() {
     use std::path::PathBuf;
 
diff --git a/library/test/src/term/terminfo/searcher.rs b/library/test/src/term/terminfo/searcher.rs
index 1b29598cf804..1f9d0bb345b7 100644
--- a/library/test/src/term/terminfo/searcher.rs
+++ b/library/test/src/term/terminfo/searcher.rs
@@ -9,7 +9,6 @@ use std::{env, fs};
 mod tests;
 
 /// Returns path to database entry for `term`
-#[allow(deprecated)]
 pub(crate) fn get_dbpath_for_term(term: &str) -> Option<PathBuf> {
     let mut dirs_to_search = Vec::new();
     let first_char = term.chars().next()?;

From 43111396e36bf29344535f2394b906d689ed9b40 Mon Sep 17 00:00:00 2001
From: Manuel Drehwald <git@manuel.drehwald.info>
Date: Fri, 9 Jan 2026 14:09:17 -0800
Subject: [PATCH 22/97] move initialization of omp/ol runtimes into
 global_ctor/dtor

---
 compiler/rustc_codegen_llvm/src/builder.rs    | 13 ---
 .../src/builder/gpu_offload.rs                | 91 ++++++++++++-------
 compiler/rustc_codegen_llvm/src/common.rs     |  4 +
 compiler/rustc_codegen_llvm/src/intrinsic.rs  |  5 +-
 4 files changed, 68 insertions(+), 45 deletions(-)

diff --git a/compiler/rustc_codegen_llvm/src/builder.rs b/compiler/rustc_codegen_llvm/src/builder.rs
index 9379faf1156f..35bf629ae81a 100644
--- a/compiler/rustc_codegen_llvm/src/builder.rs
+++ b/compiler/rustc_codegen_llvm/src/builder.rs
@@ -188,19 +188,6 @@ impl<'a, 'll, CX: Borrow<SCx<'ll>>> GenericBuilder<'a, 'll, CX> {
             load
         }
     }
-
-    fn memset(&mut self, ptr: &'ll Value, fill_byte: &'ll Value, size: &'ll Value, align: Align) {
-        unsafe {
-            llvm::LLVMRustBuildMemSet(
-                self.llbuilder,
-                ptr,
-                align.bytes() as c_uint,
-                fill_byte,
-                size,
-                false,
-            );
-        }
-    }
 }
 
 /// Empty string, to be used where LLVM expects an instruction name, indicating
diff --git a/compiler/rustc_codegen_llvm/src/builder/gpu_offload.rs b/compiler/rustc_codegen_llvm/src/builder/gpu_offload.rs
index f1735b9a0f58..0cf4c1d4f8c7 100644
--- a/compiler/rustc_codegen_llvm/src/builder/gpu_offload.rs
+++ b/compiler/rustc_codegen_llvm/src/builder/gpu_offload.rs
@@ -19,8 +19,6 @@ pub(crate) struct OffloadGlobals<'ll> {
     pub launcher_fn: &'ll llvm::Value,
     pub launcher_ty: &'ll llvm::Type,
 
-    pub bin_desc: &'ll llvm::Type,
-
     pub kernel_args_ty: &'ll llvm::Type,
 
     pub offload_entry_ty: &'ll llvm::Type,
@@ -31,8 +29,6 @@ pub(crate) struct OffloadGlobals<'ll> {
 
     pub ident_t_global: &'ll llvm::Value,
 
-    pub register_lib: &'ll llvm::Value,
-    pub unregister_lib: &'ll llvm::Value,
     pub init_rtls: &'ll llvm::Value,
 }
 
@@ -44,15 +40,6 @@ impl<'ll> OffloadGlobals<'ll> {
         let (begin_mapper, _, end_mapper, mapper_fn_ty) = gen_tgt_data_mappers(cx);
         let ident_t_global = generate_at_one(cx);
 
-        let tptr = cx.type_ptr();
-        let ti32 = cx.type_i32();
-        let tgt_bin_desc_ty = vec![ti32, tptr, tptr, tptr];
-        let bin_desc = cx.type_named_struct("struct.__tgt_bin_desc");
-        cx.set_struct_body(bin_desc, &tgt_bin_desc_ty, false);
-
-        let reg_lib_decl = cx.type_func(&[cx.type_ptr()], cx.type_void());
-        let register_lib = declare_offload_fn(&cx, "__tgt_register_lib", reg_lib_decl);
-        let unregister_lib = declare_offload_fn(&cx, "__tgt_unregister_lib", reg_lib_decl);
         let init_ty = cx.type_func(&[], cx.type_void());
         let init_rtls = declare_offload_fn(cx, "__tgt_init_all_rtls", init_ty);
 
@@ -63,20 +50,77 @@ impl<'ll> OffloadGlobals<'ll> {
         OffloadGlobals {
             launcher_fn,
             launcher_ty,
-            bin_desc,
             kernel_args_ty,
             offload_entry_ty,
             begin_mapper,
             end_mapper,
             mapper_fn_ty,
             ident_t_global,
-            register_lib,
-            unregister_lib,
             init_rtls,
         }
     }
 }
 
+// We need to register offload before using it. We also should unregister it once we are done, for
+// good measures. Previously we have done so before and after each individual offload intrinsic
+// call, but that comes at a performance cost. The repeated (un)register calls might also confuse
+// the LLVM ompOpt pass, which tries to move operations to a better location. The easiest solution,
+// which we copy from clang, is to just have those two calls once, in the global ctor/dtor section
+// of the final binary.
+pub(crate) fn register_offload<'ll>(cx: &CodegenCx<'ll, '_>) {
+    let reg_lib_decl = cx.type_func(&[cx.type_ptr()], cx.type_void());
+    let register_lib = declare_offload_fn(&cx, "__tgt_register_lib", reg_lib_decl);
+    let unregister_lib = declare_offload_fn(&cx, "__tgt_unregister_lib", reg_lib_decl);
+
+    let ptr_null = cx.const_null(cx.type_ptr());
+    let const_struct = cx.const_struct(&[cx.get_const_i32(0), ptr_null, ptr_null, ptr_null], false);
+    let omp_descriptor =
+        add_global(cx, ".omp_offloading.descriptor", const_struct, InternalLinkage);
+    // @.omp_offloading.descriptor = internal constant %__tgt_bin_desc { i32 1, ptr @.omp_offloading.device_images, ptr @__start_llvm_offload_entries, ptr @__stop_llvm_offload_entries }
+    // @.omp_offloading.descriptor = internal constant %__tgt_bin_desc { i32 0, ptr null, ptr null, ptr null }
+
+    let atexit = cx.type_func(&[cx.type_ptr()], cx.type_i32());
+    let atexit_fn = declare_offload_fn(cx, "atexit", atexit);
+
+    let desc_ty = cx.type_func(&[], cx.type_void());
+    let reg_name = ".omp_offloading.descriptor_reg";
+    let unreg_name = ".omp_offloading.descriptor_unreg";
+    let desc_reg_fn = declare_offload_fn(cx, reg_name, desc_ty);
+    let desc_unreg_fn = declare_offload_fn(cx, unreg_name, desc_ty);
+    llvm::set_linkage(desc_reg_fn, InternalLinkage);
+    llvm::set_linkage(desc_unreg_fn, InternalLinkage);
+    llvm::set_section(desc_reg_fn, c".text.startup");
+    llvm::set_section(desc_unreg_fn, c".text.startup");
+
+    // define internal void @.omp_offloading.descriptor_reg() section ".text.startup" {
+    // entry:
+    //   call void @__tgt_register_lib(ptr @.omp_offloading.descriptor)
+    //   %0 = call i32 @atexit(ptr @.omp_offloading.descriptor_unreg)
+    //   ret void
+    // }
+    let bb = Builder::append_block(cx, desc_reg_fn, "entry");
+    let mut a = Builder::build(cx, bb);
+    a.call(reg_lib_decl, None, None, register_lib, &[omp_descriptor], None, None);
+    a.call(atexit, None, None, atexit_fn, &[desc_unreg_fn], None, None);
+    a.ret_void();
+
+    // define internal void @.omp_offloading.descriptor_unreg() section ".text.startup" {
+    // entry:
+    //   call void @__tgt_unregister_lib(ptr @.omp_offloading.descriptor)
+    //   ret void
+    // }
+    let bb = Builder::append_block(cx, desc_unreg_fn, "entry");
+    let mut a = Builder::build(cx, bb);
+    a.call(reg_lib_decl, None, None, unregister_lib, &[omp_descriptor], None, None);
+    a.ret_void();
+
+    // @llvm.global_ctors = appending global [1 x { i32, ptr, ptr }] [{ i32, ptr, ptr } { i32 101, ptr @.omp_offloading.descriptor_reg, ptr null }]
+    let args = vec![cx.get_const_i32(101), desc_reg_fn, ptr_null];
+    let const_struct = cx.const_struct(&args, false);
+    let arr = cx.const_array(cx.val_ty(const_struct), &[const_struct]);
+    add_global(cx, "llvm.global_ctors", arr, AppendingLinkage);
+}
+
 pub(crate) struct OffloadKernelDims<'ll> {
     num_workgroups: &'ll Value,
     threads_per_block: &'ll Value,
@@ -487,9 +531,6 @@ pub(crate) fn gen_call_handling<'ll, 'tcx>(
     let tgt_decl = offload_globals.launcher_fn;
     let tgt_target_kernel_ty = offload_globals.launcher_ty;
 
-    // %struct.__tgt_bin_desc = type { i32, ptr, ptr, ptr }
-    let tgt_bin_desc = offload_globals.bin_desc;
-
     let tgt_kernel_decl = offload_globals.kernel_args_ty;
     let begin_mapper_decl = offload_globals.begin_mapper;
     let end_mapper_decl = offload_globals.end_mapper;
@@ -513,12 +554,9 @@ pub(crate) fn gen_call_handling<'ll, 'tcx>(
     }
 
     // Step 0)
-    // %struct.__tgt_bin_desc = type { i32, ptr, ptr, ptr }
-    // %6 = alloca %struct.__tgt_bin_desc, align 8
     unsafe {
         llvm::LLVMRustPositionBuilderPastAllocas(&builder.llbuilder, builder.llfn());
     }
-    let tgt_bin_desc_alloca = builder.direct_alloca(tgt_bin_desc, Align::EIGHT, "EmptyDesc");
 
     let ty = cx.type_array(cx.type_ptr(), num_args);
     // Baseptr are just the input pointer to the kernel, stored in a local alloca
@@ -536,7 +574,6 @@ pub(crate) fn gen_call_handling<'ll, 'tcx>(
     unsafe {
         llvm::LLVMPositionBuilderAtEnd(&builder.llbuilder, bb);
     }
-    builder.memset(tgt_bin_desc_alloca, cx.get_const_i8(0), cx.get_const_i64(32), Align::EIGHT);
 
     // Now we allocate once per function param, a copy to be passed to one of our maps.
     let mut vals = vec![];
@@ -574,15 +611,9 @@ pub(crate) fn gen_call_handling<'ll, 'tcx>(
         geps.push(gep);
     }
 
-    let mapper_fn_ty = cx.type_func(&[cx.type_ptr()], cx.type_void());
-    let register_lib_decl = offload_globals.register_lib;
-    let unregister_lib_decl = offload_globals.unregister_lib;
     let init_ty = cx.type_func(&[], cx.type_void());
     let init_rtls_decl = offload_globals.init_rtls;
 
-    // FIXME(offload): Later we want to add them to the wrapper code, rather than our main function.
-    // call void @__tgt_register_lib(ptr noundef %6)
-    builder.call(mapper_fn_ty, None, None, register_lib_decl, &[tgt_bin_desc_alloca], None, None);
     // call void @__tgt_init_all_rtls()
     builder.call(init_ty, None, None, init_rtls_decl, &[], None, None);
 
@@ -679,6 +710,4 @@ pub(crate) fn gen_call_handling<'ll, 'tcx>(
         num_args,
         s_ident_t,
     );
-
-    builder.call(mapper_fn_ty, None, None, unregister_lib_decl, &[tgt_bin_desc_alloca], None, None);
 }
diff --git a/compiler/rustc_codegen_llvm/src/common.rs b/compiler/rustc_codegen_llvm/src/common.rs
index b0cf9925019d..f2261ab79340 100644
--- a/compiler/rustc_codegen_llvm/src/common.rs
+++ b/compiler/rustc_codegen_llvm/src/common.rs
@@ -124,6 +124,10 @@ impl<'ll, CX: Borrow<SCx<'ll>>> GenericCx<'ll, CX> {
     pub(crate) fn const_null(&self, t: &'ll Type) -> &'ll Value {
         unsafe { llvm::LLVMConstNull(t) }
     }
+
+    pub(crate) fn const_struct(&self, elts: &[&'ll Value], packed: bool) -> &'ll Value {
+        struct_in_context(self.llcx(), elts, packed)
+    }
 }
 
 impl<'ll, 'tcx> ConstCodegenMethods for CodegenCx<'ll, 'tcx> {
diff --git a/compiler/rustc_codegen_llvm/src/intrinsic.rs b/compiler/rustc_codegen_llvm/src/intrinsic.rs
index 20eac4cf92c2..97bc929dff32 100644
--- a/compiler/rustc_codegen_llvm/src/intrinsic.rs
+++ b/compiler/rustc_codegen_llvm/src/intrinsic.rs
@@ -30,7 +30,9 @@ use tracing::debug;
 use crate::abi::FnAbiLlvmExt;
 use crate::builder::Builder;
 use crate::builder::autodiff::{adjust_activity_to_abi, generate_enzyme_call};
-use crate::builder::gpu_offload::{OffloadKernelDims, gen_call_handling, gen_define_handling};
+use crate::builder::gpu_offload::{
+    OffloadKernelDims, gen_call_handling, gen_define_handling, register_offload,
+};
 use crate::context::CodegenCx;
 use crate::declare::declare_raw_fn;
 use crate::errors::{
@@ -1410,6 +1412,7 @@ fn codegen_offload<'ll, 'tcx>(
             return;
         }
     };
+    register_offload(cx);
     let offload_data = gen_define_handling(&cx, &metadata, target_symbol, offload_globals);
     gen_call_handling(bx, &offload_data, &args, &types, &metadata, offload_globals, &offload_dims);
 }

From bf7c1c2d82f75faca1a911d93873b906bae1b820 Mon Sep 17 00:00:00 2001
From: Folkert de Vries <folkert@folkertdev.nl>
Date: Wed, 21 Jan 2026 20:57:49 +0100
Subject: [PATCH 23/97] test `vmulh_lane_f16` in intrinsic test

---
 library/stdarch/crates/intrinsic-test/missing_aarch64.txt    | 3 ---
 library/stdarch/crates/intrinsic-test/missing_aarch64_be.txt | 3 ---
 2 files changed, 6 deletions(-)

diff --git a/library/stdarch/crates/intrinsic-test/missing_aarch64.txt b/library/stdarch/crates/intrinsic-test/missing_aarch64.txt
index bbcfc40c69ab..814756cefa40 100644
--- a/library/stdarch/crates/intrinsic-test/missing_aarch64.txt
+++ b/library/stdarch/crates/intrinsic-test/missing_aarch64.txt
@@ -59,6 +59,3 @@ vluti4q_laneq_u8
 
 # Broken in Clang
 vcvth_s16_f16
-# FIXME: Broken output due to missing f16 printing support in Rust, see git blame for this line
-vmulh_lane_f16
-vmulh_laneq_f16
diff --git a/library/stdarch/crates/intrinsic-test/missing_aarch64_be.txt b/library/stdarch/crates/intrinsic-test/missing_aarch64_be.txt
index 28e1d9203ee5..1fa8fb7f1693 100644
--- a/library/stdarch/crates/intrinsic-test/missing_aarch64_be.txt
+++ b/library/stdarch/crates/intrinsic-test/missing_aarch64_be.txt
@@ -100,6 +100,3 @@ vluti4q_laneq_u8
 
 # Broken in Clang
 vcvth_s16_f16
-# FIXME: Broken output due to missing f16 printing support in Rust
-vmulh_lane_f16
-vmulh_laneq_f16

From b1ef655cb33986b1e91e23d374f2a61099f6774d Mon Sep 17 00:00:00 2001
From: Folkert de Vries <folkert@folkertdev.nl>
Date: Wed, 21 Jan 2026 13:11:07 +0100
Subject: [PATCH 24/97] use `simd_extract_dyn` for `extract`

---
 .../crates/core_arch/src/powerpc/altivec.rs   |  8 +++----
 library/stdarch/crates/core_arch/src/simd.rs  | 15 ++++++-------
 .../stdarch/crates/core_arch/src/x86/test.rs  | 21 ++++++++++++-------
 3 files changed, 26 insertions(+), 18 deletions(-)

diff --git a/library/stdarch/crates/core_arch/src/powerpc/altivec.rs b/library/stdarch/crates/core_arch/src/powerpc/altivec.rs
index c1881da08f86..b9a25a9d8563 100644
--- a/library/stdarch/crates/core_arch/src/powerpc/altivec.rs
+++ b/library/stdarch/crates/core_arch/src/powerpc/altivec.rs
@@ -4740,7 +4740,7 @@ mod tests {
         for off in 0..16 {
             let val: u8x16 = transmute(vec_xl(0, (pat.as_ptr() as *const u8).offset(off)));
             for i in 0..16 {
-                let v = val.extract(i);
+                let v = val.extract_dyn(i);
                 assert_eq!(off as usize + i, v as usize);
             }
         }
@@ -4795,7 +4795,7 @@ mod tests {
         )];
         for off in 0..16 {
             let v: u8x16 = transmute(vec_lde(off, pat.as_ptr() as *const u8));
-            assert_eq!(off as u8, v.extract(off as _));
+            assert_eq!(off as u8, v.extract_dyn(off as _));
         }
     }
 
@@ -4804,7 +4804,7 @@ mod tests {
         let pat = [u16x8::new(0, 1, 2, 3, 4, 5, 6, 7)];
         for off in 0..8 {
             let v: u16x8 = transmute(vec_lde(off * 2, pat.as_ptr() as *const u16));
-            assert_eq!(off as u16, v.extract(off as _));
+            assert_eq!(off as u16, v.extract_dyn(off as _));
         }
     }
 
@@ -4813,7 +4813,7 @@ mod tests {
         let pat = [u32x4::new(0, 1, 2, 3)];
         for off in 0..4 {
             let v: u32x4 = transmute(vec_lde(off * 4, pat.as_ptr() as *const u32));
-            assert_eq!(off as u32, v.extract(off as _));
+            assert_eq!(off as u32, v.extract_dyn(off as _));
         }
     }
 
diff --git a/library/stdarch/crates/core_arch/src/simd.rs b/library/stdarch/crates/core_arch/src/simd.rs
index 926163ac4cad..b670092f5b0f 100644
--- a/library/stdarch/crates/core_arch/src/simd.rs
+++ b/library/stdarch/crates/core_arch/src/simd.rs
@@ -60,13 +60,14 @@ impl<T: SimdElement, const N: usize> Simd<T, N> {
         unsafe { simd_shuffle!(one, one, [0; N]) }
     }
 
-    /// Extract the element at position `index`.
-    /// `index` is not a constant so this is not efficient!
-    /// Use for testing only.
-    // FIXME: Workaround rust@60637
-    #[inline(always)]
-    pub(crate) const fn extract(&self, index: usize) -> T {
-        self.as_array()[index]
+    /// Extract the element at position `index`. Note that `index` is not a constant so this
+    /// operation is not efficient on most platforms. Use for testing only.
+    #[inline]
+    #[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
+    pub(crate) const fn extract_dyn(&self, index: usize) -> T {
+        assert!(index < N);
+        // SAFETY: self is a vector, T its element type.
+        unsafe { crate::intrinsics::simd::simd_extract_dyn(*self, index as u32) }
     }
 
     #[inline]
diff --git a/library/stdarch/crates/core_arch/src/x86/test.rs b/library/stdarch/crates/core_arch/src/x86/test.rs
index 4b2ef26044e8..402c2a6a81bb 100644
--- a/library/stdarch/crates/core_arch/src/x86/test.rs
+++ b/library/stdarch/crates/core_arch/src/x86/test.rs
@@ -78,38 +78,45 @@ pub(crate) const fn assert_eq_m512h(a: __m512h, b: __m512h) {
 }
 
 #[target_feature(enable = "sse2")]
+#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
 pub(crate) const fn get_m128d(a: __m128d, idx: usize) -> f64 {
-    a.as_f64x2().extract(idx)
+    a.as_f64x2().extract_dyn(idx)
 }
 
 #[target_feature(enable = "sse")]
+#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
 pub(crate) const fn get_m128(a: __m128, idx: usize) -> f32 {
-    a.as_f32x4().extract(idx)
+    a.as_f32x4().extract_dyn(idx)
 }
 
 #[target_feature(enable = "avx")]
+#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
 pub(crate) const fn get_m256d(a: __m256d, idx: usize) -> f64 {
-    a.as_f64x4().extract(idx)
+    a.as_f64x4().extract_dyn(idx)
 }
 
 #[target_feature(enable = "avx")]
+#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
 pub(crate) const fn get_m256(a: __m256, idx: usize) -> f32 {
-    a.as_f32x8().extract(idx)
+    a.as_f32x8().extract_dyn(idx)
 }
 
 #[target_feature(enable = "avx512f")]
+#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
 pub(crate) const fn get_m512(a: __m512, idx: usize) -> f32 {
-    a.as_f32x16().extract(idx)
+    a.as_f32x16().extract_dyn(idx)
 }
 
 #[target_feature(enable = "avx512f")]
+#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
 pub(crate) const fn get_m512d(a: __m512d, idx: usize) -> f64 {
-    a.as_f64x8().extract(idx)
+    a.as_f64x8().extract_dyn(idx)
 }
 
 #[target_feature(enable = "avx512f")]
+#[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
 pub(crate) const fn get_m512i(a: __m512i, idx: usize) -> i64 {
-    a.as_i64x8().extract(idx)
+    a.as_i64x8().extract_dyn(idx)
 }
 
 // not actually an intrinsic but useful in various tests as we ported from

From cf08a111d040711b3a86cafa6c252d29d06f0ff5 Mon Sep 17 00:00:00 2001
From: Folkert de Vries <folkert@folkertdev.nl>
Date: Sat, 17 Jan 2026 17:01:14 +0100
Subject: [PATCH 25/97] s390x: add `nnp-assist` intrinsics

Because `qemu` does not support these (yet), I haven't added any runtime tests
---
 .../crates/core_arch/src/s390x/vector.rs      | 74 +++++++++++++++++++
 1 file changed, 74 insertions(+)

diff --git a/library/stdarch/crates/core_arch/src/s390x/vector.rs b/library/stdarch/crates/core_arch/src/s390x/vector.rs
index 97bfa32f17ad..e1f841030c00 100644
--- a/library/stdarch/crates/core_arch/src/s390x/vector.rs
+++ b/library/stdarch/crates/core_arch/src/s390x/vector.rs
@@ -281,6 +281,12 @@ unsafe extern "unadjusted" {
     #[link_name = "llvm.s390.vfenezbs"] fn vfenezbs(a: i8x16, b: i8x16) -> PackedTuple<i8x16, i32>;
     #[link_name = "llvm.s390.vfenezhs"] fn vfenezhs(a: i16x8, b: i16x8) -> PackedTuple<i16x8, i32>;
     #[link_name = "llvm.s390.vfenezfs"] fn vfenezfs(a: i32x4, b: i32x4) -> PackedTuple<i32x4, i32>;
+
+    #[link_name = "llvm.s390.vclfnhs"] fn vclfnhs(a: vector_signed_short, immarg: i32) -> vector_float;
+    #[link_name = "llvm.s390.vclfnls"] fn vclfnls(a: vector_signed_short, immarg: i32) -> vector_float;
+    #[link_name = "llvm.s390.vcfn"] fn vcfn(a: vector_signed_short, immarg: i32) -> vector_signed_short;
+    #[link_name = "llvm.s390.vcnf"] fn vcnf(a: vector_signed_short, immarg: i32) -> vector_signed_short;
+    #[link_name = "llvm.s390.vcrnfs"] fn vcrnfs(a: vector_float, b: vector_float, immarg: i32) -> vector_signed_short;
 }
 
 #[repr(simd)]
@@ -5911,6 +5917,74 @@ pub unsafe fn vec_promote<T: sealed::VectorPromote>(a: T::ElementType, b: i32) -
     T::vec_promote(a, b)
 }
 
+/// Converts the left-most half of `a` to a vector of single-precision numbers.
+/// The format of the source vector elements is specified by `B`.
+#[inline]
+#[target_feature(enable = "nnp-assist")]
+#[cfg_attr(test, assert_instr(vclfnh, B = 0))]
+#[unstable(feature = "stdarch_s390x", issue = "135681")]
+pub unsafe fn vec_extend_to_fp32_hi<const B: i32>(a: vector_signed_short) -> vector_float {
+    // On processors implementing the IBM z16 architecture, only the value 0 is supported.
+    static_assert_uimm_bits!(B, 4);
+
+    vclfnhs(a, B)
+}
+
+/// Converts the right-most half of `a` to a vector of single-precision numbers.
+/// The format of the source vector elements is specified by `B`.
+#[inline]
+#[target_feature(enable = "nnp-assist")]
+#[cfg_attr(test, assert_instr(vclfnl, B = 0))]
+#[unstable(feature = "stdarch_s390x", issue = "135681")]
+pub unsafe fn vec_extend_to_fp32_lo<const B: i32>(a: vector_signed_short) -> vector_float {
+    // On processors implementing the IBM z16 architecture, only the value 0 is supported.
+    static_assert_uimm_bits!(B, 4);
+
+    vclfnls(a, B)
+}
+
+/// Converts the elements of vector `a` to the 16-bit IEEE floating point format.
+/// The format of the source vector elements is specified by `B`.
+#[inline]
+#[target_feature(enable = "nnp-assist")]
+#[cfg_attr(test, assert_instr(vcfn, B = 0))]
+#[unstable(feature = "stdarch_s390x", issue = "135681")]
+pub unsafe fn vec_convert_to_fp16<const B: i32>(a: vector_signed_short) -> vector_signed_short {
+    // On processors implementing the IBM z16 architecture, only the value 0 is supported.
+    static_assert_uimm_bits!(B, 4);
+
+    vcfn(a, B)
+}
+
+/// Converts the elements of vector `a` to an internal floating point format.
+/// The format of the target vector elements is specified by `B`.
+#[inline]
+#[target_feature(enable = "nnp-assist")]
+#[cfg_attr(test, assert_instr(vcnf, B = 0))]
+#[unstable(feature = "stdarch_s390x", issue = "135681")]
+pub unsafe fn vec_convert_from_fp16<const B: i32>(a: vector_signed_short) -> vector_signed_short {
+    // On processors implementing the IBM z16 architecture, only the value 0 is supported.
+    static_assert_uimm_bits!(B, 4);
+
+    vcnf(a, B)
+}
+
+/// Converts the elements of single-precision vectors `a` and `b` to an internal floating point
+/// format with 16-bit sized elements. The format of the target vector elements is specified by `C`.
+#[inline]
+#[target_feature(enable = "nnp-assist")]
+#[unstable(feature = "stdarch_s390x", issue = "135681")]
+#[cfg_attr(test, assert_instr(vcrnf, C = 0))]
+pub unsafe fn vec_round_from_fp32<const C: i32>(
+    a: vector_float,
+    b: vector_float,
+) -> vector_signed_short {
+    // On processors implementing the IBM z16 architecture, only the value 0 is supported.
+    static_assert_uimm_bits!(C, 4);
+
+    vcrnfs(a, b, C)
+}
+
 #[cfg(test)]
 mod tests {
     use super::*;

From f4731a17f696cdde1650d9e660236c3077f06a3c Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Le=C3=B3n=20Orell=20Valerian=20Liehr?= <me@fmease.dev>
Date: Mon, 26 Jan 2026 00:06:59 +0100
Subject: [PATCH 26/97] Bump `std`'s `backtrace`'s `rustc-demangle`

---
 library/Cargo.lock     | 4 ++--
 library/std/Cargo.toml | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/library/Cargo.lock b/library/Cargo.lock
index f6c14bc58a04..92dbedb6457a 100644
--- a/library/Cargo.lock
+++ b/library/Cargo.lock
@@ -274,9 +274,9 @@ dependencies = [
 
 [[package]]
 name = "rustc-demangle"
-version = "0.1.26"
+version = "0.1.27"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "56f7d92ca342cea22a06f2121d944b4fd82af56988c270852495420f961d4ace"
+checksum = "b50b8869d9fc858ce7266cce0194bd74df58b9d0e3f6df3a9fc8eb470d95c09d"
 dependencies = [
  "rustc-std-workspace-core",
 ]
diff --git a/library/std/Cargo.toml b/library/std/Cargo.toml
index 5c9ae52d9e6c..80dd0801333b 100644
--- a/library/std/Cargo.toml
+++ b/library/std/Cargo.toml
@@ -26,7 +26,7 @@ hashbrown = { version = "0.16.1", default-features = false, features = [
 std_detect = { path = "../std_detect", public = true }
 
 # Dependencies of the `backtrace` crate
-rustc-demangle = { version = "0.1.24", features = ['rustc-dep-of-std'] }
+rustc-demangle = { version = "0.1.27", features = ['rustc-dep-of-std'] }
 
 [target.'cfg(not(all(windows, target_env = "msvc", not(target_vendor = "uwp"))))'.dependencies]
 miniz_oxide = { version = "0.8.0", optional = true, default-features = false }

From 29596f87becfc3ec7dc3408c848850f45f05b37a Mon Sep 17 00:00:00 2001
From: Juho Kahala <57393910+quaternic@users.noreply.github.com>
Date: Mon, 26 Jan 2026 06:28:42 +0200
Subject: [PATCH 27/97] rename uN::{gather,scatter}_bits to
 uN::{extract,deposit}_bits

---
 library/core/src/num/int_bits.rs              | 20 ++--
 library/core/src/num/uint_macros.rs           | 16 ++--
 library/coretests/benches/num/int_bits/mod.rs |  4 +-
 library/coretests/tests/num/uint_macros.rs    | 96 +++++++++----------
 4 files changed, 68 insertions(+), 68 deletions(-)

diff --git a/library/core/src/num/int_bits.rs b/library/core/src/num/int_bits.rs
index 44be6de47327..7e5459192235 100644
--- a/library/core/src/num/int_bits.rs
+++ b/library/core/src/num/int_bits.rs
@@ -1,12 +1,12 @@
-//! Implementations for `uN::gather_bits` and `uN::scatter_bits`
+//! Implementations for `uN::extract_bits` and `uN::deposit_bits`
 //!
 //! For the purposes of this implementation, the operations can be thought
 //! of as operating on the input bits as a list, starting from the least
-//! significant bit. Gathering is like `Vec::retain` that deletes bits
-//! where the mask has a zero. Scattering is like doing the inverse by
-//! inserting the zeros that gathering would delete.
+//! significant bit. Extraction is like `Vec::retain` that deletes bits
+//! where the mask has a zero. Deposition is like doing the inverse by
+//! inserting the zeros that extraction would delete.
 //!
-//! Key observation: Each bit that is gathered/scattered needs to be
+//! Key observation: Each extracted or deposited bit needs to be
 //! shifted by the count of zeros up to the corresponding mask bit.
 //!
 //! With that in mind, the general idea is to decompose the operation into
@@ -14,7 +14,7 @@
 //! of the bits by `n = 1 << stage`. The masks for each stage are computed
 //! via prefix counts of zeros in the mask.
 //!
-//! # Gathering
+//! # Extraction
 //!
 //! Consider the input as a sequence of runs of data (bitstrings A,B,C,...),
 //! split by fixed-width groups of zeros ('.'), initially at width `n = 1`.
@@ -36,9 +36,9 @@
 //! ........abbbcccccddeghh
 //! ```
 //!
-//! # Scattering
+//! # Deposition
 //!
-//! For `scatter_bits`, the stages are reversed. We start with a single run of
+//! For `deposit_bits`, the stages are reversed. We start with a single run of
 //! data in the low bits. Each stage then splits each run of data in two by
 //! shifting part of it left by `n`, which is halved each stage.
 //! ```text
@@ -100,7 +100,7 @@ macro_rules! uint_impl {
             }
 
             #[inline(always)]
-            pub(in super::super) const fn gather_impl(mut x: $U, sparse: $U) -> $U {
+            pub(in super::super) const fn extract_impl(mut x: $U, sparse: $U) -> $U {
                 let masks = prepare(sparse);
                 x &= sparse;
                 let mut stage = 0;
@@ -131,7 +131,7 @@ macro_rules! uint_impl {
                 x
             }
             #[inline(always)]
-            pub(in super::super) const fn scatter_impl(mut x: $U, sparse: $U) -> $U {
+            pub(in super::super) const fn deposit_impl(mut x: $U, sparse: $U) -> $U {
                 let masks = prepare(sparse);
                 let mut stage = STAGES;
                 while stage > 0 {
diff --git a/library/core/src/num/uint_macros.rs b/library/core/src/num/uint_macros.rs
index 57f0cd48fbe8..c48320c0eab3 100644
--- a/library/core/src/num/uint_macros.rs
+++ b/library/core/src/num/uint_macros.rs
@@ -507,15 +507,15 @@ macro_rules! uint_impl {
         /// #![feature(uint_gather_scatter_bits)]
         #[doc = concat!("let n: ", stringify!($SelfT), " = 0b1011_1100;")]
         ///
-        /// assert_eq!(n.gather_bits(0b0010_0100), 0b0000_0011);
-        /// assert_eq!(n.gather_bits(0xF0), 0b0000_1011);
+        /// assert_eq!(n.extract_bits(0b0010_0100), 0b0000_0011);
+        /// assert_eq!(n.extract_bits(0xF0), 0b0000_1011);
         /// ```
         #[unstable(feature = "uint_gather_scatter_bits", issue = "149069")]
         #[must_use = "this returns the result of the operation, \
                       without modifying the original"]
         #[inline]
-        pub const fn gather_bits(self, mask: Self) -> Self {
-            crate::num::int_bits::$ActualT::gather_impl(self as $ActualT, mask as $ActualT) as $SelfT
+        pub const fn extract_bits(self, mask: Self) -> Self {
+            crate::num::int_bits::$ActualT::extract_impl(self as $ActualT, mask as $ActualT) as $SelfT
         }
 
         /// Returns an integer with the least significant bits of `self`
@@ -524,15 +524,15 @@ macro_rules! uint_impl {
         /// #![feature(uint_gather_scatter_bits)]
         #[doc = concat!("let n: ", stringify!($SelfT), " = 0b1010_1101;")]
         ///
-        /// assert_eq!(n.scatter_bits(0b0101_0101), 0b0101_0001);
-        /// assert_eq!(n.scatter_bits(0xF0), 0b1101_0000);
+        /// assert_eq!(n.deposit_bits(0b0101_0101), 0b0101_0001);
+        /// assert_eq!(n.deposit_bits(0xF0), 0b1101_0000);
         /// ```
         #[unstable(feature = "uint_gather_scatter_bits", issue = "149069")]
         #[must_use = "this returns the result of the operation, \
                       without modifying the original"]
         #[inline]
-        pub const fn scatter_bits(self, mask: Self) -> Self {
-            crate::num::int_bits::$ActualT::scatter_impl(self as $ActualT, mask as $ActualT) as $SelfT
+        pub const fn deposit_bits(self, mask: Self) -> Self {
+            crate::num::int_bits::$ActualT::deposit_impl(self as $ActualT, mask as $ActualT) as $SelfT
         }
 
         /// Reverses the order of bits in the integer. The least significant bit becomes the most significant bit,
diff --git a/library/coretests/benches/num/int_bits/mod.rs b/library/coretests/benches/num/int_bits/mod.rs
index c6ec51f248ba..65ba48609e80 100644
--- a/library/coretests/benches/num/int_bits/mod.rs
+++ b/library/coretests/benches/num/int_bits/mod.rs
@@ -50,8 +50,8 @@ macro_rules! bench_mask_kind {
     ($mask_kind:ident, $mask:expr) => {
         mod $mask_kind {
             use super::{Data, ITERATIONS, U};
-            bench_template!(U::gather_bits, gather_bits, $mask);
-            bench_template!(U::scatter_bits, scatter_bits, $mask);
+            bench_template!(U::extract_bits, extract_bits, $mask);
+            bench_template!(U::deposit_bits, deposit_bits, $mask);
         }
     };
 }
diff --git a/library/coretests/tests/num/uint_macros.rs b/library/coretests/tests/num/uint_macros.rs
index 72d500e575fa..7c4fb22599c0 100644
--- a/library/coretests/tests/num/uint_macros.rs
+++ b/library/coretests/tests/num/uint_macros.rs
@@ -127,50 +127,50 @@ macro_rules! uint_module {
                 assert_eq_const_safe!($T: _1.swap_bytes(), _1);
             }
 
-            fn test_gather_bits() {
-                assert_eq_const_safe!($T: $T::gather_bits(0b1010_0101, 0b0000_0011), 0b_0001);
-                assert_eq_const_safe!($T: $T::gather_bits(0b1010_0101, 0b0000_0110), 0b_0010);
-                assert_eq_const_safe!($T: $T::gather_bits(0b1010_0101, 0b0000_1100), 0b_0001);
-                assert_eq_const_safe!($T: $T::gather_bits(0b1010_0101, 0b0001_1000), 0b_0000);
-                assert_eq_const_safe!($T: $T::gather_bits(0b1010_0101, 0b0011_0000), 0b_0010);
-                assert_eq_const_safe!($T: $T::gather_bits(0b1010_0101, 0b0110_0000), 0b_0001);
-                assert_eq_const_safe!($T: $T::gather_bits(0b1010_0101, 0b1100_0000), 0b_0010);
+            fn test_extract_bits() {
+                assert_eq_const_safe!($T: $T::extract_bits(0b1010_0101, 0b0000_0011), 0b_0001);
+                assert_eq_const_safe!($T: $T::extract_bits(0b1010_0101, 0b0000_0110), 0b_0010);
+                assert_eq_const_safe!($T: $T::extract_bits(0b1010_0101, 0b0000_1100), 0b_0001);
+                assert_eq_const_safe!($T: $T::extract_bits(0b1010_0101, 0b0001_1000), 0b_0000);
+                assert_eq_const_safe!($T: $T::extract_bits(0b1010_0101, 0b0011_0000), 0b_0010);
+                assert_eq_const_safe!($T: $T::extract_bits(0b1010_0101, 0b0110_0000), 0b_0001);
+                assert_eq_const_safe!($T: $T::extract_bits(0b1010_0101, 0b1100_0000), 0b_0010);
 
-                assert_eq_const_safe!($T: A.gather_bits(_0), 0);
-                assert_eq_const_safe!($T: B.gather_bits(_0), 0);
-                assert_eq_const_safe!($T: C.gather_bits(_0), 0);
-                assert_eq_const_safe!($T: _0.gather_bits(A), 0);
-                assert_eq_const_safe!($T: _0.gather_bits(B), 0);
-                assert_eq_const_safe!($T: _0.gather_bits(C), 0);
+                assert_eq_const_safe!($T: A.extract_bits(_0), 0);
+                assert_eq_const_safe!($T: B.extract_bits(_0), 0);
+                assert_eq_const_safe!($T: C.extract_bits(_0), 0);
+                assert_eq_const_safe!($T: _0.extract_bits(A), 0);
+                assert_eq_const_safe!($T: _0.extract_bits(B), 0);
+                assert_eq_const_safe!($T: _0.extract_bits(C), 0);
 
-                assert_eq_const_safe!($T: A.gather_bits(_1), A);
-                assert_eq_const_safe!($T: B.gather_bits(_1), B);
-                assert_eq_const_safe!($T: C.gather_bits(_1), C);
-                assert_eq_const_safe!($T: _1.gather_bits(0b0010_0001), 0b0000_0011);
-                assert_eq_const_safe!($T: _1.gather_bits(0b0010_1100), 0b0000_0111);
-                assert_eq_const_safe!($T: _1.gather_bits(0b0111_1001), 0b0001_1111);
+                assert_eq_const_safe!($T: A.extract_bits(_1), A);
+                assert_eq_const_safe!($T: B.extract_bits(_1), B);
+                assert_eq_const_safe!($T: C.extract_bits(_1), C);
+                assert_eq_const_safe!($T: _1.extract_bits(0b0010_0001), 0b0000_0011);
+                assert_eq_const_safe!($T: _1.extract_bits(0b0010_1100), 0b0000_0111);
+                assert_eq_const_safe!($T: _1.extract_bits(0b0111_1001), 0b0001_1111);
             }
 
-            fn test_scatter_bits() {
-                assert_eq_const_safe!($T: $T::scatter_bits(0b1111, 0b1001_0110), 0b1001_0110);
-                assert_eq_const_safe!($T: $T::scatter_bits(0b0001, 0b1001_0110), 0b0000_0010);
-                assert_eq_const_safe!($T: $T::scatter_bits(0b0010, 0b1001_0110), 0b0000_0100);
-                assert_eq_const_safe!($T: $T::scatter_bits(0b0100, 0b1001_0110), 0b0001_0000);
-                assert_eq_const_safe!($T: $T::scatter_bits(0b1000, 0b1001_0110), 0b1000_0000);
+            fn test_deposit_bits() {
+                assert_eq_const_safe!($T: $T::deposit_bits(0b1111, 0b1001_0110), 0b1001_0110);
+                assert_eq_const_safe!($T: $T::deposit_bits(0b0001, 0b1001_0110), 0b0000_0010);
+                assert_eq_const_safe!($T: $T::deposit_bits(0b0010, 0b1001_0110), 0b0000_0100);
+                assert_eq_const_safe!($T: $T::deposit_bits(0b0100, 0b1001_0110), 0b0001_0000);
+                assert_eq_const_safe!($T: $T::deposit_bits(0b1000, 0b1001_0110), 0b1000_0000);
 
-                assert_eq_const_safe!($T: A.scatter_bits(_0), 0);
-                assert_eq_const_safe!($T: B.scatter_bits(_0), 0);
-                assert_eq_const_safe!($T: C.scatter_bits(_0), 0);
-                assert_eq_const_safe!($T: _0.scatter_bits(A), 0);
-                assert_eq_const_safe!($T: _0.scatter_bits(B), 0);
-                assert_eq_const_safe!($T: _0.scatter_bits(C), 0);
+                assert_eq_const_safe!($T: A.deposit_bits(_0), 0);
+                assert_eq_const_safe!($T: B.deposit_bits(_0), 0);
+                assert_eq_const_safe!($T: C.deposit_bits(_0), 0);
+                assert_eq_const_safe!($T: _0.deposit_bits(A), 0);
+                assert_eq_const_safe!($T: _0.deposit_bits(B), 0);
+                assert_eq_const_safe!($T: _0.deposit_bits(C), 0);
 
-                assert_eq_const_safe!($T: A.scatter_bits(_1), A);
-                assert_eq_const_safe!($T: B.scatter_bits(_1), B);
-                assert_eq_const_safe!($T: C.scatter_bits(_1), C);
-                assert_eq_const_safe!($T: _1.scatter_bits(A), A);
-                assert_eq_const_safe!($T: _1.scatter_bits(B), B);
-                assert_eq_const_safe!($T: _1.scatter_bits(C), C);
+                assert_eq_const_safe!($T: A.deposit_bits(_1), A);
+                assert_eq_const_safe!($T: B.deposit_bits(_1), B);
+                assert_eq_const_safe!($T: C.deposit_bits(_1), C);
+                assert_eq_const_safe!($T: _1.deposit_bits(A), A);
+                assert_eq_const_safe!($T: _1.deposit_bits(B), B);
+                assert_eq_const_safe!($T: _1.deposit_bits(C), C);
             }
 
             fn test_reverse_bits() {
@@ -389,7 +389,7 @@ macro_rules! uint_module {
 
         #[cfg(not(miri))] // Miri is too slow
         #[test]
-        fn test_lots_of_gather_scatter() {
+        fn test_lots_of_extract_deposit() {
             // Generate a handful of bit patterns to use as inputs
             let xs = {
                 let mut xs = vec![];
@@ -414,7 +414,7 @@ macro_rules! uint_module {
 
             for sparse in sparse_masks {
                 // Collect the set bits to sequential low bits
-                let dense = sparse.gather_bits(sparse);
+                let dense = sparse.extract_bits(sparse);
                 let count = sparse.count_ones();
                 assert_eq!(count, dense.count_ones());
                 assert_eq!(count, dense.trailing_ones());
@@ -424,27 +424,27 @@ macro_rules! uint_module {
                 let mut bit = 1 as $T;
                 for _ in 0..count {
                     let lowest_one = t.isolate_lowest_one();
-                    assert_eq!(lowest_one, bit.scatter_bits(sparse));
-                    assert_eq!(bit, lowest_one.gather_bits(sparse));
+                    assert_eq!(lowest_one, bit.deposit_bits(sparse));
+                    assert_eq!(bit, lowest_one.extract_bits(sparse));
                     t ^= lowest_one;
                     bit <<= 1;
                 }
                 // Other bits are ignored
-                assert_eq!(0, bit.wrapping_neg().scatter_bits(sparse));
-                assert_eq!(0, (!sparse).gather_bits(sparse));
+                assert_eq!(0, bit.wrapping_neg().deposit_bits(sparse));
+                assert_eq!(0, (!sparse).extract_bits(sparse));
 
                 for &x in &xs {
                     // Gather bits from `x & sparse` to `dense`
-                    let dx = x.gather_bits(sparse);
+                    let dx = x.extract_bits(sparse);
                     assert_eq!(dx & !dense, 0);
 
                     // Scatter bits from `x & dense` to `sparse`
-                    let sx = x.scatter_bits(sparse);
+                    let sx = x.deposit_bits(sparse);
                     assert_eq!(sx & !sparse, 0);
 
                     // The other recovers the input (within the mask)
-                    assert_eq!(dx.scatter_bits(sparse), x & sparse);
-                    assert_eq!(sx.gather_bits(sparse), x & dense);
+                    assert_eq!(dx.deposit_bits(sparse), x & sparse);
+                    assert_eq!(sx.extract_bits(sparse), x & dense);
                 }
             }
         }

From a4f92e5d81269a2795647d080760d185897cb12b Mon Sep 17 00:00:00 2001
From: The rustc-josh-sync Cronjob Bot <github-actions@github.com>
Date: Mon, 26 Jan 2026 04:32:16 +0000
Subject: [PATCH 28/97] Prepare for merging from rust-lang/rust

This updates the rust-version file to 873d4682c7d285540b8f28bfe637006cef8918a6.
---
 library/stdarch/rust-version | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/library/stdarch/rust-version b/library/stdarch/rust-version
index df8693cd1ca8..ccc0b55d4dc5 100644
--- a/library/stdarch/rust-version
+++ b/library/stdarch/rust-version
@@ -1 +1 @@
-48622726c4a91c87bf6cd4dbe1000c95df59906e
+873d4682c7d285540b8f28bfe637006cef8918a6

From 246399cb7d7b907f4c0e89cd678bd17a067b6fd1 Mon Sep 17 00:00:00 2001
From: Folkert de Vries <folkert@folkertdev.nl>
Date: Mon, 26 Jan 2026 10:38:04 +0100
Subject: [PATCH 29/97] use `simd_splat`

---
 library/stdarch/crates/core_arch/src/macros.rs   | 11 ++---------
 .../crates/core_arch/src/powerpc/altivec.rs      |  6 +++---
 library/stdarch/crates/core_arch/src/simd.rs     | 16 ++++------------
 3 files changed, 9 insertions(+), 24 deletions(-)

diff --git a/library/stdarch/crates/core_arch/src/macros.rs b/library/stdarch/crates/core_arch/src/macros.rs
index 849297b1fc36..353829633f01 100644
--- a/library/stdarch/crates/core_arch/src/macros.rs
+++ b/library/stdarch/crates/core_arch/src/macros.rs
@@ -90,17 +90,10 @@ macro_rules! types {
         pub struct $name($v [$elem_type; $len]);
 
         impl $name {
-            /// Using `my_simd([x; N])` seemingly fails tests,
-            /// so use this internal helper for it instead.
+            /// Put the same value in every lane.
             #[inline(always)]
             $v fn splat(value: $elem_type) -> $name {
-                #[derive(Copy, Clone)]
-                #[repr(simd)]
-                struct JustOne([$elem_type; 1]);
-                let one = JustOne([value]);
-                // SAFETY: 0 is always in-bounds because we're shuffling
-                // a simd type with exactly one element.
-                unsafe { simd_shuffle!(one, one, [0; $len]) }
+                unsafe { $crate::intrinsics::simd::simd_splat(value) }
             }
 
             /// Returns an array reference containing the entire SIMD vector.
diff --git a/library/stdarch/crates/core_arch/src/powerpc/altivec.rs b/library/stdarch/crates/core_arch/src/powerpc/altivec.rs
index b9a25a9d8563..fb1a9d8ed9e2 100644
--- a/library/stdarch/crates/core_arch/src/powerpc/altivec.rs
+++ b/library/stdarch/crates/core_arch/src/powerpc/altivec.rs
@@ -1457,7 +1457,7 @@ mod sealed {
     #[cfg_attr(test, assert_instr(vspltb, IMM4 = 15))]
     unsafe fn vspltb<const IMM4: u32>(a: vector_signed_char) -> vector_signed_char {
         static_assert_uimm_bits!(IMM4, 4);
-        simd_shuffle(a, a, const { u32x16::from_array([IMM4; 16]) })
+        simd_shuffle(a, a, const { u32x16::splat(IMM4) })
     }
 
     #[inline]
@@ -1465,7 +1465,7 @@ mod sealed {
     #[cfg_attr(test, assert_instr(vsplth, IMM3 = 7))]
     unsafe fn vsplth<const IMM3: u32>(a: vector_signed_short) -> vector_signed_short {
         static_assert_uimm_bits!(IMM3, 3);
-        simd_shuffle(a, a, const { u32x8::from_array([IMM3; 8]) })
+        simd_shuffle(a, a, const { u32x8::splat(IMM3) })
     }
 
     #[inline]
@@ -1474,7 +1474,7 @@ mod sealed {
     #[cfg_attr(all(test, target_feature = "vsx"), assert_instr(xxspltw, IMM2 = 3))]
     unsafe fn vspltw<const IMM2: u32>(a: vector_signed_int) -> vector_signed_int {
         static_assert_uimm_bits!(IMM2, 2);
-        simd_shuffle(a, a, const { u32x4::from_array([IMM2; 4]) })
+        simd_shuffle(a, a, const { u32x4::splat(IMM2) })
     }
 
     #[unstable(feature = "stdarch_powerpc", issue = "111145")]
diff --git a/library/stdarch/crates/core_arch/src/simd.rs b/library/stdarch/crates/core_arch/src/simd.rs
index b670092f5b0f..313c47479203 100644
--- a/library/stdarch/crates/core_arch/src/simd.rs
+++ b/library/stdarch/crates/core_arch/src/simd.rs
@@ -50,14 +50,10 @@ impl<T: SimdElement, const N: usize> Simd<T, N> {
         Self(elements)
     }
 
-    // FIXME: Workaround rust@60637
-    #[inline(always)]
+    #[inline]
     #[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
     pub(crate) const fn splat(value: T) -> Self {
-        let one = Simd([value]);
-        // SAFETY: 0 is always in-bounds because we're shuffling
-        // a simd type with exactly one element.
-        unsafe { simd_shuffle!(one, one, [0; N]) }
+        unsafe { crate::intrinsics::simd::simd_splat(value) }
     }
 
     /// Extract the element at position `index`. Note that `index` is not a constant so this
@@ -182,14 +178,10 @@ impl<T: SimdElement, const N: usize> SimdM<T, N> {
         [zeros, ones][x as usize]
     }
 
-    // FIXME: Workaround rust@60637
-    #[inline(always)]
+    #[inline]
     #[rustc_const_unstable(feature = "stdarch_const_helpers", issue = "none")]
     pub(crate) const fn splat(value: bool) -> Self {
-        let one = SimdM([Self::bool_to_internal(value)]);
-        // SAFETY: 0 is always in-bounds because we're shuffling
-        // a simd type with exactly one element.
-        unsafe { simd_shuffle!(one, one, [0; N]) }
+        unsafe { crate::intrinsics::simd::simd_splat(value) }
     }
 
     #[inline]

From 8a32fcee2fbbb778c3032278aa6be8a6d9425c2f Mon Sep 17 00:00:00 2001
From: Chris Denton <chris@chrisdenton.dev>
Date: Mon, 26 Jan 2026 10:53:42 +0000
Subject: [PATCH 30/97] Update backtrace

---
 library/backtrace | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/library/backtrace b/library/backtrace
index b65ab935fb2e..28ec93b503bf 160000
--- a/library/backtrace
+++ b/library/backtrace
@@ -1 +1 @@
-Subproject commit b65ab935fb2e0d59dba8966ffca09c9cc5a5f57c
+Subproject commit 28ec93b503bf0410745bc3d571bf3dc1caac3019

From aaeb550f6ff84d9086dfd53d5827f3dc3128adf1 Mon Sep 17 00:00:00 2001
From: Chris Denton <chris@chrisdenton.dev>
Date: Mon, 26 Jan 2026 10:54:00 +0000
Subject: [PATCH 31/97] Update windows bindings in std

---
 Cargo.lock                                    |   6 +-
 library/Cargo.lock                            |  14 +-
 library/Cargo.toml                            |   2 +-
 library/std/Cargo.toml                        |   6 +-
 library/std/src/sys/alloc/windows.rs          |   8 +-
 library/std/src/sys/pal/windows/c.rs          |  14 +-
 .../std/src/sys/pal/windows/c/bindings.txt    |   2 +-
 .../std/src/sys/pal/windows/c/windows_sys.rs  | 282 +++++++++---------
 .../Cargo.toml                                |   4 +-
 .../src/lib.rs                                |   0
 src/tools/generate-windows-sys/Cargo.toml     |   2 +-
 src/tools/generate-windows-sys/src/main.rs    |   2 +-
 src/tools/tidy/src/pal.rs                     |   2 +-
 13 files changed, 172 insertions(+), 172 deletions(-)
 rename library/{windows_targets => windows_link}/Cargo.toml (63%)
 rename library/{windows_targets => windows_link}/src/lib.rs (100%)

diff --git a/Cargo.lock b/Cargo.lock
index 41cce3d54ddb..11d4fa025946 100644
--- a/Cargo.lock
+++ b/Cargo.lock
@@ -6419,13 +6419,13 @@ dependencies = [
 
 [[package]]
 name = "windows-bindgen"
-version = "0.61.1"
+version = "0.66.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "9b4e97b01190d32f268a2dfbd3f006f77840633746707fbe40bcee588108a231"
+checksum = "81b7ec123a4eadd44d1f44f76804316b477b2537abed9a2ab950b3c54afa1fcf"
 dependencies = [
  "serde",
  "serde_json",
- "windows-threading 0.1.0",
+ "windows-threading 0.2.1",
 ]
 
 [[package]]
diff --git a/library/Cargo.lock b/library/Cargo.lock
index f6c14bc58a04..608e7e412c3b 100644
--- a/library/Cargo.lock
+++ b/library/Cargo.lock
@@ -346,7 +346,7 @@ dependencies = [
  "vex-sdk",
  "wasi 0.11.1+wasi-snapshot-preview1",
  "wasi 0.14.4+wasi-0.2.4",
- "windows-targets 0.0.0",
+ "windows-link 0.0.0",
 ]
 
 [[package]]
@@ -427,6 +427,10 @@ dependencies = [
  "wit-bindgen",
 ]
 
+[[package]]
+name = "windows-link"
+version = "0.0.0"
+
 [[package]]
 name = "windows-link"
 version = "0.2.1"
@@ -439,20 +443,16 @@ version = "0.60.2"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "f2f500e4d28234f72040990ec9d39e3a6b950f9f22d3dba18416c35882612bcb"
 dependencies = [
- "windows-targets 0.53.5",
+ "windows-targets",
 ]
 
-[[package]]
-name = "windows-targets"
-version = "0.0.0"
-
 [[package]]
 name = "windows-targets"
 version = "0.53.5"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "4945f9f551b88e0d65f3db0bc25c33b8acea4d9e41163edf90dcd0b19f9069f3"
 dependencies = [
- "windows-link",
+ "windows-link 0.2.1",
  "windows_aarch64_gnullvm",
  "windows_aarch64_msvc",
  "windows_i686_gnu",
diff --git a/library/Cargo.toml b/library/Cargo.toml
index b26e5f41c931..87df966bb6b8 100644
--- a/library/Cargo.toml
+++ b/library/Cargo.toml
@@ -12,7 +12,7 @@ members = [
 exclude = [
   # stdarch has its own Cargo workspace
   "stdarch",
-  "windows_targets"
+  "windows_link"
 ]
 
 [profile.release.package.compiler_builtins]
diff --git a/library/std/Cargo.toml b/library/std/Cargo.toml
index 5c9ae52d9e6c..87887f113b79 100644
--- a/library/std/Cargo.toml
+++ b/library/std/Cargo.toml
@@ -55,8 +55,8 @@ object = { version = "0.37.1", default-features = false, optional = true, featur
     'archive',
 ] }
 
-[target.'cfg(any(windows, target_os = "cygwin"))'.dependencies.windows-targets]
-path = "../windows_targets"
+[target.'cfg(any(windows, target_os = "cygwin"))'.dependencies.windows-link]
+path = "../windows_link"
 
 [dev-dependencies]
 rand = { version = "0.9.0", default-features = false, features = ["alloc"] }
@@ -130,7 +130,7 @@ llvm_enzyme = ["core/llvm_enzyme"]
 
 # Enable using raw-dylib for Windows imports.
 # This will eventually be the default.
-windows_raw_dylib = ["windows-targets/windows_raw_dylib"]
+windows_raw_dylib = ["windows-link/windows_raw_dylib"]
 
 [package.metadata.fortanix-sgx]
 # Maximum possible number of threads when testing
diff --git a/library/std/src/sys/alloc/windows.rs b/library/std/src/sys/alloc/windows.rs
index 7e2402afab97..90da0b7e9965 100644
--- a/library/std/src/sys/alloc/windows.rs
+++ b/library/std/src/sys/alloc/windows.rs
@@ -20,7 +20,7 @@ const HEAP_ZERO_MEMORY: u32 = 0x00000008;
 // always return the same handle, which remains valid for the entire lifetime of the process.
 //
 // See https://docs.microsoft.com/windows/win32/api/heapapi/nf-heapapi-getprocessheap
-windows_targets::link!("kernel32.dll" "system" fn GetProcessHeap() -> c::HANDLE);
+windows_link::link!("kernel32.dll" "system" fn GetProcessHeap() -> c::HANDLE);
 
 // Allocate a block of `dwBytes` bytes of memory from a given heap `hHeap`.
 // The allocated memory may be uninitialized, or zeroed if `dwFlags` is
@@ -36,7 +36,7 @@ windows_targets::link!("kernel32.dll" "system" fn GetProcessHeap() -> c::HANDLE)
 // Note that `dwBytes` is allowed to be zero, contrary to some other allocators.
 //
 // See https://docs.microsoft.com/windows/win32/api/heapapi/nf-heapapi-heapalloc
-windows_targets::link!("kernel32.dll" "system" fn HeapAlloc(hheap: c::HANDLE, dwflags: u32, dwbytes: usize) -> *mut c_void);
+windows_link::link!("kernel32.dll" "system" fn HeapAlloc(hheap: c::HANDLE, dwflags: u32, dwbytes: usize) -> *mut c_void);
 
 // Reallocate a block of memory behind a given pointer `lpMem` from a given heap `hHeap`,
 // to a block of at least `dwBytes` bytes, either shrinking the block in place,
@@ -57,7 +57,7 @@ windows_targets::link!("kernel32.dll" "system" fn HeapAlloc(hheap: c::HANDLE, dw
 // Note that `dwBytes` is allowed to be zero, contrary to some other allocators.
 //
 // See https://docs.microsoft.com/windows/win32/api/heapapi/nf-heapapi-heaprealloc
-windows_targets::link!("kernel32.dll" "system" fn HeapReAlloc(
+windows_link::link!("kernel32.dll" "system" fn HeapReAlloc(
     hheap: c::HANDLE,
     dwflags : u32,
     lpmem: *const c_void,
@@ -78,7 +78,7 @@ windows_targets::link!("kernel32.dll" "system" fn HeapReAlloc(
 // Note that `lpMem` is allowed to be null, which will not cause the operation to fail.
 //
 // See https://docs.microsoft.com/windows/win32/api/heapapi/nf-heapapi-heapfree
-windows_targets::link!("kernel32.dll" "system" fn HeapFree(hheap: c::HANDLE, dwflags: u32, lpmem: *const c_void) -> c::BOOL);
+windows_link::link!("kernel32.dll" "system" fn HeapFree(hheap: c::HANDLE, dwflags: u32, lpmem: *const c_void) -> c::BOOL);
 
 fn get_process_heap() -> *mut c_void {
     // SAFETY: GetProcessHeap simply returns a valid handle or NULL so is always safe to call.
diff --git a/library/std/src/sys/pal/windows/c.rs b/library/std/src/sys/pal/windows/c.rs
index 0f54f80d72ee..9f1a51c7dd3f 100644
--- a/library/std/src/sys/pal/windows/c.rs
+++ b/library/std/src/sys/pal/windows/c.rs
@@ -109,7 +109,7 @@ unsafe extern "system" {
     pub fn ProcessPrng(pbdata: *mut u8, cbdata: usize) -> BOOL;
 }
 
-windows_targets::link!("ntdll.dll" "system" fn NtCreateNamedPipeFile(
+windows_link::link!("ntdll.dll" "system" fn NtCreateNamedPipeFile(
     filehandle: *mut HANDLE,
     desiredaccess: FILE_ACCESS_RIGHTS,
     objectattributes: *const OBJECT_ATTRIBUTES,
@@ -229,15 +229,15 @@ compat_fn_with_fallback! {
 
 cfg_select! {
     target_vendor = "uwp" => {
-        windows_targets::link_raw_dylib!("ntdll.dll" "system" fn NtCreateFile(filehandle : *mut HANDLE, desiredaccess : FILE_ACCESS_RIGHTS, objectattributes : *const OBJECT_ATTRIBUTES, iostatusblock : *mut IO_STATUS_BLOCK, allocationsize : *const i64, fileattributes : FILE_FLAGS_AND_ATTRIBUTES, shareaccess : FILE_SHARE_MODE, createdisposition : NTCREATEFILE_CREATE_DISPOSITION, createoptions : NTCREATEFILE_CREATE_OPTIONS, eabuffer : *const core::ffi::c_void, ealength : u32) -> NTSTATUS);
-        windows_targets::link_raw_dylib!("ntdll.dll" "system" fn NtOpenFile(filehandle : *mut HANDLE, desiredaccess : u32, objectattributes : *const OBJECT_ATTRIBUTES, iostatusblock : *mut IO_STATUS_BLOCK, shareaccess : u32, openoptions : u32) -> NTSTATUS);
-        windows_targets::link_raw_dylib!("ntdll.dll" "system" fn NtReadFile(filehandle : HANDLE, event : HANDLE, apcroutine : PIO_APC_ROUTINE, apccontext : *const core::ffi::c_void, iostatusblock : *mut IO_STATUS_BLOCK, buffer : *mut core::ffi::c_void, length : u32, byteoffset : *const i64, key : *const u32) -> NTSTATUS);
-        windows_targets::link_raw_dylib!("ntdll.dll" "system" fn NtWriteFile(filehandle : HANDLE, event : HANDLE, apcroutine : PIO_APC_ROUTINE, apccontext : *const core::ffi::c_void, iostatusblock : *mut IO_STATUS_BLOCK, buffer : *const core::ffi::c_void, length : u32, byteoffset : *const i64, key : *const u32) -> NTSTATUS);
-        windows_targets::link_raw_dylib!("ntdll.dll" "system" fn RtlNtStatusToDosError(status : NTSTATUS) -> u32);
+        windows_link::link_raw_dylib!("ntdll.dll" "system" fn NtCreateFile(filehandle : *mut HANDLE, desiredaccess : FILE_ACCESS_RIGHTS, objectattributes : *const OBJECT_ATTRIBUTES, iostatusblock : *mut IO_STATUS_BLOCK, allocationsize : *const i64, fileattributes : FILE_FLAGS_AND_ATTRIBUTES, shareaccess : FILE_SHARE_MODE, createdisposition : NTCREATEFILE_CREATE_DISPOSITION, createoptions : NTCREATEFILE_CREATE_OPTIONS, eabuffer : *const core::ffi::c_void, ealength : u32) -> NTSTATUS);
+        windows_link::link_raw_dylib!("ntdll.dll" "system" fn NtOpenFile(filehandle : *mut HANDLE, desiredaccess : u32, objectattributes : *const OBJECT_ATTRIBUTES, iostatusblock : *mut IO_STATUS_BLOCK, shareaccess : u32, openoptions : u32) -> NTSTATUS);
+        windows_link::link_raw_dylib!("ntdll.dll" "system" fn NtReadFile(filehandle : HANDLE, event : HANDLE, apcroutine : PIO_APC_ROUTINE, apccontext : *const core::ffi::c_void, iostatusblock : *mut IO_STATUS_BLOCK, buffer : *mut core::ffi::c_void, length : u32, byteoffset : *const i64, key : *const u32) -> NTSTATUS);
+        windows_link::link_raw_dylib!("ntdll.dll" "system" fn NtWriteFile(filehandle : HANDLE, event : HANDLE, apcroutine : PIO_APC_ROUTINE, apccontext : *const core::ffi::c_void, iostatusblock : *mut IO_STATUS_BLOCK, buffer : *const core::ffi::c_void, length : u32, byteoffset : *const i64, key : *const u32) -> NTSTATUS);
+        windows_link::link_raw_dylib!("ntdll.dll" "system" fn RtlNtStatusToDosError(status : NTSTATUS) -> u32);
     }
     _ => {}
 }
 
 // Only available starting with Windows 8.
 #[cfg(not(target_vendor = "win7"))]
-windows_targets::link!("ws2_32.dll" "system" fn GetHostNameW(name : PWSTR, namelen : i32) -> i32);
+windows_link::link!("ws2_32.dll" "system" fn GetHostNameW(name : PWSTR, namelen : i32) -> i32);
diff --git a/library/std/src/sys/pal/windows/c/bindings.txt b/library/std/src/sys/pal/windows/c/bindings.txt
index 12babcb84ccf..c21d1de81341 100644
--- a/library/std/src/sys/pal/windows/c/bindings.txt
+++ b/library/std/src/sys/pal/windows/c/bindings.txt
@@ -2,7 +2,7 @@
 --flat
 --sys
 --no-deps
---link windows_targets
+--link windows_link
 --filter
 !INVALID_HANDLE_VALUE
 ABOVE_NORMAL_PRIORITY_CLASS
diff --git a/library/std/src/sys/pal/windows/c/windows_sys.rs b/library/std/src/sys/pal/windows/c/windows_sys.rs
index edc9d2d11f7c..eb54efd1c1fe 100644
--- a/library/std/src/sys/pal/windows/c/windows_sys.rs
+++ b/library/std/src/sys/pal/windows/c/windows_sys.rs
@@ -1,147 +1,147 @@
-// Bindings generated by `windows-bindgen` 0.61.1
+// Bindings generated by `windows-bindgen` 0.66.0
 
 #![allow(non_snake_case, non_upper_case_globals, non_camel_case_types, dead_code, clippy::all)]
 
-windows_targets::link!("kernel32.dll" "system" fn AcquireSRWLockExclusive(srwlock : *mut SRWLOCK));
-windows_targets::link!("kernel32.dll" "system" fn AcquireSRWLockShared(srwlock : *mut SRWLOCK));
-windows_targets::link!("kernel32.dll" "system" fn AddVectoredExceptionHandler(first : u32, handler : PVECTORED_EXCEPTION_HANDLER) -> *mut core::ffi::c_void);
-windows_targets::link!("kernel32.dll" "system" fn CancelIo(hfile : HANDLE) -> BOOL);
-windows_targets::link!("kernel32.dll" "system" fn CloseHandle(hobject : HANDLE) -> BOOL);
-windows_targets::link!("kernel32.dll" "system" fn CompareStringOrdinal(lpstring1 : PCWSTR, cchcount1 : i32, lpstring2 : PCWSTR, cchcount2 : i32, bignorecase : BOOL) -> COMPARESTRING_RESULT);
-windows_targets::link!("kernel32.dll" "system" fn CopyFileExW(lpexistingfilename : PCWSTR, lpnewfilename : PCWSTR, lpprogressroutine : LPPROGRESS_ROUTINE, lpdata : *const core::ffi::c_void, pbcancel : *mut BOOL, dwcopyflags : COPYFILE_FLAGS) -> BOOL);
-windows_targets::link!("kernel32.dll" "system" fn CreateDirectoryW(lppathname : PCWSTR, lpsecurityattributes : *const SECURITY_ATTRIBUTES) -> BOOL);
-windows_targets::link!("kernel32.dll" "system" fn CreateEventW(lpeventattributes : *const SECURITY_ATTRIBUTES, bmanualreset : BOOL, binitialstate : BOOL, lpname : PCWSTR) -> HANDLE);
-windows_targets::link!("kernel32.dll" "system" fn CreateFileW(lpfilename : PCWSTR, dwdesiredaccess : u32, dwsharemode : FILE_SHARE_MODE, lpsecurityattributes : *const SECURITY_ATTRIBUTES, dwcreationdisposition : FILE_CREATION_DISPOSITION, dwflagsandattributes : FILE_FLAGS_AND_ATTRIBUTES, htemplatefile : HANDLE) -> HANDLE);
-windows_targets::link!("kernel32.dll" "system" fn CreateHardLinkW(lpfilename : PCWSTR, lpexistingfilename : PCWSTR, lpsecurityattributes : *const SECURITY_ATTRIBUTES) -> BOOL);
-windows_targets::link!("kernel32.dll" "system" fn CreateNamedPipeW(lpname : PCWSTR, dwopenmode : FILE_FLAGS_AND_ATTRIBUTES, dwpipemode : NAMED_PIPE_MODE, nmaxinstances : u32, noutbuffersize : u32, ninbuffersize : u32, ndefaulttimeout : u32, lpsecurityattributes : *const SECURITY_ATTRIBUTES) -> HANDLE);
-windows_targets::link!("kernel32.dll" "system" fn CreatePipe(hreadpipe : *mut HANDLE, hwritepipe : *mut HANDLE, lppipeattributes : *const SECURITY_ATTRIBUTES, nsize : u32) -> BOOL);
-windows_targets::link!("kernel32.dll" "system" fn CreateProcessW(lpapplicationname : PCWSTR, lpcommandline : PWSTR, lpprocessattributes : *const SECURITY_ATTRIBUTES, lpthreadattributes : *const SECURITY_ATTRIBUTES, binherithandles : BOOL, dwcreationflags : PROCESS_CREATION_FLAGS, lpenvironment : *const core::ffi::c_void, lpcurrentdirectory : PCWSTR, lpstartupinfo : *const STARTUPINFOW, lpprocessinformation : *mut PROCESS_INFORMATION) -> BOOL);
-windows_targets::link!("kernel32.dll" "system" fn CreateSymbolicLinkW(lpsymlinkfilename : PCWSTR, lptargetfilename : PCWSTR, dwflags : SYMBOLIC_LINK_FLAGS) -> bool);
-windows_targets::link!("kernel32.dll" "system" fn CreateThread(lpthreadattributes : *const SECURITY_ATTRIBUTES, dwstacksize : usize, lpstartaddress : LPTHREAD_START_ROUTINE, lpparameter : *const core::ffi::c_void, dwcreationflags : THREAD_CREATION_FLAGS, lpthreadid : *mut u32) -> HANDLE);
-windows_targets::link!("kernel32.dll" "system" fn CreateWaitableTimerExW(lptimerattributes : *const SECURITY_ATTRIBUTES, lptimername : PCWSTR, dwflags : u32, dwdesiredaccess : u32) -> HANDLE);
-windows_targets::link!("kernel32.dll" "system" fn DeleteFileW(lpfilename : PCWSTR) -> BOOL);
-windows_targets::link!("kernel32.dll" "system" fn DeleteProcThreadAttributeList(lpattributelist : LPPROC_THREAD_ATTRIBUTE_LIST));
-windows_targets::link!("kernel32.dll" "system" fn DeviceIoControl(hdevice : HANDLE, dwiocontrolcode : u32, lpinbuffer : *const core::ffi::c_void, ninbuffersize : u32, lpoutbuffer : *mut core::ffi::c_void, noutbuffersize : u32, lpbytesreturned : *mut u32, lpoverlapped : *mut OVERLAPPED) -> BOOL);
-windows_targets::link!("kernel32.dll" "system" fn DuplicateHandle(hsourceprocesshandle : HANDLE, hsourcehandle : HANDLE, htargetprocesshandle : HANDLE, lptargethandle : *mut HANDLE, dwdesiredaccess : u32, binherithandle : BOOL, dwoptions : DUPLICATE_HANDLE_OPTIONS) -> BOOL);
-windows_targets::link!("kernel32.dll" "system" fn ExitProcess(uexitcode : u32) -> !);
-windows_targets::link!("kernel32.dll" "system" fn FindClose(hfindfile : HANDLE) -> BOOL);
-windows_targets::link!("kernel32.dll" "system" fn FindFirstFileExW(lpfilename : PCWSTR, finfolevelid : FINDEX_INFO_LEVELS, lpfindfiledata : *mut core::ffi::c_void, fsearchop : FINDEX_SEARCH_OPS, lpsearchfilter : *const core::ffi::c_void, dwadditionalflags : FIND_FIRST_EX_FLAGS) -> HANDLE);
-windows_targets::link!("kernel32.dll" "system" fn FindNextFileW(hfindfile : HANDLE, lpfindfiledata : *mut WIN32_FIND_DATAW) -> BOOL);
-windows_targets::link!("kernel32.dll" "system" fn FlushFileBuffers(hfile : HANDLE) -> BOOL);
-windows_targets::link!("kernel32.dll" "system" fn FormatMessageW(dwflags : FORMAT_MESSAGE_OPTIONS, lpsource : *const core::ffi::c_void, dwmessageid : u32, dwlanguageid : u32, lpbuffer : PWSTR, nsize : u32, arguments : *const *const i8) -> u32);
-windows_targets::link!("kernel32.dll" "system" fn FreeEnvironmentStringsW(penv : PCWSTR) -> BOOL);
-windows_targets::link!("kernel32.dll" "system" fn GetActiveProcessorCount(groupnumber : u16) -> u32);
-windows_targets::link!("kernel32.dll" "system" fn GetCommandLineW() -> PCWSTR);
-windows_targets::link!("kernel32.dll" "system" fn GetConsoleMode(hconsolehandle : HANDLE, lpmode : *mut CONSOLE_MODE) -> BOOL);
-windows_targets::link!("kernel32.dll" "system" fn GetConsoleOutputCP() -> u32);
-windows_targets::link!("kernel32.dll" "system" fn GetCurrentDirectoryW(nbufferlength : u32, lpbuffer : PWSTR) -> u32);
-windows_targets::link!("kernel32.dll" "system" fn GetCurrentProcess() -> HANDLE);
-windows_targets::link!("kernel32.dll" "system" fn GetCurrentProcessId() -> u32);
-windows_targets::link!("kernel32.dll" "system" fn GetCurrentThread() -> HANDLE);
-windows_targets::link!("kernel32.dll" "system" fn GetCurrentThreadId() -> u32);
-windows_targets::link!("kernel32.dll" "system" fn GetEnvironmentStringsW() -> PWSTR);
-windows_targets::link!("kernel32.dll" "system" fn GetEnvironmentVariableW(lpname : PCWSTR, lpbuffer : PWSTR, nsize : u32) -> u32);
-windows_targets::link!("kernel32.dll" "system" fn GetExitCodeProcess(hprocess : HANDLE, lpexitcode : *mut u32) -> BOOL);
-windows_targets::link!("kernel32.dll" "system" fn GetFileAttributesW(lpfilename : PCWSTR) -> u32);
-windows_targets::link!("kernel32.dll" "system" fn GetFileInformationByHandle(hfile : HANDLE, lpfileinformation : *mut BY_HANDLE_FILE_INFORMATION) -> BOOL);
-windows_targets::link!("kernel32.dll" "system" fn GetFileInformationByHandleEx(hfile : HANDLE, fileinformationclass : FILE_INFO_BY_HANDLE_CLASS, lpfileinformation : *mut core::ffi::c_void, dwbuffersize : u32) -> BOOL);
-windows_targets::link!("kernel32.dll" "system" fn GetFileSizeEx(hfile : HANDLE, lpfilesize : *mut i64) -> BOOL);
-windows_targets::link!("kernel32.dll" "system" fn GetFileType(hfile : HANDLE) -> FILE_TYPE);
-windows_targets::link!("kernel32.dll" "system" fn GetFinalPathNameByHandleW(hfile : HANDLE, lpszfilepath : PWSTR, cchfilepath : u32, dwflags : GETFINALPATHNAMEBYHANDLE_FLAGS) -> u32);
-windows_targets::link!("kernel32.dll" "system" fn GetFullPathNameW(lpfilename : PCWSTR, nbufferlength : u32, lpbuffer : PWSTR, lpfilepart : *mut PWSTR) -> u32);
-windows_targets::link!("kernel32.dll" "system" fn GetLastError() -> WIN32_ERROR);
-windows_targets::link!("kernel32.dll" "system" fn GetModuleFileNameW(hmodule : HMODULE, lpfilename : PWSTR, nsize : u32) -> u32);
-windows_targets::link!("kernel32.dll" "system" fn GetModuleHandleA(lpmodulename : PCSTR) -> HMODULE);
-windows_targets::link!("kernel32.dll" "system" fn GetModuleHandleW(lpmodulename : PCWSTR) -> HMODULE);
-windows_targets::link!("kernel32.dll" "system" fn GetOverlappedResult(hfile : HANDLE, lpoverlapped : *const OVERLAPPED, lpnumberofbytestransferred : *mut u32, bwait : BOOL) -> BOOL);
-windows_targets::link!("kernel32.dll" "system" fn GetProcAddress(hmodule : HMODULE, lpprocname : PCSTR) -> FARPROC);
-windows_targets::link!("kernel32.dll" "system" fn GetProcessId(process : HANDLE) -> u32);
-windows_targets::link!("kernel32.dll" "system" fn GetStdHandle(nstdhandle : STD_HANDLE) -> HANDLE);
-windows_targets::link!("kernel32.dll" "system" fn GetSystemDirectoryW(lpbuffer : PWSTR, usize : u32) -> u32);
-windows_targets::link!("kernel32.dll" "system" fn GetSystemInfo(lpsysteminfo : *mut SYSTEM_INFO));
-windows_targets::link!("kernel32.dll" "system" fn GetSystemTimeAsFileTime(lpsystemtimeasfiletime : *mut FILETIME));
-windows_targets::link!("kernel32.dll" "system" fn GetSystemTimePreciseAsFileTime(lpsystemtimeasfiletime : *mut FILETIME));
-windows_targets::link!("kernel32.dll" "system" fn GetTempPathW(nbufferlength : u32, lpbuffer : PWSTR) -> u32);
-windows_targets::link!("userenv.dll" "system" fn GetUserProfileDirectoryW(htoken : HANDLE, lpprofiledir : PWSTR, lpcchsize : *mut u32) -> BOOL);
-windows_targets::link!("kernel32.dll" "system" fn GetWindowsDirectoryW(lpbuffer : PWSTR, usize : u32) -> u32);
-windows_targets::link!("kernel32.dll" "system" fn InitOnceBeginInitialize(lpinitonce : *mut INIT_ONCE, dwflags : u32, fpending : *mut BOOL, lpcontext : *mut *mut core::ffi::c_void) -> BOOL);
-windows_targets::link!("kernel32.dll" "system" fn InitOnceComplete(lpinitonce : *mut INIT_ONCE, dwflags : u32, lpcontext : *const core::ffi::c_void) -> BOOL);
-windows_targets::link!("kernel32.dll" "system" fn InitializeProcThreadAttributeList(lpattributelist : LPPROC_THREAD_ATTRIBUTE_LIST, dwattributecount : u32, dwflags : u32, lpsize : *mut usize) -> BOOL);
-windows_targets::link!("kernel32.dll" "system" fn LocalFree(hmem : HLOCAL) -> HLOCAL);
-windows_targets::link!("kernel32.dll" "system" fn LockFileEx(hfile : HANDLE, dwflags : LOCK_FILE_FLAGS, dwreserved : u32, nnumberofbytestolocklow : u32, nnumberofbytestolockhigh : u32, lpoverlapped : *mut OVERLAPPED) -> BOOL);
-windows_targets::link!("kernel32.dll" "system" fn MoveFileExW(lpexistingfilename : PCWSTR, lpnewfilename : PCWSTR, dwflags : MOVE_FILE_FLAGS) -> BOOL);
-windows_targets::link!("kernel32.dll" "system" fn MultiByteToWideChar(codepage : u32, dwflags : MULTI_BYTE_TO_WIDE_CHAR_FLAGS, lpmultibytestr : PCSTR, cbmultibyte : i32, lpwidecharstr : PWSTR, cchwidechar : i32) -> i32);
-windows_targets::link!("ntdll.dll" "system" fn NtCreateFile(filehandle : *mut HANDLE, desiredaccess : FILE_ACCESS_RIGHTS, objectattributes : *const OBJECT_ATTRIBUTES, iostatusblock : *mut IO_STATUS_BLOCK, allocationsize : *const i64, fileattributes : FILE_FLAGS_AND_ATTRIBUTES, shareaccess : FILE_SHARE_MODE, createdisposition : NTCREATEFILE_CREATE_DISPOSITION, createoptions : NTCREATEFILE_CREATE_OPTIONS, eabuffer : *const core::ffi::c_void, ealength : u32) -> NTSTATUS);
-windows_targets::link!("ntdll.dll" "system" fn NtOpenFile(filehandle : *mut HANDLE, desiredaccess : u32, objectattributes : *const OBJECT_ATTRIBUTES, iostatusblock : *mut IO_STATUS_BLOCK, shareaccess : u32, openoptions : u32) -> NTSTATUS);
-windows_targets::link!("ntdll.dll" "system" fn NtReadFile(filehandle : HANDLE, event : HANDLE, apcroutine : PIO_APC_ROUTINE, apccontext : *const core::ffi::c_void, iostatusblock : *mut IO_STATUS_BLOCK, buffer : *mut core::ffi::c_void, length : u32, byteoffset : *const i64, key : *const u32) -> NTSTATUS);
-windows_targets::link!("ntdll.dll" "system" fn NtWriteFile(filehandle : HANDLE, event : HANDLE, apcroutine : PIO_APC_ROUTINE, apccontext : *const core::ffi::c_void, iostatusblock : *mut IO_STATUS_BLOCK, buffer : *const core::ffi::c_void, length : u32, byteoffset : *const i64, key : *const u32) -> NTSTATUS);
-windows_targets::link!("advapi32.dll" "system" fn OpenProcessToken(processhandle : HANDLE, desiredaccess : TOKEN_ACCESS_MASK, tokenhandle : *mut HANDLE) -> BOOL);
-windows_targets::link!("kernel32.dll" "system" fn QueryPerformanceCounter(lpperformancecount : *mut i64) -> BOOL);
-windows_targets::link!("kernel32.dll" "system" fn QueryPerformanceFrequency(lpfrequency : *mut i64) -> BOOL);
-windows_targets::link!("kernel32.dll" "system" fn ReadConsoleW(hconsoleinput : HANDLE, lpbuffer : *mut core::ffi::c_void, nnumberofcharstoread : u32, lpnumberofcharsread : *mut u32, pinputcontrol : *const CONSOLE_READCONSOLE_CONTROL) -> BOOL);
-windows_targets::link!("kernel32.dll" "system" fn ReadFile(hfile : HANDLE, lpbuffer : *mut u8, nnumberofbytestoread : u32, lpnumberofbytesread : *mut u32, lpoverlapped : *mut OVERLAPPED) -> BOOL);
-windows_targets::link!("kernel32.dll" "system" fn ReadFileEx(hfile : HANDLE, lpbuffer : *mut u8, nnumberofbytestoread : u32, lpoverlapped : *mut OVERLAPPED, lpcompletionroutine : LPOVERLAPPED_COMPLETION_ROUTINE) -> BOOL);
-windows_targets::link!("kernel32.dll" "system" fn ReleaseSRWLockExclusive(srwlock : *mut SRWLOCK));
-windows_targets::link!("kernel32.dll" "system" fn ReleaseSRWLockShared(srwlock : *mut SRWLOCK));
-windows_targets::link!("kernel32.dll" "system" fn RemoveDirectoryW(lppathname : PCWSTR) -> BOOL);
-windows_targets::link!("advapi32.dll" "system" "SystemFunction036" fn RtlGenRandom(randombuffer : *mut core::ffi::c_void, randombufferlength : u32) -> bool);
-windows_targets::link!("ntdll.dll" "system" fn RtlNtStatusToDosError(status : NTSTATUS) -> u32);
-windows_targets::link!("kernel32.dll" "system" fn SetCurrentDirectoryW(lppathname : PCWSTR) -> BOOL);
-windows_targets::link!("kernel32.dll" "system" fn SetEnvironmentVariableW(lpname : PCWSTR, lpvalue : PCWSTR) -> BOOL);
-windows_targets::link!("kernel32.dll" "system" fn SetFileAttributesW(lpfilename : PCWSTR, dwfileattributes : FILE_FLAGS_AND_ATTRIBUTES) -> BOOL);
-windows_targets::link!("kernel32.dll" "system" fn SetFileInformationByHandle(hfile : HANDLE, fileinformationclass : FILE_INFO_BY_HANDLE_CLASS, lpfileinformation : *const core::ffi::c_void, dwbuffersize : u32) -> BOOL);
-windows_targets::link!("kernel32.dll" "system" fn SetFilePointerEx(hfile : HANDLE, lidistancetomove : i64, lpnewfilepointer : *mut i64, dwmovemethod : SET_FILE_POINTER_MOVE_METHOD) -> BOOL);
-windows_targets::link!("kernel32.dll" "system" fn SetFileTime(hfile : HANDLE, lpcreationtime : *const FILETIME, lplastaccesstime : *const FILETIME, lplastwritetime : *const FILETIME) -> BOOL);
-windows_targets::link!("kernel32.dll" "system" fn SetHandleInformation(hobject : HANDLE, dwmask : u32, dwflags : HANDLE_FLAGS) -> BOOL);
-windows_targets::link!("kernel32.dll" "system" fn SetLastError(dwerrcode : WIN32_ERROR));
-windows_targets::link!("kernel32.dll" "system" fn SetThreadStackGuarantee(stacksizeinbytes : *mut u32) -> BOOL);
-windows_targets::link!("kernel32.dll" "system" fn SetWaitableTimer(htimer : HANDLE, lpduetime : *const i64, lperiod : i32, pfncompletionroutine : PTIMERAPCROUTINE, lpargtocompletionroutine : *const core::ffi::c_void, fresume : BOOL) -> BOOL);
-windows_targets::link!("kernel32.dll" "system" fn Sleep(dwmilliseconds : u32));
-windows_targets::link!("kernel32.dll" "system" fn SleepConditionVariableSRW(conditionvariable : *mut CONDITION_VARIABLE, srwlock : *mut SRWLOCK, dwmilliseconds : u32, flags : u32) -> BOOL);
-windows_targets::link!("kernel32.dll" "system" fn SleepEx(dwmilliseconds : u32, balertable : BOOL) -> u32);
-windows_targets::link!("kernel32.dll" "system" fn SwitchToThread() -> BOOL);
-windows_targets::link!("kernel32.dll" "system" fn TerminateProcess(hprocess : HANDLE, uexitcode : u32) -> BOOL);
-windows_targets::link!("kernel32.dll" "system" fn TlsAlloc() -> u32);
-windows_targets::link!("kernel32.dll" "system" fn TlsFree(dwtlsindex : u32) -> BOOL);
-windows_targets::link!("kernel32.dll" "system" fn TlsGetValue(dwtlsindex : u32) -> *mut core::ffi::c_void);
-windows_targets::link!("kernel32.dll" "system" fn TlsSetValue(dwtlsindex : u32, lptlsvalue : *const core::ffi::c_void) -> BOOL);
-windows_targets::link!("kernel32.dll" "system" fn TryAcquireSRWLockExclusive(srwlock : *mut SRWLOCK) -> bool);
-windows_targets::link!("kernel32.dll" "system" fn TryAcquireSRWLockShared(srwlock : *mut SRWLOCK) -> bool);
-windows_targets::link!("kernel32.dll" "system" fn UnlockFile(hfile : HANDLE, dwfileoffsetlow : u32, dwfileoffsethigh : u32, nnumberofbytestounlocklow : u32, nnumberofbytestounlockhigh : u32) -> BOOL);
-windows_targets::link!("kernel32.dll" "system" fn UpdateProcThreadAttribute(lpattributelist : LPPROC_THREAD_ATTRIBUTE_LIST, dwflags : u32, attribute : usize, lpvalue : *const core::ffi::c_void, cbsize : usize, lppreviousvalue : *mut core::ffi::c_void, lpreturnsize : *const usize) -> BOOL);
-windows_targets::link!("ws2_32.dll" "system" fn WSACleanup() -> i32);
-windows_targets::link!("ws2_32.dll" "system" fn WSADuplicateSocketW(s : SOCKET, dwprocessid : u32, lpprotocolinfo : *mut WSAPROTOCOL_INFOW) -> i32);
-windows_targets::link!("ws2_32.dll" "system" fn WSAGetLastError() -> WSA_ERROR);
-windows_targets::link!("ws2_32.dll" "system" fn WSARecv(s : SOCKET, lpbuffers : *const WSABUF, dwbuffercount : u32, lpnumberofbytesrecvd : *mut u32, lpflags : *mut u32, lpoverlapped : *mut OVERLAPPED, lpcompletionroutine : LPWSAOVERLAPPED_COMPLETION_ROUTINE) -> i32);
-windows_targets::link!("ws2_32.dll" "system" fn WSASend(s : SOCKET, lpbuffers : *const WSABUF, dwbuffercount : u32, lpnumberofbytessent : *mut u32, dwflags : u32, lpoverlapped : *mut OVERLAPPED, lpcompletionroutine : LPWSAOVERLAPPED_COMPLETION_ROUTINE) -> i32);
-windows_targets::link!("ws2_32.dll" "system" fn WSASocketW(af : i32, r#type : i32, protocol : i32, lpprotocolinfo : *const WSAPROTOCOL_INFOW, g : u32, dwflags : u32) -> SOCKET);
-windows_targets::link!("ws2_32.dll" "system" fn WSAStartup(wversionrequested : u16, lpwsadata : *mut WSADATA) -> i32);
-windows_targets::link!("kernel32.dll" "system" fn WaitForMultipleObjects(ncount : u32, lphandles : *const HANDLE, bwaitall : BOOL, dwmilliseconds : u32) -> WAIT_EVENT);
-windows_targets::link!("kernel32.dll" "system" fn WaitForSingleObject(hhandle : HANDLE, dwmilliseconds : u32) -> WAIT_EVENT);
-windows_targets::link!("kernel32.dll" "system" fn WakeAllConditionVariable(conditionvariable : *mut CONDITION_VARIABLE));
-windows_targets::link!("kernel32.dll" "system" fn WakeConditionVariable(conditionvariable : *mut CONDITION_VARIABLE));
-windows_targets::link!("kernel32.dll" "system" fn WideCharToMultiByte(codepage : u32, dwflags : u32, lpwidecharstr : PCWSTR, cchwidechar : i32, lpmultibytestr : PSTR, cbmultibyte : i32, lpdefaultchar : PCSTR, lpuseddefaultchar : *mut BOOL) -> i32);
-windows_targets::link!("kernel32.dll" "system" fn WriteConsoleW(hconsoleoutput : HANDLE, lpbuffer : PCWSTR, nnumberofcharstowrite : u32, lpnumberofcharswritten : *mut u32, lpreserved : *const core::ffi::c_void) -> BOOL);
-windows_targets::link!("kernel32.dll" "system" fn WriteFileEx(hfile : HANDLE, lpbuffer : *const u8, nnumberofbytestowrite : u32, lpoverlapped : *mut OVERLAPPED, lpcompletionroutine : LPOVERLAPPED_COMPLETION_ROUTINE) -> BOOL);
-windows_targets::link!("ws2_32.dll" "system" fn accept(s : SOCKET, addr : *mut SOCKADDR, addrlen : *mut i32) -> SOCKET);
-windows_targets::link!("ws2_32.dll" "system" fn bind(s : SOCKET, name : *const SOCKADDR, namelen : i32) -> i32);
-windows_targets::link!("ws2_32.dll" "system" fn closesocket(s : SOCKET) -> i32);
-windows_targets::link!("ws2_32.dll" "system" fn connect(s : SOCKET, name : *const SOCKADDR, namelen : i32) -> i32);
-windows_targets::link!("ws2_32.dll" "system" fn freeaddrinfo(paddrinfo : *const ADDRINFOA));
-windows_targets::link!("ws2_32.dll" "system" fn getaddrinfo(pnodename : PCSTR, pservicename : PCSTR, phints : *const ADDRINFOA, ppresult : *mut *mut ADDRINFOA) -> i32);
-windows_targets::link!("ws2_32.dll" "system" fn getpeername(s : SOCKET, name : *mut SOCKADDR, namelen : *mut i32) -> i32);
-windows_targets::link!("ws2_32.dll" "system" fn getsockname(s : SOCKET, name : *mut SOCKADDR, namelen : *mut i32) -> i32);
-windows_targets::link!("ws2_32.dll" "system" fn getsockopt(s : SOCKET, level : i32, optname : i32, optval : PSTR, optlen : *mut i32) -> i32);
-windows_targets::link!("ws2_32.dll" "system" fn ioctlsocket(s : SOCKET, cmd : i32, argp : *mut u32) -> i32);
-windows_targets::link!("ws2_32.dll" "system" fn listen(s : SOCKET, backlog : i32) -> i32);
-windows_targets::link!("kernel32.dll" "system" fn lstrlenW(lpstring : PCWSTR) -> i32);
-windows_targets::link!("ws2_32.dll" "system" fn recv(s : SOCKET, buf : PSTR, len : i32, flags : SEND_RECV_FLAGS) -> i32);
-windows_targets::link!("ws2_32.dll" "system" fn recvfrom(s : SOCKET, buf : PSTR, len : i32, flags : i32, from : *mut SOCKADDR, fromlen : *mut i32) -> i32);
-windows_targets::link!("ws2_32.dll" "system" fn select(nfds : i32, readfds : *mut FD_SET, writefds : *mut FD_SET, exceptfds : *mut FD_SET, timeout : *const TIMEVAL) -> i32);
-windows_targets::link!("ws2_32.dll" "system" fn send(s : SOCKET, buf : PCSTR, len : i32, flags : SEND_RECV_FLAGS) -> i32);
-windows_targets::link!("ws2_32.dll" "system" fn sendto(s : SOCKET, buf : PCSTR, len : i32, flags : i32, to : *const SOCKADDR, tolen : i32) -> i32);
-windows_targets::link!("ws2_32.dll" "system" fn setsockopt(s : SOCKET, level : i32, optname : i32, optval : PCSTR, optlen : i32) -> i32);
-windows_targets::link!("ws2_32.dll" "system" fn shutdown(s : SOCKET, how : WINSOCK_SHUTDOWN_HOW) -> i32);
+windows_link::link!("kernel32.dll" "system" fn AcquireSRWLockExclusive(srwlock : *mut SRWLOCK));
+windows_link::link!("kernel32.dll" "system" fn AcquireSRWLockShared(srwlock : *mut SRWLOCK));
+windows_link::link!("kernel32.dll" "system" fn AddVectoredExceptionHandler(first : u32, handler : PVECTORED_EXCEPTION_HANDLER) -> *mut core::ffi::c_void);
+windows_link::link!("kernel32.dll" "system" fn CancelIo(hfile : HANDLE) -> BOOL);
+windows_link::link!("kernel32.dll" "system" fn CloseHandle(hobject : HANDLE) -> BOOL);
+windows_link::link!("kernel32.dll" "system" fn CompareStringOrdinal(lpstring1 : PCWSTR, cchcount1 : i32, lpstring2 : PCWSTR, cchcount2 : i32, bignorecase : BOOL) -> COMPARESTRING_RESULT);
+windows_link::link!("kernel32.dll" "system" fn CopyFileExW(lpexistingfilename : PCWSTR, lpnewfilename : PCWSTR, lpprogressroutine : LPPROGRESS_ROUTINE, lpdata : *const core::ffi::c_void, pbcancel : *mut BOOL, dwcopyflags : COPYFILE_FLAGS) -> BOOL);
+windows_link::link!("kernel32.dll" "system" fn CreateDirectoryW(lppathname : PCWSTR, lpsecurityattributes : *const SECURITY_ATTRIBUTES) -> BOOL);
+windows_link::link!("kernel32.dll" "system" fn CreateEventW(lpeventattributes : *const SECURITY_ATTRIBUTES, bmanualreset : BOOL, binitialstate : BOOL, lpname : PCWSTR) -> HANDLE);
+windows_link::link!("kernel32.dll" "system" fn CreateFileW(lpfilename : PCWSTR, dwdesiredaccess : u32, dwsharemode : FILE_SHARE_MODE, lpsecurityattributes : *const SECURITY_ATTRIBUTES, dwcreationdisposition : FILE_CREATION_DISPOSITION, dwflagsandattributes : FILE_FLAGS_AND_ATTRIBUTES, htemplatefile : HANDLE) -> HANDLE);
+windows_link::link!("kernel32.dll" "system" fn CreateHardLinkW(lpfilename : PCWSTR, lpexistingfilename : PCWSTR, lpsecurityattributes : *const SECURITY_ATTRIBUTES) -> BOOL);
+windows_link::link!("kernel32.dll" "system" fn CreateNamedPipeW(lpname : PCWSTR, dwopenmode : FILE_FLAGS_AND_ATTRIBUTES, dwpipemode : NAMED_PIPE_MODE, nmaxinstances : u32, noutbuffersize : u32, ninbuffersize : u32, ndefaulttimeout : u32, lpsecurityattributes : *const SECURITY_ATTRIBUTES) -> HANDLE);
+windows_link::link!("kernel32.dll" "system" fn CreatePipe(hreadpipe : *mut HANDLE, hwritepipe : *mut HANDLE, lppipeattributes : *const SECURITY_ATTRIBUTES, nsize : u32) -> BOOL);
+windows_link::link!("kernel32.dll" "system" fn CreateProcessW(lpapplicationname : PCWSTR, lpcommandline : PWSTR, lpprocessattributes : *const SECURITY_ATTRIBUTES, lpthreadattributes : *const SECURITY_ATTRIBUTES, binherithandles : BOOL, dwcreationflags : PROCESS_CREATION_FLAGS, lpenvironment : *const core::ffi::c_void, lpcurrentdirectory : PCWSTR, lpstartupinfo : *const STARTUPINFOW, lpprocessinformation : *mut PROCESS_INFORMATION) -> BOOL);
+windows_link::link!("kernel32.dll" "system" fn CreateSymbolicLinkW(lpsymlinkfilename : PCWSTR, lptargetfilename : PCWSTR, dwflags : SYMBOLIC_LINK_FLAGS) -> bool);
+windows_link::link!("kernel32.dll" "system" fn CreateThread(lpthreadattributes : *const SECURITY_ATTRIBUTES, dwstacksize : usize, lpstartaddress : LPTHREAD_START_ROUTINE, lpparameter : *const core::ffi::c_void, dwcreationflags : THREAD_CREATION_FLAGS, lpthreadid : *mut u32) -> HANDLE);
+windows_link::link!("kernel32.dll" "system" fn CreateWaitableTimerExW(lptimerattributes : *const SECURITY_ATTRIBUTES, lptimername : PCWSTR, dwflags : u32, dwdesiredaccess : u32) -> HANDLE);
+windows_link::link!("kernel32.dll" "system" fn DeleteFileW(lpfilename : PCWSTR) -> BOOL);
+windows_link::link!("kernel32.dll" "system" fn DeleteProcThreadAttributeList(lpattributelist : LPPROC_THREAD_ATTRIBUTE_LIST));
+windows_link::link!("kernel32.dll" "system" fn DeviceIoControl(hdevice : HANDLE, dwiocontrolcode : u32, lpinbuffer : *const core::ffi::c_void, ninbuffersize : u32, lpoutbuffer : *mut core::ffi::c_void, noutbuffersize : u32, lpbytesreturned : *mut u32, lpoverlapped : *mut OVERLAPPED) -> BOOL);
+windows_link::link!("kernel32.dll" "system" fn DuplicateHandle(hsourceprocesshandle : HANDLE, hsourcehandle : HANDLE, htargetprocesshandle : HANDLE, lptargethandle : *mut HANDLE, dwdesiredaccess : u32, binherithandle : BOOL, dwoptions : DUPLICATE_HANDLE_OPTIONS) -> BOOL);
+windows_link::link!("kernel32.dll" "system" fn ExitProcess(uexitcode : u32) -> !);
+windows_link::link!("kernel32.dll" "system" fn FindClose(hfindfile : HANDLE) -> BOOL);
+windows_link::link!("kernel32.dll" "system" fn FindFirstFileExW(lpfilename : PCWSTR, finfolevelid : FINDEX_INFO_LEVELS, lpfindfiledata : *mut core::ffi::c_void, fsearchop : FINDEX_SEARCH_OPS, lpsearchfilter : *const core::ffi::c_void, dwadditionalflags : FIND_FIRST_EX_FLAGS) -> HANDLE);
+windows_link::link!("kernel32.dll" "system" fn FindNextFileW(hfindfile : HANDLE, lpfindfiledata : *mut WIN32_FIND_DATAW) -> BOOL);
+windows_link::link!("kernel32.dll" "system" fn FlushFileBuffers(hfile : HANDLE) -> BOOL);
+windows_link::link!("kernel32.dll" "system" fn FormatMessageW(dwflags : FORMAT_MESSAGE_OPTIONS, lpsource : *const core::ffi::c_void, dwmessageid : u32, dwlanguageid : u32, lpbuffer : PWSTR, nsize : u32, arguments : *const *const i8) -> u32);
+windows_link::link!("kernel32.dll" "system" fn FreeEnvironmentStringsW(penv : PCWSTR) -> BOOL);
+windows_link::link!("kernel32.dll" "system" fn GetActiveProcessorCount(groupnumber : u16) -> u32);
+windows_link::link!("kernel32.dll" "system" fn GetCommandLineW() -> PCWSTR);
+windows_link::link!("kernel32.dll" "system" fn GetConsoleMode(hconsolehandle : HANDLE, lpmode : *mut CONSOLE_MODE) -> BOOL);
+windows_link::link!("kernel32.dll" "system" fn GetConsoleOutputCP() -> u32);
+windows_link::link!("kernel32.dll" "system" fn GetCurrentDirectoryW(nbufferlength : u32, lpbuffer : PWSTR) -> u32);
+windows_link::link!("kernel32.dll" "system" fn GetCurrentProcess() -> HANDLE);
+windows_link::link!("kernel32.dll" "system" fn GetCurrentProcessId() -> u32);
+windows_link::link!("kernel32.dll" "system" fn GetCurrentThread() -> HANDLE);
+windows_link::link!("kernel32.dll" "system" fn GetCurrentThreadId() -> u32);
+windows_link::link!("kernel32.dll" "system" fn GetEnvironmentStringsW() -> PWSTR);
+windows_link::link!("kernel32.dll" "system" fn GetEnvironmentVariableW(lpname : PCWSTR, lpbuffer : PWSTR, nsize : u32) -> u32);
+windows_link::link!("kernel32.dll" "system" fn GetExitCodeProcess(hprocess : HANDLE, lpexitcode : *mut u32) -> BOOL);
+windows_link::link!("kernel32.dll" "system" fn GetFileAttributesW(lpfilename : PCWSTR) -> u32);
+windows_link::link!("kernel32.dll" "system" fn GetFileInformationByHandle(hfile : HANDLE, lpfileinformation : *mut BY_HANDLE_FILE_INFORMATION) -> BOOL);
+windows_link::link!("kernel32.dll" "system" fn GetFileInformationByHandleEx(hfile : HANDLE, fileinformationclass : FILE_INFO_BY_HANDLE_CLASS, lpfileinformation : *mut core::ffi::c_void, dwbuffersize : u32) -> BOOL);
+windows_link::link!("kernel32.dll" "system" fn GetFileSizeEx(hfile : HANDLE, lpfilesize : *mut i64) -> BOOL);
+windows_link::link!("kernel32.dll" "system" fn GetFileType(hfile : HANDLE) -> FILE_TYPE);
+windows_link::link!("kernel32.dll" "system" fn GetFinalPathNameByHandleW(hfile : HANDLE, lpszfilepath : PWSTR, cchfilepath : u32, dwflags : GETFINALPATHNAMEBYHANDLE_FLAGS) -> u32);
+windows_link::link!("kernel32.dll" "system" fn GetFullPathNameW(lpfilename : PCWSTR, nbufferlength : u32, lpbuffer : PWSTR, lpfilepart : *mut PWSTR) -> u32);
+windows_link::link!("kernel32.dll" "system" fn GetLastError() -> WIN32_ERROR);
+windows_link::link!("kernel32.dll" "system" fn GetModuleFileNameW(hmodule : HMODULE, lpfilename : PWSTR, nsize : u32) -> u32);
+windows_link::link!("kernel32.dll" "system" fn GetModuleHandleA(lpmodulename : PCSTR) -> HMODULE);
+windows_link::link!("kernel32.dll" "system" fn GetModuleHandleW(lpmodulename : PCWSTR) -> HMODULE);
+windows_link::link!("kernel32.dll" "system" fn GetOverlappedResult(hfile : HANDLE, lpoverlapped : *const OVERLAPPED, lpnumberofbytestransferred : *mut u32, bwait : BOOL) -> BOOL);
+windows_link::link!("kernel32.dll" "system" fn GetProcAddress(hmodule : HMODULE, lpprocname : PCSTR) -> FARPROC);
+windows_link::link!("kernel32.dll" "system" fn GetProcessId(process : HANDLE) -> u32);
+windows_link::link!("kernel32.dll" "system" fn GetStdHandle(nstdhandle : STD_HANDLE) -> HANDLE);
+windows_link::link!("kernel32.dll" "system" fn GetSystemDirectoryW(lpbuffer : PWSTR, usize : u32) -> u32);
+windows_link::link!("kernel32.dll" "system" fn GetSystemInfo(lpsysteminfo : *mut SYSTEM_INFO));
+windows_link::link!("kernel32.dll" "system" fn GetSystemTimeAsFileTime(lpsystemtimeasfiletime : *mut FILETIME));
+windows_link::link!("kernel32.dll" "system" fn GetSystemTimePreciseAsFileTime(lpsystemtimeasfiletime : *mut FILETIME));
+windows_link::link!("kernel32.dll" "system" fn GetTempPathW(nbufferlength : u32, lpbuffer : PWSTR) -> u32);
+windows_link::link!("userenv.dll" "system" fn GetUserProfileDirectoryW(htoken : HANDLE, lpprofiledir : PWSTR, lpcchsize : *mut u32) -> BOOL);
+windows_link::link!("kernel32.dll" "system" fn GetWindowsDirectoryW(lpbuffer : PWSTR, usize : u32) -> u32);
+windows_link::link!("kernel32.dll" "system" fn InitOnceBeginInitialize(lpinitonce : *mut INIT_ONCE, dwflags : u32, fpending : *mut BOOL, lpcontext : *mut *mut core::ffi::c_void) -> BOOL);
+windows_link::link!("kernel32.dll" "system" fn InitOnceComplete(lpinitonce : *mut INIT_ONCE, dwflags : u32, lpcontext : *const core::ffi::c_void) -> BOOL);
+windows_link::link!("kernel32.dll" "system" fn InitializeProcThreadAttributeList(lpattributelist : LPPROC_THREAD_ATTRIBUTE_LIST, dwattributecount : u32, dwflags : u32, lpsize : *mut usize) -> BOOL);
+windows_link::link!("kernel32.dll" "system" fn LocalFree(hmem : HLOCAL) -> HLOCAL);
+windows_link::link!("kernel32.dll" "system" fn LockFileEx(hfile : HANDLE, dwflags : LOCK_FILE_FLAGS, dwreserved : u32, nnumberofbytestolocklow : u32, nnumberofbytestolockhigh : u32, lpoverlapped : *mut OVERLAPPED) -> BOOL);
+windows_link::link!("kernel32.dll" "system" fn MoveFileExW(lpexistingfilename : PCWSTR, lpnewfilename : PCWSTR, dwflags : MOVE_FILE_FLAGS) -> BOOL);
+windows_link::link!("kernel32.dll" "system" fn MultiByteToWideChar(codepage : u32, dwflags : MULTI_BYTE_TO_WIDE_CHAR_FLAGS, lpmultibytestr : PCSTR, cbmultibyte : i32, lpwidecharstr : PWSTR, cchwidechar : i32) -> i32);
+windows_link::link!("ntdll.dll" "system" fn NtCreateFile(filehandle : *mut HANDLE, desiredaccess : FILE_ACCESS_RIGHTS, objectattributes : *const OBJECT_ATTRIBUTES, iostatusblock : *mut IO_STATUS_BLOCK, allocationsize : *const i64, fileattributes : FILE_FLAGS_AND_ATTRIBUTES, shareaccess : FILE_SHARE_MODE, createdisposition : NTCREATEFILE_CREATE_DISPOSITION, createoptions : NTCREATEFILE_CREATE_OPTIONS, eabuffer : *const core::ffi::c_void, ealength : u32) -> NTSTATUS);
+windows_link::link!("ntdll.dll" "system" fn NtOpenFile(filehandle : *mut HANDLE, desiredaccess : u32, objectattributes : *const OBJECT_ATTRIBUTES, iostatusblock : *mut IO_STATUS_BLOCK, shareaccess : u32, openoptions : u32) -> NTSTATUS);
+windows_link::link!("ntdll.dll" "system" fn NtReadFile(filehandle : HANDLE, event : HANDLE, apcroutine : PIO_APC_ROUTINE, apccontext : *const core::ffi::c_void, iostatusblock : *mut IO_STATUS_BLOCK, buffer : *mut core::ffi::c_void, length : u32, byteoffset : *const i64, key : *const u32) -> NTSTATUS);
+windows_link::link!("ntdll.dll" "system" fn NtWriteFile(filehandle : HANDLE, event : HANDLE, apcroutine : PIO_APC_ROUTINE, apccontext : *const core::ffi::c_void, iostatusblock : *mut IO_STATUS_BLOCK, buffer : *const core::ffi::c_void, length : u32, byteoffset : *const i64, key : *const u32) -> NTSTATUS);
+windows_link::link!("advapi32.dll" "system" fn OpenProcessToken(processhandle : HANDLE, desiredaccess : TOKEN_ACCESS_MASK, tokenhandle : *mut HANDLE) -> BOOL);
+windows_link::link!("kernel32.dll" "system" fn QueryPerformanceCounter(lpperformancecount : *mut i64) -> BOOL);
+windows_link::link!("kernel32.dll" "system" fn QueryPerformanceFrequency(lpfrequency : *mut i64) -> BOOL);
+windows_link::link!("kernel32.dll" "system" fn ReadConsoleW(hconsoleinput : HANDLE, lpbuffer : *mut core::ffi::c_void, nnumberofcharstoread : u32, lpnumberofcharsread : *mut u32, pinputcontrol : *const CONSOLE_READCONSOLE_CONTROL) -> BOOL);
+windows_link::link!("kernel32.dll" "system" fn ReadFile(hfile : HANDLE, lpbuffer : *mut u8, nnumberofbytestoread : u32, lpnumberofbytesread : *mut u32, lpoverlapped : *mut OVERLAPPED) -> BOOL);
+windows_link::link!("kernel32.dll" "system" fn ReadFileEx(hfile : HANDLE, lpbuffer : *mut u8, nnumberofbytestoread : u32, lpoverlapped : *mut OVERLAPPED, lpcompletionroutine : LPOVERLAPPED_COMPLETION_ROUTINE) -> BOOL);
+windows_link::link!("kernel32.dll" "system" fn ReleaseSRWLockExclusive(srwlock : *mut SRWLOCK));
+windows_link::link!("kernel32.dll" "system" fn ReleaseSRWLockShared(srwlock : *mut SRWLOCK));
+windows_link::link!("kernel32.dll" "system" fn RemoveDirectoryW(lppathname : PCWSTR) -> BOOL);
+windows_link::link!("advapi32.dll" "system" "SystemFunction036" fn RtlGenRandom(randombuffer : *mut core::ffi::c_void, randombufferlength : u32) -> bool);
+windows_link::link!("ntdll.dll" "system" fn RtlNtStatusToDosError(status : NTSTATUS) -> u32);
+windows_link::link!("kernel32.dll" "system" fn SetCurrentDirectoryW(lppathname : PCWSTR) -> BOOL);
+windows_link::link!("kernel32.dll" "system" fn SetEnvironmentVariableW(lpname : PCWSTR, lpvalue : PCWSTR) -> BOOL);
+windows_link::link!("kernel32.dll" "system" fn SetFileAttributesW(lpfilename : PCWSTR, dwfileattributes : FILE_FLAGS_AND_ATTRIBUTES) -> BOOL);
+windows_link::link!("kernel32.dll" "system" fn SetFileInformationByHandle(hfile : HANDLE, fileinformationclass : FILE_INFO_BY_HANDLE_CLASS, lpfileinformation : *const core::ffi::c_void, dwbuffersize : u32) -> BOOL);
+windows_link::link!("kernel32.dll" "system" fn SetFilePointerEx(hfile : HANDLE, lidistancetomove : i64, lpnewfilepointer : *mut i64, dwmovemethod : SET_FILE_POINTER_MOVE_METHOD) -> BOOL);
+windows_link::link!("kernel32.dll" "system" fn SetFileTime(hfile : HANDLE, lpcreationtime : *const FILETIME, lplastaccesstime : *const FILETIME, lplastwritetime : *const FILETIME) -> BOOL);
+windows_link::link!("kernel32.dll" "system" fn SetHandleInformation(hobject : HANDLE, dwmask : u32, dwflags : HANDLE_FLAGS) -> BOOL);
+windows_link::link!("kernel32.dll" "system" fn SetLastError(dwerrcode : WIN32_ERROR));
+windows_link::link!("kernel32.dll" "system" fn SetThreadStackGuarantee(stacksizeinbytes : *mut u32) -> BOOL);
+windows_link::link!("kernel32.dll" "system" fn SetWaitableTimer(htimer : HANDLE, lpduetime : *const i64, lperiod : i32, pfncompletionroutine : PTIMERAPCROUTINE, lpargtocompletionroutine : *const core::ffi::c_void, fresume : BOOL) -> BOOL);
+windows_link::link!("kernel32.dll" "system" fn Sleep(dwmilliseconds : u32));
+windows_link::link!("kernel32.dll" "system" fn SleepConditionVariableSRW(conditionvariable : *mut CONDITION_VARIABLE, srwlock : *mut SRWLOCK, dwmilliseconds : u32, flags : u32) -> BOOL);
+windows_link::link!("kernel32.dll" "system" fn SleepEx(dwmilliseconds : u32, balertable : BOOL) -> u32);
+windows_link::link!("kernel32.dll" "system" fn SwitchToThread() -> BOOL);
+windows_link::link!("kernel32.dll" "system" fn TerminateProcess(hprocess : HANDLE, uexitcode : u32) -> BOOL);
+windows_link::link!("kernel32.dll" "system" fn TlsAlloc() -> u32);
+windows_link::link!("kernel32.dll" "system" fn TlsFree(dwtlsindex : u32) -> BOOL);
+windows_link::link!("kernel32.dll" "system" fn TlsGetValue(dwtlsindex : u32) -> *mut core::ffi::c_void);
+windows_link::link!("kernel32.dll" "system" fn TlsSetValue(dwtlsindex : u32, lptlsvalue : *const core::ffi::c_void) -> BOOL);
+windows_link::link!("kernel32.dll" "system" fn TryAcquireSRWLockExclusive(srwlock : *mut SRWLOCK) -> bool);
+windows_link::link!("kernel32.dll" "system" fn TryAcquireSRWLockShared(srwlock : *mut SRWLOCK) -> bool);
+windows_link::link!("kernel32.dll" "system" fn UnlockFile(hfile : HANDLE, dwfileoffsetlow : u32, dwfileoffsethigh : u32, nnumberofbytestounlocklow : u32, nnumberofbytestounlockhigh : u32) -> BOOL);
+windows_link::link!("kernel32.dll" "system" fn UpdateProcThreadAttribute(lpattributelist : LPPROC_THREAD_ATTRIBUTE_LIST, dwflags : u32, attribute : usize, lpvalue : *const core::ffi::c_void, cbsize : usize, lppreviousvalue : *mut core::ffi::c_void, lpreturnsize : *const usize) -> BOOL);
+windows_link::link!("ws2_32.dll" "system" fn WSACleanup() -> i32);
+windows_link::link!("ws2_32.dll" "system" fn WSADuplicateSocketW(s : SOCKET, dwprocessid : u32, lpprotocolinfo : *mut WSAPROTOCOL_INFOW) -> i32);
+windows_link::link!("ws2_32.dll" "system" fn WSAGetLastError() -> WSA_ERROR);
+windows_link::link!("ws2_32.dll" "system" fn WSARecv(s : SOCKET, lpbuffers : *const WSABUF, dwbuffercount : u32, lpnumberofbytesrecvd : *mut u32, lpflags : *mut u32, lpoverlapped : *mut OVERLAPPED, lpcompletionroutine : LPWSAOVERLAPPED_COMPLETION_ROUTINE) -> i32);
+windows_link::link!("ws2_32.dll" "system" fn WSASend(s : SOCKET, lpbuffers : *const WSABUF, dwbuffercount : u32, lpnumberofbytessent : *mut u32, dwflags : u32, lpoverlapped : *mut OVERLAPPED, lpcompletionroutine : LPWSAOVERLAPPED_COMPLETION_ROUTINE) -> i32);
+windows_link::link!("ws2_32.dll" "system" fn WSASocketW(af : i32, r#type : i32, protocol : i32, lpprotocolinfo : *const WSAPROTOCOL_INFOW, g : u32, dwflags : u32) -> SOCKET);
+windows_link::link!("ws2_32.dll" "system" fn WSAStartup(wversionrequested : u16, lpwsadata : *mut WSADATA) -> i32);
+windows_link::link!("kernel32.dll" "system" fn WaitForMultipleObjects(ncount : u32, lphandles : *const HANDLE, bwaitall : BOOL, dwmilliseconds : u32) -> WAIT_EVENT);
+windows_link::link!("kernel32.dll" "system" fn WaitForSingleObject(hhandle : HANDLE, dwmilliseconds : u32) -> WAIT_EVENT);
+windows_link::link!("kernel32.dll" "system" fn WakeAllConditionVariable(conditionvariable : *mut CONDITION_VARIABLE));
+windows_link::link!("kernel32.dll" "system" fn WakeConditionVariable(conditionvariable : *mut CONDITION_VARIABLE));
+windows_link::link!("kernel32.dll" "system" fn WideCharToMultiByte(codepage : u32, dwflags : u32, lpwidecharstr : PCWSTR, cchwidechar : i32, lpmultibytestr : PSTR, cbmultibyte : i32, lpdefaultchar : PCSTR, lpuseddefaultchar : *mut BOOL) -> i32);
+windows_link::link!("kernel32.dll" "system" fn WriteConsoleW(hconsoleoutput : HANDLE, lpbuffer : PCWSTR, nnumberofcharstowrite : u32, lpnumberofcharswritten : *mut u32, lpreserved : *const core::ffi::c_void) -> BOOL);
+windows_link::link!("kernel32.dll" "system" fn WriteFileEx(hfile : HANDLE, lpbuffer : *const u8, nnumberofbytestowrite : u32, lpoverlapped : *mut OVERLAPPED, lpcompletionroutine : LPOVERLAPPED_COMPLETION_ROUTINE) -> BOOL);
+windows_link::link!("ws2_32.dll" "system" fn accept(s : SOCKET, addr : *mut SOCKADDR, addrlen : *mut i32) -> SOCKET);
+windows_link::link!("ws2_32.dll" "system" fn bind(s : SOCKET, name : *const SOCKADDR, namelen : i32) -> i32);
+windows_link::link!("ws2_32.dll" "system" fn closesocket(s : SOCKET) -> i32);
+windows_link::link!("ws2_32.dll" "system" fn connect(s : SOCKET, name : *const SOCKADDR, namelen : i32) -> i32);
+windows_link::link!("ws2_32.dll" "system" fn freeaddrinfo(paddrinfo : *const ADDRINFOA));
+windows_link::link!("ws2_32.dll" "system" fn getaddrinfo(pnodename : PCSTR, pservicename : PCSTR, phints : *const ADDRINFOA, ppresult : *mut *mut ADDRINFOA) -> i32);
+windows_link::link!("ws2_32.dll" "system" fn getpeername(s : SOCKET, name : *mut SOCKADDR, namelen : *mut i32) -> i32);
+windows_link::link!("ws2_32.dll" "system" fn getsockname(s : SOCKET, name : *mut SOCKADDR, namelen : *mut i32) -> i32);
+windows_link::link!("ws2_32.dll" "system" fn getsockopt(s : SOCKET, level : i32, optname : i32, optval : PSTR, optlen : *mut i32) -> i32);
+windows_link::link!("ws2_32.dll" "system" fn ioctlsocket(s : SOCKET, cmd : i32, argp : *mut u32) -> i32);
+windows_link::link!("ws2_32.dll" "system" fn listen(s : SOCKET, backlog : i32) -> i32);
+windows_link::link!("kernel32.dll" "system" fn lstrlenW(lpstring : PCWSTR) -> i32);
+windows_link::link!("ws2_32.dll" "system" fn recv(s : SOCKET, buf : PSTR, len : i32, flags : SEND_RECV_FLAGS) -> i32);
+windows_link::link!("ws2_32.dll" "system" fn recvfrom(s : SOCKET, buf : PSTR, len : i32, flags : i32, from : *mut SOCKADDR, fromlen : *mut i32) -> i32);
+windows_link::link!("ws2_32.dll" "system" fn select(nfds : i32, readfds : *mut FD_SET, writefds : *mut FD_SET, exceptfds : *mut FD_SET, timeout : *const TIMEVAL) -> i32);
+windows_link::link!("ws2_32.dll" "system" fn send(s : SOCKET, buf : PCSTR, len : i32, flags : SEND_RECV_FLAGS) -> i32);
+windows_link::link!("ws2_32.dll" "system" fn sendto(s : SOCKET, buf : PCSTR, len : i32, flags : i32, to : *const SOCKADDR, tolen : i32) -> i32);
+windows_link::link!("ws2_32.dll" "system" fn setsockopt(s : SOCKET, level : i32, optname : i32, optval : PCSTR, optlen : i32) -> i32);
+windows_link::link!("ws2_32.dll" "system" fn shutdown(s : SOCKET, how : WINSOCK_SHUTDOWN_HOW) -> i32);
 pub const ABOVE_NORMAL_PRIORITY_CLASS: PROCESS_CREATION_FLAGS = 32768u32;
 #[repr(C)]
 #[derive(Clone, Copy, Default)]
diff --git a/library/windows_targets/Cargo.toml b/library/windows_link/Cargo.toml
similarity index 63%
rename from library/windows_targets/Cargo.toml
rename to library/windows_link/Cargo.toml
index 1c804a0ab391..fc5d0a69bfb5 100644
--- a/library/windows_targets/Cargo.toml
+++ b/library/windows_link/Cargo.toml
@@ -1,6 +1,6 @@
 [package]
-name = "windows-targets"
-description = "A drop-in replacement for the real windows-targets crate for use in std only."
+name = "windows-link"
+description = "A drop-in replacement for the real windows-link crate for use in std only."
 version = "0.0.0"
 edition = "2024"
 
diff --git a/library/windows_targets/src/lib.rs b/library/windows_link/src/lib.rs
similarity index 100%
rename from library/windows_targets/src/lib.rs
rename to library/windows_link/src/lib.rs
diff --git a/src/tools/generate-windows-sys/Cargo.toml b/src/tools/generate-windows-sys/Cargo.toml
index 152cd504abd1..5627a8555943 100644
--- a/src/tools/generate-windows-sys/Cargo.toml
+++ b/src/tools/generate-windows-sys/Cargo.toml
@@ -4,4 +4,4 @@ version = "0.1.0"
 edition = "2021"
 
 [dependencies.windows-bindgen]
-version = "0.61.0"
+version = "0.66.0"
diff --git a/src/tools/generate-windows-sys/src/main.rs b/src/tools/generate-windows-sys/src/main.rs
index 6bf47e840627..9b1d62f14bb7 100644
--- a/src/tools/generate-windows-sys/src/main.rs
+++ b/src/tools/generate-windows-sys/src/main.rs
@@ -29,7 +29,7 @@ fn main() -> Result<(), Box<dyn Error>> {
 
     sort_bindings("bindings.txt")?;
 
-    windows_bindgen::bindgen(["--etc", "bindings.txt"]);
+    windows_bindgen::bindgen(["--etc", "bindings.txt"]).unwrap();
 
     let mut f = std::fs::File::options().append(true).open("windows_sys.rs")?;
     f.write_all(ARM32_SHIM.as_bytes())?;
diff --git a/src/tools/tidy/src/pal.rs b/src/tools/tidy/src/pal.rs
index e6423aeeba99..f1ac90ba0bc5 100644
--- a/src/tools/tidy/src/pal.rs
+++ b/src/tools/tidy/src/pal.rs
@@ -38,7 +38,7 @@ use crate::walk::{filter_dirs, walk};
 const EXCEPTION_PATHS: &[&str] = &[
     "library/compiler-builtins",
     "library/std_detect",
-    "library/windows_targets",
+    "library/windows_link",
     "library/panic_abort",
     "library/panic_unwind",
     "library/unwind",

From 0df94dd94eeb0893d60aee40c9fcdf4d2b43a569 Mon Sep 17 00:00:00 2001
From: Piotr Osiewicz <24362066+osiewicz@users.noreply.github.com>
Date: Wed, 14 Jan 2026 21:20:24 +0100
Subject: [PATCH 32/97] checksum-freshness: Fix incorrect hash/file length
 values of binary dependency files

---
 .../rustc_builtin_macros/src/source_util.rs   | 10 ++++++-
 compiler/rustc_interface/src/passes.rs        | 29 +++++++++----------
 2 files changed, 23 insertions(+), 16 deletions(-)

diff --git a/compiler/rustc_builtin_macros/src/source_util.rs b/compiler/rustc_builtin_macros/src/source_util.rs
index 0f31de60a8a4..50db19a16d8b 100644
--- a/compiler/rustc_builtin_macros/src/source_util.rs
+++ b/compiler/rustc_builtin_macros/src/source_util.rs
@@ -275,7 +275,15 @@ fn load_binary_file(
         }
     };
     match cx.source_map().load_binary_file(&resolved_path) {
-        Ok(data) => Ok(data),
+        Ok(data) => {
+            cx.sess
+                .psess
+                .file_depinfo
+                .borrow_mut()
+                .insert(Symbol::intern(&resolved_path.to_string_lossy()));
+
+            Ok(data)
+        }
         Err(io_err) => {
             let mut err = cx.dcx().struct_span_err(
                 macro_span,
diff --git a/compiler/rustc_interface/src/passes.rs b/compiler/rustc_interface/src/passes.rs
index a0383b187de5..e1d9e2460443 100644
--- a/compiler/rustc_interface/src/passes.rs
+++ b/compiler/rustc_interface/src/passes.rs
@@ -9,6 +9,7 @@ use rustc_ast as ast;
 use rustc_attr_parsing::{AttributeParser, ShouldEmit};
 use rustc_codegen_ssa::traits::CodegenBackend;
 use rustc_codegen_ssa::{CodegenResults, CrateInfo};
+use rustc_data_structures::indexmap::IndexMap;
 use rustc_data_structures::jobserver::Proxy;
 use rustc_data_structures::steal::Steal;
 use rustc_data_structures::sync::{AppendOnlyIndexVec, FreezeLock, WorkerLocal};
@@ -586,7 +587,7 @@ fn write_out_deps(tcx: TyCtxt<'_>, outputs: &OutputFilenames, out_filenames: &[P
     let result: io::Result<()> = try {
         // Build a list of files used to compile the output and
         // write Makefile-compatible dependency rules
-        let mut files: Vec<(String, u64, Option<SourceFileHash>)> = sess
+        let mut files: IndexMap<String, (u64, Option<SourceFileHash>)> = sess
             .source_map()
             .files()
             .iter()
@@ -595,10 +596,12 @@ fn write_out_deps(tcx: TyCtxt<'_>, outputs: &OutputFilenames, out_filenames: &[P
             .map(|fmap| {
                 (
                     escape_dep_filename(&fmap.name.prefer_local_unconditionally().to_string()),
-                    // This needs to be unnormalized,
-                    // as external tools wouldn't know how rustc normalizes them
-                    fmap.unnormalized_source_len as u64,
-                    fmap.checksum_hash,
+                    (
+                        // This needs to be unnormalized,
+                        // as external tools wouldn't know how rustc normalizes them
+                        fmap.unnormalized_source_len as u64,
+                        fmap.checksum_hash,
+                    ),
                 )
             })
             .collect();
@@ -616,7 +619,7 @@ fn write_out_deps(tcx: TyCtxt<'_>, outputs: &OutputFilenames, out_filenames: &[P
         fn hash_iter_files<P: AsRef<Path>>(
             it: impl Iterator<Item = P>,
             checksum_hash_algo: Option<SourceFileHashAlgorithm>,
-        ) -> impl Iterator<Item = (P, u64, Option<SourceFileHash>)> {
+        ) -> impl Iterator<Item = (P, (u64, Option<SourceFileHash>))> {
             it.map(move |path| {
                 match checksum_hash_algo.and_then(|algo| {
                     fs::File::open(path.as_ref())
@@ -632,8 +635,8 @@ fn write_out_deps(tcx: TyCtxt<'_>, outputs: &OutputFilenames, out_filenames: &[P
                         })
                         .ok()
                 }) {
-                    Some((file_len, checksum)) => (path, file_len, Some(checksum)),
-                    None => (path, 0, None),
+                    Some((file_len, checksum)) => (path, (file_len, Some(checksum))),
+                    None => (path, (0, None)),
                 }
             })
         }
@@ -707,18 +710,14 @@ fn write_out_deps(tcx: TyCtxt<'_>, outputs: &OutputFilenames, out_filenames: &[P
                     file,
                     "{}: {}\n",
                     path.display(),
-                    files
-                        .iter()
-                        .map(|(path, _file_len, _checksum_hash_algo)| path.as_str())
-                        .intersperse(" ")
-                        .collect::<String>()
+                    files.keys().map(String::as_str).intersperse(" ").collect::<String>()
                 )?;
             }
 
             // Emit a fake target for each input file to the compilation. This
             // prevents `make` from spitting out an error if a file is later
             // deleted. For more info see #28735
-            for (path, _file_len, _checksum_hash_algo) in &files {
+            for path in files.keys() {
                 writeln!(file, "{path}:")?;
             }
 
@@ -747,7 +746,7 @@ fn write_out_deps(tcx: TyCtxt<'_>, outputs: &OutputFilenames, out_filenames: &[P
             if sess.opts.unstable_opts.checksum_hash_algorithm().is_some() {
                 files
                     .iter()
-                    .filter_map(|(path, file_len, hash_algo)| {
+                    .filter_map(|(path, (file_len, hash_algo))| {
                         hash_algo.map(|hash_algo| (path, file_len, hash_algo))
                     })
                     .try_for_each(|(path, file_len, checksum_hash)| {

From 6ecb3f33f0ed410753b33e04b80bd6c504477294 Mon Sep 17 00:00:00 2001
From: Jonathan Pallant <jonathan.pallant@ferrous-systems.com>
Date: Fri, 9 Jan 2026 08:24:13 +0000
Subject: [PATCH 33/97] Adds two new Tier 3 targets - `aarch64v8r-unknown-none`
 and `aarch64v8r-unknown-none-softfloat`.

The existing `aarch64-unknown-none` target assumes Armv8.0-A as a baseline. However, Arm recently released the Arm Cortex-R82 processor which is the first to implement the Armv8-R AArch64 mode architecture. This architecture is similar to Armv8-A AArch64, however it has a different set of mandatory features, and is based off of Armv8.4. It is largely unrelated to the existing Armv8-R architecture target (`armv8r-none-eabihf`), which only operates in AArch32 mode.

The second `aarch64v8r-unknown-none-softfloat` target allows for possible Armv8-R AArch64 CPUs with no FPU, or for use-cases where FPU register stacking is not desired. As with the existing `aarch64-unknown-none` target we have coupled FPU support and Neon support together - there is no 'has FPU but does not have NEON' target proposed even though the architecture technically allows for it.

This PR was developed by Ferrous Systems on behalf of Arm. Arm is the owner of these changes.
---
 compiler/rustc_target/src/spec/mod.rs         |   2 +
 .../spec/targets/aarch64v8r_unknown_none.rs   |  37 +++++
 .../aarch64v8r_unknown_none_softfloat.rs      |  36 +++++
 src/bootstrap/src/core/sanity.rs              |   2 +
 src/doc/rustc/src/SUMMARY.md                  |   1 +
 src/doc/rustc/src/platform-support.md         |   2 +
 .../aarch64v8r-unknown-none.md                |  84 +++++++++++
 .../platform-support/armv8r-none-eabihf.md    |   3 +
 src/tools/tidy/src/target_specific_tests.rs   |   2 +-
 tests/assembly-llvm/targets/targets-elf.rs    |   6 +
 tests/codegen-llvm/aarch64v8r-softfloat.rs    |  45 ++++++
 .../sanitizer/kasan-emits-instrumentation.rs  |   4 +-
 .../kcfi/add-cfi-normalize-integers-flag.rs   |   4 +-
 .../sanitizer/kcfi/add-kcfi-flag.rs           |   4 +-
 .../sanitizer/kcfi/add-kcfi-offset-flag.rs    |   4 +-
 ...t-kcfi-operand-bundle-attr-sanitize-off.rs |   4 +-
 ...rand-bundle-itanium-cxx-abi-generalized.rs |   4 +-
 ...-itanium-cxx-abi-normalized-generalized.rs |   4 +-
 ...erand-bundle-itanium-cxx-abi-normalized.rs |   4 +-
 ...mit-kcfi-operand-bundle-itanium-cxx-abi.rs |   4 +-
 .../kcfi/emit-kcfi-operand-bundle.rs          |   4 +-
 .../kcfi/emit-type-metadata-trait-objects.rs  |   4 +-
 .../sanitizer/kcfi/fn-ptr-reify-shim.rs       |   4 +-
 .../sanitizer/kcfi/naked-function.rs          |   4 +-
 .../sanitizer/sanitize-off-asan-kasan.rs      |   4 +-
 tests/ui/asm/aarch64v8r.rs                    | 140 ++++++++++++++++++
 26 files changed, 401 insertions(+), 15 deletions(-)
 create mode 100644 compiler/rustc_target/src/spec/targets/aarch64v8r_unknown_none.rs
 create mode 100644 compiler/rustc_target/src/spec/targets/aarch64v8r_unknown_none_softfloat.rs
 create mode 100644 src/doc/rustc/src/platform-support/aarch64v8r-unknown-none.md
 create mode 100644 tests/codegen-llvm/aarch64v8r-softfloat.rs
 create mode 100644 tests/ui/asm/aarch64v8r.rs

diff --git a/compiler/rustc_target/src/spec/mod.rs b/compiler/rustc_target/src/spec/mod.rs
index fe4b91c53f63..14e83cf3d2de 100644
--- a/compiler/rustc_target/src/spec/mod.rs
+++ b/compiler/rustc_target/src/spec/mod.rs
@@ -1709,6 +1709,8 @@ supported_targets! {
     ("aarch64-unknown-none-softfloat", aarch64_unknown_none_softfloat),
     ("aarch64_be-unknown-none-softfloat", aarch64_be_unknown_none_softfloat),
     ("aarch64-unknown-nuttx", aarch64_unknown_nuttx),
+    ("aarch64v8r-unknown-none", aarch64v8r_unknown_none),
+    ("aarch64v8r-unknown-none-softfloat", aarch64v8r_unknown_none_softfloat),
 
     ("x86_64-fortanix-unknown-sgx", x86_64_fortanix_unknown_sgx),
 
diff --git a/compiler/rustc_target/src/spec/targets/aarch64v8r_unknown_none.rs b/compiler/rustc_target/src/spec/targets/aarch64v8r_unknown_none.rs
new file mode 100644
index 000000000000..8f8bbb4a41ca
--- /dev/null
+++ b/compiler/rustc_target/src/spec/targets/aarch64v8r_unknown_none.rs
@@ -0,0 +1,37 @@
+use crate::spec::{
+    Arch, Cc, LinkerFlavor, Lld, PanicStrategy, RelocModel, SanitizerSet, StackProbeType, Target,
+    TargetMetadata, TargetOptions,
+};
+
+pub(crate) fn target() -> Target {
+    let opts = TargetOptions {
+        // based off the aarch64-unknown-none target at time of addition
+        linker_flavor: LinkerFlavor::Gnu(Cc::No, Lld::Yes),
+        linker: Some("rust-lld".into()),
+        supported_sanitizers: SanitizerSet::KCFI | SanitizerSet::KERNELADDRESS,
+        relocation_model: RelocModel::Static,
+        disable_redzone: true,
+        max_atomic_width: Some(128),
+        stack_probes: StackProbeType::Inline,
+        panic_strategy: PanicStrategy::Abort,
+        default_uwtable: true,
+
+        // deviations from aarch64-unknown-none: `+v8a` -> `+v8r`; `+v8r` implies `+neon`
+        features: "+v8r,+strict-align".into(),
+        ..Default::default()
+    };
+    Target {
+        llvm_target: "aarch64-unknown-none".into(),
+        metadata: TargetMetadata {
+            description: Some("Bare Armv8-R AArch64, hardfloat".into()),
+            tier: Some(3),
+            host_tools: Some(false),
+            std: Some(false),
+        },
+        pointer_width: 64,
+        // $ clang-21 -S -emit-llvm -target aarch64 -mcpu=cortex-r82 stub.c
+        data_layout: "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32".into(),
+        arch: Arch::AArch64,
+        options: opts,
+    }
+}
diff --git a/compiler/rustc_target/src/spec/targets/aarch64v8r_unknown_none_softfloat.rs b/compiler/rustc_target/src/spec/targets/aarch64v8r_unknown_none_softfloat.rs
new file mode 100644
index 000000000000..63f518873c60
--- /dev/null
+++ b/compiler/rustc_target/src/spec/targets/aarch64v8r_unknown_none_softfloat.rs
@@ -0,0 +1,36 @@
+use crate::spec::{
+    Abi, Arch, Cc, LinkerFlavor, Lld, PanicStrategy, RelocModel, SanitizerSet, StackProbeType,
+    Target, TargetMetadata, TargetOptions,
+};
+
+pub(crate) fn target() -> Target {
+    let opts = TargetOptions {
+        abi: Abi::SoftFloat,
+        linker_flavor: LinkerFlavor::Gnu(Cc::No, Lld::Yes),
+        linker: Some("rust-lld".into()),
+        relocation_model: RelocModel::Static,
+        disable_redzone: true,
+        max_atomic_width: Some(128),
+        supported_sanitizers: SanitizerSet::KCFI | SanitizerSet::KERNELADDRESS,
+        stack_probes: StackProbeType::Inline,
+        panic_strategy: PanicStrategy::Abort,
+        default_uwtable: true,
+
+        // deviations from aarch64-unknown-none: `+v8a` -> `+v8r`
+        features: "+v8r,+strict-align,-neon".into(),
+        ..Default::default()
+    };
+    Target {
+        llvm_target: "aarch64-unknown-none".into(),
+        metadata: TargetMetadata {
+            description: Some("Bare Armv8-R AArch64, softfloat".into()),
+            tier: Some(3),
+            host_tools: Some(false),
+            std: Some(false),
+        },
+        pointer_width: 64,
+        data_layout: "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32".into(),
+        arch: Arch::AArch64,
+        options: opts,
+    }
+}
diff --git a/src/bootstrap/src/core/sanity.rs b/src/bootstrap/src/core/sanity.rs
index a16a2b17be17..8b6405afa892 100644
--- a/src/bootstrap/src/core/sanity.rs
+++ b/src/bootstrap/src/core/sanity.rs
@@ -46,6 +46,8 @@ const STAGE0_MISSING_TARGETS: &[&str] = &[
     "armv6-none-eabi",
     "armv6-none-eabihf",
     "thumbv6-none-eabi",
+    "aarch64v8r-unknown-none",
+    "aarch64v8r-unknown-none-softfloat",
 ];
 
 /// Minimum version threshold for libstdc++ required when using prebuilt LLVM
diff --git a/src/doc/rustc/src/SUMMARY.md b/src/doc/rustc/src/SUMMARY.md
index 632b9e2fc431..2ec0c3648bdf 100644
--- a/src/doc/rustc/src/SUMMARY.md
+++ b/src/doc/rustc/src/SUMMARY.md
@@ -50,6 +50,7 @@
     - [aarch64-unknown-linux-gnu](platform-support/aarch64-unknown-linux-gnu.md)
     - [aarch64-unknown-linux-musl](platform-support/aarch64-unknown-linux-musl.md)
     - [aarch64-unknown-none*](platform-support/aarch64-unknown-none.md)
+    - [aarch64v8r-unknown-none*](platform-support/aarch64v8r-unknown-none.md)
     - [aarch64_be-unknown-none-softfloat](platform-support/aarch64_be-unknown-none-softfloat.md)
     - [aarch64_be-unknown-linux-musl](platform-support/aarch64_be-unknown-linux-musl.md)
     - [amdgcn-amd-amdhsa](platform-support/amdgcn-amd-amdhsa.md)
diff --git a/src/doc/rustc/src/platform-support.md b/src/doc/rustc/src/platform-support.md
index dff8953347ff..114f66282afd 100644
--- a/src/doc/rustc/src/platform-support.md
+++ b/src/doc/rustc/src/platform-support.md
@@ -275,6 +275,8 @@ target | std | host | notes
 [`aarch64-unknown-trusty`](platform-support/trusty.md) | ✓ |  |
 [`aarch64-uwp-windows-msvc`](platform-support/uwp-windows-msvc.md) | ✓ |  |
 [`aarch64-wrs-vxworks`](platform-support/vxworks.md) | ✓ |  | ARM64 VxWorks OS
+[`aarch64v8r-unknown-none`](platform-support/aarch64v8r-unknown-none.md) | * | | Bare Armv8-R in AArch64 mode, hardfloat
+[`aarch64v8r-unknown-none-softfloat`](platform-support/aarch64v8r-unknown-none.md) | * | | Bare Armv8-R in AArch64 mode, softfloat
 [`aarch64_be-unknown-hermit`](platform-support/hermit.md) | ✓ |  | ARM64 Hermit (big-endian)
 `aarch64_be-unknown-linux-gnu` | ✓ | ✓ | ARM64 Linux (big-endian)
 `aarch64_be-unknown-linux-gnu_ilp32` | ✓ | ✓ | ARM64 Linux (big-endian, ILP32 ABI)
diff --git a/src/doc/rustc/src/platform-support/aarch64v8r-unknown-none.md b/src/doc/rustc/src/platform-support/aarch64v8r-unknown-none.md
new file mode 100644
index 000000000000..9e232b320516
--- /dev/null
+++ b/src/doc/rustc/src/platform-support/aarch64v8r-unknown-none.md
@@ -0,0 +1,84 @@
+# `aarch64v8r-unknown-none` and `aarch64v8r-unknown-none-softfloat`
+
+* **Tier: 3**
+* **Library Support:** core and alloc (bare-metal, `#![no_std]`)
+
+Bare-metal target for CPUs in the Armv8-R architecture family, running in
+AArch64 mode. Processors in this family include the
+[Arm Cortex-R82][cortex-r82].
+
+For Armv8-R CPUs running in AArch32 mode (such as the Arm Cortex-R52), see
+[`armv8r-none-eabihf`](armv8r-none-eabihf.md) instead.
+
+[cortex-r82]: https://developer.arm.com/processors/Cortex-R82
+
+## Target maintainers
+
+- [Rust Embedded Devices Working Group Arm Team]
+- [@rust-lang/arm-maintainers][arm_maintainers] ([rust@arm.com][arm_email])
+
+[Rust Embedded Devices Working Group Arm Team]: https://github.com/rust-embedded/wg?tab=readme-ov-file#the-arm-team
+[arm_maintainers]: https://github.com/rust-lang/team/blob/master/teams/arm-maintainers.toml
+[arm_email]: mailto:rust@arm.com
+
+## Target CPU and Target Feature options
+
+Unlike AArch64 v8-A processors, not all AArch64 v8-R processors include an FPU
+(that is, not all Armv8-R AArch64 processors implement the optional Armv8
+`FEAT_FP` extension). If you do not have an FPU, or have an FPU but wish to use
+a soft-float ABI anyway, you should use the `aarch64v8r-unknown-none-softfloat`
+target. If you wish to use the standard hard-float Arm AArch64 calling
+convention, and you have an FPU, you can use the `aarch64v8r-unknown-none`
+target.
+
+When using the `aarch64v8r-unknown-none` target, the minimum floating-point
+features assumed are the Advanced SIMD features (`FEAT_AdvSIMD`, or `+neon`),
+the implementation of which is branded Arm NEON.
+
+If your processor supports a different set of floating-point features than the
+default expectations then these should also be enabled or disabled as needed
+with [`-C target-feature=(+/-)`][target-feature]. However, note that currently
+Rust does not support building hard-float AArch64 targets with Advanced SIMD
+support disabled. It is also possible to tell Rust (or LLVM) that you have a
+specific model of Arm processor, using the [`-Ctarget-cpu`][target-cpu] option.
+Doing so may change the default set of target-features enabled.
+
+[target-feature]: https://doc.rust-lang.org/rustc/codegen-options/index.html#target-feature
+[target-cpu]: https://doc.rust-lang.org/rustc/codegen-options/index.html#target-cpu
+
+## Requirements
+
+These targets are cross-compiled and use static linking.
+
+By default, the `lld` linker included with Rust will be used; however, you may
+want to use the GNU linker instead. This can be obtained for Windows/Mac/Linux
+from the [Arm Developer Website][arm-gnu-toolchain], or possibly from your OS's
+package manager. To use it, add the following to your `.cargo/config.toml`:
+
+```toml
+[target.aarch64-unknown-none]
+linker = "aarch64-none-elf-ld"
+```
+
+The GNU linker can also be used by specifying `aarch64-none-elf-gcc` as the
+linker. This is needed when using GCC's link time optimization.
+
+These targets don't provide a linker script, so you'll need to bring your own
+according to the specific device you are using. Pass
+`-Clink-arg=-Tyour_script.ld` as a rustc argument to make the linker use
+`your_script.ld` during linking.
+
+[arm-gnu-toolchain]: https://developer.arm.com/Tools%20and%20Software/GNU%20Toolchain
+
+## Cross-compilation toolchains and C code
+
+This target supports C code compiled with the `aarch64-none-elf` target
+triple and a suitable `-march` or `-mcpu` flag.
+
+## Start-up and Low-Level Code
+
+The [Rust Embedded Devices Working Group Arm Team] maintain the
+[`aarch64-cpu`] crate, which may be useful for writing bare-metal code using
+this target.
+
+[`aarch64-cpu`]: https://docs.rs/aarch64-cpu
diff --git a/src/doc/rustc/src/platform-support/armv8r-none-eabihf.md b/src/doc/rustc/src/platform-support/armv8r-none-eabihf.md
index 85abac3d7eb8..73d88bcb89a1 100644
--- a/src/doc/rustc/src/platform-support/armv8r-none-eabihf.md
+++ b/src/doc/rustc/src/platform-support/armv8r-none-eabihf.md
@@ -15,6 +15,9 @@ and [Cortex-R52+][cortex-r52-plus].
 See [`arm-none-eabi`](arm-none-eabi.md) for information applicable to all
 `arm-none-eabi` targets.
 
+For Armv8-R CPUs running in AArch64 mode (such as the Arm Cortex-R82), see
+[`aarch64v8r-unknown-none`](aarch64v8r-unknown-none.md) instead.
+
 [cortex-r52]: https://www.arm.com/products/silicon-ip-cpu/cortex-r/cortex-r52
 [cortex-r52-plus]: https://www.arm.com/products/silicon-ip-cpu/cortex-r/cortex-r52-plus
 
diff --git a/src/tools/tidy/src/target_specific_tests.rs b/src/tools/tidy/src/target_specific_tests.rs
index 11138de5de76..ea365527a8cd 100644
--- a/src/tools/tidy/src/target_specific_tests.rs
+++ b/src/tools/tidy/src/target_specific_tests.rs
@@ -98,7 +98,7 @@ fn arch_to_llvm_component(arch: &str) -> String {
     // enough for the purpose of this tidy check.
     match arch {
         "amdgcn" => "amdgpu".into(),
-        "aarch64_be" | "arm64_32" | "arm64e" | "arm64ec" => "aarch64".into(),
+        "aarch64v8r" | "aarch64_be" | "arm64_32" | "arm64e" | "arm64ec" => "aarch64".into(),
         "i386" | "i586" | "i686" | "x86" | "x86_64" | "x86_64h" => "x86".into(),
         "loongarch32" | "loongarch64" => "loongarch".into(),
         "nvptx64" => "nvptx".into(),
diff --git a/tests/assembly-llvm/targets/targets-elf.rs b/tests/assembly-llvm/targets/targets-elf.rs
index 0d5cd796aa48..c38e86315b27 100644
--- a/tests/assembly-llvm/targets/targets-elf.rs
+++ b/tests/assembly-llvm/targets/targets-elf.rs
@@ -67,6 +67,12 @@
 //@ revisions: aarch64_unknown_none_softfloat
 //@ [aarch64_unknown_none_softfloat] compile-flags: --target aarch64-unknown-none-softfloat
 //@ [aarch64_unknown_none_softfloat] needs-llvm-components: aarch64
+//@ revisions: aarch64v8r_unknown_none
+//@ [aarch64v8r_unknown_none] compile-flags: --target aarch64v8r-unknown-none
+//@ [aarch64v8r_unknown_none] needs-llvm-components: aarch64
+//@ revisions: aarch64v8r_unknown_none_softfloat
+//@ [aarch64v8r_unknown_none_softfloat] compile-flags: --target aarch64v8r-unknown-none-softfloat
+//@ [aarch64v8r_unknown_none_softfloat] needs-llvm-components: aarch64
 //@ revisions: aarch64_unknown_nto_qnx700
 //@ [aarch64_unknown_nto_qnx700] compile-flags: --target aarch64-unknown-nto-qnx700
 //@ [aarch64_unknown_nto_qnx700] needs-llvm-components: aarch64
diff --git a/tests/codegen-llvm/aarch64v8r-softfloat.rs b/tests/codegen-llvm/aarch64v8r-softfloat.rs
new file mode 100644
index 000000000000..5ccda4f3a0ae
--- /dev/null
+++ b/tests/codegen-llvm/aarch64v8r-softfloat.rs
@@ -0,0 +1,45 @@
+//@ add-minicore
+//@ compile-flags: --target aarch64v8r-unknown-none-softfloat -Zmerge-functions=disabled
+//@ needs-llvm-components: aarch64
+#![crate_type = "lib"]
+#![feature(no_core, lang_items)]
+#![no_core]
+
+extern crate minicore;
+use minicore::*;
+
+// CHECK: i64 @pass_f64_C(i64 {{[^,]*}})
+#[no_mangle]
+extern "C" fn pass_f64_C(x: f64) -> f64 {
+    x
+}
+
+// CHECK: i64 @pass_f32_pair_C(i64 {{[^,]*}})
+#[no_mangle]
+extern "C" fn pass_f32_pair_C(x: (f32, f32)) -> (f32, f32) {
+    x
+}
+
+// CHECK: [2 x i64] @pass_f64_pair_C([2 x i64] {{[^,]*}})
+#[no_mangle]
+extern "C" fn pass_f64_pair_C(x: (f64, f64)) -> (f64, f64) {
+    x
+}
+
+// CHECK: i64 @pass_f64_Rust(i64 {{[^,]*}})
+#[no_mangle]
+fn pass_f64_Rust(x: f64) -> f64 {
+    x
+}
+
+// CHECK: i64 @pass_f32_pair_Rust(i64 {{[^,]*}})
+#[no_mangle]
+fn pass_f32_pair_Rust(x: (f32, f32)) -> (f32, f32) {
+    x
+}
+
+// CHECK: void @pass_f64_pair_Rust(ptr {{.*}}%{{[^ ]+}}, ptr {{.*}}%{{[^ ]+}})
+#[no_mangle]
+fn pass_f64_pair_Rust(x: (f64, f64)) -> (f64, f64) {
+    x
+}
diff --git a/tests/codegen-llvm/sanitizer/kasan-emits-instrumentation.rs b/tests/codegen-llvm/sanitizer/kasan-emits-instrumentation.rs
index da0c976d8a53..f0135cdd0011 100644
--- a/tests/codegen-llvm/sanitizer/kasan-emits-instrumentation.rs
+++ b/tests/codegen-llvm/sanitizer/kasan-emits-instrumentation.rs
@@ -2,9 +2,11 @@
 
 //@ add-minicore
 //@ compile-flags: -Zsanitizer=kernel-address -Copt-level=0
-//@ revisions: aarch64 riscv64imac riscv64gc x86_64
+//@ revisions: aarch64 aarch64v8r riscv64imac riscv64gc x86_64
 //@[aarch64] compile-flags: --target aarch64-unknown-none
 //@[aarch64] needs-llvm-components: aarch64
+//@[aarch64v8r] compile-flags: --target aarch64v8r-unknown-none
+//@[aarch64v8r] needs-llvm-components: aarch64
 //@[riscv64imac] compile-flags: --target riscv64imac-unknown-none-elf
 //@[riscv64imac] needs-llvm-components: riscv
 //@[riscv64gc] compile-flags: --target riscv64gc-unknown-none-elf
diff --git a/tests/codegen-llvm/sanitizer/kcfi/add-cfi-normalize-integers-flag.rs b/tests/codegen-llvm/sanitizer/kcfi/add-cfi-normalize-integers-flag.rs
index 24c5d1be1d60..53b8c605eb73 100644
--- a/tests/codegen-llvm/sanitizer/kcfi/add-cfi-normalize-integers-flag.rs
+++ b/tests/codegen-llvm/sanitizer/kcfi/add-cfi-normalize-integers-flag.rs
@@ -1,9 +1,11 @@
 // Verifies that "cfi-normalize-integers" module flag is added.
 //
 //@ add-minicore
-//@ revisions: aarch64 x86_64
+//@ revisions: aarch64 aarch64v8r x86_64
 //@ [aarch64] compile-flags: --target aarch64-unknown-none
 //@ [aarch64] needs-llvm-components: aarch64
+//@ [aarch64v8r] compile-flags: --target aarch64v8r-unknown-none
+//@ [aarch64v8r] needs-llvm-components: aarch64
 //@ [x86_64] compile-flags: --target x86_64-unknown-none
 //@ [x86_64] needs-llvm-components: x86
 //@ compile-flags: -Ctarget-feature=-crt-static -Zsanitizer=kcfi -Zsanitizer-cfi-normalize-integers
diff --git a/tests/codegen-llvm/sanitizer/kcfi/add-kcfi-flag.rs b/tests/codegen-llvm/sanitizer/kcfi/add-kcfi-flag.rs
index 53b1a3f2d74a..9058d5b5cfcb 100644
--- a/tests/codegen-llvm/sanitizer/kcfi/add-kcfi-flag.rs
+++ b/tests/codegen-llvm/sanitizer/kcfi/add-kcfi-flag.rs
@@ -1,9 +1,11 @@
 // Verifies that "kcfi" module flag is added.
 //
 //@ add-minicore
-//@ revisions: aarch64 x86_64
+//@ revisions: aarch64 aarch64v8r x86_64
 //@ [aarch64] compile-flags: --target aarch64-unknown-none
 //@ [aarch64] needs-llvm-components: aarch64
+//@ [aarch64v8r] compile-flags: --target aarch64v8r-unknown-none
+//@ [aarch64v8r] needs-llvm-components: aarch64
 //@ [x86_64] compile-flags: --target x86_64-unknown-none
 //@ [x86_64] needs-llvm-components: x86
 //@ compile-flags: -Ctarget-feature=-crt-static -Zsanitizer=kcfi
diff --git a/tests/codegen-llvm/sanitizer/kcfi/add-kcfi-offset-flag.rs b/tests/codegen-llvm/sanitizer/kcfi/add-kcfi-offset-flag.rs
index 82747351e028..6574302033c8 100644
--- a/tests/codegen-llvm/sanitizer/kcfi/add-kcfi-offset-flag.rs
+++ b/tests/codegen-llvm/sanitizer/kcfi/add-kcfi-offset-flag.rs
@@ -1,9 +1,11 @@
 // Verifies that "kcfi-offset" module flag is added.
 //
 //@ add-minicore
-//@ revisions: aarch64 x86_64
+//@ revisions: aarch64 aarch64v8r x86_64
 //@ [aarch64] compile-flags: --target aarch64-unknown-none
 //@ [aarch64] needs-llvm-components: aarch64
+//@ [aarch64v8r] compile-flags: --target aarch64v8r-unknown-none
+//@ [aarch64v8r] needs-llvm-components: aarch64
 //@ [x86_64] compile-flags: --target x86_64-unknown-none
 //@ [x86_64] needs-llvm-components: x86
 //@ compile-flags: -Ctarget-feature=-crt-static -Zsanitizer=kcfi -Z patchable-function-entry=4,3
diff --git a/tests/codegen-llvm/sanitizer/kcfi/emit-kcfi-operand-bundle-attr-sanitize-off.rs b/tests/codegen-llvm/sanitizer/kcfi/emit-kcfi-operand-bundle-attr-sanitize-off.rs
index ee4928053cf9..eb9ab6b8f90c 100644
--- a/tests/codegen-llvm/sanitizer/kcfi/emit-kcfi-operand-bundle-attr-sanitize-off.rs
+++ b/tests/codegen-llvm/sanitizer/kcfi/emit-kcfi-operand-bundle-attr-sanitize-off.rs
@@ -1,9 +1,11 @@
 // Verifies that KCFI operand bundles are omitted.
 //
 //@ add-minicore
-//@ revisions: aarch64 x86_64
+//@ revisions: aarch64 aarch64v8r x86_64
 //@ [aarch64] compile-flags: --target aarch64-unknown-none
 //@ [aarch64] needs-llvm-components: aarch64
+//@ [aarch64v8r] compile-flags: --target aarch64v8r-unknown-none
+//@ [aarch64v8r] needs-llvm-components: aarch64
 //@ [x86_64] compile-flags: --target x86_64-unknown-none
 //@ [x86_64] needs-llvm-components: x86
 //@ compile-flags: -Cno-prepopulate-passes -Zsanitizer=kcfi -Copt-level=0
diff --git a/tests/codegen-llvm/sanitizer/kcfi/emit-kcfi-operand-bundle-itanium-cxx-abi-generalized.rs b/tests/codegen-llvm/sanitizer/kcfi/emit-kcfi-operand-bundle-itanium-cxx-abi-generalized.rs
index 9b861c08ac95..f934a3bfcee7 100644
--- a/tests/codegen-llvm/sanitizer/kcfi/emit-kcfi-operand-bundle-itanium-cxx-abi-generalized.rs
+++ b/tests/codegen-llvm/sanitizer/kcfi/emit-kcfi-operand-bundle-itanium-cxx-abi-generalized.rs
@@ -1,9 +1,11 @@
 // Verifies that generalized KCFI type metadata for functions are emitted.
 //
 //@ add-minicore
-//@ revisions: aarch64 x86_64
+//@ revisions: aarch64 aarch64v8r x86_64
 //@ [aarch64] compile-flags: --target aarch64-unknown-none
 //@ [aarch64] needs-llvm-components: aarch64
+//@ [aarch64v8r] compile-flags: --target aarch64v8r-unknown-none
+//@ [aarch64v8r] needs-llvm-components: aarch64
 //@ [x86_64] compile-flags: --target x86_64-unknown-none
 //@ [x86_64] needs-llvm-components: x86
 //@ compile-flags: -Cno-prepopulate-passes -Zsanitizer=kcfi -Zsanitizer-cfi-generalize-pointers
diff --git a/tests/codegen-llvm/sanitizer/kcfi/emit-kcfi-operand-bundle-itanium-cxx-abi-normalized-generalized.rs b/tests/codegen-llvm/sanitizer/kcfi/emit-kcfi-operand-bundle-itanium-cxx-abi-normalized-generalized.rs
index c2410aa9f4d8..b72b6d7ce308 100644
--- a/tests/codegen-llvm/sanitizer/kcfi/emit-kcfi-operand-bundle-itanium-cxx-abi-normalized-generalized.rs
+++ b/tests/codegen-llvm/sanitizer/kcfi/emit-kcfi-operand-bundle-itanium-cxx-abi-normalized-generalized.rs
@@ -1,9 +1,11 @@
 // Verifies that normalized and generalized KCFI type metadata for functions are emitted.
 //
 //@ add-minicore
-//@ revisions: aarch64 x86_64
+//@ revisions: aarch64 aarch64v8r x86_64
 //@ [aarch64] compile-flags: --target aarch64-unknown-none
 //@ [aarch64] needs-llvm-components: aarch64
+//@ [aarch64v8r] compile-flags: --target aarch64v8r-unknown-none
+//@ [aarch64v8r] needs-llvm-components: aarch64
 //@ [x86_64] compile-flags: --target x86_64-unknown-none
 //@ [x86_64] needs-llvm-components: x86
 //@ compile-flags: -Cno-prepopulate-passes -Zsanitizer=kcfi -Zsanitizer-cfi-normalize-integers -Zsanitizer-cfi-generalize-pointers
diff --git a/tests/codegen-llvm/sanitizer/kcfi/emit-kcfi-operand-bundle-itanium-cxx-abi-normalized.rs b/tests/codegen-llvm/sanitizer/kcfi/emit-kcfi-operand-bundle-itanium-cxx-abi-normalized.rs
index fbad335286cb..064ab53a1856 100644
--- a/tests/codegen-llvm/sanitizer/kcfi/emit-kcfi-operand-bundle-itanium-cxx-abi-normalized.rs
+++ b/tests/codegen-llvm/sanitizer/kcfi/emit-kcfi-operand-bundle-itanium-cxx-abi-normalized.rs
@@ -1,9 +1,11 @@
 // Verifies that normalized KCFI type metadata for functions are emitted.
 //
 //@ add-minicore
-//@ revisions: aarch64 x86_64
+//@ revisions: aarch64 aarch64v8r x86_64
 //@ [aarch64] compile-flags: --target aarch64-unknown-none
 //@ [aarch64] needs-llvm-components: aarch64
+//@ [aarch64v8r] compile-flags: --target aarch64v8r-unknown-none
+//@ [aarch64v8r] needs-llvm-components: aarch64
 //@ [x86_64] compile-flags: --target x86_64-unknown-none
 //@ [x86_64] needs-llvm-components: x86
 //@ compile-flags: -Cno-prepopulate-passes -Zsanitizer=kcfi -Zsanitizer-cfi-normalize-integers
diff --git a/tests/codegen-llvm/sanitizer/kcfi/emit-kcfi-operand-bundle-itanium-cxx-abi.rs b/tests/codegen-llvm/sanitizer/kcfi/emit-kcfi-operand-bundle-itanium-cxx-abi.rs
index 6c7a8194ec4e..8410286e49db 100644
--- a/tests/codegen-llvm/sanitizer/kcfi/emit-kcfi-operand-bundle-itanium-cxx-abi.rs
+++ b/tests/codegen-llvm/sanitizer/kcfi/emit-kcfi-operand-bundle-itanium-cxx-abi.rs
@@ -1,9 +1,11 @@
 // Verifies that KCFI type metadata for functions are emitted.
 //
 //@ add-minicore
-//@ revisions: aarch64 x86_64
+//@ revisions: aarch64 aarch64v8r x86_64
 //@ [aarch64] compile-flags: --target aarch64-unknown-none
 //@ [aarch64] needs-llvm-components: aarch64
+//@ [aarch64v8r] compile-flags: --target aarch64v8r-unknown-none
+//@ [aarch64v8r] needs-llvm-components: aarch64
 //@ [x86_64] compile-flags: --target x86_64-unknown-none
 //@ [x86_64] needs-llvm-components: x86
 //@ compile-flags: -Cno-prepopulate-passes -Zsanitizer=kcfi -Copt-level=0
diff --git a/tests/codegen-llvm/sanitizer/kcfi/emit-kcfi-operand-bundle.rs b/tests/codegen-llvm/sanitizer/kcfi/emit-kcfi-operand-bundle.rs
index e22a210f3dfb..3494854bcffd 100644
--- a/tests/codegen-llvm/sanitizer/kcfi/emit-kcfi-operand-bundle.rs
+++ b/tests/codegen-llvm/sanitizer/kcfi/emit-kcfi-operand-bundle.rs
@@ -1,9 +1,11 @@
 // Verifies that KCFI operand bundles are emitted.
 //
 //@ add-minicore
-//@ revisions: aarch64 x86_64
+//@ revisions: aarch64 aarch64v8r x86_64
 //@ [aarch64] compile-flags: --target aarch64-unknown-none
 //@ [aarch64] needs-llvm-components: aarch64
+//@ [aarch64v8r] compile-flags: --target aarch64v8r-unknown-none
+//@ [aarch64v8r] needs-llvm-components: aarch64
 //@ [x86_64] compile-flags: --target x86_64-unknown-none
 //@ [x86_64] needs-llvm-components: x86
 //@ compile-flags: -Cno-prepopulate-passes -Zsanitizer=kcfi -Copt-level=0
diff --git a/tests/codegen-llvm/sanitizer/kcfi/emit-type-metadata-trait-objects.rs b/tests/codegen-llvm/sanitizer/kcfi/emit-type-metadata-trait-objects.rs
index 3312f12f6885..4510e70cbc35 100644
--- a/tests/codegen-llvm/sanitizer/kcfi/emit-type-metadata-trait-objects.rs
+++ b/tests/codegen-llvm/sanitizer/kcfi/emit-type-metadata-trait-objects.rs
@@ -1,9 +1,11 @@
 // Verifies that type metadata identifiers for trait objects are emitted correctly.
 //
 //@ add-minicore
-//@ revisions: aarch64 x86_64
+//@ revisions: aarch64v8r aarch64 x86_64
 //@ [aarch64] compile-flags: --target aarch64-unknown-none
 //@ [aarch64] needs-llvm-components: aarch64
+//@ [aarch64v8r] compile-flags: --target aarch64v8r-unknown-none
+//@ [aarch64v8r] needs-llvm-components: aarch64
 //@ [x86_64] compile-flags: --target x86_64-unknown-none
 //@ [x86_64] needs-llvm-components: x86
 //@ compile-flags: -Cno-prepopulate-passes -Zsanitizer=kcfi -Copt-level=0
diff --git a/tests/codegen-llvm/sanitizer/kcfi/fn-ptr-reify-shim.rs b/tests/codegen-llvm/sanitizer/kcfi/fn-ptr-reify-shim.rs
index 676b2af8c8f1..8cfb6a57a4a9 100644
--- a/tests/codegen-llvm/sanitizer/kcfi/fn-ptr-reify-shim.rs
+++ b/tests/codegen-llvm/sanitizer/kcfi/fn-ptr-reify-shim.rs
@@ -1,7 +1,9 @@
 //@ add-minicore
-//@ revisions: aarch64 x86_64
+//@ revisions: aarch64 aarch64v8r x86_64
 //@ [aarch64] compile-flags: --target aarch64-unknown-none
 //@ [aarch64] needs-llvm-components: aarch64
+//@ [aarch64v8r] compile-flags: --target aarch64v8r-unknown-none
+//@ [aarch64v8r] needs-llvm-components: aarch64
 //@ [x86_64] compile-flags: --target x86_64-unknown-none
 //@ [x86_64] needs-llvm-components: x86
 //@ compile-flags: -Ctarget-feature=-crt-static -Zsanitizer=kcfi -Cno-prepopulate-passes -Copt-level=0
diff --git a/tests/codegen-llvm/sanitizer/kcfi/naked-function.rs b/tests/codegen-llvm/sanitizer/kcfi/naked-function.rs
index 830689780dce..6b9d11b192b3 100644
--- a/tests/codegen-llvm/sanitizer/kcfi/naked-function.rs
+++ b/tests/codegen-llvm/sanitizer/kcfi/naked-function.rs
@@ -1,7 +1,9 @@
 //@ add-minicore
-//@ revisions: aarch64 x86_64
+//@ revisions: aarch64 aarch64v8r x86_64
 //@ [aarch64] compile-flags: --target aarch64-unknown-none
 //@ [aarch64] needs-llvm-components: aarch64
+//@ [aarch64v8r] compile-flags: --target aarch64v8r-unknown-none
+//@ [aarch64v8r] needs-llvm-components: aarch64
 //@ [x86_64] compile-flags: --target x86_64-unknown-none
 //@ [x86_64] needs-llvm-components: x86
 //@ compile-flags: -Ctarget-feature=-crt-static -Zsanitizer=kcfi -Cno-prepopulate-passes -Copt-level=0
diff --git a/tests/codegen-llvm/sanitizer/sanitize-off-asan-kasan.rs b/tests/codegen-llvm/sanitizer/sanitize-off-asan-kasan.rs
index c5df311efae0..cef4a650e477 100644
--- a/tests/codegen-llvm/sanitizer/sanitize-off-asan-kasan.rs
+++ b/tests/codegen-llvm/sanitizer/sanitize-off-asan-kasan.rs
@@ -3,9 +3,11 @@
 //
 //@ add-minicore
 //@ compile-flags: -Zsanitizer=kernel-address -Ctarget-feature=-crt-static -Copt-level=0
-//@ revisions: aarch64 riscv64imac riscv64gc x86_64
+//@ revisions: aarch64 aarch64v8r riscv64imac riscv64gc x86_64
 //@[aarch64] compile-flags: --target aarch64-unknown-none
 //@[aarch64] needs-llvm-components: aarch64
+//@[aarch64v8r] compile-flags: --target aarch64v8r-unknown-none
+//@[aarch64v8r] needs-llvm-components: aarch64
 //@[riscv64imac] compile-flags: --target riscv64imac-unknown-none-elf
 //@[riscv64imac] needs-llvm-components: riscv
 //@[riscv64gc] compile-flags: --target riscv64gc-unknown-none-elf
diff --git a/tests/ui/asm/aarch64v8r.rs b/tests/ui/asm/aarch64v8r.rs
new file mode 100644
index 000000000000..6b582bb730f0
--- /dev/null
+++ b/tests/ui/asm/aarch64v8r.rs
@@ -0,0 +1,140 @@
+// Codegen test of mandatory Armv8-R AArch64 extensions
+
+//@ add-minicore
+//@ revisions: hf sf
+//@ [hf] compile-flags: --target aarch64v8r-unknown-none
+//@ [hf] needs-llvm-components: aarch64
+//@ [sf] compile-flags: --target aarch64v8r-unknown-none-softfloat
+//@ [sf] needs-llvm-components: aarch64
+//@ build-pass
+//@ ignore-backends: gcc
+
+#![feature(no_core)]
+#![no_core]
+#![no_main]
+#![crate_type = "rlib"]
+#![deny(dead_code)] // ensures we call all private functions from the public one
+
+extern crate minicore;
+use minicore::*;
+
+/* # Mandatory extensions
+ *
+ * A comment indicates that the extension has no associated assembly instruction and cannot be
+ * codegen tested
+ *
+ * ## References:
+ *
+ * - Arm Architecture Reference Manual for R-profile AArch64 architecture (DDI 0628) -- has the
+ *   list of mandatory extensions
+ * - Arm Architecture Reference Manual for A-profile architecture (ARM DDI 0487) -- has the
+ *   mapping from features to instructions
+ * - Feature names in A-profile architecture (109697_0100_02_en Version 1.0) -- overview of
+ *   what each extension mean
+ * */
+pub fn mandatory_extensions() {
+    /* ## ARMv8.0 */
+    feat_aa64();
+    // FEAT_AA64EL0
+    // FEAT_AA64EL1
+    // FEAT_AA64EL2
+    feat_crc32();
+    // FEAT_EL0
+    // FEAT_EL1
+    // FEAT_EL2
+    // FEAT_IVIPT
+
+    /* ## ARMv8.1 */
+    // FEAT_HPDS
+    feat_lse();
+    feat_pan();
+
+    /* ## ARMv8.2 */
+    feat_asmv8p2();
+    feat_dpb();
+    // FEAT_Debugv8p2
+    // FEAT_PAN2
+    feat_ras();
+    // FEAT_TTCNP
+    feat_uao();
+    // FEAT_XNX
+
+    /* ## ARMv8.3 */
+    feat_lrcpc();
+    feat_pauth();
+
+    /* ## ARMv8.4 */
+    feat_dit();
+    // FEAT_Debugv8p4
+    feat_flagm();
+    // FEAT_IDST
+    feat_lrcpc2();
+    // FEAT_LSE2
+    // FEAT_S2FWB
+    feat_tlbios();
+    feat_tlbirange();
+    // FEAT_TTL
+}
+
+fn feat_aa64() {
+    // CurrentEL register only present when FEAT_AA64 is implemented
+    unsafe { asm!("mrs x0, CurrentEL") }
+}
+
+fn feat_crc32() {
+    // instruction is present when FEAT_CRC32 is implemented
+    unsafe { asm!("crc32b w0, w1, w2") }
+}
+
+fn feat_lse() {
+    // instruction is present when FEAT_LSE is implemented
+    unsafe { asm!("casp w0, w1, w2, w3, [x4]") }
+}
+
+fn feat_pan() {
+    unsafe { asm!("mrs x0, PAN") }
+}
+
+fn feat_asmv8p2() {
+    unsafe { asm!("BFC w0, #0, #1") }
+}
+
+fn feat_dpb() {
+    unsafe { asm!("DC CVAP, x0") }
+}
+
+fn feat_ras() {
+    unsafe { asm!("ESB") }
+}
+
+fn feat_uao() {
+    unsafe { asm!("mrs x0, UAO") }
+}
+
+fn feat_lrcpc() {
+    unsafe { asm!("ldaprb w0, [x1]") }
+}
+
+fn feat_pauth() {
+    unsafe { asm!("xpacd x0") }
+}
+
+fn feat_dit() {
+    unsafe { asm!("mrs x0, DIT") }
+}
+
+fn feat_flagm() {
+    unsafe { asm!("cfinv") }
+}
+
+fn feat_lrcpc2() {
+    unsafe { asm!("stlurb w0, [x1]") }
+}
+
+fn feat_tlbios() {
+    unsafe { asm!("tlbi VMALLE1OS") }
+}
+
+fn feat_tlbirange() {
+    unsafe { asm!("tlbi RVAE1IS, x0") }
+}

From bf1c3f6a14d41785416e89eaa909a674021e7727 Mon Sep 17 00:00:00 2001
From: cyrgani <ansgar.w.zielke@gmail.com>
Date: Mon, 26 Jan 2026 11:02:50 +0000
Subject: [PATCH 34/97] move `Types` from `with_api!` to `Server`

---
 .../rustc_expand/src/proc_macro_server.rs     |   4 +-
 library/proc_macro/src/bridge/client.rs       |  13 +-
 library/proc_macro/src/bridge/mod.rs          | 121 ++++++++----------
 library/proc_macro/src/bridge/server.rs       |  59 ++++-----
 .../crates/proc-macro-srv/src/dylib.rs        |   2 +-
 .../src/server_impl/rust_analyzer_span.rs     |   4 +-
 .../src/server_impl/token_id.rs               |   4 +-
 7 files changed, 81 insertions(+), 126 deletions(-)

diff --git a/compiler/rustc_expand/src/proc_macro_server.rs b/compiler/rustc_expand/src/proc_macro_server.rs
index a51aa90355bc..12490880ab0e 100644
--- a/compiler/rustc_expand/src/proc_macro_server.rs
+++ b/compiler/rustc_expand/src/proc_macro_server.rs
@@ -458,13 +458,11 @@ impl<'a, 'b> Rustc<'a, 'b> {
     }
 }
 
-impl server::Types for Rustc<'_, '_> {
+impl server::Server for Rustc<'_, '_> {
     type TokenStream = TokenStream;
     type Span = Span;
     type Symbol = Symbol;
-}
 
-impl server::Server for Rustc<'_, '_> {
     fn globals(&mut self) -> ExpnGlobals<Self::Span> {
         ExpnGlobals {
             def_site: self.def_site,
diff --git a/library/proc_macro/src/bridge/client.rs b/library/proc_macro/src/bridge/client.rs
index 0d87a727ae40..381c8502c853 100644
--- a/library/proc_macro/src/bridge/client.rs
+++ b/library/proc_macro/src/bridge/client.rs
@@ -67,12 +67,6 @@ impl<S> Decode<'_, '_, S> for Span {
     }
 }
 
-// FIXME(eddyb) generate these impls by pattern-matching on the
-// names of methods - also could use the presence of `fn drop`
-// to distinguish between 'owned and 'interned, above.
-// Alternatively, special "modes" could be listed of types in with_api
-// instead of pattern matching on methods, here and in server decl.
-
 impl Clone for TokenStream {
     fn clone(&self) -> Self {
         Methods::ts_clone(self)
@@ -104,10 +98,7 @@ pub(crate) use super::symbol::Symbol;
 
 macro_rules! define_client_side {
     (
-        Methods {
-            $(fn $method:ident($($arg:ident: $arg_ty:ty),* $(,)?) $(-> $ret_ty:ty)*;)*
-        },
-        $($name:ident),* $(,)?
+        $(fn $method:ident($($arg:ident: $arg_ty:ty),* $(,)?) $(-> $ret_ty:ty)*;)*
     ) => {
         impl Methods {
             $(pub(crate) fn $method($($arg: $arg_ty),*) $(-> $ret_ty)? {
@@ -130,7 +121,7 @@ macro_rules! define_client_side {
         }
     }
 }
-with_api!(self, self, define_client_side);
+with_api!(self, define_client_side);
 
 struct Bridge<'a> {
     /// Reusable buffer (only `clear`-ed, never shrunk), primarily
diff --git a/library/proc_macro/src/bridge/mod.rs b/library/proc_macro/src/bridge/mod.rs
index 6f7c8726f925..f454861be4ed 100644
--- a/library/proc_macro/src/bridge/mod.rs
+++ b/library/proc_macro/src/bridge/mod.rs
@@ -18,87 +18,71 @@ use crate::{Delimiter, Level, Spacing};
 /// Higher-order macro describing the server RPC API, allowing automatic
 /// generation of type-safe Rust APIs, both client-side and server-side.
 ///
-/// `with_api!(MySelf, my_self, my_macro)` expands to:
+/// `with_api!(MySelf, my_macro)` expands to:
 /// ```rust,ignore (pseudo-code)
 /// my_macro! {
-///     Methods {
-///         // ...
-///         fn lit_character(ch: char) -> MySelf::Literal;
-///         // ...
-///         fn lit_span(my_self: &MySelf::Literal) -> MySelf::Span;
-///         fn lit_set_span(my_self: &mut MySelf::Literal, span: MySelf::Span);
-///     },
-///     Literal,
-///     Span,
+///     fn lit_character(ch: char) -> MySelf::Literal;
+///     fn lit_span(lit: &MySelf::Literal) -> MySelf::Span;
+///     fn lit_set_span(lit: &mut MySelf::Literal, span: MySelf::Span);
 ///     // ...
 /// }
 /// ```
 ///
-/// The first two arguments serve to customize the arguments names
-/// and argument/return types, to enable several different usecases:
-///
-/// If `my_self` is just `self`, then each `fn` signature can be used
-/// as-is for a method. If it's anything else (`self_` in practice),
-/// then the signatures don't have a special `self` argument, and
-/// can, therefore, have a different one introduced.
+/// The first argument serves to customize the argument/return types,
+/// to enable several different usecases:
 ///
 /// If `MySelf` is just `Self`, then the types are only valid inside
 /// a trait or a trait impl, where the trait has associated types
 /// for each of the API types. If non-associated types are desired,
 /// a module name (`self` in practice) can be used instead of `Self`.
 macro_rules! with_api {
-    ($S:ident, $self:ident, $m:ident) => {
+    ($S:ident, $m:ident) => {
         $m! {
-            Methods {
-                fn injected_env_var(var: &str) -> Option<String>;
-                fn track_env_var(var: &str, value: Option<&str>);
-                fn track_path(path: &str);
-                fn literal_from_str(s: &str) -> Result<Literal<$S::Span, $S::Symbol>, ()>;
-                fn emit_diagnostic(diagnostic: Diagnostic<$S::Span>);
+            fn injected_env_var(var: &str) -> Option<String>;
+            fn track_env_var(var: &str, value: Option<&str>);
+            fn track_path(path: &str);
+            fn literal_from_str(s: &str) -> Result<Literal<$S::Span, $S::Symbol>, ()>;
+            fn emit_diagnostic(diagnostic: Diagnostic<$S::Span>);
 
-                fn ts_drop(stream: $S::TokenStream);
-                fn ts_clone(stream: &$S::TokenStream) -> $S::TokenStream;
-                fn ts_is_empty(stream: &$S::TokenStream) -> bool;
-                fn ts_expand_expr(stream: &$S::TokenStream) -> Result<$S::TokenStream, ()>;
-                fn ts_from_str(src: &str) -> $S::TokenStream;
-                fn ts_to_string(stream: &$S::TokenStream) -> String;
-                fn ts_from_token_tree(
-                    tree: TokenTree<$S::TokenStream, $S::Span, $S::Symbol>,
-                ) -> $S::TokenStream;
-                fn ts_concat_trees(
-                    base: Option<$S::TokenStream>,
-                    trees: Vec<TokenTree<$S::TokenStream, $S::Span, $S::Symbol>>,
-                ) -> $S::TokenStream;
-                fn ts_concat_streams(
-                    base: Option<$S::TokenStream>,
-                    streams: Vec<$S::TokenStream>,
-                ) -> $S::TokenStream;
-                fn ts_into_trees(
-                    stream: $S::TokenStream
-                ) -> Vec<TokenTree<$S::TokenStream, $S::Span, $S::Symbol>>;
+            fn ts_drop(stream: $S::TokenStream);
+            fn ts_clone(stream: &$S::TokenStream) -> $S::TokenStream;
+            fn ts_is_empty(stream: &$S::TokenStream) -> bool;
+            fn ts_expand_expr(stream: &$S::TokenStream) -> Result<$S::TokenStream, ()>;
+            fn ts_from_str(src: &str) -> $S::TokenStream;
+            fn ts_to_string(stream: &$S::TokenStream) -> String;
+            fn ts_from_token_tree(
+                tree: TokenTree<$S::TokenStream, $S::Span, $S::Symbol>,
+            ) -> $S::TokenStream;
+            fn ts_concat_trees(
+                base: Option<$S::TokenStream>,
+                trees: Vec<TokenTree<$S::TokenStream, $S::Span, $S::Symbol>>,
+            ) -> $S::TokenStream;
+            fn ts_concat_streams(
+                base: Option<$S::TokenStream>,
+                streams: Vec<$S::TokenStream>,
+            ) -> $S::TokenStream;
+            fn ts_into_trees(
+                stream: $S::TokenStream
+            ) -> Vec<TokenTree<$S::TokenStream, $S::Span, $S::Symbol>>;
 
-                fn span_debug(span: $S::Span) -> String;
-                fn span_parent(span: $S::Span) -> Option<$S::Span>;
-                fn span_source(span: $S::Span) -> $S::Span;
-                fn span_byte_range(span: $S::Span) -> Range<usize>;
-                fn span_start(span: $S::Span) -> $S::Span;
-                fn span_end(span: $S::Span) -> $S::Span;
-                fn span_line(span: $S::Span) -> usize;
-                fn span_column(span: $S::Span) -> usize;
-                fn span_file(span: $S::Span) -> String;
-                fn span_local_file(span: $S::Span) -> Option<String>;
-                fn span_join(span: $S::Span, other: $S::Span) -> Option<$S::Span>;
-                fn span_subspan(span: $S::Span, start: Bound<usize>, end: Bound<usize>) -> Option<$S::Span>;
-                fn span_resolved_at(span: $S::Span, at: $S::Span) -> $S::Span;
-                fn span_source_text(span: $S::Span) -> Option<String>;
-                fn span_save_span(span: $S::Span) -> usize;
-                fn span_recover_proc_macro_span(id: usize) -> $S::Span;
+            fn span_debug(span: $S::Span) -> String;
+            fn span_parent(span: $S::Span) -> Option<$S::Span>;
+            fn span_source(span: $S::Span) -> $S::Span;
+            fn span_byte_range(span: $S::Span) -> Range<usize>;
+            fn span_start(span: $S::Span) -> $S::Span;
+            fn span_end(span: $S::Span) -> $S::Span;
+            fn span_line(span: $S::Span) -> usize;
+            fn span_column(span: $S::Span) -> usize;
+            fn span_file(span: $S::Span) -> String;
+            fn span_local_file(span: $S::Span) -> Option<String>;
+            fn span_join(span: $S::Span, other: $S::Span) -> Option<$S::Span>;
+            fn span_subspan(span: $S::Span, start: Bound<usize>, end: Bound<usize>) -> Option<$S::Span>;
+            fn span_resolved_at(span: $S::Span, at: $S::Span) -> $S::Span;
+            fn span_source_text(span: $S::Span) -> Option<String>;
+            fn span_save_span(span: $S::Span) -> usize;
+            fn span_recover_proc_macro_span(id: usize) -> $S::Span;
 
-                fn symbol_normalize_and_validate_ident(string: &str) -> Result<$S::Symbol, ()>;
-            },
-            TokenStream,
-            Span,
-            Symbol,
+            fn symbol_normalize_and_validate_ident(string: &str) -> Result<$S::Symbol, ()>;
         }
     };
 }
@@ -158,10 +142,7 @@ mod api_tags {
 
     macro_rules! declare_tags {
         (
-            Methods {
-                $(fn $method:ident($($arg:ident: $arg_ty:ty),* $(,)?) $(-> $ret_ty:ty)*;)*
-            },
-            $($name:ident),* $(,)?
+            $(fn $method:ident($($arg:ident: $arg_ty:ty),* $(,)?) $(-> $ret_ty:ty)*;)*
         ) => {
             pub(super) enum Method {
                 $($method),*
@@ -169,7 +150,7 @@ mod api_tags {
             rpc_encode_decode!(enum Method { $($method),* });
         }
     }
-    with_api!(self, self, declare_tags);
+    with_api!(self, declare_tags);
 }
 
 /// Helper to wrap associated types to allow trait impl dispatch.
diff --git a/library/proc_macro/src/bridge/server.rs b/library/proc_macro/src/bridge/server.rs
index b79de9984453..2fed45d3a0ab 100644
--- a/library/proc_macro/src/bridge/server.rs
+++ b/library/proc_macro/src/bridge/server.rs
@@ -5,12 +5,12 @@ use std::marker::PhantomData;
 
 use super::*;
 
-pub(super) struct HandleStore<S: Types> {
+pub(super) struct HandleStore<S: Server> {
     token_stream: handle::OwnedStore<Marked<S::TokenStream, client::TokenStream>>,
     span: handle::InternedStore<Marked<S::Span, client::Span>>,
 }
 
-impl<S: Types> HandleStore<S> {
+impl<S: Server> HandleStore<S> {
     fn new(handle_counters: &'static client::HandleCounters) -> Self {
         HandleStore {
             token_stream: handle::OwnedStore::new(&handle_counters.token_stream),
@@ -19,19 +19,19 @@ impl<S: Types> HandleStore<S> {
     }
 }
 
-impl<S: Types> Encode<HandleStore<S>> for Marked<S::TokenStream, client::TokenStream> {
+impl<S: Server> Encode<HandleStore<S>> for Marked<S::TokenStream, client::TokenStream> {
     fn encode(self, w: &mut Writer, s: &mut HandleStore<S>) {
         s.token_stream.alloc(self).encode(w, s);
     }
 }
 
-impl<S: Types> Decode<'_, '_, HandleStore<S>> for Marked<S::TokenStream, client::TokenStream> {
+impl<S: Server> Decode<'_, '_, HandleStore<S>> for Marked<S::TokenStream, client::TokenStream> {
     fn decode(r: &mut Reader<'_>, s: &mut HandleStore<S>) -> Self {
         s.token_stream.take(handle::Handle::decode(r, &mut ()))
     }
 }
 
-impl<'s, S: Types> Decode<'_, 's, HandleStore<S>>
+impl<'s, S: Server> Decode<'_, 's, HandleStore<S>>
     for &'s Marked<S::TokenStream, client::TokenStream>
 {
     fn decode(r: &mut Reader<'_>, s: &'s mut HandleStore<S>) -> Self {
@@ -39,32 +39,32 @@ impl<'s, S: Types> Decode<'_, 's, HandleStore<S>>
     }
 }
 
-impl<S: Types> Encode<HandleStore<S>> for Marked<S::Span, client::Span> {
+impl<S: Server> Encode<HandleStore<S>> for Marked<S::Span, client::Span> {
     fn encode(self, w: &mut Writer, s: &mut HandleStore<S>) {
         s.span.alloc(self).encode(w, s);
     }
 }
 
-impl<S: Types> Decode<'_, '_, HandleStore<S>> for Marked<S::Span, client::Span> {
+impl<S: Server> Decode<'_, '_, HandleStore<S>> for Marked<S::Span, client::Span> {
     fn decode(r: &mut Reader<'_>, s: &mut HandleStore<S>) -> Self {
         s.span.copy(handle::Handle::decode(r, &mut ()))
     }
 }
 
-pub trait Types {
-    type TokenStream: 'static + Clone;
-    type Span: 'static + Copy + Eq + Hash;
-    type Symbol: 'static;
+struct Dispatcher<S: Server> {
+    handle_store: HandleStore<S>,
+    server: S,
 }
 
-macro_rules! declare_server_traits {
+macro_rules! define_server_dispatcher_impl {
     (
-        Methods {
-            $(fn $method:ident($($arg:ident: $arg_ty:ty),* $(,)?) $(-> $ret_ty:ty)*;)*
-        },
-        $($name:ident),* $(,)?
+        $(fn $method:ident($($arg:ident: $arg_ty:ty),* $(,)?) $(-> $ret_ty:ty)*;)*
     ) => {
-        pub trait Server: Types {
+        pub trait Server {
+            type TokenStream: 'static + Clone;
+            type Span: 'static + Copy + Eq + Hash;
+            type Symbol: 'static;
+
             fn globals(&mut self) -> ExpnGlobals<Self::Span>;
 
             /// Intern a symbol received from RPC
@@ -75,32 +75,21 @@ macro_rules! declare_server_traits {
 
             $(fn $method(&mut self, $($arg: $arg_ty),*) $(-> $ret_ty)?;)*
         }
-    }
-}
-with_api!(Self, self_, declare_server_traits);
 
-struct Dispatcher<S: Types> {
-    handle_store: HandleStore<S>,
-    server: S,
-}
-
-macro_rules! define_dispatcher_impl {
-    (
-        Methods {
-            $(fn $method:ident($($arg:ident: $arg_ty:ty),* $(,)?) $(-> $ret_ty:ty)*;)*
-        },
-        $($name:ident),* $(,)?
-    ) => {
         // FIXME(eddyb) `pub` only for `ExecutionStrategy` below.
         pub trait DispatcherTrait {
             // HACK(eddyb) these are here to allow `Self::$name` to work below.
-            $(type $name;)*
+            type TokenStream;
+            type Span;
+            type Symbol;
 
             fn dispatch(&mut self, buf: Buffer) -> Buffer;
         }
 
         impl<S: Server> DispatcherTrait for Dispatcher<S> {
-            $(type $name = Marked<S::$name, client::$name>;)*
+            type TokenStream = Marked<S::TokenStream, client::TokenStream>;
+            type Span = Marked<S::Span, client::Span>;
+            type Symbol = Marked<S::Symbol, client::Symbol>;
 
             fn dispatch(&mut self, mut buf: Buffer) -> Buffer {
                 let Dispatcher { handle_store, server } = self;
@@ -136,7 +125,7 @@ macro_rules! define_dispatcher_impl {
         }
     }
 }
-with_api!(Self, self_, define_dispatcher_impl);
+with_api!(Self, define_server_dispatcher_impl);
 
 pub trait ExecutionStrategy {
     fn run_bridge_and_client(
diff --git a/src/tools/rust-analyzer/crates/proc-macro-srv/src/dylib.rs b/src/tools/rust-analyzer/crates/proc-macro-srv/src/dylib.rs
index 8680e9180e3a..9a65538675fe 100644
--- a/src/tools/rust-analyzer/crates/proc-macro-srv/src/dylib.rs
+++ b/src/tools/rust-analyzer/crates/proc-macro-srv/src/dylib.rs
@@ -48,7 +48,7 @@ impl Expander {
         callback: Option<ProcMacroClientHandle<'_>>,
     ) -> Result<TokenStream<S>, PanicMessage>
     where
-        <S::Server<'a> as bridge::server::Types>::TokenStream: Default,
+        <S::Server<'a> as bridge::server::Server>::TokenStream: Default,
     {
         self.inner
             .proc_macros
diff --git a/src/tools/rust-analyzer/crates/proc-macro-srv/src/server_impl/rust_analyzer_span.rs b/src/tools/rust-analyzer/crates/proc-macro-srv/src/server_impl/rust_analyzer_span.rs
index ec30630c10bb..eacb100fbc9f 100644
--- a/src/tools/rust-analyzer/crates/proc-macro-srv/src/server_impl/rust_analyzer_span.rs
+++ b/src/tools/rust-analyzer/crates/proc-macro-srv/src/server_impl/rust_analyzer_span.rs
@@ -30,13 +30,11 @@ pub struct RaSpanServer<'a> {
     pub callback: Option<ProcMacroClientHandle<'a>>,
 }
 
-impl server::Types for RaSpanServer<'_> {
+impl server::Server for RaSpanServer<'_> {
     type TokenStream = crate::token_stream::TokenStream<Span>;
     type Span = Span;
     type Symbol = Symbol;
-}
 
-impl server::Server for RaSpanServer<'_> {
     fn globals(&mut self) -> ExpnGlobals<Self::Span> {
         ExpnGlobals {
             def_site: self.def_site,
diff --git a/src/tools/rust-analyzer/crates/proc-macro-srv/src/server_impl/token_id.rs b/src/tools/rust-analyzer/crates/proc-macro-srv/src/server_impl/token_id.rs
index 3bf07290c8c0..70484c4dc28f 100644
--- a/src/tools/rust-analyzer/crates/proc-macro-srv/src/server_impl/token_id.rs
+++ b/src/tools/rust-analyzer/crates/proc-macro-srv/src/server_impl/token_id.rs
@@ -36,13 +36,11 @@ pub struct SpanIdServer<'a> {
     pub callback: Option<ProcMacroClientHandle<'a>>,
 }
 
-impl server::Types for SpanIdServer<'_> {
+impl server::Server for SpanIdServer<'_> {
     type TokenStream = crate::token_stream::TokenStream<Span>;
     type Span = Span;
     type Symbol = Symbol;
-}
 
-impl server::Server for SpanIdServer<'_> {
     fn globals(&mut self) -> ExpnGlobals<Self::Span> {
         ExpnGlobals {
             def_site: self.def_site,

From 5fef797f6e8360b2457cb9a4133f59effb9c5d65 Mon Sep 17 00:00:00 2001
From: cyrgani <ansgar.w.zielke@gmail.com>
Date: Mon, 26 Jan 2026 14:00:39 +0000
Subject: [PATCH 35/97] inline `Writer` and `Reader` type aliases

---
 library/proc_macro/src/bridge/client.rs | 10 ++--
 library/proc_macro/src/bridge/mod.rs    |  5 +-
 library/proc_macro/src/bridge/rpc.rs    | 64 ++++++++++++-------------
 library/proc_macro/src/bridge/server.rs | 10 ++--
 library/proc_macro/src/bridge/symbol.rs |  8 ++--
 5 files changed, 48 insertions(+), 49 deletions(-)

diff --git a/library/proc_macro/src/bridge/client.rs b/library/proc_macro/src/bridge/client.rs
index 381c8502c853..83a3b21e3548 100644
--- a/library/proc_macro/src/bridge/client.rs
+++ b/library/proc_macro/src/bridge/client.rs
@@ -30,19 +30,19 @@ impl Drop for TokenStream {
 }
 
 impl<S> Encode<S> for TokenStream {
-    fn encode(self, w: &mut Writer, s: &mut S) {
+    fn encode(self, w: &mut Buffer, s: &mut S) {
         mem::ManuallyDrop::new(self).handle.encode(w, s);
     }
 }
 
 impl<S> Encode<S> for &TokenStream {
-    fn encode(self, w: &mut Writer, s: &mut S) {
+    fn encode(self, w: &mut Buffer, s: &mut S) {
         self.handle.encode(w, s);
     }
 }
 
 impl<S> Decode<'_, '_, S> for TokenStream {
-    fn decode(r: &mut Reader<'_>, s: &mut S) -> Self {
+    fn decode(r: &mut &[u8], s: &mut S) -> Self {
         TokenStream { handle: handle::Handle::decode(r, s) }
     }
 }
@@ -56,13 +56,13 @@ impl !Send for Span {}
 impl !Sync for Span {}
 
 impl<S> Encode<S> for Span {
-    fn encode(self, w: &mut Writer, s: &mut S) {
+    fn encode(self, w: &mut Buffer, s: &mut S) {
         self.handle.encode(w, s);
     }
 }
 
 impl<S> Decode<'_, '_, S> for Span {
-    fn decode(r: &mut Reader<'_>, s: &mut S) -> Self {
+    fn decode(r: &mut &[u8], s: &mut S) -> Self {
         Span { handle: handle::Handle::decode(r, s) }
     }
 }
diff --git a/library/proc_macro/src/bridge/mod.rs b/library/proc_macro/src/bridge/mod.rs
index f454861be4ed..006aa5f973fc 100644
--- a/library/proc_macro/src/bridge/mod.rs
+++ b/library/proc_macro/src/bridge/mod.rs
@@ -113,7 +113,7 @@ mod symbol;
 
 use buffer::Buffer;
 pub use rpc::PanicMessage;
-use rpc::{Decode, Encode, Reader, Writer};
+use rpc::{Decode, Encode};
 
 /// Configuration for establishing an active connection between a server and a
 /// client.  The server creates the bridge config (`run_server` in `server.rs`),
@@ -138,7 +138,8 @@ impl !Sync for BridgeConfig<'_> {}
 #[forbid(unsafe_code)]
 #[allow(non_camel_case_types)]
 mod api_tags {
-    use super::rpc::{Decode, Encode, Reader, Writer};
+    use super::buffer::Buffer;
+    use super::rpc::{Decode, Encode};
 
     macro_rules! declare_tags {
         (
diff --git a/library/proc_macro/src/bridge/rpc.rs b/library/proc_macro/src/bridge/rpc.rs
index ed67674a74ab..254b176e19c5 100644
--- a/library/proc_macro/src/bridge/rpc.rs
+++ b/library/proc_macro/src/bridge/rpc.rs
@@ -4,28 +4,26 @@ use std::any::Any;
 use std::io::Write;
 use std::num::NonZero;
 
-pub(super) type Writer = super::buffer::Buffer;
+use super::buffer::Buffer;
 
 pub(super) trait Encode<S>: Sized {
-    fn encode(self, w: &mut Writer, s: &mut S);
+    fn encode(self, w: &mut Buffer, s: &mut S);
 }
 
-pub(super) type Reader<'a> = &'a [u8];
-
 pub(super) trait Decode<'a, 's, S>: Sized {
-    fn decode(r: &mut Reader<'a>, s: &'s mut S) -> Self;
+    fn decode(r: &mut &'a [u8], s: &'s mut S) -> Self;
 }
 
 macro_rules! rpc_encode_decode {
     (le $ty:ty) => {
         impl<S> Encode<S> for $ty {
-            fn encode(self, w: &mut Writer, _: &mut S) {
+            fn encode(self, w: &mut Buffer, _: &mut S) {
                 w.extend_from_array(&self.to_le_bytes());
             }
         }
 
         impl<S> Decode<'_, '_, S> for $ty {
-            fn decode(r: &mut Reader<'_>, _: &mut S) -> Self {
+            fn decode(r: &mut &[u8], _: &mut S) -> Self {
                 const N: usize = size_of::<$ty>();
 
                 let mut bytes = [0; N];
@@ -38,7 +36,7 @@ macro_rules! rpc_encode_decode {
     };
     (struct $name:ident $(<$($T:ident),+>)? { $($field:ident),* $(,)? }) => {
         impl<S, $($($T: Encode<S>),+)?> Encode<S> for $name $(<$($T),+>)? {
-            fn encode(self, w: &mut Writer, s: &mut S) {
+            fn encode(self, w: &mut Buffer, s: &mut S) {
                 $(self.$field.encode(w, s);)*
             }
         }
@@ -46,7 +44,7 @@ macro_rules! rpc_encode_decode {
         impl<'a, S, $($($T: for<'s> Decode<'a, 's, S>),+)?> Decode<'a, '_, S>
             for $name $(<$($T),+>)?
         {
-            fn decode(r: &mut Reader<'a>, s: &mut S) -> Self {
+            fn decode(r: &mut &'a [u8], s: &mut S) -> Self {
                 $name {
                     $($field: Decode::decode(r, s)),*
                 }
@@ -55,7 +53,7 @@ macro_rules! rpc_encode_decode {
     };
     (enum $name:ident $(<$($T:ident),+>)? { $($variant:ident $(($field:ident))*),* $(,)? }) => {
         impl<S, $($($T: Encode<S>),+)?> Encode<S> for $name $(<$($T),+>)? {
-            fn encode(self, w: &mut Writer, s: &mut S) {
+            fn encode(self, w: &mut Buffer, s: &mut S) {
                 // HACK(eddyb): `Tag` enum duplicated between the
                 // two impls as there's no other place to stash it.
                 #[repr(u8)] enum Tag { $($variant),* }
@@ -72,7 +70,7 @@ macro_rules! rpc_encode_decode {
         impl<'a, S, $($($T: for<'s> Decode<'a, 's, S>),+)?> Decode<'a, '_, S>
             for $name $(<$($T),+>)?
         {
-            fn decode(r: &mut Reader<'a>, s: &mut S) -> Self {
+            fn decode(r: &mut &'a [u8], s: &mut S) -> Self {
                 // HACK(eddyb): `Tag` enum duplicated between the
                 // two impls as there's no other place to stash it.
                 #[allow(non_upper_case_globals)]
@@ -95,21 +93,21 @@ macro_rules! rpc_encode_decode {
 }
 
 impl<S> Encode<S> for () {
-    fn encode(self, _: &mut Writer, _: &mut S) {}
+    fn encode(self, _: &mut Buffer, _: &mut S) {}
 }
 
 impl<S> Decode<'_, '_, S> for () {
-    fn decode(_: &mut Reader<'_>, _: &mut S) -> Self {}
+    fn decode(_: &mut &[u8], _: &mut S) -> Self {}
 }
 
 impl<S> Encode<S> for u8 {
-    fn encode(self, w: &mut Writer, _: &mut S) {
+    fn encode(self, w: &mut Buffer, _: &mut S) {
         w.push(self);
     }
 }
 
 impl<S> Decode<'_, '_, S> for u8 {
-    fn decode(r: &mut Reader<'_>, _: &mut S) -> Self {
+    fn decode(r: &mut &[u8], _: &mut S) -> Self {
         let x = r[0];
         *r = &r[1..];
         x
@@ -120,13 +118,13 @@ rpc_encode_decode!(le u32);
 rpc_encode_decode!(le usize);
 
 impl<S> Encode<S> for bool {
-    fn encode(self, w: &mut Writer, s: &mut S) {
+    fn encode(self, w: &mut Buffer, s: &mut S) {
         (self as u8).encode(w, s);
     }
 }
 
 impl<S> Decode<'_, '_, S> for bool {
-    fn decode(r: &mut Reader<'_>, s: &mut S) -> Self {
+    fn decode(r: &mut &[u8], s: &mut S) -> Self {
         match u8::decode(r, s) {
             0 => false,
             1 => true,
@@ -136,31 +134,31 @@ impl<S> Decode<'_, '_, S> for bool {
 }
 
 impl<S> Encode<S> for char {
-    fn encode(self, w: &mut Writer, s: &mut S) {
+    fn encode(self, w: &mut Buffer, s: &mut S) {
         (self as u32).encode(w, s);
     }
 }
 
 impl<S> Decode<'_, '_, S> for char {
-    fn decode(r: &mut Reader<'_>, s: &mut S) -> Self {
+    fn decode(r: &mut &[u8], s: &mut S) -> Self {
         char::from_u32(u32::decode(r, s)).unwrap()
     }
 }
 
 impl<S> Encode<S> for NonZero<u32> {
-    fn encode(self, w: &mut Writer, s: &mut S) {
+    fn encode(self, w: &mut Buffer, s: &mut S) {
         self.get().encode(w, s);
     }
 }
 
 impl<S> Decode<'_, '_, S> for NonZero<u32> {
-    fn decode(r: &mut Reader<'_>, s: &mut S) -> Self {
+    fn decode(r: &mut &[u8], s: &mut S) -> Self {
         Self::new(u32::decode(r, s)).unwrap()
     }
 }
 
 impl<S, A: Encode<S>, B: Encode<S>> Encode<S> for (A, B) {
-    fn encode(self, w: &mut Writer, s: &mut S) {
+    fn encode(self, w: &mut Buffer, s: &mut S) {
         self.0.encode(w, s);
         self.1.encode(w, s);
     }
@@ -169,20 +167,20 @@ impl<S, A: Encode<S>, B: Encode<S>> Encode<S> for (A, B) {
 impl<'a, S, A: for<'s> Decode<'a, 's, S>, B: for<'s> Decode<'a, 's, S>> Decode<'a, '_, S>
     for (A, B)
 {
-    fn decode(r: &mut Reader<'a>, s: &mut S) -> Self {
+    fn decode(r: &mut &'a [u8], s: &mut S) -> Self {
         (Decode::decode(r, s), Decode::decode(r, s))
     }
 }
 
 impl<S> Encode<S> for &[u8] {
-    fn encode(self, w: &mut Writer, s: &mut S) {
+    fn encode(self, w: &mut Buffer, s: &mut S) {
         self.len().encode(w, s);
         w.write_all(self).unwrap();
     }
 }
 
 impl<'a, S> Decode<'a, '_, S> for &'a [u8] {
-    fn decode(r: &mut Reader<'a>, s: &mut S) -> Self {
+    fn decode(r: &mut &'a [u8], s: &mut S) -> Self {
         let len = usize::decode(r, s);
         let xs = &r[..len];
         *r = &r[len..];
@@ -191,31 +189,31 @@ impl<'a, S> Decode<'a, '_, S> for &'a [u8] {
 }
 
 impl<S> Encode<S> for &str {
-    fn encode(self, w: &mut Writer, s: &mut S) {
+    fn encode(self, w: &mut Buffer, s: &mut S) {
         self.as_bytes().encode(w, s);
     }
 }
 
 impl<'a, S> Decode<'a, '_, S> for &'a str {
-    fn decode(r: &mut Reader<'a>, s: &mut S) -> Self {
+    fn decode(r: &mut &'a [u8], s: &mut S) -> Self {
         str::from_utf8(<&[u8]>::decode(r, s)).unwrap()
     }
 }
 
 impl<S> Encode<S> for String {
-    fn encode(self, w: &mut Writer, s: &mut S) {
+    fn encode(self, w: &mut Buffer, s: &mut S) {
         self[..].encode(w, s);
     }
 }
 
 impl<S> Decode<'_, '_, S> for String {
-    fn decode(r: &mut Reader<'_>, s: &mut S) -> Self {
+    fn decode(r: &mut &[u8], s: &mut S) -> Self {
         <&str>::decode(r, s).to_string()
     }
 }
 
 impl<S, T: Encode<S>> Encode<S> for Vec<T> {
-    fn encode(self, w: &mut Writer, s: &mut S) {
+    fn encode(self, w: &mut Buffer, s: &mut S) {
         self.len().encode(w, s);
         for x in self {
             x.encode(w, s);
@@ -224,7 +222,7 @@ impl<S, T: Encode<S>> Encode<S> for Vec<T> {
 }
 
 impl<'a, S, T: for<'s> Decode<'a, 's, S>> Decode<'a, '_, S> for Vec<T> {
-    fn decode(r: &mut Reader<'a>, s: &mut S) -> Self {
+    fn decode(r: &mut &'a [u8], s: &mut S) -> Self {
         let len = usize::decode(r, s);
         let mut vec = Vec::with_capacity(len);
         for _ in 0..len {
@@ -278,13 +276,13 @@ impl PanicMessage {
 }
 
 impl<S> Encode<S> for PanicMessage {
-    fn encode(self, w: &mut Writer, s: &mut S) {
+    fn encode(self, w: &mut Buffer, s: &mut S) {
         self.as_str().encode(w, s);
     }
 }
 
 impl<S> Decode<'_, '_, S> for PanicMessage {
-    fn decode(r: &mut Reader<'_>, s: &mut S) -> Self {
+    fn decode(r: &mut &[u8], s: &mut S) -> Self {
         match Option::<String>::decode(r, s) {
             Some(s) => PanicMessage::String(s),
             None => PanicMessage::Unknown,
diff --git a/library/proc_macro/src/bridge/server.rs b/library/proc_macro/src/bridge/server.rs
index 2fed45d3a0ab..8f31d7aa9f55 100644
--- a/library/proc_macro/src/bridge/server.rs
+++ b/library/proc_macro/src/bridge/server.rs
@@ -20,13 +20,13 @@ impl<S: Server> HandleStore<S> {
 }
 
 impl<S: Server> Encode<HandleStore<S>> for Marked<S::TokenStream, client::TokenStream> {
-    fn encode(self, w: &mut Writer, s: &mut HandleStore<S>) {
+    fn encode(self, w: &mut Buffer, s: &mut HandleStore<S>) {
         s.token_stream.alloc(self).encode(w, s);
     }
 }
 
 impl<S: Server> Decode<'_, '_, HandleStore<S>> for Marked<S::TokenStream, client::TokenStream> {
-    fn decode(r: &mut Reader<'_>, s: &mut HandleStore<S>) -> Self {
+    fn decode(r: &mut &[u8], s: &mut HandleStore<S>) -> Self {
         s.token_stream.take(handle::Handle::decode(r, &mut ()))
     }
 }
@@ -34,19 +34,19 @@ impl<S: Server> Decode<'_, '_, HandleStore<S>> for Marked<S::TokenStream, client
 impl<'s, S: Server> Decode<'_, 's, HandleStore<S>>
     for &'s Marked<S::TokenStream, client::TokenStream>
 {
-    fn decode(r: &mut Reader<'_>, s: &'s mut HandleStore<S>) -> Self {
+    fn decode(r: &mut &[u8], s: &'s mut HandleStore<S>) -> Self {
         &s.token_stream[handle::Handle::decode(r, &mut ())]
     }
 }
 
 impl<S: Server> Encode<HandleStore<S>> for Marked<S::Span, client::Span> {
-    fn encode(self, w: &mut Writer, s: &mut HandleStore<S>) {
+    fn encode(self, w: &mut Buffer, s: &mut HandleStore<S>) {
         s.span.alloc(self).encode(w, s);
     }
 }
 
 impl<S: Server> Decode<'_, '_, HandleStore<S>> for Marked<S::Span, client::Span> {
-    fn decode(r: &mut Reader<'_>, s: &mut HandleStore<S>) -> Self {
+    fn decode(r: &mut &[u8], s: &mut HandleStore<S>) -> Self {
         s.span.copy(handle::Handle::decode(r, &mut ()))
     }
 }
diff --git a/library/proc_macro/src/bridge/symbol.rs b/library/proc_macro/src/bridge/symbol.rs
index edba142bad72..02b1d351ac16 100644
--- a/library/proc_macro/src/bridge/symbol.rs
+++ b/library/proc_macro/src/bridge/symbol.rs
@@ -94,25 +94,25 @@ impl fmt::Display for Symbol {
 }
 
 impl<S> Encode<S> for Symbol {
-    fn encode(self, w: &mut Writer, s: &mut S) {
+    fn encode(self, w: &mut Buffer, s: &mut S) {
         self.with(|sym| sym.encode(w, s))
     }
 }
 
 impl<S: server::Server> Decode<'_, '_, server::HandleStore<S>> for Marked<S::Symbol, Symbol> {
-    fn decode(r: &mut Reader<'_>, s: &mut server::HandleStore<S>) -> Self {
+    fn decode(r: &mut &[u8], s: &mut server::HandleStore<S>) -> Self {
         Mark::mark(S::intern_symbol(<&str>::decode(r, s)))
     }
 }
 
 impl<S: server::Server> Encode<server::HandleStore<S>> for Marked<S::Symbol, Symbol> {
-    fn encode(self, w: &mut Writer, s: &mut server::HandleStore<S>) {
+    fn encode(self, w: &mut Buffer, s: &mut server::HandleStore<S>) {
         S::with_symbol_string(&self.unmark(), |sym| sym.encode(w, s))
     }
 }
 
 impl<S> Decode<'_, '_, S> for Symbol {
-    fn decode(r: &mut Reader<'_>, s: &mut S) -> Self {
+    fn decode(r: &mut &[u8], s: &mut S) -> Self {
         Symbol::new(<&str>::decode(r, s))
     }
 }

From 8d6b2f6a49c02456002094c069ac5a4d266625d7 Mon Sep 17 00:00:00 2001
From: zakie <realzzaekkii@gmail.com>
Date: Mon, 26 Jan 2026 23:36:26 +0900
Subject: [PATCH 36/97] docs: fix broken Xtensa installation link

---
 src/doc/rustc/src/platform-support/xtensa.md | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/doc/rustc/src/platform-support/xtensa.md b/src/doc/rustc/src/platform-support/xtensa.md
index 8592ce7eda9d..39bcc02355cb 100644
--- a/src/doc/rustc/src/platform-support/xtensa.md
+++ b/src/doc/rustc/src/platform-support/xtensa.md
@@ -24,4 +24,4 @@ Xtensa targets that support `std` are documented in the [ESP-IDF platform suppor
 
 ## Building the targets
 
-The targets can be built by installing the [Xtensa enabled Rust channel](https://github.com/esp-rs/rust/). See instructions in the [RISC-V and Xtensa Targets section of The Rust on ESP Book](https://docs.espressif.com/projects/rust/book/installation/index.html).
+The targets can be built by installing the [Xtensa enabled Rust channel](https://github.com/esp-rs/rust/). See instructions in the [RISC-V and Xtensa Targets section of The Rust on ESP Book](https://docs.espressif.com/projects/rust/book/getting-started/toolchain.html).

From f8d05b6c855f64e11dc9bdec4db21bd4c3c6a969 Mon Sep 17 00:00:00 2001
From: cyrgani <ansgar.w.zielke@gmail.com>
Date: Mon, 26 Jan 2026 14:43:50 +0000
Subject: [PATCH 37/97] flatten the `api_tags` module

---
 library/proc_macro/src/bridge/client.rs |  2 +-
 library/proc_macro/src/bridge/mod.rs    | 24 +++++++++---------------
 library/proc_macro/src/bridge/rpc.rs    |  6 ++++--
 library/proc_macro/src/bridge/server.rs |  4 ++--
 4 files changed, 16 insertions(+), 20 deletions(-)

diff --git a/library/proc_macro/src/bridge/client.rs b/library/proc_macro/src/bridge/client.rs
index 83a3b21e3548..8f4a79b389f6 100644
--- a/library/proc_macro/src/bridge/client.rs
+++ b/library/proc_macro/src/bridge/client.rs
@@ -106,7 +106,7 @@ macro_rules! define_client_side {
                     let mut buf = bridge.cached_buffer.take();
 
                     buf.clear();
-                    api_tags::Method::$method.encode(&mut buf, &mut ());
+                    ApiTags::$method.encode(&mut buf, &mut ());
                     $($arg.encode(&mut buf, &mut ());)*
 
                     buf = bridge.dispatch.call(buf);
diff --git a/library/proc_macro/src/bridge/mod.rs b/library/proc_macro/src/bridge/mod.rs
index 006aa5f973fc..cf6ffd86f414 100644
--- a/library/proc_macro/src/bridge/mod.rs
+++ b/library/proc_macro/src/bridge/mod.rs
@@ -135,24 +135,18 @@ pub struct BridgeConfig<'a> {
 impl !Send for BridgeConfig<'_> {}
 impl !Sync for BridgeConfig<'_> {}
 
-#[forbid(unsafe_code)]
-#[allow(non_camel_case_types)]
-mod api_tags {
-    use super::buffer::Buffer;
-    use super::rpc::{Decode, Encode};
-
-    macro_rules! declare_tags {
-        (
-            $(fn $method:ident($($arg:ident: $arg_ty:ty),* $(,)?) $(-> $ret_ty:ty)*;)*
-        ) => {
-            pub(super) enum Method {
-                $($method),*
-            }
-            rpc_encode_decode!(enum Method { $($method),* });
+macro_rules! declare_tags {
+    (
+        $(fn $method:ident($($arg:ident: $arg_ty:ty),* $(,)?) $(-> $ret_ty:ty)*;)*
+    ) => {
+        #[allow(non_camel_case_types)]
+        pub(super) enum ApiTags {
+            $($method),*
         }
+        rpc_encode_decode!(enum ApiTags { $($method),* });
     }
-    with_api!(self, declare_tags);
 }
+with_api!(self, declare_tags);
 
 /// Helper to wrap associated types to allow trait impl dispatch.
 /// That is, normally a pair of impls for `T::Foo` and `T::Bar`
diff --git a/library/proc_macro/src/bridge/rpc.rs b/library/proc_macro/src/bridge/rpc.rs
index 254b176e19c5..5786c62d9464 100644
--- a/library/proc_macro/src/bridge/rpc.rs
+++ b/library/proc_macro/src/bridge/rpc.rs
@@ -56,7 +56,9 @@ macro_rules! rpc_encode_decode {
             fn encode(self, w: &mut Buffer, s: &mut S) {
                 // HACK(eddyb): `Tag` enum duplicated between the
                 // two impls as there's no other place to stash it.
-                #[repr(u8)] enum Tag { $($variant),* }
+                #[allow(non_camel_case_types)]
+                #[repr(u8)]
+                enum Tag { $($variant),* }
 
                 match self {
                     $($name::$variant $(($field))* => {
@@ -73,7 +75,7 @@ macro_rules! rpc_encode_decode {
             fn decode(r: &mut &'a [u8], s: &mut S) -> Self {
                 // HACK(eddyb): `Tag` enum duplicated between the
                 // two impls as there's no other place to stash it.
-                #[allow(non_upper_case_globals)]
+                #[allow(non_upper_case_globals, non_camel_case_types)]
                 mod tag {
                     #[repr(u8)] enum Tag { $($variant),* }
 
diff --git a/library/proc_macro/src/bridge/server.rs b/library/proc_macro/src/bridge/server.rs
index 8f31d7aa9f55..f477fa28798d 100644
--- a/library/proc_macro/src/bridge/server.rs
+++ b/library/proc_macro/src/bridge/server.rs
@@ -95,8 +95,8 @@ macro_rules! define_server_dispatcher_impl {
                 let Dispatcher { handle_store, server } = self;
 
                 let mut reader = &buf[..];
-                match api_tags::Method::decode(&mut reader, &mut ()) {
-                    $(api_tags::Method::$method => {
+                match ApiTags::decode(&mut reader, &mut ()) {
+                    $(ApiTags::$method => {
                         let mut call_method = || {
                             $(let $arg = <$arg_ty>::decode(&mut reader, handle_store).unmark();)*
                             let r = server.$method($($arg),*);

From d5328c545a0cad33053369ddbc0e5f27aa2924aa Mon Sep 17 00:00:00 2001
From: cyrgani <ansgar.w.zielke@gmail.com>
Date: Mon, 26 Jan 2026 14:58:29 +0000
Subject: [PATCH 38/97] introduce `MarkedX` type aliases

---
 library/proc_macro/src/bridge/server.rs | 43 +++++++++++--------------
 library/proc_macro/src/bridge/symbol.rs |  4 +--
 2 files changed, 21 insertions(+), 26 deletions(-)

diff --git a/library/proc_macro/src/bridge/server.rs b/library/proc_macro/src/bridge/server.rs
index f477fa28798d..073ddb554994 100644
--- a/library/proc_macro/src/bridge/server.rs
+++ b/library/proc_macro/src/bridge/server.rs
@@ -6,8 +6,8 @@ use std::marker::PhantomData;
 use super::*;
 
 pub(super) struct HandleStore<S: Server> {
-    token_stream: handle::OwnedStore<Marked<S::TokenStream, client::TokenStream>>,
-    span: handle::InternedStore<Marked<S::Span, client::Span>>,
+    token_stream: handle::OwnedStore<MarkedTokenStream<S>>,
+    span: handle::InternedStore<MarkedSpan<S>>,
 }
 
 impl<S: Server> HandleStore<S> {
@@ -19,33 +19,35 @@ impl<S: Server> HandleStore<S> {
     }
 }
 
-impl<S: Server> Encode<HandleStore<S>> for Marked<S::TokenStream, client::TokenStream> {
+pub(super) type MarkedTokenStream<S> = Marked<<S as Server>::TokenStream, client::TokenStream>;
+pub(super) type MarkedSpan<S> = Marked<<S as Server>::Span, client::Span>;
+pub(super) type MarkedSymbol<S> = Marked<<S as Server>::Symbol, client::Symbol>;
+
+impl<S: Server> Encode<HandleStore<S>> for MarkedTokenStream<S> {
     fn encode(self, w: &mut Buffer, s: &mut HandleStore<S>) {
         s.token_stream.alloc(self).encode(w, s);
     }
 }
 
-impl<S: Server> Decode<'_, '_, HandleStore<S>> for Marked<S::TokenStream, client::TokenStream> {
+impl<S: Server> Decode<'_, '_, HandleStore<S>> for MarkedTokenStream<S> {
     fn decode(r: &mut &[u8], s: &mut HandleStore<S>) -> Self {
         s.token_stream.take(handle::Handle::decode(r, &mut ()))
     }
 }
 
-impl<'s, S: Server> Decode<'_, 's, HandleStore<S>>
-    for &'s Marked<S::TokenStream, client::TokenStream>
-{
+impl<'s, S: Server> Decode<'_, 's, HandleStore<S>> for &'s MarkedTokenStream<S> {
     fn decode(r: &mut &[u8], s: &'s mut HandleStore<S>) -> Self {
         &s.token_stream[handle::Handle::decode(r, &mut ())]
     }
 }
 
-impl<S: Server> Encode<HandleStore<S>> for Marked<S::Span, client::Span> {
+impl<S: Server> Encode<HandleStore<S>> for MarkedSpan<S> {
     fn encode(self, w: &mut Buffer, s: &mut HandleStore<S>) {
         s.span.alloc(self).encode(w, s);
     }
 }
 
-impl<S: Server> Decode<'_, '_, HandleStore<S>> for Marked<S::Span, client::Span> {
+impl<S: Server> Decode<'_, '_, HandleStore<S>> for MarkedSpan<S> {
     fn decode(r: &mut &[u8], s: &mut HandleStore<S>) -> Self {
         s.span.copy(handle::Handle::decode(r, &mut ()))
     }
@@ -87,9 +89,9 @@ macro_rules! define_server_dispatcher_impl {
         }
 
         impl<S: Server> DispatcherTrait for Dispatcher<S> {
-            type TokenStream = Marked<S::TokenStream, client::TokenStream>;
-            type Span = Marked<S::Span, client::Span>;
-            type Symbol = Marked<S::Symbol, client::Symbol>;
+            type TokenStream = MarkedTokenStream<S>;
+            type Span = MarkedSpan<S>;
+            type Symbol = MarkedSymbol<S>;
 
             fn dispatch(&mut self, mut buf: Buffer) -> Buffer {
                 let Dispatcher { handle_store, server } = self;
@@ -292,7 +294,7 @@ fn run_server<
     let globals = dispatcher.server.globals();
 
     let mut buf = Buffer::new();
-    (<ExpnGlobals<Marked<S::Span, client::Span>> as Mark>::mark(globals), input)
+    (<ExpnGlobals<MarkedSpan<S>> as Mark>::mark(globals), input)
         .encode(&mut buf, &mut dispatcher.handle_store);
 
     buf = strategy.run_bridge_and_client(&mut dispatcher, buf, run_client, force_show_panics);
@@ -317,13 +319,11 @@ impl client::Client<crate::TokenStream, crate::TokenStream> {
             strategy,
             handle_counters,
             server,
-            <Marked<S::TokenStream, client::TokenStream>>::mark(input),
+            <MarkedTokenStream<S>>::mark(input),
             run,
             force_show_panics,
         )
-        .map(|s| {
-            <Option<Marked<S::TokenStream, client::TokenStream>>>::unmark(s).unwrap_or_default()
-        })
+        .map(|s| <Option<MarkedTokenStream<S>>>::unmark(s).unwrap_or_default())
     }
 }
 
@@ -345,15 +345,10 @@ impl client::Client<(crate::TokenStream, crate::TokenStream), crate::TokenStream
             strategy,
             handle_counters,
             server,
-            (
-                <Marked<S::TokenStream, client::TokenStream>>::mark(input),
-                <Marked<S::TokenStream, client::TokenStream>>::mark(input2),
-            ),
+            (<MarkedTokenStream<S>>::mark(input), <MarkedTokenStream<S>>::mark(input2)),
             run,
             force_show_panics,
         )
-        .map(|s| {
-            <Option<Marked<S::TokenStream, client::TokenStream>>>::unmark(s).unwrap_or_default()
-        })
+        .map(|s| <Option<MarkedTokenStream<S>>>::unmark(s).unwrap_or_default())
     }
 }
diff --git a/library/proc_macro/src/bridge/symbol.rs b/library/proc_macro/src/bridge/symbol.rs
index 02b1d351ac16..2a04f7d808bd 100644
--- a/library/proc_macro/src/bridge/symbol.rs
+++ b/library/proc_macro/src/bridge/symbol.rs
@@ -99,13 +99,13 @@ impl<S> Encode<S> for Symbol {
     }
 }
 
-impl<S: server::Server> Decode<'_, '_, server::HandleStore<S>> for Marked<S::Symbol, Symbol> {
+impl<S: server::Server> Decode<'_, '_, server::HandleStore<S>> for server::MarkedSymbol<S> {
     fn decode(r: &mut &[u8], s: &mut server::HandleStore<S>) -> Self {
         Mark::mark(S::intern_symbol(<&str>::decode(r, s)))
     }
 }
 
-impl<S: server::Server> Encode<server::HandleStore<S>> for Marked<S::Symbol, Symbol> {
+impl<S: server::Server> Encode<server::HandleStore<S>> for server::MarkedSymbol<S> {
     fn encode(self, w: &mut Buffer, s: &mut server::HandleStore<S>) {
         S::with_symbol_string(&self.unmark(), |sym| sym.encode(w, s))
     }

From 356107e0b46182a080ab4876282cebbb97e33b1a Mon Sep 17 00:00:00 2001
From: cyrgani <ansgar.w.zielke@gmail.com>
Date: Mon, 26 Jan 2026 14:27:18 +0000
Subject: [PATCH 39/97] remove some unneeded impls

---
 library/proc_macro/src/bridge/mod.rs | 17 +------------
 library/proc_macro/src/bridge/rpc.rs | 37 ++++++----------------------
 2 files changed, 8 insertions(+), 46 deletions(-)

diff --git a/library/proc_macro/src/bridge/mod.rs b/library/proc_macro/src/bridge/mod.rs
index cf6ffd86f414..97e36a3d70c1 100644
--- a/library/proc_macro/src/bridge/mod.rs
+++ b/library/proc_macro/src/bridge/mod.rs
@@ -13,7 +13,7 @@ use std::ops::{Bound, Range};
 use std::sync::Once;
 use std::{fmt, marker, mem, panic, thread};
 
-use crate::{Delimiter, Level, Spacing};
+use crate::{Delimiter, Level};
 
 /// Higher-order macro describing the server RPC API, allowing automatic
 /// generation of type-safe Rust APIs, both client-side and server-side.
@@ -187,12 +187,6 @@ impl<'a, T, M> Unmark for &'a Marked<T, M> {
         &self.value
     }
 }
-impl<'a, T, M> Unmark for &'a mut Marked<T, M> {
-    type Unmarked = &'a mut T;
-    fn unmark(self) -> Self::Unmarked {
-        &mut self.value
-    }
-}
 
 impl<T: Mark> Mark for Vec<T> {
     type Unmarked = Vec<T::Unmarked>;
@@ -230,8 +224,6 @@ macro_rules! mark_noop {
 mark_noop! {
     (),
     bool,
-    char,
-    &'_ [u8],
     &'_ str,
     String,
     u8,
@@ -239,7 +231,6 @@ mark_noop! {
     Delimiter,
     LitKind,
     Level,
-    Spacing,
 }
 
 rpc_encode_decode!(
@@ -258,12 +249,6 @@ rpc_encode_decode!(
         Help,
     }
 );
-rpc_encode_decode!(
-    enum Spacing {
-        Alone,
-        Joint,
-    }
-);
 
 #[derive(Copy, Clone, Eq, PartialEq, Debug)]
 pub enum LitKind {
diff --git a/library/proc_macro/src/bridge/rpc.rs b/library/proc_macro/src/bridge/rpc.rs
index 5786c62d9464..63329c8c0260 100644
--- a/library/proc_macro/src/bridge/rpc.rs
+++ b/library/proc_macro/src/bridge/rpc.rs
@@ -135,18 +135,6 @@ impl<S> Decode<'_, '_, S> for bool {
     }
 }
 
-impl<S> Encode<S> for char {
-    fn encode(self, w: &mut Buffer, s: &mut S) {
-        (self as u32).encode(w, s);
-    }
-}
-
-impl<S> Decode<'_, '_, S> for char {
-    fn decode(r: &mut &[u8], s: &mut S) -> Self {
-        char::from_u32(u32::decode(r, s)).unwrap()
-    }
-}
-
 impl<S> Encode<S> for NonZero<u32> {
     fn encode(self, w: &mut Buffer, s: &mut S) {
         self.get().encode(w, s);
@@ -174,31 +162,20 @@ impl<'a, S, A: for<'s> Decode<'a, 's, S>, B: for<'s> Decode<'a, 's, S>> Decode<'
     }
 }
 
-impl<S> Encode<S> for &[u8] {
-    fn encode(self, w: &mut Buffer, s: &mut S) {
-        self.len().encode(w, s);
-        w.write_all(self).unwrap();
-    }
-}
-
-impl<'a, S> Decode<'a, '_, S> for &'a [u8] {
-    fn decode(r: &mut &'a [u8], s: &mut S) -> Self {
-        let len = usize::decode(r, s);
-        let xs = &r[..len];
-        *r = &r[len..];
-        xs
-    }
-}
-
 impl<S> Encode<S> for &str {
     fn encode(self, w: &mut Buffer, s: &mut S) {
-        self.as_bytes().encode(w, s);
+        let bytes = self.as_bytes();
+        bytes.len().encode(w, s);
+        w.write_all(bytes).unwrap();
     }
 }
 
 impl<'a, S> Decode<'a, '_, S> for &'a str {
     fn decode(r: &mut &'a [u8], s: &mut S) -> Self {
-        str::from_utf8(<&[u8]>::decode(r, s)).unwrap()
+        let len = usize::decode(r, s);
+        let xs = &r[..len];
+        *r = &r[len..];
+        str::from_utf8(xs).unwrap()
     }
 }
 

From 21ebd03e5ec9c62c1b582adb90d179aaec504d7b Mon Sep 17 00:00:00 2001
From: Guillaume Gomez <guillaume1.gomez@gmail.com>
Date: Mon, 26 Jan 2026 16:18:36 +0100
Subject: [PATCH 40/97] Try to reduce rustdoc GUI tests flakyness

---
 package.json                 | 2 +-
 tests/rustdoc-gui/utils.goml | 1 +
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/package.json b/package.json
index 0cba589d23f5..1fe87b181669 100644
--- a/package.json
+++ b/package.json
@@ -1,6 +1,6 @@
 {
   "dependencies": {
-    "browser-ui-test": "^0.23.1",
+    "browser-ui-test": "^0.23.2",
     "es-check": "^9.4.4",
     "eslint": "^8.57.1",
     "typescript": "^5.8.3"
diff --git a/tests/rustdoc-gui/utils.goml b/tests/rustdoc-gui/utils.goml
index fa863ae4e96e..53ea91b929fe 100644
--- a/tests/rustdoc-gui/utils.goml
+++ b/tests/rustdoc-gui/utils.goml
@@ -110,6 +110,7 @@ define-function: (
         call-function: ("open-search", {})
         // We empty the search input in case it wasn't empty.
         set-property: (".search-input", {"value": ""})
+        focus: ".search-input"
         // We write the actual query.
         write-into: (".search-input", |query|)
         press-key: 'Enter'

From 6e7a87c5c5a20d43e254986724e4d781556d8a53 Mon Sep 17 00:00:00 2001
From: cyrgani <ansgar.w.zielke@gmail.com>
Date: Mon, 26 Jan 2026 15:24:22 +0000
Subject: [PATCH 41/97] merge `Mark` and `Unmark` traits

---
 library/proc_macro/src/bridge/mod.rs | 31 ++++++----------------------
 1 file changed, 6 insertions(+), 25 deletions(-)

diff --git a/library/proc_macro/src/bridge/mod.rs b/library/proc_macro/src/bridge/mod.rs
index 97e36a3d70c1..244ab7d81b02 100644
--- a/library/proc_macro/src/bridge/mod.rs
+++ b/library/proc_macro/src/bridge/mod.rs
@@ -155,11 +155,6 @@ with_api!(self, declare_tags);
 trait Mark {
     type Unmarked;
     fn mark(unmarked: Self::Unmarked) -> Self;
-}
-
-/// Unwrap types wrapped by `Mark::mark` (see `Mark` for details).
-trait Unmark {
-    type Unmarked;
     fn unmark(self) -> Self::Unmarked;
 }
 
@@ -174,15 +169,15 @@ impl<T, M> Mark for Marked<T, M> {
     fn mark(unmarked: Self::Unmarked) -> Self {
         Marked { value: unmarked, _marker: marker::PhantomData }
     }
-}
-impl<T, M> Unmark for Marked<T, M> {
-    type Unmarked = T;
     fn unmark(self) -> Self::Unmarked {
         self.value
     }
 }
-impl<'a, T, M> Unmark for &'a Marked<T, M> {
+impl<'a, T, M> Mark for &'a Marked<T, M> {
     type Unmarked = &'a T;
+    fn mark(_: Self::Unmarked) -> Self {
+        unreachable!()
+    }
     fn unmark(self) -> Self::Unmarked {
         &self.value
     }
@@ -194,9 +189,6 @@ impl<T: Mark> Mark for Vec<T> {
         // Should be a no-op due to std's in-place collect optimizations.
         unmarked.into_iter().map(T::mark).collect()
     }
-}
-impl<T: Unmark> Unmark for Vec<T> {
-    type Unmarked = Vec<T::Unmarked>;
     fn unmark(self) -> Self::Unmarked {
         // Should be a no-op due to std's in-place collect optimizations.
         self.into_iter().map(T::unmark).collect()
@@ -211,9 +203,6 @@ macro_rules! mark_noop {
                 fn mark(unmarked: Self::Unmarked) -> Self {
                     unmarked
                 }
-            }
-            impl Unmark for $ty {
-                type Unmarked = Self;
                 fn unmark(self) -> Self::Unmarked {
                     self
                 }
@@ -294,13 +283,9 @@ macro_rules! mark_compound {
                     $($field: Mark::mark(unmarked.$field)),*
                 }
             }
-        }
-
-        impl<$($T: Unmark),+> Unmark for $name <$($T),+> {
-            type Unmarked = $name <$($T::Unmarked),+>;
             fn unmark(self) -> Self::Unmarked {
                 $name {
-                    $($field: Unmark::unmark(self.$field)),*
+                    $($field: Mark::unmark(self.$field)),*
                 }
             }
         }
@@ -315,14 +300,10 @@ macro_rules! mark_compound {
                     })*
                 }
             }
-        }
-
-        impl<$($T: Unmark),+> Unmark for $name <$($T),+> {
-            type Unmarked = $name <$($T::Unmarked),+>;
             fn unmark(self) -> Self::Unmarked {
                 match self {
                     $($name::$variant $(($field))? => {
-                        $name::$variant $((Unmark::unmark($field)))?
+                        $name::$variant $((Mark::unmark($field)))?
                     })*
                 }
             }

From 1f6a55d8ba5d51dda17bec2f90ac48e807de79f5 Mon Sep 17 00:00:00 2001
From: rustbot <47979223+rustbot@users.noreply.github.com>
Date: Mon, 26 Jan 2026 18:00:52 +0100
Subject: [PATCH 42/97] Update books

---
 src/doc/reference       | 2 +-
 src/doc/rust-by-example | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/doc/reference b/src/doc/reference
index 28b5a5441998..990819b86c22 160000
--- a/src/doc/reference
+++ b/src/doc/reference
@@ -1 +1 @@
-Subproject commit 28b5a54419985f03db5294de5eede71b6665b594
+Subproject commit 990819b86c22bbf538c0526f0287670f3dc1a67a
diff --git a/src/doc/rust-by-example b/src/doc/rust-by-example
index 8de6ff811315..bac931ef1673 160000
--- a/src/doc/rust-by-example
+++ b/src/doc/rust-by-example
@@ -1 +1 @@
-Subproject commit 8de6ff811315ac3a96ebe01d74057382e42ffdee
+Subproject commit bac931ef1673af63fb60c3d691633034713cca20

From d541277ce18c874dd423f2550685762b351c0faa Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Luka=20Bla=C5=A1kovi=C4=87?= <lblasc@tvbeat.com>
Date: Mon, 26 Jan 2026 17:08:00 +0000
Subject: [PATCH 43/97] os allow missing_docs

---
 library/core/src/os/mod.rs | 1 +
 1 file changed, 1 insertion(+)

diff --git a/library/core/src/os/mod.rs b/library/core/src/os/mod.rs
index 897f59f530ed..5ac2b637941a 100644
--- a/library/core/src/os/mod.rs
+++ b/library/core/src/os/mod.rs
@@ -1,6 +1,7 @@
 //! OS-specific functionality.
 
 #![unstable(feature = "darwin_objc", issue = "145496")]
+#![allow(missing_docs)]
 
 #[cfg(all(
     doc,

From abcd22d5ed8b8efc6ce6928a852f8b7a2659c553 Mon Sep 17 00:00:00 2001
From: xtqqczze <45661989+xtqqczze@users.noreply.github.com>
Date: Mon, 26 Jan 2026 17:31:34 +0000
Subject: [PATCH 44/97] Omit standard copyright notice

Remove copyright notices for files licensed under the standard terms (MIT OR Apache-2.0).
---
 REUSE.toml                                         | 2 +-
 compiler/rustc_codegen_gcc/example/alloc_system.rs | 3 ---
 src/doc/rustc-dev-guide/src/conventions.md         | 3 +--
 src/tools/miri/tests/pass/intrinsics/integer.rs    | 3 ---
 src/tools/miri/tests/pass/issues/issue-30530.rs    | 3 ---
 src/tools/miri/tests/pass/tag-align-dyn-u64.rs     | 3 ---
 6 files changed, 2 insertions(+), 15 deletions(-)

diff --git a/REUSE.toml b/REUSE.toml
index 6052c2df4c7a..5ee913426a14 100644
--- a/REUSE.toml
+++ b/REUSE.toml
@@ -53,7 +53,7 @@ path = [
 ]
 precedence = "override"
 SPDX-FileCopyrightText = "The Rust Project Developers (see https://thanks.rust-lang.org)"
-SPDX-License-Identifier = "MIT or Apache-2.0"
+SPDX-License-Identifier = "MIT OR Apache-2.0"
 
 [[annotations]]
 path = "compiler/rustc_llvm/llvm-wrapper/SymbolWrapper.cpp"
diff --git a/compiler/rustc_codegen_gcc/example/alloc_system.rs b/compiler/rustc_codegen_gcc/example/alloc_system.rs
index 4d70122496b7..31457185f1a8 100644
--- a/compiler/rustc_codegen_gcc/example/alloc_system.rs
+++ b/compiler/rustc_codegen_gcc/example/alloc_system.rs
@@ -1,6 +1,3 @@
-// SPDX-License-Identifier: MIT OR Apache-2.0
-// SPDX-FileCopyrightText: The Rust Project Developers (see https://thanks.rust-lang.org)
-
 #![no_std]
 #![feature(allocator_api, rustc_private)]
 
diff --git a/src/doc/rustc-dev-guide/src/conventions.md b/src/doc/rustc-dev-guide/src/conventions.md
index 5153f2c5711a..0e08ef9042d1 100644
--- a/src/doc/rustc-dev-guide/src/conventions.md
+++ b/src/doc/rustc-dev-guide/src/conventions.md
@@ -76,8 +76,7 @@ These use a pinned version of `ruff`, to avoid relying on the local environment.
 <!-- REUSE-IgnoreEnd -->
 
 In the past, files began with a copyright and license notice.
-Please **omit** this notice for new files licensed under the standard terms (dual
-MIT/Apache-2.0).
+Please **omit** this notice for new files licensed under the standard terms (MIT OR Apache-2.0).
 
 All of the copyright notices should be gone by now, but if you come across one
 in the rust-lang/rust repo, feel free to open a PR to remove it.
diff --git a/src/tools/miri/tests/pass/intrinsics/integer.rs b/src/tools/miri/tests/pass/intrinsics/integer.rs
index a67c52f7b420..b56ee00422f0 100644
--- a/src/tools/miri/tests/pass/intrinsics/integer.rs
+++ b/src/tools/miri/tests/pass/intrinsics/integer.rs
@@ -1,6 +1,3 @@
-// SPDX-License-Identifier: MIT OR Apache-2.0
-// SPDX-FileCopyrightText: The Rust Project Developers (see https://thanks.rust-lang.org)
-
 #![feature(core_intrinsics, funnel_shifts)]
 use std::intrinsics::*;
 
diff --git a/src/tools/miri/tests/pass/issues/issue-30530.rs b/src/tools/miri/tests/pass/issues/issue-30530.rs
index af338e8032d1..3be3b54f2159 100644
--- a/src/tools/miri/tests/pass/issues/issue-30530.rs
+++ b/src/tools/miri/tests/pass/issues/issue-30530.rs
@@ -1,6 +1,3 @@
-// SPDX-License-Identifier: MIT OR Apache-2.0
-// SPDX-FileCopyrightText: The Rust Project Developers (see https://thanks.rust-lang.org)
-
 // Regression test for Issue #30530: alloca's created for storing
 // intermediate scratch values during brace-less match arms need to be
 // initialized with their drop-flag set to "dropped" (or else we end
diff --git a/src/tools/miri/tests/pass/tag-align-dyn-u64.rs b/src/tools/miri/tests/pass/tag-align-dyn-u64.rs
index e4abc3895008..58a38ff1c713 100644
--- a/src/tools/miri/tests/pass/tag-align-dyn-u64.rs
+++ b/src/tools/miri/tests/pass/tag-align-dyn-u64.rs
@@ -1,6 +1,3 @@
-// SPDX-License-Identifier: MIT OR Apache-2.0
-// SPDX-FileCopyrightText: The Rust Project Developers (see https://thanks.rust-lang.org)
-
 use std::mem;
 
 enum Tag<A> {

From 4a27be69726a9bd9badaa3b4ae1b5a4a63388235 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Esteban=20K=C3=BCber?= <esteban@kuber.com.ar>
Date: Sat, 8 Nov 2025 22:16:44 +0000
Subject: [PATCH 45/97] Do not mention `-Zmacro-backtrace` for std macros that
 are a wrapper around a compiler intrinsic

---
 compiler/rustc_expand/src/base.rs             | 14 ++++++++++++-
 .../tests/ui/recursive_format_impl.stderr     | 18 ----------------
 .../concurrency/windows_join_main.stderr      |  1 -
 .../dangling_primitive.stderr                 |  1 -
 .../out_of_bounds_read.stderr                 |  1 -
 .../out_of_bounds_read_neg_offset.stderr      |  1 -
 .../out_of_bounds_write.stderr                |  1 -
 .../miri/tests/fail/erroneous_const2.stderr   |  2 --
 .../return_pointer_on_unwind.stderr           |  1 -
 .../tests/fail/intrinsics/simd-scatter.stderr |  1 -
 .../tests/fail/provenance/mix-ptrs1.stderr    |  1 -
 .../tests/fail/provenance/mix-ptrs2.stderr    |  1 -
 src/tools/miri/tests/fail/rc_as_ptr.stderr    |  1 -
 .../fail/stacked_borrows/zst_slice.stderr     |  1 -
 .../parent_read_freezes_raw_mut.stderr        |  1 -
 .../tree_borrows/protector-write-lazy.stderr  |  1 -
 .../tests/pass/alloc-access-tracking.stderr   |  2 --
 .../main-alongside-macro-calls.fail.stdout    |  4 ----
 tests/ui/asm/aarch64/type-check-2.stderr      |  1 -
 tests/ui/asm/parse-error.stderr               |  8 -------
 tests/ui/asm/x86_64/type-check-2.stderr       |  1 -
 .../defaults-not-assumed-fail.stderr          |  3 ---
 .../ui/async-await/unreachable-lint-2.stderr  |  1 -
 ...y-operation-error-on-function-70724.stderr |  4 ----
 tests/ui/binop/eq-vec.stderr                  |  1 -
 .../function-comparison-errors-59488.stderr   |  6 ------
 tests/ui/binop/issue-77910-1.stderr           |  3 ---
 .../higher-ranked-outlives-for-capture.stderr |  2 --
 tests/ui/borrowck/borrowck-and-init.stderr    |  2 --
 .../borrowck-borrowed-uniq-rvalue-2.stderr    |  1 -
 .../borrowck/borrowck-break-uninit-2.stderr   |  1 -
 .../ui/borrowck/borrowck-break-uninit.stderr  |  1 -
 tests/ui/borrowck/borrowck-or-init.stderr     |  2 --
 tests/ui/borrowck/borrowck-while-break.stderr |  2 --
 .../ui/borrowck/issue-24267-flow-exit.stderr  |  2 --
 tests/ui/borrowck/issue-47646.stderr          |  2 --
 tests/ui/borrowck/issue-64453.stderr          |  1 -
 ...ownership-struct-update-moved-error.stderr |  1 -
 .../ui/borrowck/suggest-assign-rvalue.stderr  | 10 ---------
 .../diagnostics/arrays.stderr                 |  2 --
 .../diagnostics/box.stderr                    |  2 --
 .../diagnostics/repr_packed.stderr            |  1 -
 .../simple-struct-min-capture.stderr          |  2 --
 tests/ui/closures/issue-111932.stderr         |  1 -
 tests/ui/codemap_tests/bad-format-args.stderr |  2 --
 tests/ui/codemap_tests/tab_3.stderr           |  1 -
 .../vec-macro-in-static-array.stderr          |  1 -
 tests/ui/consts/const-eval/const_panic.stderr |  4 ----
 .../consts/const-eval/const_panic_2021.stderr |  4 ----
 .../const-eval/const_panic_libcore_bin.stderr |  2 --
 tests/ui/consts/const-eval/format.stderr      |  2 --
 tests/ui/consts/const-eval/issue-44578.stderr |  3 ---
 .../ui/consts/control-flow/issue-50577.stderr |  2 --
 .../min_const_fn/bad_const_fn_body_ice.stderr |  3 ---
 .../ui/consts/recursive-const-in-impl.stderr  |  1 -
 .../yield-while-ref-reborrowed.stderr         |  2 --
 .../ice-line-bounds-issue-148732.stderr       |  3 ---
 .../ui/derives/nonsense-input-to-debug.stderr |  2 --
 tests/ui/error-codes/E0010-teach.stderr       |  2 --
 tests/ui/error-codes/E0010.stderr             |  3 ---
 .../span-format_args-issue-140578.stderr      | 10 ---------
 .../expr/if/assert-macro-without-else.stderr  |  4 ----
 .../feature-gate-global-registration.stderr   |  2 --
 tests/ui/fmt/format-args-argument-span.stderr |  4 ----
 tests/ui/fmt/ifmt-bad-arg.stderr              |  2 --
 tests/ui/fmt/ifmt-unimpl.stderr               |  1 -
 tests/ui/fmt/non-source-literals.stderr       |  4 ----
 .../precise-capturing/migration-note.stderr   |  1 -
 ...745-avoid-expr-from-macro-expansion.stderr |  2 --
 tests/ui/issues/issue-42796.stderr            |  1 -
 .../iter-macro-not-async-closure.stderr       |  2 --
 .../lifetimes/borrowck-let-suggestion.stderr  |  1 -
 tests/ui/lint/dead-code/closure-bang.stderr   |  1 -
 tests/ui/lint/fn-ptr-comparisons-some.stderr  |  1 -
 tests/ui/lint/fn-ptr-comparisons-weird.stderr |  2 --
 .../ui/liveness/liveness-move-in-while.stderr |  1 -
 .../liveness/liveness-use-after-move.stderr   |  1 -
 .../liveness/liveness-use-after-send.stderr   |  1 -
 tests/ui/loops/loop-proper-liveness.stderr    |  1 -
 .../macros/assert.with-generic-asset.stderr   |  2 --
 .../assert.without-generic-asset.stderr       |  2 --
 .../failed-to-reparse-issue-139445.stderr     |  4 ----
 tests/ui/macros/format-parse-errors.stderr    |  2 --
 .../macro-expansion-empty-span-147255.stderr  |  1 -
 .../macros/macro-local-data-key-priv.stderr   |  1 -
 tests/ui/macros/vec-macro-in-pattern.stderr   |  3 ---
 .../mismatched-types-issue-126222.stderr      |  4 ----
 tests/ui/modules/issue-107649.stderr          |  1 -
 ...es-based-on-type-capture-clause-bad.stderr |  1 -
 .../nll-problem-case-3-issue-21906.nll.stderr |  2 --
 tests/ui/on-unimplemented/no-debug.stderr     |  4 ----
 ...t-mode-unimplemented-for-constblock.stderr |  3 ---
 ...fetime_errors_on_promotion_misusage.stderr |  2 --
 tests/ui/reachable/expr_again.stderr          |  1 -
 tests/ui/reachable/expr_block.stderr          |  2 --
 tests/ui/reachable/expr_if.stderr             |  2 --
 tests/ui/reachable/expr_loop.stderr           |  5 -----
 tests/ui/reachable/expr_match.stderr          |  5 -----
 .../ui/reachable/unreachable-code-ret.stderr  |  1 -
 .../underscore-bindings-disambiguators.stderr | 12 -----------
 .../diverge-causes-unreachable-code.stderr    |  7 -------
 .../dbg-macro-move-semantics.stderr           |  1 -
 .../dbg-macro-requires-debug.stderr           |  1 -
 tests/ui/span/coerce-suggestions.stderr       |  2 --
 tests/ui/span/issue-33884.stderr              |  2 --
 tests/ui/span/issue-39698.stderr              |  2 --
 tests/ui/span/slice-borrow.stderr             |  1 -
 .../statics/check-values-constraints.stderr   | 21 -------------------
 tests/ui/suggestions/bound-suggestions.stderr |  6 ------
 tests/ui/suggestions/issue-97760.stderr       |  1 -
 tests/ui/suggestions/path-display.stderr      |  2 --
 tests/ui/thread-local/no-unstable.stderr      |  4 ----
 .../ui/traits/const-traits/issue-79450.stderr |  1 -
 .../try-block-maybe-bad-lifetime.stderr       |  1 -
 tests/ui/try-block/try-block-opt-init.stderr  |  2 --
 ...ounds_from_bounds_param.edition2024.stderr |  3 ---
 tests/ui/type-alias-impl-trait/nested.stderr  |  1 -
 ...igned-block-without-tail-expression.stderr |  4 ----
 .../closure-ty-mismatch-issue-128561.stderr   |  2 --
 ...0017-format-into-help-deletes-macro.stderr |  1 -
 ...2007-leaked-writeln-macro-internals.stderr |  1 -
 ...stion-mark-operator-suggestion-span.stderr |  1 -
 ...suggest-clone-in-macro-issue-139253.stderr |  2 --
 tests/ui/uninhabited/void-branch.stderr       |  2 --
 .../use/use-after-move-based-on-type.stderr   |  1 -
 125 files changed, 13 insertions(+), 314 deletions(-)

diff --git a/compiler/rustc_expand/src/base.rs b/compiler/rustc_expand/src/base.rs
index 6a3c9697a939..653f2071d898 100644
--- a/compiler/rustc_expand/src/base.rs
+++ b/compiler/rustc_expand/src/base.rs
@@ -849,6 +849,9 @@ pub struct SyntaxExtension {
     /// Should debuginfo for the macro be collapsed to the outermost expansion site (in other
     /// words, was the macro definition annotated with `#[collapse_debuginfo]`)?
     pub collapse_debuginfo: bool,
+    /// Suppresses the "this error originates in the macro" note when a diagnostic points at this
+    /// macro.
+    pub hide_backtrace: bool,
 }
 
 impl SyntaxExtension {
@@ -882,6 +885,7 @@ impl SyntaxExtension {
             allow_internal_unsafe: false,
             local_inner_macros: false,
             collapse_debuginfo: false,
+            hide_backtrace: false,
         }
     }
 
@@ -912,6 +916,12 @@ impl SyntaxExtension {
         collapse_table[flag as usize][attr as usize]
     }
 
+    fn get_hide_backtrace(attrs: &[hir::Attribute]) -> bool {
+        // FIXME(estebank): instead of reusing `#[rustc_diagnostic_item]` as a proxy, introduce a
+        // new attribute purely for this under the `#[diagnostic]` namespace.
+        ast::attr::find_by_name(attrs, sym::rustc_diagnostic_item).is_some()
+    }
+
     /// Constructs a syntax extension with the given properties
     /// and other properties converted from attributes.
     pub fn new(
@@ -948,6 +958,7 @@ impl SyntaxExtension {
             // Not a built-in macro
             None => (None, helper_attrs),
         };
+        let hide_backtrace = builtin_name.is_some() || Self::get_hide_backtrace(attrs);
 
         let stability = find_attr!(attrs, AttributeKind::Stability { stability, .. } => *stability);
 
@@ -982,6 +993,7 @@ impl SyntaxExtension {
             allow_internal_unsafe,
             local_inner_macros,
             collapse_debuginfo,
+            hide_backtrace,
         }
     }
 
@@ -1061,7 +1073,7 @@ impl SyntaxExtension {
             self.allow_internal_unsafe,
             self.local_inner_macros,
             self.collapse_debuginfo,
-            self.builtin_name.is_some(),
+            self.hide_backtrace,
         )
     }
 }
diff --git a/src/tools/clippy/tests/ui/recursive_format_impl.stderr b/src/tools/clippy/tests/ui/recursive_format_impl.stderr
index 31960c7193b4..4361d612bf2a 100644
--- a/src/tools/clippy/tests/ui/recursive_format_impl.stderr
+++ b/src/tools/clippy/tests/ui/recursive_format_impl.stderr
@@ -12,72 +12,54 @@ error: using `self` as `Display` in `impl Display` will cause infinite recursion
    |
 LL |         write!(f, "{}", self)
    |         ^^^^^^^^^^^^^^^^^^^^^
-   |
-   = note: this error originates in the macro `write` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error: using `self` as `Display` in `impl Display` will cause infinite recursion
   --> tests/ui/recursive_format_impl.rs:86:9
    |
 LL |         write!(f, "{}", &self)
    |         ^^^^^^^^^^^^^^^^^^^^^^
-   |
-   = note: this error originates in the macro `write` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error: using `self` as `Debug` in `impl Debug` will cause infinite recursion
   --> tests/ui/recursive_format_impl.rs:93:9
    |
 LL |         write!(f, "{:?}", &self)
    |         ^^^^^^^^^^^^^^^^^^^^^^^^
-   |
-   = note: this error originates in the macro `write` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error: using `self` as `Display` in `impl Display` will cause infinite recursion
   --> tests/ui/recursive_format_impl.rs:103:9
    |
 LL |         write!(f, "{}", &&&self)
    |         ^^^^^^^^^^^^^^^^^^^^^^^^
-   |
-   = note: this error originates in the macro `write` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error: using `self` as `Display` in `impl Display` will cause infinite recursion
   --> tests/ui/recursive_format_impl.rs:178:9
    |
 LL |         write!(f, "{}", &*self)
    |         ^^^^^^^^^^^^^^^^^^^^^^^
-   |
-   = note: this error originates in the macro `write` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error: using `self` as `Debug` in `impl Debug` will cause infinite recursion
   --> tests/ui/recursive_format_impl.rs:185:9
    |
 LL |         write!(f, "{:?}", &*self)
    |         ^^^^^^^^^^^^^^^^^^^^^^^^^
-   |
-   = note: this error originates in the macro `write` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error: using `self` as `Display` in `impl Display` will cause infinite recursion
   --> tests/ui/recursive_format_impl.rs:202:9
    |
 LL |         write!(f, "{}", *self)
    |         ^^^^^^^^^^^^^^^^^^^^^^
-   |
-   = note: this error originates in the macro `write` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error: using `self` as `Display` in `impl Display` will cause infinite recursion
   --> tests/ui/recursive_format_impl.rs:219:9
    |
 LL |         write!(f, "{}", **&&*self)
    |         ^^^^^^^^^^^^^^^^^^^^^^^^^^
-   |
-   = note: this error originates in the macro `write` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error: using `self` as `Display` in `impl Display` will cause infinite recursion
   --> tests/ui/recursive_format_impl.rs:236:9
    |
 LL |         write!(f, "{}", &&**&&*self)
    |         ^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-   |
-   = note: this error originates in the macro `write` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error: aborting due to 10 previous errors
 
diff --git a/src/tools/miri/tests/fail-dep/concurrency/windows_join_main.stderr b/src/tools/miri/tests/fail-dep/concurrency/windows_join_main.stderr
index 3d324ad0bdef..2f3e41b405bc 100644
--- a/src/tools/miri/tests/fail-dep/concurrency/windows_join_main.stderr
+++ b/src/tools/miri/tests/fail-dep/concurrency/windows_join_main.stderr
@@ -31,7 +31,6 @@ LL | |             assert_eq!(WaitForSingleObject(MAIN_THREAD, INFINITE), WAIT_O
 LL | |         }
 LL | |     })
    | |______^
-   = note: this error originates in the macro `assert_eq` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 note: some details are omitted, run with `MIRIFLAGS=-Zmiri-backtrace=full` for a verbose backtrace
 
diff --git a/src/tools/miri/tests/fail/dangling_pointers/dangling_primitive.stderr b/src/tools/miri/tests/fail/dangling_pointers/dangling_primitive.stderr
index 24a807afd73d..afc2cb214842 100644
--- a/src/tools/miri/tests/fail/dangling_pointers/dangling_primitive.stderr
+++ b/src/tools/miri/tests/fail/dangling_pointers/dangling_primitive.stderr
@@ -16,7 +16,6 @@ help: ALLOC was deallocated here:
    |
 LL |     };
    |     ^
-   = note: this error originates in the macro `$crate::macros::dbg_internal` which comes from the expansion of the macro `dbg` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 note: some details are omitted, run with `MIRIFLAGS=-Zmiri-backtrace=full` for a verbose backtrace
 
diff --git a/src/tools/miri/tests/fail/dangling_pointers/out_of_bounds_read.stderr b/src/tools/miri/tests/fail/dangling_pointers/out_of_bounds_read.stderr
index b957056ad36e..836c1bd8af89 100644
--- a/src/tools/miri/tests/fail/dangling_pointers/out_of_bounds_read.stderr
+++ b/src/tools/miri/tests/fail/dangling_pointers/out_of_bounds_read.stderr
@@ -11,7 +11,6 @@ help: ALLOC was allocated here:
    |
 LL |     let v: Vec<u16> = vec![1, 2];
    |                       ^^^^^^^^^^
-   = note: this error originates in the macro `vec` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 note: some details are omitted, run with `MIRIFLAGS=-Zmiri-backtrace=full` for a verbose backtrace
 
diff --git a/src/tools/miri/tests/fail/dangling_pointers/out_of_bounds_read_neg_offset.stderr b/src/tools/miri/tests/fail/dangling_pointers/out_of_bounds_read_neg_offset.stderr
index 6cae87b759ee..5635bb9cc443 100644
--- a/src/tools/miri/tests/fail/dangling_pointers/out_of_bounds_read_neg_offset.stderr
+++ b/src/tools/miri/tests/fail/dangling_pointers/out_of_bounds_read_neg_offset.stderr
@@ -11,7 +11,6 @@ help: ALLOC was allocated here:
    |
 LL |     let v: Vec<u16> = vec![1, 2];
    |                       ^^^^^^^^^^
-   = note: this error originates in the macro `vec` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 note: some details are omitted, run with `MIRIFLAGS=-Zmiri-backtrace=full` for a verbose backtrace
 
diff --git a/src/tools/miri/tests/fail/dangling_pointers/out_of_bounds_write.stderr b/src/tools/miri/tests/fail/dangling_pointers/out_of_bounds_write.stderr
index 13e83e4696cf..c18a55d30cc1 100644
--- a/src/tools/miri/tests/fail/dangling_pointers/out_of_bounds_write.stderr
+++ b/src/tools/miri/tests/fail/dangling_pointers/out_of_bounds_write.stderr
@@ -11,7 +11,6 @@ help: ALLOC was allocated here:
    |
 LL |     let mut v: Vec<u16> = vec![1, 2];
    |                           ^^^^^^^^^^
-   = note: this error originates in the macro `vec` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 note: some details are omitted, run with `MIRIFLAGS=-Zmiri-backtrace=full` for a verbose backtrace
 
diff --git a/src/tools/miri/tests/fail/erroneous_const2.stderr b/src/tools/miri/tests/fail/erroneous_const2.stderr
index 08d2cc124f13..d9074e6e2498 100644
--- a/src/tools/miri/tests/fail/erroneous_const2.stderr
+++ b/src/tools/miri/tests/fail/erroneous_const2.stderr
@@ -23,8 +23,6 @@ note: erroneous constant encountered
    |
 LL |     println!("{}", FOO);
    |                    ^^^
-   |
-   = note: this note originates in the macro `$crate::format_args_nl` which comes from the expansion of the macro `println` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error: aborting due to 1 previous error
 
diff --git a/src/tools/miri/tests/fail/function_calls/return_pointer_on_unwind.stderr b/src/tools/miri/tests/fail/function_calls/return_pointer_on_unwind.stderr
index 845b4f977ca3..364a4b4a7441 100644
--- a/src/tools/miri/tests/fail/function_calls/return_pointer_on_unwind.stderr
+++ b/src/tools/miri/tests/fail/function_calls/return_pointer_on_unwind.stderr
@@ -11,7 +11,6 @@ LL |     dbg!(x.0);
    |
    = help: this indicates a bug in the program: it performed an invalid operation, and caused Undefined Behavior
    = help: see https://doc.rust-lang.org/nightly/reference/behavior-considered-undefined.html for further information
-   = note: this error originates in the macro `$crate::macros::dbg_internal` which comes from the expansion of the macro `dbg` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 Uninitialized memory occurred at ALLOC[0x0..0x4], in this allocation:
 ALLOC (stack variable, size: 132, align: 4) {
diff --git a/src/tools/miri/tests/fail/intrinsics/simd-scatter.stderr b/src/tools/miri/tests/fail/intrinsics/simd-scatter.stderr
index 4d1dcec3b576..cd38ff4355aa 100644
--- a/src/tools/miri/tests/fail/intrinsics/simd-scatter.stderr
+++ b/src/tools/miri/tests/fail/intrinsics/simd-scatter.stderr
@@ -16,7 +16,6 @@ help: ALLOC was allocated here:
    |
 LL |         let mut vec: Vec<i8> = vec![10, 11, 12, 13, 14, 15, 16, 17, 18];
    |                                ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-   = note: this error originates in the macro `vec` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 note: some details are omitted, run with `MIRIFLAGS=-Zmiri-backtrace=full` for a verbose backtrace
 
diff --git a/src/tools/miri/tests/fail/provenance/mix-ptrs1.stderr b/src/tools/miri/tests/fail/provenance/mix-ptrs1.stderr
index 92aeb6445b4f..e1d4b7d95f66 100644
--- a/src/tools/miri/tests/fail/provenance/mix-ptrs1.stderr
+++ b/src/tools/miri/tests/fail/provenance/mix-ptrs1.stderr
@@ -6,7 +6,6 @@ LL |         assert_eq!(*strange_ptr.with_addr(ptr.addr()), 0);
    |
    = help: this indicates a bug in the program: it performed an invalid operation, and caused Undefined Behavior
    = help: see https://doc.rust-lang.org/nightly/reference/behavior-considered-undefined.html for further information
-   = note: this error originates in the macro `assert_eq` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 note: some details are omitted, run with `MIRIFLAGS=-Zmiri-backtrace=full` for a verbose backtrace
 
diff --git a/src/tools/miri/tests/fail/provenance/mix-ptrs2.stderr b/src/tools/miri/tests/fail/provenance/mix-ptrs2.stderr
index e00e72a50c6b..a77f73f81e5f 100644
--- a/src/tools/miri/tests/fail/provenance/mix-ptrs2.stderr
+++ b/src/tools/miri/tests/fail/provenance/mix-ptrs2.stderr
@@ -6,7 +6,6 @@ LL |         assert_eq!(*ptr, 42);
    |
    = help: this indicates a bug in the program: it performed an invalid operation, and caused Undefined Behavior
    = help: see https://doc.rust-lang.org/nightly/reference/behavior-considered-undefined.html for further information
-   = note: this error originates in the macro `assert_eq` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 note: some details are omitted, run with `MIRIFLAGS=-Zmiri-backtrace=full` for a verbose backtrace
 
diff --git a/src/tools/miri/tests/fail/rc_as_ptr.stderr b/src/tools/miri/tests/fail/rc_as_ptr.stderr
index d2d9d94afd44..d97878f815cc 100644
--- a/src/tools/miri/tests/fail/rc_as_ptr.stderr
+++ b/src/tools/miri/tests/fail/rc_as_ptr.stderr
@@ -16,7 +16,6 @@ help: ALLOC was deallocated here:
    |
 LL |     drop(strong);
    |     ^^^^^^^^^^^^
-   = note: this error originates in the macro `assert_eq` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 note: some details are omitted, run with `MIRIFLAGS=-Zmiri-backtrace=full` for a verbose backtrace
 
diff --git a/src/tools/miri/tests/fail/stacked_borrows/zst_slice.stderr b/src/tools/miri/tests/fail/stacked_borrows/zst_slice.stderr
index 91b320465624..c0e4f24a5a15 100644
--- a/src/tools/miri/tests/fail/stacked_borrows/zst_slice.stderr
+++ b/src/tools/miri/tests/fail/stacked_borrows/zst_slice.stderr
@@ -11,7 +11,6 @@ help: <TAG> would have been created here, but this is a zero-size retag ([0x0..0
    |
 LL |         assert_eq!(*s.as_ptr().add(1), 2);
    |                     ^^^^^^^^^^
-   = note: this error originates in the macro `assert_eq` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 note: some details are omitted, run with `MIRIFLAGS=-Zmiri-backtrace=full` for a verbose backtrace
 
diff --git a/src/tools/miri/tests/fail/tree_borrows/parent_read_freezes_raw_mut.stderr b/src/tools/miri/tests/fail/tree_borrows/parent_read_freezes_raw_mut.stderr
index d0cd0088c0be..791263b95248 100644
--- a/src/tools/miri/tests/fail/tree_borrows/parent_read_freezes_raw_mut.stderr
+++ b/src/tools/miri/tests/fail/tree_borrows/parent_read_freezes_raw_mut.stderr
@@ -24,7 +24,6 @@ help: the accessed tag <TAG> later transitioned to Frozen due to a reborrow (act
 LL |         assert_eq!(root, 0); // Parent Read
    |         ^^^^^^^^^^^^^^^^^^^
    = help: this transition corresponds to a loss of write permissions
-   = note: this error originates in the macro `assert_eq` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 note: some details are omitted, run with `MIRIFLAGS=-Zmiri-backtrace=full` for a verbose backtrace
 
diff --git a/src/tools/miri/tests/fail/tree_borrows/protector-write-lazy.stderr b/src/tools/miri/tests/fail/tree_borrows/protector-write-lazy.stderr
index 6ebc2dd40e29..9606aaadf33c 100644
--- a/src/tools/miri/tests/fail/tree_borrows/protector-write-lazy.stderr
+++ b/src/tools/miri/tests/fail/tree_borrows/protector-write-lazy.stderr
@@ -18,7 +18,6 @@ help: the accessed tag <TAG> later transitioned to Disabled due to a protector r
 LL | }
    |  ^
    = help: this transition corresponds to a loss of read and write permissions
-   = note: this error originates in the macro `$crate::format_args_nl` which comes from the expansion of the macro `println` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 note: some details are omitted, run with `MIRIFLAGS=-Zmiri-backtrace=full` for a verbose backtrace
 
diff --git a/src/tools/miri/tests/pass/alloc-access-tracking.stderr b/src/tools/miri/tests/pass/alloc-access-tracking.stderr
index 5dfcd0180e4c..f1c9241beded 100644
--- a/src/tools/miri/tests/pass/alloc-access-tracking.stderr
+++ b/src/tools/miri/tests/pass/alloc-access-tracking.stderr
@@ -15,8 +15,6 @@ note: read access at ALLOC[0..1]
    |
 LL |         assert_eq!(*ptr, 42);
    |         ^^^^^^^^^^^^^^^^^^^^ tracking was triggered here
-   |
-   = note: this note originates in the macro `assert_eq` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 note: freed allocation ALLOC
   --> RUSTLIB/alloc/src/boxed.rs:LL:CC
diff --git a/tests/rustdoc-ui/doctest/main-alongside-macro-calls.fail.stdout b/tests/rustdoc-ui/doctest/main-alongside-macro-calls.fail.stdout
index 65989a8ef47c..8c01c6ff5a41 100644
--- a/tests/rustdoc-ui/doctest/main-alongside-macro-calls.fail.stdout
+++ b/tests/rustdoc-ui/doctest/main-alongside-macro-calls.fail.stdout
@@ -13,8 +13,6 @@ error: macros that expand to items must be delimited with braces or followed by
    |
 LL | println!();
    | ^^^^^^^^^^
-   |
-   = note: this error originates in the macro `println` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error: macro expansion ignores `{` and any tokens following
   --> $SRC_DIR/std/src/macros.rs:LL:COL
@@ -35,8 +33,6 @@ error: macros that expand to items must be delimited with braces or followed by
    |
 LL | println!();
    | ^^^^^^^^^^
-   |
-   = note: this error originates in the macro `println` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error: macro expansion ignores `{` and any tokens following
   --> $SRC_DIR/std/src/macros.rs:LL:COL
diff --git a/tests/ui/asm/aarch64/type-check-2.stderr b/tests/ui/asm/aarch64/type-check-2.stderr
index 84bc5f08b4ed..2cd767db0334 100644
--- a/tests/ui/asm/aarch64/type-check-2.stderr
+++ b/tests/ui/asm/aarch64/type-check-2.stderr
@@ -21,7 +21,6 @@ LL |         asm!("{}", in(reg) vec![0]);
    |                            ^^^^^^^
    |
    = note: only integers, floats, SIMD vectors, pointers and function pointers can be used as arguments for inline assembly
-   = note: this error originates in the macro `vec` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error: cannot use value of type `(i32, i32, i32)` for inline assembly
   --> $DIR/type-check-2.rs:36:28
diff --git a/tests/ui/asm/parse-error.stderr b/tests/ui/asm/parse-error.stderr
index dff85a601b73..fe6802b0c0c9 100644
--- a/tests/ui/asm/parse-error.stderr
+++ b/tests/ui/asm/parse-error.stderr
@@ -193,16 +193,12 @@ error: asm template must be a string literal
    |
 LL |         asm!(format!("{{{}}}", 0), in(reg) foo);
    |              ^^^^^^^^^^^^^^^^^^^^
-   |
-   = note: this error originates in the macro `format` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error: asm template must be a string literal
   --> $DIR/parse-error.rs:86:21
    |
 LL |         asm!("{1}", format!("{{{}}}", 0), in(reg) foo, out(reg) bar);
    |                     ^^^^^^^^^^^^^^^^^^^^
-   |
-   = note: this error originates in the macro `format` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error: _ cannot be used for input operands
   --> $DIR/parse-error.rs:88:28
@@ -357,16 +353,12 @@ error: asm template must be a string literal
    |
 LL | global_asm!(format!("{{{}}}", 0), const FOO);
    |             ^^^^^^^^^^^^^^^^^^^^
-   |
-   = note: this error originates in the macro `format` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error: asm template must be a string literal
   --> $DIR/parse-error.rs:143:20
    |
 LL | global_asm!("{1}", format!("{{{}}}", 0), const FOO, const BAR);
    |                    ^^^^^^^^^^^^^^^^^^^^
-   |
-   = note: this error originates in the macro `format` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error: the `in` operand cannot be used with `global_asm!`
   --> $DIR/parse-error.rs:146:19
diff --git a/tests/ui/asm/x86_64/type-check-2.stderr b/tests/ui/asm/x86_64/type-check-2.stderr
index d5c5a3ff1f84..e5d39b2fbd05 100644
--- a/tests/ui/asm/x86_64/type-check-2.stderr
+++ b/tests/ui/asm/x86_64/type-check-2.stderr
@@ -21,7 +21,6 @@ LL |         asm!("{}", in(reg) vec![0]);
    |                            ^^^^^^^
    |
    = note: only integers, floats, SIMD vectors, pointers and function pointers can be used as arguments for inline assembly
-   = note: this error originates in the macro `vec` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error: cannot use value of type `(i32, i32, i32)` for inline assembly
   --> $DIR/type-check-2.rs:52:28
diff --git a/tests/ui/associated-consts/defaults-not-assumed-fail.stderr b/tests/ui/associated-consts/defaults-not-assumed-fail.stderr
index 40f5f889f361..8b38905e1c57 100644
--- a/tests/ui/associated-consts/defaults-not-assumed-fail.stderr
+++ b/tests/ui/associated-consts/defaults-not-assumed-fail.stderr
@@ -23,8 +23,6 @@ note: erroneous constant encountered
    |
 LL |     assert_eq!(<() as Tr>::B, 0);    // causes the error above
    |     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-   |
-   = note: this note originates in the macro `assert_eq` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 note: erroneous constant encountered
   --> $DIR/defaults-not-assumed-fail.rs:34:5
@@ -33,7 +31,6 @@ LL |     assert_eq!(<() as Tr>::B, 0);    // causes the error above
    |     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^
    |
    = note: duplicate diagnostic emitted due to `-Z deduplicate-diagnostics=no`
-   = note: this note originates in the macro `assert_eq` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error: aborting due to 1 previous error
 
diff --git a/tests/ui/async-await/unreachable-lint-2.stderr b/tests/ui/async-await/unreachable-lint-2.stderr
index cbebc9951f32..5e7b328cf523 100644
--- a/tests/ui/async-await/unreachable-lint-2.stderr
+++ b/tests/ui/async-await/unreachable-lint-2.stderr
@@ -11,7 +11,6 @@ note: the lint level is defined here
    |
 LL | #![deny(unreachable_code)]
    |         ^^^^^^^^^^^^^^^^
-   = note: this error originates in the macro `println` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error: aborting due to 1 previous error
 
diff --git a/tests/ui/binop/binary-operation-error-on-function-70724.stderr b/tests/ui/binop/binary-operation-error-on-function-70724.stderr
index 11b0e4ba19c5..2eb980764a39 100644
--- a/tests/ui/binop/binary-operation-error-on-function-70724.stderr
+++ b/tests/ui/binop/binary-operation-error-on-function-70724.stderr
@@ -6,8 +6,6 @@ LL |     assert_eq!(a, 0);
    |     |
    |     fn() -> i32 {a}
    |     {integer}
-   |
-   = note: this error originates in the macro `assert_eq` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error[E0308]: mismatched types
   --> $DIR/binary-operation-error-on-function-70724.rs:7:5
@@ -17,7 +15,6 @@ LL |     assert_eq!(a, 0);
    |
    = note: expected fn item `fn() -> i32 {a}`
                  found type `{integer}`
-   = note: this error originates in the macro `assert_eq` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error[E0277]: `fn() -> i32 {a}` doesn't implement `Debug`
   --> $DIR/binary-operation-error-on-function-70724.rs:7:5
@@ -29,7 +26,6 @@ LL |     assert_eq!(a, 0);
    |     ^^^^^^^^^^^^^^^^ the trait `Debug` is not implemented for fn item `fn() -> i32 {a}`
    |
    = help: use parentheses to call this function: `a()`
-   = note: this error originates in the macro `assert_eq` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error: aborting due to 3 previous errors
 
diff --git a/tests/ui/binop/eq-vec.stderr b/tests/ui/binop/eq-vec.stderr
index 14739752877c..158bfe625934 100644
--- a/tests/ui/binop/eq-vec.stderr
+++ b/tests/ui/binop/eq-vec.stderr
@@ -12,7 +12,6 @@ note: an implementation of `PartialEq` might be missing for `Foo`
    |
 LL |     enum Foo {
    |     ^^^^^^^^ must implement `PartialEq`
-   = note: this error originates in the macro `assert_eq` (in Nightly builds, run with -Z macro-backtrace for more info)
 help: consider annotating `Foo` with `#[derive(PartialEq)]`
    |
 LL +     #[derive(PartialEq)]
diff --git a/tests/ui/binop/function-comparison-errors-59488.stderr b/tests/ui/binop/function-comparison-errors-59488.stderr
index 615458bc45b4..43ecd6a36f38 100644
--- a/tests/ui/binop/function-comparison-errors-59488.stderr
+++ b/tests/ui/binop/function-comparison-errors-59488.stderr
@@ -80,24 +80,18 @@ LL |     assert_eq!(Foo::Bar, i);
    |     |
    |     fn(usize) -> Foo {Foo::Bar}
    |     fn(usize) -> Foo {Foo::Bar}
-   |
-   = note: this error originates in the macro `assert_eq` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error[E0277]: `fn(usize) -> Foo {Foo::Bar}` doesn't implement `Debug`
   --> $DIR/function-comparison-errors-59488.rs:31:5
    |
 LL |     assert_eq!(Foo::Bar, i);
    |     ^^^^^^^^^^^^^^^^^^^^^^^ the trait `Debug` is not implemented for fn item `fn(usize) -> Foo {Foo::Bar}`
-   |
-   = note: this error originates in the macro `assert_eq` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error[E0277]: `fn(usize) -> Foo {Foo::Bar}` doesn't implement `Debug`
   --> $DIR/function-comparison-errors-59488.rs:31:5
    |
 LL |     assert_eq!(Foo::Bar, i);
    |     ^^^^^^^^^^^^^^^^^^^^^^^ the trait `Debug` is not implemented for fn item `fn(usize) -> Foo {Foo::Bar}`
-   |
-   = note: this error originates in the macro `assert_eq` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error: aborting due to 10 previous errors
 
diff --git a/tests/ui/binop/issue-77910-1.stderr b/tests/ui/binop/issue-77910-1.stderr
index 80c384f39bd1..9503813f4eb8 100644
--- a/tests/ui/binop/issue-77910-1.stderr
+++ b/tests/ui/binop/issue-77910-1.stderr
@@ -6,8 +6,6 @@ LL |     assert_eq!(foo, y);
    |     |
    |     for<'a> fn(&'a i32) -> &'a i32 {foo}
    |     _
-   |
-   = note: this error originates in the macro `assert_eq` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error[E0277]: `for<'a> fn(&'a i32) -> &'a i32 {foo}` doesn't implement `Debug`
   --> $DIR/issue-77910-1.rs:8:5
@@ -19,7 +17,6 @@ LL |     assert_eq!(foo, y);
    |     ^^^^^^^^^^^^^^^^^^ the trait `Debug` is not implemented for fn item `for<'a> fn(&'a i32) -> &'a i32 {foo}`
    |
    = help: use parentheses to call this function: `foo(/* &i32 */)`
-   = note: this error originates in the macro `assert_eq` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error[E0381]: used binding `xs` isn't initialized
   --> $DIR/issue-77910-1.rs:3:5
diff --git a/tests/ui/borrowck/alias-liveness/higher-ranked-outlives-for-capture.stderr b/tests/ui/borrowck/alias-liveness/higher-ranked-outlives-for-capture.stderr
index b5c2b662f315..c82821b04a35 100644
--- a/tests/ui/borrowck/alias-liveness/higher-ranked-outlives-for-capture.stderr
+++ b/tests/ui/borrowck/alias-liveness/higher-ranked-outlives-for-capture.stderr
@@ -8,8 +8,6 @@ LL |     test(&vec![])
    |     argument requires that borrow lasts for `'static`
 LL | }
    | - temporary value is freed at the end of this statement
-   |
-   = note: this error originates in the macro `vec` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error: aborting due to 1 previous error
 
diff --git a/tests/ui/borrowck/borrowck-and-init.stderr b/tests/ui/borrowck/borrowck-and-init.stderr
index 37386f1c4651..e6d49bc6e471 100644
--- a/tests/ui/borrowck/borrowck-and-init.stderr
+++ b/tests/ui/borrowck/borrowck-and-init.stderr
@@ -8,8 +8,6 @@ LL |     println!("{}", false && { i = 5; true });
    |                               ----- binding initialized here in some conditions
 LL |     println!("{}", i);
    |                    ^ `i` used here but it is possibly-uninitialized
-   |
-   = note: this error originates in the macro `$crate::format_args_nl` which comes from the expansion of the macro `println` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error: aborting due to 1 previous error
 
diff --git a/tests/ui/borrowck/borrowck-borrowed-uniq-rvalue-2.stderr b/tests/ui/borrowck/borrowck-borrowed-uniq-rvalue-2.stderr
index 7f0ecf7b3596..9fd4ee9b99ba 100644
--- a/tests/ui/borrowck/borrowck-borrowed-uniq-rvalue-2.stderr
+++ b/tests/ui/borrowck/borrowck-borrowed-uniq-rvalue-2.stderr
@@ -8,7 +8,6 @@ LL |     let x = defer(&vec!["Goodbye", "world!"]);
 LL |     x.x[0];
    |     ------ borrow later used here
    |
-   = note: this error originates in the macro `vec` (in Nightly builds, run with -Z macro-backtrace for more info)
 help: consider using a `let` binding to create a longer lived value
    |
 LL ~     let binding = vec!["Goodbye", "world!"];
diff --git a/tests/ui/borrowck/borrowck-break-uninit-2.stderr b/tests/ui/borrowck/borrowck-break-uninit-2.stderr
index e23ca534e745..03730e338ee0 100644
--- a/tests/ui/borrowck/borrowck-break-uninit-2.stderr
+++ b/tests/ui/borrowck/borrowck-break-uninit-2.stderr
@@ -7,7 +7,6 @@ LL |     let x: isize;
 LL |     println!("{}", x);
    |                    ^ `x` used here but it isn't initialized
    |
-   = note: this error originates in the macro `$crate::format_args_nl` which comes from the expansion of the macro `println` (in Nightly builds, run with -Z macro-backtrace for more info)
 help: consider assigning a value
    |
 LL |     let x: isize = 42;
diff --git a/tests/ui/borrowck/borrowck-break-uninit.stderr b/tests/ui/borrowck/borrowck-break-uninit.stderr
index 0367d224f801..6ed095f2e4a3 100644
--- a/tests/ui/borrowck/borrowck-break-uninit.stderr
+++ b/tests/ui/borrowck/borrowck-break-uninit.stderr
@@ -7,7 +7,6 @@ LL |     let x: isize;
 LL |     println!("{}", x);
    |                    ^ `x` used here but it isn't initialized
    |
-   = note: this error originates in the macro `$crate::format_args_nl` which comes from the expansion of the macro `println` (in Nightly builds, run with -Z macro-backtrace for more info)
 help: consider assigning a value
    |
 LL |     let x: isize = 42;
diff --git a/tests/ui/borrowck/borrowck-or-init.stderr b/tests/ui/borrowck/borrowck-or-init.stderr
index 7b43f2aee30e..63c0c982351b 100644
--- a/tests/ui/borrowck/borrowck-or-init.stderr
+++ b/tests/ui/borrowck/borrowck-or-init.stderr
@@ -8,8 +8,6 @@ LL |     println!("{}", false || { i = 5; true });
    |                               ----- binding initialized here in some conditions
 LL |     println!("{}", i);
    |                    ^ `i` used here but it is possibly-uninitialized
-   |
-   = note: this error originates in the macro `$crate::format_args_nl` which comes from the expansion of the macro `println` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error: aborting due to 1 previous error
 
diff --git a/tests/ui/borrowck/borrowck-while-break.stderr b/tests/ui/borrowck/borrowck-while-break.stderr
index e91af728b649..68333ce0a75d 100644
--- a/tests/ui/borrowck/borrowck-while-break.stderr
+++ b/tests/ui/borrowck/borrowck-while-break.stderr
@@ -8,8 +8,6 @@ LL |     while cond {
 ...
 LL |     println!("{}", v);
    |                    ^ `v` used here but it is possibly-uninitialized
-   |
-   = note: this error originates in the macro `$crate::format_args_nl` which comes from the expansion of the macro `println` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error: aborting due to 1 previous error
 
diff --git a/tests/ui/borrowck/issue-24267-flow-exit.stderr b/tests/ui/borrowck/issue-24267-flow-exit.stderr
index 216f8d49b1b0..e81f00f8c157 100644
--- a/tests/ui/borrowck/issue-24267-flow-exit.stderr
+++ b/tests/ui/borrowck/issue-24267-flow-exit.stderr
@@ -7,7 +7,6 @@ LL |     loop { x = break; }
 LL |     println!("{}", x);
    |                    ^ `x` used here but it isn't initialized
    |
-   = note: this error originates in the macro `$crate::format_args_nl` which comes from the expansion of the macro `println` (in Nightly builds, run with -Z macro-backtrace for more info)
 help: consider assigning a value
    |
 LL |     let x: i32 = 42;
@@ -22,7 +21,6 @@ LL |     for _ in 0..10 { x = continue; }
 LL |     println!("{}", x);
    |                    ^ `x` used here but it isn't initialized
    |
-   = note: this error originates in the macro `$crate::format_args_nl` which comes from the expansion of the macro `println` (in Nightly builds, run with -Z macro-backtrace for more info)
 help: consider assigning a value
    |
 LL |     let x: i32 = 42;
diff --git a/tests/ui/borrowck/issue-47646.stderr b/tests/ui/borrowck/issue-47646.stderr
index cfe6f3f39938..c8d48b76757a 100644
--- a/tests/ui/borrowck/issue-47646.stderr
+++ b/tests/ui/borrowck/issue-47646.stderr
@@ -12,8 +12,6 @@ LL |             println!("{:?}", heap);
 ...
 LL |     };
    |      - ... and the mutable borrow might be used here, when that temporary is dropped and runs the destructor for type `(Option<std::collections::binary_heap::PeekMut<'_, i32>>, ())`
-   |
-   = note: this error originates in the macro `$crate::format_args_nl` which comes from the expansion of the macro `println` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error: aborting due to 1 previous error
 
diff --git a/tests/ui/borrowck/issue-64453.stderr b/tests/ui/borrowck/issue-64453.stderr
index 29a7363705cd..9136d6a7dc33 100644
--- a/tests/ui/borrowck/issue-64453.stderr
+++ b/tests/ui/borrowck/issue-64453.stderr
@@ -8,7 +8,6 @@ note: function `format` is not const
   --> $SRC_DIR/alloc/src/fmt.rs:LL:COL
    = note: calls in statics are limited to constant functions, tuple structs and tuple variants
    = note: consider wrapping this expression in `std::sync::LazyLock::new(|| ...)`
-   = note: this error originates in the macro `format` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error[E0507]: cannot move out of static item `settings_dir`
   --> $DIR/issue-64453.rs:13:37
diff --git a/tests/ui/borrowck/ownership-struct-update-moved-error.stderr b/tests/ui/borrowck/ownership-struct-update-moved-error.stderr
index 83cfc7bb412c..f081bea76b7a 100644
--- a/tests/ui/borrowck/ownership-struct-update-moved-error.stderr
+++ b/tests/ui/borrowck/ownership-struct-update-moved-error.stderr
@@ -13,7 +13,6 @@ note: `Mine::make_string_bar` takes ownership of the receiver `self`, which move
    |
 LL |     fn make_string_bar(mut self) -> Mine {
    |                            ^^^^
-   = note: this error originates in the macro `$crate::format_args_nl` which comes from the expansion of the macro `println` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error: aborting due to 1 previous error
 
diff --git a/tests/ui/borrowck/suggest-assign-rvalue.stderr b/tests/ui/borrowck/suggest-assign-rvalue.stderr
index daaef6e3892d..6ae893915aa9 100644
--- a/tests/ui/borrowck/suggest-assign-rvalue.stderr
+++ b/tests/ui/borrowck/suggest-assign-rvalue.stderr
@@ -19,7 +19,6 @@ LL |     let my_float: f32;
 LL |     println!("my_float: {}", my_float);
    |                              ^^^^^^^^ `my_float` used here but it isn't initialized
    |
-   = note: this error originates in the macro `$crate::format_args_nl` which comes from the expansion of the macro `println` (in Nightly builds, run with -Z macro-backtrace for more info)
 help: consider assigning a value
    |
 LL |     let my_float: f32 = 3.14159;
@@ -33,7 +32,6 @@ LL |     let demo: Demo;
 LL |     println!("demo: {:?}", demo);
    |                            ^^^^ `demo` used here but it isn't initialized
    |
-   = note: this error originates in the macro `$crate::format_args_nl` which comes from the expansion of the macro `println` (in Nightly builds, run with -Z macro-backtrace for more info)
 help: consider assigning a value
    |
 LL |     let demo: Demo = Default::default();
@@ -47,7 +45,6 @@ LL |     let demo_no: DemoNoDef;
 LL |     println!("demo_no: {:?}", demo_no);
    |                               ^^^^^^^ `demo_no` used here but it isn't initialized
    |
-   = note: this error originates in the macro `$crate::format_args_nl` which comes from the expansion of the macro `println` (in Nightly builds, run with -Z macro-backtrace for more info)
 help: consider assigning a value
    |
 LL |     let demo_no: DemoNoDef = /* value */;
@@ -61,7 +58,6 @@ LL |     let arr: [i32; 5];
 LL |     println!("arr: {:?}", arr);
    |                           ^^^ `arr` used here but it isn't initialized
    |
-   = note: this error originates in the macro `$crate::format_args_nl` which comes from the expansion of the macro `println` (in Nightly builds, run with -Z macro-backtrace for more info)
 help: consider assigning a value
    |
 LL |     let arr: [i32; 5] = [42; 5];
@@ -75,7 +71,6 @@ LL |     let foo: Vec<&str>;
 LL |     println!("foo: {:?}", foo);
    |                           ^^^ `foo` used here but it isn't initialized
    |
-   = note: this error originates in the macro `$crate::format_args_nl` which comes from the expansion of the macro `println` (in Nightly builds, run with -Z macro-backtrace for more info)
 help: consider assigning a value
    |
 LL |     let foo: Vec<&str> = vec![];
@@ -89,7 +84,6 @@ LL |     let my_string: String;
 LL |     println!("my_string: {}", my_string);
    |                               ^^^^^^^^^ `my_string` used here but it isn't initialized
    |
-   = note: this error originates in the macro `$crate::format_args_nl` which comes from the expansion of the macro `println` (in Nightly builds, run with -Z macro-backtrace for more info)
 help: consider assigning a value
    |
 LL |     let my_string: String = Default::default();
@@ -103,7 +97,6 @@ LL |     let my_int: &i32;
 LL |     println!("my_int: {}", *my_int);
    |                            ^^^^^^^ `*my_int` used here but it isn't initialized
    |
-   = note: this error originates in the macro `$crate::format_args_nl` which comes from the expansion of the macro `println` (in Nightly builds, run with -Z macro-backtrace for more info)
 help: consider assigning a value
    |
 LL |     let my_int: &i32 = &42;
@@ -117,7 +110,6 @@ LL |     let hello: &str;
 LL |     println!("hello: {}", hello);
    |                           ^^^^^ `hello` used here but it isn't initialized
    |
-   = note: this error originates in the macro `$crate::format_args_nl` which comes from the expansion of the macro `println` (in Nightly builds, run with -Z macro-backtrace for more info)
 help: consider assigning a value
    |
 LL |     let hello: &str = "";
@@ -130,8 +122,6 @@ LL |     let never: !;
    |         ----- binding declared here but left uninitialized
 LL |     println!("never: {}", never);
    |                           ^^^^^ `never` used here but it isn't initialized
-   |
-   = note: this error originates in the macro `$crate::format_args_nl` which comes from the expansion of the macro `println` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error: aborting due to 10 previous errors
 
diff --git a/tests/ui/closures/2229_closure_analysis/diagnostics/arrays.stderr b/tests/ui/closures/2229_closure_analysis/diagnostics/arrays.stderr
index 97ecdfab8205..4249dea10a36 100644
--- a/tests/ui/closures/2229_closure_analysis/diagnostics/arrays.stderr
+++ b/tests/ui/closures/2229_closure_analysis/diagnostics/arrays.stderr
@@ -53,8 +53,6 @@ LL |     println!("{}", arr[3]);
 ...
 LL |     c();
    |     - mutable borrow later used here
-   |
-   = note: this error originates in the macro `$crate::format_args_nl` which comes from the expansion of the macro `println` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error[E0502]: cannot borrow `arr` as immutable because it is also borrowed as mutable
   --> $DIR/arrays.rs:71:24
diff --git a/tests/ui/closures/2229_closure_analysis/diagnostics/box.stderr b/tests/ui/closures/2229_closure_analysis/diagnostics/box.stderr
index 2e3259e64059..09143f44dc83 100644
--- a/tests/ui/closures/2229_closure_analysis/diagnostics/box.stderr
+++ b/tests/ui/closures/2229_closure_analysis/diagnostics/box.stderr
@@ -25,8 +25,6 @@ LL |     println!("{}", e.0.0.m.x);
 LL |
 LL |     c();
    |     - mutable borrow later used here
-   |
-   = note: this error originates in the macro `$crate::format_args_nl` which comes from the expansion of the macro `println` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error[E0506]: cannot assign to `e.0.0.m.x` because it is borrowed
   --> $DIR/box.rs:55:5
diff --git a/tests/ui/closures/2229_closure_analysis/diagnostics/repr_packed.stderr b/tests/ui/closures/2229_closure_analysis/diagnostics/repr_packed.stderr
index 0e93e033c022..f59be6b7a720 100644
--- a/tests/ui/closures/2229_closure_analysis/diagnostics/repr_packed.stderr
+++ b/tests/ui/closures/2229_closure_analysis/diagnostics/repr_packed.stderr
@@ -7,7 +7,6 @@ LL |         println!("{}", foo.x);
    = note: this struct is 1-byte aligned, but the type of this field may require higher alignment
    = note: creating a misaligned reference is undefined behavior (even if that reference is never dereferenced)
    = help: copy the field contents to a local variable, or replace the reference with a raw pointer and use `read_unaligned`/`write_unaligned` (loads and stores via `*p` must be properly aligned even when using raw pointers)
-   = note: this error originates in the macro `$crate::format_args_nl` which comes from the expansion of the macro `println` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error: aborting due to 1 previous error
 
diff --git a/tests/ui/closures/2229_closure_analysis/diagnostics/simple-struct-min-capture.stderr b/tests/ui/closures/2229_closure_analysis/diagnostics/simple-struct-min-capture.stderr
index 68fdb3ce131f..406f7c63b734 100644
--- a/tests/ui/closures/2229_closure_analysis/diagnostics/simple-struct-min-capture.stderr
+++ b/tests/ui/closures/2229_closure_analysis/diagnostics/simple-struct-min-capture.stderr
@@ -13,8 +13,6 @@ LL |     println!("{:?}", p);
 LL |
 LL |     c();
    |     - mutable borrow later used here
-   |
-   = note: this error originates in the macro `$crate::format_args_nl` which comes from the expansion of the macro `println` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error: aborting due to 1 previous error
 
diff --git a/tests/ui/closures/issue-111932.stderr b/tests/ui/closures/issue-111932.stderr
index fc3b7b0c6e66..2d10a2657aa0 100644
--- a/tests/ui/closures/issue-111932.stderr
+++ b/tests/ui/closures/issue-111932.stderr
@@ -17,7 +17,6 @@ LL |         println!("{:?}", foo);
    |                   required by this formatting parameter
    |
    = help: the trait `Sized` is not implemented for `dyn Foo`
-   = note: this error originates in the macro `$crate::format_args_nl` which comes from the expansion of the macro `println` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error: aborting due to 2 previous errors
 
diff --git a/tests/ui/codemap_tests/bad-format-args.stderr b/tests/ui/codemap_tests/bad-format-args.stderr
index 8f79beaa9e1b..ef0fa5f481e5 100644
--- a/tests/ui/codemap_tests/bad-format-args.stderr
+++ b/tests/ui/codemap_tests/bad-format-args.stderr
@@ -3,8 +3,6 @@ error: requires at least a format string argument
    |
 LL |     format!();
    |     ^^^^^^^^^
-   |
-   = note: this error originates in the macro `$crate::__export::format_args` which comes from the expansion of the macro `format` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error: expected `,`, found `1`
   --> $DIR/bad-format-args.rs:3:16
diff --git a/tests/ui/codemap_tests/tab_3.stderr b/tests/ui/codemap_tests/tab_3.stderr
index 7ae21a57052f..2a0a9e2d48f3 100644
--- a/tests/ui/codemap_tests/tab_3.stderr
+++ b/tests/ui/codemap_tests/tab_3.stderr
@@ -11,7 +11,6 @@ LL |         println!("{:?}", some_vec);
    |
 note: `into_iter` takes ownership of the receiver `self`, which moves `some_vec`
   --> $SRC_DIR/core/src/iter/traits/collect.rs:LL:COL
-   = note: this error originates in the macro `$crate::format_args_nl` which comes from the expansion of the macro `println` (in Nightly builds, run with -Z macro-backtrace for more info)
 help: you can `clone` the value and consume it, but this might not be your desired behavior
    |
 LL |     some_vec.clone().into_iter();
diff --git a/tests/ui/const-generics/vec-macro-in-static-array.stderr b/tests/ui/const-generics/vec-macro-in-static-array.stderr
index de21f2274f3a..63d7b0c89fa1 100644
--- a/tests/ui/const-generics/vec-macro-in-static-array.stderr
+++ b/tests/ui/const-generics/vec-macro-in-static-array.stderr
@@ -6,7 +6,6 @@ LL | static VEC: [u32; 256] = vec![];
    |
    = note: expected array `[u32; 256]`
              found struct `Vec<_>`
-   = note: this error originates in the macro `vec` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error: aborting due to 1 previous error
 
diff --git a/tests/ui/consts/const-eval/const_panic.stderr b/tests/ui/consts/const-eval/const_panic.stderr
index a2036e834b0b..8e0384b2f2af 100644
--- a/tests/ui/consts/const-eval/const_panic.stderr
+++ b/tests/ui/consts/const-eval/const_panic.stderr
@@ -21,8 +21,6 @@ error[E0080]: evaluation panicked: not implemented
    |
 LL | const X: () = std::unimplemented!();
    |               ^^^^^^^^^^^^^^^^^^^^^ evaluation of `X` failed here
-   |
-   = note: this error originates in the macro `std::unimplemented` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error[E0080]: evaluation panicked: hello
   --> $DIR/const_panic.rs:19:15
@@ -59,8 +57,6 @@ error[E0080]: evaluation panicked: not implemented
    |
 LL | const X_CORE: () = core::unimplemented!();
    |                    ^^^^^^^^^^^^^^^^^^^^^^ evaluation of `X_CORE` failed here
-   |
-   = note: this error originates in the macro `core::unimplemented` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error[E0080]: evaluation panicked: hello
   --> $DIR/const_panic.rs:37:20
diff --git a/tests/ui/consts/const-eval/const_panic_2021.stderr b/tests/ui/consts/const-eval/const_panic_2021.stderr
index ba771a35d036..a0181ccca391 100644
--- a/tests/ui/consts/const-eval/const_panic_2021.stderr
+++ b/tests/ui/consts/const-eval/const_panic_2021.stderr
@@ -21,8 +21,6 @@ error[E0080]: evaluation panicked: not implemented
    |
 LL | const D: () = std::unimplemented!();
    |               ^^^^^^^^^^^^^^^^^^^^^ evaluation of `D` failed here
-   |
-   = note: this error originates in the macro `std::unimplemented` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error[E0080]: evaluation panicked: hello
   --> $DIR/const_panic_2021.rs:18:15
@@ -53,8 +51,6 @@ error[E0080]: evaluation panicked: not implemented
    |
 LL | const D_CORE: () = core::unimplemented!();
    |                    ^^^^^^^^^^^^^^^^^^^^^^ evaluation of `D_CORE` failed here
-   |
-   = note: this error originates in the macro `core::unimplemented` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error[E0080]: evaluation panicked: hello
   --> $DIR/const_panic_2021.rs:33:20
diff --git a/tests/ui/consts/const-eval/const_panic_libcore_bin.stderr b/tests/ui/consts/const-eval/const_panic_libcore_bin.stderr
index e07b172d426c..a9dc43caf76a 100644
--- a/tests/ui/consts/const-eval/const_panic_libcore_bin.stderr
+++ b/tests/ui/consts/const-eval/const_panic_libcore_bin.stderr
@@ -15,8 +15,6 @@ error[E0080]: evaluation panicked: not implemented
    |
 LL | const X: () = unimplemented!();
    |               ^^^^^^^^^^^^^^^^ evaluation of `X` failed here
-   |
-   = note: this error originates in the macro `unimplemented` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error: aborting due to 3 previous errors
 
diff --git a/tests/ui/consts/const-eval/format.stderr b/tests/ui/consts/const-eval/format.stderr
index 06bada8da011..67bef0ce6c35 100644
--- a/tests/ui/consts/const-eval/format.stderr
+++ b/tests/ui/consts/const-eval/format.stderr
@@ -13,7 +13,6 @@ LL |     println!("{:?}", 0);
    |     ^^^^^^^^^^^^^^^^^^^
    |
    = note: calls in constant functions are limited to constant functions, tuple structs and tuple variants
-   = note: this error originates in the macro `println` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error[E0015]: cannot call non-const function `std::io::_print` in constant functions
   --> $DIR/format.rs:7:5
@@ -24,7 +23,6 @@ LL |     println!("{:?}", 0);
 note: function `_print` is not const
   --> $SRC_DIR/std/src/io/stdio.rs:LL:COL
    = note: calls in constant functions are limited to constant functions, tuple structs and tuple variants
-   = note: this error originates in the macro `println` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error[E0015]: cannot call non-const formatting macro in constant functions
   --> $DIR/format.rs:13:5
diff --git a/tests/ui/consts/const-eval/issue-44578.stderr b/tests/ui/consts/const-eval/issue-44578.stderr
index fd0b9ae1e17d..7625664f9ed6 100644
--- a/tests/ui/consts/const-eval/issue-44578.stderr
+++ b/tests/ui/consts/const-eval/issue-44578.stderr
@@ -23,8 +23,6 @@ note: erroneous constant encountered
    |
 LL |     println!("{}", <Bar<u16, u8> as Foo>::AMT);
    |                    ^^^^^^^^^^^^^^^^^^^^^^^^^^
-   |
-   = note: this note originates in the macro `$crate::format_args_nl` which comes from the expansion of the macro `println` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 note: erroneous constant encountered
   --> $DIR/issue-44578.rs:26:20
@@ -33,7 +31,6 @@ LL |     println!("{}", <Bar<u16, u8> as Foo>::AMT);
    |                    ^^^^^^^^^^^^^^^^^^^^^^^^^^
    |
    = note: duplicate diagnostic emitted due to `-Z deduplicate-diagnostics=no`
-   = note: this note originates in the macro `$crate::format_args_nl` which comes from the expansion of the macro `println` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error: aborting due to 1 previous error
 
diff --git a/tests/ui/consts/control-flow/issue-50577.stderr b/tests/ui/consts/control-flow/issue-50577.stderr
index 96b11f71bb3e..6f62510c8801 100644
--- a/tests/ui/consts/control-flow/issue-50577.stderr
+++ b/tests/ui/consts/control-flow/issue-50577.stderr
@@ -3,8 +3,6 @@ error[E0308]: mismatched types
    |
 LL |         Drop = assert_eq!(1, 1),
    |                ^^^^^^^^^^^^^^^^ expected `isize`, found `()`
-   |
-   = note: this error originates in the macro `assert_eq` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error: aborting due to 1 previous error
 
diff --git a/tests/ui/consts/min_const_fn/bad_const_fn_body_ice.stderr b/tests/ui/consts/min_const_fn/bad_const_fn_body_ice.stderr
index 8e52a7aa35e1..f6ddb19f9634 100644
--- a/tests/ui/consts/min_const_fn/bad_const_fn_body_ice.stderr
+++ b/tests/ui/consts/min_const_fn/bad_const_fn_body_ice.stderr
@@ -3,8 +3,6 @@ error[E0010]: allocations are not allowed in constant functions
    |
 LL |     vec![1, 2, 3]
    |     ^^^^^^^^^^^^^ allocation not allowed in constant functions
-   |
-   = note: this error originates in the macro `vec` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error[E0015]: cannot call non-const method `slice::<impl [i32]>::into_vec::<std::alloc::Global>` in constant functions
   --> $DIR/bad_const_fn_body_ice.rs:2:5
@@ -13,7 +11,6 @@ LL |     vec![1, 2, 3]
    |     ^^^^^^^^^^^^^
    |
    = note: calls in constant functions are limited to constant functions, tuple structs and tuple variants
-   = note: this error originates in the macro `vec` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error: aborting due to 2 previous errors
 
diff --git a/tests/ui/consts/recursive-const-in-impl.stderr b/tests/ui/consts/recursive-const-in-impl.stderr
index ec5ad52fadd4..c53ce701566e 100644
--- a/tests/ui/consts/recursive-const-in-impl.stderr
+++ b/tests/ui/consts/recursive-const-in-impl.stderr
@@ -6,7 +6,6 @@ LL |     println!("{}", Thing::<i32>::X);
    |
    = help: consider increasing the recursion limit by adding a `#![recursion_limit = "14"]` attribute to your crate (`recursive_const_in_impl`)
    = note: query depth increased by 9 when simplifying constant for the type system `main::promoted[0]`
-   = note: this error originates in the macro `$crate::format_args_nl` which comes from the expansion of the macro `println` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error: aborting due to 1 previous error
 
diff --git a/tests/ui/coroutine/yield-while-ref-reborrowed.stderr b/tests/ui/coroutine/yield-while-ref-reborrowed.stderr
index 0b2cc92f4b4a..836360b87303 100644
--- a/tests/ui/coroutine/yield-while-ref-reborrowed.stderr
+++ b/tests/ui/coroutine/yield-while-ref-reborrowed.stderr
@@ -10,8 +10,6 @@ LL |     println!("{}", x);
    |                    ^ second borrow occurs here
 LL |     Pin::new(&mut b).resume(());
    |              ------ first borrow later used here
-   |
-   = note: this error originates in the macro `$crate::format_args_nl` which comes from the expansion of the macro `println` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error: aborting due to 1 previous error
 
diff --git a/tests/ui/delegation/ice-line-bounds-issue-148732.stderr b/tests/ui/delegation/ice-line-bounds-issue-148732.stderr
index f34ac0ea306c..83cc238b5e0c 100644
--- a/tests/ui/delegation/ice-line-bounds-issue-148732.stderr
+++ b/tests/ui/delegation/ice-line-bounds-issue-148732.stderr
@@ -3,8 +3,6 @@ error[E0106]: missing lifetime specifier
    |
 LL |     dbg!(b);
    |     ^^^^^^^ expected named lifetime parameter
-   |
-   = note: this error originates in the macro `$crate::macros::dbg_internal` which comes from the expansion of the macro `dbg` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error[E0425]: cannot find function `a` in this scope
   --> $DIR/ice-line-bounds-issue-148732.rs:1:7
@@ -37,7 +35,6 @@ LL |     dbg!(b);
    |     ^^^^^^^ the trait `Debug` is not implemented for fn item `fn() {b}`
    |
    = help: use parentheses to call this function: `b()`
-   = note: this error originates in the macro `$crate::macros::dbg_internal` which comes from the expansion of the macro `dbg` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error: aborting due to 4 previous errors
 
diff --git a/tests/ui/derives/nonsense-input-to-debug.stderr b/tests/ui/derives/nonsense-input-to-debug.stderr
index 7c97ca93cfc9..207d7b1969de 100644
--- a/tests/ui/derives/nonsense-input-to-debug.stderr
+++ b/tests/ui/derives/nonsense-input-to-debug.stderr
@@ -13,8 +13,6 @@ LL |     should_be_vec_t: vec![T],
    |                      expected type
    |                      in this macro invocation
    |                      this macro call doesn't expand to a type
-   |
-   = note: this error originates in the macro `vec` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error[E0392]: type parameter `T` is never used
   --> $DIR/nonsense-input-to-debug.rs:5:17
diff --git a/tests/ui/error-codes/E0010-teach.stderr b/tests/ui/error-codes/E0010-teach.stderr
index 82bbe01aef79..9318e8df7e25 100644
--- a/tests/ui/error-codes/E0010-teach.stderr
+++ b/tests/ui/error-codes/E0010-teach.stderr
@@ -5,7 +5,6 @@ LL | const CON: Vec<i32> = vec![1, 2, 3];
    |                       ^^^^^^^^^^^^^ allocation not allowed in constants
    |
    = note: The runtime heap is not yet available at compile-time, so no runtime heap allocations can be created.
-   = note: this error originates in the macro `vec` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error[E0015]: cannot call non-const method `slice::<impl [i32]>::into_vec::<std::alloc::Global>` in constants
   --> $DIR/E0010-teach.rs:5:23
@@ -14,7 +13,6 @@ LL | const CON: Vec<i32> = vec![1, 2, 3];
    |                       ^^^^^^^^^^^^^
    |
    = note: calls in constants are limited to constant functions, tuple structs and tuple variants
-   = note: this error originates in the macro `vec` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error: aborting due to 2 previous errors
 
diff --git a/tests/ui/error-codes/E0010.stderr b/tests/ui/error-codes/E0010.stderr
index 87b722b5f656..d08b7f90afb4 100644
--- a/tests/ui/error-codes/E0010.stderr
+++ b/tests/ui/error-codes/E0010.stderr
@@ -3,8 +3,6 @@ error[E0010]: allocations are not allowed in constants
    |
 LL | const CON: Vec<i32> = vec![1, 2, 3];
    |                       ^^^^^^^^^^^^^ allocation not allowed in constants
-   |
-   = note: this error originates in the macro `vec` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error[E0015]: cannot call non-const method `slice::<impl [i32]>::into_vec::<std::alloc::Global>` in constants
   --> $DIR/E0010.rs:3:23
@@ -13,7 +11,6 @@ LL | const CON: Vec<i32> = vec![1, 2, 3];
    |                       ^^^^^^^^^^^^^
    |
    = note: calls in constants are limited to constant functions, tuple structs and tuple variants
-   = note: this error originates in the macro `vec` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error: aborting due to 2 previous errors
 
diff --git a/tests/ui/errors/span-format_args-issue-140578.stderr b/tests/ui/errors/span-format_args-issue-140578.stderr
index 6a273e5cd515..b5394b6c33af 100644
--- a/tests/ui/errors/span-format_args-issue-140578.stderr
+++ b/tests/ui/errors/span-format_args-issue-140578.stderr
@@ -3,40 +3,30 @@ error[E0282]: type annotations needed
    |
 LL |   print!("{:?} {a} {a:?}", [], a = 1 + 1);
    |                            ^^ cannot infer type
-   |
-   = note: this error originates in the macro `$crate::format_args` which comes from the expansion of the macro `print` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error[E0282]: type annotations needed
   --> $DIR/span-format_args-issue-140578.rs:7:30
    |
 LL |   println!("{:?} {a} {a:?}", [], a = 1 + 1);
    |                              ^^ cannot infer type
-   |
-   = note: this error originates in the macro `$crate::format_args_nl` which comes from the expansion of the macro `println` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error[E0282]: type annotations needed
   --> $DIR/span-format_args-issue-140578.rs:12:35
    |
 LL |   println!("{:?} {:?} {a} {a:?}", [], [], a = 1 + 1);
    |                                   ^^ cannot infer type
-   |
-   = note: this error originates in the macro `$crate::format_args_nl` which comes from the expansion of the macro `println` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error[E0282]: type annotations needed
   --> $DIR/span-format_args-issue-140578.rs:17:41
    |
 LL |   println!("{:?} {:?} {a} {a:?} {b:?}", [], [], a = 1 + 1, b = []);
    |                                         ^^ cannot infer type
-   |
-   = note: this error originates in the macro `$crate::format_args_nl` which comes from the expansion of the macro `println` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error[E0282]: type annotations needed
   --> $DIR/span-format_args-issue-140578.rs:26:9
    |
 LL |         [],
    |         ^^ cannot infer type
-   |
-   = note: this error originates in the macro `$crate::format_args_nl` which comes from the expansion of the macro `println` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error: aborting due to 5 previous errors
 
diff --git a/tests/ui/expr/if/assert-macro-without-else.stderr b/tests/ui/expr/if/assert-macro-without-else.stderr
index 74179ba899f5..98f22607bea7 100644
--- a/tests/ui/expr/if/assert-macro-without-else.stderr
+++ b/tests/ui/expr/if/assert-macro-without-else.stderr
@@ -11,16 +11,12 @@ error[E0308]: mismatched types
    |
 LL |     assert_eq!(1, 1)
    |     ^^^^^^^^^^^^^^^^ expected `i32`, found `()`
-   |
-   = note: this error originates in the macro `assert_eq` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error[E0308]: mismatched types
   --> $DIR/assert-macro-without-else.rs:14:5
    |
 LL |     assert_ne!(1, 2)
    |     ^^^^^^^^^^^^^^^^ expected `bool`, found `()`
-   |
-   = note: this error originates in the macro `assert_ne` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error[E0308]: mismatched types
   --> $DIR/assert-macro-without-else.rs:26:9
diff --git a/tests/ui/feature-gates/feature-gate-global-registration.stderr b/tests/ui/feature-gates/feature-gate-global-registration.stderr
index 70538ae6f317..5da1721d99dd 100644
--- a/tests/ui/feature-gates/feature-gate-global-registration.stderr
+++ b/tests/ui/feature-gates/feature-gate-global-registration.stderr
@@ -6,8 +6,6 @@ LL | todo!();
    | |
    | expected one of `!` or `::`
    | in this macro invocation
-   |
-   = note: this error originates in the macro `todo` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error: aborting due to 1 previous error
 
diff --git a/tests/ui/fmt/format-args-argument-span.stderr b/tests/ui/fmt/format-args-argument-span.stderr
index d46cfb438cf6..a486abe821b7 100644
--- a/tests/ui/fmt/format-args-argument-span.stderr
+++ b/tests/ui/fmt/format-args-argument-span.stderr
@@ -6,7 +6,6 @@ LL |     println!("{x:?} {x} {x:?}");
    |
    = help: the trait `std::fmt::Display` is not implemented for `Option<{integer}>`
    = note: in format strings you may be able to use `{:?}` (or {:#?} for pretty-print) instead
-   = note: this error originates in the macro `$crate::format_args_nl` which comes from the expansion of the macro `println` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error[E0277]: `Option<{integer}>` doesn't implement `std::fmt::Display`
   --> $DIR/format-args-argument-span.rs:15:37
@@ -18,7 +17,6 @@ LL |     println!("{x:?} {x} {x:?}", x = Some(1));
    |
    = help: the trait `std::fmt::Display` is not implemented for `Option<{integer}>`
    = note: in format strings you may be able to use `{:?}` (or {:#?} for pretty-print) instead
-   = note: this error originates in the macro `$crate::format_args_nl` which comes from the expansion of the macro `println` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error[E0277]: `DisplayOnly` doesn't implement `Debug`
   --> $DIR/format-args-argument-span.rs:18:19
@@ -28,7 +26,6 @@ LL |     println!("{x} {x:?} {x}");
    |
    = help: the trait `Debug` is not implemented for `DisplayOnly`
    = note: add `#[derive(Debug)]` to `DisplayOnly` or manually `impl Debug for DisplayOnly`
-   = note: this error originates in the macro `$crate::format_args_nl` which comes from the expansion of the macro `println` (in Nightly builds, run with -Z macro-backtrace for more info)
 help: consider annotating `DisplayOnly` with `#[derive(Debug)]`
    |
 LL + #[derive(Debug)]
@@ -45,7 +42,6 @@ LL |     println!("{x} {x:?} {x}", x = DisplayOnly);
    |
    = help: the trait `Debug` is not implemented for `DisplayOnly`
    = note: add `#[derive(Debug)]` to `DisplayOnly` or manually `impl Debug for DisplayOnly`
-   = note: this error originates in the macro `$crate::format_args_nl` which comes from the expansion of the macro `println` (in Nightly builds, run with -Z macro-backtrace for more info)
 help: consider annotating `DisplayOnly` with `#[derive(Debug)]`
    |
 LL + #[derive(Debug)]
diff --git a/tests/ui/fmt/ifmt-bad-arg.stderr b/tests/ui/fmt/ifmt-bad-arg.stderr
index b565b836f211..9018482e7078 100644
--- a/tests/ui/fmt/ifmt-bad-arg.stderr
+++ b/tests/ui/fmt/ifmt-bad-arg.stderr
@@ -320,7 +320,6 @@ LL |     println!("{} {:.*} {}", 1, 3.2, 4);
               found reference `&{float}`
 note: associated function defined here
   --> $SRC_DIR/core/src/fmt/rt.rs:LL:COL
-   = note: this error originates in the macro `$crate::format_args_nl` which comes from the expansion of the macro `println` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error[E0308]: mismatched types
   --> $DIR/ifmt-bad-arg.rs:81:35
@@ -334,7 +333,6 @@ LL |     println!("{} {:07$.*} {}", 1, 3.2, 4);
               found reference `&{float}`
 note: associated function defined here
   --> $SRC_DIR/core/src/fmt/rt.rs:LL:COL
-   = note: this error originates in the macro `$crate::format_args_nl` which comes from the expansion of the macro `println` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error: aborting due to 38 previous errors
 
diff --git a/tests/ui/fmt/ifmt-unimpl.stderr b/tests/ui/fmt/ifmt-unimpl.stderr
index 5e80f892dcb5..5e97e69c7cf3 100644
--- a/tests/ui/fmt/ifmt-unimpl.stderr
+++ b/tests/ui/fmt/ifmt-unimpl.stderr
@@ -17,7 +17,6 @@ LL |     format!("{:X}", "3");
              i32
            and 9 others
    = note: required for `&str` to implement `UpperHex`
-   = note: this error originates in the macro `$crate::__export::format_args` which comes from the expansion of the macro `format` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error: aborting due to 1 previous error
 
diff --git a/tests/ui/fmt/non-source-literals.stderr b/tests/ui/fmt/non-source-literals.stderr
index 5f042e1e631a..953a4a64fd8d 100644
--- a/tests/ui/fmt/non-source-literals.stderr
+++ b/tests/ui/fmt/non-source-literals.stderr
@@ -10,7 +10,6 @@ help: the trait `std::fmt::Display` is not implemented for `NonDisplay`
 LL | pub struct NonDisplay;
    | ^^^^^^^^^^^^^^^^^^^^^
    = note: in format strings you may be able to use `{:?}` (or {:#?} for pretty-print) instead
-   = note: this error originates in the macro `$crate::__export::format_args` which comes from the expansion of the macro `format` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error[E0277]: `NonDisplay` doesn't implement `std::fmt::Display`
   --> $DIR/non-source-literals.rs:10:45
@@ -24,7 +23,6 @@ help: the trait `std::fmt::Display` is not implemented for `NonDisplay`
 LL | pub struct NonDisplay;
    | ^^^^^^^^^^^^^^^^^^^^^
    = note: in format strings you may be able to use `{:?}` (or {:#?} for pretty-print) instead
-   = note: this error originates in the macro `$crate::__export::format_args` which comes from the expansion of the macro `format` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error[E0277]: `NonDebug` doesn't implement `Debug`
   --> $DIR/non-source-literals.rs:11:42
@@ -34,7 +32,6 @@ LL |     let _ = format!(concat!("{:", "?}"), NonDebug);
    |
    = help: the trait `Debug` is not implemented for `NonDebug`
    = note: add `#[derive(Debug)]` to `NonDebug` or manually `impl Debug for NonDebug`
-   = note: this error originates in the macro `$crate::__export::format_args` which comes from the expansion of the macro `format` (in Nightly builds, run with -Z macro-backtrace for more info)
 help: consider annotating `NonDebug` with `#[derive(Debug)]`
    |
 LL + #[derive(Debug)]
@@ -49,7 +46,6 @@ LL |     let _ = format!(concat!("{", "0", ":?}"), NonDebug);
    |
    = help: the trait `Debug` is not implemented for `NonDebug`
    = note: add `#[derive(Debug)]` to `NonDebug` or manually `impl Debug for NonDebug`
-   = note: this error originates in the macro `$crate::__export::format_args` which comes from the expansion of the macro `format` (in Nightly builds, run with -Z macro-backtrace for more info)
 help: consider annotating `NonDebug` with `#[derive(Debug)]`
    |
 LL + #[derive(Debug)]
diff --git a/tests/ui/impl-trait/precise-capturing/migration-note.stderr b/tests/ui/impl-trait/precise-capturing/migration-note.stderr
index 880e7878477a..fef0a85bf1ae 100644
--- a/tests/ui/impl-trait/precise-capturing/migration-note.stderr
+++ b/tests/ui/impl-trait/precise-capturing/migration-note.stderr
@@ -282,7 +282,6 @@ note: this call may capture more lifetimes than intended, because Rust 2024 has
    |
 LL |     let x = { let x = display_len(&mut vec![0]); x };
    |                       ^^^^^^^^^^^^^^^^^^^^^^^^^
-   = note: this error originates in the macro `vec` (in Nightly builds, run with -Z macro-backtrace for more info)
 help: use the precise capturing `use<...>` syntax to make the captures explicit
    |
 LL | fn display_len<T>(x: &Vec<T>) -> impl Display + use<T> {
diff --git a/tests/ui/inference/need_type_info/issue-107745-avoid-expr-from-macro-expansion.stderr b/tests/ui/inference/need_type_info/issue-107745-avoid-expr-from-macro-expansion.stderr
index 3de317d2af6d..ff668f88d4d1 100644
--- a/tests/ui/inference/need_type_info/issue-107745-avoid-expr-from-macro-expansion.stderr
+++ b/tests/ui/inference/need_type_info/issue-107745-avoid-expr-from-macro-expansion.stderr
@@ -3,8 +3,6 @@ error[E0282]: type annotations needed
    |
 LL |     println!("{:?}", []);
    |                      ^^ cannot infer type
-   |
-   = note: this error originates in the macro `$crate::format_args_nl` which comes from the expansion of the macro `println` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error: aborting due to 1 previous error
 
diff --git a/tests/ui/issues/issue-42796.stderr b/tests/ui/issues/issue-42796.stderr
index 670b98c77089..0e7ce9e98c4d 100644
--- a/tests/ui/issues/issue-42796.stderr
+++ b/tests/ui/issues/issue-42796.stderr
@@ -9,7 +9,6 @@ LL |     let mut s_copy = s;
 LL |     println!("{}", s);
    |                    ^ value borrowed here after move
    |
-   = note: this error originates in the macro `$crate::format_args_nl` which comes from the expansion of the macro `println` (in Nightly builds, run with -Z macro-backtrace for more info)
 help: consider cloning the value if the performance cost is acceptable
    |
 LL |     let mut s_copy = s.clone();
diff --git a/tests/ui/iterators/iter-macro-not-async-closure.stderr b/tests/ui/iterators/iter-macro-not-async-closure.stderr
index 2f0343a2d0d6..906ebd482fb6 100644
--- a/tests/ui/iterators/iter-macro-not-async-closure.stderr
+++ b/tests/ui/iterators/iter-macro-not-async-closure.stderr
@@ -35,7 +35,6 @@ note: required by a bound in `call_async_once`
    |
 LL | async fn call_async_once(f: impl AsyncFnOnce()) {
    |                                  ^^^^^^^^^^^^^ required by this bound in `call_async_once`
-   = note: this error originates in the macro `pin` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error[E0277]: the trait bound `{gen closure@$DIR/iter-macro-not-async-closure.rs:19:21: 19:28}: AsyncFnOnce()` is not satisfied
   --> $DIR/iter-macro-not-async-closure.rs:25:13
@@ -48,7 +47,6 @@ note: required by a bound in `call_async_once`
    |
 LL | async fn call_async_once(f: impl AsyncFnOnce()) {
    |                                  ^^^^^^^^^^^^^ required by this bound in `call_async_once`
-   = note: this error originates in the macro `pin` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error[E0277]: the trait bound `{gen closure@$DIR/iter-macro-not-async-closure.rs:19:21: 19:28}: AsyncFnOnce()` is not satisfied
   --> $DIR/iter-macro-not-async-closure.rs:30:5
diff --git a/tests/ui/lifetimes/borrowck-let-suggestion.stderr b/tests/ui/lifetimes/borrowck-let-suggestion.stderr
index 4703d7f10dc2..6a35f61708d2 100644
--- a/tests/ui/lifetimes/borrowck-let-suggestion.stderr
+++ b/tests/ui/lifetimes/borrowck-let-suggestion.stderr
@@ -9,7 +9,6 @@ LL |
 LL |     x.use_mut();
    |     - borrow later used here
    |
-   = note: this error originates in the macro `vec` (in Nightly builds, run with -Z macro-backtrace for more info)
 help: consider consuming the `Vec<i32>` when turning it into an `Iterator`
    |
 LL |     let mut x = vec![1].into_iter();
diff --git a/tests/ui/lint/dead-code/closure-bang.stderr b/tests/ui/lint/dead-code/closure-bang.stderr
index a0f5962dfe02..c2f83c17179c 100644
--- a/tests/ui/lint/dead-code/closure-bang.stderr
+++ b/tests/ui/lint/dead-code/closure-bang.stderr
@@ -11,7 +11,6 @@ note: the lint level is defined here
    |
 LL | #![deny(unreachable_code)]
    |         ^^^^^^^^^^^^^^^^
-   = note: this error originates in the macro `println` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error: aborting due to 1 previous error
 
diff --git a/tests/ui/lint/fn-ptr-comparisons-some.stderr b/tests/ui/lint/fn-ptr-comparisons-some.stderr
index 522c4399bce1..8674ce5e4a88 100644
--- a/tests/ui/lint/fn-ptr-comparisons-some.stderr
+++ b/tests/ui/lint/fn-ptr-comparisons-some.stderr
@@ -18,7 +18,6 @@ LL |     assert_eq!(Some::<FnPtr>(func), Some(func as unsafe extern "C" fn()));
    = note: the address of the same function can vary between different codegen units
    = note: furthermore, different functions could have the same address after being merged together
    = note: for more information visit <https://doc.rust-lang.org/nightly/core/ptr/fn.fn_addr_eq.html>
-   = note: this warning originates in the macro `assert_eq` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 warning: 2 warnings emitted
 
diff --git a/tests/ui/lint/fn-ptr-comparisons-weird.stderr b/tests/ui/lint/fn-ptr-comparisons-weird.stderr
index 2014e519c253..3c76e05016f5 100644
--- a/tests/ui/lint/fn-ptr-comparisons-weird.stderr
+++ b/tests/ui/lint/fn-ptr-comparisons-weird.stderr
@@ -61,7 +61,6 @@ LL |     let _ = assert_eq!(g, g);
    = note: the address of the same function can vary between different codegen units
    = note: furthermore, different functions could have the same address after being merged together
    = note: for more information visit <https://doc.rust-lang.org/nightly/core/ptr/fn.fn_addr_eq.html>
-   = note: this warning originates in the macro `assert_eq` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 warning: function pointer comparisons do not produce meaningful results since their addresses are not guaranteed to be unique
   --> $DIR/fn-ptr-comparisons-weird.rs:35:13
@@ -72,7 +71,6 @@ LL |     let _ = assert_ne!(g, g);
    = note: the address of the same function can vary between different codegen units
    = note: furthermore, different functions could have the same address after being merged together
    = note: for more information visit <https://doc.rust-lang.org/nightly/core/ptr/fn.fn_addr_eq.html>
-   = note: this warning originates in the macro `assert_ne` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 warning: 7 warnings emitted
 
diff --git a/tests/ui/liveness/liveness-move-in-while.stderr b/tests/ui/liveness/liveness-move-in-while.stderr
index dc48c4cc9acf..1bb97ad68c7c 100644
--- a/tests/ui/liveness/liveness-move-in-while.stderr
+++ b/tests/ui/liveness/liveness-move-in-while.stderr
@@ -35,7 +35,6 @@ LL |         while true { while true { while true { x = y; x.clone(); } } }
    |         |            inside of this loop
    |         inside of this loop
    |
-   = note: this error originates in the macro `$crate::format_args_nl` which comes from the expansion of the macro `println` (in Nightly builds, run with -Z macro-backtrace for more info)
 help: consider cloning the value if the performance cost is acceptable
    |
 LL |         while true { while true { while true { x = y.clone(); x.clone(); } } }
diff --git a/tests/ui/liveness/liveness-use-after-move.stderr b/tests/ui/liveness/liveness-use-after-move.stderr
index eab51edca37f..a94ceae79d56 100644
--- a/tests/ui/liveness/liveness-use-after-move.stderr
+++ b/tests/ui/liveness/liveness-use-after-move.stderr
@@ -9,7 +9,6 @@ LL |
 LL |     println!("{}", *x);
    |                    ^^ value borrowed here after move
    |
-   = note: this error originates in the macro `$crate::format_args_nl` which comes from the expansion of the macro `println` (in Nightly builds, run with -Z macro-backtrace for more info)
 help: consider cloning the value if the performance cost is acceptable
    |
 LL |     let y = x.clone();
diff --git a/tests/ui/liveness/liveness-use-after-send.stderr b/tests/ui/liveness/liveness-use-after-send.stderr
index 2323451a7d2d..da682325347c 100644
--- a/tests/ui/liveness/liveness-use-after-send.stderr
+++ b/tests/ui/liveness/liveness-use-after-send.stderr
@@ -13,7 +13,6 @@ note: consider changing this parameter type in function `send` to borrow instead
    |
 LL | fn send<T:Send + std::fmt::Debug>(ch: Chan<T>, data: T) {
    |    ---- in this function                             ^ this parameter takes ownership of the value
-   = note: this error originates in the macro `$crate::format_args_nl` which comes from the expansion of the macro `println` (in Nightly builds, run with -Z macro-backtrace for more info)
 help: consider cloning the value if the performance cost is acceptable
    |
 LL |     send(ch, message.clone());
diff --git a/tests/ui/loops/loop-proper-liveness.stderr b/tests/ui/loops/loop-proper-liveness.stderr
index cd4c064bcd19..5432043c7d24 100644
--- a/tests/ui/loops/loop-proper-liveness.stderr
+++ b/tests/ui/loops/loop-proper-liveness.stderr
@@ -7,7 +7,6 @@ LL |     let x: i32;
 LL |     println!("{:?}", x);
    |                      ^ `x` used here but it isn't initialized
    |
-   = note: this error originates in the macro `$crate::format_args_nl` which comes from the expansion of the macro `println` (in Nightly builds, run with -Z macro-backtrace for more info)
 help: consider assigning a value
    |
 LL |     let x: i32 = 42;
diff --git a/tests/ui/macros/assert.with-generic-asset.stderr b/tests/ui/macros/assert.with-generic-asset.stderr
index 51d8f28a35c3..523346830662 100644
--- a/tests/ui/macros/assert.with-generic-asset.stderr
+++ b/tests/ui/macros/assert.with-generic-asset.stderr
@@ -15,8 +15,6 @@ error: macro requires a boolean expression as an argument
    |
 LL |     debug_assert!();
    |     ^^^^^^^^^^^^^^^ boolean expression required
-   |
-   = note: this error originates in the macro `debug_assert` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error: expected expression, found keyword `struct`
   --> $DIR/assert.rs:8:19
diff --git a/tests/ui/macros/assert.without-generic-asset.stderr b/tests/ui/macros/assert.without-generic-asset.stderr
index 51d8f28a35c3..523346830662 100644
--- a/tests/ui/macros/assert.without-generic-asset.stderr
+++ b/tests/ui/macros/assert.without-generic-asset.stderr
@@ -15,8 +15,6 @@ error: macro requires a boolean expression as an argument
    |
 LL |     debug_assert!();
    |     ^^^^^^^^^^^^^^^ boolean expression required
-   |
-   = note: this error originates in the macro `debug_assert` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error: expected expression, found keyword `struct`
   --> $DIR/assert.rs:8:19
diff --git a/tests/ui/macros/failed-to-reparse-issue-139445.stderr b/tests/ui/macros/failed-to-reparse-issue-139445.stderr
index 6f7d88fb3446..fc3a2645e25e 100644
--- a/tests/ui/macros/failed-to-reparse-issue-139445.stderr
+++ b/tests/ui/macros/failed-to-reparse-issue-139445.stderr
@@ -9,16 +9,12 @@ error: expected `while`, `for`, `loop` or `{` after a label
    |
 LL |     assert_eq!(3, 'a,)
    |     ^^^^^^^^^^^^^^^^^^ expected `while`, `for`, `loop` or `{` after a label
-   |
-   = note: this error originates in the macro `assert_eq` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error: expected expression, found ``
   --> $DIR/failed-to-reparse-issue-139445.rs:2:5
    |
 LL |     assert_eq!(3, 'a,)
    |     ^^^^^^^^^^^^^^^^^^ expected expression
-   |
-   = note: this error originates in the macro `assert_eq` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error: aborting due to 3 previous errors
 
diff --git a/tests/ui/macros/format-parse-errors.stderr b/tests/ui/macros/format-parse-errors.stderr
index f9ea4c63377b..baa29170a7d4 100644
--- a/tests/ui/macros/format-parse-errors.stderr
+++ b/tests/ui/macros/format-parse-errors.stderr
@@ -3,8 +3,6 @@ error: requires at least a format string argument
    |
 LL |     format!();
    |     ^^^^^^^^^
-   |
-   = note: this error originates in the macro `$crate::__export::format_args` which comes from the expansion of the macro `format` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error: expected expression, found keyword `struct`
   --> $DIR/format-parse-errors.rs:5:13
diff --git a/tests/ui/macros/macro-expansion-empty-span-147255.stderr b/tests/ui/macros/macro-expansion-empty-span-147255.stderr
index 99396622b34e..cea691679988 100644
--- a/tests/ui/macros/macro-expansion-empty-span-147255.stderr
+++ b/tests/ui/macros/macro-expansion-empty-span-147255.stderr
@@ -8,7 +8,6 @@ LL |     println!("{}", x_str);
    |
    = help: the trait `std::fmt::Display` is not implemented for `()`
    = note: in format strings you may be able to use `{:?}` (or {:#?} for pretty-print) instead
-   = note: this error originates in the macro `$crate::format_args_nl` which comes from the expansion of the macro `println` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error: aborting due to 1 previous error
 
diff --git a/tests/ui/macros/macro-local-data-key-priv.stderr b/tests/ui/macros/macro-local-data-key-priv.stderr
index 8df1aec140d0..2aced92c4152 100644
--- a/tests/ui/macros/macro-local-data-key-priv.stderr
+++ b/tests/ui/macros/macro-local-data-key-priv.stderr
@@ -9,7 +9,6 @@ note: the constant `baz` is defined here
    |
 LL |     thread_local!(static baz: f64 = 0.0);
    |     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-   = note: this error originates in the macro `$crate::thread::local_impl::thread_local_process_attrs` which comes from the expansion of the macro `thread_local` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error: aborting due to 1 previous error
 
diff --git a/tests/ui/macros/vec-macro-in-pattern.stderr b/tests/ui/macros/vec-macro-in-pattern.stderr
index 71ba0ea5ad4f..e5723efc0b2d 100644
--- a/tests/ui/macros/vec-macro-in-pattern.stderr
+++ b/tests/ui/macros/vec-macro-in-pattern.stderr
@@ -5,7 +5,6 @@ LL |         Some(vec![43]) => {}
    |              ^^^^^^^^ not a tuple struct or tuple variant
    |
    = note: function calls are not allowed in patterns: <https://doc.rust-lang.org/book/ch19-00-patterns.html>
-   = note: this error originates in the macro `vec` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error[E0658]: usage of qualified paths in this context is experimental
   --> $DIR/vec-macro-in-pattern.rs:7:14
@@ -16,7 +15,6 @@ LL |         Some(vec![43]) => {}
    = note: see issue #86935 <https://github.com/rust-lang/rust/issues/86935> for more information
    = help: add `#![feature(more_qualified_paths)]` to the crate attributes to enable
    = note: this compiler was built on YYYY-MM-DD; consider upgrading it if it is out of date
-   = note: this error originates in the macro `vec` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error[E0164]: expected tuple struct or tuple variant, found associated function `<[_]>::into_vec`
   --> $DIR/vec-macro-in-pattern.rs:7:14
@@ -25,7 +23,6 @@ LL |         Some(vec![43]) => {}
    |              ^^^^^^^^ `fn` calls are not allowed in patterns
    |
    = help: for more information, visit https://doc.rust-lang.org/book/ch19-00-patterns.html
-   = note: this error originates in the macro `vec` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error: aborting due to 3 previous errors
 
diff --git a/tests/ui/mismatched_types/mismatched-types-issue-126222.stderr b/tests/ui/mismatched_types/mismatched-types-issue-126222.stderr
index 6843cb65a8cd..09ba15253dc5 100644
--- a/tests/ui/mismatched_types/mismatched-types-issue-126222.stderr
+++ b/tests/ui/mismatched_types/mismatched-types-issue-126222.stderr
@@ -4,7 +4,6 @@ error[E0308]: mismatched types
 LL |             x => dbg!(x),
    |                  ^^^^^^^ expected `()`, found integer
    |
-   = note: this error originates in the macro `$crate::macros::dbg_internal` which comes from the expansion of the macro `dbg` (in Nightly builds, run with -Z macro-backtrace for more info)
 help: you might have meant to return this value
    |
 LL |             x => return dbg!(x),
@@ -16,7 +15,6 @@ error[E0308]: mismatched types
 LL |                 dbg!(x)
    |                 ^^^^^^^ expected `()`, found integer
    |
-   = note: this error originates in the macro `$crate::macros::dbg_internal` which comes from the expansion of the macro `dbg` (in Nightly builds, run with -Z macro-backtrace for more info)
 help: you might have meant to return this value
    |
 LL |                 return dbg!(x)
@@ -28,7 +26,6 @@ error[E0308]: mismatched types
 LL |             _ => dbg!(1)
    |                  ^^^^^^^ expected `()`, found integer
    |
-   = note: this error originates in the macro `$crate::macros::dbg_internal` which comes from the expansion of the macro `dbg` (in Nightly builds, run with -Z macro-backtrace for more info)
 help: you might have meant to return this value
    |
 LL |             _ => return dbg!(1)
@@ -40,7 +37,6 @@ error[E0308]: mismatched types
 LL |             _ => {dbg!(1)}
    |                   ^^^^^^^ expected `()`, found integer
    |
-   = note: this error originates in the macro `$crate::macros::dbg_internal` which comes from the expansion of the macro `dbg` (in Nightly builds, run with -Z macro-backtrace for more info)
 help: you might have meant to return this value
    |
 LL |             _ => {return dbg!(1)}
diff --git a/tests/ui/modules/issue-107649.stderr b/tests/ui/modules/issue-107649.stderr
index 45cb29d10ec2..40dda93ad015 100644
--- a/tests/ui/modules/issue-107649.stderr
+++ b/tests/ui/modules/issue-107649.stderr
@@ -5,7 +5,6 @@ error[E0277]: `Dummy` doesn't implement `Debug`
     |     ^^^^^^^^^^^^^^^^ the trait `Debug` is not implemented for `Dummy`
     |
     = note: add `#[derive(Debug)]` to `Dummy` or manually `impl Debug for Dummy`
-    = note: this error originates in the macro `$crate::macros::dbg_internal` which comes from the expansion of the macro `dbg` (in Nightly builds, run with -Z macro-backtrace for more info)
 help: consider annotating `Dummy` with `#[derive(Debug)]`
    --> $DIR/auxiliary/dummy_lib.rs:2:1
     |
diff --git a/tests/ui/moves/moves-based-on-type-capture-clause-bad.stderr b/tests/ui/moves/moves-based-on-type-capture-clause-bad.stderr
index 17049fe67318..ba729493c9b7 100644
--- a/tests/ui/moves/moves-based-on-type-capture-clause-bad.stderr
+++ b/tests/ui/moves/moves-based-on-type-capture-clause-bad.stderr
@@ -11,7 +11,6 @@ LL |     });
 LL |     println!("{}", x);
    |                    ^ value borrowed here after move
    |
-   = note: this error originates in the macro `$crate::format_args_nl` which comes from the expansion of the macro `println` (in Nightly builds, run with -Z macro-backtrace for more info)
 help: consider cloning the value before moving it into the closure
    |
 LL ~     let value = x.clone();
diff --git a/tests/ui/nll/polonius/nll-problem-case-3-issue-21906.nll.stderr b/tests/ui/nll/polonius/nll-problem-case-3-issue-21906.nll.stderr
index dc38b8c127e5..e16300886b0b 100644
--- a/tests/ui/nll/polonius/nll-problem-case-3-issue-21906.nll.stderr
+++ b/tests/ui/nll/polonius/nll-problem-case-3-issue-21906.nll.stderr
@@ -59,8 +59,6 @@ LL |         return Some(y);
 ...
 LL |     println!("{:?}", x.data);
    |                      ^^^^^^ immutable borrow occurs here
-   |
-   = note: this error originates in the macro `$crate::format_args_nl` which comes from the expansion of the macro `println` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error[E0499]: cannot borrow `*vec` as mutable more than once at a time
   --> $DIR/nll-problem-case-3-issue-21906.rs:77:9
diff --git a/tests/ui/on-unimplemented/no-debug.stderr b/tests/ui/on-unimplemented/no-debug.stderr
index 1e6fa7d52fa0..3c3b8d2e2054 100644
--- a/tests/ui/on-unimplemented/no-debug.stderr
+++ b/tests/ui/on-unimplemented/no-debug.stderr
@@ -8,7 +8,6 @@ LL |     println!("{:?} {:?}", Foo, Bar);
    |
    = help: the trait `Debug` is not implemented for `Foo`
    = note: add `#[derive(Debug)]` to `Foo` or manually `impl Debug for Foo`
-   = note: this error originates in the macro `$crate::format_args_nl` which comes from the expansion of the macro `println` (in Nightly builds, run with -Z macro-backtrace for more info)
 help: consider annotating `Foo` with `#[derive(Debug)]`
    |
 LL + #[derive(Debug)]
@@ -24,7 +23,6 @@ LL |     println!("{:?} {:?}", Foo, Bar);
    |                    required by this formatting parameter
    |
    = help: the trait `Debug` is not implemented for `Bar`
-   = note: this error originates in the macro `$crate::format_args_nl` which comes from the expansion of the macro `println` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error[E0277]: `Foo` doesn't implement `std::fmt::Display`
   --> $DIR/no-debug.rs:11:23
@@ -40,7 +38,6 @@ help: the trait `std::fmt::Display` is not implemented for `Foo`
 LL | struct Foo;
    | ^^^^^^^^^^
    = note: in format strings you may be able to use `{:?}` (or {:#?} for pretty-print) instead
-   = note: this error originates in the macro `$crate::format_args_nl` which comes from the expansion of the macro `println` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error[E0277]: `Bar` doesn't implement `std::fmt::Display`
   --> $DIR/no-debug.rs:11:28
@@ -52,7 +49,6 @@ LL |     println!("{} {}", Foo, Bar);
    |
    = help: the trait `std::fmt::Display` is not implemented for `Bar`
    = note: in format strings you may be able to use `{:?}` (or {:#?} for pretty-print) instead
-   = note: this error originates in the macro `$crate::format_args_nl` which comes from the expansion of the macro `println` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error: aborting due to 4 previous errors
 
diff --git a/tests/ui/pattern/deref-patterns/ice-adjust-mode-unimplemented-for-constblock.stderr b/tests/ui/pattern/deref-patterns/ice-adjust-mode-unimplemented-for-constblock.stderr
index 43b0ad18a79b..40615633ea48 100644
--- a/tests/ui/pattern/deref-patterns/ice-adjust-mode-unimplemented-for-constblock.stderr
+++ b/tests/ui/pattern/deref-patterns/ice-adjust-mode-unimplemented-for-constblock.stderr
@@ -5,7 +5,6 @@ LL |     let vec![const { vec![] }]: Vec<usize> = vec![];
    |         ^^^^^^^^^^^^^^^^^^^^^^ not a tuple struct or tuple variant
    |
    = note: function calls are not allowed in patterns: <https://doc.rust-lang.org/book/ch19-00-patterns.html>
-   = note: this error originates in the macro `vec` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error[E0658]: usage of qualified paths in this context is experimental
   --> $DIR/ice-adjust-mode-unimplemented-for-constblock.rs:5:9
@@ -16,7 +15,6 @@ LL |     let vec![const { vec![] }]: Vec<usize> = vec![];
    = note: see issue #86935 <https://github.com/rust-lang/rust/issues/86935> for more information
    = help: add `#![feature(more_qualified_paths)]` to the crate attributes to enable
    = note: this compiler was built on YYYY-MM-DD; consider upgrading it if it is out of date
-   = note: this error originates in the macro `vec` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error: arbitrary expressions aren't allowed in patterns
   --> $DIR/ice-adjust-mode-unimplemented-for-constblock.rs:5:14
@@ -33,7 +31,6 @@ LL |     let vec![const { vec![] }]: Vec<usize> = vec![];
    |         ^^^^^^^^^^^^^^^^^^^^^^ `fn` calls are not allowed in patterns
    |
    = help: for more information, visit https://doc.rust-lang.org/book/ch19-00-patterns.html
-   = note: this error originates in the macro `vec` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error: aborting due to 4 previous errors
 
diff --git a/tests/ui/pin-macro/lifetime_errors_on_promotion_misusage.stderr b/tests/ui/pin-macro/lifetime_errors_on_promotion_misusage.stderr
index 4ecc6370d3ca..347ec0a7743e 100644
--- a/tests/ui/pin-macro/lifetime_errors_on_promotion_misusage.stderr
+++ b/tests/ui/pin-macro/lifetime_errors_on_promotion_misusage.stderr
@@ -10,7 +10,6 @@ LL |     stuff(phantom_pinned)
    |           -------------- borrow later used here
    |
    = note: consider using a `let` binding to create a longer lived value
-   = note: this error originates in the macro `pin` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error[E0716]: temporary value dropped while borrowed
   --> $DIR/lifetime_errors_on_promotion_misusage.rs:18:30
@@ -24,7 +23,6 @@ LL |     };
    |     - temporary value is freed at the end of this statement
    |
    = note: consider using a `let` binding to create a longer lived value
-   = note: this error originates in the macro `pin` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error: aborting due to 2 previous errors
 
diff --git a/tests/ui/reachable/expr_again.stderr b/tests/ui/reachable/expr_again.stderr
index 5dec512ba5de..2e00fdc7b431 100644
--- a/tests/ui/reachable/expr_again.stderr
+++ b/tests/ui/reachable/expr_again.stderr
@@ -11,7 +11,6 @@ note: the lint level is defined here
    |
 LL | #![deny(unreachable_code)]
    |         ^^^^^^^^^^^^^^^^
-   = note: this error originates in the macro `println` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error: aborting due to 1 previous error
 
diff --git a/tests/ui/reachable/expr_block.stderr b/tests/ui/reachable/expr_block.stderr
index d5f248a24910..aaca4053f27f 100644
--- a/tests/ui/reachable/expr_block.stderr
+++ b/tests/ui/reachable/expr_block.stderr
@@ -19,8 +19,6 @@ LL |         return;
    |         ------ any code following this expression is unreachable
 LL |         println!("foo");
    |         ^^^^^^^^^^^^^^^ unreachable statement
-   |
-   = note: this error originates in the macro `println` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error: aborting due to 2 previous errors
 
diff --git a/tests/ui/reachable/expr_if.stderr b/tests/ui/reachable/expr_if.stderr
index ebd0b5a3ebef..662692ed6f28 100644
--- a/tests/ui/reachable/expr_if.stderr
+++ b/tests/ui/reachable/expr_if.stderr
@@ -23,8 +23,6 @@ LL |         return;
 ...
 LL |     println!("But I am.");
    |     ^^^^^^^^^^^^^^^^^^^^^ unreachable statement
-   |
-   = note: this error originates in the macro `println` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error: aborting due to 2 previous errors
 
diff --git a/tests/ui/reachable/expr_loop.stderr b/tests/ui/reachable/expr_loop.stderr
index 918584686050..83b8d024c4fc 100644
--- a/tests/ui/reachable/expr_loop.stderr
+++ b/tests/ui/reachable/expr_loop.stderr
@@ -11,7 +11,6 @@ note: the lint level is defined here
    |
 LL | #![deny(unreachable_code)]
    |         ^^^^^^^^^^^^^^^^
-   = note: this error originates in the macro `println` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error: unreachable statement
   --> $DIR/expr_loop.rs:21:5
@@ -20,8 +19,6 @@ LL |     loop { return; }
    |            ------ any code following this expression is unreachable
 LL |     println!("I am dead.");
    |     ^^^^^^^^^^^^^^^^^^^^^^ unreachable statement
-   |
-   = note: this error originates in the macro `println` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error: unreachable statement
   --> $DIR/expr_loop.rs:32:5
@@ -30,8 +27,6 @@ LL |     loop { 'middle: loop { loop { break 'middle; } } }
    |     -------------------------------------------------- any code following this expression is unreachable
 LL |     println!("I am dead.");
    |     ^^^^^^^^^^^^^^^^^^^^^^ unreachable statement
-   |
-   = note: this error originates in the macro `println` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error: aborting due to 3 previous errors
 
diff --git a/tests/ui/reachable/expr_match.stderr b/tests/ui/reachable/expr_match.stderr
index ae202a6e0c34..92f6d6758d99 100644
--- a/tests/ui/reachable/expr_match.stderr
+++ b/tests/ui/reachable/expr_match.stderr
@@ -11,7 +11,6 @@ note: the lint level is defined here
    |
 LL | #![deny(unreachable_code)]
    |         ^^^^^^^^^^^^^^^^
-   = note: this error originates in the macro `println` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error: unreachable statement
   --> $DIR/expr_match.rs:19:5
@@ -20,8 +19,6 @@ LL |     match () { () if false => return, () => return }
    |     ------------------------------------------------ any code following this `match` expression is unreachable, as all arms diverge
 LL |     println!("I am dead");
    |     ^^^^^^^^^^^^^^^^^^^^^ unreachable statement
-   |
-   = note: this error originates in the macro `println` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error: unreachable expression
   --> $DIR/expr_match.rs:25:25
@@ -42,8 +39,6 @@ LL | |     }
    | |_____- any code following this `match` expression is unreachable, as all arms diverge
 LL |       println!("I am dead");
    |       ^^^^^^^^^^^^^^^^^^^^^ unreachable statement
-   |
-   = note: this error originates in the macro `println` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error: aborting due to 4 previous errors
 
diff --git a/tests/ui/reachable/unreachable-code-ret.stderr b/tests/ui/reachable/unreachable-code-ret.stderr
index d86def536df8..f51273eb4207 100644
--- a/tests/ui/reachable/unreachable-code-ret.stderr
+++ b/tests/ui/reachable/unreachable-code-ret.stderr
@@ -11,7 +11,6 @@ note: the lint level is defined here
    |
 LL | #![deny(unreachable_code)]
    |         ^^^^^^^^^^^^^^^^
-   = note: this error originates in the macro `println` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error: aborting due to 1 previous error
 
diff --git a/tests/ui/resolve/underscore-bindings-disambiguators.stderr b/tests/ui/resolve/underscore-bindings-disambiguators.stderr
index ec14ede03e3f..9208b84c43a2 100644
--- a/tests/ui/resolve/underscore-bindings-disambiguators.stderr
+++ b/tests/ui/resolve/underscore-bindings-disambiguators.stderr
@@ -21,48 +21,36 @@ error[E0080]: evaluation panicked: not yet implemented
    |
 LL |     const _: () = todo!();
    |                   ^^^^^^^ evaluation of `impls::_` failed here
-   |
-   = note: this error originates in the macro `todo` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error[E0080]: evaluation panicked: not yet implemented
   --> $DIR/underscore-bindings-disambiguators.rs:20:19
    |
 LL |     const _: () = todo!();
    |                   ^^^^^^^ evaluation of `impls::_` failed here
-   |
-   = note: this error originates in the macro `todo` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error[E0080]: evaluation panicked: not yet implemented
   --> $DIR/underscore-bindings-disambiguators.rs:21:19
    |
 LL |     const _: () = todo!();
    |                   ^^^^^^^ evaluation of `impls::_` failed here
-   |
-   = note: this error originates in the macro `todo` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error[E0080]: evaluation panicked: not yet implemented
   --> $DIR/underscore-bindings-disambiguators.rs:22:19
    |
 LL |     const _: () = todo!();
    |                   ^^^^^^^ evaluation of `impls::_` failed here
-   |
-   = note: this error originates in the macro `todo` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error[E0080]: evaluation panicked: not yet implemented
   --> $DIR/underscore-bindings-disambiguators.rs:23:19
    |
 LL |     const _: () = todo!();
    |                   ^^^^^^^ evaluation of `impls::_` failed here
-   |
-   = note: this error originates in the macro `todo` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error[E0080]: evaluation panicked: not yet implemented
   --> $DIR/underscore-bindings-disambiguators.rs:28:15
    |
 LL | const _: () = todo!();
    |               ^^^^^^^ evaluation of `_` failed here
-   |
-   = note: this error originates in the macro `todo` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error: aborting due to 8 previous errors
 
diff --git a/tests/ui/rfcs/rfc-0000-never_patterns/diverge-causes-unreachable-code.stderr b/tests/ui/rfcs/rfc-0000-never_patterns/diverge-causes-unreachable-code.stderr
index c33a5855d506..a55d540dc7f2 100644
--- a/tests/ui/rfcs/rfc-0000-never_patterns/diverge-causes-unreachable-code.stderr
+++ b/tests/ui/rfcs/rfc-0000-never_patterns/diverge-causes-unreachable-code.stderr
@@ -11,7 +11,6 @@ note: the lint level is defined here
    |
 LL | #![deny(unreachable_code)]
    |         ^^^^^^^^^^^^^^^^
-   = note: this error originates in the macro `$crate::print` which comes from the expansion of the macro `println` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error: unreachable statement
   --> $DIR/diverge-causes-unreachable-code.rs:16:5
@@ -20,8 +19,6 @@ LL | fn ref_never_arg(&!: &Void) -> u32 {
    |                  -- any code following a never pattern is unreachable
 LL |     println!();
    |     ^^^^^^^^^^ unreachable statement
-   |
-   = note: this error originates in the macro `$crate::print` which comes from the expansion of the macro `println` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error: unreachable statement
   --> $DIR/diverge-causes-unreachable-code.rs:25:5
@@ -31,8 +28,6 @@ LL |         let ! = *ptr;
 LL |     }
 LL |     println!();
    |     ^^^^^^^^^^ unreachable statement
-   |
-   = note: this error originates in the macro `$crate::print` which comes from the expansion of the macro `println` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error: unreachable statement
   --> $DIR/diverge-causes-unreachable-code.rs:34:5
@@ -42,8 +37,6 @@ LL |         match *ptr { ! };
 LL |     }
 LL |     println!();
    |     ^^^^^^^^^^ unreachable statement
-   |
-   = note: this error originates in the macro `$crate::print` which comes from the expansion of the macro `println` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error: aborting due to 4 previous errors
 
diff --git a/tests/ui/rfcs/rfc-2361-dbg-macro/dbg-macro-move-semantics.stderr b/tests/ui/rfcs/rfc-2361-dbg-macro/dbg-macro-move-semantics.stderr
index fdf5115303ba..f8ef315b9cc7 100644
--- a/tests/ui/rfcs/rfc-2361-dbg-macro/dbg-macro-move-semantics.stderr
+++ b/tests/ui/rfcs/rfc-2361-dbg-macro/dbg-macro-move-semantics.stderr
@@ -8,7 +8,6 @@ LL |     let _ = dbg!(a);
 LL |     let _ = dbg!(a);
    |             ^^^^^^^ value used here after move
    |
-   = note: this error originates in the macro `$crate::macros::dbg_internal` which comes from the expansion of the macro `dbg` (in Nightly builds, run with -Z macro-backtrace for more info)
 help: consider borrowing instead of transferring ownership
    |
 LL |     let _ = dbg!(&a);
diff --git a/tests/ui/rfcs/rfc-2361-dbg-macro/dbg-macro-requires-debug.stderr b/tests/ui/rfcs/rfc-2361-dbg-macro/dbg-macro-requires-debug.stderr
index 2c4ce2676b07..4cdeb184bd91 100644
--- a/tests/ui/rfcs/rfc-2361-dbg-macro/dbg-macro-requires-debug.stderr
+++ b/tests/ui/rfcs/rfc-2361-dbg-macro/dbg-macro-requires-debug.stderr
@@ -5,7 +5,6 @@ LL |     let _: NotDebug = dbg!(NotDebug);
    |                       ^^^^^^^^^^^^^^ the trait `Debug` is not implemented for `NotDebug`
    |
    = note: add `#[derive(Debug)]` to `NotDebug` or manually `impl Debug for NotDebug`
-   = note: this error originates in the macro `$crate::macros::dbg_internal` which comes from the expansion of the macro `dbg` (in Nightly builds, run with -Z macro-backtrace for more info)
 help: consider annotating `NotDebug` with `#[derive(Debug)]`
    |
 LL + #[derive(Debug)]
diff --git a/tests/ui/span/coerce-suggestions.stderr b/tests/ui/span/coerce-suggestions.stderr
index 77b01ee08b79..d0f76a23edc4 100644
--- a/tests/ui/span/coerce-suggestions.stderr
+++ b/tests/ui/span/coerce-suggestions.stderr
@@ -56,8 +56,6 @@ error[E0308]: mismatched types
    |
 LL |     s = format!("foo");
    |         ^^^^^^^^^^^^^^ expected `&mut String`, found `String`
-   |
-   = note: this error originates in the macro `format` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error: aborting due to 5 previous errors
 
diff --git a/tests/ui/span/issue-33884.stderr b/tests/ui/span/issue-33884.stderr
index 29490d86fffe..a5c3e9fa7c45 100644
--- a/tests/ui/span/issue-33884.stderr
+++ b/tests/ui/span/issue-33884.stderr
@@ -3,8 +3,6 @@ error[E0308]: mismatched types
    |
 LL |     stream.write_fmt(format!("message received"))
    |                      ^^^^^^^^^^^^^^^^^^^^^^^^^^^ expected `Arguments<'_>`, found `String`
-   |
-   = note: this error originates in the macro `format` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error: aborting due to 1 previous error
 
diff --git a/tests/ui/span/issue-39698.stderr b/tests/ui/span/issue-39698.stderr
index eb18969c3c0d..dd57fa061866 100644
--- a/tests/ui/span/issue-39698.stderr
+++ b/tests/ui/span/issue-39698.stderr
@@ -71,8 +71,6 @@ LL |         T::T1(a, d) | T::T2(d, b) | T::T3(c) | T::T4(a) => { println!("{:?}
    |               |                                      binding initialized here in some conditions
    |               binding initialized here in some conditions
    |               binding declared here but left uninitialized
-   |
-   = note: this error originates in the macro `$crate::format_args_nl` which comes from the expansion of the macro `println` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error: aborting due to 5 previous errors
 
diff --git a/tests/ui/span/slice-borrow.stderr b/tests/ui/span/slice-borrow.stderr
index 48ac20feea72..6d37019e91b4 100644
--- a/tests/ui/span/slice-borrow.stderr
+++ b/tests/ui/span/slice-borrow.stderr
@@ -10,7 +10,6 @@ LL |     y.use_ref();
    |     - borrow later used here
    |
    = note: consider using a `let` binding to create a longer lived value
-   = note: this error originates in the macro `vec` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error: aborting due to 1 previous error
 
diff --git a/tests/ui/statics/check-values-constraints.stderr b/tests/ui/statics/check-values-constraints.stderr
index c54f4830533a..082dd3490603 100644
--- a/tests/ui/statics/check-values-constraints.stderr
+++ b/tests/ui/statics/check-values-constraints.stderr
@@ -16,8 +16,6 @@ error[E0010]: allocations are not allowed in statics
    |
 LL | static STATIC11: Vec<MyOwned> = vec![MyOwned];
    |                                 ^^^^^^^^^^^^^ allocation not allowed in statics
-   |
-   = note: this error originates in the macro `vec` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error[E0015]: cannot call non-const method `slice::<impl [MyOwned]>::into_vec::<std::alloc::Global>` in statics
   --> $DIR/check-values-constraints.rs:81:33
@@ -27,7 +25,6 @@ LL | static STATIC11: Vec<MyOwned> = vec![MyOwned];
    |
    = note: calls in statics are limited to constant functions, tuple structs and tuple variants
    = note: consider wrapping this expression in `std::sync::LazyLock::new(|| ...)`
-   = note: this error originates in the macro `vec` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error[E0015]: cannot call non-const method `<str as ToString>::to_string` in statics
   --> $DIR/check-values-constraints.rs:92:38
@@ -50,8 +47,6 @@ error[E0010]: allocations are not allowed in statics
    |
 LL |     vec![MyOwned],
    |     ^^^^^^^^^^^^^ allocation not allowed in statics
-   |
-   = note: this error originates in the macro `vec` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error[E0015]: cannot call non-const method `slice::<impl [MyOwned]>::into_vec::<std::alloc::Global>` in statics
   --> $DIR/check-values-constraints.rs:96:5
@@ -61,15 +56,12 @@ LL |     vec![MyOwned],
    |
    = note: calls in statics are limited to constant functions, tuple structs and tuple variants
    = note: consider wrapping this expression in `std::sync::LazyLock::new(|| ...)`
-   = note: this error originates in the macro `vec` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error[E0010]: allocations are not allowed in statics
   --> $DIR/check-values-constraints.rs:98:5
    |
 LL |     vec![MyOwned],
    |     ^^^^^^^^^^^^^ allocation not allowed in statics
-   |
-   = note: this error originates in the macro `vec` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error[E0015]: cannot call non-const method `slice::<impl [MyOwned]>::into_vec::<std::alloc::Global>` in statics
   --> $DIR/check-values-constraints.rs:98:5
@@ -79,15 +71,12 @@ LL |     vec![MyOwned],
    |
    = note: calls in statics are limited to constant functions, tuple structs and tuple variants
    = note: consider wrapping this expression in `std::sync::LazyLock::new(|| ...)`
-   = note: this error originates in the macro `vec` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error[E0010]: allocations are not allowed in statics
   --> $DIR/check-values-constraints.rs:103:6
    |
 LL |     &vec![MyOwned],
    |      ^^^^^^^^^^^^^ allocation not allowed in statics
-   |
-   = note: this error originates in the macro `vec` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error[E0015]: cannot call non-const method `slice::<impl [MyOwned]>::into_vec::<std::alloc::Global>` in statics
   --> $DIR/check-values-constraints.rs:103:6
@@ -97,15 +86,12 @@ LL |     &vec![MyOwned],
    |
    = note: calls in statics are limited to constant functions, tuple structs and tuple variants
    = note: consider wrapping this expression in `std::sync::LazyLock::new(|| ...)`
-   = note: this error originates in the macro `vec` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error[E0010]: allocations are not allowed in statics
   --> $DIR/check-values-constraints.rs:105:6
    |
 LL |     &vec![MyOwned],
    |      ^^^^^^^^^^^^^ allocation not allowed in statics
-   |
-   = note: this error originates in the macro `vec` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error[E0015]: cannot call non-const method `slice::<impl [MyOwned]>::into_vec::<std::alloc::Global>` in statics
   --> $DIR/check-values-constraints.rs:105:6
@@ -115,15 +101,12 @@ LL |     &vec![MyOwned],
    |
    = note: calls in statics are limited to constant functions, tuple structs and tuple variants
    = note: consider wrapping this expression in `std::sync::LazyLock::new(|| ...)`
-   = note: this error originates in the macro `vec` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error[E0010]: allocations are not allowed in statics
   --> $DIR/check-values-constraints.rs:111:31
    |
 LL | static STATIC19: Vec<isize> = vec![3];
    |                               ^^^^^^^ allocation not allowed in statics
-   |
-   = note: this error originates in the macro `vec` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error[E0015]: cannot call non-const method `slice::<impl [isize]>::into_vec::<std::alloc::Global>` in statics
   --> $DIR/check-values-constraints.rs:111:31
@@ -133,15 +116,12 @@ LL | static STATIC19: Vec<isize> = vec![3];
    |
    = note: calls in statics are limited to constant functions, tuple structs and tuple variants
    = note: consider wrapping this expression in `std::sync::LazyLock::new(|| ...)`
-   = note: this error originates in the macro `vec` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error[E0010]: allocations are not allowed in statics
   --> $DIR/check-values-constraints.rs:117:32
    |
 LL |         static x: Vec<isize> = vec![3];
    |                                ^^^^^^^ allocation not allowed in statics
-   |
-   = note: this error originates in the macro `vec` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error[E0015]: cannot call non-const method `slice::<impl [isize]>::into_vec::<std::alloc::Global>` in statics
   --> $DIR/check-values-constraints.rs:117:32
@@ -151,7 +131,6 @@ LL |         static x: Vec<isize> = vec![3];
    |
    = note: calls in statics are limited to constant functions, tuple structs and tuple variants
    = note: consider wrapping this expression in `std::sync::LazyLock::new(|| ...)`
-   = note: this error originates in the macro `vec` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error[E0507]: cannot move out of static item `x`
   --> $DIR/check-values-constraints.rs:119:9
diff --git a/tests/ui/suggestions/bound-suggestions.stderr b/tests/ui/suggestions/bound-suggestions.stderr
index ec1d23fac458..ba792578a202 100644
--- a/tests/ui/suggestions/bound-suggestions.stderr
+++ b/tests/ui/suggestions/bound-suggestions.stderr
@@ -6,7 +6,6 @@ LL |     println!("{:?}", t);
    |               |
    |               required by this formatting parameter
    |
-   = note: this error originates in the macro `$crate::format_args_nl` which comes from the expansion of the macro `println` (in Nightly builds, run with -Z macro-backtrace for more info)
 help: consider restricting opaque type `impl Sized` with trait `Debug`
    |
 LL | fn test_impl(t: impl Sized + std::fmt::Debug) {
@@ -20,7 +19,6 @@ LL |     println!("{:?}", t);
    |               |
    |               required by this formatting parameter
    |
-   = note: this error originates in the macro `$crate::format_args_nl` which comes from the expansion of the macro `println` (in Nightly builds, run with -Z macro-backtrace for more info)
 help: consider restricting type parameter `T` with trait `Debug`
    |
 LL | fn test_no_bounds<T: std::fmt::Debug>(t: T) {
@@ -34,7 +32,6 @@ LL |     println!("{:?}", t);
    |               |
    |               required by this formatting parameter
    |
-   = note: this error originates in the macro `$crate::format_args_nl` which comes from the expansion of the macro `println` (in Nightly builds, run with -Z macro-backtrace for more info)
 help: consider further restricting type parameter `T` with trait `Debug`
    |
 LL | fn test_one_bound<T: Sized + std::fmt::Debug>(t: T) {
@@ -48,7 +45,6 @@ LL |     println!("{:?} {:?}", x, y);
    |                    |
    |                    required by this formatting parameter
    |
-   = note: this error originates in the macro `$crate::format_args_nl` which comes from the expansion of the macro `println` (in Nightly builds, run with -Z macro-backtrace for more info)
 help: consider further restricting type parameter `Y` with trait `Debug`
    |
 LL | fn test_no_bounds_where<X, Y>(x: X, y: Y) where X: std::fmt::Debug, Y: std::fmt::Debug {
@@ -62,7 +58,6 @@ LL |     println!("{:?}", x);
    |               |
    |               required by this formatting parameter
    |
-   = note: this error originates in the macro `$crate::format_args_nl` which comes from the expansion of the macro `println` (in Nightly builds, run with -Z macro-backtrace for more info)
 help: consider further restricting type parameter `X` with trait `Debug`
    |
 LL | fn test_one_bound_where<X>(x: X) where X: Sized + std::fmt::Debug {
@@ -76,7 +71,6 @@ LL |     println!("{:?}", x);
    |               |
    |               required by this formatting parameter
    |
-   = note: this error originates in the macro `$crate::format_args_nl` which comes from the expansion of the macro `println` (in Nightly builds, run with -Z macro-backtrace for more info)
 help: consider further restricting type parameter `X` with trait `Debug`
    |
 LL | fn test_many_bounds_where<X>(x: X) where X: Sized + std::fmt::Debug, X: Sized {
diff --git a/tests/ui/suggestions/issue-97760.stderr b/tests/ui/suggestions/issue-97760.stderr
index c3cf7e13987b..f3dc3f74efe8 100644
--- a/tests/ui/suggestions/issue-97760.stderr
+++ b/tests/ui/suggestions/issue-97760.stderr
@@ -6,7 +6,6 @@ LL |         println!("{x}");
    |
    = help: the trait `std::fmt::Display` is not implemented for `<impl IntoIterator as IntoIterator>::Item`
    = note: in format strings you may be able to use `{:?}` (or {:#?} for pretty-print) instead
-   = note: this error originates in the macro `$crate::format_args_nl` which comes from the expansion of the macro `println` (in Nightly builds, run with -Z macro-backtrace for more info)
 help: introduce a type parameter with a trait bound instead of using `impl Trait`
    |
 LL ~ pub fn print_values<I: IntoIterator>(values: &I)
diff --git a/tests/ui/suggestions/path-display.stderr b/tests/ui/suggestions/path-display.stderr
index 0c7271b3c1c3..df9e855bb714 100644
--- a/tests/ui/suggestions/path-display.stderr
+++ b/tests/ui/suggestions/path-display.stderr
@@ -10,7 +10,6 @@ LL |     println!("{}", path);
    = note: in format strings you may be able to use `{:?}` (or {:#?} for pretty-print) instead
    = note: call `.display()` or `.to_string_lossy()` to safely print paths, as they may contain non-Unicode data
    = note: required for `&Path` to implement `std::fmt::Display`
-   = note: this error originates in the macro `$crate::format_args_nl` which comes from the expansion of the macro `println` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error[E0277]: `PathBuf` doesn't implement `std::fmt::Display`
   --> $DIR/path-display.rs:9:20
@@ -23,7 +22,6 @@ LL |     println!("{}", path);
    = help: the trait `std::fmt::Display` is not implemented for `PathBuf`
    = note: in format strings you may be able to use `{:?}` (or {:#?} for pretty-print) instead
    = note: call `.display()` or `.to_string_lossy()` to safely print paths, as they may contain non-Unicode data
-   = note: this error originates in the macro `$crate::format_args_nl` which comes from the expansion of the macro `println` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error: aborting due to 2 previous errors
 
diff --git a/tests/ui/thread-local/no-unstable.stderr b/tests/ui/thread-local/no-unstable.stderr
index fbcd804d9178..438020d00b7d 100644
--- a/tests/ui/thread-local/no-unstable.stderr
+++ b/tests/ui/thread-local/no-unstable.stderr
@@ -10,7 +10,6 @@ LL | | }
    = help: add `#![feature(rustc_attrs)]` to the crate attributes to enable
    = note: the `#[rustc_dummy]` attribute is an internal implementation detail that will never be stable
    = note: the `#[rustc_dummy]` attribute is used for rustc unit tests
-   = note: this error originates in the macro `$crate::thread::local_impl::thread_local_process_attrs` which comes from the expansion of the macro `thread_local` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error[E0658]: use of an internal attribute
   --> $DIR/no-unstable.rs:1:1
@@ -24,7 +23,6 @@ LL | | }
    = help: add `#![feature(rustc_attrs)]` to the crate attributes to enable
    = note: the `#[rustc_dummy]` attribute is an internal implementation detail that will never be stable
    = note: the `#[rustc_dummy]` attribute is used for rustc unit tests
-   = note: this error originates in the macro `$crate::thread::local_impl::thread_local_process_attrs` which comes from the expansion of the macro `thread_local` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error[E0658]: `#[used(linker)]` is currently unstable
   --> $DIR/no-unstable.rs:1:1
@@ -38,7 +36,6 @@ LL | | }
    = note: see issue #93798 <https://github.com/rust-lang/rust/issues/93798> for more information
    = help: add `#![feature(used_with_arg)]` to the crate attributes to enable
    = note: this compiler was built on YYYY-MM-DD; consider upgrading it if it is out of date
-   = note: this error originates in the macro `$crate::thread::local_impl::thread_local_process_attrs` which comes from the expansion of the macro `thread_local` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error: `#[used]` attribute cannot be used on constants
   --> $DIR/no-unstable.rs:1:1
@@ -50,7 +47,6 @@ LL | | }
    | |_^
    |
    = help: `#[used]` can only be applied to statics
-   = note: this error originates in the macro `$crate::thread::local_impl::thread_local_process_attrs` which comes from the expansion of the macro `thread_local` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error: aborting due to 4 previous errors
 
diff --git a/tests/ui/traits/const-traits/issue-79450.stderr b/tests/ui/traits/const-traits/issue-79450.stderr
index 702e93a76a8f..82d5ea34582f 100644
--- a/tests/ui/traits/const-traits/issue-79450.stderr
+++ b/tests/ui/traits/const-traits/issue-79450.stderr
@@ -7,7 +7,6 @@ LL |         println!("lul");
 note: function `_print` is not const
   --> $SRC_DIR/std/src/io/stdio.rs:LL:COL
    = note: calls in constant functions are limited to constant functions, tuple structs and tuple variants
-   = note: this error originates in the macro `println` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error: aborting due to 1 previous error
 
diff --git a/tests/ui/try-block/try-block-maybe-bad-lifetime.stderr b/tests/ui/try-block/try-block-maybe-bad-lifetime.stderr
index 71c7e460c399..7fe151021976 100644
--- a/tests/ui/try-block/try-block-maybe-bad-lifetime.stderr
+++ b/tests/ui/try-block/try-block-maybe-bad-lifetime.stderr
@@ -22,7 +22,6 @@ LL |         };
 LL |         println!("{}", x);
    |                        ^ value borrowed here after move
    |
-   = note: this error originates in the macro `$crate::format_args_nl` which comes from the expansion of the macro `println` (in Nightly builds, run with -Z macro-backtrace for more info)
 help: consider cloning the value if the performance cost is acceptable
    |
 LL |             ::std::mem::drop(x.clone());
diff --git a/tests/ui/try-block/try-block-opt-init.stderr b/tests/ui/try-block/try-block-opt-init.stderr
index 1679fc2ac18c..b838af5d53b9 100644
--- a/tests/ui/try-block/try-block-opt-init.stderr
+++ b/tests/ui/try-block/try-block-opt-init.stderr
@@ -9,8 +9,6 @@ LL |         cfg_res = 5;
 ...
 LL |     assert_eq!(cfg_res, 5);
    |     ^^^^^^^^^^^^^^^^^^^^^^ `cfg_res` used here but it is possibly-uninitialized
-   |
-   = note: this error originates in the macro `assert_eq` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error: aborting due to 1 previous error
 
diff --git a/tests/ui/type-alias-impl-trait/imply_bounds_from_bounds_param.edition2024.stderr b/tests/ui/type-alias-impl-trait/imply_bounds_from_bounds_param.edition2024.stderr
index a7135e8f05f4..da2099c1ed27 100644
--- a/tests/ui/type-alias-impl-trait/imply_bounds_from_bounds_param.edition2024.stderr
+++ b/tests/ui/type-alias-impl-trait/imply_bounds_from_bounds_param.edition2024.stderr
@@ -35,7 +35,6 @@ note: this call may capture more lifetimes than intended, because Rust 2024 has
    |
 LL |     let mut thing = test(&mut z);
    |                     ^^^^^^^^^^^^
-   = note: this error originates in the macro `assert_eq` (in Nightly builds, run with -Z macro-backtrace for more info)
 help: use the precise capturing `use<...>` syntax to make the captures explicit
    |
 LL | fn test<'a>(y: &'a mut i32) -> impl PlusOne + use<> {
@@ -57,7 +56,6 @@ note: this call may capture more lifetimes than intended, because Rust 2024 has
    |
 LL |     let mut thing = test(&mut z);
    |                     ^^^^^^^^^^^^
-   = note: this error originates in the macro `assert_eq` (in Nightly builds, run with -Z macro-backtrace for more info)
 help: use the precise capturing `use<...>` syntax to make the captures explicit
    |
 LL | fn test<'a>(y: &'a mut i32) -> impl PlusOne + use<> {
@@ -79,7 +77,6 @@ note: this call may capture more lifetimes than intended, because Rust 2024 has
    |
 LL |     let mut thing = test(&mut z);
    |                     ^^^^^^^^^^^^
-   = note: this error originates in the macro `assert_eq` (in Nightly builds, run with -Z macro-backtrace for more info)
 help: use the precise capturing `use<...>` syntax to make the captures explicit
    |
 LL | fn test<'a>(y: &'a mut i32) -> impl PlusOne + use<> {
diff --git a/tests/ui/type-alias-impl-trait/nested.stderr b/tests/ui/type-alias-impl-trait/nested.stderr
index f72830b864d1..9ac0fe5302be 100644
--- a/tests/ui/type-alias-impl-trait/nested.stderr
+++ b/tests/ui/type-alias-impl-trait/nested.stderr
@@ -20,7 +20,6 @@ LL |     println!("{:?}", bar());
    |               required by this formatting parameter
    |
    = help: the trait `Debug` is not implemented for `Bar`
-   = note: this error originates in the macro `$crate::format_args_nl` which comes from the expansion of the macro `println` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error: aborting due to 2 previous errors
 
diff --git a/tests/ui/type/binding-assigned-block-without-tail-expression.stderr b/tests/ui/type/binding-assigned-block-without-tail-expression.stderr
index ff34facf3892..ed7ff22e501c 100644
--- a/tests/ui/type/binding-assigned-block-without-tail-expression.stderr
+++ b/tests/ui/type/binding-assigned-block-without-tail-expression.stderr
@@ -11,7 +11,6 @@ LL |     println!("{}", x);
    |
    = help: the trait `std::fmt::Display` is not implemented for `()`
    = note: in format strings you may be able to use `{:?}` (or {:#?} for pretty-print) instead
-   = note: this error originates in the macro `$crate::format_args_nl` which comes from the expansion of the macro `println` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error[E0277]: `()` doesn't implement `std::fmt::Display`
   --> $DIR/binding-assigned-block-without-tail-expression.rs:15:20
@@ -26,7 +25,6 @@ LL |     println!("{}", y);
    |
    = help: the trait `std::fmt::Display` is not implemented for `()`
    = note: in format strings you may be able to use `{:?}` (or {:#?} for pretty-print) instead
-   = note: this error originates in the macro `$crate::format_args_nl` which comes from the expansion of the macro `println` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error[E0277]: `()` doesn't implement `std::fmt::Display`
   --> $DIR/binding-assigned-block-without-tail-expression.rs:16:20
@@ -41,7 +39,6 @@ LL |     println!("{}", z);
    |
    = help: the trait `std::fmt::Display` is not implemented for `()`
    = note: in format strings you may be able to use `{:?}` (or {:#?} for pretty-print) instead
-   = note: this error originates in the macro `$crate::format_args_nl` which comes from the expansion of the macro `println` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error[E0277]: `()` doesn't implement `std::fmt::Display`
   --> $DIR/binding-assigned-block-without-tail-expression.rs:17:20
@@ -59,7 +56,6 @@ LL |       println!("{}", s);
    |
    = help: the trait `std::fmt::Display` is not implemented for `()`
    = note: in format strings you may be able to use `{:?}` (or {:#?} for pretty-print) instead
-   = note: this error originates in the macro `$crate::format_args_nl` which comes from the expansion of the macro `println` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error[E0308]: mismatched types
   --> $DIR/binding-assigned-block-without-tail-expression.rs:18:18
diff --git a/tests/ui/typeck/closure-ty-mismatch-issue-128561.stderr b/tests/ui/typeck/closure-ty-mismatch-issue-128561.stderr
index 0907489f8e8a..b4bf0e00cfe2 100644
--- a/tests/ui/typeck/closure-ty-mismatch-issue-128561.stderr
+++ b/tests/ui/typeck/closure-ty-mismatch-issue-128561.stderr
@@ -14,8 +14,6 @@ error[E0308]: mismatched types
    |
 LL |     b"abc".iter().for_each(|x| dbg!(x));
    |                                ^^^^^^^ expected `()`, found `&u8`
-   |
-   = note: this error originates in the macro `$crate::macros::dbg_internal` which comes from the expansion of the macro `dbg` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error[E0308]: mismatched types
   --> $DIR/closure-ty-mismatch-issue-128561.rs:8:9
diff --git a/tests/ui/typeck/issue-110017-format-into-help-deletes-macro.stderr b/tests/ui/typeck/issue-110017-format-into-help-deletes-macro.stderr
index bc722cdd57a5..efd8d6e2686c 100644
--- a/tests/ui/typeck/issue-110017-format-into-help-deletes-macro.stderr
+++ b/tests/ui/typeck/issue-110017-format-into-help-deletes-macro.stderr
@@ -6,7 +6,6 @@ LL |      Err(format!("error: {x}"))
    |
    = note: expected struct `Box<dyn std::error::Error>`
               found struct `String`
-   = note: this error originates in the macro `format` (in Nightly builds, run with -Z macro-backtrace for more info)
 help: call `Into::into` on this expression to convert `String` into `Box<dyn std::error::Error>`
    |
 LL |      Err(format!("error: {x}").into())
diff --git a/tests/ui/typeck/issue-112007-leaked-writeln-macro-internals.stderr b/tests/ui/typeck/issue-112007-leaked-writeln-macro-internals.stderr
index 30d51420b7cb..cc5a4af88064 100644
--- a/tests/ui/typeck/issue-112007-leaked-writeln-macro-internals.stderr
+++ b/tests/ui/typeck/issue-112007-leaked-writeln-macro-internals.stderr
@@ -12,7 +12,6 @@ LL | |     }
    |
    = note: expected unit type `()`
                    found enum `Result<(), std::fmt::Error>`
-   = note: this error originates in the macro `writeln` (in Nightly builds, run with -Z macro-backtrace for more info)
 help: consider using a semicolon here
    |
 LL |     };
diff --git a/tests/ui/typeck/question-mark-operator-suggestion-span.stderr b/tests/ui/typeck/question-mark-operator-suggestion-span.stderr
index 089b3bcd1988..f567e553d8b7 100644
--- a/tests/ui/typeck/question-mark-operator-suggestion-span.stderr
+++ b/tests/ui/typeck/question-mark-operator-suggestion-span.stderr
@@ -12,7 +12,6 @@ LL | |     }
    |
    = note: expected unit type `()`
                    found enum `Result<(), std::fmt::Error>`
-   = note: this error originates in the macro `writeln` (in Nightly builds, run with -Z macro-backtrace for more info)
 help: consider using a semicolon here
    |
 LL |     };
diff --git a/tests/ui/typeck/suggestions/suggest-clone-in-macro-issue-139253.stderr b/tests/ui/typeck/suggestions/suggest-clone-in-macro-issue-139253.stderr
index 972c2ced0037..6785d48eca60 100644
--- a/tests/ui/typeck/suggestions/suggest-clone-in-macro-issue-139253.stderr
+++ b/tests/ui/typeck/suggestions/suggest-clone-in-macro-issue-139253.stderr
@@ -26,7 +26,6 @@ error[E0308]: mismatched types
 LL |     let c: S = dbg!(field);
    |                ^^^^^^^^^^^ expected `S`, found `&S`
    |
-   = note: this error originates in the macro `$crate::macros::dbg_internal` which comes from the expansion of the macro `dbg` (in Nightly builds, run with -Z macro-backtrace for more info)
 help: consider using clone here
    |
 LL |     let c: S = dbg!(field).clone();
@@ -38,7 +37,6 @@ error[E0308]: mismatched types
 LL |     let c: S = dbg!(dbg!(field));
    |                ^^^^^^^^^^^^^^^^^ expected `S`, found `&S`
    |
-   = note: this error originates in the macro `$crate::macros::dbg_internal` which comes from the expansion of the macro `dbg` (in Nightly builds, run with -Z macro-backtrace for more info)
 help: consider using clone here
    |
 LL |     let c: S = dbg!(dbg!(field)).clone();
diff --git a/tests/ui/uninhabited/void-branch.stderr b/tests/ui/uninhabited/void-branch.stderr
index ee5efb94ed21..15693fc85f4b 100644
--- a/tests/ui/uninhabited/void-branch.stderr
+++ b/tests/ui/uninhabited/void-branch.stderr
@@ -16,7 +16,6 @@ note: the lint level is defined here
    |
 LL | #![deny(unreachable_code)]
    |         ^^^^^^^^^^^^^^^^
-   = note: this error originates in the macro `$crate::format_args` which comes from the expansion of the macro `println` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error: unreachable expression
   --> $DIR/void-branch.rs:25:9
@@ -31,7 +30,6 @@ note: this expression has type `Infallible`, which is uninhabited
    |
 LL |         infallible();
    |         ^^^^^^^^^^^^
-   = note: this error originates in the macro `$crate::format_args` which comes from the expansion of the macro `println` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error: aborting due to 2 previous errors
 
diff --git a/tests/ui/use/use-after-move-based-on-type.stderr b/tests/ui/use/use-after-move-based-on-type.stderr
index 02a6ed599a92..1e72b3a1e95a 100644
--- a/tests/ui/use/use-after-move-based-on-type.stderr
+++ b/tests/ui/use/use-after-move-based-on-type.stderr
@@ -8,7 +8,6 @@ LL |     let _y = x;
 LL |     println!("{}", x);
    |                    ^ value borrowed here after move
    |
-   = note: this error originates in the macro `$crate::format_args_nl` which comes from the expansion of the macro `println` (in Nightly builds, run with -Z macro-backtrace for more info)
 help: consider cloning the value if the performance cost is acceptable
    |
 LL |     let _y = x.clone();

From 0ef4c3aca7ab97df85f2aaf1e7f542faf4528b51 Mon Sep 17 00:00:00 2001
From: Folkert de Vries <folkert@folkertdev.nl>
Date: Mon, 26 Jan 2026 20:42:22 +0100
Subject: [PATCH 46/97] use `simd_splat` for the `set1` functions

---
 .../stdarch/crates/core_arch/src/x86/avx.rs    | 18 ++++++------------
 .../stdarch/crates/core_arch/src/x86/sse.rs    |  2 +-
 .../stdarch/crates/core_arch/src/x86/sse2.rs   |  8 ++++----
 3 files changed, 11 insertions(+), 17 deletions(-)

diff --git a/library/stdarch/crates/core_arch/src/x86/avx.rs b/library/stdarch/crates/core_arch/src/x86/avx.rs
index e0e01ae6d034..c8cddad2efa6 100644
--- a/library/stdarch/crates/core_arch/src/x86/avx.rs
+++ b/library/stdarch/crates/core_arch/src/x86/avx.rs
@@ -2746,7 +2746,7 @@ pub const fn _mm256_setr_epi64x(a: i64, b: i64, c: i64, d: i64) -> __m256i {
 #[stable(feature = "simd_x86", since = "1.27.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_set1_pd(a: f64) -> __m256d {
-    _mm256_setr_pd(a, a, a, a)
+    f64x4::splat(a).as_m256d()
 }
 
 /// Broadcasts single-precision (32-bit) floating-point value `a` to all
@@ -2759,7 +2759,7 @@ pub const fn _mm256_set1_pd(a: f64) -> __m256d {
 #[stable(feature = "simd_x86", since = "1.27.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_set1_ps(a: f32) -> __m256 {
-    _mm256_setr_ps(a, a, a, a, a, a, a, a)
+    f32x8::splat(a).as_m256()
 }
 
 /// Broadcasts 8-bit integer `a` to all elements of returned vector.
@@ -2772,13 +2772,7 @@ pub const fn _mm256_set1_ps(a: f32) -> __m256 {
 #[stable(feature = "simd_x86", since = "1.27.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_set1_epi8(a: i8) -> __m256i {
-    #[rustfmt::skip]
-    _mm256_setr_epi8(
-        a, a, a, a, a, a, a, a,
-        a, a, a, a, a, a, a, a,
-        a, a, a, a, a, a, a, a,
-        a, a, a, a, a, a, a, a,
-    )
+    i8x32::splat(a).as_m256i()
 }
 
 /// Broadcasts 16-bit integer `a` to all elements of returned vector.
@@ -2793,7 +2787,7 @@ pub const fn _mm256_set1_epi8(a: i8) -> __m256i {
 #[stable(feature = "simd_x86", since = "1.27.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_set1_epi16(a: i16) -> __m256i {
-    _mm256_setr_epi16(a, a, a, a, a, a, a, a, a, a, a, a, a, a, a, a)
+    i16x16::splat(a).as_m256i()
 }
 
 /// Broadcasts 32-bit integer `a` to all elements of returned vector.
@@ -2806,7 +2800,7 @@ pub const fn _mm256_set1_epi16(a: i16) -> __m256i {
 #[stable(feature = "simd_x86", since = "1.27.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_set1_epi32(a: i32) -> __m256i {
-    _mm256_setr_epi32(a, a, a, a, a, a, a, a)
+    i32x8::splat(a).as_m256i()
 }
 
 /// Broadcasts 64-bit integer `a` to all elements of returned vector.
@@ -2821,7 +2815,7 @@ pub const fn _mm256_set1_epi32(a: i32) -> __m256i {
 #[stable(feature = "simd_x86", since = "1.27.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm256_set1_epi64x(a: i64) -> __m256i {
-    _mm256_setr_epi64x(a, a, a, a)
+    i64x4::splat(a).as_m256i()
 }
 
 /// Cast vector of type __m256d to type __m256.
diff --git a/library/stdarch/crates/core_arch/src/x86/sse.rs b/library/stdarch/crates/core_arch/src/x86/sse.rs
index f167e8381d27..38b309c1cb79 100644
--- a/library/stdarch/crates/core_arch/src/x86/sse.rs
+++ b/library/stdarch/crates/core_arch/src/x86/sse.rs
@@ -932,7 +932,7 @@ pub const fn _mm_set_ss(a: f32) -> __m128 {
 #[stable(feature = "simd_x86", since = "1.27.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_set1_ps(a: f32) -> __m128 {
-    __m128([a, a, a, a])
+    f32x4::splat(a).as_m128()
 }
 
 /// Alias for [`_mm_set1_ps`](fn._mm_set1_ps.html)
diff --git a/library/stdarch/crates/core_arch/src/x86/sse2.rs b/library/stdarch/crates/core_arch/src/x86/sse2.rs
index fc010e8467bb..d712c4f4c5d7 100644
--- a/library/stdarch/crates/core_arch/src/x86/sse2.rs
+++ b/library/stdarch/crates/core_arch/src/x86/sse2.rs
@@ -1176,7 +1176,7 @@ pub const fn _mm_set_epi8(
 #[stable(feature = "simd_x86", since = "1.27.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_set1_epi64x(a: i64) -> __m128i {
-    _mm_set_epi64x(a, a)
+    i64x2::splat(a).as_m128i()
 }
 
 /// Broadcasts 32-bit integer `a` to all elements.
@@ -1188,7 +1188,7 @@ pub const fn _mm_set1_epi64x(a: i64) -> __m128i {
 #[stable(feature = "simd_x86", since = "1.27.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_set1_epi32(a: i32) -> __m128i {
-    _mm_set_epi32(a, a, a, a)
+    i32x4::splat(a).as_m128i()
 }
 
 /// Broadcasts 16-bit integer `a` to all elements.
@@ -1200,7 +1200,7 @@ pub const fn _mm_set1_epi32(a: i32) -> __m128i {
 #[stable(feature = "simd_x86", since = "1.27.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_set1_epi16(a: i16) -> __m128i {
-    _mm_set_epi16(a, a, a, a, a, a, a, a)
+    i16x8::splat(a).as_m128i()
 }
 
 /// Broadcasts 8-bit integer `a` to all elements.
@@ -1212,7 +1212,7 @@ pub const fn _mm_set1_epi16(a: i16) -> __m128i {
 #[stable(feature = "simd_x86", since = "1.27.0")]
 #[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
 pub const fn _mm_set1_epi8(a: i8) -> __m128i {
-    _mm_set_epi8(a, a, a, a, a, a, a, a, a, a, a, a, a, a, a, a)
+    i8x16::splat(a).as_m128i()
 }
 
 /// Sets packed 32-bit integers with the supplied values in reverse order.

From fdad66a382cc53f284a8194e140e42df4b20222d Mon Sep 17 00:00:00 2001
From: Folkert de Vries <folkert@folkertdev.nl>
Date: Mon, 26 Jan 2026 23:17:31 +0100
Subject: [PATCH 47/97] enable `target_feature_inline_always` in `core` and
 `std`

this is required for compiling `stdarch`
---
 library/core/src/lib.rs | 1 +
 library/std/src/lib.rs  | 1 +
 2 files changed, 2 insertions(+)

diff --git a/library/core/src/lib.rs b/library/core/src/lib.rs
index c4d16ba633b8..e8c9d26fb3b5 100644
--- a/library/core/src/lib.rs
+++ b/library/core/src/lib.rs
@@ -182,6 +182,7 @@
 #![feature(staged_api)]
 #![feature(stmt_expr_attributes)]
 #![feature(strict_provenance_lints)]
+#![feature(target_feature_inline_always)]
 #![feature(trait_alias)]
 #![feature(transparent_unions)]
 #![feature(try_blocks)]
diff --git a/library/std/src/lib.rs b/library/std/src/lib.rs
index 8bec157e4e6e..b213fa749177 100644
--- a/library/std/src/lib.rs
+++ b/library/std/src/lib.rs
@@ -309,6 +309,7 @@
 #![feature(staged_api)]
 #![feature(stmt_expr_attributes)]
 #![feature(strict_provenance_lints)]
+#![feature(target_feature_inline_always)]
 #![feature(thread_local)]
 #![feature(try_blocks)]
 #![feature(try_trait_v2)]

From 0385e26e7d1e6a984954d1daa448471e9ef1051e Mon Sep 17 00:00:00 2001
From: Nicholas Nethercote <n.nethercote@gmail.com>
Date: Tue, 20 Jan 2026 11:56:19 +1100
Subject: [PATCH 48/97] Reintroduce `QueryStackFrame` split.

I tried removing it in #151203, to replace it with something simpler.
But a couple of fuzzing failures have come up and I don't have a clear
picture on how to fix them. So I'm reverting the main part of #151203.

This commit also adds the two fuzzing tests.

Fixes #151226, #151358.
---
 compiler/rustc_middle/src/query/mod.rs        |   2 +-
 compiler/rustc_middle/src/query/plumbing.rs   |   2 +-
 compiler/rustc_middle/src/ty/print/pretty.rs  |   4 +-
 compiler/rustc_middle/src/values.rs           |   4 +-
 compiler/rustc_query_impl/src/lib.rs          |   9 +-
 compiler/rustc_query_impl/src/plumbing.rs     |  96 ++++++++-----
 .../rustc_query_system/src/query/config.rs    |   5 +-
 compiler/rustc_query_system/src/query/job.rs  | 131 ++++++++++--------
 compiler/rustc_query_system/src/query/mod.rs  | 105 ++++++++++++--
 .../rustc_query_system/src/query/plumbing.rs  |  61 ++++----
 .../query-cycle-printing-issue-151226.rs      |   8 ++
 .../query-cycle-printing-issue-151226.stderr  |  36 +++++
 .../query-cycle-printing-issue-151358.rs      |   7 +
 .../query-cycle-printing-issue-151358.stderr  |   9 ++
 tests/ui/resolve/query-cycle-issue-124901.rs  |   2 +-
 .../resolve/query-cycle-issue-124901.stderr   |   9 +-
 16 files changed, 341 insertions(+), 149 deletions(-)
 create mode 100644 tests/ui/query-system/query-cycle-printing-issue-151226.rs
 create mode 100644 tests/ui/query-system/query-cycle-printing-issue-151226.stderr
 create mode 100644 tests/ui/query-system/query-cycle-printing-issue-151358.rs
 create mode 100644 tests/ui/query-system/query-cycle-printing-issue-151358.stderr

diff --git a/compiler/rustc_middle/src/query/mod.rs b/compiler/rustc_middle/src/query/mod.rs
index 2f83f3078e89..9d17c998a8f2 100644
--- a/compiler/rustc_middle/src/query/mod.rs
+++ b/compiler/rustc_middle/src/query/mod.rs
@@ -88,7 +88,7 @@ use rustc_index::IndexVec;
 use rustc_lint_defs::LintId;
 use rustc_macros::rustc_queries;
 use rustc_query_system::ich::StableHashingContext;
-use rustc_query_system::query::{QueryMode, QueryState};
+use rustc_query_system::query::{QueryMode, QueryStackDeferred, QueryState};
 use rustc_session::Limits;
 use rustc_session::config::{EntryFnType, OptLevel, OutputFilenames, SymbolManglingVersion};
 use rustc_session::cstore::{
diff --git a/compiler/rustc_middle/src/query/plumbing.rs b/compiler/rustc_middle/src/query/plumbing.rs
index 17330f4e14be..9ee8d743e64a 100644
--- a/compiler/rustc_middle/src/query/plumbing.rs
+++ b/compiler/rustc_middle/src/query/plumbing.rs
@@ -427,7 +427,7 @@ macro_rules! define_callbacks {
         #[derive(Default)]
         pub struct QueryStates<'tcx> {
             $(
-                pub $name: QueryState<$($K)*>,
+                pub $name: QueryState<$($K)*, QueryStackDeferred<'tcx>>,
             )*
         }
 
diff --git a/compiler/rustc_middle/src/ty/print/pretty.rs b/compiler/rustc_middle/src/ty/print/pretty.rs
index de13c4f836a5..76a4f61e6714 100644
--- a/compiler/rustc_middle/src/ty/print/pretty.rs
+++ b/compiler/rustc_middle/src/ty/print/pretty.rs
@@ -159,9 +159,7 @@ pub macro with_types_for_signature($e:expr) {{
 /// Avoids running any queries during prints.
 pub macro with_no_queries($e:expr) {{
     $crate::ty::print::with_reduced_queries!($crate::ty::print::with_forced_impl_filename_line!(
-        $crate::ty::print::with_no_trimmed_paths!($crate::ty::print::with_no_visible_paths!(
-            $crate::ty::print::with_forced_impl_filename_line!($e)
-        ))
+        $crate::ty::print::with_no_trimmed_paths!($crate::ty::print::with_no_visible_paths!($e))
     ))
 }}
 
diff --git a/compiler/rustc_middle/src/values.rs b/compiler/rustc_middle/src/values.rs
index 8d614a535498..bc73d36216ef 100644
--- a/compiler/rustc_middle/src/values.rs
+++ b/compiler/rustc_middle/src/values.rs
@@ -88,7 +88,7 @@ impl<'tcx> Value<TyCtxt<'tcx>> for Representability {
             if info.query.dep_kind == dep_kinds::representability
                 && let Some(field_id) = info.query.def_id
                 && let Some(field_id) = field_id.as_local()
-                && let Some(DefKind::Field) = info.query.def_kind
+                && let Some(DefKind::Field) = info.query.info.def_kind
             {
                 let parent_id = tcx.parent(field_id.to_def_id());
                 let item_id = match tcx.def_kind(parent_id) {
@@ -224,7 +224,7 @@ impl<'tcx, T> Value<TyCtxt<'tcx>> for Result<T, &'_ ty::layout::LayoutError<'_>>
                             continue;
                         };
                         let frame_span =
-                            frame.query.default_span(cycle[(i + 1) % cycle.len()].span);
+                            frame.query.info.default_span(cycle[(i + 1) % cycle.len()].span);
                         if frame_span.is_dummy() {
                             continue;
                         }
diff --git a/compiler/rustc_query_impl/src/lib.rs b/compiler/rustc_query_impl/src/lib.rs
index 57027e937a4a..e8983bfa1ddb 100644
--- a/compiler/rustc_query_impl/src/lib.rs
+++ b/compiler/rustc_query_impl/src/lib.rs
@@ -23,7 +23,7 @@ use rustc_query_system::dep_graph::SerializedDepNodeIndex;
 use rustc_query_system::ich::StableHashingContext;
 use rustc_query_system::query::{
     CycleError, CycleErrorHandling, HashResult, QueryCache, QueryConfig, QueryMap, QueryMode,
-    QueryState, get_query_incr, get_query_non_incr,
+    QueryStackDeferred, QueryState, get_query_incr, get_query_non_incr,
 };
 use rustc_span::{ErrorGuaranteed, Span};
 
@@ -79,7 +79,10 @@ where
     }
 
     #[inline(always)]
-    fn query_state<'a>(self, qcx: QueryCtxt<'tcx>) -> &'a QueryState<Self::Key>
+    fn query_state<'a>(
+        self,
+        qcx: QueryCtxt<'tcx>,
+    ) -> &'a QueryState<Self::Key, QueryStackDeferred<'tcx>>
     where
         QueryCtxt<'tcx>: 'a,
     {
@@ -88,7 +91,7 @@ where
         unsafe {
             &*(&qcx.tcx.query_system.states as *const QueryStates<'tcx>)
                 .byte_add(self.dynamic.query_state)
-                .cast::<QueryState<Self::Key>>()
+                .cast::<QueryState<Self::Key, QueryStackDeferred<'tcx>>>()
         }
     }
 
diff --git a/compiler/rustc_query_impl/src/plumbing.rs b/compiler/rustc_query_impl/src/plumbing.rs
index 246152f5390c..847b5f901d7f 100644
--- a/compiler/rustc_query_impl/src/plumbing.rs
+++ b/compiler/rustc_query_impl/src/plumbing.rs
@@ -6,6 +6,7 @@ use std::num::NonZero;
 
 use rustc_data_structures::jobserver::Proxy;
 use rustc_data_structures::stable_hasher::{HashStable, StableHasher};
+use rustc_data_structures::sync::{DynSend, DynSync};
 use rustc_data_structures::unord::UnordMap;
 use rustc_hashes::Hash64;
 use rustc_hir::limit::Limit;
@@ -26,8 +27,8 @@ use rustc_middle::ty::{self, TyCtxt};
 use rustc_query_system::dep_graph::{DepNodeParams, HasDepContext};
 use rustc_query_system::ich::StableHashingContext;
 use rustc_query_system::query::{
-    QueryCache, QueryConfig, QueryContext, QueryJobId, QueryMap, QuerySideEffect, QueryStackFrame,
-    force_query,
+    QueryCache, QueryConfig, QueryContext, QueryJobId, QueryMap, QuerySideEffect,
+    QueryStackDeferred, QueryStackFrame, QueryStackFrameExtra, force_query,
 };
 use rustc_query_system::{QueryOverflow, QueryOverflowNote};
 use rustc_serialize::{Decodable, Encodable};
@@ -66,7 +67,9 @@ impl<'tcx> HasDepContext for QueryCtxt<'tcx> {
     }
 }
 
-impl QueryContext for QueryCtxt<'_> {
+impl<'tcx> QueryContext for QueryCtxt<'tcx> {
+    type QueryInfo = QueryStackDeferred<'tcx>;
+
     #[inline]
     fn jobserver_proxy(&self) -> &Proxy {
         &*self.jobserver_proxy
@@ -95,7 +98,10 @@ impl QueryContext for QueryCtxt<'_> {
     /// Prefer passing `false` to `require_complete` to avoid potential deadlocks,
     /// especially when called from within a deadlock handler, unless a
     /// complete map is needed and no deadlock is possible at this call site.
-    fn collect_active_jobs(self, require_complete: bool) -> Result<QueryMap, QueryMap> {
+    fn collect_active_jobs(
+        self,
+        require_complete: bool,
+    ) -> Result<QueryMap<QueryStackDeferred<'tcx>>, QueryMap<QueryStackDeferred<'tcx>>> {
         let mut jobs = QueryMap::default();
         let mut complete = true;
 
@@ -108,6 +114,13 @@ impl QueryContext for QueryCtxt<'_> {
         if complete { Ok(jobs) } else { Err(jobs) }
     }
 
+    fn lift_query_info(
+        self,
+        info: &QueryStackDeferred<'tcx>,
+    ) -> rustc_query_system::query::QueryStackFrameExtra {
+        info.extract()
+    }
+
     // Interactions with on_disk_cache
     fn load_side_effect(
         self,
@@ -168,7 +181,10 @@ impl QueryContext for QueryCtxt<'_> {
 
         self.sess.dcx().emit_fatal(QueryOverflow {
             span: info.job.span,
-            note: QueryOverflowNote { desc: info.query.description, depth },
+            note: QueryOverflowNote {
+                desc: self.lift_query_info(&info.query.info).description,
+                depth,
+            },
             suggested_limit,
             crate_name: self.crate_name(LOCAL_CRATE),
         });
@@ -305,16 +321,17 @@ macro_rules! should_ever_cache_on_disk {
     };
 }
 
-pub(crate) fn create_query_frame<
-    'tcx,
-    K: Copy + Key + for<'a> HashStable<StableHashingContext<'a>>,
->(
-    tcx: TyCtxt<'tcx>,
-    do_describe: fn(TyCtxt<'tcx>, K) -> String,
-    key: K,
-    kind: DepKind,
-    name: &'static str,
-) -> QueryStackFrame {
+fn create_query_frame_extra<'tcx, K: Key + Copy + 'tcx>(
+    (tcx, key, kind, name, do_describe): (
+        TyCtxt<'tcx>,
+        K,
+        DepKind,
+        &'static str,
+        fn(TyCtxt<'tcx>, K) -> String,
+    ),
+) -> QueryStackFrameExtra {
+    let def_id = key.key_as_def_id();
+
     // If reduced queries are requested, we may be printing a query stack due
     // to a panic. Avoid using `default_span` and `def_kind` in that case.
     let reduce_queries = with_reduced_queries();
@@ -326,36 +343,49 @@ pub(crate) fn create_query_frame<
     } else {
         description
     };
-
-    let span = if reduce_queries {
+    let span = if kind == dep_graph::dep_kinds::def_span || reduce_queries {
         // The `def_span` query is used to calculate `default_span`,
         // so exit to avoid infinite recursion.
         None
     } else {
-        Some(tcx.with_reduced_queries(|| key.default_span(tcx)))
+        Some(key.default_span(tcx))
     };
 
-    let def_id = key.key_as_def_id();
-
-    let def_kind = if reduce_queries {
+    let def_kind = if kind == dep_graph::dep_kinds::def_kind || reduce_queries {
         // Try to avoid infinite recursion.
         None
     } else {
-        def_id
-            .and_then(|def_id| def_id.as_local())
-            .map(|def_id| tcx.with_reduced_queries(|| tcx.def_kind(def_id)))
+        def_id.and_then(|def_id| def_id.as_local()).map(|def_id| tcx.def_kind(def_id))
     };
+    QueryStackFrameExtra::new(description, span, def_kind)
+}
 
+pub(crate) fn create_query_frame<
+    'tcx,
+    K: Copy + DynSend + DynSync + Key + for<'a> HashStable<StableHashingContext<'a>> + 'tcx,
+>(
+    tcx: TyCtxt<'tcx>,
+    do_describe: fn(TyCtxt<'tcx>, K) -> String,
+    key: K,
+    kind: DepKind,
+    name: &'static str,
+) -> QueryStackFrame<QueryStackDeferred<'tcx>> {
+    let def_id = key.key_as_def_id();
+
+    let hash = || {
+        tcx.with_stable_hashing_context(|mut hcx| {
+            let mut hasher = StableHasher::new();
+            kind.as_usize().hash_stable(&mut hcx, &mut hasher);
+            key.hash_stable(&mut hcx, &mut hasher);
+            hasher.finish::<Hash64>()
+        })
+    };
     let def_id_for_ty_in_cycle = key.def_id_for_ty_in_cycle();
 
-    let hash = tcx.with_stable_hashing_context(|mut hcx| {
-        let mut hasher = StableHasher::new();
-        kind.as_usize().hash_stable(&mut hcx, &mut hasher);
-        key.hash_stable(&mut hcx, &mut hasher);
-        hasher.finish::<Hash64>()
-    });
+    let info =
+        QueryStackDeferred::new((tcx, key, kind, name, do_describe), create_query_frame_extra);
 
-    QueryStackFrame::new(description, span, def_id, def_kind, kind, def_id_for_ty_in_cycle, hash)
+    QueryStackFrame::new(info, kind, hash, def_id, def_id_for_ty_in_cycle)
 }
 
 pub(crate) fn encode_query_results<'a, 'tcx, Q>(
@@ -710,7 +740,7 @@ macro_rules! define_queries {
 
             pub(crate) fn collect_active_jobs<'tcx>(
                 tcx: TyCtxt<'tcx>,
-                qmap: &mut QueryMap,
+                qmap: &mut QueryMap<QueryStackDeferred<'tcx>>,
                 require_complete: bool,
             ) -> Option<()> {
                 let make_query = |tcx, key| {
@@ -794,7 +824,7 @@ macro_rules! define_queries {
         // These arrays are used for iteration and can't be indexed by `DepKind`.
 
         const COLLECT_ACTIVE_JOBS: &[
-            for<'tcx> fn(TyCtxt<'tcx>, &mut QueryMap, bool) -> Option<()>
+            for<'tcx> fn(TyCtxt<'tcx>, &mut QueryMap<QueryStackDeferred<'tcx>>, bool) -> Option<()>
         ] =
             &[$(query_impl::$name::collect_active_jobs),*];
 
diff --git a/compiler/rustc_query_system/src/query/config.rs b/compiler/rustc_query_system/src/query/config.rs
index 739e8e3a8f26..66b04aa7b467 100644
--- a/compiler/rustc_query_system/src/query/config.rs
+++ b/compiler/rustc_query_system/src/query/config.rs
@@ -6,6 +6,7 @@ use std::hash::Hash;
 use rustc_data_structures::fingerprint::Fingerprint;
 use rustc_span::ErrorGuaranteed;
 
+use super::QueryStackFrameExtra;
 use crate::dep_graph::{DepKind, DepNode, DepNodeParams, SerializedDepNodeIndex};
 use crate::ich::StableHashingContext;
 use crate::query::caches::QueryCache;
@@ -26,7 +27,7 @@ pub trait QueryConfig<Qcx: QueryContext>: Copy {
     fn format_value(self) -> fn(&Self::Value) -> String;
 
     // Don't use this method to access query results, instead use the methods on TyCtxt
-    fn query_state<'a>(self, tcx: Qcx) -> &'a QueryState<Self::Key>
+    fn query_state<'a>(self, tcx: Qcx) -> &'a QueryState<Self::Key, Qcx::QueryInfo>
     where
         Qcx: 'a;
 
@@ -56,7 +57,7 @@ pub trait QueryConfig<Qcx: QueryContext>: Copy {
     fn value_from_cycle_error(
         self,
         tcx: Qcx::DepContext,
-        cycle_error: &CycleError,
+        cycle_error: &CycleError<QueryStackFrameExtra>,
         guar: ErrorGuaranteed,
     ) -> Self::Value;
 
diff --git a/compiler/rustc_query_system/src/query/job.rs b/compiler/rustc_query_system/src/query/job.rs
index 0431151c74c9..5810ce0cbe66 100644
--- a/compiler/rustc_query_system/src/query/job.rs
+++ b/compiler/rustc_query_system/src/query/job.rs
@@ -1,3 +1,4 @@
+use std::fmt::Debug;
 use std::hash::Hash;
 use std::io::Write;
 use std::iter;
@@ -11,6 +12,7 @@ use rustc_hir::def::DefKind;
 use rustc_session::Session;
 use rustc_span::{DUMMY_SP, Span};
 
+use super::QueryStackFrameExtra;
 use crate::dep_graph::DepContext;
 use crate::error::CycleStack;
 use crate::query::plumbing::CycleError;
@@ -18,45 +20,54 @@ use crate::query::{QueryContext, QueryStackFrame};
 
 /// Represents a span and a query key.
 #[derive(Clone, Debug)]
-pub struct QueryInfo {
+pub struct QueryInfo<I> {
     /// The span corresponding to the reason for which this query was required.
     pub span: Span,
-    pub query: QueryStackFrame,
+    pub query: QueryStackFrame<I>,
 }
 
-pub type QueryMap = FxHashMap<QueryJobId, QueryJobInfo>;
+impl<I> QueryInfo<I> {
+    pub(crate) fn lift<Qcx: QueryContext<QueryInfo = I>>(
+        &self,
+        qcx: Qcx,
+    ) -> QueryInfo<QueryStackFrameExtra> {
+        QueryInfo { span: self.span, query: self.query.lift(qcx) }
+    }
+}
+
+pub type QueryMap<I> = FxHashMap<QueryJobId, QueryJobInfo<I>>;
 
 /// A value uniquely identifying an active query job.
 #[derive(Copy, Clone, Eq, PartialEq, Hash, Debug)]
 pub struct QueryJobId(pub NonZero<u64>);
 
 impl QueryJobId {
-    fn query(self, map: &QueryMap) -> QueryStackFrame {
+    fn query<I: Clone>(self, map: &QueryMap<I>) -> QueryStackFrame<I> {
         map.get(&self).unwrap().query.clone()
     }
 
-    fn span(self, map: &QueryMap) -> Span {
+    fn span<I>(self, map: &QueryMap<I>) -> Span {
         map.get(&self).unwrap().job.span
     }
 
-    fn parent(self, map: &QueryMap) -> Option<QueryJobId> {
+    fn parent<I>(self, map: &QueryMap<I>) -> Option<QueryJobId> {
         map.get(&self).unwrap().job.parent
     }
 
-    fn latch(self, map: &QueryMap) -> Option<&QueryLatch> {
+    fn latch<I>(self, map: &QueryMap<I>) -> Option<&QueryLatch<I>> {
         map.get(&self).unwrap().job.latch.as_ref()
     }
 }
 
 #[derive(Clone, Debug)]
-pub struct QueryJobInfo {
-    pub query: QueryStackFrame,
-    pub job: QueryJob,
+pub struct QueryJobInfo<I> {
+    pub query: QueryStackFrame<I>,
+    pub job: QueryJob<I>,
 }
 
 /// Represents an active query job.
 #[derive(Debug)]
-pub struct QueryJob {
+pub struct QueryJob<I> {
     pub id: QueryJobId,
 
     /// The span corresponding to the reason for which this query was required.
@@ -66,23 +77,23 @@ pub struct QueryJob {
     pub parent: Option<QueryJobId>,
 
     /// The latch that is used to wait on this job.
-    latch: Option<QueryLatch>,
+    latch: Option<QueryLatch<I>>,
 }
 
-impl Clone for QueryJob {
+impl<I> Clone for QueryJob<I> {
     fn clone(&self) -> Self {
         Self { id: self.id, span: self.span, parent: self.parent, latch: self.latch.clone() }
     }
 }
 
-impl QueryJob {
+impl<I> QueryJob<I> {
     /// Creates a new query job.
     #[inline]
     pub fn new(id: QueryJobId, span: Span, parent: Option<QueryJobId>) -> Self {
         QueryJob { id, span, parent, latch: None }
     }
 
-    pub(super) fn latch(&mut self) -> QueryLatch {
+    pub(super) fn latch(&mut self) -> QueryLatch<I> {
         if self.latch.is_none() {
             self.latch = Some(QueryLatch::new());
         }
@@ -102,12 +113,12 @@ impl QueryJob {
 }
 
 impl QueryJobId {
-    pub(super) fn find_cycle_in_stack(
+    pub(super) fn find_cycle_in_stack<I: Clone>(
         &self,
-        query_map: QueryMap,
+        query_map: QueryMap<I>,
         current_job: &Option<QueryJobId>,
         span: Span,
-    ) -> CycleError {
+    ) -> CycleError<I> {
         // Find the waitee amongst `current_job` parents
         let mut cycle = Vec::new();
         let mut current_job = Option::clone(current_job);
@@ -141,7 +152,7 @@ impl QueryJobId {
 
     #[cold]
     #[inline(never)]
-    pub fn find_dep_kind_root(&self, query_map: QueryMap) -> (QueryJobInfo, usize) {
+    pub fn find_dep_kind_root<I: Clone>(&self, query_map: QueryMap<I>) -> (QueryJobInfo<I>, usize) {
         let mut depth = 1;
         let info = query_map.get(&self).unwrap();
         let dep_kind = info.query.dep_kind;
@@ -161,31 +172,31 @@ impl QueryJobId {
 }
 
 #[derive(Debug)]
-struct QueryWaiter {
+struct QueryWaiter<I> {
     query: Option<QueryJobId>,
     condvar: Condvar,
     span: Span,
-    cycle: Mutex<Option<CycleError>>,
+    cycle: Mutex<Option<CycleError<I>>>,
 }
 
 #[derive(Debug)]
-struct QueryLatchInfo {
+struct QueryLatchInfo<I> {
     complete: bool,
-    waiters: Vec<Arc<QueryWaiter>>,
+    waiters: Vec<Arc<QueryWaiter<I>>>,
 }
 
 #[derive(Debug)]
-pub(super) struct QueryLatch {
-    info: Arc<Mutex<QueryLatchInfo>>,
+pub(super) struct QueryLatch<I> {
+    info: Arc<Mutex<QueryLatchInfo<I>>>,
 }
 
-impl Clone for QueryLatch {
+impl<I> Clone for QueryLatch<I> {
     fn clone(&self) -> Self {
         Self { info: Arc::clone(&self.info) }
     }
 }
 
-impl QueryLatch {
+impl<I> QueryLatch<I> {
     fn new() -> Self {
         QueryLatch {
             info: Arc::new(Mutex::new(QueryLatchInfo { complete: false, waiters: Vec::new() })),
@@ -198,7 +209,7 @@ impl QueryLatch {
         qcx: impl QueryContext,
         query: Option<QueryJobId>,
         span: Span,
-    ) -> Result<(), CycleError> {
+    ) -> Result<(), CycleError<I>> {
         let waiter =
             Arc::new(QueryWaiter { query, span, cycle: Mutex::new(None), condvar: Condvar::new() });
         self.wait_on_inner(qcx, &waiter);
@@ -213,7 +224,7 @@ impl QueryLatch {
     }
 
     /// Awaits the caller on this latch by blocking the current thread.
-    fn wait_on_inner(&self, qcx: impl QueryContext, waiter: &Arc<QueryWaiter>) {
+    fn wait_on_inner(&self, qcx: impl QueryContext, waiter: &Arc<QueryWaiter<I>>) {
         let mut info = self.info.lock();
         if !info.complete {
             // We push the waiter on to the `waiters` list. It can be accessed inside
@@ -249,7 +260,7 @@ impl QueryLatch {
 
     /// Removes a single waiter from the list of waiters.
     /// This is used to break query cycles.
-    fn extract_waiter(&self, waiter: usize) -> Arc<QueryWaiter> {
+    fn extract_waiter(&self, waiter: usize) -> Arc<QueryWaiter<I>> {
         let mut info = self.info.lock();
         debug_assert!(!info.complete);
         // Remove the waiter from the list of waiters
@@ -269,7 +280,11 @@ type Waiter = (QueryJobId, usize);
 /// For visits of resumable waiters it returns Some(Some(Waiter)) which has the
 /// required information to resume the waiter.
 /// If all `visit` calls returns None, this function also returns None.
-fn visit_waiters<F>(query_map: &QueryMap, query: QueryJobId, mut visit: F) -> Option<Option<Waiter>>
+fn visit_waiters<I, F>(
+    query_map: &QueryMap<I>,
+    query: QueryJobId,
+    mut visit: F,
+) -> Option<Option<Waiter>>
 where
     F: FnMut(Span, QueryJobId) -> Option<Option<Waiter>>,
 {
@@ -299,8 +314,8 @@ where
 /// `span` is the reason for the `query` to execute. This is initially DUMMY_SP.
 /// If a cycle is detected, this initial value is replaced with the span causing
 /// the cycle.
-fn cycle_check(
-    query_map: &QueryMap,
+fn cycle_check<I>(
+    query_map: &QueryMap<I>,
     query: QueryJobId,
     span: Span,
     stack: &mut Vec<(Span, QueryJobId)>,
@@ -339,8 +354,8 @@ fn cycle_check(
 /// Finds out if there's a path to the compiler root (aka. code which isn't in a query)
 /// from `query` without going through any of the queries in `visited`.
 /// This is achieved with a depth first search.
-fn connected_to_root(
-    query_map: &QueryMap,
+fn connected_to_root<I>(
+    query_map: &QueryMap<I>,
     query: QueryJobId,
     visited: &mut FxHashSet<QueryJobId>,
 ) -> bool {
@@ -361,7 +376,7 @@ fn connected_to_root(
 }
 
 // Deterministically pick an query from a list
-fn pick_query<'a, T, F>(query_map: &QueryMap, queries: &'a [T], f: F) -> &'a T
+fn pick_query<'a, I: Clone, T, F>(query_map: &QueryMap<I>, queries: &'a [T], f: F) -> &'a T
 where
     F: Fn(&T) -> (Span, QueryJobId),
 {
@@ -386,10 +401,10 @@ where
 /// the function return true.
 /// If a cycle was not found, the starting query is removed from `jobs` and
 /// the function returns false.
-fn remove_cycle(
-    query_map: &QueryMap,
+fn remove_cycle<I: Clone>(
+    query_map: &QueryMap<I>,
     jobs: &mut Vec<QueryJobId>,
-    wakelist: &mut Vec<Arc<QueryWaiter>>,
+    wakelist: &mut Vec<Arc<QueryWaiter<I>>>,
 ) -> bool {
     let mut visited = FxHashSet::default();
     let mut stack = Vec::new();
@@ -490,7 +505,10 @@ fn remove_cycle(
 /// uses a query latch and then resuming that waiter.
 /// There may be multiple cycles involved in a deadlock, so this searches
 /// all active queries for cycles before finally resuming all the waiters at once.
-pub fn break_query_cycles(query_map: QueryMap, registry: &rustc_thread_pool::Registry) {
+pub fn break_query_cycles<I: Clone + Debug>(
+    query_map: QueryMap<I>,
+    registry: &rustc_thread_pool::Registry,
+) {
     let mut wakelist = Vec::new();
     // It is OK per the comments:
     // - https://github.com/rust-lang/rust/pull/131200#issuecomment-2798854932
@@ -541,7 +559,7 @@ pub fn report_cycle<'a>(
 ) -> Diag<'a> {
     assert!(!stack.is_empty());
 
-    let span = stack[0].query.default_span(stack[1 % stack.len()].span);
+    let span = stack[0].query.info.default_span(stack[1 % stack.len()].span);
 
     let mut cycle_stack = Vec::new();
 
@@ -550,31 +568,31 @@ pub fn report_cycle<'a>(
 
     for i in 1..stack.len() {
         let query = &stack[i].query;
-        let span = query.default_span(stack[(i + 1) % stack.len()].span);
-        cycle_stack.push(CycleStack { span, desc: query.description.to_owned() });
+        let span = query.info.default_span(stack[(i + 1) % stack.len()].span);
+        cycle_stack.push(CycleStack { span, desc: query.info.description.to_owned() });
     }
 
     let mut cycle_usage = None;
     if let Some((span, ref query)) = *usage {
         cycle_usage = Some(crate::error::CycleUsage {
-            span: query.default_span(span),
-            usage: query.description.to_string(),
+            span: query.info.default_span(span),
+            usage: query.info.description.to_string(),
         });
     }
 
-    let alias = if stack.iter().all(|entry| matches!(entry.query.def_kind, Some(DefKind::TyAlias)))
-    {
-        Some(crate::error::Alias::Ty)
-    } else if stack.iter().all(|entry| entry.query.def_kind == Some(DefKind::TraitAlias)) {
-        Some(crate::error::Alias::Trait)
-    } else {
-        None
-    };
+    let alias =
+        if stack.iter().all(|entry| matches!(entry.query.info.def_kind, Some(DefKind::TyAlias))) {
+            Some(crate::error::Alias::Ty)
+        } else if stack.iter().all(|entry| entry.query.info.def_kind == Some(DefKind::TraitAlias)) {
+            Some(crate::error::Alias::Trait)
+        } else {
+            None
+        };
 
     let cycle_diag = crate::error::Cycle {
         span,
         cycle_stack,
-        stack_bottom: stack[0].query.description.to_owned(),
+        stack_bottom: stack[0].query.info.description.to_owned(),
         alias,
         cycle_usage,
         stack_count,
@@ -610,11 +628,12 @@ pub fn print_query_stack<Qcx: QueryContext>(
         let Some(query_info) = query_map.get(&query) else {
             break;
         };
+        let query_extra = qcx.lift_query_info(&query_info.query.info);
         if Some(count_printed) < limit_frames || limit_frames.is_none() {
             // Only print to stderr as many stack frames as `num_frames` when present.
             dcx.struct_failure_note(format!(
                 "#{} [{:?}] {}",
-                count_printed, query_info.query.dep_kind, query_info.query.description
+                count_printed, query_info.query.dep_kind, query_extra.description
             ))
             .with_span(query_info.job.span)
             .emit();
@@ -627,7 +646,7 @@ pub fn print_query_stack<Qcx: QueryContext>(
                 "#{} [{}] {}",
                 count_total,
                 qcx.dep_context().dep_kind_vtable(query_info.query.dep_kind).name,
-                query_info.query.description
+                query_extra.description
             );
         }
 
diff --git a/compiler/rustc_query_system/src/query/mod.rs b/compiler/rustc_query_system/src/query/mod.rs
index 796f41d41efa..3ff980fa9bc5 100644
--- a/compiler/rustc_query_system/src/query/mod.rs
+++ b/compiler/rustc_query_system/src/query/mod.rs
@@ -1,4 +1,10 @@
+use std::fmt::Debug;
+use std::marker::PhantomData;
+use std::mem::transmute;
+use std::sync::Arc;
+
 use rustc_data_structures::jobserver::Proxy;
+use rustc_data_structures::sync::{DynSend, DynSync};
 use rustc_errors::DiagInner;
 use rustc_hashes::Hash64;
 use rustc_hir::def::DefKind;
@@ -36,31 +42,59 @@ pub enum CycleErrorHandling {
 ///
 /// This is mostly used in case of cycles for error reporting.
 #[derive(Clone, Debug)]
-pub struct QueryStackFrame {
-    pub description: String,
-    span: Option<Span>,
-    pub def_id: Option<DefId>,
-    pub def_kind: Option<DefKind>,
-    /// A def-id that is extracted from a `Ty` in a query key
-    pub def_id_for_ty_in_cycle: Option<DefId>,
+pub struct QueryStackFrame<I> {
+    /// This field initially stores a `QueryStackDeferred` during collection,
+    /// but can later be changed to `QueryStackFrameExtra` containing concrete information
+    /// by calling `lift`. This is done so that collecting query does not need to invoke
+    /// queries, instead `lift` will call queries in a more appropriate location.
+    pub info: I,
+
     pub dep_kind: DepKind,
     /// This hash is used to deterministically pick
     /// a query to remove cycles in the parallel compiler.
     hash: Hash64,
+    pub def_id: Option<DefId>,
+    /// A def-id that is extracted from a `Ty` in a query key
+    pub def_id_for_ty_in_cycle: Option<DefId>,
 }
 
-impl QueryStackFrame {
+impl<I> QueryStackFrame<I> {
     #[inline]
     pub fn new(
-        description: String,
-        span: Option<Span>,
-        def_id: Option<DefId>,
-        def_kind: Option<DefKind>,
+        info: I,
         dep_kind: DepKind,
+        hash: impl FnOnce() -> Hash64,
+        def_id: Option<DefId>,
         def_id_for_ty_in_cycle: Option<DefId>,
-        hash: Hash64,
     ) -> Self {
-        Self { description, span, def_id, def_kind, def_id_for_ty_in_cycle, dep_kind, hash }
+        Self { info, def_id, dep_kind, hash: hash(), def_id_for_ty_in_cycle }
+    }
+
+    fn lift<Qcx: QueryContext<QueryInfo = I>>(
+        &self,
+        qcx: Qcx,
+    ) -> QueryStackFrame<QueryStackFrameExtra> {
+        QueryStackFrame {
+            info: qcx.lift_query_info(&self.info),
+            dep_kind: self.dep_kind,
+            hash: self.hash,
+            def_id: self.def_id,
+            def_id_for_ty_in_cycle: self.def_id_for_ty_in_cycle,
+        }
+    }
+}
+
+#[derive(Clone, Debug)]
+pub struct QueryStackFrameExtra {
+    pub description: String,
+    span: Option<Span>,
+    pub def_kind: Option<DefKind>,
+}
+
+impl QueryStackFrameExtra {
+    #[inline]
+    pub fn new(description: String, span: Option<Span>, def_kind: Option<DefKind>) -> Self {
+        Self { description, span, def_kind }
     }
 
     // FIXME(eddyb) Get more valid `Span`s on queries.
@@ -73,6 +107,40 @@ impl QueryStackFrame {
     }
 }
 
+/// Track a 'side effect' for a particular query.
+/// This is used to hold a closure which can create `QueryStackFrameExtra`.
+#[derive(Clone)]
+pub struct QueryStackDeferred<'tcx> {
+    _dummy: PhantomData<&'tcx ()>,
+
+    // `extract` may contain references to 'tcx, but we can't tell drop checking that it won't
+    // access it in the destructor.
+    extract: Arc<dyn Fn() -> QueryStackFrameExtra + DynSync + DynSend>,
+}
+
+impl<'tcx> QueryStackDeferred<'tcx> {
+    pub fn new<C: Copy + DynSync + DynSend + 'tcx>(
+        context: C,
+        extract: fn(C) -> QueryStackFrameExtra,
+    ) -> Self {
+        let extract: Arc<dyn Fn() -> QueryStackFrameExtra + DynSync + DynSend + 'tcx> =
+            Arc::new(move || extract(context));
+        // SAFETY: The `extract` closure does not access 'tcx in its destructor as the only
+        // captured variable is `context` which is Copy and cannot have a destructor.
+        Self { _dummy: PhantomData, extract: unsafe { transmute(extract) } }
+    }
+
+    pub fn extract(&self) -> QueryStackFrameExtra {
+        (self.extract)()
+    }
+}
+
+impl<'tcx> Debug for QueryStackDeferred<'tcx> {
+    fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result {
+        f.write_str("QueryStackDeferred")
+    }
+}
+
 /// Tracks 'side effects' for a particular query.
 /// This struct is saved to disk along with the query result,
 /// and loaded from disk if we mark the query as green.
@@ -92,6 +160,8 @@ pub enum QuerySideEffect {
 }
 
 pub trait QueryContext: HasDepContext {
+    type QueryInfo: Clone;
+
     /// Gets a jobserver reference which is used to release then acquire
     /// a token while waiting on a query.
     fn jobserver_proxy(&self) -> &Proxy;
@@ -101,7 +171,12 @@ pub trait QueryContext: HasDepContext {
     /// Get the query information from the TLS context.
     fn current_query_job(self) -> Option<QueryJobId>;
 
-    fn collect_active_jobs(self, require_complete: bool) -> Result<QueryMap, QueryMap>;
+    fn collect_active_jobs(
+        self,
+        require_complete: bool,
+    ) -> Result<QueryMap<Self::QueryInfo>, QueryMap<Self::QueryInfo>>;
+
+    fn lift_query_info(self, info: &Self::QueryInfo) -> QueryStackFrameExtra;
 
     /// Load a side effect associated to the node in the previous session.
     fn load_side_effect(
diff --git a/compiler/rustc_query_system/src/query/plumbing.rs b/compiler/rustc_query_system/src/query/plumbing.rs
index 150ad238dad9..5be4ee145208 100644
--- a/compiler/rustc_query_system/src/query/plumbing.rs
+++ b/compiler/rustc_query_system/src/query/plumbing.rs
@@ -18,7 +18,7 @@ use rustc_errors::{Diag, FatalError, StashKey};
 use rustc_span::{DUMMY_SP, Span};
 use tracing::instrument;
 
-use super::QueryConfig;
+use super::{QueryConfig, QueryStackFrameExtra};
 use crate::dep_graph::{DepContext, DepGraphData, DepNode, DepNodeIndex, DepNodeParams};
 use crate::ich::StableHashingContext;
 use crate::query::caches::QueryCache;
@@ -32,23 +32,23 @@ fn equivalent_key<K: Eq, V>(k: &K) -> impl Fn(&(K, V)) -> bool + '_ {
     move |x| x.0 == *k
 }
 
-pub struct QueryState<K> {
-    active: Sharded<hashbrown::HashTable<(K, QueryResult)>>,
+pub struct QueryState<K, I> {
+    active: Sharded<hashbrown::HashTable<(K, QueryResult<I>)>>,
 }
 
 /// Indicates the state of a query for a given key in a query map.
-enum QueryResult {
+enum QueryResult<I> {
     /// An already executing query. The query job can be used to await for its completion.
-    Started(QueryJob),
+    Started(QueryJob<I>),
 
     /// The query panicked. Queries trying to wait on this will raise a fatal error which will
     /// silently panic.
     Poisoned,
 }
 
-impl QueryResult {
+impl<I> QueryResult<I> {
     /// Unwraps the query job expecting that it has started.
-    fn expect_job(self) -> QueryJob {
+    fn expect_job(self) -> QueryJob<I> {
         match self {
             Self::Started(job) => job,
             Self::Poisoned => {
@@ -58,7 +58,7 @@ impl QueryResult {
     }
 }
 
-impl<K> QueryState<K>
+impl<K, I> QueryState<K, I>
 where
     K: Eq + Hash + Copy + Debug,
 {
@@ -69,13 +69,13 @@ where
     pub fn collect_active_jobs<Qcx: Copy>(
         &self,
         qcx: Qcx,
-        make_query: fn(Qcx, K) -> QueryStackFrame,
-        jobs: &mut QueryMap,
+        make_query: fn(Qcx, K) -> QueryStackFrame<I>,
+        jobs: &mut QueryMap<I>,
         require_complete: bool,
     ) -> Option<()> {
         let mut active = Vec::new();
 
-        let mut collect = |iter: LockGuard<'_, HashTable<(K, QueryResult)>>| {
+        let mut collect = |iter: LockGuard<'_, HashTable<(K, QueryResult<I>)>>| {
             for (k, v) in iter.iter() {
                 if let QueryResult::Started(ref job) = *v {
                     active.push((*k, job.clone()));
@@ -106,19 +106,19 @@ where
     }
 }
 
-impl<K> Default for QueryState<K> {
-    fn default() -> QueryState<K> {
+impl<K, I> Default for QueryState<K, I> {
+    fn default() -> QueryState<K, I> {
         QueryState { active: Default::default() }
     }
 }
 
 /// A type representing the responsibility to execute the job in the `job` field.
 /// This will poison the relevant query if dropped.
-struct JobOwner<'tcx, K>
+struct JobOwner<'tcx, K, I>
 where
     K: Eq + Hash + Copy,
 {
-    state: &'tcx QueryState<K>,
+    state: &'tcx QueryState<K, I>,
     key: K,
 }
 
@@ -159,7 +159,7 @@ where
         }
         CycleErrorHandling::Stash => {
             let guar = if let Some(root) = cycle_error.cycle.first()
-                && let Some(span) = root.query.span
+                && let Some(span) = root.query.info.span
             {
                 error.stash(span, StashKey::Cycle).unwrap()
             } else {
@@ -170,7 +170,7 @@ where
     }
 }
 
-impl<'tcx, K> JobOwner<'tcx, K>
+impl<'tcx, K, I> JobOwner<'tcx, K, I>
 where
     K: Eq + Hash + Copy,
 {
@@ -207,7 +207,7 @@ where
     }
 }
 
-impl<'tcx, K> Drop for JobOwner<'tcx, K>
+impl<'tcx, K, I> Drop for JobOwner<'tcx, K, I>
 where
     K: Eq + Hash + Copy,
 {
@@ -235,10 +235,19 @@ where
 }
 
 #[derive(Clone, Debug)]
-pub struct CycleError {
+pub struct CycleError<I = QueryStackFrameExtra> {
     /// The query and related span that uses the cycle.
-    pub usage: Option<(Span, QueryStackFrame)>,
-    pub cycle: Vec<QueryInfo>,
+    pub usage: Option<(Span, QueryStackFrame<I>)>,
+    pub cycle: Vec<QueryInfo<I>>,
+}
+
+impl<I> CycleError<I> {
+    fn lift<Qcx: QueryContext<QueryInfo = I>>(&self, qcx: Qcx) -> CycleError<QueryStackFrameExtra> {
+        CycleError {
+            usage: self.usage.as_ref().map(|(span, frame)| (*span, frame.lift(qcx))),
+            cycle: self.cycle.iter().map(|info| info.lift(qcx)).collect(),
+        }
+    }
 }
 
 /// Checks whether there is already a value for this key in the in-memory
@@ -275,10 +284,10 @@ where
 {
     // Ensure there was no errors collecting all active jobs.
     // We need the complete map to ensure we find a cycle to break.
-    let query_map = qcx.collect_active_jobs(false).expect("failed to collect active queries");
+    let query_map = qcx.collect_active_jobs(false).ok().expect("failed to collect active queries");
 
     let error = try_execute.find_cycle_in_stack(query_map, &qcx.current_query_job(), span);
-    (mk_cycle(query, qcx, error), None)
+    (mk_cycle(query, qcx, error.lift(qcx)), None)
 }
 
 #[inline(always)]
@@ -287,7 +296,7 @@ fn wait_for_query<Q, Qcx>(
     qcx: Qcx,
     span: Span,
     key: Q::Key,
-    latch: QueryLatch,
+    latch: QueryLatch<Qcx::QueryInfo>,
     current: Option<QueryJobId>,
 ) -> (Q::Value, Option<DepNodeIndex>)
 where
@@ -327,7 +336,7 @@ where
 
             (v, Some(index))
         }
-        Err(cycle) => (mk_cycle(query, qcx, cycle), None),
+        Err(cycle) => (mk_cycle(query, qcx, cycle.lift(qcx)), None),
     }
 }
 
@@ -405,7 +414,7 @@ where
 fn execute_job<Q, Qcx, const INCR: bool>(
     query: Q,
     qcx: Qcx,
-    state: &QueryState<Q::Key>,
+    state: &QueryState<Q::Key, Qcx::QueryInfo>,
     key: Q::Key,
     key_hash: u64,
     id: QueryJobId,
diff --git a/tests/ui/query-system/query-cycle-printing-issue-151226.rs b/tests/ui/query-system/query-cycle-printing-issue-151226.rs
new file mode 100644
index 000000000000..9d0a20737c9f
--- /dev/null
+++ b/tests/ui/query-system/query-cycle-printing-issue-151226.rs
@@ -0,0 +1,8 @@
+struct A<T>(std::sync::OnceLock<Self>);
+//~^ ERROR recursive type `A` has infinite size
+//~| ERROR cycle detected when computing layout of `A<()>`
+
+static B: A<()> = todo!();
+//~^ ERROR cycle occurred during layout computation
+
+fn main() {}
diff --git a/tests/ui/query-system/query-cycle-printing-issue-151226.stderr b/tests/ui/query-system/query-cycle-printing-issue-151226.stderr
new file mode 100644
index 000000000000..7e574b5911a3
--- /dev/null
+++ b/tests/ui/query-system/query-cycle-printing-issue-151226.stderr
@@ -0,0 +1,36 @@
+error[E0072]: recursive type `A` has infinite size
+  --> $DIR/query-cycle-printing-issue-151226.rs:1:1
+   |
+LL | struct A<T>(std::sync::OnceLock<Self>);
+   | ^^^^^^^^^^^ ------------------------- recursive without indirection
+   |
+help: insert some indirection (e.g., a `Box`, `Rc`, or `&`) to break the cycle
+   |
+LL | struct A<T>(Box<std::sync::OnceLock<Self>>);
+   |             ++++                         +
+
+error[E0391]: cycle detected when computing layout of `A<()>`
+   |
+   = note: ...which requires computing layout of `std::sync::once_lock::OnceLock<A<()>>`...
+   = note: ...which requires computing layout of `core::cell::UnsafeCell<core::mem::maybe_uninit::MaybeUninit<A<()>>>`...
+   = note: ...which requires computing layout of `core::mem::maybe_uninit::MaybeUninit<A<()>>`...
+   = note: ...which requires computing layout of `core::mem::manually_drop::ManuallyDrop<A<()>>`...
+   = note: ...which requires computing layout of `core::mem::maybe_dangling::MaybeDangling<A<()>>`...
+   = note: ...which again requires computing layout of `A<()>`, completing the cycle
+note: cycle used when checking that `B` is well-formed
+  --> $DIR/query-cycle-printing-issue-151226.rs:5:1
+   |
+LL | static B: A<()> = todo!();
+   | ^^^^^^^^^^^^^^^
+   = note: see https://rustc-dev-guide.rust-lang.org/overview.html#queries and https://rustc-dev-guide.rust-lang.org/query.html for more information
+
+error[E0080]: a cycle occurred during layout computation
+  --> $DIR/query-cycle-printing-issue-151226.rs:5:1
+   |
+LL | static B: A<()> = todo!();
+   | ^^^^^^^^^^^^^^^ evaluation of `B` failed here
+
+error: aborting due to 3 previous errors
+
+Some errors have detailed explanations: E0072, E0080, E0391.
+For more information about an error, try `rustc --explain E0072`.
diff --git a/tests/ui/query-system/query-cycle-printing-issue-151358.rs b/tests/ui/query-system/query-cycle-printing-issue-151358.rs
new file mode 100644
index 000000000000..04d8664420be
--- /dev/null
+++ b/tests/ui/query-system/query-cycle-printing-issue-151358.rs
@@ -0,0 +1,7 @@
+//~ ERROR: cycle detected when looking up span for `Default`
+trait Default {}
+use std::num::NonZero;
+fn main() {
+    NonZero();
+    format!("{}", 0);
+}
diff --git a/tests/ui/query-system/query-cycle-printing-issue-151358.stderr b/tests/ui/query-system/query-cycle-printing-issue-151358.stderr
new file mode 100644
index 000000000000..9c1d7b1de33a
--- /dev/null
+++ b/tests/ui/query-system/query-cycle-printing-issue-151358.stderr
@@ -0,0 +1,9 @@
+error[E0391]: cycle detected when looking up span for `Default`
+   |
+   = note: ...which immediately requires looking up span for `Default` again
+   = note: cycle used when perform lints prior to AST lowering
+   = note: see https://rustc-dev-guide.rust-lang.org/overview.html#queries and https://rustc-dev-guide.rust-lang.org/query.html for more information
+
+error: aborting due to 1 previous error
+
+For more information about this error, try `rustc --explain E0391`.
diff --git a/tests/ui/resolve/query-cycle-issue-124901.rs b/tests/ui/resolve/query-cycle-issue-124901.rs
index ccaee0e6bc6f..6cb1e58b6258 100644
--- a/tests/ui/resolve/query-cycle-issue-124901.rs
+++ b/tests/ui/resolve/query-cycle-issue-124901.rs
@@ -1,4 +1,4 @@
-//~ ERROR: cycle detected when getting HIR ID of `Default`
+//~ ERROR: cycle detected when looking up span for `Default`
 trait Default {
     type Id;
 
diff --git a/tests/ui/resolve/query-cycle-issue-124901.stderr b/tests/ui/resolve/query-cycle-issue-124901.stderr
index 3679925c6db4..9c1d7b1de33a 100644
--- a/tests/ui/resolve/query-cycle-issue-124901.stderr
+++ b/tests/ui/resolve/query-cycle-issue-124901.stderr
@@ -1,10 +1,7 @@
-error[E0391]: cycle detected when getting HIR ID of `Default`
+error[E0391]: cycle detected when looking up span for `Default`
    |
-   = note: ...which requires getting the crate HIR...
-   = note: ...which requires perform lints prior to AST lowering...
-   = note: ...which requires looking up span for `Default`...
-   = note: ...which again requires getting HIR ID of `Default`, completing the cycle
-   = note: cycle used when getting the resolver for lowering
+   = note: ...which immediately requires looking up span for `Default` again
+   = note: cycle used when perform lints prior to AST lowering
    = note: see https://rustc-dev-guide.rust-lang.org/overview.html#queries and https://rustc-dev-guide.rust-lang.org/query.html for more information
 
 error: aborting due to 1 previous error

From 9b15010686b4650d2eaad0a7ca129eda16199c72 Mon Sep 17 00:00:00 2001
From: Trevor Gross <tg@trevorgross.com>
Date: Thu, 22 Jan 2026 23:34:15 -0600
Subject: [PATCH 49/97] lint: Use rustc_apfloat for `overflowing_literals`, add
 f16 and f128

Switch to parsing float literals for overflow checks using
`rustc_apfloat` rather than host floats. This avoids small variations in
platform support and makes it possible to start checking `f16` and
`f128` as well.

Using APFloat matches what we try to do elsewhere to avoid platform
inconsistencies.
---
 Cargo.lock                               |  1 +
 compiler/rustc_lint/Cargo.toml           |  1 +
 compiler/rustc_lint/src/types/literal.rs | 35 ++++++++++-------
 library/core/src/fmt/float.rs            |  8 +++-
 tests/ui/lint/lint-type-overflow2.rs     |  6 +++
 tests/ui/lint/lint-type-overflow2.stderr | 48 ++++++++++++++++++++----
 6 files changed, 77 insertions(+), 22 deletions(-)

diff --git a/Cargo.lock b/Cargo.lock
index 01300d56cff9..89d0f9ed5cb6 100644
--- a/Cargo.lock
+++ b/Cargo.lock
@@ -4170,6 +4170,7 @@ version = "0.0.0"
 dependencies = [
  "bitflags",
  "rustc_abi",
+ "rustc_apfloat",
  "rustc_ast",
  "rustc_ast_pretty",
  "rustc_attr_parsing",
diff --git a/compiler/rustc_lint/Cargo.toml b/compiler/rustc_lint/Cargo.toml
index 3a50aac50cb3..035d8b4903fa 100644
--- a/compiler/rustc_lint/Cargo.toml
+++ b/compiler/rustc_lint/Cargo.toml
@@ -7,6 +7,7 @@ edition = "2024"
 # tidy-alphabetical-start
 bitflags = "2.4.1"
 rustc_abi = { path = "../rustc_abi" }
+rustc_apfloat = "0.2.0"
 rustc_ast = { path = "../rustc_ast" }
 rustc_ast_pretty = { path = "../rustc_ast_pretty" }
 rustc_attr_parsing = { path = "../rustc_attr_parsing" }
diff --git a/compiler/rustc_lint/src/types/literal.rs b/compiler/rustc_lint/src/types/literal.rs
index d49f599407c2..b6c67549c47e 100644
--- a/compiler/rustc_lint/src/types/literal.rs
+++ b/compiler/rustc_lint/src/types/literal.rs
@@ -1,10 +1,12 @@
 use hir::{ExprKind, Node};
 use rustc_abi::{Integer, Size};
+use rustc_apfloat::Float;
+use rustc_apfloat::ieee::{DoubleS, HalfS, IeeeFloat, QuadS, Semantics, SingleS};
 use rustc_hir::{HirId, attrs};
 use rustc_middle::ty::Ty;
 use rustc_middle::ty::layout::IntegerExt;
 use rustc_middle::{bug, ty};
-use rustc_span::Span;
+use rustc_span::{Span, Symbol};
 use {rustc_ast as ast, rustc_hir as hir};
 
 use crate::LateContext;
@@ -383,6 +385,13 @@ fn lint_uint_literal<'tcx>(
     }
 }
 
+/// `None` if `v` does not parse as the float type, otherwise indicates whether a literal rounds
+/// to infinity.
+fn float_is_infinite<S: Semantics>(v: Symbol) -> Option<bool> {
+    let x: IeeeFloat<S> = v.as_str().parse().ok()?;
+    Some(x.is_infinite())
+}
+
 pub(crate) fn lint_literal<'tcx>(
     cx: &LateContext<'tcx>,
     type_limits: &TypeLimits,
@@ -405,18 +414,18 @@ pub(crate) fn lint_literal<'tcx>(
             lint_uint_literal(cx, hir_id, span, lit, t)
         }
         ty::Float(t) => {
-            let (is_infinite, sym) = match lit.node {
-                ast::LitKind::Float(v, _) => match t {
-                    // FIXME(f16_f128): add this check once `is_infinite` is reliable (ABI
-                    // issues resolved).
-                    ty::FloatTy::F16 => (Ok(false), v),
-                    ty::FloatTy::F32 => (v.as_str().parse().map(f32::is_infinite), v),
-                    ty::FloatTy::F64 => (v.as_str().parse().map(f64::is_infinite), v),
-                    ty::FloatTy::F128 => (Ok(false), v),
-                },
-                _ => bug!(),
+            let ast::LitKind::Float(v, _) = lit.node else {
+                bug!();
             };
-            if is_infinite == Ok(true) {
+
+            let is_infinite = match t {
+                ty::FloatTy::F16 => float_is_infinite::<HalfS>(v),
+                ty::FloatTy::F32 => float_is_infinite::<SingleS>(v),
+                ty::FloatTy::F64 => float_is_infinite::<DoubleS>(v),
+                ty::FloatTy::F128 => float_is_infinite::<QuadS>(v),
+            };
+
+            if is_infinite == Some(true) {
                 cx.emit_span_lint(
                     OVERFLOWING_LITERALS,
                     span,
@@ -426,7 +435,7 @@ pub(crate) fn lint_literal<'tcx>(
                             .sess()
                             .source_map()
                             .span_to_snippet(lit.span)
-                            .unwrap_or_else(|_| sym.to_string()),
+                            .unwrap_or_else(|_| v.to_string()),
                     },
                 );
             }
diff --git a/library/core/src/fmt/float.rs b/library/core/src/fmt/float.rs
index 556db239f249..59a74b7e0e5c 100644
--- a/library/core/src/fmt/float.rs
+++ b/library/core/src/fmt/float.rs
@@ -13,8 +13,14 @@ macro_rules! impl_general_format {
     ($($t:ident)*) => {
         $(impl GeneralFormat for $t {
             fn already_rounded_value_should_use_exponential(&self) -> bool {
+                // `max_abs` rounds to infinity for `f16`. This is fine to save us from a more
+                // complex macro, it just means a positive-exponent `f16` will never print as
+                // scientific notation by default (reasonably, the max is 65504.0).
+                #[allow(overflowing_literals)]
+                let max_abs = 1e+16;
+
                 let abs = $t::abs(*self);
-                (abs != 0.0 && abs < 1e-4) || abs >= 1e+16
+                (abs != 0.0 && abs < 1e-4) || abs >= max_abs
             }
         })*
     }
diff --git a/tests/ui/lint/lint-type-overflow2.rs b/tests/ui/lint/lint-type-overflow2.rs
index ac7420326c89..d3ff02aeb722 100644
--- a/tests/ui/lint/lint-type-overflow2.rs
+++ b/tests/ui/lint/lint-type-overflow2.rs
@@ -1,13 +1,19 @@
 //@ compile-flags: -O
 
+#![feature(f16)]
+#![feature(f128)]
 #![deny(overflowing_literals)]
 
 fn main() {
     let x2: i8 = --128; //~ ERROR literal out of range for `i8`
     //~| WARN use of a double negation
 
+    let x = -65520.0_f16; //~ ERROR literal out of range for `f16`
+    let x =  65520.0_f16; //~ ERROR literal out of range for `f16`
     let x = -3.40282357e+38_f32; //~ ERROR literal out of range for `f32`
     let x =  3.40282357e+38_f32; //~ ERROR literal out of range for `f32`
     let x = -1.7976931348623159e+308_f64; //~ ERROR literal out of range for `f64`
     let x =  1.7976931348623159e+308_f64; //~ ERROR literal out of range for `f64`
+    let x = -1.1897314953572317650857593266280075e+4932_f128; //~ ERROR literal out of range for `f128`
+    let x =  1.1897314953572317650857593266280075e+4932_f128; //~ ERROR literal out of range for `f128`
 }
diff --git a/tests/ui/lint/lint-type-overflow2.stderr b/tests/ui/lint/lint-type-overflow2.stderr
index 2cfb18e9fe92..c045d243753e 100644
--- a/tests/ui/lint/lint-type-overflow2.stderr
+++ b/tests/ui/lint/lint-type-overflow2.stderr
@@ -1,5 +1,5 @@
 warning: use of a double negation
-  --> $DIR/lint-type-overflow2.rs:6:18
+  --> $DIR/lint-type-overflow2.rs:8:18
    |
 LL |     let x2: i8 = --128;
    |                  ^^^^^
@@ -13,7 +13,7 @@ LL |     let x2: i8 = -(-128);
    |                   +    +
 
 error: literal out of range for `i8`
-  --> $DIR/lint-type-overflow2.rs:6:20
+  --> $DIR/lint-type-overflow2.rs:8:20
    |
 LL |     let x2: i8 = --128;
    |                    ^^^
@@ -21,13 +21,29 @@ LL |     let x2: i8 = --128;
    = note: the literal `128` does not fit into the type `i8` whose range is `-128..=127`
    = help: consider using the type `u8` instead
 note: the lint level is defined here
-  --> $DIR/lint-type-overflow2.rs:3:9
+  --> $DIR/lint-type-overflow2.rs:5:9
    |
 LL | #![deny(overflowing_literals)]
    |         ^^^^^^^^^^^^^^^^^^^^
 
+error: literal out of range for `f16`
+  --> $DIR/lint-type-overflow2.rs:11:14
+   |
+LL |     let x = -65520.0_f16;
+   |              ^^^^^^^^^^^
+   |
+   = note: the literal `65520.0_f16` does not fit into the type `f16` and will be converted to `f16::INFINITY`
+
+error: literal out of range for `f16`
+  --> $DIR/lint-type-overflow2.rs:12:14
+   |
+LL |     let x =  65520.0_f16;
+   |              ^^^^^^^^^^^
+   |
+   = note: the literal `65520.0_f16` does not fit into the type `f16` and will be converted to `f16::INFINITY`
+
 error: literal out of range for `f32`
-  --> $DIR/lint-type-overflow2.rs:9:14
+  --> $DIR/lint-type-overflow2.rs:13:14
    |
 LL |     let x = -3.40282357e+38_f32;
    |              ^^^^^^^^^^^^^^^^^^
@@ -35,7 +51,7 @@ LL |     let x = -3.40282357e+38_f32;
    = note: the literal `3.40282357e+38_f32` does not fit into the type `f32` and will be converted to `f32::INFINITY`
 
 error: literal out of range for `f32`
-  --> $DIR/lint-type-overflow2.rs:10:14
+  --> $DIR/lint-type-overflow2.rs:14:14
    |
 LL |     let x =  3.40282357e+38_f32;
    |              ^^^^^^^^^^^^^^^^^^
@@ -43,7 +59,7 @@ LL |     let x =  3.40282357e+38_f32;
    = note: the literal `3.40282357e+38_f32` does not fit into the type `f32` and will be converted to `f32::INFINITY`
 
 error: literal out of range for `f64`
-  --> $DIR/lint-type-overflow2.rs:11:14
+  --> $DIR/lint-type-overflow2.rs:15:14
    |
 LL |     let x = -1.7976931348623159e+308_f64;
    |              ^^^^^^^^^^^^^^^^^^^^^^^^^^^
@@ -51,12 +67,28 @@ LL |     let x = -1.7976931348623159e+308_f64;
    = note: the literal `1.7976931348623159e+308_f64` does not fit into the type `f64` and will be converted to `f64::INFINITY`
 
 error: literal out of range for `f64`
-  --> $DIR/lint-type-overflow2.rs:12:14
+  --> $DIR/lint-type-overflow2.rs:16:14
    |
 LL |     let x =  1.7976931348623159e+308_f64;
    |              ^^^^^^^^^^^^^^^^^^^^^^^^^^^
    |
    = note: the literal `1.7976931348623159e+308_f64` does not fit into the type `f64` and will be converted to `f64::INFINITY`
 
-error: aborting due to 5 previous errors; 1 warning emitted
+error: literal out of range for `f128`
+  --> $DIR/lint-type-overflow2.rs:17:14
+   |
+LL |     let x = -1.1897314953572317650857593266280075e+4932_f128;
+   |              ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+   |
+   = note: the literal `1.1897314953572317650857593266280075e+4932_f128` does not fit into the type `f128` and will be converted to `f128::INFINITY`
+
+error: literal out of range for `f128`
+  --> $DIR/lint-type-overflow2.rs:18:14
+   |
+LL |     let x =  1.1897314953572317650857593266280075e+4932_f128;
+   |              ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+   |
+   = note: the literal `1.1897314953572317650857593266280075e+4932_f128` does not fit into the type `f128` and will be converted to `f128::INFINITY`
+
+error: aborting due to 9 previous errors; 1 warning emitted
 

From 120247a76fdf68ad9004ec9acd9c5261140e53ff Mon Sep 17 00:00:00 2001
From: Nicholas Nethercote <n.nethercote@gmail.com>
Date: Wed, 14 Jan 2026 12:24:54 +1100
Subject: [PATCH 50/97] Use an associated type default for `Key::Cache`.

They currently aren't used because r-a didn't support them, but r-a
support was recently merged in
https://github.com/rust-lang/rust-analyzer/pull/21243.
---
 compiler/rustc_middle/src/query/keys.rs | 116 +-----------------------
 1 file changed, 1 insertion(+), 115 deletions(-)

diff --git a/compiler/rustc_middle/src/query/keys.rs b/compiler/rustc_middle/src/query/keys.rs
index dd9ba4325545..4fa8ca7d85bd 100644
--- a/compiler/rustc_middle/src/query/keys.rs
+++ b/compiler/rustc_middle/src/query/keys.rs
@@ -29,15 +29,7 @@ pub trait Key: Sized {
     /// constraint is not enforced here.
     ///
     /// [`QueryCache`]: rustc_query_system::query::QueryCache
-    // N.B. Most of the keys down below have `type Cache<V> = DefaultCache<Self, V>;`,
-    //      it would be reasonable to use associated type defaults, to remove the duplication...
-    //
-    //      ...But r-a doesn't support them yet and using a default here causes r-a to not infer
-    //      return types of queries which is very annoying. Thus, until r-a support associated
-    //      type defaults, please restrain from using them here <3
-    //
-    //      r-a issue: <https://github.com/rust-lang/rust-analyzer/issues/13693>
-    type Cache<V>;
+    type Cache<V> = DefaultCache<Self, V>;
 
     /// In the event that a cycle occurs, if no explicit span has been
     /// given for a query with key `self`, what span should we use?
@@ -72,8 +64,6 @@ impl Key for () {
 }
 
 impl<'tcx> Key for ty::InstanceKind<'tcx> {
-    type Cache<V> = DefaultCache<Self, V>;
-
     fn default_span(&self, tcx: TyCtxt<'_>) -> Span {
         tcx.def_span(self.def_id())
     }
@@ -89,32 +79,24 @@ impl<'tcx> AsLocalKey for ty::InstanceKind<'tcx> {
 }
 
 impl<'tcx> Key for ty::Instance<'tcx> {
-    type Cache<V> = DefaultCache<Self, V>;
-
     fn default_span(&self, tcx: TyCtxt<'_>) -> Span {
         tcx.def_span(self.def_id())
     }
 }
 
 impl<'tcx> Key for mir::interpret::GlobalId<'tcx> {
-    type Cache<V> = DefaultCache<Self, V>;
-
     fn default_span(&self, tcx: TyCtxt<'_>) -> Span {
         self.instance.default_span(tcx)
     }
 }
 
 impl<'tcx> Key for (Ty<'tcx>, Option<ty::ExistentialTraitRef<'tcx>>) {
-    type Cache<V> = DefaultCache<Self, V>;
-
     fn default_span(&self, _: TyCtxt<'_>) -> Span {
         DUMMY_SP
     }
 }
 
 impl<'tcx> Key for mir::interpret::LitToConstInput<'tcx> {
-    type Cache<V> = DefaultCache<Self, V>;
-
     fn default_span(&self, _tcx: TyCtxt<'_>) -> Span {
         DUMMY_SP
     }
@@ -184,8 +166,6 @@ impl AsLocalKey for DefId {
 }
 
 impl Key for LocalModDefId {
-    type Cache<V> = DefaultCache<Self, V>;
-
     fn default_span(&self, tcx: TyCtxt<'_>) -> Span {
         tcx.def_span(*self)
     }
@@ -197,8 +177,6 @@ impl Key for LocalModDefId {
 }
 
 impl Key for ModDefId {
-    type Cache<V> = DefaultCache<Self, V>;
-
     fn default_span(&self, tcx: TyCtxt<'_>) -> Span {
         tcx.def_span(*self)
     }
@@ -219,56 +197,42 @@ impl AsLocalKey for ModDefId {
 }
 
 impl Key for SimplifiedType {
-    type Cache<V> = DefaultCache<Self, V>;
-
     fn default_span(&self, _: TyCtxt<'_>) -> Span {
         DUMMY_SP
     }
 }
 
 impl Key for (DefId, DefId) {
-    type Cache<V> = DefaultCache<Self, V>;
-
     fn default_span(&self, tcx: TyCtxt<'_>) -> Span {
         self.1.default_span(tcx)
     }
 }
 
 impl<'tcx> Key for (ty::Instance<'tcx>, LocalDefId) {
-    type Cache<V> = DefaultCache<Self, V>;
-
     fn default_span(&self, tcx: TyCtxt<'_>) -> Span {
         self.0.default_span(tcx)
     }
 }
 
 impl Key for (DefId, LocalDefId) {
-    type Cache<V> = DefaultCache<Self, V>;
-
     fn default_span(&self, tcx: TyCtxt<'_>) -> Span {
         self.1.default_span(tcx)
     }
 }
 
 impl Key for (LocalDefId, DefId) {
-    type Cache<V> = DefaultCache<Self, V>;
-
     fn default_span(&self, tcx: TyCtxt<'_>) -> Span {
         self.0.default_span(tcx)
     }
 }
 
 impl Key for (LocalDefId, LocalDefId) {
-    type Cache<V> = DefaultCache<Self, V>;
-
     fn default_span(&self, tcx: TyCtxt<'_>) -> Span {
         self.0.default_span(tcx)
     }
 }
 
 impl Key for (DefId, Ident) {
-    type Cache<V> = DefaultCache<Self, V>;
-
     fn default_span(&self, tcx: TyCtxt<'_>) -> Span {
         tcx.def_span(self.0)
     }
@@ -280,16 +244,12 @@ impl Key for (DefId, Ident) {
 }
 
 impl Key for (LocalDefId, LocalDefId, Ident) {
-    type Cache<V> = DefaultCache<Self, V>;
-
     fn default_span(&self, tcx: TyCtxt<'_>) -> Span {
         self.1.default_span(tcx)
     }
 }
 
 impl Key for (CrateNum, DefId) {
-    type Cache<V> = DefaultCache<Self, V>;
-
     fn default_span(&self, tcx: TyCtxt<'_>) -> Span {
         self.1.default_span(tcx)
     }
@@ -305,8 +265,6 @@ impl AsLocalKey for (CrateNum, DefId) {
 }
 
 impl Key for (CrateNum, SimplifiedType) {
-    type Cache<V> = DefaultCache<Self, V>;
-
     fn default_span(&self, _: TyCtxt<'_>) -> Span {
         DUMMY_SP
     }
@@ -322,120 +280,90 @@ impl AsLocalKey for (CrateNum, SimplifiedType) {
 }
 
 impl Key for (DefId, SimplifiedType) {
-    type Cache<V> = DefaultCache<Self, V>;
-
     fn default_span(&self, tcx: TyCtxt<'_>) -> Span {
         self.0.default_span(tcx)
     }
 }
 
 impl Key for (DefId, ty::SizedTraitKind) {
-    type Cache<V> = DefaultCache<Self, V>;
-
     fn default_span(&self, tcx: TyCtxt<'_>) -> Span {
         self.0.default_span(tcx)
     }
 }
 
 impl<'tcx> Key for GenericArgsRef<'tcx> {
-    type Cache<V> = DefaultCache<Self, V>;
-
     fn default_span(&self, _: TyCtxt<'_>) -> Span {
         DUMMY_SP
     }
 }
 
 impl<'tcx> Key for (DefId, GenericArgsRef<'tcx>) {
-    type Cache<V> = DefaultCache<Self, V>;
-
     fn default_span(&self, tcx: TyCtxt<'_>) -> Span {
         self.0.default_span(tcx)
     }
 }
 
 impl<'tcx> Key for (ty::UnevaluatedConst<'tcx>, ty::UnevaluatedConst<'tcx>) {
-    type Cache<V> = DefaultCache<Self, V>;
-
     fn default_span(&self, tcx: TyCtxt<'_>) -> Span {
         (self.0).def.default_span(tcx)
     }
 }
 
 impl<'tcx> Key for (LocalDefId, DefId, GenericArgsRef<'tcx>) {
-    type Cache<V> = DefaultCache<Self, V>;
-
     fn default_span(&self, tcx: TyCtxt<'_>) -> Span {
         self.0.default_span(tcx)
     }
 }
 
 impl<'tcx> Key for (ty::ParamEnv<'tcx>, ty::TraitRef<'tcx>) {
-    type Cache<V> = DefaultCache<Self, V>;
-
     fn default_span(&self, tcx: TyCtxt<'_>) -> Span {
         tcx.def_span(self.1.def_id)
     }
 }
 
 impl<'tcx> Key for ty::ParamEnvAnd<'tcx, Ty<'tcx>> {
-    type Cache<V> = DefaultCache<Self, V>;
-
     fn default_span(&self, _tcx: TyCtxt<'_>) -> Span {
         DUMMY_SP
     }
 }
 
 impl<'tcx> Key for ty::TraitRef<'tcx> {
-    type Cache<V> = DefaultCache<Self, V>;
-
     fn default_span(&self, tcx: TyCtxt<'_>) -> Span {
         tcx.def_span(self.def_id)
     }
 }
 
 impl<'tcx> Key for ty::PolyTraitRef<'tcx> {
-    type Cache<V> = DefaultCache<Self, V>;
-
     fn default_span(&self, tcx: TyCtxt<'_>) -> Span {
         tcx.def_span(self.def_id())
     }
 }
 
 impl<'tcx> Key for ty::PolyExistentialTraitRef<'tcx> {
-    type Cache<V> = DefaultCache<Self, V>;
-
     fn default_span(&self, tcx: TyCtxt<'_>) -> Span {
         tcx.def_span(self.def_id())
     }
 }
 
 impl<'tcx> Key for (ty::PolyTraitRef<'tcx>, ty::PolyTraitRef<'tcx>) {
-    type Cache<V> = DefaultCache<Self, V>;
-
     fn default_span(&self, tcx: TyCtxt<'_>) -> Span {
         tcx.def_span(self.0.def_id())
     }
 }
 
 impl<'tcx> Key for GenericArg<'tcx> {
-    type Cache<V> = DefaultCache<Self, V>;
-
     fn default_span(&self, _: TyCtxt<'_>) -> Span {
         DUMMY_SP
     }
 }
 
 impl<'tcx> Key for ty::Const<'tcx> {
-    type Cache<V> = DefaultCache<Self, V>;
-
     fn default_span(&self, _: TyCtxt<'_>) -> Span {
         DUMMY_SP
     }
 }
 
 impl<'tcx> Key for Ty<'tcx> {
-    type Cache<V> = DefaultCache<Self, V>;
-
     fn default_span(&self, _: TyCtxt<'_>) -> Span {
         DUMMY_SP
     }
@@ -450,40 +378,30 @@ impl<'tcx> Key for Ty<'tcx> {
 }
 
 impl<'tcx> Key for TyAndLayout<'tcx> {
-    type Cache<V> = DefaultCache<Self, V>;
-
     fn default_span(&self, _: TyCtxt<'_>) -> Span {
         DUMMY_SP
     }
 }
 
 impl<'tcx> Key for (Ty<'tcx>, Ty<'tcx>) {
-    type Cache<V> = DefaultCache<Self, V>;
-
     fn default_span(&self, _: TyCtxt<'_>) -> Span {
         DUMMY_SP
     }
 }
 
 impl<'tcx> Key for ty::Clauses<'tcx> {
-    type Cache<V> = DefaultCache<Self, V>;
-
     fn default_span(&self, _: TyCtxt<'_>) -> Span {
         DUMMY_SP
     }
 }
 
 impl<'tcx> Key for ty::ParamEnv<'tcx> {
-    type Cache<V> = DefaultCache<Self, V>;
-
     fn default_span(&self, _: TyCtxt<'_>) -> Span {
         DUMMY_SP
     }
 }
 
 impl<'tcx, T: Key> Key for ty::PseudoCanonicalInput<'tcx, T> {
-    type Cache<V> = DefaultCache<Self, V>;
-
     fn default_span(&self, tcx: TyCtxt<'_>) -> Span {
         self.value.default_span(tcx)
     }
@@ -494,24 +412,18 @@ impl<'tcx, T: Key> Key for ty::PseudoCanonicalInput<'tcx, T> {
 }
 
 impl Key for Symbol {
-    type Cache<V> = DefaultCache<Self, V>;
-
     fn default_span(&self, _tcx: TyCtxt<'_>) -> Span {
         DUMMY_SP
     }
 }
 
 impl Key for Option<Symbol> {
-    type Cache<V> = DefaultCache<Self, V>;
-
     fn default_span(&self, _tcx: TyCtxt<'_>) -> Span {
         DUMMY_SP
     }
 }
 
 impl<'tcx> Key for &'tcx OsStr {
-    type Cache<V> = DefaultCache<Self, V>;
-
     fn default_span(&self, _tcx: TyCtxt<'_>) -> Span {
         DUMMY_SP
     }
@@ -520,80 +432,60 @@ impl<'tcx> Key for &'tcx OsStr {
 /// Canonical query goals correspond to abstract trait operations that
 /// are not tied to any crate in particular.
 impl<'tcx, T: Clone> Key for CanonicalQueryInput<'tcx, T> {
-    type Cache<V> = DefaultCache<Self, V>;
-
     fn default_span(&self, _tcx: TyCtxt<'_>) -> Span {
         DUMMY_SP
     }
 }
 
 impl<'tcx, T: Clone> Key for (CanonicalQueryInput<'tcx, T>, bool) {
-    type Cache<V> = DefaultCache<Self, V>;
-
     fn default_span(&self, _tcx: TyCtxt<'_>) -> Span {
         DUMMY_SP
     }
 }
 
 impl Key for (Symbol, u32, u32) {
-    type Cache<V> = DefaultCache<Self, V>;
-
     fn default_span(&self, _tcx: TyCtxt<'_>) -> Span {
         DUMMY_SP
     }
 }
 
 impl<'tcx> Key for (DefId, Ty<'tcx>, GenericArgsRef<'tcx>, ty::ParamEnv<'tcx>) {
-    type Cache<V> = DefaultCache<Self, V>;
-
     fn default_span(&self, _tcx: TyCtxt<'_>) -> Span {
         DUMMY_SP
     }
 }
 
 impl<'tcx> Key for (Ty<'tcx>, rustc_abi::VariantIdx) {
-    type Cache<V> = DefaultCache<Self, V>;
-
     fn default_span(&self, _tcx: TyCtxt<'_>) -> Span {
         DUMMY_SP
     }
 }
 
 impl<'tcx> Key for (ty::Predicate<'tcx>, traits::WellFormedLoc) {
-    type Cache<V> = DefaultCache<Self, V>;
-
     fn default_span(&self, _tcx: TyCtxt<'_>) -> Span {
         DUMMY_SP
     }
 }
 
 impl<'tcx> Key for (ty::PolyFnSig<'tcx>, &'tcx ty::List<Ty<'tcx>>) {
-    type Cache<V> = DefaultCache<Self, V>;
-
     fn default_span(&self, _: TyCtxt<'_>) -> Span {
         DUMMY_SP
     }
 }
 
 impl<'tcx> Key for (ty::Instance<'tcx>, &'tcx ty::List<Ty<'tcx>>) {
-    type Cache<V> = DefaultCache<Self, V>;
-
     fn default_span(&self, tcx: TyCtxt<'_>) -> Span {
         self.0.default_span(tcx)
     }
 }
 
 impl<'tcx> Key for ty::Value<'tcx> {
-    type Cache<V> = DefaultCache<Self, V>;
-
     fn default_span(&self, _: TyCtxt<'_>) -> Span {
         DUMMY_SP
     }
 }
 
 impl Key for HirId {
-    type Cache<V> = DefaultCache<Self, V>;
-
     fn default_span(&self, tcx: TyCtxt<'_>) -> Span {
         tcx.hir_span(*self)
     }
@@ -605,8 +497,6 @@ impl Key for HirId {
 }
 
 impl Key for (LocalDefId, HirId) {
-    type Cache<V> = DefaultCache<Self, V>;
-
     fn default_span(&self, tcx: TyCtxt<'_>) -> Span {
         tcx.hir_span(self.1)
     }
@@ -631,8 +521,6 @@ impl<'tcx> Key for (LocalExpnId, &'tcx TokenStream) {
 }
 
 impl<'tcx> Key for (ValidityRequirement, ty::PseudoCanonicalInput<'tcx, Ty<'tcx>>) {
-    type Cache<V> = DefaultCache<Self, V>;
-
     // Just forward to `Ty<'tcx>`
 
     fn default_span(&self, _: TyCtxt<'_>) -> Span {
@@ -648,8 +536,6 @@ impl<'tcx> Key for (ValidityRequirement, ty::PseudoCanonicalInput<'tcx, Ty<'tcx>
 }
 
 impl<'tcx> Key for (ty::Instance<'tcx>, CollectionMode) {
-    type Cache<V> = DefaultCache<Self, V>;
-
     fn default_span(&self, tcx: TyCtxt<'_>) -> Span {
         self.0.default_span(tcx)
     }

From aebcf78527c38199c48aea2939d6e5062ea85e9e Mon Sep 17 00:00:00 2001
From: Nicholas Nethercote <n.nethercote@gmail.com>
Date: Wed, 14 Jan 2026 14:12:59 +1100
Subject: [PATCH 51/97] Remove unused `Key`/`AsLocalKey` impls.

---
 compiler/rustc_middle/src/query/keys.rs | 166 +-----------------------
 1 file changed, 3 insertions(+), 163 deletions(-)

diff --git a/compiler/rustc_middle/src/query/keys.rs b/compiler/rustc_middle/src/query/keys.rs
index 4fa8ca7d85bd..cccb7d51bd3e 100644
--- a/compiler/rustc_middle/src/query/keys.rs
+++ b/compiler/rustc_middle/src/query/keys.rs
@@ -3,8 +3,8 @@
 use std::ffi::OsStr;
 
 use rustc_ast::tokenstream::TokenStream;
-use rustc_hir::def_id::{CrateNum, DefId, LOCAL_CRATE, LocalDefId, LocalModDefId, ModDefId};
-use rustc_hir::hir_id::{HirId, OwnerId};
+use rustc_hir::def_id::{CrateNum, DefId, LOCAL_CRATE, LocalDefId, LocalModDefId};
+use rustc_hir::hir_id::OwnerId;
 use rustc_query_system::dep_graph::DepNodeIndex;
 use rustc_query_system::query::{DefIdCache, DefaultCache, SingleCache, VecCache};
 use rustc_span::{DUMMY_SP, Ident, LocalExpnId, Span, Symbol};
@@ -12,7 +12,7 @@ use rustc_span::{DUMMY_SP, Ident, LocalExpnId, Span, Symbol};
 use crate::infer::canonical::CanonicalQueryInput;
 use crate::mir::mono::CollectionMode;
 use crate::ty::fast_reject::SimplifiedType;
-use crate::ty::layout::{TyAndLayout, ValidityRequirement};
+use crate::ty::layout::ValidityRequirement;
 use crate::ty::{self, GenericArg, GenericArgsRef, Ty, TyCtxt};
 use crate::{mir, traits};
 
@@ -69,15 +69,6 @@ impl<'tcx> Key for ty::InstanceKind<'tcx> {
     }
 }
 
-impl<'tcx> AsLocalKey for ty::InstanceKind<'tcx> {
-    type LocalKey = Self;
-
-    #[inline(always)]
-    fn as_local_key(&self) -> Option<Self::LocalKey> {
-        self.def_id().is_local().then(|| *self)
-    }
-}
-
 impl<'tcx> Key for ty::Instance<'tcx> {
     fn default_span(&self, tcx: TyCtxt<'_>) -> Span {
         tcx.def_span(self.def_id())
@@ -176,26 +167,6 @@ impl Key for LocalModDefId {
     }
 }
 
-impl Key for ModDefId {
-    fn default_span(&self, tcx: TyCtxt<'_>) -> Span {
-        tcx.def_span(*self)
-    }
-
-    #[inline(always)]
-    fn key_as_def_id(&self) -> Option<DefId> {
-        Some(self.to_def_id())
-    }
-}
-
-impl AsLocalKey for ModDefId {
-    type LocalKey = LocalModDefId;
-
-    #[inline(always)]
-    fn as_local_key(&self) -> Option<Self::LocalKey> {
-        self.as_local()
-    }
-}
-
 impl Key for SimplifiedType {
     fn default_span(&self, _: TyCtxt<'_>) -> Span {
         DUMMY_SP
@@ -208,30 +179,6 @@ impl Key for (DefId, DefId) {
     }
 }
 
-impl<'tcx> Key for (ty::Instance<'tcx>, LocalDefId) {
-    fn default_span(&self, tcx: TyCtxt<'_>) -> Span {
-        self.0.default_span(tcx)
-    }
-}
-
-impl Key for (DefId, LocalDefId) {
-    fn default_span(&self, tcx: TyCtxt<'_>) -> Span {
-        self.1.default_span(tcx)
-    }
-}
-
-impl Key for (LocalDefId, DefId) {
-    fn default_span(&self, tcx: TyCtxt<'_>) -> Span {
-        self.0.default_span(tcx)
-    }
-}
-
-impl Key for (LocalDefId, LocalDefId) {
-    fn default_span(&self, tcx: TyCtxt<'_>) -> Span {
-        self.0.default_span(tcx)
-    }
-}
-
 impl Key for (DefId, Ident) {
     fn default_span(&self, tcx: TyCtxt<'_>) -> Span {
         tcx.def_span(self.0)
@@ -279,12 +226,6 @@ impl AsLocalKey for (CrateNum, SimplifiedType) {
     }
 }
 
-impl Key for (DefId, SimplifiedType) {
-    fn default_span(&self, tcx: TyCtxt<'_>) -> Span {
-        self.0.default_span(tcx)
-    }
-}
-
 impl Key for (DefId, ty::SizedTraitKind) {
     fn default_span(&self, tcx: TyCtxt<'_>) -> Span {
         self.0.default_span(tcx)
@@ -303,66 +244,18 @@ impl<'tcx> Key for (DefId, GenericArgsRef<'tcx>) {
     }
 }
 
-impl<'tcx> Key for (ty::UnevaluatedConst<'tcx>, ty::UnevaluatedConst<'tcx>) {
-    fn default_span(&self, tcx: TyCtxt<'_>) -> Span {
-        (self.0).def.default_span(tcx)
-    }
-}
-
-impl<'tcx> Key for (LocalDefId, DefId, GenericArgsRef<'tcx>) {
-    fn default_span(&self, tcx: TyCtxt<'_>) -> Span {
-        self.0.default_span(tcx)
-    }
-}
-
-impl<'tcx> Key for (ty::ParamEnv<'tcx>, ty::TraitRef<'tcx>) {
-    fn default_span(&self, tcx: TyCtxt<'_>) -> Span {
-        tcx.def_span(self.1.def_id)
-    }
-}
-
-impl<'tcx> Key for ty::ParamEnvAnd<'tcx, Ty<'tcx>> {
-    fn default_span(&self, _tcx: TyCtxt<'_>) -> Span {
-        DUMMY_SP
-    }
-}
-
 impl<'tcx> Key for ty::TraitRef<'tcx> {
     fn default_span(&self, tcx: TyCtxt<'_>) -> Span {
         tcx.def_span(self.def_id)
     }
 }
 
-impl<'tcx> Key for ty::PolyTraitRef<'tcx> {
-    fn default_span(&self, tcx: TyCtxt<'_>) -> Span {
-        tcx.def_span(self.def_id())
-    }
-}
-
-impl<'tcx> Key for ty::PolyExistentialTraitRef<'tcx> {
-    fn default_span(&self, tcx: TyCtxt<'_>) -> Span {
-        tcx.def_span(self.def_id())
-    }
-}
-
-impl<'tcx> Key for (ty::PolyTraitRef<'tcx>, ty::PolyTraitRef<'tcx>) {
-    fn default_span(&self, tcx: TyCtxt<'_>) -> Span {
-        tcx.def_span(self.0.def_id())
-    }
-}
-
 impl<'tcx> Key for GenericArg<'tcx> {
     fn default_span(&self, _: TyCtxt<'_>) -> Span {
         DUMMY_SP
     }
 }
 
-impl<'tcx> Key for ty::Const<'tcx> {
-    fn default_span(&self, _: TyCtxt<'_>) -> Span {
-        DUMMY_SP
-    }
-}
-
 impl<'tcx> Key for Ty<'tcx> {
     fn default_span(&self, _: TyCtxt<'_>) -> Span {
         DUMMY_SP
@@ -377,12 +270,6 @@ impl<'tcx> Key for Ty<'tcx> {
     }
 }
 
-impl<'tcx> Key for TyAndLayout<'tcx> {
-    fn default_span(&self, _: TyCtxt<'_>) -> Span {
-        DUMMY_SP
-    }
-}
-
 impl<'tcx> Key for (Ty<'tcx>, Ty<'tcx>) {
     fn default_span(&self, _: TyCtxt<'_>) -> Span {
         DUMMY_SP
@@ -395,12 +282,6 @@ impl<'tcx> Key for ty::Clauses<'tcx> {
     }
 }
 
-impl<'tcx> Key for ty::ParamEnv<'tcx> {
-    fn default_span(&self, _: TyCtxt<'_>) -> Span {
-        DUMMY_SP
-    }
-}
-
 impl<'tcx, T: Key> Key for ty::PseudoCanonicalInput<'tcx, T> {
     fn default_span(&self, tcx: TyCtxt<'_>) -> Span {
         self.value.default_span(tcx)
@@ -443,18 +324,6 @@ impl<'tcx, T: Clone> Key for (CanonicalQueryInput<'tcx, T>, bool) {
     }
 }
 
-impl Key for (Symbol, u32, u32) {
-    fn default_span(&self, _tcx: TyCtxt<'_>) -> Span {
-        DUMMY_SP
-    }
-}
-
-impl<'tcx> Key for (DefId, Ty<'tcx>, GenericArgsRef<'tcx>, ty::ParamEnv<'tcx>) {
-    fn default_span(&self, _tcx: TyCtxt<'_>) -> Span {
-        DUMMY_SP
-    }
-}
-
 impl<'tcx> Key for (Ty<'tcx>, rustc_abi::VariantIdx) {
     fn default_span(&self, _tcx: TyCtxt<'_>) -> Span {
         DUMMY_SP
@@ -485,39 +354,10 @@ impl<'tcx> Key for ty::Value<'tcx> {
     }
 }
 
-impl Key for HirId {
-    fn default_span(&self, tcx: TyCtxt<'_>) -> Span {
-        tcx.hir_span(*self)
-    }
-
-    #[inline(always)]
-    fn key_as_def_id(&self) -> Option<DefId> {
-        None
-    }
-}
-
-impl Key for (LocalDefId, HirId) {
-    fn default_span(&self, tcx: TyCtxt<'_>) -> Span {
-        tcx.hir_span(self.1)
-    }
-
-    #[inline(always)]
-    fn key_as_def_id(&self) -> Option<DefId> {
-        Some(self.0.into())
-    }
-}
-
 impl<'tcx> Key for (LocalExpnId, &'tcx TokenStream) {
-    type Cache<V> = DefaultCache<Self, V>;
-
     fn default_span(&self, _tcx: TyCtxt<'_>) -> Span {
         self.0.expn_data().call_site
     }
-
-    #[inline(always)]
-    fn key_as_def_id(&self) -> Option<DefId> {
-        None
-    }
 }
 
 impl<'tcx> Key for (ValidityRequirement, ty::PseudoCanonicalInput<'tcx, Ty<'tcx>>) {

From 5e629be64827e048388b41bfd236572fd3081f84 Mon Sep 17 00:00:00 2001
From: Zalathar <Zalathar@users.noreply.github.com>
Date: Mon, 26 Jan 2026 22:21:21 +1100
Subject: [PATCH 52/97] Add `CompilerKind` to distinguish between rustc and
 rustdoc

---
 src/tools/compiletest/src/runtest.rs          | 64 +++++++++++++++----
 src/tools/compiletest/src/runtest/assembly.rs |  3 +-
 src/tools/compiletest/src/runtest/ui.rs       | 10 +--
 3 files changed, 59 insertions(+), 18 deletions(-)

diff --git a/src/tools/compiletest/src/runtest.rs b/src/tools/compiletest/src/runtest.rs
index 2bfb73f05d16..5686bfa8f614 100644
--- a/src/tools/compiletest/src/runtest.rs
+++ b/src/tools/compiletest/src/runtest.rs
@@ -255,6 +255,13 @@ enum Emit {
     LinkArgsAsm,
 }
 
+/// Indicates whether we are using `rustc` or `rustdoc` to compile an input file.
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+enum CompilerKind {
+    Rustc,
+    Rustdoc,
+}
+
 impl<'test> TestCx<'test> {
     /// Code executed for each revision in turn (or, if there are no
     /// revisions, exactly once, with revision == None).
@@ -958,6 +965,8 @@ impl<'test> TestCx<'test> {
         local_pm: Option<PassMode>,
         passes: Vec<String>,
     ) -> ProcRes {
+        let compiler_kind = self.compiler_kind_for_non_aux();
+
         // Only use `make_exe_name` when the test ends up being executed.
         let output_file = match will_execute {
             WillExecute::Yes => TargetLocation::ThisFile(self.make_exe_name()),
@@ -973,7 +982,7 @@ impl<'test> TestCx<'test> {
                 // want to actually assert warnings about all this code. Instead
                 // let's just ignore unused code warnings by defaults and tests
                 // can turn it back on if needed.
-                if !self.is_rustdoc()
+                if compiler_kind == CompilerKind::Rustc
                     // Note that we use the local pass mode here as we don't want
                     // to set unused to allow if we've overridden the pass mode
                     // via command line flags.
@@ -988,6 +997,7 @@ impl<'test> TestCx<'test> {
         };
 
         let rustc = self.make_compile_args(
+            compiler_kind,
             &self.testpaths.file,
             output_file,
             emit,
@@ -1347,6 +1357,7 @@ impl<'test> TestCx<'test> {
     fn build_minicore(&self) -> Utf8PathBuf {
         let output_file_path = self.output_base_dir().join("libminicore.rlib");
         let mut rustc = self.make_compile_args(
+            CompilerKind::Rustc,
             &self.config.minicore_path,
             TargetLocation::ThisFile(output_file_path.clone()),
             Emit::None,
@@ -1404,6 +1415,8 @@ impl<'test> TestCx<'test> {
         // Create the directory for the stdout/stderr files.
         create_dir_all(aux_cx.output_base_dir()).unwrap();
         let mut aux_rustc = aux_cx.make_compile_args(
+            // Always use `rustc` for aux crates, even in rustdoc tests.
+            CompilerKind::Rustc,
             &aux_path,
             aux_output,
             Emit::None,
@@ -1554,15 +1567,41 @@ impl<'test> TestCx<'test> {
         result
     }
 
-    fn is_rustdoc(&self) -> bool {
-        matches!(
-            self.config.suite,
-            TestSuite::RustdocUi | TestSuite::RustdocJs | TestSuite::RustdocJson
-        )
+    /// Choose a compiler kind (rustc or rustdoc) for compiling test files,
+    /// based on the test suite being tested.
+    fn compiler_kind_for_non_aux(&self) -> CompilerKind {
+        match self.config.suite {
+            TestSuite::RustdocJs | TestSuite::RustdocJson | TestSuite::RustdocUi => {
+                CompilerKind::Rustdoc
+            }
+
+            // Exhaustively match all other suites.
+            // Note that some suites never actually use this method, so the
+            // return value for those suites is not necessarily meaningful.
+            TestSuite::AssemblyLlvm
+            | TestSuite::BuildStd
+            | TestSuite::CodegenLlvm
+            | TestSuite::CodegenUnits
+            | TestSuite::Coverage
+            | TestSuite::CoverageRunRustdoc
+            | TestSuite::Crashes
+            | TestSuite::Debuginfo
+            | TestSuite::Incremental
+            | TestSuite::MirOpt
+            | TestSuite::Pretty
+            | TestSuite::RunMake
+            | TestSuite::RunMakeCargo
+            | TestSuite::RustdocGui
+            | TestSuite::RustdocHtml
+            | TestSuite::RustdocJsStd
+            | TestSuite::Ui
+            | TestSuite::UiFullDeps => CompilerKind::Rustc,
+        }
     }
 
     fn make_compile_args(
         &self,
+        compiler_kind: CompilerKind,
         input_file: &Utf8Path,
         output_file: TargetLocation,
         emit: Emit,
@@ -1570,12 +1609,12 @@ impl<'test> TestCx<'test> {
         link_to_aux: LinkToAux,
         passes: Vec<String>, // Vec of passes under mir-opt test to be dumped
     ) -> Command {
-        let is_aux = input_file.components().map(|c| c.as_os_str()).any(|c| c == "auxiliary");
-        let is_rustdoc = self.is_rustdoc() && !is_aux;
-        let mut rustc = if !is_rustdoc {
-            Command::new(&self.config.rustc_path)
-        } else {
-            Command::new(&self.config.rustdoc_path.clone().expect("no rustdoc built yet"))
+        let is_rustdoc = compiler_kind == CompilerKind::Rustdoc;
+        let mut rustc = match compiler_kind {
+            CompilerKind::Rustc => Command::new(&self.config.rustc_path),
+            CompilerKind::Rustdoc => {
+                Command::new(&self.config.rustdoc_path.clone().expect("no rustdoc built yet"))
+            }
         };
         rustc.arg(input_file);
 
@@ -2127,6 +2166,7 @@ impl<'test> TestCx<'test> {
         let output_path = self.output_base_name().with_extension("ll");
         let input_file = &self.testpaths.file;
         let rustc = self.make_compile_args(
+            CompilerKind::Rustc,
             input_file,
             TargetLocation::ThisFile(output_path.clone()),
             Emit::LlvmIr,
diff --git a/src/tools/compiletest/src/runtest/assembly.rs b/src/tools/compiletest/src/runtest/assembly.rs
index c805b4c7a59e..18027328abfe 100644
--- a/src/tools/compiletest/src/runtest/assembly.rs
+++ b/src/tools/compiletest/src/runtest/assembly.rs
@@ -1,6 +1,6 @@
 use camino::Utf8PathBuf;
 
-use super::{AllowUnused, Emit, LinkToAux, ProcRes, TargetLocation, TestCx};
+use crate::runtest::{AllowUnused, CompilerKind, Emit, LinkToAux, ProcRes, TargetLocation, TestCx};
 
 impl TestCx<'_> {
     pub(super) fn run_assembly_test(&self) {
@@ -35,6 +35,7 @@ impl TestCx<'_> {
         };
 
         let rustc = self.make_compile_args(
+            CompilerKind::Rustc,
             input_file,
             TargetLocation::ThisFile(output_path.clone()),
             emit,
diff --git a/src/tools/compiletest/src/runtest/ui.rs b/src/tools/compiletest/src/runtest/ui.rs
index 9147471c5bbc..31b80d0924da 100644
--- a/src/tools/compiletest/src/runtest/ui.rs
+++ b/src/tools/compiletest/src/runtest/ui.rs
@@ -5,12 +5,11 @@ use std::io::Write;
 use rustfix::{Filter, apply_suggestions, get_suggestions_from_json};
 use tracing::debug;
 
-use super::{
-    AllowUnused, Emit, FailMode, LinkToAux, PassMode, RunFailMode, RunResult, TargetLocation,
-    TestCx, TestOutput, Truncated, UI_FIXED, WillExecute,
-};
 use crate::json;
-use crate::runtest::ProcRes;
+use crate::runtest::{
+    AllowUnused, Emit, FailMode, LinkToAux, PassMode, ProcRes, RunFailMode, RunResult,
+    TargetLocation, TestCx, TestOutput, Truncated, UI_FIXED, WillExecute,
+};
 
 impl TestCx<'_> {
     pub(super) fn run_ui_test(&self) {
@@ -228,6 +227,7 @@ impl TestCx<'_> {
             // And finally, compile the fixed code and make sure it both
             // succeeds and has no diagnostics.
             let mut rustc = self.make_compile_args(
+                self.compiler_kind_for_non_aux(),
                 &self.expected_output_path(UI_FIXED),
                 TargetLocation::ThisFile(self.make_exe_name()),
                 emit_metadata,

From 0b42f38dc72e6479ea59d64d997475fa09555d74 Mon Sep 17 00:00:00 2001
From: Zalathar <Zalathar@users.noreply.github.com>
Date: Mon, 26 Jan 2026 22:41:57 +1100
Subject: [PATCH 53/97] Replace `is_rustdoc` with clearer compiler-kind checks

---
 src/tools/compiletest/src/runtest.rs | 69 +++++++++++++++-------------
 1 file changed, 36 insertions(+), 33 deletions(-)

diff --git a/src/tools/compiletest/src/runtest.rs b/src/tools/compiletest/src/runtest.rs
index 5686bfa8f614..5fcc97fbf537 100644
--- a/src/tools/compiletest/src/runtest.rs
+++ b/src/tools/compiletest/src/runtest.rs
@@ -1609,7 +1609,8 @@ impl<'test> TestCx<'test> {
         link_to_aux: LinkToAux,
         passes: Vec<String>, // Vec of passes under mir-opt test to be dumped
     ) -> Command {
-        let is_rustdoc = compiler_kind == CompilerKind::Rustdoc;
+        // FIXME(Zalathar): We should have a cleaner distinction between
+        // `rustc` flags, `rustdoc` flags, and flags shared by both.
         let mut rustc = match compiler_kind {
             CompilerKind::Rustc => Command::new(&self.config.rustc_path),
             CompilerKind::Rustdoc => {
@@ -1672,7 +1673,7 @@ impl<'test> TestCx<'test> {
         }
         self.set_revision_flags(&mut rustc);
 
-        if !is_rustdoc {
+        if compiler_kind == CompilerKind::Rustc {
             if let Some(ref incremental_dir) = self.props.incremental_dir {
                 rustc.args(&["-C", &format!("incremental={}", incremental_dir)]);
                 rustc.args(&["-Z", "incremental-verify-ich"]);
@@ -1683,7 +1684,7 @@ impl<'test> TestCx<'test> {
             }
         }
 
-        if self.config.optimize_tests && !is_rustdoc {
+        if self.config.optimize_tests && compiler_kind == CompilerKind::Rustc {
             match self.config.mode {
                 TestMode::Ui => {
                     // If optimize-tests is true we still only want to optimize tests that actually get
@@ -1825,27 +1826,28 @@ impl<'test> TestCx<'test> {
             ));
         }
 
-        match emit {
-            Emit::None => {}
-            Emit::Metadata if is_rustdoc => {}
-            Emit::Metadata => {
-                rustc.args(&["--emit", "metadata"]);
-            }
-            Emit::LlvmIr => {
-                rustc.args(&["--emit", "llvm-ir"]);
-            }
-            Emit::Mir => {
-                rustc.args(&["--emit", "mir"]);
-            }
-            Emit::Asm => {
-                rustc.args(&["--emit", "asm"]);
-            }
-            Emit::LinkArgsAsm => {
-                rustc.args(&["-Clink-args=--emit=asm"]);
+        if compiler_kind == CompilerKind::Rustc {
+            match emit {
+                Emit::None => {}
+                Emit::Metadata => {
+                    rustc.args(&["--emit", "metadata"]);
+                }
+                Emit::LlvmIr => {
+                    rustc.args(&["--emit", "llvm-ir"]);
+                }
+                Emit::Mir => {
+                    rustc.args(&["--emit", "mir"]);
+                }
+                Emit::Asm => {
+                    rustc.args(&["--emit", "asm"]);
+                }
+                Emit::LinkArgsAsm => {
+                    rustc.args(&["-Clink-args=--emit=asm"]);
+                }
             }
         }
 
-        if !is_rustdoc {
+        if compiler_kind == CompilerKind::Rustc {
             if self.config.target == "wasm32-unknown-unknown" || self.is_vxworks_pure_static() {
                 // rustc.arg("-g"); // get any backtrace at all on errors
             } else if !self.props.no_prefer_dynamic {
@@ -1860,14 +1862,15 @@ impl<'test> TestCx<'test> {
             TargetLocation::ThisFile(path) => {
                 rustc.arg("-o").arg(path);
             }
-            TargetLocation::ThisDirectory(path) => {
-                if is_rustdoc {
+            TargetLocation::ThisDirectory(path) => match compiler_kind {
+                CompilerKind::Rustdoc => {
                     // `rustdoc` uses `-o` for the output directory.
                     rustc.arg("-o").arg(path);
-                } else {
+                }
+                CompilerKind::Rustc => {
                     rustc.arg("--out-dir").arg(path);
                 }
-            }
+            },
         }
 
         match self.config.compare_mode {
@@ -1910,17 +1913,17 @@ impl<'test> TestCx<'test> {
 
         if self.props.force_host {
             self.maybe_add_external_args(&mut rustc, &self.config.host_rustcflags);
-            if !is_rustdoc {
-                if let Some(ref linker) = self.config.host_linker {
-                    rustc.arg(format!("-Clinker={}", linker));
-                }
+            if compiler_kind == CompilerKind::Rustc
+                && let Some(ref linker) = self.config.host_linker
+            {
+                rustc.arg(format!("-Clinker={linker}"));
             }
         } else {
             self.maybe_add_external_args(&mut rustc, &self.config.target_rustcflags);
-            if !is_rustdoc {
-                if let Some(ref linker) = self.config.target_linker {
-                    rustc.arg(format!("-Clinker={}", linker));
-                }
+            if compiler_kind == CompilerKind::Rustc
+                && let Some(ref linker) = self.config.target_linker
+            {
+                rustc.arg(format!("-Clinker={linker}"));
             }
         }
 

From 40d4d322b80c59acc60aa647a27334d1231a5646 Mon Sep 17 00:00:00 2001
From: Zalathar <Zalathar@users.noreply.github.com>
Date: Tue, 27 Jan 2026 16:23:50 +1100
Subject: [PATCH 54/97] Rename `rustc` command variable to `compiler`

---
 src/tools/compiletest/src/runtest.rs | 141 ++++++++++++++-------------
 1 file changed, 71 insertions(+), 70 deletions(-)

diff --git a/src/tools/compiletest/src/runtest.rs b/src/tools/compiletest/src/runtest.rs
index 5fcc97fbf537..e6eb1f3bd957 100644
--- a/src/tools/compiletest/src/runtest.rs
+++ b/src/tools/compiletest/src/runtest.rs
@@ -1611,16 +1611,16 @@ impl<'test> TestCx<'test> {
     ) -> Command {
         // FIXME(Zalathar): We should have a cleaner distinction between
         // `rustc` flags, `rustdoc` flags, and flags shared by both.
-        let mut rustc = match compiler_kind {
+        let mut compiler = match compiler_kind {
             CompilerKind::Rustc => Command::new(&self.config.rustc_path),
             CompilerKind::Rustdoc => {
                 Command::new(&self.config.rustdoc_path.clone().expect("no rustdoc built yet"))
             }
         };
-        rustc.arg(input_file);
+        compiler.arg(input_file);
 
         // Use a single thread for efficiency and a deterministic error message order
-        rustc.arg("-Zthreads=1");
+        compiler.arg("-Zthreads=1");
 
         // Hide libstd sources from ui tests to make sure we generate the stderr
         // output that users will see.
@@ -1630,19 +1630,19 @@ impl<'test> TestCx<'test> {
         // This also has the benefit of more effectively normalizing output between different
         // compilers, so that we don't have to know the `/rustc/$sha` output to normalize after the
         // fact.
-        rustc.arg("-Zsimulate-remapped-rust-src-base=/rustc/FAKE_PREFIX");
-        rustc.arg("-Ztranslate-remapped-path-to-local-path=no");
+        compiler.arg("-Zsimulate-remapped-rust-src-base=/rustc/FAKE_PREFIX");
+        compiler.arg("-Ztranslate-remapped-path-to-local-path=no");
 
         // Hide Cargo dependency sources from ui tests to make sure the error message doesn't
         // change depending on whether $CARGO_HOME is remapped or not. If this is not present,
         // when $CARGO_HOME is remapped the source won't be shown, and when it's not remapped the
         // source will be shown, causing a blessing hell.
-        rustc.arg("-Z").arg(format!(
+        compiler.arg("-Z").arg(format!(
             "ignore-directory-in-diagnostics-source-blocks={}",
             home::cargo_home().expect("failed to find cargo home").to_str().unwrap()
         ));
         // Similarly, vendored sources shouldn't be shown when running from a dist tarball.
-        rustc.arg("-Z").arg(format!(
+        compiler.arg("-Z").arg(format!(
             "ignore-directory-in-diagnostics-source-blocks={}",
             self.config.src_root.join("vendor"),
         ));
@@ -1654,12 +1654,12 @@ impl<'test> TestCx<'test> {
             && !self.config.host_rustcflags.iter().any(|flag| flag == "--sysroot")
         {
             // In stage 0, make sure we use `stage0-sysroot` instead of the bootstrap sysroot.
-            rustc.arg("--sysroot").arg(&self.config.sysroot_base);
+            compiler.arg("--sysroot").arg(&self.config.sysroot_base);
         }
 
         // If the provided codegen backend is not LLVM, we need to pass it.
         if let Some(ref backend) = self.config.override_codegen_backend {
-            rustc.arg(format!("-Zcodegen-backend={}", backend));
+            compiler.arg(format!("-Zcodegen-backend={}", backend));
         }
 
         // Optionally prevent default --target if specified in test compile-flags.
@@ -1669,18 +1669,18 @@ impl<'test> TestCx<'test> {
             let target =
                 if self.props.force_host { &*self.config.host } else { &*self.config.target };
 
-            rustc.arg(&format!("--target={}", target));
+            compiler.arg(&format!("--target={}", target));
         }
-        self.set_revision_flags(&mut rustc);
+        self.set_revision_flags(&mut compiler);
 
         if compiler_kind == CompilerKind::Rustc {
             if let Some(ref incremental_dir) = self.props.incremental_dir {
-                rustc.args(&["-C", &format!("incremental={}", incremental_dir)]);
-                rustc.args(&["-Z", "incremental-verify-ich"]);
+                compiler.args(&["-C", &format!("incremental={}", incremental_dir)]);
+                compiler.args(&["-Z", "incremental-verify-ich"]);
             }
 
             if self.config.mode == TestMode::CodegenUnits {
-                rustc.args(&["-Z", "human_readable_cgu_names"]);
+                compiler.args(&["-Z", "human_readable_cgu_names"]);
             }
         }
 
@@ -1698,7 +1698,7 @@ impl<'test> TestCx<'test> {
                             .iter()
                             .any(|arg| arg == "-O" || arg.contains("opt-level"))
                     {
-                        rustc.arg("-O");
+                        compiler.arg("-O");
                     }
                 }
                 TestMode::DebugInfo => { /* debuginfo tests must be unoptimized */ }
@@ -1709,7 +1709,7 @@ impl<'test> TestCx<'test> {
                     // compile flags (below) or in per-test `compile-flags`.
                 }
                 _ => {
-                    rustc.arg("-O");
+                    compiler.arg("-O");
                 }
             }
         }
@@ -1730,24 +1730,24 @@ impl<'test> TestCx<'test> {
                 if self.props.error_patterns.is_empty()
                     && self.props.regex_error_patterns.is_empty()
                 {
-                    rustc.args(&["--error-format", "json"]);
-                    rustc.args(&["--json", "future-incompat"]);
+                    compiler.args(&["--error-format", "json"]);
+                    compiler.args(&["--json", "future-incompat"]);
                 }
-                rustc.arg("-Zui-testing");
-                rustc.arg("-Zdeduplicate-diagnostics=no");
+                compiler.arg("-Zui-testing");
+                compiler.arg("-Zdeduplicate-diagnostics=no");
             }
             TestMode::Ui => {
                 if !self.props.compile_flags.iter().any(|s| s.starts_with("--error-format")) {
-                    rustc.args(&["--error-format", "json"]);
-                    rustc.args(&["--json", "future-incompat"]);
+                    compiler.args(&["--error-format", "json"]);
+                    compiler.args(&["--json", "future-incompat"]);
                 }
-                rustc.arg("-Ccodegen-units=1");
+                compiler.arg("-Ccodegen-units=1");
                 // Hide line numbers to reduce churn
-                rustc.arg("-Zui-testing");
-                rustc.arg("-Zdeduplicate-diagnostics=no");
-                rustc.arg("-Zwrite-long-types-to-disk=no");
+                compiler.arg("-Zui-testing");
+                compiler.arg("-Zdeduplicate-diagnostics=no");
+                compiler.arg("-Zwrite-long-types-to-disk=no");
                 // FIXME: use this for other modes too, for perf?
-                rustc.arg("-Cstrip=debuginfo");
+                compiler.arg("-Cstrip=debuginfo");
             }
             TestMode::MirOpt => {
                 // We check passes under test to minimize the mir-opt test dump
@@ -1759,7 +1759,7 @@ impl<'test> TestCx<'test> {
                     "-Zdump-mir=all".to_string()
                 };
 
-                rustc.args(&[
+                compiler.args(&[
                     "-Copt-level=1",
                     &zdump_arg,
                     "-Zvalidate-mir",
@@ -1769,45 +1769,46 @@ impl<'test> TestCx<'test> {
                     "--crate-type=rlib",
                 ]);
                 if let Some(pass) = &self.props.mir_unit_test {
-                    rustc.args(&["-Zmir-opt-level=0", &format!("-Zmir-enable-passes=+{}", pass)]);
+                    compiler
+                        .args(&["-Zmir-opt-level=0", &format!("-Zmir-enable-passes=+{}", pass)]);
                 } else {
-                    rustc.args(&[
+                    compiler.args(&[
                         "-Zmir-opt-level=4",
                         "-Zmir-enable-passes=+ReorderBasicBlocks,+ReorderLocals",
                     ]);
                 }
 
-                set_mir_dump_dir(&mut rustc);
+                set_mir_dump_dir(&mut compiler);
             }
             TestMode::CoverageMap => {
-                rustc.arg("-Cinstrument-coverage");
+                compiler.arg("-Cinstrument-coverage");
                 // These tests only compile to LLVM IR, so they don't need the
                 // profiler runtime to be present.
-                rustc.arg("-Zno-profiler-runtime");
+                compiler.arg("-Zno-profiler-runtime");
                 // Coverage mappings are sensitive to MIR optimizations, and
                 // the current snapshots assume `opt-level=2` unless overridden
                 // by `compile-flags`.
-                rustc.arg("-Copt-level=2");
+                compiler.arg("-Copt-level=2");
             }
             TestMode::CoverageRun => {
-                rustc.arg("-Cinstrument-coverage");
+                compiler.arg("-Cinstrument-coverage");
                 // Coverage reports are sometimes sensitive to optimizations,
                 // and the current snapshots assume `opt-level=2` unless
                 // overridden by `compile-flags`.
-                rustc.arg("-Copt-level=2");
+                compiler.arg("-Copt-level=2");
             }
             TestMode::Assembly | TestMode::Codegen => {
-                rustc.arg("-Cdebug-assertions=no");
+                compiler.arg("-Cdebug-assertions=no");
                 // For assembly and codegen tests, we want to use the same order
                 // of the items of a codegen unit as the source order, so that
                 // we can compare the output with the source code through filecheck.
-                rustc.arg("-Zcodegen-source-order");
+                compiler.arg("-Zcodegen-source-order");
             }
             TestMode::Crashes => {
-                set_mir_dump_dir(&mut rustc);
+                set_mir_dump_dir(&mut compiler);
             }
             TestMode::CodegenUnits => {
-                rustc.arg("-Zprint-mono-items");
+                compiler.arg("-Zprint-mono-items");
             }
             TestMode::Pretty
             | TestMode::DebugInfo
@@ -1820,7 +1821,7 @@ impl<'test> TestCx<'test> {
         }
 
         if self.props.remap_src_base {
-            rustc.arg(format!(
+            compiler.arg(format!(
                 "--remap-path-prefix={}={}",
                 self.config.src_test_suite_root, FAKE_SRC_BASE,
             ));
@@ -1830,19 +1831,19 @@ impl<'test> TestCx<'test> {
             match emit {
                 Emit::None => {}
                 Emit::Metadata => {
-                    rustc.args(&["--emit", "metadata"]);
+                    compiler.args(&["--emit", "metadata"]);
                 }
                 Emit::LlvmIr => {
-                    rustc.args(&["--emit", "llvm-ir"]);
+                    compiler.args(&["--emit", "llvm-ir"]);
                 }
                 Emit::Mir => {
-                    rustc.args(&["--emit", "mir"]);
+                    compiler.args(&["--emit", "mir"]);
                 }
                 Emit::Asm => {
-                    rustc.args(&["--emit", "asm"]);
+                    compiler.args(&["--emit", "asm"]);
                 }
                 Emit::LinkArgsAsm => {
-                    rustc.args(&["-Clink-args=--emit=asm"]);
+                    compiler.args(&["-Clink-args=--emit=asm"]);
                 }
             }
         }
@@ -1851,7 +1852,7 @@ impl<'test> TestCx<'test> {
             if self.config.target == "wasm32-unknown-unknown" || self.is_vxworks_pure_static() {
                 // rustc.arg("-g"); // get any backtrace at all on errors
             } else if !self.props.no_prefer_dynamic {
-                rustc.args(&["-C", "prefer-dynamic"]);
+                compiler.args(&["-C", "prefer-dynamic"]);
             }
         }
 
@@ -1860,37 +1861,37 @@ impl<'test> TestCx<'test> {
             // avoid a compiler warning about `--out-dir` being ignored.
             _ if self.props.compile_flags.iter().any(|flag| flag == "-o") => {}
             TargetLocation::ThisFile(path) => {
-                rustc.arg("-o").arg(path);
+                compiler.arg("-o").arg(path);
             }
             TargetLocation::ThisDirectory(path) => match compiler_kind {
                 CompilerKind::Rustdoc => {
                     // `rustdoc` uses `-o` for the output directory.
-                    rustc.arg("-o").arg(path);
+                    compiler.arg("-o").arg(path);
                 }
                 CompilerKind::Rustc => {
-                    rustc.arg("--out-dir").arg(path);
+                    compiler.arg("--out-dir").arg(path);
                 }
             },
         }
 
         match self.config.compare_mode {
             Some(CompareMode::Polonius) => {
-                rustc.args(&["-Zpolonius=next"]);
+                compiler.args(&["-Zpolonius=next"]);
             }
             Some(CompareMode::NextSolver) => {
-                rustc.args(&["-Znext-solver"]);
+                compiler.args(&["-Znext-solver"]);
             }
             Some(CompareMode::NextSolverCoherence) => {
-                rustc.args(&["-Znext-solver=coherence"]);
+                compiler.args(&["-Znext-solver=coherence"]);
             }
             Some(CompareMode::SplitDwarf) if self.config.target.contains("windows") => {
-                rustc.args(&["-Csplit-debuginfo=unpacked", "-Zunstable-options"]);
+                compiler.args(&["-Csplit-debuginfo=unpacked", "-Zunstable-options"]);
             }
             Some(CompareMode::SplitDwarf) => {
-                rustc.args(&["-Csplit-debuginfo=unpacked"]);
+                compiler.args(&["-Csplit-debuginfo=unpacked"]);
             }
             Some(CompareMode::SplitDwarfSingle) => {
-                rustc.args(&["-Csplit-debuginfo=packed"]);
+                compiler.args(&["-Csplit-debuginfo=packed"]);
             }
             None => {}
         }
@@ -1899,44 +1900,44 @@ impl<'test> TestCx<'test> {
         // overwrite this.
         // Don't allow `unused_attributes` since these are usually actual mistakes, rather than just unused code.
         if let AllowUnused::Yes = allow_unused {
-            rustc.args(&["-A", "unused", "-W", "unused_attributes"]);
+            compiler.args(&["-A", "unused", "-W", "unused_attributes"]);
         }
 
         // Allow tests to use internal features.
-        rustc.args(&["-A", "internal_features"]);
+        compiler.args(&["-A", "internal_features"]);
 
         // Allow tests to have unused parens and braces.
         // Add #![deny(unused_parens, unused_braces)] to the test file if you want to
         // test that these lints are working.
-        rustc.args(&["-A", "unused_parens"]);
-        rustc.args(&["-A", "unused_braces"]);
+        compiler.args(&["-A", "unused_parens"]);
+        compiler.args(&["-A", "unused_braces"]);
 
         if self.props.force_host {
-            self.maybe_add_external_args(&mut rustc, &self.config.host_rustcflags);
+            self.maybe_add_external_args(&mut compiler, &self.config.host_rustcflags);
             if compiler_kind == CompilerKind::Rustc
                 && let Some(ref linker) = self.config.host_linker
             {
-                rustc.arg(format!("-Clinker={linker}"));
+                compiler.arg(format!("-Clinker={linker}"));
             }
         } else {
-            self.maybe_add_external_args(&mut rustc, &self.config.target_rustcflags);
+            self.maybe_add_external_args(&mut compiler, &self.config.target_rustcflags);
             if compiler_kind == CompilerKind::Rustc
                 && let Some(ref linker) = self.config.target_linker
             {
-                rustc.arg(format!("-Clinker={linker}"));
+                compiler.arg(format!("-Clinker={linker}"));
             }
         }
 
         // Use dynamic musl for tests because static doesn't allow creating dylibs
         if self.config.host.contains("musl") || self.is_vxworks_pure_dynamic() {
-            rustc.arg("-Ctarget-feature=-crt-static");
+            compiler.arg("-Ctarget-feature=-crt-static");
         }
 
         if let LinkToAux::Yes = link_to_aux {
             // if we pass an `-L` argument to a directory that doesn't exist,
             // macOS ld emits warnings which disrupt the .stderr files
             if self.has_aux_dir() {
-                rustc.arg("-L").arg(self.aux_output_dir_name());
+                compiler.arg("-L").arg(self.aux_output_dir_name());
             }
         }
 
@@ -1950,13 +1951,13 @@ impl<'test> TestCx<'test> {
         //
         // `minicore` requires `#![no_std]` and `#![no_core]`, which means no unwinding panics.
         if self.props.add_minicore {
-            rustc.arg("-Cpanic=abort");
-            rustc.arg("-Cforce-unwind-tables=yes");
+            compiler.arg("-Cpanic=abort");
+            compiler.arg("-Cforce-unwind-tables=yes");
         }
 
-        rustc.args(&self.props.compile_flags);
+        compiler.args(&self.props.compile_flags);
 
-        rustc
+        compiler
     }
 
     fn make_exe_name(&self) -> Utf8PathBuf {

From 51de309db24a8fd25df589987bb6e37d3253c214 Mon Sep 17 00:00:00 2001
From: Scott McMurray <scottmcm@users.noreply.github.com>
Date: Tue, 27 Jan 2026 00:10:12 -0800
Subject: [PATCH 55/97] Tweak `SlicePartialEq` to allow MIR-inlining the
 `compare_bytes` call

150265 disabled this because it was a net perf win, but let's see if we can tweak the structure of this to allow more inlining on this side while still not MIR-inlining the loop when it's not just `memcmp`.

This should also allow MIR-inlining the length check, which was previously blocked.
---
 library/core/src/slice/cmp.rs                 |  56 ++--
 ..._conditions.JumpThreading.panic-abort.diff | 290 +++++++++++++-----
 ...conditions.JumpThreading.panic-unwind.diff | 290 +++++++++++++-----
 3 files changed, 455 insertions(+), 181 deletions(-)

diff --git a/library/core/src/slice/cmp.rs b/library/core/src/slice/cmp.rs
index c3ff928a3277..2390ca74a8e0 100644
--- a/library/core/src/slice/cmp.rs
+++ b/library/core/src/slice/cmp.rs
@@ -4,6 +4,7 @@ use super::{from_raw_parts, memchr};
 use crate::ascii;
 use crate::cmp::{self, BytewiseEq, Ordering};
 use crate::intrinsics::compare_bytes;
+use crate::mem::SizedTypeProperties;
 use crate::num::NonZero;
 use crate::ops::ControlFlow;
 
@@ -15,7 +16,14 @@ where
 {
     #[inline]
     fn eq(&self, other: &[U]) -> bool {
-        SlicePartialEq::equal(self, other)
+        let len = self.len();
+        if len == other.len() {
+            // SAFETY: Just checked that they're the same length, and the pointers
+            // come from references-to-slices so they're guaranteed readable.
+            unsafe { SlicePartialEq::equal_same_length(self.as_ptr(), other.as_ptr(), len) }
+        } else {
+            false
+        }
     }
 }
 
@@ -95,12 +103,14 @@ impl<T: PartialOrd> PartialOrd for [T] {
 // intermediate trait for specialization of slice's PartialEq
 #[rustc_const_unstable(feature = "const_cmp", issue = "143800")]
 const trait SlicePartialEq<B> {
-    fn equal(&self, other: &[B]) -> bool;
+    /// # Safety
+    /// `lhs` and `rhs` are both readable for `len` elements
+    unsafe fn equal_same_length(lhs: *const Self, rhs: *const B, len: usize) -> bool;
 }
 
 // Generic slice equality
 #[rustc_const_unstable(feature = "const_cmp", issue = "143800")]
-impl<A, B> const SlicePartialEq<B> for [A]
+impl<A, B> const SlicePartialEq<B> for A
 where
     A: [const] PartialEq<B>,
 {
@@ -109,19 +119,15 @@ where
     // such as in `<str as PartialEq>::eq`.
     // The codegen backend can still inline it later if needed.
     #[rustc_no_mir_inline]
-    default fn equal(&self, other: &[B]) -> bool {
-        if self.len() != other.len() {
-            return false;
-        }
-
+    default unsafe fn equal_same_length(lhs: *const Self, rhs: *const B, len: usize) -> bool {
         // Implemented as explicit indexing rather
         // than zipped iterators for performance reasons.
         // See PR https://github.com/rust-lang/rust/pull/116846
-        // FIXME(const_hack): make this a `for idx in 0..self.len()` loop.
+        // FIXME(const_hack): make this a `for idx in 0..len` loop.
         let mut idx = 0;
-        while idx < self.len() {
-            // bound checks are optimized away
-            if self[idx] != other[idx] {
+        while idx < len {
+            // SAFETY: idx < len, so both are in-bounds and readable
+            if unsafe { *lhs.add(idx) != *rhs.add(idx) } {
                 return false;
             }
             idx += 1;
@@ -134,30 +140,18 @@ where
 // When each element can be compared byte-wise, we can compare all the bytes
 // from the whole size in one call to the intrinsics.
 #[rustc_const_unstable(feature = "const_cmp", issue = "143800")]
-impl<A, B> const SlicePartialEq<B> for [A]
+impl<A, B> const SlicePartialEq<B> for A
 where
     A: [const] BytewiseEq<B>,
 {
-    // This is usually a pretty good backend inlining candidate because the
-    // intrinsic tends to just be `memcmp`.  However, as of 2025-12 letting
-    // MIR inline this makes reuse worse because it means that, for example,
-    // `String::eq` doesn't inline, whereas by keeping this from inling all
-    // the wrappers until the call to this disappear.  If the heuristics have
-    // changed and this is no longer fruitful, though, please do remove it.
-    // In the mean time, it's fine to not inline it in MIR because the backend
-    // will still inline it if it things it's important to do so.
-    #[rustc_no_mir_inline]
     #[inline]
-    fn equal(&self, other: &[B]) -> bool {
-        if self.len() != other.len() {
-            return false;
-        }
-
-        // SAFETY: `self` and `other` are references and are thus guaranteed to be valid.
-        // The two slices have been checked to have the same size above.
+    unsafe fn equal_same_length(lhs: *const Self, rhs: *const B, len: usize) -> bool {
+        // SAFETY: by our precondition, `lhs` and `rhs` are guaranteed to be valid
+        // for reading `len` values, which also means the size is guaranteed
+        // not to overflow because it exists in memory;
         unsafe {
-            let size = size_of_val(self);
-            compare_bytes(self.as_ptr() as *const u8, other.as_ptr() as *const u8, size) == 0
+            let size = crate::intrinsics::unchecked_mul(len, Self::SIZE);
+            compare_bytes(lhs as _, rhs as _, size) == 0
         }
     }
 }
diff --git a/tests/mir-opt/jump_threading.chained_conditions.JumpThreading.panic-abort.diff b/tests/mir-opt/jump_threading.chained_conditions.JumpThreading.panic-abort.diff
index 6c9cf0cf623b..a0aeb0a30f41 100644
--- a/tests/mir-opt/jump_threading.chained_conditions.JumpThreading.panic-abort.diff
+++ b/tests/mir-opt/jump_threading.chained_conditions.JumpThreading.panic-abort.diff
@@ -93,64 +93,100 @@
                   }
                   scope 25 (inlined std::cmp::impls::<impl PartialEq for &[u8]>::eq) {
                       scope 26 (inlined core::slice::cmp::<impl PartialEq for [u8]>::eq) {
+                          let _39: usize;
+                          let mut _40: bool;
+                          let mut _41: usize;
+                          let mut _42: *const u8;
+                          let mut _43: *const u8;
+                          scope 27 {
+                              scope 28 (inlined core::slice::<impl [u8]>::as_ptr) {
+                                  let mut _44: *const [u8];
+                              }
+                              scope 29 (inlined core::slice::<impl [u8]>::as_ptr) {
+                                  let mut _45: *const [u8];
+                              }
+                              scope 30 (inlined <u8 as core::slice::cmp::SlicePartialEq<u8>>::equal_same_length) {
+                                  let mut _46: i32;
+                                  scope 31 {
+                                  }
+                              }
+                          }
                       }
                   }
               }
           }
       }
-      scope 27 (inlined std::cmp::impls::<impl PartialEq<&str> for &String>::eq) {
-          let mut _39: &std::string::String;
-          let mut _40: &str;
-          scope 28 (inlined <String as PartialEq<str>>::eq) {
-              scope 29 (inlined #[track_caller] <String as Index<RangeFull>>::index) {
-                  let _41: &str;
-                  scope 30 (inlined String::as_str) {
-                      let _42: &[u8];
-                      scope 31 (inlined Vec::<u8>::as_slice) {
-                          let _43: *const [u8];
-                          let mut _44: *const u8;
-                          let mut _45: usize;
-                          scope 32 (inlined Vec::<u8>::as_ptr) {
-                              scope 33 (inlined alloc::raw_vec::RawVec::<u8>::ptr) {
-                                  scope 34 (inlined alloc::raw_vec::RawVecInner::ptr::<u8>) {
-                                      scope 35 (inlined alloc::raw_vec::RawVecInner::non_null::<u8>) {
-                                          let mut _46: std::ptr::NonNull<u8>;
-                                          scope 36 (inlined std::ptr::Unique::<u8>::cast::<u8>) {
-                                              scope 37 (inlined NonNull::<u8>::cast::<u8>) {
-                                                  scope 38 (inlined NonNull::<u8>::as_ptr) {
+      scope 32 (inlined std::cmp::impls::<impl PartialEq<&str> for &String>::eq) {
+          let mut _47: &std::string::String;
+          let mut _48: &str;
+          scope 33 (inlined <String as PartialEq<str>>::eq) {
+              scope 34 (inlined #[track_caller] <String as Index<RangeFull>>::index) {
+                  let _49: &str;
+                  scope 35 (inlined String::as_str) {
+                      let _50: &[u8];
+                      scope 36 (inlined Vec::<u8>::as_slice) {
+                          let _51: *const [u8];
+                          let mut _52: *const u8;
+                          let mut _53: usize;
+                          scope 37 (inlined Vec::<u8>::as_ptr) {
+                              scope 38 (inlined alloc::raw_vec::RawVec::<u8>::ptr) {
+                                  scope 39 (inlined alloc::raw_vec::RawVecInner::ptr::<u8>) {
+                                      scope 40 (inlined alloc::raw_vec::RawVecInner::non_null::<u8>) {
+                                          let mut _54: std::ptr::NonNull<u8>;
+                                          scope 41 (inlined std::ptr::Unique::<u8>::cast::<u8>) {
+                                              scope 42 (inlined NonNull::<u8>::cast::<u8>) {
+                                                  scope 43 (inlined NonNull::<u8>::as_ptr) {
                                                   }
                                               }
                                           }
-                                          scope 39 (inlined std::ptr::Unique::<u8>::as_non_null_ptr) {
+                                          scope 44 (inlined std::ptr::Unique::<u8>::as_non_null_ptr) {
                                           }
                                       }
-                                      scope 40 (inlined NonNull::<u8>::as_ptr) {
+                                      scope 45 (inlined NonNull::<u8>::as_ptr) {
                                       }
                                   }
                               }
                           }
                       }
-                      scope 41 (inlined from_utf8_unchecked) {
+                      scope 46 (inlined from_utf8_unchecked) {
                       }
                   }
-                  scope 42 (inlined #[track_caller] core::str::traits::<impl SliceIndex<str> for RangeFull>::index) {
+                  scope 47 (inlined #[track_caller] core::str::traits::<impl SliceIndex<str> for RangeFull>::index) {
                   }
               }
-              scope 43 (inlined #[track_caller] core::str::traits::<impl Index<RangeFull> for str>::index) {
-                  scope 44 (inlined #[track_caller] core::str::traits::<impl SliceIndex<str> for RangeFull>::index) {
+              scope 48 (inlined #[track_caller] core::str::traits::<impl Index<RangeFull> for str>::index) {
+                  scope 49 (inlined #[track_caller] core::str::traits::<impl SliceIndex<str> for RangeFull>::index) {
                   }
               }
-              scope 45 (inlined core::str::traits::<impl PartialEq for str>::eq) {
-                  let mut _47: &&[u8];
-                  let _48: &[u8];
-                  let mut _49: &&[u8];
-                  let _50: &[u8];
-                  scope 46 (inlined core::str::<impl str>::as_bytes) {
+              scope 50 (inlined core::str::traits::<impl PartialEq for str>::eq) {
+                  let mut _55: &&[u8];
+                  let _56: &[u8];
+                  let mut _57: &&[u8];
+                  let _58: &[u8];
+                  scope 51 (inlined core::str::<impl str>::as_bytes) {
                   }
-                  scope 47 (inlined core::str::<impl str>::as_bytes) {
+                  scope 52 (inlined core::str::<impl str>::as_bytes) {
                   }
-                  scope 48 (inlined std::cmp::impls::<impl PartialEq for &[u8]>::eq) {
-                      scope 49 (inlined core::slice::cmp::<impl PartialEq for [u8]>::eq) {
+                  scope 53 (inlined std::cmp::impls::<impl PartialEq for &[u8]>::eq) {
+                      scope 54 (inlined core::slice::cmp::<impl PartialEq for [u8]>::eq) {
+                          let _59: usize;
+                          let mut _60: bool;
+                          let mut _61: usize;
+                          let mut _62: *const u8;
+                          let mut _63: *const u8;
+                          scope 55 {
+                              scope 56 (inlined core::slice::<impl [u8]>::as_ptr) {
+                                  let mut _64: *const [u8];
+                              }
+                              scope 57 (inlined core::slice::<impl [u8]>::as_ptr) {
+                                  let mut _65: *const [u8];
+                              }
+                              scope 58 (inlined <u8 as core::slice::cmp::SlicePartialEq<u8>>::equal_same_length) {
+                                  let mut _66: i32;
+                                  scope 59 {
+                                  }
+                              }
+                          }
                       }
                   }
               }
@@ -179,7 +215,7 @@
       bb3: {
           _1 = chained_conditions::BacktraceStyle::Off;
 -         goto -> bb18;
-+         goto -> bb23;
++         goto -> bb29;
       }
   
       bb4: {
@@ -216,9 +252,17 @@
           StorageDead(_30);
           StorageLive(_36);
           StorageLive(_38);
+          StorageLive(_39);
+          StorageLive(_42);
+          StorageLive(_43);
           _36 = copy _29 as &[u8] (Transmute);
           _38 = copy _28 as &[u8] (Transmute);
-          _7 = <[u8] as core::slice::cmp::SlicePartialEq<u8>>::equal(move _36, move _38) -> [return: bb19, unwind unreachable];
+          _39 = PtrMetadata(copy _36);
+          StorageLive(_40);
+          StorageLive(_41);
+          _41 = PtrMetadata(copy _38);
+          _40 = Eq(copy _39, move _41);
+          switchInt(move _40) -> [0: bb20, otherwise: bb19];
       }
   
       bb5: {
@@ -249,39 +293,47 @@
           StorageLive(_17);
           _20 = const chained_conditions::promoted[0];
           _17 = &(*_20);
-          StorageLive(_39);
-          StorageLive(_40);
-          _39 = copy (*_15);
-          _40 = copy (*_17);
-          StorageLive(_41);
-          StorageLive(_42);
-          StorageLive(_43);
-          StorageLive(_44);
-          StorageLive(_46);
-          _46 = copy ((((((*_39).0: std::vec::Vec<u8>).0: alloc::raw_vec::RawVec<u8>).0: alloc::raw_vec::RawVecInner).0: std::ptr::Unique<u8>).0: std::ptr::NonNull<u8>);
-          _44 = copy _46 as *const u8 (Transmute);
-          StorageDead(_46);
-          StorageLive(_45);
-          _45 = copy (((*_39).0: std::vec::Vec<u8>).1: usize);
-          _43 = *const [u8] from (copy _44, move _45);
-          StorageDead(_45);
-          StorageDead(_44);
-          _42 = &(*_43);
-          StorageDead(_43);
-          _41 = copy _42 as &str (Transmute);
-          StorageDead(_42);
+          StorageLive(_47);
           StorageLive(_48);
+          _47 = copy (*_15);
+          _48 = copy (*_17);
+          StorageLive(_49);
           StorageLive(_50);
-          _48 = copy _41 as &[u8] (Transmute);
-          _50 = copy _40 as &[u8] (Transmute);
-          _14 = <[u8] as core::slice::cmp::SlicePartialEq<u8>>::equal(move _48, move _50) -> [return: bb20, unwind unreachable];
+          StorageLive(_51);
+          StorageLive(_52);
+          StorageLive(_54);
+          _54 = copy ((((((*_47).0: std::vec::Vec<u8>).0: alloc::raw_vec::RawVec<u8>).0: alloc::raw_vec::RawVecInner).0: std::ptr::Unique<u8>).0: std::ptr::NonNull<u8>);
+          _52 = copy _54 as *const u8 (Transmute);
+          StorageDead(_54);
+          StorageLive(_53);
+          _53 = copy (((*_47).0: std::vec::Vec<u8>).1: usize);
+          _51 = *const [u8] from (copy _52, move _53);
+          StorageDead(_53);
+          StorageDead(_52);
+          _50 = &(*_51);
+          StorageDead(_51);
+          _49 = copy _50 as &str (Transmute);
+          StorageDead(_50);
+          StorageLive(_56);
+          StorageLive(_58);
+          StorageLive(_59);
+          StorageLive(_62);
+          StorageLive(_63);
+          _56 = copy _49 as &[u8] (Transmute);
+          _58 = copy _48 as &[u8] (Transmute);
+          _59 = PtrMetadata(copy _56);
+          StorageLive(_60);
+          StorageLive(_61);
+          _61 = PtrMetadata(copy _58);
+          _60 = Eq(copy _59, move _61);
+          switchInt(move _60) -> [0: bb24, otherwise: bb23];
       }
   
       bb7: {
           StorageDead(_5);
           StorageDead(_6);
 -         goto -> bb18;
-+         goto -> bb21;
++         goto -> bb27;
       }
   
       bb8: {
@@ -304,14 +356,14 @@
           StorageDead(_13);
           _1 = chained_conditions::BacktraceStyle::Short;
 -         goto -> bb18;
-+         goto -> bb23;
++         goto -> bb29;
       }
   
       bb10: {
           StorageDead(_12);
           StorageDead(_13);
 -         goto -> bb18;
-+         goto -> bb21;
++         goto -> bb27;
       }
   
       bb11: {
@@ -356,6 +408,31 @@
       }
   
       bb19: {
+          StorageDead(_41);
+          StorageLive(_44);
+          _44 = &raw const (*_36);
+          _42 = copy _44 as *const u8 (PtrToPtr);
+          StorageDead(_44);
+          StorageLive(_45);
+          _45 = &raw const (*_38);
+          _43 = copy _45 as *const u8 (PtrToPtr);
+          StorageDead(_45);
+          StorageLive(_46);
+          _46 = compare_bytes(move _42, move _43, move _39) -> [return: bb22, unwind unreachable];
+      }
+  
+      bb20: {
+          StorageDead(_41);
+          _7 = const false;
+-         goto -> bb21;
++         goto -> bb32;
+      }
+  
+      bb21: {
+          StorageDead(_40);
+          StorageDead(_43);
+          StorageDead(_42);
+          StorageDead(_39);
           StorageDead(_38);
           StorageDead(_36);
           StorageDead(_29);
@@ -364,31 +441,94 @@
           switchInt(move _7) -> [0: bb6, otherwise: bb5];
       }
   
-      bb20: {
-          StorageDead(_50);
+      bb22: {
+          _7 = Eq(move _46, const 0_i32);
+          StorageDead(_46);
+          goto -> bb21;
+      }
+  
+      bb23: {
+          StorageDead(_61);
+          StorageLive(_64);
+          _64 = &raw const (*_56);
+          _62 = copy _64 as *const u8 (PtrToPtr);
+          StorageDead(_64);
+          StorageLive(_65);
+          _65 = &raw const (*_58);
+          _63 = copy _65 as *const u8 (PtrToPtr);
+          StorageDead(_65);
+          StorageLive(_66);
+          _66 = compare_bytes(move _62, move _63, move _59) -> [return: bb26, unwind unreachable];
+      }
+  
+      bb24: {
+          StorageDead(_61);
+          _14 = const false;
+-         goto -> bb25;
++         goto -> bb31;
+      }
+  
+      bb25: {
+          StorageDead(_60);
+          StorageDead(_63);
+          StorageDead(_62);
+          StorageDead(_59);
+          StorageDead(_58);
+          StorageDead(_56);
+          StorageDead(_49);
           StorageDead(_48);
-          StorageDead(_41);
-          StorageDead(_40);
-          StorageDead(_39);
+          StorageDead(_47);
           switchInt(move _14) -> [0: bb9, otherwise: bb8];
+      }
+  
+      bb26: {
+          _14 = Eq(move _66, const 0_i32);
+          StorageDead(_66);
+          goto -> bb25;
 +     }
 + 
-+     bb21: {
++     bb27: {
 +         _24 = discriminant(_2);
-+         switchInt(move _24) -> [1: bb22, otherwise: bb15];
++         switchInt(move _24) -> [1: bb28, otherwise: bb15];
 +     }
 + 
-+     bb22: {
++     bb28: {
 +         goto -> bb15;
 +     }
 + 
-+     bb23: {
++     bb29: {
 +         _24 = discriminant(_2);
-+         switchInt(move _24) -> [1: bb24, otherwise: bb15];
++         switchInt(move _24) -> [1: bb30, otherwise: bb15];
 +     }
 + 
-+     bb24: {
++     bb30: {
 +         goto -> bb17;
++     }
++ 
++     bb31: {
++         StorageDead(_60);
++         StorageDead(_63);
++         StorageDead(_62);
++         StorageDead(_59);
++         StorageDead(_58);
++         StorageDead(_56);
++         StorageDead(_49);
++         StorageDead(_48);
++         StorageDead(_47);
++         goto -> bb9;
++     }
++ 
++     bb32: {
++         StorageDead(_40);
++         StorageDead(_43);
++         StorageDead(_42);
++         StorageDead(_39);
++         StorageDead(_38);
++         StorageDead(_36);
++         StorageDead(_29);
++         StorageDead(_28);
++         StorageDead(_27);
++         goto -> bb6;
       }
   }
   
diff --git a/tests/mir-opt/jump_threading.chained_conditions.JumpThreading.panic-unwind.diff b/tests/mir-opt/jump_threading.chained_conditions.JumpThreading.panic-unwind.diff
index 49cd68577a12..71d91fed6307 100644
--- a/tests/mir-opt/jump_threading.chained_conditions.JumpThreading.panic-unwind.diff
+++ b/tests/mir-opt/jump_threading.chained_conditions.JumpThreading.panic-unwind.diff
@@ -93,64 +93,100 @@
                   }
                   scope 25 (inlined std::cmp::impls::<impl PartialEq for &[u8]>::eq) {
                       scope 26 (inlined core::slice::cmp::<impl PartialEq for [u8]>::eq) {
+                          let _39: usize;
+                          let mut _40: bool;
+                          let mut _41: usize;
+                          let mut _42: *const u8;
+                          let mut _43: *const u8;
+                          scope 27 {
+                              scope 28 (inlined core::slice::<impl [u8]>::as_ptr) {
+                                  let mut _44: *const [u8];
+                              }
+                              scope 29 (inlined core::slice::<impl [u8]>::as_ptr) {
+                                  let mut _45: *const [u8];
+                              }
+                              scope 30 (inlined <u8 as core::slice::cmp::SlicePartialEq<u8>>::equal_same_length) {
+                                  let mut _46: i32;
+                                  scope 31 {
+                                  }
+                              }
+                          }
                       }
                   }
               }
           }
       }
-      scope 27 (inlined std::cmp::impls::<impl PartialEq<&str> for &String>::eq) {
-          let mut _39: &std::string::String;
-          let mut _40: &str;
-          scope 28 (inlined <String as PartialEq<str>>::eq) {
-              scope 29 (inlined #[track_caller] <String as Index<RangeFull>>::index) {
-                  let _41: &str;
-                  scope 30 (inlined String::as_str) {
-                      let _42: &[u8];
-                      scope 31 (inlined Vec::<u8>::as_slice) {
-                          let _43: *const [u8];
-                          let mut _44: *const u8;
-                          let mut _45: usize;
-                          scope 32 (inlined Vec::<u8>::as_ptr) {
-                              scope 33 (inlined alloc::raw_vec::RawVec::<u8>::ptr) {
-                                  scope 34 (inlined alloc::raw_vec::RawVecInner::ptr::<u8>) {
-                                      scope 35 (inlined alloc::raw_vec::RawVecInner::non_null::<u8>) {
-                                          let mut _46: std::ptr::NonNull<u8>;
-                                          scope 36 (inlined std::ptr::Unique::<u8>::cast::<u8>) {
-                                              scope 37 (inlined NonNull::<u8>::cast::<u8>) {
-                                                  scope 38 (inlined NonNull::<u8>::as_ptr) {
+      scope 32 (inlined std::cmp::impls::<impl PartialEq<&str> for &String>::eq) {
+          let mut _47: &std::string::String;
+          let mut _48: &str;
+          scope 33 (inlined <String as PartialEq<str>>::eq) {
+              scope 34 (inlined #[track_caller] <String as Index<RangeFull>>::index) {
+                  let _49: &str;
+                  scope 35 (inlined String::as_str) {
+                      let _50: &[u8];
+                      scope 36 (inlined Vec::<u8>::as_slice) {
+                          let _51: *const [u8];
+                          let mut _52: *const u8;
+                          let mut _53: usize;
+                          scope 37 (inlined Vec::<u8>::as_ptr) {
+                              scope 38 (inlined alloc::raw_vec::RawVec::<u8>::ptr) {
+                                  scope 39 (inlined alloc::raw_vec::RawVecInner::ptr::<u8>) {
+                                      scope 40 (inlined alloc::raw_vec::RawVecInner::non_null::<u8>) {
+                                          let mut _54: std::ptr::NonNull<u8>;
+                                          scope 41 (inlined std::ptr::Unique::<u8>::cast::<u8>) {
+                                              scope 42 (inlined NonNull::<u8>::cast::<u8>) {
+                                                  scope 43 (inlined NonNull::<u8>::as_ptr) {
                                                   }
                                               }
                                           }
-                                          scope 39 (inlined std::ptr::Unique::<u8>::as_non_null_ptr) {
+                                          scope 44 (inlined std::ptr::Unique::<u8>::as_non_null_ptr) {
                                           }
                                       }
-                                      scope 40 (inlined NonNull::<u8>::as_ptr) {
+                                      scope 45 (inlined NonNull::<u8>::as_ptr) {
                                       }
                                   }
                               }
                           }
                       }
-                      scope 41 (inlined from_utf8_unchecked) {
+                      scope 46 (inlined from_utf8_unchecked) {
                       }
                   }
-                  scope 42 (inlined #[track_caller] core::str::traits::<impl SliceIndex<str> for RangeFull>::index) {
+                  scope 47 (inlined #[track_caller] core::str::traits::<impl SliceIndex<str> for RangeFull>::index) {
                   }
               }
-              scope 43 (inlined #[track_caller] core::str::traits::<impl Index<RangeFull> for str>::index) {
-                  scope 44 (inlined #[track_caller] core::str::traits::<impl SliceIndex<str> for RangeFull>::index) {
+              scope 48 (inlined #[track_caller] core::str::traits::<impl Index<RangeFull> for str>::index) {
+                  scope 49 (inlined #[track_caller] core::str::traits::<impl SliceIndex<str> for RangeFull>::index) {
                   }
               }
-              scope 45 (inlined core::str::traits::<impl PartialEq for str>::eq) {
-                  let mut _47: &&[u8];
-                  let _48: &[u8];
-                  let mut _49: &&[u8];
-                  let _50: &[u8];
-                  scope 46 (inlined core::str::<impl str>::as_bytes) {
+              scope 50 (inlined core::str::traits::<impl PartialEq for str>::eq) {
+                  let mut _55: &&[u8];
+                  let _56: &[u8];
+                  let mut _57: &&[u8];
+                  let _58: &[u8];
+                  scope 51 (inlined core::str::<impl str>::as_bytes) {
                   }
-                  scope 47 (inlined core::str::<impl str>::as_bytes) {
+                  scope 52 (inlined core::str::<impl str>::as_bytes) {
                   }
-                  scope 48 (inlined std::cmp::impls::<impl PartialEq for &[u8]>::eq) {
-                      scope 49 (inlined core::slice::cmp::<impl PartialEq for [u8]>::eq) {
+                  scope 53 (inlined std::cmp::impls::<impl PartialEq for &[u8]>::eq) {
+                      scope 54 (inlined core::slice::cmp::<impl PartialEq for [u8]>::eq) {
+                          let _59: usize;
+                          let mut _60: bool;
+                          let mut _61: usize;
+                          let mut _62: *const u8;
+                          let mut _63: *const u8;
+                          scope 55 {
+                              scope 56 (inlined core::slice::<impl [u8]>::as_ptr) {
+                                  let mut _64: *const [u8];
+                              }
+                              scope 57 (inlined core::slice::<impl [u8]>::as_ptr) {
+                                  let mut _65: *const [u8];
+                              }
+                              scope 58 (inlined <u8 as core::slice::cmp::SlicePartialEq<u8>>::equal_same_length) {
+                                  let mut _66: i32;
+                                  scope 59 {
+                                  }
+                              }
+                          }
                       }
                   }
               }
@@ -179,7 +215,7 @@
       bb3: {
           _1 = chained_conditions::BacktraceStyle::Off;
 -         goto -> bb19;
-+         goto -> bb27;
++         goto -> bb33;
       }
   
       bb4: {
@@ -216,9 +252,17 @@
           StorageDead(_30);
           StorageLive(_36);
           StorageLive(_38);
+          StorageLive(_39);
+          StorageLive(_42);
+          StorageLive(_43);
           _36 = copy _29 as &[u8] (Transmute);
           _38 = copy _28 as &[u8] (Transmute);
-          _7 = <[u8] as core::slice::cmp::SlicePartialEq<u8>>::equal(move _36, move _38) -> [return: bb23, unwind: bb22];
+          _39 = PtrMetadata(copy _36);
+          StorageLive(_40);
+          StorageLive(_41);
+          _41 = PtrMetadata(copy _38);
+          _40 = Eq(copy _39, move _41);
+          switchInt(move _40) -> [0: bb24, otherwise: bb23];
       }
   
       bb5: {
@@ -249,39 +293,47 @@
           StorageLive(_17);
           _20 = const chained_conditions::promoted[0];
           _17 = &(*_20);
-          StorageLive(_39);
-          StorageLive(_40);
-          _39 = copy (*_15);
-          _40 = copy (*_17);
-          StorageLive(_41);
-          StorageLive(_42);
-          StorageLive(_43);
-          StorageLive(_44);
-          StorageLive(_46);
-          _46 = copy ((((((*_39).0: std::vec::Vec<u8>).0: alloc::raw_vec::RawVec<u8>).0: alloc::raw_vec::RawVecInner).0: std::ptr::Unique<u8>).0: std::ptr::NonNull<u8>);
-          _44 = copy _46 as *const u8 (Transmute);
-          StorageDead(_46);
-          StorageLive(_45);
-          _45 = copy (((*_39).0: std::vec::Vec<u8>).1: usize);
-          _43 = *const [u8] from (copy _44, move _45);
-          StorageDead(_45);
-          StorageDead(_44);
-          _42 = &(*_43);
-          StorageDead(_43);
-          _41 = copy _42 as &str (Transmute);
-          StorageDead(_42);
+          StorageLive(_47);
           StorageLive(_48);
+          _47 = copy (*_15);
+          _48 = copy (*_17);
+          StorageLive(_49);
           StorageLive(_50);
-          _48 = copy _41 as &[u8] (Transmute);
-          _50 = copy _40 as &[u8] (Transmute);
-          _14 = <[u8] as core::slice::cmp::SlicePartialEq<u8>>::equal(move _48, move _50) -> [return: bb24, unwind: bb22];
+          StorageLive(_51);
+          StorageLive(_52);
+          StorageLive(_54);
+          _54 = copy ((((((*_47).0: std::vec::Vec<u8>).0: alloc::raw_vec::RawVec<u8>).0: alloc::raw_vec::RawVecInner).0: std::ptr::Unique<u8>).0: std::ptr::NonNull<u8>);
+          _52 = copy _54 as *const u8 (Transmute);
+          StorageDead(_54);
+          StorageLive(_53);
+          _53 = copy (((*_47).0: std::vec::Vec<u8>).1: usize);
+          _51 = *const [u8] from (copy _52, move _53);
+          StorageDead(_53);
+          StorageDead(_52);
+          _50 = &(*_51);
+          StorageDead(_51);
+          _49 = copy _50 as &str (Transmute);
+          StorageDead(_50);
+          StorageLive(_56);
+          StorageLive(_58);
+          StorageLive(_59);
+          StorageLive(_62);
+          StorageLive(_63);
+          _56 = copy _49 as &[u8] (Transmute);
+          _58 = copy _48 as &[u8] (Transmute);
+          _59 = PtrMetadata(copy _56);
+          StorageLive(_60);
+          StorageLive(_61);
+          _61 = PtrMetadata(copy _58);
+          _60 = Eq(copy _59, move _61);
+          switchInt(move _60) -> [0: bb28, otherwise: bb27];
       }
   
       bb7: {
           StorageDead(_5);
           StorageDead(_6);
 -         goto -> bb19;
-+         goto -> bb25;
++         goto -> bb31;
       }
   
       bb8: {
@@ -304,14 +356,14 @@
           StorageDead(_13);
           _1 = chained_conditions::BacktraceStyle::Short;
 -         goto -> bb19;
-+         goto -> bb27;
++         goto -> bb33;
       }
   
       bb10: {
           StorageDead(_12);
           StorageDead(_13);
 -         goto -> bb19;
-+         goto -> bb25;
++         goto -> bb31;
       }
   
       bb11: {
@@ -373,6 +425,31 @@
       }
   
       bb23: {
+          StorageDead(_41);
+          StorageLive(_44);
+          _44 = &raw const (*_36);
+          _42 = copy _44 as *const u8 (PtrToPtr);
+          StorageDead(_44);
+          StorageLive(_45);
+          _45 = &raw const (*_38);
+          _43 = copy _45 as *const u8 (PtrToPtr);
+          StorageDead(_45);
+          StorageLive(_46);
+          _46 = compare_bytes(move _42, move _43, move _39) -> [return: bb26, unwind unreachable];
+      }
+  
+      bb24: {
+          StorageDead(_41);
+          _7 = const false;
+-         goto -> bb25;
++         goto -> bb36;
+      }
+  
+      bb25: {
+          StorageDead(_40);
+          StorageDead(_43);
+          StorageDead(_42);
+          StorageDead(_39);
           StorageDead(_38);
           StorageDead(_36);
           StorageDead(_29);
@@ -381,31 +458,94 @@
           switchInt(move _7) -> [0: bb6, otherwise: bb5];
       }
   
-      bb24: {
-          StorageDead(_50);
+      bb26: {
+          _7 = Eq(move _46, const 0_i32);
+          StorageDead(_46);
+          goto -> bb25;
+      }
+  
+      bb27: {
+          StorageDead(_61);
+          StorageLive(_64);
+          _64 = &raw const (*_56);
+          _62 = copy _64 as *const u8 (PtrToPtr);
+          StorageDead(_64);
+          StorageLive(_65);
+          _65 = &raw const (*_58);
+          _63 = copy _65 as *const u8 (PtrToPtr);
+          StorageDead(_65);
+          StorageLive(_66);
+          _66 = compare_bytes(move _62, move _63, move _59) -> [return: bb30, unwind unreachable];
+      }
+  
+      bb28: {
+          StorageDead(_61);
+          _14 = const false;
+-         goto -> bb29;
++         goto -> bb35;
+      }
+  
+      bb29: {
+          StorageDead(_60);
+          StorageDead(_63);
+          StorageDead(_62);
+          StorageDead(_59);
+          StorageDead(_58);
+          StorageDead(_56);
+          StorageDead(_49);
           StorageDead(_48);
-          StorageDead(_41);
-          StorageDead(_40);
-          StorageDead(_39);
+          StorageDead(_47);
           switchInt(move _14) -> [0: bb9, otherwise: bb8];
+      }
+  
+      bb30: {
+          _14 = Eq(move _66, const 0_i32);
+          StorageDead(_66);
+          goto -> bb29;
 +     }
 + 
-+     bb25: {
++     bb31: {
 +         _24 = discriminant(_2);
-+         switchInt(move _24) -> [1: bb26, otherwise: bb16];
++         switchInt(move _24) -> [1: bb32, otherwise: bb16];
 +     }
 + 
-+     bb26: {
++     bb32: {
 +         goto -> bb16;
 +     }
 + 
-+     bb27: {
++     bb33: {
 +         _24 = discriminant(_2);
-+         switchInt(move _24) -> [1: bb28, otherwise: bb16];
++         switchInt(move _24) -> [1: bb34, otherwise: bb16];
 +     }
 + 
-+     bb28: {
++     bb34: {
 +         goto -> bb18;
++     }
++ 
++     bb35: {
++         StorageDead(_60);
++         StorageDead(_63);
++         StorageDead(_62);
++         StorageDead(_59);
++         StorageDead(_58);
++         StorageDead(_56);
++         StorageDead(_49);
++         StorageDead(_48);
++         StorageDead(_47);
++         goto -> bb9;
++     }
++ 
++     bb36: {
++         StorageDead(_40);
++         StorageDead(_43);
++         StorageDead(_42);
++         StorageDead(_39);
++         StorageDead(_38);
++         StorageDead(_36);
++         StorageDead(_29);
++         StorageDead(_28);
++         StorageDead(_27);
++         goto -> bb6;
       }
   }
   

From 814d902c503920334e3b992cb3d208b9742e24f3 Mon Sep 17 00:00:00 2001
From: joboet <jonasboettiger@icloud.com>
Date: Thu, 15 Jan 2026 14:27:10 +0100
Subject: [PATCH 56/97] std: move time implementations to `sys` (preparation)

---
 library/std/src/sys/mod.rs      | 1 +
 library/std/src/sys/time/mod.rs | 4 ++++
 2 files changed, 5 insertions(+)
 create mode 100644 library/std/src/sys/time/mod.rs

diff --git a/library/std/src/sys/mod.rs b/library/std/src/sys/mod.rs
index c9035938cfdd..5436c144d333 100644
--- a/library/std/src/sys/mod.rs
+++ b/library/std/src/sys/mod.rs
@@ -26,6 +26,7 @@ pub mod stdio;
 pub mod sync;
 pub mod thread;
 pub mod thread_local;
+pub mod time;
 
 // FIXME(117276): remove this, move feature implementations into individual
 //                submodules.
diff --git a/library/std/src/sys/time/mod.rs b/library/std/src/sys/time/mod.rs
new file mode 100644
index 000000000000..015871e6f1ec
--- /dev/null
+++ b/library/std/src/sys/time/mod.rs
@@ -0,0 +1,4 @@
+cfg_select! {
+}
+
+pub use imp::{Instant, SystemTime, UNIX_EPOCH};

From 29b16c0a55e14504ec24eddc0a3ace7074687ce4 Mon Sep 17 00:00:00 2001
From: joboet <jonasboettiger@icloud.com>
Date: Thu, 15 Jan 2026 14:38:41 +0100
Subject: [PATCH 57/97] std: move time implementations to `sys` (small
 platforms)

Let's start with the easy ones:
* Motor just reexports its platform library
* The SGX code is just a trivial move
* Trusty, WASM and ZKVM are unsupported, this is very trivial. And we can get
  rid of some `#[path = ...]`s, yay!
---
 library/std/src/sys/pal/motor/mod.rs              |  1 -
 library/std/src/sys/pal/motor/time.rs             |  1 -
 library/std/src/sys/pal/sgx/mod.rs                |  1 -
 library/std/src/sys/pal/trusty/mod.rs             |  2 --
 library/std/src/sys/pal/unsupported/mod.rs        |  1 -
 library/std/src/sys/pal/wasm/mod.rs               |  2 --
 library/std/src/sys/pal/xous/mod.rs               |  1 -
 library/std/src/sys/pal/zkvm/mod.rs               |  2 --
 library/std/src/sys/time/mod.rs                   | 15 +++++++++++++++
 .../std/src/sys/{pal/sgx/time.rs => time/sgx.rs}  |  2 +-
 .../unsupported/time.rs => time/unsupported.rs}   |  0
 .../src/sys/{pal/xous/time.rs => time/xous.rs}    |  0
 12 files changed, 16 insertions(+), 12 deletions(-)
 delete mode 100644 library/std/src/sys/pal/motor/time.rs
 rename library/std/src/sys/{pal/sgx/time.rs => time/sgx.rs} (97%)
 rename library/std/src/sys/{pal/unsupported/time.rs => time/unsupported.rs} (100%)
 rename library/std/src/sys/{pal/xous/time.rs => time/xous.rs} (100%)

diff --git a/library/std/src/sys/pal/motor/mod.rs b/library/std/src/sys/pal/motor/mod.rs
index e5b99cea01d5..a520375a4bbf 100644
--- a/library/std/src/sys/pal/motor/mod.rs
+++ b/library/std/src/sys/pal/motor/mod.rs
@@ -1,7 +1,6 @@
 #![allow(unsafe_op_in_unsafe_fn)]
 
 pub mod os;
-pub mod time;
 
 pub use moto_rt::futex;
 
diff --git a/library/std/src/sys/pal/motor/time.rs b/library/std/src/sys/pal/motor/time.rs
deleted file mode 100644
index e917fd466c2e..000000000000
--- a/library/std/src/sys/pal/motor/time.rs
+++ /dev/null
@@ -1 +0,0 @@
-pub use moto_rt::time::{Instant, SystemTime, UNIX_EPOCH};
diff --git a/library/std/src/sys/pal/sgx/mod.rs b/library/std/src/sys/pal/sgx/mod.rs
index 7f1c81a0ff7b..1de3ca4a5d79 100644
--- a/library/std/src/sys/pal/sgx/mod.rs
+++ b/library/std/src/sys/pal/sgx/mod.rs
@@ -12,7 +12,6 @@ pub mod abi;
 mod libunwind_integration;
 pub mod os;
 pub mod thread_parking;
-pub mod time;
 pub mod waitqueue;
 
 // SAFETY: must be called only once during runtime initialization.
diff --git a/library/std/src/sys/pal/trusty/mod.rs b/library/std/src/sys/pal/trusty/mod.rs
index 76a3a75b10c1..b785c2dbb789 100644
--- a/library/std/src/sys/pal/trusty/mod.rs
+++ b/library/std/src/sys/pal/trusty/mod.rs
@@ -5,7 +5,5 @@
 mod common;
 #[path = "../unsupported/os.rs"]
 pub mod os;
-#[path = "../unsupported/time.rs"]
-pub mod time;
 
 pub use common::*;
diff --git a/library/std/src/sys/pal/unsupported/mod.rs b/library/std/src/sys/pal/unsupported/mod.rs
index c33d2e5fb02a..0f157819d5a6 100644
--- a/library/std/src/sys/pal/unsupported/mod.rs
+++ b/library/std/src/sys/pal/unsupported/mod.rs
@@ -1,7 +1,6 @@
 #![deny(unsafe_op_in_unsafe_fn)]
 
 pub mod os;
-pub mod time;
 
 mod common;
 pub use common::*;
diff --git a/library/std/src/sys/pal/wasm/mod.rs b/library/std/src/sys/pal/wasm/mod.rs
index 80429a9aae18..5f56eddd6a81 100644
--- a/library/std/src/sys/pal/wasm/mod.rs
+++ b/library/std/src/sys/pal/wasm/mod.rs
@@ -18,8 +18,6 @@
 
 #[path = "../unsupported/os.rs"]
 pub mod os;
-#[path = "../unsupported/time.rs"]
-pub mod time;
 
 #[cfg(target_feature = "atomics")]
 #[path = "atomics/futex.rs"]
diff --git a/library/std/src/sys/pal/xous/mod.rs b/library/std/src/sys/pal/xous/mod.rs
index 19575220b22e..87c99068929c 100644
--- a/library/std/src/sys/pal/xous/mod.rs
+++ b/library/std/src/sys/pal/xous/mod.rs
@@ -1,7 +1,6 @@
 #![forbid(unsafe_op_in_unsafe_fn)]
 
 pub mod os;
-pub mod time;
 
 #[path = "../unsupported/common.rs"]
 mod common;
diff --git a/library/std/src/sys/pal/zkvm/mod.rs b/library/std/src/sys/pal/zkvm/mod.rs
index f09020820a03..1b18adb811d9 100644
--- a/library/std/src/sys/pal/zkvm/mod.rs
+++ b/library/std/src/sys/pal/zkvm/mod.rs
@@ -12,8 +12,6 @@ pub const WORD_SIZE: usize = size_of::<u32>();
 
 pub mod abi;
 pub mod os;
-#[path = "../unsupported/time.rs"]
-pub mod time;
 
 use crate::io as std_io;
 
diff --git a/library/std/src/sys/time/mod.rs b/library/std/src/sys/time/mod.rs
index 015871e6f1ec..81c568bf9320 100644
--- a/library/std/src/sys/time/mod.rs
+++ b/library/std/src/sys/time/mod.rs
@@ -1,4 +1,19 @@
 cfg_select! {
+    target_os = "motor" => {
+        use moto_rt::time as imp;
+    }
+    all(target_vendor = "fortanix", target_env = "sgx") => {
+        mod sgx;
+        use sgx as imp;
+    }
+    target_os = "xous" => {
+        mod xous;
+        use xous as imp;
+    }
+    _ => {
+        mod unsupported;
+        use unsupported as imp;
+    }
 }
 
 pub use imp::{Instant, SystemTime, UNIX_EPOCH};
diff --git a/library/std/src/sys/pal/sgx/time.rs b/library/std/src/sys/time/sgx.rs
similarity index 97%
rename from library/std/src/sys/pal/sgx/time.rs
rename to library/std/src/sys/time/sgx.rs
index a9a448226619..910e734c916e 100644
--- a/library/std/src/sys/pal/sgx/time.rs
+++ b/library/std/src/sys/time/sgx.rs
@@ -1,4 +1,4 @@
-use super::abi::usercalls;
+use crate::sys::pal::abi::usercalls;
 use crate::time::Duration;
 
 #[derive(Copy, Clone, PartialEq, Eq, PartialOrd, Ord, Debug, Hash)]
diff --git a/library/std/src/sys/pal/unsupported/time.rs b/library/std/src/sys/time/unsupported.rs
similarity index 100%
rename from library/std/src/sys/pal/unsupported/time.rs
rename to library/std/src/sys/time/unsupported.rs
diff --git a/library/std/src/sys/pal/xous/time.rs b/library/std/src/sys/time/xous.rs
similarity index 100%
rename from library/std/src/sys/pal/xous/time.rs
rename to library/std/src/sys/time/xous.rs

From 5978e194564d628afe2e54cc1068d0791a7e2e8d Mon Sep 17 00:00:00 2001
From: joboet <jonasboettiger@icloud.com>
Date: Thu, 15 Jan 2026 14:57:03 +0100
Subject: [PATCH 58/97] std: move time implementations to `sys` (VEX)

Now that the `unsupported` module exists, we can use it for VEX. VEX actually
supports `Instant` though, so the implementation-select needs to combine that
with the `unsupported` module.
---
 library/std/src/sys/pal/vexos/mod.rs                   |  1 -
 library/std/src/sys/time/mod.rs                        | 10 ++++++++++
 .../std/src/sys/{pal/vexos/time.rs => time/vexos.rs}   |  5 -----
 3 files changed, 10 insertions(+), 6 deletions(-)
 rename library/std/src/sys/{pal/vexos/time.rs => time/vexos.rs} (83%)

diff --git a/library/std/src/sys/pal/vexos/mod.rs b/library/std/src/sys/pal/vexos/mod.rs
index 0abfc2fd7986..16aa3f088f04 100644
--- a/library/std/src/sys/pal/vexos/mod.rs
+++ b/library/std/src/sys/pal/vexos/mod.rs
@@ -1,5 +1,4 @@
 pub mod os;
-pub mod time;
 
 #[expect(dead_code)]
 #[path = "../unsupported/common.rs"]
diff --git a/library/std/src/sys/time/mod.rs b/library/std/src/sys/time/mod.rs
index 81c568bf9320..0e3376e2f910 100644
--- a/library/std/src/sys/time/mod.rs
+++ b/library/std/src/sys/time/mod.rs
@@ -6,6 +6,16 @@ cfg_select! {
         mod sgx;
         use sgx as imp;
     }
+    target_os = "vexos" => {
+        mod vexos;
+        #[expect(unused)]
+        mod unsupported;
+
+        mod imp {
+            pub use super::vexos::Instant;
+            pub use super::unsupported::{SystemTime, UNIX_EPOCH};
+        }
+    }
     target_os = "xous" => {
         mod xous;
         use xous as imp;
diff --git a/library/std/src/sys/pal/vexos/time.rs b/library/std/src/sys/time/vexos.rs
similarity index 83%
rename from library/std/src/sys/pal/vexos/time.rs
rename to library/std/src/sys/time/vexos.rs
index f95d96cd27ac..966c239699ce 100644
--- a/library/std/src/sys/pal/vexos/time.rs
+++ b/library/std/src/sys/time/vexos.rs
@@ -1,10 +1,5 @@
 use crate::time::Duration;
 
-#[expect(dead_code)]
-#[path = "../unsupported/time.rs"]
-mod unsupported_time;
-pub use unsupported_time::{SystemTime, UNIX_EPOCH};
-
 #[derive(Copy, Clone, PartialEq, Eq, PartialOrd, Ord, Debug, Hash)]
 pub struct Instant(Duration);
 

From bd754c7119a73bfc5e9e0d23071ebffc2ebce245 Mon Sep 17 00:00:00 2001
From: joboet <jonasboettiger@icloud.com>
Date: Thu, 15 Jan 2026 14:47:05 +0100
Subject: [PATCH 59/97] std: move time implementations to `sys` (Solid)
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

On SOLID, the conversion functions are also used to implement helpers for
timeout conversion, so these stay in the PAL. The `Instant` (µITRON) and
`SystemTime` (SOLID-specific) implementations are merged into one. While it was
nice to have the µITRON parts in a separate module, there really isn't a need
for this currently, as there is no other µITRON target. Let's not worry about
this until such a target gets added...

Note that I've extracted the `get_tim` call from `Instant` into a wrapper
function in the PAL to avoid the need to make the inner `Instant` field public
for use in the PAL.
---
 library/std/src/sys/pal/itron/time.rs         | 47 +++++--------------
 library/std/src/sys/pal/solid/mod.rs          |  1 -
 library/std/src/sys/time/mod.rs               |  4 ++
 .../sys/{pal/solid/time.rs => time/solid.rs}  | 35 ++++++++++++--
 4 files changed, 47 insertions(+), 40 deletions(-)
 rename library/std/src/sys/{pal/solid/time.rs => time/solid.rs} (65%)

diff --git a/library/std/src/sys/pal/itron/time.rs b/library/std/src/sys/pal/itron/time.rs
index 7976c27f4952..ff3cffd2069e 100644
--- a/library/std/src/sys/pal/itron/time.rs
+++ b/library/std/src/sys/pal/itron/time.rs
@@ -3,38 +3,16 @@ use super::error::expect_success;
 use crate::mem::MaybeUninit;
 use crate::time::Duration;
 
-#[derive(Copy, Clone, PartialEq, Eq, PartialOrd, Ord, Debug, Hash)]
-pub struct Instant(abi::SYSTIM);
+#[cfg(test)]
+mod tests;
 
-impl Instant {
-    pub fn now() -> Instant {
-        // Safety: The provided pointer is valid
-        unsafe {
-            let mut out = MaybeUninit::uninit();
-            expect_success(abi::get_tim(out.as_mut_ptr()), &"get_tim");
-            Instant(out.assume_init())
-        }
-    }
-
-    pub fn checked_sub_instant(&self, other: &Instant) -> Option<Duration> {
-        self.0.checked_sub(other.0).map(|ticks| {
-            // `SYSTIM` is measured in microseconds
-            Duration::from_micros(ticks)
-        })
-    }
-
-    pub fn checked_add_duration(&self, other: &Duration) -> Option<Instant> {
-        // `SYSTIM` is measured in microseconds
-        let ticks = other.as_micros();
-
-        Some(Instant(self.0.checked_add(ticks.try_into().ok()?)?))
-    }
-
-    pub fn checked_sub_duration(&self, other: &Duration) -> Option<Instant> {
-        // `SYSTIM` is measured in microseconds
-        let ticks = other.as_micros();
-
-        Some(Instant(self.0.checked_sub(ticks.try_into().ok()?)?))
+#[inline]
+pub fn get_tim() -> abi::SYSTIM {
+    // Safety: The provided pointer is valid
+    unsafe {
+        let mut out = MaybeUninit::uninit();
+        expect_success(abi::get_tim(out.as_mut_ptr()), &"get_tim");
+        out.assume_init()
     }
 }
 
@@ -98,7 +76,7 @@ pub fn with_tmos_strong(dur: Duration, mut f: impl FnMut(abi::TMO) -> abi::ER) -
     // a problem in practice. (`u64::MAX` μs ≈ 584942 years)
     let ticks = dur.as_micros().min(abi::SYSTIM::MAX as u128) as abi::SYSTIM;
 
-    let start = Instant::now().0;
+    let start = get_tim();
     let mut elapsed = 0;
     let mut er = abi::E_TMOUT;
     while elapsed <= ticks {
@@ -106,11 +84,8 @@ pub fn with_tmos_strong(dur: Duration, mut f: impl FnMut(abi::TMO) -> abi::ER) -
         if er != abi::E_TMOUT {
             break;
         }
-        elapsed = Instant::now().0.wrapping_sub(start);
+        elapsed = get_tim().wrapping_sub(start);
     }
 
     er
 }
-
-#[cfg(test)]
-mod tests;
diff --git a/library/std/src/sys/pal/solid/mod.rs b/library/std/src/sys/pal/solid/mod.rs
index 4eec12dacd7c..1376af8304cf 100644
--- a/library/std/src/sys/pal/solid/mod.rs
+++ b/library/std/src/sys/pal/solid/mod.rs
@@ -21,7 +21,6 @@ pub mod itron {
 pub(crate) mod error;
 pub mod os;
 pub use self::itron::thread_parking;
-pub mod time;
 
 // SAFETY: must be called only once during runtime initialization.
 // NOTE: this is not guaranteed to run, for example when Rust code is called externally.
diff --git a/library/std/src/sys/time/mod.rs b/library/std/src/sys/time/mod.rs
index 0e3376e2f910..e5b9a3a057f0 100644
--- a/library/std/src/sys/time/mod.rs
+++ b/library/std/src/sys/time/mod.rs
@@ -6,6 +6,10 @@ cfg_select! {
         mod sgx;
         use sgx as imp;
     }
+    target_os = "solid_asp3" => {
+        mod solid;
+        use solid as imp;
+    }
     target_os = "vexos" => {
         mod vexos;
         #[expect(unused)]
diff --git a/library/std/src/sys/pal/solid/time.rs b/library/std/src/sys/time/solid.rs
similarity index 65%
rename from library/std/src/sys/pal/solid/time.rs
rename to library/std/src/sys/time/solid.rs
index d5cf70f94c98..fa929c67241e 100644
--- a/library/std/src/sys/pal/solid/time.rs
+++ b/library/std/src/sys/time/solid.rs
@@ -1,9 +1,38 @@
-use super::abi;
-use super::error::expect_success;
-pub use super::itron::time::Instant;
 use crate::mem::MaybeUninit;
+use crate::sys::pal::error::expect_success;
+use crate::sys::pal::{abi, itron};
 use crate::time::Duration;
 
+#[derive(Copy, Clone, PartialEq, Eq, PartialOrd, Ord, Debug, Hash)]
+pub struct Instant(itron::abi::SYSTIM);
+
+impl Instant {
+    pub fn now() -> Instant {
+        Instant(itron::time::get_tim())
+    }
+
+    pub fn checked_sub_instant(&self, other: &Instant) -> Option<Duration> {
+        self.0.checked_sub(other.0).map(|ticks| {
+            // `SYSTIM` is measured in microseconds
+            Duration::from_micros(ticks)
+        })
+    }
+
+    pub fn checked_add_duration(&self, other: &Duration) -> Option<Instant> {
+        // `SYSTIM` is measured in microseconds
+        let ticks = other.as_micros();
+
+        Some(Instant(self.0.checked_add(ticks.try_into().ok()?)?))
+    }
+
+    pub fn checked_sub_duration(&self, other: &Duration) -> Option<Instant> {
+        // `SYSTIM` is measured in microseconds
+        let ticks = other.as_micros();
+
+        Some(Instant(self.0.checked_sub(ticks.try_into().ok()?)?))
+    }
+}
+
 #[derive(Copy, Clone, PartialEq, Eq, PartialOrd, Ord, Debug, Hash)]
 pub struct SystemTime(abi::time_t);
 

From 963f6029ce51ce1b0654620b80d7f8cb089b3142 Mon Sep 17 00:00:00 2001
From: joboet <jonasboettiger@icloud.com>
Date: Thu, 15 Jan 2026 14:53:52 +0100
Subject: [PATCH 60/97] std: move time implementations to `sys` (UEFI)

Next up: UEFI. Unfortunately the time conversion internals are also required by
the filesystem code, so I've left them in the PAL. The `Instant` internals
however are only used for the `Instant` implementation, so I've moved them to
`sys` (for now).
---
 library/std/src/sys/fs/uefi.rs                |   7 +-
 library/std/src/sys/pal/uefi/mod.rs           |   2 +-
 library/std/src/sys/pal/uefi/system_time.rs   | 151 +++++++++++++++
 library/std/src/sys/time/mod.rs               |   4 +
 .../sys/{pal/uefi/time.rs => time/uefi.rs}    | 172 +-----------------
 5 files changed, 168 insertions(+), 168 deletions(-)
 create mode 100644 library/std/src/sys/pal/uefi/system_time.rs
 rename library/std/src/sys/{pal/uefi/time.rs => time/uefi.rs} (52%)

diff --git a/library/std/src/sys/fs/uefi.rs b/library/std/src/sys/fs/uefi.rs
index a1bb0c6e828b..8135519317a0 100644
--- a/library/std/src/sys/fs/uefi.rs
+++ b/library/std/src/sys/fs/uefi.rs
@@ -580,7 +580,8 @@ mod uefi_fs {
     use crate::path::Path;
     use crate::ptr::NonNull;
     use crate::sys::pal::helpers::{self, UefiBox};
-    use crate::sys::time::{self, SystemTime};
+    use crate::sys::pal::system_time;
+    use crate::sys::time::SystemTime;
 
     pub(crate) struct File {
         protocol: NonNull<file::Protocol>,
@@ -879,7 +880,7 @@ mod uefi_fs {
     /// conversion to SystemTime, we use the current time to get the timezone in such cases.
     pub(crate) fn uefi_to_systemtime(mut time: r_efi::efi::Time) -> Option<SystemTime> {
         time.timezone = if time.timezone == r_efi::efi::UNSPECIFIED_TIMEZONE {
-            time::system_time_internal::now().timezone
+            system_time::now().timezone
         } else {
             time.timezone
         };
@@ -888,7 +889,7 @@ mod uefi_fs {
 
     /// Convert to UEFI Time with the current timezone.
     pub(crate) fn systemtime_to_uefi(time: SystemTime) -> r_efi::efi::Time {
-        let now = time::system_time_internal::now();
+        let now = system_time::now();
         time.to_uefi_loose(now.timezone, now.daylight)
     }
 
diff --git a/library/std/src/sys/pal/uefi/mod.rs b/library/std/src/sys/pal/uefi/mod.rs
index b181d78c2345..e4a8f50e4274 100644
--- a/library/std/src/sys/pal/uefi/mod.rs
+++ b/library/std/src/sys/pal/uefi/mod.rs
@@ -15,7 +15,7 @@
 
 pub mod helpers;
 pub mod os;
-pub mod time;
+pub mod system_time;
 
 #[cfg(test)]
 mod tests;
diff --git a/library/std/src/sys/pal/uefi/system_time.rs b/library/std/src/sys/pal/uefi/system_time.rs
new file mode 100644
index 000000000000..557a49b27c2d
--- /dev/null
+++ b/library/std/src/sys/pal/uefi/system_time.rs
@@ -0,0 +1,151 @@
+use r_efi::efi::{RuntimeServices, Time};
+
+use super::helpers;
+use crate::mem::MaybeUninit;
+use crate::ptr::NonNull;
+use crate::time::Duration;
+
+const SECS_IN_MINUTE: u64 = 60;
+const SECS_IN_HOUR: u64 = SECS_IN_MINUTE * 60;
+const SECS_IN_DAY: u64 = SECS_IN_HOUR * 24;
+const SYSTEMTIME_TIMEZONE: i64 = -1440 * SECS_IN_MINUTE as i64;
+
+pub(crate) fn now() -> Time {
+    let runtime_services: NonNull<RuntimeServices> =
+        helpers::runtime_services().expect("Runtime services are not available");
+    let mut t: MaybeUninit<Time> = MaybeUninit::uninit();
+    let r =
+        unsafe { ((*runtime_services.as_ptr()).get_time)(t.as_mut_ptr(), crate::ptr::null_mut()) };
+    if r.is_error() {
+        panic!("time not implemented on this platform");
+    }
+
+    unsafe { t.assume_init() }
+}
+
+/// This algorithm is a modified form of the one described in the post
+/// https://blog.reverberate.org/2020/05/12/optimizing-date-algorithms.html
+///
+/// The changes are to use 1900-01-01-00:00:00 with timezone -1440 as anchor instead of UNIX
+/// epoch used in the original algorithm.
+pub(crate) const fn from_uefi(t: &Time) -> Option<Duration> {
+    if !(t.month <= 12
+        && t.month != 0
+        && t.year >= 1900
+        && t.year <= 9999
+        && t.day <= 31
+        && t.day != 0
+        && t.second < 60
+        && t.minute <= 60
+        && t.hour < 24
+        && t.nanosecond < 1_000_000_000
+        && ((t.timezone <= 1440 && t.timezone >= -1440)
+            || t.timezone == r_efi::efi::UNSPECIFIED_TIMEZONE))
+    {
+        return None;
+    }
+
+    const YEAR_BASE: u32 = 4800; /* Before min year, multiple of 400. */
+
+    // Calculate the number of days since 1/1/1900. This is the earliest supported date in UEFI
+    // time.
+    // Use 1 March as the start
+    let (m_adj, overflow): (u32, bool) = (t.month as u32).overflowing_sub(3);
+    let (carry, adjust): (u32, u32) = if overflow { (1, 12) } else { (0, 0) };
+    let y_adj: u32 = (t.year as u32) + YEAR_BASE - carry;
+    let month_days: u32 = (m_adj.wrapping_add(adjust) * 62719 + 769) / 2048;
+    let leap_days: u32 = y_adj / 4 - y_adj / 100 + y_adj / 400;
+    let days: u32 = y_adj * 365 + leap_days + month_days + (t.day as u32 - 1) - 2447065;
+
+    let localtime_epoch: u64 = (days as u64) * SECS_IN_DAY
+        + (t.second as u64)
+        + (t.minute as u64) * SECS_IN_MINUTE
+        + (t.hour as u64) * SECS_IN_HOUR;
+
+    let normalized_timezone = if t.timezone == r_efi::efi::UNSPECIFIED_TIMEZONE {
+        -SYSTEMTIME_TIMEZONE
+    } else {
+        (t.timezone as i64) * SECS_IN_MINUTE as i64 - SYSTEMTIME_TIMEZONE
+    };
+
+    // Calculate the offset from 1/1/1900 at timezone -1440 min
+    let epoch = localtime_epoch.checked_add_signed(normalized_timezone).unwrap();
+
+    Some(Duration::new(epoch, t.nanosecond))
+}
+
+/// This algorithm is a modified version of the one described in the post:
+/// https://howardhinnant.github.io/date_algorithms.html#clive_from_days
+///
+/// The changes are to use 1900-01-01-00:00:00 with timezone -1440 as anchor instead of UNIX
+/// epoch used in the original algorithm.
+pub(crate) const fn to_uefi(dur: &Duration, timezone: i16, daylight: u8) -> Result<Time, i16> {
+    const MIN_IN_HOUR: u64 = 60;
+    const MIN_IN_DAY: u64 = MIN_IN_HOUR * 24;
+
+    // Check timezone validity
+    assert!(timezone <= 1440 && timezone >= -1440);
+
+    // Convert to seconds since 1900-01-01-00:00:00 in timezone.
+    let Some(secs) = dur
+        .as_secs()
+        .checked_add_signed(SYSTEMTIME_TIMEZONE - (timezone as i64 * SECS_IN_MINUTE as i64))
+    else {
+        // If the current timezone cannot be used, find the closest timezone that will allow the
+        // conversion to succeed.
+        let new_tz = (dur.as_secs() / SECS_IN_MINUTE) as i16
+            + (SYSTEMTIME_TIMEZONE / SECS_IN_MINUTE as i64) as i16;
+        return Err(new_tz);
+    };
+
+    let days = secs / SECS_IN_DAY;
+    let remaining_secs = secs % SECS_IN_DAY;
+
+    let z = days + 693901;
+    let era = z / 146097;
+    let doe = z - (era * 146097);
+    let yoe = (doe - doe / 1460 + doe / 36524 - doe / 146096) / 365;
+    let mut y = yoe + era * 400;
+    let doy = doe - (365 * yoe + yoe / 4 - yoe / 100);
+    let mp = (5 * doy + 2) / 153;
+    let d = doy - (153 * mp + 2) / 5 + 1;
+    let m = if mp < 10 { mp + 3 } else { mp - 9 };
+
+    if m <= 2 {
+        y += 1;
+    }
+
+    let hour = (remaining_secs / SECS_IN_HOUR) as u8;
+    let minute = ((remaining_secs % SECS_IN_HOUR) / SECS_IN_MINUTE) as u8;
+    let second = (remaining_secs % SECS_IN_MINUTE) as u8;
+
+    // At this point, invalid time will be greater than MAX representable time. It cannot be less
+    // than minimum time since we already take care of that case above.
+    if y <= 9999 {
+        Ok(Time {
+            year: y as u16,
+            month: m as u8,
+            day: d as u8,
+            hour,
+            minute,
+            second,
+            nanosecond: dur.subsec_nanos(),
+            timezone,
+            daylight,
+            pad1: 0,
+            pad2: 0,
+        })
+    } else {
+        assert!(y == 10000);
+        assert!(m == 1);
+
+        let delta = ((d - 1) as u64 * MIN_IN_DAY
+            + hour as u64 * MIN_IN_HOUR
+            + minute as u64
+            + if second == 0 { 0 } else { 1 }) as i16;
+        let new_tz = timezone + delta;
+
+        assert!(new_tz <= 1440 && new_tz >= -1440);
+        Err(new_tz)
+    }
+}
diff --git a/library/std/src/sys/time/mod.rs b/library/std/src/sys/time/mod.rs
index e5b9a3a057f0..0275c91918fe 100644
--- a/library/std/src/sys/time/mod.rs
+++ b/library/std/src/sys/time/mod.rs
@@ -10,6 +10,10 @@ cfg_select! {
         mod solid;
         use solid as imp;
     }
+    target_os = "uefi" => {
+        mod uefi;
+        use uefi as imp;
+    }
     target_os = "vexos" => {
         mod vexos;
         #[expect(unused)]
diff --git a/library/std/src/sys/pal/uefi/time.rs b/library/std/src/sys/time/uefi.rs
similarity index 52%
rename from library/std/src/sys/pal/uefi/time.rs
rename to library/std/src/sys/time/uefi.rs
index 3dccd03ff3fc..5a7eab9031ec 100644
--- a/library/std/src/sys/pal/uefi/time.rs
+++ b/library/std/src/sys/time/uefi.rs
@@ -1,7 +1,6 @@
+use crate::sys::pal::system_time;
 use crate::time::Duration;
 
-const SECS_IN_MINUTE: u64 = 60;
-
 #[derive(Copy, Clone, PartialEq, Eq, PartialOrd, Ord, Debug, Hash)]
 pub struct Instant(Duration);
 
@@ -88,7 +87,7 @@ impl SystemTime {
     .unwrap();
 
     pub(crate) const fn from_uefi(t: r_efi::efi::Time) -> Option<Self> {
-        match system_time_internal::from_uefi(&t) {
+        match system_time::from_uefi(&t) {
             Some(x) => Some(Self(x)),
             None => None,
         }
@@ -99,12 +98,12 @@ impl SystemTime {
         timezone: i16,
         daylight: u8,
     ) -> Result<r_efi::efi::Time, i16> {
-        // system_time_internal::to_uefi requires a valid timezone. In case of unspecified timezone,
+        // system_time::to_uefi requires a valid timezone. In case of unspecified timezone,
         // we just pass 0 since it is assumed that no timezone related adjustments are required.
         if timezone == r_efi::efi::UNSPECIFIED_TIMEZONE {
-            system_time_internal::to_uefi(&self.0, 0, daylight)
+            system_time::to_uefi(&self.0, 0, daylight)
         } else {
-            system_time_internal::to_uefi(&self.0, timezone, daylight)
+            system_time::to_uefi(&self.0, timezone, daylight)
         }
     }
 
@@ -118,8 +117,7 @@ impl SystemTime {
     }
 
     pub fn now() -> SystemTime {
-        Self::from_uefi(system_time_internal::now())
-            .expect("time incorrectly implemented on this platform")
+        Self::from_uefi(system_time::now()).expect("time incorrectly implemented on this platform")
     }
 
     pub fn sub_time(&self, other: &SystemTime) -> Result<Duration, Duration> {
@@ -138,169 +136,15 @@ impl SystemTime {
     }
 }
 
-pub(crate) mod system_time_internal {
-    use r_efi::efi::{RuntimeServices, Time};
-
-    use super::super::helpers;
-    use super::*;
-    use crate::mem::MaybeUninit;
-    use crate::ptr::NonNull;
-
-    const SECS_IN_HOUR: u64 = SECS_IN_MINUTE * 60;
-    const SECS_IN_DAY: u64 = SECS_IN_HOUR * 24;
-    const SYSTEMTIME_TIMEZONE: i64 = -1440 * SECS_IN_MINUTE as i64;
-
-    pub(crate) fn now() -> Time {
-        let runtime_services: NonNull<RuntimeServices> =
-            helpers::runtime_services().expect("Runtime services are not available");
-        let mut t: MaybeUninit<Time> = MaybeUninit::uninit();
-        let r = unsafe {
-            ((*runtime_services.as_ptr()).get_time)(t.as_mut_ptr(), crate::ptr::null_mut())
-        };
-        if r.is_error() {
-            panic!("time not implemented on this platform");
-        }
-
-        unsafe { t.assume_init() }
-    }
-
-    /// This algorithm is a modified form of the one described in the post
-    /// https://blog.reverberate.org/2020/05/12/optimizing-date-algorithms.html
-    ///
-    /// The changes are to use 1900-01-01-00:00:00 with timezone -1440 as anchor instead of UNIX
-    /// epoch used in the original algorithm.
-    pub(crate) const fn from_uefi(t: &Time) -> Option<Duration> {
-        if !(t.month <= 12
-            && t.month != 0
-            && t.year >= 1900
-            && t.year <= 9999
-            && t.day <= 31
-            && t.day != 0
-            && t.second < 60
-            && t.minute <= 60
-            && t.hour < 24
-            && t.nanosecond < 1_000_000_000
-            && ((t.timezone <= 1440 && t.timezone >= -1440)
-                || t.timezone == r_efi::efi::UNSPECIFIED_TIMEZONE))
-        {
-            return None;
-        }
-
-        const YEAR_BASE: u32 = 4800; /* Before min year, multiple of 400. */
-
-        // Calculate the number of days since 1/1/1900. This is the earliest supported date in UEFI
-        // time.
-        // Use 1 March as the start
-        let (m_adj, overflow): (u32, bool) = (t.month as u32).overflowing_sub(3);
-        let (carry, adjust): (u32, u32) = if overflow { (1, 12) } else { (0, 0) };
-        let y_adj: u32 = (t.year as u32) + YEAR_BASE - carry;
-        let month_days: u32 = (m_adj.wrapping_add(adjust) * 62719 + 769) / 2048;
-        let leap_days: u32 = y_adj / 4 - y_adj / 100 + y_adj / 400;
-        let days: u32 = y_adj * 365 + leap_days + month_days + (t.day as u32 - 1) - 2447065;
-
-        let localtime_epoch: u64 = (days as u64) * SECS_IN_DAY
-            + (t.second as u64)
-            + (t.minute as u64) * SECS_IN_MINUTE
-            + (t.hour as u64) * SECS_IN_HOUR;
-
-        let normalized_timezone = if t.timezone == r_efi::efi::UNSPECIFIED_TIMEZONE {
-            -SYSTEMTIME_TIMEZONE
-        } else {
-            (t.timezone as i64) * SECS_IN_MINUTE as i64 - SYSTEMTIME_TIMEZONE
-        };
-
-        // Calculate the offset from 1/1/1900 at timezone -1440 min
-        let epoch = localtime_epoch.checked_add_signed(normalized_timezone).unwrap();
-
-        Some(Duration::new(epoch, t.nanosecond))
-    }
-
-    /// This algorithm is a modified version of the one described in the post:
-    /// https://howardhinnant.github.io/date_algorithms.html#clive_from_days
-    ///
-    /// The changes are to use 1900-01-01-00:00:00 with timezone -1440 as anchor instead of UNIX
-    /// epoch used in the original algorithm.
-    pub(crate) const fn to_uefi(dur: &Duration, timezone: i16, daylight: u8) -> Result<Time, i16> {
-        const MIN_IN_HOUR: u64 = 60;
-        const MIN_IN_DAY: u64 = MIN_IN_HOUR * 24;
-
-        // Check timezone validity
-        assert!(timezone <= 1440 && timezone >= -1440);
-
-        // Convert to seconds since 1900-01-01-00:00:00 in timezone.
-        let Some(secs) = dur
-            .as_secs()
-            .checked_add_signed(SYSTEMTIME_TIMEZONE - (timezone as i64 * SECS_IN_MINUTE as i64))
-        else {
-            // If the current timezone cannot be used, find the closest timezone that will allow the
-            // conversion to succeed.
-            let new_tz = (dur.as_secs() / SECS_IN_MINUTE) as i16
-                + (SYSTEMTIME_TIMEZONE / SECS_IN_MINUTE as i64) as i16;
-            return Err(new_tz);
-        };
-
-        let days = secs / SECS_IN_DAY;
-        let remaining_secs = secs % SECS_IN_DAY;
-
-        let z = days + 693901;
-        let era = z / 146097;
-        let doe = z - (era * 146097);
-        let yoe = (doe - doe / 1460 + doe / 36524 - doe / 146096) / 365;
-        let mut y = yoe + era * 400;
-        let doy = doe - (365 * yoe + yoe / 4 - yoe / 100);
-        let mp = (5 * doy + 2) / 153;
-        let d = doy - (153 * mp + 2) / 5 + 1;
-        let m = if mp < 10 { mp + 3 } else { mp - 9 };
-
-        if m <= 2 {
-            y += 1;
-        }
-
-        let hour = (remaining_secs / SECS_IN_HOUR) as u8;
-        let minute = ((remaining_secs % SECS_IN_HOUR) / SECS_IN_MINUTE) as u8;
-        let second = (remaining_secs % SECS_IN_MINUTE) as u8;
-
-        // At this point, invalid time will be greater than MAX representable time. It cannot be less
-        // than minimum time since we already take care of that case above.
-        if y <= 9999 {
-            Ok(Time {
-                year: y as u16,
-                month: m as u8,
-                day: d as u8,
-                hour,
-                minute,
-                second,
-                nanosecond: dur.subsec_nanos(),
-                timezone,
-                daylight,
-                pad1: 0,
-                pad2: 0,
-            })
-        } else {
-            assert!(y == 10000);
-            assert!(m == 1);
-
-            let delta = ((d - 1) as u64 * MIN_IN_DAY
-                + hour as u64 * MIN_IN_HOUR
-                + minute as u64
-                + if second == 0 { 0 } else { 1 }) as i16;
-            let new_tz = timezone + delta;
-
-            assert!(new_tz <= 1440 && new_tz >= -1440);
-            Err(new_tz)
-        }
-    }
-}
-
-pub(crate) mod instant_internal {
+mod instant_internal {
     use r_efi::protocols::timestamp;
 
-    use super::super::helpers;
     use super::*;
     use crate::mem::MaybeUninit;
     use crate::ptr::NonNull;
     use crate::sync::atomic::{Atomic, AtomicPtr, Ordering};
     use crate::sys::helpers::mul_div_u64;
+    use crate::sys::pal::helpers;
 
     const NS_PER_SEC: u64 = 1_000_000_000;
 

From 6cb343bfb2a5b9000cbccaa521f71a89e4a958c4 Mon Sep 17 00:00:00 2001
From: joboet <jonasboettiger@icloud.com>
Date: Thu, 15 Jan 2026 15:09:14 +0100
Subject: [PATCH 61/97] std: move time implementations to `sys` (Windows)

Windows has a similar problem as UEFI: some internals are also used for
implementing other things. Thus I've left everything except for the actual
`Instant` and `SystemTime` implementations inside the PAL.

I've also taken the liberty of improving the code clarity a bit: there were a
number of manual `SystemTime` conversions (including one that masked an `i64`
to 32-bits before casting to `u32`, yikes) that now just call `from_intervals`.
Also, defining a `PerformanceCounterInstant` just to convert it to a regular
`Instant` immediately doesn't really make sense to me. I've thus changed the
`perf_counter` module to contain only free functions that wrap system
functionality. The actual conversion now happens in `Instant::now`.
---
 library/std/src/sys/pal/windows/time.rs | 215 +++---------------------
 library/std/src/sys/time/mod.rs         |   4 +
 library/std/src/sys/time/windows.rs     | 156 +++++++++++++++++
 3 files changed, 182 insertions(+), 193 deletions(-)
 create mode 100644 library/std/src/sys/time/windows.rs

diff --git a/library/std/src/sys/pal/windows/time.rs b/library/std/src/sys/pal/windows/time.rs
index a555b2b54623..b4b1d50a8889 100644
--- a/library/std/src/sys/pal/windows/time.rs
+++ b/library/std/src/sys/pal/windows/time.rs
@@ -1,170 +1,12 @@
-use core::hash::{Hash, Hasher};
-use core::ops::Neg;
-
-use crate::cmp::Ordering;
+use crate::ops::Neg;
 use crate::ptr::null;
-use crate::sys::{IntoInner, c};
+use crate::sys::pal::c;
 use crate::time::Duration;
-use crate::{fmt, mem};
 
 const NANOS_PER_SEC: u64 = 1_000_000_000;
-const INTERVALS_PER_SEC: u64 = NANOS_PER_SEC / 100;
+pub const INTERVALS_PER_SEC: u64 = NANOS_PER_SEC / 100;
 
-#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd, Debug, Hash)]
-pub struct Instant {
-    // This duration is relative to an arbitrary microsecond epoch
-    // from the winapi QueryPerformanceCounter function.
-    t: Duration,
-}
-
-#[derive(Copy, Clone)]
-pub struct SystemTime {
-    t: c::FILETIME,
-}
-
-const INTERVALS_TO_UNIX_EPOCH: u64 = 11_644_473_600 * INTERVALS_PER_SEC;
-
-pub const UNIX_EPOCH: SystemTime = SystemTime {
-    t: c::FILETIME {
-        dwLowDateTime: INTERVALS_TO_UNIX_EPOCH as u32,
-        dwHighDateTime: (INTERVALS_TO_UNIX_EPOCH >> 32) as u32,
-    },
-};
-
-impl Instant {
-    pub fn now() -> Instant {
-        // High precision timing on windows operates in "Performance Counter"
-        // units, as returned by the WINAPI QueryPerformanceCounter function.
-        // These relate to seconds by a factor of QueryPerformanceFrequency.
-        // In order to keep unit conversions out of normal interval math, we
-        // measure in QPC units and immediately convert to nanoseconds.
-        perf_counter::PerformanceCounterInstant::now().into()
-    }
-
-    pub fn checked_sub_instant(&self, other: &Instant) -> Option<Duration> {
-        // On windows there's a threshold below which we consider two timestamps
-        // equivalent due to measurement error. For more details + doc link,
-        // check the docs on epsilon.
-        let epsilon = perf_counter::PerformanceCounterInstant::epsilon();
-        if other.t > self.t && other.t - self.t <= epsilon {
-            Some(Duration::new(0, 0))
-        } else {
-            self.t.checked_sub(other.t)
-        }
-    }
-
-    pub fn checked_add_duration(&self, other: &Duration) -> Option<Instant> {
-        Some(Instant { t: self.t.checked_add(*other)? })
-    }
-
-    pub fn checked_sub_duration(&self, other: &Duration) -> Option<Instant> {
-        Some(Instant { t: self.t.checked_sub(*other)? })
-    }
-}
-
-impl SystemTime {
-    pub const MAX: SystemTime = SystemTime {
-        t: c::FILETIME {
-            dwLowDateTime: (i64::MAX & 0xFFFFFFFF) as u32,
-            dwHighDateTime: (i64::MAX >> 32) as u32,
-        },
-    };
-
-    pub const MIN: SystemTime =
-        SystemTime { t: c::FILETIME { dwLowDateTime: 0, dwHighDateTime: 0 } };
-
-    pub fn now() -> SystemTime {
-        unsafe {
-            let mut t: SystemTime = mem::zeroed();
-            c::GetSystemTimePreciseAsFileTime(&mut t.t);
-            t
-        }
-    }
-
-    fn from_intervals(intervals: i64) -> SystemTime {
-        SystemTime {
-            t: c::FILETIME {
-                dwLowDateTime: intervals as u32,
-                dwHighDateTime: (intervals >> 32) as u32,
-            },
-        }
-    }
-
-    fn intervals(&self) -> i64 {
-        (self.t.dwLowDateTime as i64) | ((self.t.dwHighDateTime as i64) << 32)
-    }
-
-    pub fn sub_time(&self, other: &SystemTime) -> Result<Duration, Duration> {
-        let me = self.intervals();
-        let other = other.intervals();
-        if me >= other {
-            Ok(intervals2dur((me - other) as u64))
-        } else {
-            Err(intervals2dur((other - me) as u64))
-        }
-    }
-
-    pub fn checked_add_duration(&self, other: &Duration) -> Option<SystemTime> {
-        let intervals = self.intervals().checked_add(checked_dur2intervals(other)?)?;
-        Some(SystemTime::from_intervals(intervals))
-    }
-
-    pub fn checked_sub_duration(&self, other: &Duration) -> Option<SystemTime> {
-        // Windows does not support times before 1601, hence why we don't
-        // support negatives. In order to tackle this, we try to convert the
-        // resulting value into an u64, which should obviously fail in the case
-        // that the value is below zero.
-        let intervals: u64 =
-            self.intervals().checked_sub(checked_dur2intervals(other)?)?.try_into().ok()?;
-        Some(SystemTime::from_intervals(intervals as i64))
-    }
-}
-
-impl PartialEq for SystemTime {
-    fn eq(&self, other: &SystemTime) -> bool {
-        self.intervals() == other.intervals()
-    }
-}
-
-impl Eq for SystemTime {}
-
-impl PartialOrd for SystemTime {
-    fn partial_cmp(&self, other: &SystemTime) -> Option<Ordering> {
-        Some(self.cmp(other))
-    }
-}
-
-impl Ord for SystemTime {
-    fn cmp(&self, other: &SystemTime) -> Ordering {
-        self.intervals().cmp(&other.intervals())
-    }
-}
-
-impl fmt::Debug for SystemTime {
-    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
-        f.debug_struct("SystemTime").field("intervals", &self.intervals()).finish()
-    }
-}
-
-impl From<c::FILETIME> for SystemTime {
-    fn from(t: c::FILETIME) -> SystemTime {
-        SystemTime { t }
-    }
-}
-
-impl IntoInner<c::FILETIME> for SystemTime {
-    fn into_inner(self) -> c::FILETIME {
-        self.t
-    }
-}
-
-impl Hash for SystemTime {
-    fn hash<H: Hasher>(&self, state: &mut H) {
-        self.intervals().hash(state)
-    }
-}
-
-fn checked_dur2intervals(dur: &Duration) -> Option<i64> {
+pub fn checked_dur2intervals(dur: &Duration) -> Option<i64> {
     dur.as_secs()
         .checked_mul(INTERVALS_PER_SEC)?
         .checked_add(dur.subsec_nanos() as u64 / 100)?
@@ -172,43 +14,23 @@ fn checked_dur2intervals(dur: &Duration) -> Option<i64> {
         .ok()
 }
 
-fn intervals2dur(intervals: u64) -> Duration {
+pub fn intervals2dur(intervals: u64) -> Duration {
     Duration::new(intervals / INTERVALS_PER_SEC, ((intervals % INTERVALS_PER_SEC) * 100) as u32)
 }
 
-mod perf_counter {
+pub mod perf_counter {
     use super::NANOS_PER_SEC;
     use crate::sync::atomic::{Atomic, AtomicU64, Ordering};
-    use crate::sys::helpers::mul_div_u64;
     use crate::sys::{c, cvt};
     use crate::time::Duration;
 
-    pub struct PerformanceCounterInstant {
-        ts: i64,
-    }
-    impl PerformanceCounterInstant {
-        pub fn now() -> Self {
-            Self { ts: query() }
-        }
-
-        // Per microsoft docs, the margin of error for cross-thread time comparisons
-        // using QueryPerformanceCounter is 1 "tick" -- defined as 1/frequency().
-        // Reference: https://docs.microsoft.com/en-us/windows/desktop/SysInfo
-        //                   /acquiring-high-resolution-time-stamps
-        pub fn epsilon() -> Duration {
-            let epsilon = NANOS_PER_SEC / (frequency() as u64);
-            Duration::from_nanos(epsilon)
-        }
-    }
-    impl From<PerformanceCounterInstant> for super::Instant {
-        fn from(other: PerformanceCounterInstant) -> Self {
-            let freq = frequency() as u64;
-            let instant_nsec = mul_div_u64(other.ts as u64, NANOS_PER_SEC, freq);
-            Self { t: Duration::from_nanos(instant_nsec) }
-        }
+    pub fn now() -> i64 {
+        let mut qpc_value: i64 = 0;
+        cvt(unsafe { c::QueryPerformanceCounter(&mut qpc_value) }).unwrap();
+        qpc_value
     }
 
-    fn frequency() -> i64 {
+    pub fn frequency() -> i64 {
         // Either the cached result of `QueryPerformanceFrequency` or `0` for
         // uninitialized. Storing this as a single `AtomicU64` allows us to use
         // `Relaxed` operations, as we are only interested in the effects on a
@@ -230,10 +52,13 @@ mod perf_counter {
         frequency
     }
 
-    fn query() -> i64 {
-        let mut qpc_value: i64 = 0;
-        cvt(unsafe { c::QueryPerformanceCounter(&mut qpc_value) }).unwrap();
-        qpc_value
+    // Per microsoft docs, the margin of error for cross-thread time comparisons
+    // using QueryPerformanceCounter is 1 "tick" -- defined as 1/frequency().
+    // Reference: https://docs.microsoft.com/en-us/windows/desktop/SysInfo
+    //                   /acquiring-high-resolution-time-stamps
+    pub fn epsilon() -> Duration {
+        let epsilon = NANOS_PER_SEC / (frequency() as u64);
+        Duration::from_nanos(epsilon)
     }
 }
 
@@ -241,6 +66,7 @@ mod perf_counter {
 pub(crate) struct WaitableTimer {
     handle: c::HANDLE,
 }
+
 impl WaitableTimer {
     /// Creates a high-resolution timer. Will fail before Windows 10, version 1803.
     pub fn high_resolution() -> Result<Self, ()> {
@@ -254,6 +80,7 @@ impl WaitableTimer {
         };
         if !handle.is_null() { Ok(Self { handle }) } else { Err(()) }
     }
+
     pub fn set(&self, duration: Duration) -> Result<(), ()> {
         // Convert the Duration to a format similar to FILETIME.
         // Negative values are relative times whereas positive values are absolute.
@@ -262,11 +89,13 @@ impl WaitableTimer {
         let result = unsafe { c::SetWaitableTimer(self.handle, &time, 0, None, null(), c::FALSE) };
         if result != 0 { Ok(()) } else { Err(()) }
     }
+
     pub fn wait(&self) -> Result<(), ()> {
         let result = unsafe { c::WaitForSingleObject(self.handle, c::INFINITE) };
         if result != c::WAIT_FAILED { Ok(()) } else { Err(()) }
     }
 }
+
 impl Drop for WaitableTimer {
     fn drop(&mut self) {
         unsafe { c::CloseHandle(self.handle) };
diff --git a/library/std/src/sys/time/mod.rs b/library/std/src/sys/time/mod.rs
index 0275c91918fe..810d16b19368 100644
--- a/library/std/src/sys/time/mod.rs
+++ b/library/std/src/sys/time/mod.rs
@@ -24,6 +24,10 @@ cfg_select! {
             pub use super::unsupported::{SystemTime, UNIX_EPOCH};
         }
     }
+    target_os = "windows" => {
+        mod windows;
+        use windows as imp;
+    }
     target_os = "xous" => {
         mod xous;
         use xous as imp;
diff --git a/library/std/src/sys/time/windows.rs b/library/std/src/sys/time/windows.rs
new file mode 100644
index 000000000000..2e38dbf5cf28
--- /dev/null
+++ b/library/std/src/sys/time/windows.rs
@@ -0,0 +1,156 @@
+use crate::cmp::Ordering;
+use crate::hash::{Hash, Hasher};
+use crate::sys::helpers::mul_div_u64;
+use crate::sys::pal::time::{
+    INTERVALS_PER_SEC, checked_dur2intervals, intervals2dur, perf_counter,
+};
+use crate::sys::{IntoInner, c};
+use crate::time::Duration;
+use crate::{fmt, mem};
+
+const NANOS_PER_SEC: u64 = 1_000_000_000;
+
+#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd, Debug, Hash)]
+pub struct Instant {
+    // This duration is relative to an arbitrary microsecond epoch
+    // from the winapi QueryPerformanceCounter function.
+    t: Duration,
+}
+
+#[derive(Copy, Clone)]
+pub struct SystemTime {
+    t: c::FILETIME,
+}
+
+pub const UNIX_EPOCH: SystemTime =
+    SystemTime::from_intervals(11_644_473_600 * INTERVALS_PER_SEC as i64);
+
+impl Instant {
+    pub fn now() -> Instant {
+        // High precision timing on windows operates in "Performance Counter"
+        // units, as returned by the WINAPI QueryPerformanceCounter function.
+        // These relate to seconds by a factor of QueryPerformanceFrequency.
+        // In order to keep unit conversions out of normal interval math, we
+        // measure in QPC units and immediately convert to nanoseconds.
+
+        let freq = perf_counter::frequency() as u64;
+        let now = perf_counter::now();
+        let instant_nsec = mul_div_u64(now as u64, NANOS_PER_SEC, freq);
+        Self { t: Duration::from_nanos(instant_nsec) }
+    }
+
+    pub fn checked_sub_instant(&self, other: &Instant) -> Option<Duration> {
+        // On windows there's a threshold below which we consider two timestamps
+        // equivalent due to measurement error. For more details + doc link,
+        // check the docs on epsilon.
+        let epsilon = perf_counter::epsilon();
+        if other.t > self.t && other.t - self.t <= epsilon {
+            Some(Duration::new(0, 0))
+        } else {
+            self.t.checked_sub(other.t)
+        }
+    }
+
+    pub fn checked_add_duration(&self, other: &Duration) -> Option<Instant> {
+        Some(Instant { t: self.t.checked_add(*other)? })
+    }
+
+    pub fn checked_sub_duration(&self, other: &Duration) -> Option<Instant> {
+        Some(Instant { t: self.t.checked_sub(*other)? })
+    }
+}
+
+impl SystemTime {
+    pub const MAX: SystemTime = SystemTime::from_intervals(i64::MAX);
+    pub const MIN: SystemTime = SystemTime::from_intervals(0);
+
+    pub fn now() -> SystemTime {
+        unsafe {
+            let mut t: SystemTime = mem::zeroed();
+            c::GetSystemTimePreciseAsFileTime(&mut t.t);
+            t
+        }
+    }
+
+    const fn from_intervals(intervals: i64) -> SystemTime {
+        SystemTime {
+            t: c::FILETIME {
+                dwLowDateTime: intervals as u32,
+                dwHighDateTime: (intervals >> 32) as u32,
+            },
+        }
+    }
+
+    fn intervals(&self) -> i64 {
+        (self.t.dwLowDateTime as i64) | ((self.t.dwHighDateTime as i64) << 32)
+    }
+
+    pub fn sub_time(&self, other: &SystemTime) -> Result<Duration, Duration> {
+        let me = self.intervals();
+        let other = other.intervals();
+        if me >= other {
+            Ok(intervals2dur((me - other) as u64))
+        } else {
+            Err(intervals2dur((other - me) as u64))
+        }
+    }
+
+    pub fn checked_add_duration(&self, other: &Duration) -> Option<SystemTime> {
+        let intervals = self.intervals().checked_add(checked_dur2intervals(other)?)?;
+        Some(SystemTime::from_intervals(intervals))
+    }
+
+    pub fn checked_sub_duration(&self, other: &Duration) -> Option<SystemTime> {
+        // Windows does not support times before 1601, hence why we don't
+        // support negatives. In order to tackle this, we try to convert the
+        // resulting value into an u64, which should obviously fail in the case
+        // that the value is below zero.
+        let intervals: u64 =
+            self.intervals().checked_sub(checked_dur2intervals(other)?)?.try_into().ok()?;
+        Some(SystemTime::from_intervals(intervals as i64))
+    }
+}
+
+impl PartialEq for SystemTime {
+    fn eq(&self, other: &SystemTime) -> bool {
+        self.intervals() == other.intervals()
+    }
+}
+
+impl Eq for SystemTime {}
+
+impl PartialOrd for SystemTime {
+    fn partial_cmp(&self, other: &SystemTime) -> Option<Ordering> {
+        Some(self.cmp(other))
+    }
+}
+
+impl Ord for SystemTime {
+    fn cmp(&self, other: &SystemTime) -> Ordering {
+        self.intervals().cmp(&other.intervals())
+    }
+}
+
+impl fmt::Debug for SystemTime {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        f.debug_struct("SystemTime").field("intervals", &self.intervals()).finish()
+    }
+}
+
+impl From<c::FILETIME> for SystemTime {
+    fn from(t: c::FILETIME) -> SystemTime {
+        SystemTime { t }
+    }
+}
+
+impl IntoInner<c::FILETIME> for SystemTime {
+    fn into_inner(self) -> c::FILETIME {
+        self.t
+    }
+}
+
+impl Hash for SystemTime {
+    fn hash<H: Hasher>(&self, state: &mut H) {
+        self.intervals().hash(state)
+    }
+}

From 05bbfa2593ca5cea5ffb6d53f838bed6f3ec3f46 Mon Sep 17 00:00:00 2001
From: joboet <jonasboettiger@icloud.com>
Date: Thu, 15 Jan 2026 15:17:41 +0100
Subject: [PATCH 62/97] std: move time implementations to `sys` (UNIX)

Now for UNIX: `Timespec` is also used for things like futex or `Condvar`
timeouts, so it stays in the PAL along with some related definitions.
Everything else is `SystemTime`- and `Instant`-specific, and is thus moved to
`sys::time`.
---
 library/std/src/sys/fs/unix.rs       |   4 +-
 library/std/src/sys/pal/unix/time.rs | 151 ++-------------------------
 library/std/src/sys/time/mod.rs      |   4 +
 library/std/src/sys/time/unix.rs     | 141 +++++++++++++++++++++++++
 4 files changed, 154 insertions(+), 146 deletions(-)
 create mode 100644 library/std/src/sys/time/unix.rs

diff --git a/library/std/src/sys/fs/unix.rs b/library/std/src/sys/fs/unix.rs
index ca9d3fd592bf..3ca84db0f47f 100644
--- a/library/std/src/sys/fs/unix.rs
+++ b/library/std/src/sys/fs/unix.rs
@@ -1822,7 +1822,7 @@ impl File {
             _ => {
                 #[cfg(all(target_os = "linux", target_env = "gnu", target_pointer_width = "32", not(target_arch = "riscv32")))]
                 {
-                    use crate::sys::{time::__timespec64, weak::weak};
+                    use crate::sys::pal::{time::__timespec64, weak::weak};
 
                     // Added in glibc 2.34
                     weak!(
@@ -2258,7 +2258,7 @@ fn set_times_impl(p: &CStr, times: FileTimes, follow_symlinks: bool) -> io::Resu
             let flags = if follow_symlinks { 0 } else { libc::AT_SYMLINK_NOFOLLOW };
             #[cfg(all(target_os = "linux", target_env = "gnu", target_pointer_width = "32", not(target_arch = "riscv32")))]
             {
-                use crate::sys::{time::__timespec64, weak::weak};
+                use crate::sys::pal::{time::__timespec64, weak::weak};
 
                 // Added in glibc 2.34
                 weak!(
diff --git a/library/std/src/sys/pal/unix/time.rs b/library/std/src/sys/pal/unix/time.rs
index 0021c013d3d9..fbea94ec84e7 100644
--- a/library/std/src/sys/pal/unix/time.rs
+++ b/library/std/src/sys/pal/unix/time.rs
@@ -1,11 +1,10 @@
 use core::num::niche_types::Nanoseconds;
 
-use crate::sys::AsInner;
+use crate::io;
 use crate::time::Duration;
-use crate::{fmt, io};
 
 const NSEC_PER_SEC: u64 = 1_000_000_000;
-pub const UNIX_EPOCH: SystemTime = SystemTime { t: Timespec::zero() };
+
 #[allow(dead_code)] // Used for pthread condvar timeouts
 pub const TIMESPEC_MAX: libc::timespec =
     libc::timespec { tv_sec: <libc::time_t>::MAX, tv_nsec: 1_000_000_000 - 1 };
@@ -18,60 +17,19 @@ pub(in crate::sys) const TIMESPEC_MAX_CAPPED: libc::timespec = libc::timespec {
     tv_nsec: (u64::MAX % NSEC_PER_SEC) as i64,
 };
 
-#[derive(Copy, Clone, PartialEq, Eq, PartialOrd, Ord, Hash)]
-pub struct SystemTime {
-    pub(crate) t: Timespec,
-}
-
 #[derive(Copy, Clone, PartialEq, Eq, PartialOrd, Ord, Hash)]
 pub(crate) struct Timespec {
-    tv_sec: i64,
-    tv_nsec: Nanoseconds,
-}
-
-impl SystemTime {
-    pub const MAX: SystemTime = SystemTime { t: Timespec::MAX };
-
-    pub const MIN: SystemTime = SystemTime { t: Timespec::MIN };
-
-    #[cfg_attr(any(target_os = "horizon", target_os = "hurd"), allow(unused))]
-    pub fn new(tv_sec: i64, tv_nsec: i64) -> Result<SystemTime, io::Error> {
-        Ok(SystemTime { t: Timespec::new(tv_sec, tv_nsec)? })
-    }
-
-    pub fn now() -> SystemTime {
-        SystemTime { t: Timespec::now(libc::CLOCK_REALTIME) }
-    }
-
-    pub fn sub_time(&self, other: &SystemTime) -> Result<Duration, Duration> {
-        self.t.sub_timespec(&other.t)
-    }
-
-    pub fn checked_add_duration(&self, other: &Duration) -> Option<SystemTime> {
-        Some(SystemTime { t: self.t.checked_add_duration(other)? })
-    }
-
-    pub fn checked_sub_duration(&self, other: &Duration) -> Option<SystemTime> {
-        Some(SystemTime { t: self.t.checked_sub_duration(other)? })
-    }
-}
-
-impl fmt::Debug for SystemTime {
-    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
-        f.debug_struct("SystemTime")
-            .field("tv_sec", &self.t.tv_sec)
-            .field("tv_nsec", &self.t.tv_nsec)
-            .finish()
-    }
+    pub tv_sec: i64,
+    pub tv_nsec: Nanoseconds,
 }
 
 impl Timespec {
-    const MAX: Timespec = unsafe { Self::new_unchecked(i64::MAX, 1_000_000_000 - 1) };
+    pub const MAX: Timespec = unsafe { Self::new_unchecked(i64::MAX, 1_000_000_000 - 1) };
 
     // As described below, on Apple OS, dates before epoch are represented differently.
     // This is not an issue here however, because we are using tv_sec = i64::MIN,
     // which will cause the compatibility wrapper to not be executed at all.
-    const MIN: Timespec = unsafe { Self::new_unchecked(i64::MIN, 0) };
+    pub const MIN: Timespec = unsafe { Self::new_unchecked(i64::MIN, 0) };
 
     const unsafe fn new_unchecked(tv_sec: i64, tv_nsec: i64) -> Timespec {
         Timespec { tv_sec, tv_nsec: unsafe { Nanoseconds::new_unchecked(tv_nsec as u32) } }
@@ -81,7 +39,7 @@ impl Timespec {
         unsafe { Self::new_unchecked(0, 0) }
     }
 
-    const fn new(tv_sec: i64, tv_nsec: i64) -> Result<Timespec, io::Error> {
+    pub const fn new(tv_sec: i64, tv_nsec: i64) -> Result<Timespec, io::Error> {
         // On Apple OS, dates before epoch are represented differently than on other
         // Unix platforms: e.g. 1/10th of a second before epoch is represented as `seconds=-1`
         // and `nanoseconds=100_000_000` on other platforms, but is `seconds=0` and
@@ -263,98 +221,3 @@ impl __timespec64 {
         Self { tv_sec, tv_nsec, _padding: 0 }
     }
 }
-
-#[derive(Copy, Clone, PartialEq, Eq, PartialOrd, Ord, Hash)]
-pub struct Instant {
-    t: Timespec,
-}
-
-impl Instant {
-    // CLOCK_UPTIME_RAW   clock that increments monotonically, in the same man-
-    //                    ner as CLOCK_MONOTONIC_RAW, but that does not incre-
-    //                    ment while the system is asleep.  The returned value
-    //                    is identical to the result of mach_absolute_time()
-    //                    after the appropriate mach_timebase conversion is
-    //                    applied.
-    //
-    // We use `CLOCK_UPTIME_RAW` instead of `CLOCK_MONOTONIC` since
-    // `CLOCK_UPTIME_RAW` is based on `mach_absolute_time`, which is the
-    // clock that all timeouts and deadlines are measured against inside
-    // the kernel.
-    #[cfg(target_vendor = "apple")]
-    pub(crate) const CLOCK_ID: libc::clockid_t = libc::CLOCK_UPTIME_RAW;
-
-    #[cfg(not(target_vendor = "apple"))]
-    pub(crate) const CLOCK_ID: libc::clockid_t = libc::CLOCK_MONOTONIC;
-
-    pub fn now() -> Instant {
-        // https://pubs.opengroup.org/onlinepubs/9799919799/functions/clock_getres.html
-        Instant { t: Timespec::now(Self::CLOCK_ID) }
-    }
-
-    pub fn checked_sub_instant(&self, other: &Instant) -> Option<Duration> {
-        self.t.sub_timespec(&other.t).ok()
-    }
-
-    pub fn checked_add_duration(&self, other: &Duration) -> Option<Instant> {
-        Some(Instant { t: self.t.checked_add_duration(other)? })
-    }
-
-    pub fn checked_sub_duration(&self, other: &Duration) -> Option<Instant> {
-        Some(Instant { t: self.t.checked_sub_duration(other)? })
-    }
-
-    #[cfg_attr(
-        not(target_os = "linux"),
-        allow(unused, reason = "needed by the `sleep_until` on some unix platforms")
-    )]
-    pub(crate) fn into_timespec(self) -> Timespec {
-        self.t
-    }
-
-    /// Returns `self` converted into units of `mach_absolute_time`, or `None`
-    /// if `self` is before the system boot time. If the conversion cannot be
-    /// performed precisely, this ceils the result up to the nearest
-    /// representable value.
-    #[cfg(target_vendor = "apple")]
-    pub fn into_mach_absolute_time_ceil(self) -> Option<u128> {
-        #[repr(C)]
-        struct mach_timebase_info {
-            numer: u32,
-            denom: u32,
-        }
-
-        unsafe extern "C" {
-            unsafe fn mach_timebase_info(info: *mut mach_timebase_info) -> libc::kern_return_t;
-        }
-
-        let secs = u64::try_from(self.t.tv_sec).ok()?;
-
-        let mut timebase = mach_timebase_info { numer: 0, denom: 0 };
-        assert_eq!(unsafe { mach_timebase_info(&mut timebase) }, libc::KERN_SUCCESS);
-
-        // Since `tv_sec` is 64-bit and `tv_nsec` is smaller than 1 billion,
-        // this cannot overflow. The resulting number needs at most 94 bits.
-        let nanos =
-            u128::from(secs) * u128::from(NSEC_PER_SEC) + u128::from(self.t.tv_nsec.as_inner());
-        // This multiplication cannot overflow since multiplying a 94-bit
-        // number by a 32-bit number yields a number that needs at most
-        // 126 bits.
-        Some((nanos * u128::from(timebase.denom)).div_ceil(u128::from(timebase.numer)))
-    }
-}
-
-impl AsInner<Timespec> for Instant {
-    fn as_inner(&self) -> &Timespec {
-        &self.t
-    }
-}
-
-impl fmt::Debug for Instant {
-    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
-        f.debug_struct("Instant")
-            .field("tv_sec", &self.t.tv_sec)
-            .field("tv_nsec", &self.t.tv_nsec)
-            .finish()
-    }
-}
diff --git a/library/std/src/sys/time/mod.rs b/library/std/src/sys/time/mod.rs
index 810d16b19368..3efab78518c2 100644
--- a/library/std/src/sys/time/mod.rs
+++ b/library/std/src/sys/time/mod.rs
@@ -14,6 +14,10 @@ cfg_select! {
         mod uefi;
         use uefi as imp;
     }
+    target_family = "unix" => {
+        mod unix;
+        use unix as imp;
+    }
     target_os = "vexos" => {
         mod vexos;
         #[expect(unused)]
diff --git a/library/std/src/sys/time/unix.rs b/library/std/src/sys/time/unix.rs
new file mode 100644
index 000000000000..21d246bc850a
--- /dev/null
+++ b/library/std/src/sys/time/unix.rs
@@ -0,0 +1,141 @@
+use crate::sys::AsInner;
+use crate::sys::pal::time::Timespec;
+use crate::time::Duration;
+use crate::{fmt, io};
+
+pub const UNIX_EPOCH: SystemTime = SystemTime { t: Timespec::zero() };
+
+#[derive(Copy, Clone, PartialEq, Eq, PartialOrd, Ord, Hash)]
+pub struct SystemTime {
+    pub(crate) t: Timespec,
+}
+
+impl SystemTime {
+    pub const MAX: SystemTime = SystemTime { t: Timespec::MAX };
+
+    pub const MIN: SystemTime = SystemTime { t: Timespec::MIN };
+
+    #[cfg_attr(any(target_os = "horizon", target_os = "hurd"), allow(unused))]
+    pub fn new(tv_sec: i64, tv_nsec: i64) -> Result<SystemTime, io::Error> {
+        Ok(SystemTime { t: Timespec::new(tv_sec, tv_nsec)? })
+    }
+
+    pub fn now() -> SystemTime {
+        SystemTime { t: Timespec::now(libc::CLOCK_REALTIME) }
+    }
+
+    pub fn sub_time(&self, other: &SystemTime) -> Result<Duration, Duration> {
+        self.t.sub_timespec(&other.t)
+    }
+
+    pub fn checked_add_duration(&self, other: &Duration) -> Option<SystemTime> {
+        Some(SystemTime { t: self.t.checked_add_duration(other)? })
+    }
+
+    pub fn checked_sub_duration(&self, other: &Duration) -> Option<SystemTime> {
+        Some(SystemTime { t: self.t.checked_sub_duration(other)? })
+    }
+}
+
+impl fmt::Debug for SystemTime {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        f.debug_struct("SystemTime")
+            .field("tv_sec", &self.t.tv_sec)
+            .field("tv_nsec", &self.t.tv_nsec)
+            .finish()
+    }
+}
+
+#[derive(Copy, Clone, PartialEq, Eq, PartialOrd, Ord, Hash)]
+pub struct Instant {
+    t: Timespec,
+}
+
+impl Instant {
+    // CLOCK_UPTIME_RAW   clock that increments monotonically, in the same man-
+    //                    ner as CLOCK_MONOTONIC_RAW, but that does not incre-
+    //                    ment while the system is asleep.  The returned value
+    //                    is identical to the result of mach_absolute_time()
+    //                    after the appropriate mach_timebase conversion is
+    //                    applied.
+    //
+    // We use `CLOCK_UPTIME_RAW` instead of `CLOCK_MONOTONIC` since
+    // `CLOCK_UPTIME_RAW` is based on `mach_absolute_time`, which is the
+    // clock that all timeouts and deadlines are measured against inside
+    // the kernel.
+    #[cfg(target_vendor = "apple")]
+    pub(crate) const CLOCK_ID: libc::clockid_t = libc::CLOCK_UPTIME_RAW;
+
+    #[cfg(not(target_vendor = "apple"))]
+    pub(crate) const CLOCK_ID: libc::clockid_t = libc::CLOCK_MONOTONIC;
+
+    pub fn now() -> Instant {
+        // https://pubs.opengroup.org/onlinepubs/9799919799/functions/clock_getres.html
+        Instant { t: Timespec::now(Self::CLOCK_ID) }
+    }
+
+    pub fn checked_sub_instant(&self, other: &Instant) -> Option<Duration> {
+        self.t.sub_timespec(&other.t).ok()
+    }
+
+    pub fn checked_add_duration(&self, other: &Duration) -> Option<Instant> {
+        Some(Instant { t: self.t.checked_add_duration(other)? })
+    }
+
+    pub fn checked_sub_duration(&self, other: &Duration) -> Option<Instant> {
+        Some(Instant { t: self.t.checked_sub_duration(other)? })
+    }
+
+    #[cfg_attr(
+        not(target_os = "linux"),
+        allow(unused, reason = "needed by the `sleep_until` on some unix platforms")
+    )]
+    pub(crate) fn into_timespec(self) -> Timespec {
+        self.t
+    }
+
+    /// Returns `self` converted into units of `mach_absolute_time`, or `None`
+    /// if `self` is before the system boot time. If the conversion cannot be
+    /// performed precisely, this ceils the result up to the nearest
+    /// representable value.
+    #[cfg(target_vendor = "apple")]
+    pub fn into_mach_absolute_time_ceil(self) -> Option<u128> {
+        #[repr(C)]
+        struct mach_timebase_info {
+            numer: u32,
+            denom: u32,
+        }
+
+        unsafe extern "C" {
+            unsafe fn mach_timebase_info(info: *mut mach_timebase_info) -> libc::kern_return_t;
+        }
+
+        let secs = u64::try_from(self.t.tv_sec).ok()?;
+
+        let mut timebase = mach_timebase_info { numer: 0, denom: 0 };
+        assert_eq!(unsafe { mach_timebase_info(&mut timebase) }, libc::KERN_SUCCESS);
+
+        // Since `tv_sec` is 64-bit and `tv_nsec` is smaller than 1 billion,
+        // this cannot overflow. The resulting number needs at most 94 bits.
+        let nanos = 1_000_000_000 * u128::from(secs) + u128::from(self.t.tv_nsec.as_inner());
+        // This multiplication cannot overflow since multiplying a 94-bit
+        // number by a 32-bit number yields a number that needs at most
+        // 126 bits.
+        Some((nanos * u128::from(timebase.denom)).div_ceil(u128::from(timebase.numer)))
+    }
+}
+
+impl AsInner<Timespec> for Instant {
+    fn as_inner(&self) -> &Timespec {
+        &self.t
+    }
+}
+
+impl fmt::Debug for Instant {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        f.debug_struct("Instant")
+            .field("tv_sec", &self.t.tv_sec)
+            .field("tv_nsec", &self.t.tv_nsec)
+            .finish()
+    }
+}

From eec058eacc1ba500aba4393dbec47a1acd6e2d2a Mon Sep 17 00:00:00 2001
From: joboet <jonasboettiger@icloud.com>
Date: Thu, 15 Jan 2026 15:21:58 +0100
Subject: [PATCH 63/97] std: move time implementations to `sys` (WASI/TEEOS)

WASI and TEEOS share the UNIX implementation. Since `Timespec` lives in the
PAL, this means that the `#[path]` imports of `unix/time.rs` still remain for
these two, unfortunately. Maybe we'll solve that in the future by always
including the UNIX PAL for these remotely UNIXy platforms. But that's a story
for another time...
---
 library/std/src/sys/pal/teeos/mod.rs |  1 -
 library/std/src/sys/time/mod.rs      | 10 +++++++++-
 library/std/src/sys/time/unix.rs     |  2 +-
 3 files changed, 10 insertions(+), 3 deletions(-)

diff --git a/library/std/src/sys/pal/teeos/mod.rs b/library/std/src/sys/pal/teeos/mod.rs
index d40c10663fd1..f76c26d3c966 100644
--- a/library/std/src/sys/pal/teeos/mod.rs
+++ b/library/std/src/sys/pal/teeos/mod.rs
@@ -7,7 +7,6 @@
 #![allow(dead_code)]
 
 pub mod os;
-#[allow(non_upper_case_globals)]
 #[path = "../unix/time.rs"]
 pub mod time;
 
diff --git a/library/std/src/sys/time/mod.rs b/library/std/src/sys/time/mod.rs
index 3efab78518c2..6cd1850e7cca 100644
--- a/library/std/src/sys/time/mod.rs
+++ b/library/std/src/sys/time/mod.rs
@@ -1,4 +1,8 @@
 cfg_select! {
+    target_os = "hermit" => {
+        mod hermit;
+        use hermit as imp;
+    }
     target_os = "motor" => {
         use moto_rt::time as imp;
     }
@@ -14,7 +18,11 @@ cfg_select! {
         mod uefi;
         use uefi as imp;
     }
-    target_family = "unix" => {
+    any(
+        target_os = "teeos",
+        target_family = "unix",
+        target_os = "wasi",
+    ) => {
         mod unix;
         use unix as imp;
     }
diff --git a/library/std/src/sys/time/unix.rs b/library/std/src/sys/time/unix.rs
index 21d246bc850a..944cb552cad9 100644
--- a/library/std/src/sys/time/unix.rs
+++ b/library/std/src/sys/time/unix.rs
@@ -15,7 +15,7 @@ impl SystemTime {
 
     pub const MIN: SystemTime = SystemTime { t: Timespec::MIN };
 
-    #[cfg_attr(any(target_os = "horizon", target_os = "hurd"), allow(unused))]
+    #[cfg_attr(any(target_os = "horizon", target_os = "hurd", target_os = "teeos"), expect(unused))]
     pub fn new(tv_sec: i64, tv_nsec: i64) -> Result<SystemTime, io::Error> {
         Ok(SystemTime { t: Timespec::new(tv_sec, tv_nsec)? })
     }

From fe51f9debcaf35692bc1760850577f5e6846a009 Mon Sep 17 00:00:00 2001
From: joboet <jonasboettiger@icloud.com>
Date: Thu, 15 Jan 2026 15:25:14 +0100
Subject: [PATCH 64/97] std: move time implementations to `sys` (Hermit)

Last on the list: Hermit. Since I anticipate that Hermit will share the UNIX
implementation in the future, I've left `Timespec` in the PAL to maintain a
similar structure. Also, I noticed that some public `Instant` methods were
redefined on the internal `Instant`. But the networking code can just use the
public `Instant`, so I've removed them.
---
 .../src/sys/net/connection/socket/hermit.rs   |   3 +-
 library/std/src/sys/pal/hermit/time.rs        | 154 ++----------------
 library/std/src/sys/time/hermit.rs            |  63 +++++++
 3 files changed, 75 insertions(+), 145 deletions(-)
 create mode 100644 library/std/src/sys/time/hermit.rs

diff --git a/library/std/src/sys/net/connection/socket/hermit.rs b/library/std/src/sys/net/connection/socket/hermit.rs
index d57a075eb42d..59f515d31aff 100644
--- a/library/std/src/sys/net/connection/socket/hermit.rs
+++ b/library/std/src/sys/net/connection/socket/hermit.rs
@@ -9,10 +9,9 @@ use crate::io::{self, BorrowedBuf, BorrowedCursor, IoSlice, IoSliceMut};
 use crate::net::{Shutdown, SocketAddr};
 use crate::os::hermit::io::{AsFd, AsRawFd, BorrowedFd, FromRawFd, RawFd};
 use crate::sys::fd::FileDesc;
-use crate::sys::time::Instant;
 use crate::sys::{AsInner, FromInner, IntoInner};
 pub use crate::sys::{cvt, cvt_r};
-use crate::time::Duration;
+use crate::time::{Duration, Instant};
 use crate::{cmp, mem};
 
 #[expect(non_camel_case_types)]
diff --git a/library/std/src/sys/pal/hermit/time.rs b/library/std/src/sys/pal/hermit/time.rs
index 734ad2540a18..b9851eb6754d 100644
--- a/library/std/src/sys/pal/hermit/time.rs
+++ b/library/std/src/sys/pal/hermit/time.rs
@@ -1,35 +1,32 @@
-#![allow(dead_code)]
+use hermit_abi::{self, timespec};
 
-use core::hash::{Hash, Hasher};
-
-use super::hermit_abi::{self, CLOCK_MONOTONIC, CLOCK_REALTIME, timespec};
 use crate::cmp::Ordering;
-use crate::ops::{Add, AddAssign, Sub, SubAssign};
+use crate::hash::{Hash, Hasher};
 use crate::time::Duration;
 
 const NSEC_PER_SEC: i32 = 1_000_000_000;
 
 #[derive(Copy, Clone, Debug)]
-struct Timespec {
-    t: timespec,
+pub struct Timespec {
+    pub t: timespec,
 }
 
 impl Timespec {
-    const MAX: Timespec = Self::new(i64::MAX, 1_000_000_000 - 1);
+    pub const MAX: Timespec = Self::new(i64::MAX, 1_000_000_000 - 1);
 
-    const MIN: Timespec = Self::new(i64::MIN, 0);
+    pub const MIN: Timespec = Self::new(i64::MIN, 0);
 
-    const fn zero() -> Timespec {
+    pub const fn zero() -> Timespec {
         Timespec { t: timespec { tv_sec: 0, tv_nsec: 0 } }
     }
 
-    const fn new(tv_sec: i64, tv_nsec: i32) -> Timespec {
+    pub const fn new(tv_sec: i64, tv_nsec: i32) -> Timespec {
         assert!(tv_nsec >= 0 && tv_nsec < NSEC_PER_SEC);
         // SAFETY: The assert above checks tv_nsec is within the valid range
         Timespec { t: timespec { tv_sec, tv_nsec } }
     }
 
-    fn sub_timespec(&self, other: &Timespec) -> Result<Duration, Duration> {
+    pub fn sub_timespec(&self, other: &Timespec) -> Result<Duration, Duration> {
         fn sub_ge_to_unsigned(a: i64, b: i64) -> u64 {
             debug_assert!(a >= b);
             a.wrapping_sub(b).cast_unsigned()
@@ -57,7 +54,7 @@ impl Timespec {
         }
     }
 
-    fn checked_add_duration(&self, other: &Duration) -> Option<Timespec> {
+    pub fn checked_add_duration(&self, other: &Duration) -> Option<Timespec> {
         let mut secs = self.t.tv_sec.checked_add_unsigned(other.as_secs())?;
 
         // Nano calculations can't overflow because nanos are <1B which fit
@@ -70,7 +67,7 @@ impl Timespec {
         Some(Timespec { t: timespec { tv_sec: secs, tv_nsec: nsec as _ } })
     }
 
-    fn checked_sub_duration(&self, other: &Duration) -> Option<Timespec> {
+    pub fn checked_sub_duration(&self, other: &Duration) -> Option<Timespec> {
         let mut secs = self.t.tv_sec.checked_sub_unsigned(other.as_secs())?;
 
         // Similar to above, nanos can't overflow.
@@ -111,132 +108,3 @@ impl Hash for Timespec {
         self.t.tv_nsec.hash(state);
     }
 }
-
-#[derive(Copy, Clone, PartialEq, Eq, PartialOrd, Ord, Debug, Hash)]
-pub struct Instant(Timespec);
-
-impl Instant {
-    pub fn now() -> Instant {
-        let mut time: Timespec = Timespec::zero();
-        let _ = unsafe { hermit_abi::clock_gettime(CLOCK_MONOTONIC, &raw mut time.t) };
-
-        Instant(time)
-    }
-
-    #[stable(feature = "time2", since = "1.8.0")]
-    pub fn elapsed(&self) -> Duration {
-        Instant::now() - *self
-    }
-
-    pub fn duration_since(&self, earlier: Instant) -> Duration {
-        self.checked_duration_since(earlier).unwrap_or_default()
-    }
-
-    pub fn checked_duration_since(&self, earlier: Instant) -> Option<Duration> {
-        self.checked_sub_instant(&earlier)
-    }
-
-    pub fn checked_sub_instant(&self, other: &Instant) -> Option<Duration> {
-        self.0.sub_timespec(&other.0).ok()
-    }
-
-    pub fn checked_add_duration(&self, other: &Duration) -> Option<Instant> {
-        Some(Instant(self.0.checked_add_duration(other)?))
-    }
-
-    pub fn checked_sub_duration(&self, other: &Duration) -> Option<Instant> {
-        Some(Instant(self.0.checked_sub_duration(other)?))
-    }
-
-    pub fn checked_add(&self, duration: Duration) -> Option<Instant> {
-        self.0.checked_add_duration(&duration).map(Instant)
-    }
-
-    pub fn checked_sub(&self, duration: Duration) -> Option<Instant> {
-        self.0.checked_sub_duration(&duration).map(Instant)
-    }
-}
-
-impl Add<Duration> for Instant {
-    type Output = Instant;
-
-    /// # Panics
-    ///
-    /// This function may panic if the resulting point in time cannot be represented by the
-    /// underlying data structure. See [`Instant::checked_add`] for a version without panic.
-    fn add(self, other: Duration) -> Instant {
-        self.checked_add(other).expect("overflow when adding duration to instant")
-    }
-}
-
-impl AddAssign<Duration> for Instant {
-    fn add_assign(&mut self, other: Duration) {
-        *self = *self + other;
-    }
-}
-
-impl Sub<Duration> for Instant {
-    type Output = Instant;
-
-    fn sub(self, other: Duration) -> Instant {
-        self.checked_sub(other).expect("overflow when subtracting duration from instant")
-    }
-}
-
-impl SubAssign<Duration> for Instant {
-    fn sub_assign(&mut self, other: Duration) {
-        *self = *self - other;
-    }
-}
-
-impl Sub<Instant> for Instant {
-    type Output = Duration;
-
-    /// Returns the amount of time elapsed from another instant to this one,
-    /// or zero duration if that instant is later than this one.
-    ///
-    /// # Panics
-    ///
-    /// Previous Rust versions panicked when `other` was later than `self`. Currently this
-    /// method saturates. Future versions may reintroduce the panic in some circumstances.
-    /// See [Monotonicity].
-    ///
-    /// [Monotonicity]: Instant#monotonicity
-    fn sub(self, other: Instant) -> Duration {
-        self.duration_since(other)
-    }
-}
-
-#[derive(Copy, Clone, PartialEq, Eq, PartialOrd, Ord, Hash, Debug)]
-pub struct SystemTime(Timespec);
-
-pub const UNIX_EPOCH: SystemTime = SystemTime(Timespec::zero());
-
-impl SystemTime {
-    pub const MAX: SystemTime = SystemTime(Timespec::MAX);
-
-    pub const MIN: SystemTime = SystemTime(Timespec::MIN);
-
-    pub fn new(tv_sec: i64, tv_nsec: i32) -> SystemTime {
-        SystemTime(Timespec::new(tv_sec, tv_nsec))
-    }
-
-    pub fn now() -> SystemTime {
-        let mut time: Timespec = Timespec::zero();
-        let _ = unsafe { hermit_abi::clock_gettime(CLOCK_REALTIME, &raw mut time.t) };
-
-        SystemTime(time)
-    }
-
-    pub fn sub_time(&self, other: &SystemTime) -> Result<Duration, Duration> {
-        self.0.sub_timespec(&other.0)
-    }
-
-    pub fn checked_add_duration(&self, other: &Duration) -> Option<SystemTime> {
-        Some(SystemTime(self.0.checked_add_duration(other)?))
-    }
-
-    pub fn checked_sub_duration(&self, other: &Duration) -> Option<SystemTime> {
-        Some(SystemTime(self.0.checked_sub_duration(other)?))
-    }
-}
diff --git a/library/std/src/sys/time/hermit.rs b/library/std/src/sys/time/hermit.rs
new file mode 100644
index 000000000000..18ece2e3010d
--- /dev/null
+++ b/library/std/src/sys/time/hermit.rs
@@ -0,0 +1,63 @@
+use hermit_abi::{self, CLOCK_MONOTONIC, CLOCK_REALTIME};
+
+use crate::hash::Hash;
+use crate::sys::pal::time::Timespec;
+use crate::time::Duration;
+
+#[derive(Copy, Clone, PartialEq, Eq, PartialOrd, Ord, Debug, Hash)]
+pub struct Instant(Timespec);
+
+impl Instant {
+    pub fn now() -> Instant {
+        let mut time: Timespec = Timespec::zero();
+        let _ = unsafe { hermit_abi::clock_gettime(CLOCK_MONOTONIC, &raw mut time.t) };
+
+        Instant(time)
+    }
+
+    pub fn checked_sub_instant(&self, other: &Instant) -> Option<Duration> {
+        self.0.sub_timespec(&other.0).ok()
+    }
+
+    pub fn checked_add_duration(&self, other: &Duration) -> Option<Instant> {
+        Some(Instant(self.0.checked_add_duration(other)?))
+    }
+
+    pub fn checked_sub_duration(&self, other: &Duration) -> Option<Instant> {
+        Some(Instant(self.0.checked_sub_duration(other)?))
+    }
+}
+
+#[derive(Copy, Clone, PartialEq, Eq, PartialOrd, Ord, Hash, Debug)]
+pub struct SystemTime(Timespec);
+
+pub const UNIX_EPOCH: SystemTime = SystemTime(Timespec::zero());
+
+impl SystemTime {
+    pub const MAX: SystemTime = SystemTime(Timespec::MAX);
+
+    pub const MIN: SystemTime = SystemTime(Timespec::MIN);
+
+    pub fn new(tv_sec: i64, tv_nsec: i32) -> SystemTime {
+        SystemTime(Timespec::new(tv_sec, tv_nsec))
+    }
+
+    pub fn now() -> SystemTime {
+        let mut time: Timespec = Timespec::zero();
+        let _ = unsafe { hermit_abi::clock_gettime(CLOCK_REALTIME, &raw mut time.t) };
+
+        SystemTime(time)
+    }
+
+    pub fn sub_time(&self, other: &SystemTime) -> Result<Duration, Duration> {
+        self.0.sub_timespec(&other.0)
+    }
+
+    pub fn checked_add_duration(&self, other: &Duration) -> Option<SystemTime> {
+        Some(SystemTime(self.0.checked_add_duration(other)?))
+    }
+
+    pub fn checked_sub_duration(&self, other: &Duration) -> Option<SystemTime> {
+        Some(SystemTime(self.0.checked_sub_duration(other)?))
+    }
+}

From 5a98a51987c1fe3a1f6011754a436d4ca62f3cf0 Mon Sep 17 00:00:00 2001
From: joboet <jonasboettiger@icloud.com>
Date: Fri, 16 Jan 2026 15:19:37 +0100
Subject: [PATCH 65/97] hardcode some Windows constants in miri

The `std` paths are subject to change, but the values themselves will never
change.
---
 src/tools/miri/src/shims/time.rs | 21 +++++++++------------
 1 file changed, 9 insertions(+), 12 deletions(-)

diff --git a/src/tools/miri/src/shims/time.rs b/src/tools/miri/src/shims/time.rs
index c49aa9f20f6c..865a80251e31 100644
--- a/src/tools/miri/src/shims/time.rs
+++ b/src/tools/miri/src/shims/time.rs
@@ -275,26 +275,23 @@ pub trait EvalContextExt<'tcx>: crate::MiriInterpCxExt<'tcx> {
         interp_ok(Scalar::from_i32(-1)) // Return non-zero on success
     }
 
-    #[allow(non_snake_case, clippy::arithmetic_side_effects)]
+    #[allow(clippy::arithmetic_side_effects)]
     fn system_time_since_windows_epoch(&self, time: &SystemTime) -> InterpResult<'tcx, Duration> {
-        let this = self.eval_context_ref();
-
-        let INTERVALS_PER_SEC = this.eval_windows_u64("time", "INTERVALS_PER_SEC");
-        let INTERVALS_TO_UNIX_EPOCH = this.eval_windows_u64("time", "INTERVALS_TO_UNIX_EPOCH");
-        let SECONDS_TO_UNIX_EPOCH = INTERVALS_TO_UNIX_EPOCH / INTERVALS_PER_SEC;
+        // The amount of seconds between 1601/1/1 and 1970/1/1.
+        // See https://learn.microsoft.com/en-us/windows/win32/sysinfo/converting-a-time-t-value-to-a-file-time
+        // (just divide by the number of 100 ns intervals per second).
+        const SECONDS_TO_UNIX_EPOCH: u64 = 11_644_473_600;
 
         interp_ok(system_time_to_duration(time)? + Duration::from_secs(SECONDS_TO_UNIX_EPOCH))
     }
 
     #[allow(non_snake_case, clippy::arithmetic_side_effects)]
     fn windows_ticks_for(&self, duration: Duration) -> InterpResult<'tcx, u64> {
-        let this = self.eval_context_ref();
+        // 1 interval = 100 ns.
+        // See https://learn.microsoft.com/en-us/windows/win32/api/minwinbase/ns-minwinbase-filetime
+        const NANOS_PER_INTERVAL: u128 = 100;
 
-        let NANOS_PER_SEC = this.eval_windows_u64("time", "NANOS_PER_SEC");
-        let INTERVALS_PER_SEC = this.eval_windows_u64("time", "INTERVALS_PER_SEC");
-        let NANOS_PER_INTERVAL = NANOS_PER_SEC / INTERVALS_PER_SEC;
-
-        let ticks = u64::try_from(duration.as_nanos() / u128::from(NANOS_PER_INTERVAL))
+        let ticks = u64::try_from(duration.as_nanos() / NANOS_PER_INTERVAL)
             .map_err(|_| err_unsup_format!("programs running more than 2^64 Windows ticks after the Windows epoch are not supported"))?;
         interp_ok(ticks)
     }

From 89d7695040cb21b5c29d4f2a5e69681f4b192172 Mon Sep 17 00:00:00 2001
From: Zalathar <Zalathar@users.noreply.github.com>
Date: Sun, 25 Jan 2026 13:48:39 +1100
Subject: [PATCH 66/97] Rename `DynamicQuery` to `QueryVTable`

---
 compiler/rustc_middle/src/query/mod.rs      |  2 +-
 compiler/rustc_middle/src/query/plumbing.rs | 16 ++++++---
 compiler/rustc_query_impl/src/lib.rs        | 39 ++++++++++-----------
 compiler/rustc_query_impl/src/plumbing.rs   | 14 ++++----
 4 files changed, 38 insertions(+), 33 deletions(-)

diff --git a/compiler/rustc_middle/src/query/mod.rs b/compiler/rustc_middle/src/query/mod.rs
index 9d17c998a8f2..901a023c4f30 100644
--- a/compiler/rustc_middle/src/query/mod.rs
+++ b/compiler/rustc_middle/src/query/mod.rs
@@ -122,7 +122,7 @@ use crate::mir::mono::{
     CodegenUnit, CollectionMode, MonoItem, MonoItemPartitions, NormalizationErrorInMono,
 };
 use crate::query::erase::{Erase, erase, restore};
-use crate::query::plumbing::{CyclePlaceholder, DynamicQuery};
+use crate::query::plumbing::CyclePlaceholder;
 use crate::traits::query::{
     CanonicalAliasGoal, CanonicalDropckOutlivesGoal, CanonicalImpliedOutlivesBoundsGoal,
     CanonicalMethodAutoderefStepsGoal, CanonicalPredicateGoal, CanonicalTypeOpAscribeUserTypeGoal,
diff --git a/compiler/rustc_middle/src/query/plumbing.rs b/compiler/rustc_middle/src/query/plumbing.rs
index 9ee8d743e64a..0e536352563f 100644
--- a/compiler/rustc_middle/src/query/plumbing.rs
+++ b/compiler/rustc_middle/src/query/plumbing.rs
@@ -14,11 +14,14 @@ use crate::dep_graph;
 use crate::dep_graph::DepKind;
 use crate::query::on_disk_cache::{CacheEncoder, EncodedDepNodeIndex, OnDiskCache};
 use crate::query::{
-    DynamicQueries, ExternProviders, Providers, QueryArenas, QueryCaches, QueryEngine, QueryStates,
+    ExternProviders, PerQueryVTables, Providers, QueryArenas, QueryCaches, QueryEngine, QueryStates,
 };
 use crate::ty::TyCtxt;
 
-pub struct DynamicQuery<'tcx, C: QueryCache> {
+/// Stores function pointers and other metadata for a particular query.
+///
+/// Used indirectly by query plumbing in `rustc_query_system`, via a trait.
+pub struct QueryVTable<'tcx, C: QueryCache> {
     pub name: &'static str,
     pub eval_always: bool,
     pub dep_kind: DepKind,
@@ -62,7 +65,7 @@ pub struct QuerySystem<'tcx> {
     pub states: QueryStates<'tcx>,
     pub arenas: WorkerLocal<QueryArenas<'tcx>>,
     pub caches: QueryCaches<'tcx>,
-    pub dynamic_queries: DynamicQueries<'tcx>,
+    pub query_vtables: PerQueryVTables<'tcx>,
 
     /// This provides access to the incremental compilation on-disk cache for query results.
     /// Do not access this directly. It is only meant to be used by
@@ -418,9 +421,12 @@ macro_rules! define_callbacks {
             })*
         }
 
-        pub struct DynamicQueries<'tcx> {
+        /// Holds a `QueryVTable` for each query.
+        ///
+        /// ("Per" just makes this pluralized name more visually distinct.)
+        pub struct PerQueryVTables<'tcx> {
             $(
-                pub $name: DynamicQuery<'tcx, queries::$name::Storage<'tcx>>,
+                pub $name: ::rustc_middle::query::plumbing::QueryVTable<'tcx, queries::$name::Storage<'tcx>>,
             )*
         }
 
diff --git a/compiler/rustc_query_impl/src/lib.rs b/compiler/rustc_query_impl/src/lib.rs
index e8983bfa1ddb..a8dcd3eb153b 100644
--- a/compiler/rustc_query_impl/src/lib.rs
+++ b/compiler/rustc_query_impl/src/lib.rs
@@ -12,10 +12,9 @@ use rustc_middle::arena::Arena;
 use rustc_middle::dep_graph::{self, DepKind, DepKindVTable, DepNodeIndex};
 use rustc_middle::query::erase::{Erase, erase, restore};
 use rustc_middle::query::on_disk_cache::{CacheEncoder, EncodedDepNodeIndex, OnDiskCache};
-use rustc_middle::query::plumbing::{DynamicQuery, QuerySystem, QuerySystemFns};
+use rustc_middle::query::plumbing::{QuerySystem, QuerySystemFns, QueryVTable};
 use rustc_middle::query::{
-    AsLocalKey, DynamicQueries, ExternProviders, Providers, QueryCaches, QueryEngine, QueryStates,
-    queries,
+    AsLocalKey, ExternProviders, Providers, QueryCaches, QueryEngine, QueryStates, queries,
 };
 use rustc_middle::ty::TyCtxt;
 use rustc_query_system::Value;
@@ -44,7 +43,7 @@ struct DynamicConfig<
     const DEPTH_LIMIT: bool,
     const FEEDABLE: bool,
 > {
-    dynamic: &'tcx DynamicQuery<'tcx, C>,
+    vtable: &'tcx QueryVTable<'tcx, C>,
 }
 
 impl<'tcx, C: QueryCache, const ANON: bool, const DEPTH_LIMIT: bool, const FEEDABLE: bool> Copy
@@ -70,12 +69,12 @@ where
 
     #[inline(always)]
     fn name(self) -> &'static str {
-        self.dynamic.name
+        self.vtable.name
     }
 
     #[inline(always)]
     fn cache_on_disk(self, tcx: TyCtxt<'tcx>, key: &Self::Key) -> bool {
-        (self.dynamic.cache_on_disk)(tcx, key)
+        (self.vtable.cache_on_disk)(tcx, key)
     }
 
     #[inline(always)]
@@ -90,7 +89,7 @@ where
         // This is just manually doing the subfield referencing through pointer math.
         unsafe {
             &*(&qcx.tcx.query_system.states as *const QueryStates<'tcx>)
-                .byte_add(self.dynamic.query_state)
+                .byte_add(self.vtable.query_state)
                 .cast::<QueryState<Self::Key, QueryStackDeferred<'tcx>>>()
         }
     }
@@ -104,19 +103,19 @@ where
         // This is just manually doing the subfield referencing through pointer math.
         unsafe {
             &*(&qcx.tcx.query_system.caches as *const QueryCaches<'tcx>)
-                .byte_add(self.dynamic.query_cache)
+                .byte_add(self.vtable.query_cache)
                 .cast::<Self::Cache>()
         }
     }
 
     #[inline(always)]
     fn execute_query(self, tcx: TyCtxt<'tcx>, key: Self::Key) -> Self::Value {
-        (self.dynamic.execute_query)(tcx, key)
+        (self.vtable.execute_query)(tcx, key)
     }
 
     #[inline(always)]
     fn compute(self, qcx: QueryCtxt<'tcx>, key: Self::Key) -> Self::Value {
-        (self.dynamic.compute)(qcx.tcx, key)
+        (self.vtable.compute)(qcx.tcx, key)
     }
 
     #[inline(always)]
@@ -127,8 +126,8 @@ where
         prev_index: SerializedDepNodeIndex,
         index: DepNodeIndex,
     ) -> Option<Self::Value> {
-        if self.dynamic.can_load_from_disk {
-            (self.dynamic.try_load_from_disk)(qcx.tcx, key, prev_index, index)
+        if self.vtable.can_load_from_disk {
+            (self.vtable.try_load_from_disk)(qcx.tcx, key, prev_index, index)
         } else {
             None
         }
@@ -141,7 +140,7 @@ where
         key: &Self::Key,
         index: SerializedDepNodeIndex,
     ) -> bool {
-        (self.dynamic.loadable_from_disk)(qcx.tcx, key, index)
+        (self.vtable.loadable_from_disk)(qcx.tcx, key, index)
     }
 
     fn value_from_cycle_error(
@@ -150,12 +149,12 @@ where
         cycle_error: &CycleError,
         guar: ErrorGuaranteed,
     ) -> Self::Value {
-        (self.dynamic.value_from_cycle_error)(tcx, cycle_error, guar)
+        (self.vtable.value_from_cycle_error)(tcx, cycle_error, guar)
     }
 
     #[inline(always)]
     fn format_value(self) -> fn(&Self::Value) -> String {
-        self.dynamic.format_value
+        self.vtable.format_value
     }
 
     #[inline(always)]
@@ -165,7 +164,7 @@ where
 
     #[inline(always)]
     fn eval_always(self) -> bool {
-        self.dynamic.eval_always
+        self.vtable.eval_always
     }
 
     #[inline(always)]
@@ -180,17 +179,17 @@ where
 
     #[inline(always)]
     fn dep_kind(self) -> DepKind {
-        self.dynamic.dep_kind
+        self.vtable.dep_kind
     }
 
     #[inline(always)]
     fn cycle_error_handling(self) -> CycleErrorHandling {
-        self.dynamic.cycle_error_handling
+        self.vtable.cycle_error_handling
     }
 
     #[inline(always)]
     fn hash_result(self) -> HashResult<Self::Value> {
-        self.dynamic.hash_result
+        self.vtable.hash_result
     }
 }
 
@@ -217,7 +216,7 @@ pub fn query_system<'a>(
         states: Default::default(),
         arenas: Default::default(),
         caches: Default::default(),
-        dynamic_queries: dynamic_queries(),
+        query_vtables: make_query_vtables(),
         on_disk_cache,
         fns: QuerySystemFns {
             engine: engine(incremental),
diff --git a/compiler/rustc_query_impl/src/plumbing.rs b/compiler/rustc_query_impl/src/plumbing.rs
index 0c3fcf25c655..0104998a1f0d 100644
--- a/compiler/rustc_query_impl/src/plumbing.rs
+++ b/compiler/rustc_query_impl/src/plumbing.rs
@@ -641,10 +641,10 @@ macro_rules! define_queries {
                 }
             }
 
-            pub(crate) fn dynamic_query<'tcx>()
-                -> DynamicQuery<'tcx, queries::$name::Storage<'tcx>>
+            pub(crate) fn make_query_vtable<'tcx>()
+                -> QueryVTable<'tcx, queries::$name::Storage<'tcx>>
             {
-                DynamicQuery {
+                QueryVTable {
                     name: stringify!($name),
                     eval_always: is_eval_always!([$($modifiers)*]),
                     dep_kind: dep_graph::dep_kinds::$name,
@@ -725,7 +725,7 @@ macro_rules! define_queries {
                 #[inline(always)]
                 fn config(tcx: TyCtxt<'tcx>) -> Self::Config {
                     DynamicConfig {
-                        dynamic: &tcx.query_system.dynamic_queries.$name,
+                        vtable: &tcx.query_system.query_vtables.$name,
                     }
                 }
 
@@ -810,10 +810,10 @@ macro_rules! define_queries {
             }
         }
 
-        pub fn dynamic_queries<'tcx>() -> DynamicQueries<'tcx> {
-            DynamicQueries {
+        pub fn make_query_vtables<'tcx>() -> ::rustc_middle::query::PerQueryVTables<'tcx> {
+            ::rustc_middle::query::PerQueryVTables {
                 $(
-                    $name: query_impl::$name::dynamic_query(),
+                    $name: query_impl::$name::make_query_vtable(),
                 )*
             }
         }

From 2c9175d73db97065ef306758dbbc684e2a17536a Mon Sep 17 00:00:00 2001
From: Zalathar <Zalathar@users.noreply.github.com>
Date: Sun, 25 Jan 2026 13:55:02 +1100
Subject: [PATCH 67/97] Rename trait `QueryConfig` to `QueryDispatcher`

---
 compiler/rustc_query_impl/src/lib.rs          | 46 +++++++++++++-----
 compiler/rustc_query_impl/src/plumbing.rs     | 47 ++++++++++---------
 .../src/query/{config.rs => dispatcher.rs}    | 12 +++--
 compiler/rustc_query_system/src/query/mod.rs  |  4 +-
 .../rustc_query_system/src/query/plumbing.rs  | 28 +++++------
 5 files changed, 82 insertions(+), 55 deletions(-)
 rename compiler/rustc_query_system/src/query/{config.rs => dispatcher.rs} (85%)

diff --git a/compiler/rustc_query_impl/src/lib.rs b/compiler/rustc_query_impl/src/lib.rs
index a8dcd3eb153b..b628224db536 100644
--- a/compiler/rustc_query_impl/src/lib.rs
+++ b/compiler/rustc_query_impl/src/lib.rs
@@ -21,7 +21,7 @@ use rustc_query_system::Value;
 use rustc_query_system::dep_graph::SerializedDepNodeIndex;
 use rustc_query_system::ich::StableHashingContext;
 use rustc_query_system::query::{
-    CycleError, CycleErrorHandling, HashResult, QueryCache, QueryConfig, QueryMap, QueryMode,
+    CycleError, CycleErrorHandling, HashResult, QueryCache, QueryDispatcher, QueryMap, QueryMode,
     QueryStackDeferred, QueryState, get_query_incr, get_query_non_incr,
 };
 use rustc_span::{ErrorGuaranteed, Span};
@@ -36,7 +36,13 @@ pub use crate::plumbing::{QueryCtxt, query_key_hash_verify_all};
 mod profiling_support;
 pub use self::profiling_support::alloc_self_profile_query_strings;
 
-struct DynamicConfig<
+/// Combines a [`QueryVTable`] with some additional compile-time booleans
+/// to implement [`QueryDispatcher`], for use by code in [`rustc_query_system`].
+///
+/// Baking these boolean flags into the type gives a modest but measurable
+/// improvement to compiler perf and compiler code size; see
+/// <https://github.com/rust-lang/rust/pull/151633>.
+struct SemiDynamicQueryDispatcher<
     'tcx,
     C: QueryCache,
     const ANON: bool,
@@ -46,20 +52,23 @@ struct DynamicConfig<
     vtable: &'tcx QueryVTable<'tcx, C>,
 }
 
+// Manually implement Copy/Clone, because deriving would put trait bounds on the cache type.
 impl<'tcx, C: QueryCache, const ANON: bool, const DEPTH_LIMIT: bool, const FEEDABLE: bool> Copy
-    for DynamicConfig<'tcx, C, ANON, DEPTH_LIMIT, FEEDABLE>
+    for SemiDynamicQueryDispatcher<'tcx, C, ANON, DEPTH_LIMIT, FEEDABLE>
 {
 }
 impl<'tcx, C: QueryCache, const ANON: bool, const DEPTH_LIMIT: bool, const FEEDABLE: bool> Clone
-    for DynamicConfig<'tcx, C, ANON, DEPTH_LIMIT, FEEDABLE>
+    for SemiDynamicQueryDispatcher<'tcx, C, ANON, DEPTH_LIMIT, FEEDABLE>
 {
     fn clone(&self) -> Self {
         *self
     }
 }
 
+// This is `impl QueryDispatcher for SemiDynamicQueryDispatcher`.
 impl<'tcx, C: QueryCache, const ANON: bool, const DEPTH_LIMIT: bool, const FEEDABLE: bool>
-    QueryConfig<QueryCtxt<'tcx>> for DynamicConfig<'tcx, C, ANON, DEPTH_LIMIT, FEEDABLE>
+    QueryDispatcher<QueryCtxt<'tcx>>
+    for SemiDynamicQueryDispatcher<'tcx, C, ANON, DEPTH_LIMIT, FEEDABLE>
 where
     for<'a> C::Key: HashStable<StableHashingContext<'a>>,
 {
@@ -193,17 +202,28 @@ where
     }
 }
 
-/// This is implemented per query. It allows restoring query values from their erased state
-/// and constructing a QueryConfig.
-trait QueryConfigRestored<'tcx> {
-    type RestoredValue;
-    type Config: QueryConfig<QueryCtxt<'tcx>>;
+/// Provides access to vtable-like operations for a query
+/// (by creating a [`QueryDispatcher`]),
+/// but also keeps track of the "unerased" value type of the query
+/// (i.e. the actual result type in the query declaration).
+///
+/// This trait allows some per-query code to be defined in generic functions
+/// with a trait bound, instead of having to be defined inline within a macro
+/// expansion.
+///
+/// There is one macro-generated implementation of this trait for each query,
+/// on the type `rustc_query_impl::query_impl::$name::QueryType`.
+trait QueryDispatcherUnerased<'tcx> {
+    type UnerasedValue;
+    type Dispatcher: QueryDispatcher<QueryCtxt<'tcx>>;
 
     const NAME: &'static &'static str;
 
-    fn config(tcx: TyCtxt<'tcx>) -> Self::Config;
-    fn restore(value: <Self::Config as QueryConfig<QueryCtxt<'tcx>>>::Value)
-    -> Self::RestoredValue;
+    fn query_dispatcher(tcx: TyCtxt<'tcx>) -> Self::Dispatcher;
+
+    fn restore_val(
+        value: <Self::Dispatcher as QueryDispatcher<QueryCtxt<'tcx>>>::Value,
+    ) -> Self::UnerasedValue;
 }
 
 pub fn query_system<'a>(
diff --git a/compiler/rustc_query_impl/src/plumbing.rs b/compiler/rustc_query_impl/src/plumbing.rs
index 0104998a1f0d..6ead03a527a7 100644
--- a/compiler/rustc_query_impl/src/plumbing.rs
+++ b/compiler/rustc_query_impl/src/plumbing.rs
@@ -27,14 +27,14 @@ use rustc_middle::ty::{self, TyCtxt};
 use rustc_query_system::dep_graph::{DepNodeParams, HasDepContext};
 use rustc_query_system::ich::StableHashingContext;
 use rustc_query_system::query::{
-    QueryCache, QueryConfig, QueryContext, QueryJobId, QueryMap, QuerySideEffect,
+    QueryCache, QueryContext, QueryDispatcher, QueryJobId, QueryMap, QuerySideEffect,
     QueryStackDeferred, QueryStackFrame, QueryStackFrameExtra, force_query,
 };
 use rustc_query_system::{QueryOverflow, QueryOverflowNote};
 use rustc_serialize::{Decodable, Encodable};
 use rustc_span::def_id::LOCAL_CRATE;
 
-use crate::QueryConfigRestored;
+use crate::QueryDispatcherUnerased;
 
 /// Implements [`QueryContext`] for use by [`rustc_query_system`], since that
 /// crate does not have direct access to [`TyCtxt`].
@@ -387,13 +387,13 @@ pub(crate) fn create_query_frame<
 }
 
 pub(crate) fn encode_query_results<'a, 'tcx, Q>(
-    query: Q::Config,
+    query: Q::Dispatcher,
     qcx: QueryCtxt<'tcx>,
     encoder: &mut CacheEncoder<'a, 'tcx>,
     query_result_index: &mut EncodedDepNodeIndex,
 ) where
-    Q: super::QueryConfigRestored<'tcx>,
-    Q::RestoredValue: Encodable<CacheEncoder<'a, 'tcx>>,
+    Q: QueryDispatcherUnerased<'tcx>,
+    Q::UnerasedValue: Encodable<CacheEncoder<'a, 'tcx>>,
 {
     let _timer = qcx.tcx.prof.generic_activity_with_arg("encode_query_results_for", query.name());
 
@@ -408,13 +408,13 @@ pub(crate) fn encode_query_results<'a, 'tcx, Q>(
 
             // Encode the type check tables with the `SerializedDepNodeIndex`
             // as tag.
-            encoder.encode_tagged(dep_node, &Q::restore(*value));
+            encoder.encode_tagged(dep_node, &Q::restore_val(*value));
         }
     });
 }
 
 pub(crate) fn query_key_hash_verify<'tcx>(
-    query: impl QueryConfig<QueryCtxt<'tcx>>,
+    query: impl QueryDispatcher<QueryCtxt<'tcx>>,
     qcx: QueryCtxt<'tcx>,
 ) {
     let _timer = qcx.tcx.prof.generic_activity_with_arg("query_key_hash_verify_for", query.name());
@@ -442,7 +442,7 @@ pub(crate) fn query_key_hash_verify<'tcx>(
 
 fn try_load_from_on_disk_cache<'tcx, Q>(query: Q, tcx: TyCtxt<'tcx>, dep_node: DepNode)
 where
-    Q: QueryConfig<QueryCtxt<'tcx>>,
+    Q: QueryDispatcher<QueryCtxt<'tcx>>,
 {
     debug_assert!(tcx.dep_graph.is_green(&dep_node));
 
@@ -488,7 +488,7 @@ where
 
 fn force_from_dep_node<'tcx, Q>(query: Q, tcx: TyCtxt<'tcx>, dep_node: DepNode) -> bool
 where
-    Q: QueryConfig<QueryCtxt<'tcx>>,
+    Q: QueryDispatcher<QueryCtxt<'tcx>>,
 {
     // We must avoid ever having to call `force_from_dep_node()` for a
     // `DepNode::codegen_unit`:
@@ -521,9 +521,10 @@ pub(crate) fn make_dep_kind_vtable_for_query<'tcx, Q>(
     is_eval_always: bool,
 ) -> DepKindVTable<'tcx>
 where
-    Q: QueryConfigRestored<'tcx>,
+    Q: QueryDispatcherUnerased<'tcx>,
 {
-    let fingerprint_style = <Q::Config as QueryConfig<QueryCtxt<'tcx>>>::Key::fingerprint_style();
+    let fingerprint_style =
+        <Q::Dispatcher as QueryDispatcher<QueryCtxt<'tcx>>>::Key::fingerprint_style();
 
     if is_anon || !fingerprint_style.reconstructible() {
         return DepKindVTable {
@@ -541,10 +542,10 @@ where
         is_eval_always,
         fingerprint_style,
         force_from_dep_node: Some(|tcx, dep_node, _| {
-            force_from_dep_node(Q::config(tcx), tcx, dep_node)
+            force_from_dep_node(Q::query_dispatcher(tcx), tcx, dep_node)
         }),
         try_load_from_on_disk_cache: Some(|tcx, dep_node| {
-            try_load_from_on_disk_cache(Q::config(tcx), tcx, dep_node)
+            try_load_from_on_disk_cache(Q::query_dispatcher(tcx), tcx, dep_node)
         }),
         name: Q::NAME,
     }
@@ -613,7 +614,7 @@ macro_rules! define_queries {
                     #[cfg(debug_assertions)]
                     let _guard = tracing::span!(tracing::Level::TRACE, stringify!($name), ?key).entered();
                     get_query_incr(
-                        QueryType::config(tcx),
+                        QueryType::query_dispatcher(tcx),
                         QueryCtxt::new(tcx),
                         span,
                         key,
@@ -633,7 +634,7 @@ macro_rules! define_queries {
                     __mode: QueryMode,
                 ) -> Option<Erase<queries::$name::Value<'tcx>>> {
                     Some(get_query_non_incr(
-                        QueryType::config(tcx),
+                        QueryType::query_dispatcher(tcx),
                         QueryCtxt::new(tcx),
                         span,
                         key,
@@ -710,9 +711,9 @@ macro_rules! define_queries {
                 data: PhantomData<&'tcx ()>
             }
 
-            impl<'tcx> QueryConfigRestored<'tcx> for QueryType<'tcx> {
-                type RestoredValue = queries::$name::Value<'tcx>;
-                type Config = DynamicConfig<
+            impl<'tcx> QueryDispatcherUnerased<'tcx> for QueryType<'tcx> {
+                type UnerasedValue = queries::$name::Value<'tcx>;
+                type Dispatcher = SemiDynamicQueryDispatcher<
                     'tcx,
                     queries::$name::Storage<'tcx>,
                     { is_anon!([$($modifiers)*]) },
@@ -723,14 +724,14 @@ macro_rules! define_queries {
                 const NAME: &'static &'static str = &stringify!($name);
 
                 #[inline(always)]
-                fn config(tcx: TyCtxt<'tcx>) -> Self::Config {
-                    DynamicConfig {
+                fn query_dispatcher(tcx: TyCtxt<'tcx>) -> Self::Dispatcher {
+                    SemiDynamicQueryDispatcher {
                         vtable: &tcx.query_system.query_vtables.$name,
                     }
                 }
 
                 #[inline(always)]
-                fn restore(value: <Self::Config as QueryConfig<QueryCtxt<'tcx>>>::Value) -> Self::RestoredValue {
+                fn restore_val(value: <Self::Dispatcher as QueryDispatcher<QueryCtxt<'tcx>>>::Value) -> Self::UnerasedValue {
                     restore::<queries::$name::Value<'tcx>>(value)
                 }
             }
@@ -782,7 +783,7 @@ macro_rules! define_queries {
                     query_result_index: &mut EncodedDepNodeIndex
                 ) {
                     $crate::plumbing::encode_query_results::<query_impl::$name::QueryType<'tcx>>(
-                        query_impl::$name::QueryType::config(tcx),
+                        query_impl::$name::QueryType::query_dispatcher(tcx),
                         QueryCtxt::new(tcx),
                         encoder,
                         query_result_index,
@@ -792,7 +793,7 @@ macro_rules! define_queries {
 
             pub(crate) fn query_key_hash_verify<'tcx>(tcx: TyCtxt<'tcx>) {
                 $crate::plumbing::query_key_hash_verify(
-                    query_impl::$name::QueryType::config(tcx),
+                    query_impl::$name::QueryType::query_dispatcher(tcx),
                     QueryCtxt::new(tcx),
                 )
             }
diff --git a/compiler/rustc_query_system/src/query/config.rs b/compiler/rustc_query_system/src/query/dispatcher.rs
similarity index 85%
rename from compiler/rustc_query_system/src/query/config.rs
rename to compiler/rustc_query_system/src/query/dispatcher.rs
index 66b04aa7b467..bba1703dfbb6 100644
--- a/compiler/rustc_query_system/src/query/config.rs
+++ b/compiler/rustc_query_system/src/query/dispatcher.rs
@@ -1,5 +1,3 @@
-//! Query configuration and description traits.
-
 use std::fmt::Debug;
 use std::hash::Hash;
 
@@ -14,7 +12,15 @@ use crate::query::{CycleError, CycleErrorHandling, DepNodeIndex, QueryContext, Q
 
 pub type HashResult<V> = Option<fn(&mut StableHashingContext<'_>, &V) -> Fingerprint>;
 
-pub trait QueryConfig<Qcx: QueryContext>: Copy {
+/// Trait that can be used as a vtable for a single query, providing operations
+/// and metadata for that query.
+///
+/// Implemented by `rustc_query_impl::SemiDynamicQueryDispatcher`, which
+/// mostly delegates to `rustc_middle::query::plumbing::QueryVTable`.
+/// Those types are not visible from this `rustc_query_system` crate.
+///
+/// "Dispatcher" should be understood as a near-synonym of "vtable".
+pub trait QueryDispatcher<Qcx: QueryContext>: Copy {
     fn name(self) -> &'static str;
 
     // `Key` and `Value` are `Copy` instead of `Clone` to ensure copying them stays cheap,
diff --git a/compiler/rustc_query_system/src/query/mod.rs b/compiler/rustc_query_system/src/query/mod.rs
index 3ff980fa9bc5..701253d50fcc 100644
--- a/compiler/rustc_query_system/src/query/mod.rs
+++ b/compiler/rustc_query_system/src/query/mod.rs
@@ -13,7 +13,7 @@ use rustc_span::Span;
 use rustc_span::def_id::DefId;
 
 pub use self::caches::{DefIdCache, DefaultCache, QueryCache, SingleCache, VecCache};
-pub use self::config::{HashResult, QueryConfig};
+pub use self::dispatcher::{HashResult, QueryDispatcher};
 pub use self::job::{
     QueryInfo, QueryJob, QueryJobId, QueryJobInfo, QueryMap, break_query_cycles, print_query_stack,
     report_cycle,
@@ -22,7 +22,7 @@ pub use self::plumbing::*;
 use crate::dep_graph::{DepKind, DepNodeIndex, HasDepContext, SerializedDepNodeIndex};
 
 mod caches;
-mod config;
+mod dispatcher;
 mod job;
 mod plumbing;
 
diff --git a/compiler/rustc_query_system/src/query/plumbing.rs b/compiler/rustc_query_system/src/query/plumbing.rs
index 5be4ee145208..9afad1546e9e 100644
--- a/compiler/rustc_query_system/src/query/plumbing.rs
+++ b/compiler/rustc_query_system/src/query/plumbing.rs
@@ -18,7 +18,7 @@ use rustc_errors::{Diag, FatalError, StashKey};
 use rustc_span::{DUMMY_SP, Span};
 use tracing::instrument;
 
-use super::{QueryConfig, QueryStackFrameExtra};
+use super::{QueryDispatcher, QueryStackFrameExtra};
 use crate::dep_graph::{DepContext, DepGraphData, DepNode, DepNodeIndex, DepNodeParams};
 use crate::ich::StableHashingContext;
 use crate::query::caches::QueryCache;
@@ -126,7 +126,7 @@ where
 #[inline(never)]
 fn mk_cycle<Q, Qcx>(query: Q, qcx: Qcx, cycle_error: CycleError) -> Q::Value
 where
-    Q: QueryConfig<Qcx>,
+    Q: QueryDispatcher<Qcx>,
     Qcx: QueryContext,
 {
     let error = report_cycle(qcx.dep_context().sess(), &cycle_error);
@@ -140,7 +140,7 @@ fn handle_cycle_error<Q, Qcx>(
     error: Diag<'_>,
 ) -> Q::Value
 where
-    Q: QueryConfig<Qcx>,
+    Q: QueryDispatcher<Qcx>,
     Qcx: QueryContext,
 {
     match query.cycle_error_handling() {
@@ -279,7 +279,7 @@ fn cycle_error<Q, Qcx>(
     span: Span,
 ) -> (Q::Value, Option<DepNodeIndex>)
 where
-    Q: QueryConfig<Qcx>,
+    Q: QueryDispatcher<Qcx>,
     Qcx: QueryContext,
 {
     // Ensure there was no errors collecting all active jobs.
@@ -300,7 +300,7 @@ fn wait_for_query<Q, Qcx>(
     current: Option<QueryJobId>,
 ) -> (Q::Value, Option<DepNodeIndex>)
 where
-    Q: QueryConfig<Qcx>,
+    Q: QueryDispatcher<Qcx>,
     Qcx: QueryContext,
 {
     // For parallel queries, we'll block and wait until the query running
@@ -349,7 +349,7 @@ fn try_execute_query<Q, Qcx, const INCR: bool>(
     dep_node: Option<DepNode>,
 ) -> (Q::Value, Option<DepNodeIndex>)
 where
-    Q: QueryConfig<Qcx>,
+    Q: QueryDispatcher<Qcx>,
     Qcx: QueryContext,
 {
     let state = query.query_state(qcx);
@@ -421,7 +421,7 @@ fn execute_job<Q, Qcx, const INCR: bool>(
     dep_node: Option<DepNode>,
 ) -> (Q::Value, Option<DepNodeIndex>)
 where
-    Q: QueryConfig<Qcx>,
+    Q: QueryDispatcher<Qcx>,
     Qcx: QueryContext,
 {
     // Use `JobOwner` so the query will be poisoned if executing it panics.
@@ -491,7 +491,7 @@ fn execute_job_non_incr<Q, Qcx>(
     job_id: QueryJobId,
 ) -> (Q::Value, DepNodeIndex)
 where
-    Q: QueryConfig<Qcx>,
+    Q: QueryDispatcher<Qcx>,
     Qcx: QueryContext,
 {
     debug_assert!(!qcx.dep_context().dep_graph().is_fully_enabled());
@@ -530,7 +530,7 @@ fn execute_job_incr<Q, Qcx>(
     job_id: QueryJobId,
 ) -> (Q::Value, DepNodeIndex)
 where
-    Q: QueryConfig<Qcx>,
+    Q: QueryDispatcher<Qcx>,
     Qcx: QueryContext,
 {
     if !query.anon() && !query.eval_always() {
@@ -585,7 +585,7 @@ fn try_load_from_disk_and_cache_in_memory<Q, Qcx>(
     dep_node: &DepNode,
 ) -> Option<(Q::Value, DepNodeIndex)>
 where
-    Q: QueryConfig<Qcx>,
+    Q: QueryDispatcher<Qcx>,
     Qcx: QueryContext,
 {
     // Note this function can be called concurrently from the same query
@@ -771,7 +771,7 @@ fn ensure_must_run<Q, Qcx>(
     check_cache: bool,
 ) -> (bool, Option<DepNode>)
 where
-    Q: QueryConfig<Qcx>,
+    Q: QueryDispatcher<Qcx>,
     Qcx: QueryContext,
 {
     if query.eval_always() {
@@ -819,7 +819,7 @@ pub enum QueryMode {
 #[inline(always)]
 pub fn get_query_non_incr<Q, Qcx>(query: Q, qcx: Qcx, span: Span, key: Q::Key) -> Q::Value
 where
-    Q: QueryConfig<Qcx>,
+    Q: QueryDispatcher<Qcx>,
     Qcx: QueryContext,
 {
     debug_assert!(!qcx.dep_context().dep_graph().is_fully_enabled());
@@ -836,7 +836,7 @@ pub fn get_query_incr<Q, Qcx>(
     mode: QueryMode,
 ) -> Option<Q::Value>
 where
-    Q: QueryConfig<Qcx>,
+    Q: QueryDispatcher<Qcx>,
     Qcx: QueryContext,
 {
     debug_assert!(qcx.dep_context().dep_graph().is_fully_enabled());
@@ -862,7 +862,7 @@ where
 
 pub fn force_query<Q, Qcx>(query: Q, qcx: Qcx, key: Q::Key, dep_node: DepNode)
 where
-    Q: QueryConfig<Qcx>,
+    Q: QueryDispatcher<Qcx>,
     Qcx: QueryContext,
 {
     // We may be concurrently trying both execute and force a query.

From 3510a9ad0c3c86226788faf3c0cd8027b2dbe6f2 Mon Sep 17 00:00:00 2001
From: Nikita Popov <npopov@redhat.com>
Date: Tue, 6 Jan 2026 10:43:07 +0100
Subject: [PATCH 68/97] Update to LLVM 22

---
 .gitmodules      | 2 +-
 src/llvm-project | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/.gitmodules b/.gitmodules
index 8617643a1202..b11b47ec108b 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -25,7 +25,7 @@
 [submodule "src/llvm-project"]
 	path = src/llvm-project
 	url = https://github.com/rust-lang/llvm-project.git
-	branch = rustc/21.1-2025-08-01
+	branch = rustc/22.1-2026-01-27
 	shallow = true
 [submodule "src/doc/embedded-book"]
 	path = src/doc/embedded-book
diff --git a/src/llvm-project b/src/llvm-project
index 00d23d10dc48..41256ab128f2 160000
--- a/src/llvm-project
+++ b/src/llvm-project
@@ -1 +1 @@
-Subproject commit 00d23d10dc48c6bb9d57ba96d4a748d85d77d0c7
+Subproject commit 41256ab128f2af613b4a16771cda6baa36b55f45

From 749a27975cabc86c3c935af5dc721938265370db Mon Sep 17 00:00:00 2001
From: Nikita Popov <npopov@redhat.com>
Date: Thu, 8 Jan 2026 15:32:16 +0100
Subject: [PATCH 69/97] Update host toolchain

---
 src/ci/docker/scripts/build-clang.sh | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/ci/docker/scripts/build-clang.sh b/src/ci/docker/scripts/build-clang.sh
index 905c40773042..b3b1dc47e2ef 100755
--- a/src/ci/docker/scripts/build-clang.sh
+++ b/src/ci/docker/scripts/build-clang.sh
@@ -5,7 +5,7 @@ set -ex
 source shared.sh
 
 # Try to keep the LLVM version here in sync with src/ci/scripts/install-clang.sh
-LLVM=llvmorg-21.1.0-rc2
+LLVM=llvmorg-22.1.0-rc2
 
 mkdir llvm-project
 cd llvm-project

From e015fc820db5d7fe2495c09b1fdd5e2092ed3cd1 Mon Sep 17 00:00:00 2001
From: Nikita Popov <npopov@redhat.com>
Date: Tue, 27 Jan 2026 12:03:48 +0100
Subject: [PATCH 70/97] Adjust loongarch assembly test

This generates different code on loongarch32r now.
---
 tests/assembly-llvm/asm/loongarch-type.rs | 27 +++++++++++++++++------
 1 file changed, 20 insertions(+), 7 deletions(-)

diff --git a/tests/assembly-llvm/asm/loongarch-type.rs b/tests/assembly-llvm/asm/loongarch-type.rs
index e0a7940f89a3..5efad583a39d 100644
--- a/tests/assembly-llvm/asm/loongarch-type.rs
+++ b/tests/assembly-llvm/asm/loongarch-type.rs
@@ -1,10 +1,14 @@
 //@ add-minicore
-//@ revisions: loongarch32 loongarch64
+//@ revisions: loongarch32s loongarch32r loongarch64
 
 //@ assembly-output: emit-asm
 
-//@[loongarch32] compile-flags: --target loongarch32-unknown-none
-//@[loongarch32] needs-llvm-components: loongarch
+//@[loongarch32s] compile-flags: --target loongarch32-unknown-none -Ctarget-feature=+32s
+//@[loongarch32s] needs-llvm-components: loongarch
+
+//@[loongarch32r] compile-flags: --target loongarch32-unknown-none
+//@[loongarch32r] needs-llvm-components: loongarch
+//@[loongarch32r] min-llvm-version: 22
 
 //@[loongarch64] compile-flags: --target loongarch64-unknown-none
 //@[loongarch64] needs-llvm-components: loongarch
@@ -28,8 +32,12 @@ extern "C" {
 
 // CHECK-LABEL: sym_fn:
 // CHECK: #APP
-// CHECK: pcalau12i $t0, %got_pc_hi20(extern_func)
-// CHECK: ld.{{[wd]}} $t0, $t0, %got_pc_lo12(extern_func)
+// loongarch64: pcalau12i $t0, %got_pc_hi20(extern_func)
+// loongarch64: ld.d $t0, $t0, %got_pc_lo12(extern_func)
+// loongarch32s: pcalau12i $t0, %got_pc_hi20(extern_func)
+// loongarch32s: ld.w $t0, $t0, %got_pc_lo12(extern_func)
+// loongarch32r: pcaddu12i $t0, %got_pcadd_hi20(extern_func)
+// loongarch32r: ld.w $t0, $t0, %got_pcadd_lo12(.Lpcadd_hi0)
 // CHECK: #NO_APP
 #[no_mangle]
 pub unsafe fn sym_fn() {
@@ -38,8 +46,13 @@ pub unsafe fn sym_fn() {
 
 // CHECK-LABEL: sym_static:
 // CHECK: #APP
-// CHECK: pcalau12i $t0, %got_pc_hi20(extern_static)
-// CHECK: ld.{{[wd]}} $t0, $t0, %got_pc_lo12(extern_static)
+// loongarch64: pcalau12i $t0, %got_pc_hi20(extern_static)
+// loongarch64: ld.d $t0, $t0, %got_pc_lo12(extern_static)
+// loongarch32s: pcalau12i $t0, %got_pc_hi20(extern_static)
+// loongarch32s: ld.w $t0, $t0, %got_pc_lo12(extern_static)
+// loongarch32r: pcaddu12i $t0, %got_pcadd_hi20(extern_static)
+// loongarch32r: ld.w $t0, $t0, %got_pcadd_lo12(.Lpcadd_hi1)
+
 // CHECK: #NO_APP
 #[no_mangle]
 pub unsafe fn sym_static() {

From c8975a2468eef8fab7572f5a50ff89531ec3ec1b Mon Sep 17 00:00:00 2001
From: Jonathan Brouwer <jonathantbrouwer@gmail.com>
Date: Tue, 27 Jan 2026 13:05:27 +0100
Subject: [PATCH 71/97] Add `extern core` to diagnostic tests

---
 .../diagnostic-derive-doc-comment-field.rs    |  1 +
 .../session-diagnostic/diagnostic-derive.rs   |  8 +++---
 .../subdiagnostic-derive.rs                   | 25 +++++++------------
 3 files changed, 15 insertions(+), 19 deletions(-)

diff --git a/tests/ui-fulldeps/session-diagnostic/diagnostic-derive-doc-comment-field.rs b/tests/ui-fulldeps/session-diagnostic/diagnostic-derive-doc-comment-field.rs
index 37f78a7777c4..4f08c5327c15 100644
--- a/tests/ui-fulldeps/session-diagnostic/diagnostic-derive-doc-comment-field.rs
+++ b/tests/ui-fulldeps/session-diagnostic/diagnostic-derive-doc-comment-field.rs
@@ -18,6 +18,7 @@ extern crate rustc_fluent_macro;
 extern crate rustc_macros;
 extern crate rustc_session;
 extern crate rustc_span;
+extern crate core;
 
 use rustc_errors::{Applicability, DiagMessage, SubdiagMessage};
 use rustc_macros::{Diagnostic, Subdiagnostic};
diff --git a/tests/ui-fulldeps/session-diagnostic/diagnostic-derive.rs b/tests/ui-fulldeps/session-diagnostic/diagnostic-derive.rs
index fa2d037064d2..fcae379d982f 100644
--- a/tests/ui-fulldeps/session-diagnostic/diagnostic-derive.rs
+++ b/tests/ui-fulldeps/session-diagnostic/diagnostic-derive.rs
@@ -29,6 +29,8 @@ use rustc_errors::{Applicability, DiagMessage, ErrCode, MultiSpan, SubdiagMessag
 
 extern crate rustc_session;
 
+extern crate core;
+
 rustc_fluent_macro::fluent_messages! { "./example.ftl" }
 
 // E0123 and E0456 are no longer used, so we define our own constants here just for this test.
@@ -56,7 +58,7 @@ enum DiagnosticOnEnum {
 #[derive(Diagnostic)]
 #[diag(no_crate_example, code = E0123)]
 #[diag = "E0123"]
-//~^ ERROR failed to resolve: you might be missing crate `core`
+//~^ ERROR expected parentheses: #[diag(...)]
 struct WrongStructAttrStyle {}
 
 #[derive(Diagnostic)]
@@ -801,7 +803,7 @@ struct SuggestionsNoItem {
 struct SuggestionsInvalidItem {
     #[suggestion(code(foo))]
     //~^ ERROR `code(...)` must contain only string literals
-    //~| ERROR failed to resolve: you might be missing crate `core`
+    //~| ERROR unexpected token, expected `)`
     sub: Span,
 }
 
@@ -809,7 +811,7 @@ struct SuggestionsInvalidItem {
 #[diag(no_crate_example)]
 struct SuggestionsInvalidLiteral {
     #[suggestion(code = 3)]
-    //~^ ERROR failed to resolve: you might be missing crate `core`
+    //~^ ERROR expected string literal
     sub: Span,
 }
 
diff --git a/tests/ui-fulldeps/session-diagnostic/subdiagnostic-derive.rs b/tests/ui-fulldeps/session-diagnostic/subdiagnostic-derive.rs
index c837372a7a7a..6481e8a3307c 100644
--- a/tests/ui-fulldeps/session-diagnostic/subdiagnostic-derive.rs
+++ b/tests/ui-fulldeps/session-diagnostic/subdiagnostic-derive.rs
@@ -16,6 +16,7 @@ extern crate rustc_fluent_macro;
 extern crate rustc_macros;
 extern crate rustc_session;
 extern crate rustc_span;
+extern crate core;
 
 use rustc_errors::{Applicability, DiagMessage, SubdiagMessage};
 use rustc_macros::Subdiagnostic;
@@ -94,8 +95,7 @@ struct G {
 
 #[derive(Subdiagnostic)]
 #[label("...")]
-//~^ ERROR failed to resolve: you might be missing crate `core`
-//~| NOTE you might be missing crate `core`
+//~^ ERROR unexpected literal in nested attribute, expected ident
 struct H {
     #[primary_span]
     span: Span,
@@ -310,8 +310,7 @@ struct AB {
 
 #[derive(Subdiagnostic)]
 union AC {
-    //~^ ERROR failed to resolve: you might be missing crate `core`
-    //~| NOTE you might be missing crate `core`
+    //~^ ERROR unexpected unsupported untagged union
     span: u32,
     b: u64,
 }
@@ -581,8 +580,7 @@ struct BD {
     span2: Span,
     #[suggestion_part(foo = "bar")]
     //~^ ERROR `code` is the only valid nested attribute
-    //~| ERROR failed to resolve: you might be missing crate `core`
-    //~| NOTE you might be missing crate `core`
+    //~| ERROR expected `,`
     span4: Span,
     #[suggestion_part(code = "...")]
     //~^ ERROR the `#[suggestion_part(...)]` attribute can only be applied to fields of type `Span` or `MultiSpan`
@@ -674,8 +672,7 @@ enum BL {
 struct BM {
     #[suggestion_part(code("foo"))]
     //~^ ERROR expected exactly one string literal for `code = ...`
-    //~| ERROR failed to resolve: you might be missing crate `core`
-    //~| NOTE you might be missing crate `core`
+    //~| ERROR unexpected token, expected `)`
     span: Span,
     r#type: String,
 }
@@ -685,8 +682,7 @@ struct BM {
 struct BN {
     #[suggestion_part(code("foo", "bar"))]
     //~^ ERROR expected exactly one string literal for `code = ...`
-    //~| ERROR failed to resolve: you might be missing crate `core`
-    //~| NOTE you might be missing crate `core`
+    //~| ERROR unexpected token, expected `)`
     span: Span,
     r#type: String,
 }
@@ -696,8 +692,7 @@ struct BN {
 struct BO {
     #[suggestion_part(code(3))]
     //~^ ERROR expected exactly one string literal for `code = ...`
-    //~| ERROR failed to resolve: you might be missing crate `core`
-    //~| NOTE you might be missing crate `core`
+    //~| ERROR unexpected token, expected `)`
     span: Span,
     r#type: String,
 }
@@ -718,8 +713,7 @@ struct BP {
 #[multipart_suggestion(no_crate_example)]
 struct BQ {
     #[suggestion_part(code = 3)]
-    //~^ ERROR failed to resolve: you might be missing crate `core`
-    //~| NOTE you might be missing crate `core`
+    //~^ ERROR expected string literal
     span: Span,
     r#type: String,
 }
@@ -811,8 +805,7 @@ struct SuggestionStyleInvalid3 {
 #[derive(Subdiagnostic)]
 #[suggestion(no_crate_example, code = "", style("foo"))]
 //~^ ERROR expected `= "xxx"`
-//~| ERROR failed to resolve: you might be missing crate `core`
-//~| NOTE you might be missing crate `core`
+//~| ERROR expected `,`
 struct SuggestionStyleInvalid4 {
     #[primary_span]
     sub: Span,

From 4039cef09ef4eb6b4731195338ce8b238f562a5d Mon Sep 17 00:00:00 2001
From: dianne <diannes.gm@gmail.com>
Date: Wed, 31 Dec 2025 14:10:03 -0800
Subject: [PATCH 72/97] Don't evaluate const blocks in constant promotion

---
 .../rustc_mir_transform/src/promote_consts.rs | 39 +++++++++--
 ...l-const-block-during-promotion.fail.stderr | 42 ++++++++++++
 .../dont-eval-const-block-during-promotion.rs | 65 +++++++++++++++++++
 3 files changed, 142 insertions(+), 4 deletions(-)
 create mode 100644 tests/ui/inline-const/dont-eval-const-block-during-promotion.fail.stderr
 create mode 100644 tests/ui/inline-const/dont-eval-const-block-during-promotion.rs

diff --git a/compiler/rustc_mir_transform/src/promote_consts.rs b/compiler/rustc_mir_transform/src/promote_consts.rs
index 2cc8e9d6739c..6e7b93a5e719 100644
--- a/compiler/rustc_mir_transform/src/promote_consts.rs
+++ b/compiler/rustc_mir_transform/src/promote_consts.rs
@@ -18,6 +18,7 @@ use rustc_const_eval::check_consts::{ConstCx, qualifs};
 use rustc_data_structures::assert_matches;
 use rustc_data_structures::fx::FxHashSet;
 use rustc_hir as hir;
+use rustc_hir::def::DefKind;
 use rustc_index::{IndexSlice, IndexVec};
 use rustc_middle::mir::visit::{MutVisitor, MutatingUseContext, PlaceContext, Visitor};
 use rustc_middle::mir::*;
@@ -329,6 +330,7 @@ impl<'tcx> Validator<'_, 'tcx> {
                 if let TempState::Defined { location: loc, .. } = self.temps[local]
                     && let Left(statement) =  self.body.stmt_at(loc)
                     && let Some((_, Rvalue::Use(Operand::Constant(c)))) = statement.kind.as_assign()
+                    && self.should_evaluate_for_promotion_checks(c.const_)
                     && let Some(idx) = c.const_.try_eval_target_usize(self.tcx, self.typing_env)
                     // Determine the type of the thing we are indexing.
                     && let ty::Array(_, len) = place_base.ty(self.body, self.tcx).ty.kind()
@@ -484,7 +486,9 @@ impl<'tcx> Validator<'_, 'tcx> {
                             let sz = lhs_ty.primitive_size(self.tcx);
                             // Integer division: the RHS must be a non-zero const.
                             let rhs_val = match rhs {
-                                Operand::Constant(c) => {
+                                Operand::Constant(c)
+                                    if self.should_evaluate_for_promotion_checks(c.const_) =>
+                                {
                                     c.const_.try_eval_scalar_int(self.tcx, self.typing_env)
                                 }
                                 _ => None,
@@ -502,9 +506,14 @@ impl<'tcx> Validator<'_, 'tcx> {
                                         // The RHS is -1 or unknown, so we have to be careful.
                                         // But is the LHS int::MIN?
                                         let lhs_val = match lhs {
-                                            Operand::Constant(c) => c
-                                                .const_
-                                                .try_eval_scalar_int(self.tcx, self.typing_env),
+                                            Operand::Constant(c)
+                                                if self.should_evaluate_for_promotion_checks(
+                                                    c.const_,
+                                                ) =>
+                                            {
+                                                c.const_
+                                                    .try_eval_scalar_int(self.tcx, self.typing_env)
+                                            }
                                             _ => None,
                                         };
                                         let lhs_min = sz.signed_int_min();
@@ -683,6 +692,28 @@ impl<'tcx> Validator<'_, 'tcx> {
         // This passed all checks, so let's accept.
         Ok(())
     }
+
+    /// Can we try to evaluate a given constant at this point in compilation? Attempting to evaluate
+    /// a const block before borrow-checking will result in a query cycle (#150464).
+    fn should_evaluate_for_promotion_checks(&self, constant: Const<'tcx>) -> bool {
+        match constant {
+            // `Const::Ty` is always a `ConstKind::Param` right now and that can never be turned
+            // into a mir value for promotion
+            // FIXME(mgca): do we want uses of type_const to be normalized during promotion?
+            Const::Ty(..) => false,
+            Const::Val(..) => true,
+            // Evaluating a MIR constant requires borrow-checking it. For inline consts, as of
+            // #138499, this means borrow-checking its typeck root. Since borrow-checking the
+            // typeck root requires promoting its constants, trying to evaluate an inline const here
+            // will result in a query cycle. To avoid the cycle, we can't evaluate const blocks yet.
+            // Other kinds of unevaluated's can cause query cycles too when they arise from
+            // self-reference in user code; e.g. evaluating a constant can require evaluating a
+            // const function that uses that constant, again requiring evaluation of the constant.
+            // However, this form of cycle renders both the constant and function unusable in
+            // general, so we don't need to special-case it here.
+            Const::Unevaluated(uc, _) => self.tcx.def_kind(uc.def) != DefKind::InlineConst,
+        }
+    }
 }
 
 fn validate_candidates(
diff --git a/tests/ui/inline-const/dont-eval-const-block-during-promotion.fail.stderr b/tests/ui/inline-const/dont-eval-const-block-during-promotion.fail.stderr
new file mode 100644
index 000000000000..a4d133cbc011
--- /dev/null
+++ b/tests/ui/inline-const/dont-eval-const-block-during-promotion.fail.stderr
@@ -0,0 +1,42 @@
+error[E0716]: temporary value dropped while borrowed
+  --> $DIR/dont-eval-const-block-during-promotion.rs:48:14
+   |
+LL |         x = &([0][const { 0 }] & 0);
+   |              ^^^^^^^^^^^^^^^^^^^^^^- temporary value is freed at the end of this statement
+   |              |
+   |              creates a temporary value which is freed while still in use
+...
+LL |         (x, y, z);
+   |          - borrow later used here
+   |
+   = note: consider using a `let` binding to create a longer lived value
+
+error[E0716]: temporary value dropped while borrowed
+  --> $DIR/dont-eval-const-block-during-promotion.rs:50:14
+   |
+LL |         y = &(1 / const { 1 });
+   |              ^^^^^^^^^^^^^^^^^- temporary value is freed at the end of this statement
+   |              |
+   |              creates a temporary value which is freed while still in use
+...
+LL |         (x, y, z);
+   |             - borrow later used here
+   |
+   = note: consider using a `let` binding to create a longer lived value
+
+error[E0716]: temporary value dropped while borrowed
+  --> $DIR/dont-eval-const-block-during-promotion.rs:52:14
+   |
+LL |         z = &(const { 1 } / -1);
+   |              ^^^^^^^^^^^^^^^^^^- temporary value is freed at the end of this statement
+   |              |
+   |              creates a temporary value which is freed while still in use
+LL |
+LL |         (x, y, z);
+   |                - borrow later used here
+   |
+   = note: consider using a `let` binding to create a longer lived value
+
+error: aborting due to 3 previous errors
+
+For more information about this error, try `rustc --explain E0716`.
diff --git a/tests/ui/inline-const/dont-eval-const-block-during-promotion.rs b/tests/ui/inline-const/dont-eval-const-block-during-promotion.rs
new file mode 100644
index 000000000000..3ecf7acf8edc
--- /dev/null
+++ b/tests/ui/inline-const/dont-eval-const-block-during-promotion.rs
@@ -0,0 +1,65 @@
+//! Test for #150464: as of #138499, trying to evaluate const blocks during constant promotion will
+//! result in a query cycle, so we shouldn't do it. Evaluation can happen when trying to promote
+//! integer division and array indexing, where it's necessary for the operation to succeed to be
+//! able to use it in a promoted constant.
+//@ revisions: pass fail
+//@[pass] check-pass
+
+use std::mem::offset_of;
+
+struct Thing(i32);
+
+fn main() {
+    // For a temporary involving array indexing to be promoted, we evaluate the index to make sure
+    // it's in-bounds. As of #150557 we treat inline constants as maybe-out-of-bounds to avoid the
+    // query cycle from evaluating them. That allows this to compile:
+    let x = &([0][const { 0 }] & 0);
+    // Likewise, integer divisors must be nonzero. Avoiding the query cycle allows this to compile:
+    let y = &(1 / const { 1 });
+    // Likewise, signed integer dividends can't be the integer minimum when the divisor is -1.
+    let z = &(const { 1 } / -1);
+    // These temporaries are all lifetime-extended, so they don't need to be promoted for references
+    // to them to be live later in the block. Generally, code with const blocks in these positions
+    // should compile as long as being promoted isn't necessary for borrow-checking to succeed.
+    (x, y, z);
+
+    // A reduced example from real code (#150464): this can't be promoted since the array is a local
+    // variable, but it still resulted in a query cycle because the index was evaluated for the
+    // bounds-check before checking that. By not evaluating the const block, we avoid the cycle.
+    // Since this doesn't rely on promotion, it should borrow-check successfully.
+    let temp = [0u8];
+    let _ = &(temp[const { 0usize }] & 0u8);
+    // #150464 was reported because `offset_of!` started desugaring to a const block in #148151.
+    let _ = &(temp[offset_of!(Thing, 0)] & 0u8);
+
+    // Similarly, at the time #150464 was reported, the index here was evaluated before checking
+    // that the indexed expression is an array. As above, this can't be promoted, but still resulted
+    // in a query cycle. By not evaluating the const block, we avoid the cycle. Since this doesn't
+    // rely on promotion, it should borrow-check successfully.
+    let temp: &[u8] = &[0u8];
+    let _ = &(temp[const { 0usize }] & 0u8);
+
+    // By no longer promoting these temporaries, they're dropped at the ends of their respective
+    // statements, so we can't refer to them thereafter. This code no longer query-cycles, but it
+    // fails to borrow-check instead.
+    #[cfg(fail)]
+    {
+        let (x, y, z);
+        x = &([0][const { 0 }] & 0);
+        //[fail]~^ ERROR: temporary value dropped while borrowed
+        y = &(1 / const { 1 });
+        //[fail]~^ ERROR: temporary value dropped while borrowed
+        z = &(const { 1 } / -1);
+        //[fail]~^ ERROR: temporary value dropped while borrowed
+        (x, y, z);
+    }
+
+    // Sanity check: those temporaries do promote if the const blocks are removed.
+    // If constant promotion is changed so that these are no longer implicitly promoted, the
+    // comments on this test file should be reworded to reflect that.
+    let (x, y, z);
+    x = &([0][0] & 0);
+    y = &(1 / 1);
+    z = &(1 / -1);
+    (x, y, z);
+}

From a8e91473c5bc1261487079db19e7fbfa19ac33f5 Mon Sep 17 00:00:00 2001
From: Vadim Petrochenkov <vadim.petrochenkov@gmail.com>
Date: Sun, 28 Dec 2025 23:11:15 +0300
Subject: [PATCH 73/97] tests: Reproduce the issue with missing MIR for
 ambiguous reexports

---
 tests/ui/imports/ambiguous-reachable.rs       | 10 ++++++
 tests/ui/imports/ambiguous-reachable.stderr   | 31 +++++++++++++++++++
 .../auxiliary/ambiguous-reachable-extern.rs   | 14 +++++++++
 3 files changed, 55 insertions(+)
 create mode 100644 tests/ui/imports/ambiguous-reachable.rs
 create mode 100644 tests/ui/imports/ambiguous-reachable.stderr
 create mode 100644 tests/ui/imports/auxiliary/ambiguous-reachable-extern.rs

diff --git a/tests/ui/imports/ambiguous-reachable.rs b/tests/ui/imports/ambiguous-reachable.rs
new file mode 100644
index 000000000000..1ca31c402ae6
--- /dev/null
+++ b/tests/ui/imports/ambiguous-reachable.rs
@@ -0,0 +1,10 @@
+//@ build-fail
+//@ aux-crate: ambiguous_reachable_extern=ambiguous-reachable-extern.rs
+
+#![allow(ambiguous_glob_imports)]
+
+fn main() {
+    ambiguous_reachable_extern::generic::<u8>();
+}
+
+//~? ERROR missing optimized MIR
diff --git a/tests/ui/imports/ambiguous-reachable.stderr b/tests/ui/imports/ambiguous-reachable.stderr
new file mode 100644
index 000000000000..5ba00970a23a
--- /dev/null
+++ b/tests/ui/imports/ambiguous-reachable.stderr
@@ -0,0 +1,31 @@
+error: missing optimized MIR for `ambiguous_reachable_extern::m1::generic::<u8>` in the crate `ambiguous_reachable_extern`
+   |
+note: missing optimized MIR for this item (was the crate `ambiguous_reachable_extern` compiled with `--emit=metadata`?)
+  --> $DIR/auxiliary/ambiguous-reachable-extern.rs:2:5
+   |
+LL |     pub fn generic<T>() {
+   |     ^^^^^^^^^^^^^^^^^^^
+
+error: aborting due to 1 previous error
+
+Future incompatibility report: Future breakage diagnostic:
+warning: `generic` is ambiguous
+  --> $DIR/ambiguous-reachable.rs:7:33
+   |
+LL |     ambiguous_reachable_extern::generic::<u8>();
+   |                                 ^^^^^^^ ambiguous name
+   |
+   = warning: this was previously accepted by the compiler but is being phased out; it will become a hard error in a future release!
+   = note: for more information, see issue #114095 <https://github.com/rust-lang/rust/issues/114095>
+   = note: ambiguous because of multiple glob imports of a name in the same module
+note: `generic` could refer to the function defined here
+  --> $DIR/auxiliary/ambiguous-reachable-extern.rs:13:9
+   |
+LL | pub use m1::*;
+   |         ^^
+note: `generic` could also refer to the function defined here
+  --> $DIR/auxiliary/ambiguous-reachable-extern.rs:14:9
+   |
+LL | pub use m2::*;
+   |         ^^
+
diff --git a/tests/ui/imports/auxiliary/ambiguous-reachable-extern.rs b/tests/ui/imports/auxiliary/ambiguous-reachable-extern.rs
new file mode 100644
index 000000000000..af81812560e3
--- /dev/null
+++ b/tests/ui/imports/auxiliary/ambiguous-reachable-extern.rs
@@ -0,0 +1,14 @@
+mod m1 {
+    pub fn generic<T>() {
+        let x = 10;
+        let y = 11;
+        println!("hello {x} world {:?}", y);
+    }
+}
+
+mod m2 {
+    pub fn generic() {}
+}
+
+pub use m1::*;
+pub use m2::*;

From 4bdccabda5ab612f07eadfde96915bf0edd61e95 Mon Sep 17 00:00:00 2001
From: Amanda Stjerna <amanda.stjerna@it.uu.se>
Date: Mon, 26 Jan 2026 17:02:31 +0100
Subject: [PATCH 74/97] Borrowck: Simplify SCC annotation computation,
 placeholder rewriting

This simplifies the `PlaceholderReachability` `enum` by
replacing the case when no placeholders were reached with
a standard `Option::None`.

It also rewrites the API for `scc::Annotations` to be update-mut
rather than a more Functional programming style. This showed some slight
performance impact in early tests of the PR and definitely makes
the implementation simpler.
---
 .../rustc_borrowck/src/handle_placeholders.rs | 111 +++++++-----------
 .../src/graph/scc/mod.rs                      |  28 ++---
 .../src/graph/scc/tests.rs                    |  17 ++-
 3 files changed, 56 insertions(+), 100 deletions(-)

diff --git a/compiler/rustc_borrowck/src/handle_placeholders.rs b/compiler/rustc_borrowck/src/handle_placeholders.rs
index 60be521c29af..2a7dc8ba1016 100644
--- a/compiler/rustc_borrowck/src/handle_placeholders.rs
+++ b/compiler/rustc_borrowck/src/handle_placeholders.rs
@@ -62,57 +62,23 @@ impl scc::Annotations<RegionVid> for SccAnnotations<'_, '_, RegionTracker> {
 }
 
 #[derive(Copy, Debug, Clone, PartialEq, Eq)]
-enum PlaceholderReachability {
-    /// This SCC reaches no placeholders.
-    NoPlaceholders,
-    /// This SCC reaches at least one placeholder.
-    Placeholders {
-        /// The largest-universed placeholder we can reach
-        max_universe: (UniverseIndex, RegionVid),
+struct PlaceholderReachability {
+    /// The largest-universed placeholder we can reach
+    max_universe: (UniverseIndex, RegionVid),
 
-        /// The placeholder with the smallest ID
-        min_placeholder: RegionVid,
+    /// The placeholder with the smallest ID
+    min_placeholder: RegionVid,
 
-        /// The placeholder with the largest ID
-        max_placeholder: RegionVid,
-    },
+    /// The placeholder with the largest ID
+    max_placeholder: RegionVid,
 }
 
 impl PlaceholderReachability {
     /// Merge the reachable placeholders of two graph components.
-    fn merge(self, other: PlaceholderReachability) -> PlaceholderReachability {
-        use PlaceholderReachability::*;
-        match (self, other) {
-            (NoPlaceholders, NoPlaceholders) => NoPlaceholders,
-            (NoPlaceholders, p @ Placeholders { .. })
-            | (p @ Placeholders { .. }, NoPlaceholders) => p,
-            (
-                Placeholders {
-                    min_placeholder: min_pl,
-                    max_placeholder: max_pl,
-                    max_universe: max_u,
-                },
-                Placeholders { min_placeholder, max_placeholder, max_universe },
-            ) => Placeholders {
-                min_placeholder: min_pl.min(min_placeholder),
-                max_placeholder: max_pl.max(max_placeholder),
-                max_universe: max_u.max(max_universe),
-            },
-        }
-    }
-
-    fn max_universe(&self) -> Option<(UniverseIndex, RegionVid)> {
-        match self {
-            Self::NoPlaceholders => None,
-            Self::Placeholders { max_universe, .. } => Some(*max_universe),
-        }
-    }
-
-    /// If we have reached placeholders, determine if they can
-    /// be named from this universe.
-    fn can_be_named_by(&self, from: UniverseIndex) -> bool {
-        self.max_universe()
-            .is_none_or(|(max_placeholder_universe, _)| from.can_name(max_placeholder_universe))
+    fn merge(&mut self, other: &Self) {
+        self.max_universe = self.max_universe.max(other.max_universe);
+        self.min_placeholder = self.min_placeholder.min(other.min_placeholder);
+        self.max_placeholder = self.max_placeholder.max(other.max_placeholder);
     }
 }
 
@@ -120,7 +86,7 @@ impl PlaceholderReachability {
 /// the values of its elements. This annotates a single SCC.
 #[derive(Copy, Debug, Clone)]
 pub(crate) struct RegionTracker {
-    reachable_placeholders: PlaceholderReachability,
+    reachable_placeholders: Option<PlaceholderReachability>,
 
     /// The largest universe nameable from this SCC.
     /// It is the smallest nameable universes of all
@@ -135,13 +101,13 @@ impl RegionTracker {
     pub(crate) fn new(rvid: RegionVid, definition: &RegionDefinition<'_>) -> Self {
         let reachable_placeholders =
             if matches!(definition.origin, NllRegionVariableOrigin::Placeholder(_)) {
-                PlaceholderReachability::Placeholders {
+                Some(PlaceholderReachability {
                     max_universe: (definition.universe, rvid),
                     min_placeholder: rvid,
                     max_placeholder: rvid,
-                }
+                })
             } else {
-                PlaceholderReachability::NoPlaceholders
+                None
             };
 
         Self {
@@ -159,43 +125,46 @@ impl RegionTracker {
     }
 
     pub(crate) fn max_placeholder_universe_reached(self) -> UniverseIndex {
-        if let Some((universe, _)) = self.reachable_placeholders.max_universe() {
-            universe
-        } else {
-            UniverseIndex::ROOT
-        }
+        self.reachable_placeholders.map(|pls| pls.max_universe.0).unwrap_or(UniverseIndex::ROOT)
+    }
+
+    /// Can all reachable placeholders be named from `from`?
+    /// True vacuously in case no placeholders were reached.
+    fn placeholders_can_be_named_by(&self, from: UniverseIndex) -> bool {
+        self.reachable_placeholders.is_none_or(|pls| from.can_name(pls.max_universe.0))
     }
 
     /// Determine if we can name all the placeholders in `other`.
     pub(crate) fn can_name_all_placeholders(&self, other: Self) -> bool {
-        other.reachable_placeholders.can_be_named_by(self.max_nameable_universe.0)
+        // HACK: We first check whether we can name the highest existential universe
+        // of `other`. This only exists to avoid errors in case that scc already
+        // depends on a placeholder it cannot name itself.
+        self.max_nameable_universe().can_name(other.max_nameable_universe())
+            || other.placeholders_can_be_named_by(self.max_nameable_universe.0)
     }
 
     /// If this SCC reaches a placeholder it can't name, return it.
     fn unnameable_placeholder(&self) -> Option<(UniverseIndex, RegionVid)> {
-        self.reachable_placeholders.max_universe().filter(|&(placeholder_universe, _)| {
-            !self.max_nameable_universe().can_name(placeholder_universe)
-        })
+        self.reachable_placeholders
+            .filter(|pls| !self.max_nameable_universe().can_name(pls.max_universe.0))
+            .map(|pls| pls.max_universe)
     }
 }
 
 impl scc::Annotation for RegionTracker {
-    fn merge_scc(self, other: Self) -> Self {
+    fn update_scc(&mut self, other: &Self) {
         trace!("{:?} << {:?}", self.representative, other.representative);
-
-        Self {
-            representative: self.representative.min(other.representative),
-            max_nameable_universe: self.max_nameable_universe.min(other.max_nameable_universe),
-            reachable_placeholders: self.reachable_placeholders.merge(other.reachable_placeholders),
-        }
+        self.representative = self.representative.min(other.representative);
+        self.update_reachable(other);
     }
 
-    fn merge_reached(self, other: Self) -> Self {
-        Self {
-            max_nameable_universe: self.max_nameable_universe.min(other.max_nameable_universe),
-            reachable_placeholders: self.reachable_placeholders.merge(other.reachable_placeholders),
-            representative: self.representative,
-        }
+    fn update_reachable(&mut self, other: &Self) {
+        self.max_nameable_universe = self.max_nameable_universe.min(other.max_nameable_universe);
+        match (self.reachable_placeholders.as_mut(), other.reachable_placeholders.as_ref()) {
+            (None, None) | (Some(_), None) => (),
+            (None, Some(theirs)) => self.reachable_placeholders = Some(*theirs),
+            (Some(ours), Some(theirs)) => ours.merge(theirs),
+        };
     }
 }
 
diff --git a/compiler/rustc_data_structures/src/graph/scc/mod.rs b/compiler/rustc_data_structures/src/graph/scc/mod.rs
index 91cbe3c533bb..954e4116fb55 100644
--- a/compiler/rustc_data_structures/src/graph/scc/mod.rs
+++ b/compiler/rustc_data_structures/src/graph/scc/mod.rs
@@ -27,26 +27,18 @@ mod tests;
 /// the max/min element of the SCC, or all of the above.
 ///
 /// Concretely, the both merge operations must commute, e.g. where `merge`
-/// is `merge_scc` and `merge_reached`: `a.merge(b) == b.merge(a)`
+/// is `update_scc` and `update_reached`: `a.merge(b) == b.merge(a)`
 ///
 /// In general, what you want is probably always min/max according
 /// to some ordering, potentially with side constraints (min x such
 /// that P holds).
 pub trait Annotation: Debug + Copy {
     /// Merge two existing annotations into one during
-    /// path compression.o
-    fn merge_scc(self, other: Self) -> Self;
+    /// path compression.
+    fn update_scc(&mut self, other: &Self);
 
     /// Merge a successor into this annotation.
-    fn merge_reached(self, other: Self) -> Self;
-
-    fn update_scc(&mut self, other: Self) {
-        *self = self.merge_scc(other)
-    }
-
-    fn update_reachable(&mut self, other: Self) {
-        *self = self.merge_reached(other)
-    }
+    fn update_reachable(&mut self, other: &Self);
 }
 
 /// An accumulator for annotations.
@@ -70,12 +62,8 @@ impl<N: Idx, S: Idx + Ord> Annotations<N> for NoAnnotations<S> {
 
 /// The empty annotation, which does nothing.
 impl Annotation for () {
-    fn merge_reached(self, _other: Self) -> Self {
-        ()
-    }
-    fn merge_scc(self, _other: Self) -> Self {
-        ()
-    }
+    fn update_reachable(&mut self, _other: &Self) {}
+    fn update_scc(&mut self, _other: &Self) {}
 }
 
 /// Strongly connected components (SCC) of a graph. The type `N` is
@@ -614,7 +602,7 @@ where
                             *min_depth = successor_min_depth;
                             *min_cycle_root = successor_node;
                         }
-                        current_component_annotation.update_scc(successor_annotation);
+                        current_component_annotation.update_scc(&successor_annotation);
                     }
                     // The starting node `node` is succeeded by a fully identified SCC
                     // which is now added to the set under `scc_index`.
@@ -629,7 +617,7 @@ where
                         // the `successors_stack` for later.
                         trace!(?node, ?successor_scc_index);
                         successors_stack.push(successor_scc_index);
-                        current_component_annotation.update_reachable(successor_annotation);
+                        current_component_annotation.update_reachable(&successor_annotation);
                     }
                     // `node` has no more (direct) successors; search recursively.
                     None => {
diff --git a/compiler/rustc_data_structures/src/graph/scc/tests.rs b/compiler/rustc_data_structures/src/graph/scc/tests.rs
index 8f04baf51f35..4626861c3e00 100644
--- a/compiler/rustc_data_structures/src/graph/scc/tests.rs
+++ b/compiler/rustc_data_structures/src/graph/scc/tests.rs
@@ -32,12 +32,12 @@ impl Maxes {
 }
 
 impl Annotation for MaxReached {
-    fn merge_scc(self, other: Self) -> Self {
-        Self(std::cmp::max(other.0, self.0))
+    fn update_scc(&mut self, other: &Self) {
+        self.0 = self.0.max(other.0);
     }
 
-    fn merge_reached(self, other: Self) -> Self {
-        Self(std::cmp::max(other.0, self.0))
+    fn update_reachable(&mut self, other: &Self) {
+        self.0 = self.0.max(other.0);
     }
 }
 
@@ -75,13 +75,12 @@ impl Annotations<usize> for MinMaxes {
 }
 
 impl Annotation for MinMaxIn {
-    fn merge_scc(self, other: Self) -> Self {
-        Self { min: std::cmp::min(self.min, other.min), max: std::cmp::max(self.max, other.max) }
+    fn update_scc(&mut self, other: &Self) {
+        self.min = self.min.min(other.min);
+        self.max = self.max.max(other.max);
     }
 
-    fn merge_reached(self, _other: Self) -> Self {
-        self
-    }
+    fn update_reachable(&mut self, _other: &Self) {}
 }
 
 #[test]

From 44e89f8262c21222ab0fb97cee026d87501b007a Mon Sep 17 00:00:00 2001
From: Vadim Petrochenkov <vadim.petrochenkov@gmail.com>
Date: Thu, 8 Jan 2026 23:48:46 +0300
Subject: [PATCH 75/97] resolve: Mark items under ambigous imports as exported

---
 .../src/effective_visibilities.rs             | 31 +++----------------
 tests/rustdoc-html/glob-shadowing.rs          | 12 ++++---
 tests/rustdoc-json/reexport/glob_collision.rs |  4 ++-
 tests/ui/imports/ambiguous-reachable.rs       |  4 +--
 tests/ui/imports/ambiguous-reachable.stderr   | 12 ++-----
 5 files changed, 18 insertions(+), 45 deletions(-)

diff --git a/compiler/rustc_resolve/src/effective_visibilities.rs b/compiler/rustc_resolve/src/effective_visibilities.rs
index 295635a60547..55518276a4f0 100644
--- a/compiler/rustc_resolve/src/effective_visibilities.rs
+++ b/compiler/rustc_resolve/src/effective_visibilities.rs
@@ -96,13 +96,10 @@ impl<'a, 'ra, 'tcx> EffectiveVisibilitiesVisitor<'a, 'ra, 'tcx> {
         // is the maximum value among visibilities of declarations corresponding to that def id.
         for (decl, eff_vis) in visitor.import_effective_visibilities.iter() {
             let DeclKind::Import { import, .. } = decl.kind else { unreachable!() };
-            if !decl.is_ambiguity_recursive() {
-                if let Some(node_id) = import.id() {
-                    r.effective_visibilities.update_eff_vis(r.local_def_id(node_id), eff_vis, r.tcx)
-                }
-            } else if decl.ambiguity.get().is_some()
-                && eff_vis.is_public_at_level(Level::Reexported)
-            {
+            if let Some(node_id) = import.id() {
+                r.effective_visibilities.update_eff_vis(r.local_def_id(node_id), eff_vis, r.tcx)
+            }
+            if decl.ambiguity.get().is_some() && eff_vis.is_public_at_level(Level::Reexported) {
                 exported_ambiguities.insert(*decl);
             }
         }
@@ -123,31 +120,13 @@ impl<'a, 'ra, 'tcx> EffectiveVisibilitiesVisitor<'a, 'ra, 'tcx> {
             // Set the given effective visibility level to `Level::Direct` and
             // sets the rest of the `use` chain to `Level::Reexported` until
             // we hit the actual exported item.
-            //
-            // If the binding is ambiguous, put the root ambiguity binding and all reexports
-            // leading to it into the table. They are used by the `ambiguous_glob_reexports`
-            // lint. For all bindings added to the table this way `is_ambiguity` returns true.
-            let is_ambiguity =
-                |decl: Decl<'ra>, warn: bool| decl.ambiguity.get().is_some() && !warn;
             let mut parent_id = ParentId::Def(module_id);
-            let mut warn_ambiguity = decl.warn_ambiguity.get();
             while let DeclKind::Import { source_decl, .. } = decl.kind {
                 self.update_import(decl, parent_id);
-
-                if is_ambiguity(decl, warn_ambiguity) {
-                    // Stop at the root ambiguity, further bindings in the chain should not
-                    // be reexported because the root ambiguity blocks any access to them.
-                    // (Those further bindings are most likely not ambiguities themselves.)
-                    break;
-                }
-
                 parent_id = ParentId::Import(decl);
                 decl = source_decl;
-                warn_ambiguity |= source_decl.warn_ambiguity.get();
             }
-            if !is_ambiguity(decl, warn_ambiguity)
-                && let Some(def_id) = decl.res().opt_def_id().and_then(|id| id.as_local())
-            {
+            if let Some(def_id) = decl.res().opt_def_id().and_then(|id| id.as_local()) {
                 self.update_def(def_id, decl.vis().expect_local(), parent_id);
             }
         }
diff --git a/tests/rustdoc-html/glob-shadowing.rs b/tests/rustdoc-html/glob-shadowing.rs
index d9e9ead3f9a9..c1eeb7e663e7 100644
--- a/tests/rustdoc-html/glob-shadowing.rs
+++ b/tests/rustdoc-html/glob-shadowing.rs
@@ -1,9 +1,9 @@
 //@ has 'glob_shadowing/index.html'
-//@ count - '//dt' 6
-//@ !has - '//dd' 'sub1::describe'
+//@ count - '//dt' 7
+//@ !has - '//dd' 'sub1::describe1'
 //@ has - '//dd' 'sub2::describe'
 
-//@ !has - '//dd' 'sub1::describe2'
+//@ has - '//dd' 'sub1::describe2'
 
 //@ !has - '//dd' 'sub1::prelude'
 //@ has - '//dd' 'mod::prelude'
@@ -18,7 +18,7 @@
 
 mod sub1 {
     // this should be shadowed by sub2::describe
-    /// sub1::describe
+    /// sub1::describe1
     pub fn describe() -> &'static str {
         "sub1::describe"
     }
@@ -33,7 +33,9 @@ mod sub1 {
     pub struct Foo;
 
     // this should be shadowed,
-    // because both sub1::describe2 and sub3::describe2 are from glob reexport
+    // because both sub1::describe2 and sub3::describe2 are from glob reexport,
+    // but it is still usable from other crates under the `ambiguous_glob_imports` lint,
+    // so it is reachable and documented
     /// sub1::describe2
     pub fn describe2() -> &'static str {
         "sub1::describe2"
diff --git a/tests/rustdoc-json/reexport/glob_collision.rs b/tests/rustdoc-json/reexport/glob_collision.rs
index 48de1b5e7721..dd6eab6517b0 100644
--- a/tests/rustdoc-json/reexport/glob_collision.rs
+++ b/tests/rustdoc-json/reexport/glob_collision.rs
@@ -1,7 +1,9 @@
 // Regression test for https://github.com/rust-lang/rust/issues/100973
+// Update: the rules has changed after #147984, one of the colliding items is now available
+// from other crates under a deprecation lint.
 
 //@ set m1 = "$.index[?(@.name == 'm1' && @.inner.module)].id"
-//@ is "$.index[?(@.name == 'm1')].inner.module.items" []
+//@ is "$.index[?(@.name == 'm1')].inner.module.items" [0]
 //@ is "$.index[?(@.name == 'm1')].inner.module.is_stripped" true
 mod m1 {
     pub fn f() {}
diff --git a/tests/ui/imports/ambiguous-reachable.rs b/tests/ui/imports/ambiguous-reachable.rs
index 1ca31c402ae6..fc92315622aa 100644
--- a/tests/ui/imports/ambiguous-reachable.rs
+++ b/tests/ui/imports/ambiguous-reachable.rs
@@ -1,4 +1,4 @@
-//@ build-fail
+//@ build-pass
 //@ aux-crate: ambiguous_reachable_extern=ambiguous-reachable-extern.rs
 
 #![allow(ambiguous_glob_imports)]
@@ -6,5 +6,3 @@
 fn main() {
     ambiguous_reachable_extern::generic::<u8>();
 }
-
-//~? ERROR missing optimized MIR
diff --git a/tests/ui/imports/ambiguous-reachable.stderr b/tests/ui/imports/ambiguous-reachable.stderr
index 5ba00970a23a..78a0d76d68b5 100644
--- a/tests/ui/imports/ambiguous-reachable.stderr
+++ b/tests/ui/imports/ambiguous-reachable.stderr
@@ -1,13 +1,3 @@
-error: missing optimized MIR for `ambiguous_reachable_extern::m1::generic::<u8>` in the crate `ambiguous_reachable_extern`
-   |
-note: missing optimized MIR for this item (was the crate `ambiguous_reachable_extern` compiled with `--emit=metadata`?)
-  --> $DIR/auxiliary/ambiguous-reachable-extern.rs:2:5
-   |
-LL |     pub fn generic<T>() {
-   |     ^^^^^^^^^^^^^^^^^^^
-
-error: aborting due to 1 previous error
-
 Future incompatibility report: Future breakage diagnostic:
 warning: `generic` is ambiguous
   --> $DIR/ambiguous-reachable.rs:7:33
@@ -23,6 +13,8 @@ note: `generic` could refer to the function defined here
    |
 LL | pub use m1::*;
    |         ^^
+   = help: consider updating this dependency to resolve this error
+   = help: if updating the dependency does not resolve the problem report the problem to the author of the relevant crate
 note: `generic` could also refer to the function defined here
   --> $DIR/auxiliary/ambiguous-reachable-extern.rs:14:9
    |

From 5726e37819f63b7b9716b4a54efea4378ec85cb0 Mon Sep 17 00:00:00 2001
From: Vadim Petrochenkov <vadim.petrochenkov@gmail.com>
Date: Thu, 22 Jan 2026 16:56:11 +0300
Subject: [PATCH 76/97] resolve: Replace `Macros20NormalizedIdent` with
 `IdentKey`

---
 .../rustc_resolve/src/build_reduced_graph.rs  |  86 ++++----
 compiler/rustc_resolve/src/check_unused.rs    |   6 +-
 compiler/rustc_resolve/src/diagnostics.rs     |  91 ++++-----
 compiler/rustc_resolve/src/errors.rs          |   4 +-
 compiler/rustc_resolve/src/ident.rs           |  91 +++++----
 compiler/rustc_resolve/src/imports.rs         | 167 +++++++++-------
 compiler/rustc_resolve/src/late.rs            |  12 +-
 .../rustc_resolve/src/late/diagnostics.rs     |  42 ++--
 compiler/rustc_resolve/src/lib.rs             | 183 +++++++++++++-----
 compiler/rustc_resolve/src/macros.rs          |  35 ++--
 compiler/rustc_span/src/hygiene.rs            |   8 +-
 compiler/rustc_span/src/lib.rs                |  27 +--
 compiler/rustc_span/src/symbol.rs             |  45 +----
 .../hygiene/cross-crate-name-hiding-2.stderr  |   8 +-
 tests/ui/lint/unused/unused-macros.stderr     |   5 +
 .../dollar-crate-issue-62325.stdout           |  22 +--
 tests/ui/proc-macro/dollar-crate.stdout       |  48 ++---
 tests/ui/proc-macro/generate-mod.stderr       |  10 +
 tests/ui/proc-macro/nested-macro-rules.stdout |  16 +-
 19 files changed, 495 insertions(+), 411 deletions(-)

diff --git a/compiler/rustc_resolve/src/build_reduced_graph.rs b/compiler/rustc_resolve/src/build_reduced_graph.rs
index aa458024b89e..e06ca59771e6 100644
--- a/compiler/rustc_resolve/src/build_reduced_graph.rs
+++ b/compiler/rustc_resolve/src/build_reduced_graph.rs
@@ -26,7 +26,7 @@ use rustc_middle::metadata::{ModChild, Reexport};
 use rustc_middle::ty::{Feed, Visibility};
 use rustc_middle::{bug, span_bug};
 use rustc_span::hygiene::{ExpnId, LocalExpnId, MacroKind};
-use rustc_span::{Ident, Macros20NormalizedIdent, Span, Symbol, kw, sym};
+use rustc_span::{Ident, Span, Symbol, kw, sym};
 use thin_vec::ThinVec;
 use tracing::debug;
 
@@ -36,9 +36,9 @@ use crate::imports::{ImportData, ImportKind};
 use crate::macros::{MacroRulesDecl, MacroRulesScope, MacroRulesScopeRef};
 use crate::ref_mut::CmCell;
 use crate::{
-    BindingKey, Decl, DeclData, DeclKind, ExternPreludeEntry, Finalize, MacroData, Module,
-    ModuleKind, ModuleOrUniformRoot, ParentScope, PathResult, ResolutionError, Resolver, Segment,
-    Used, VisResolutionError, errors,
+    BindingKey, Decl, DeclData, DeclKind, ExternPreludeEntry, Finalize, IdentKey, MacroData,
+    Module, ModuleKind, ModuleOrUniformRoot, ParentScope, PathResult, ResolutionError, Resolver,
+    Segment, Used, VisResolutionError, errors,
 };
 
 type Res = def::Res<NodeId>;
@@ -48,12 +48,15 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> {
     /// and report an error in case of a collision.
     pub(crate) fn plant_decl_into_local_module(
         &mut self,
-        ident: Macros20NormalizedIdent,
+        ident: IdentKey,
+        orig_ident_span: Span,
         ns: Namespace,
         decl: Decl<'ra>,
     ) {
-        if let Err(old_decl) = self.try_plant_decl_into_local_module(ident, ns, decl, false) {
-            self.report_conflict(ident.0, ns, old_decl, decl);
+        if let Err(old_decl) =
+            self.try_plant_decl_into_local_module(ident, orig_ident_span, ns, decl, false)
+        {
+            self.report_conflict(ident, ns, old_decl, decl);
         }
     }
 
@@ -61,7 +64,7 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> {
     fn define_local(
         &mut self,
         parent: Module<'ra>,
-        ident: Ident,
+        orig_ident: Ident,
         ns: Namespace,
         res: Res,
         vis: Visibility,
@@ -69,15 +72,16 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> {
         expn_id: LocalExpnId,
     ) {
         let decl = self.arenas.new_def_decl(res, vis.to_def_id(), span, expn_id, Some(parent));
-        let ident = Macros20NormalizedIdent::new(ident);
-        self.plant_decl_into_local_module(ident, ns, decl);
+        let ident = IdentKey::new(orig_ident);
+        self.plant_decl_into_local_module(ident, orig_ident.span, ns, decl);
     }
 
     /// Create a name definitinon from the given components, and put it into the extern module.
     fn define_extern(
         &self,
         parent: Module<'ra>,
-        ident: Macros20NormalizedIdent,
+        ident: IdentKey,
+        orig_ident_span: Span,
         ns: Namespace,
         child_index: usize,
         res: Res,
@@ -102,7 +106,7 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> {
         let key =
             BindingKey::new_disambiguated(ident, ns, || (child_index + 1).try_into().unwrap()); // 0 indicates no underscore
         if self
-            .resolution_or_default(parent, key)
+            .resolution_or_default(parent, key, orig_ident_span)
             .borrow_mut_unchecked()
             .non_glob_decl
             .replace(decl)
@@ -279,8 +283,8 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> {
                     .unwrap_or_else(|| res.def_id()),
             )
         };
-        let ModChild { ident, res, vis, ref reexport_chain } = *child;
-        let ident = Macros20NormalizedIdent::new(ident);
+        let ModChild { ident: orig_ident, res, vis, ref reexport_chain } = *child;
+        let ident = IdentKey::new(orig_ident);
         let span = child_span(self, reexport_chain, res);
         let res = res.expect_non_local();
         let expansion = parent_scope.expansion;
@@ -293,7 +297,18 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> {
 
         // Record primary definitions.
         let define_extern = |ns| {
-            self.define_extern(parent, ident, ns, child_index, res, vis, span, expansion, ambig)
+            self.define_extern(
+                parent,
+                ident,
+                orig_ident.span,
+                ns,
+                child_index,
+                res,
+                vis,
+                span,
+                expansion,
+                ambig,
+            )
         };
         match res {
             Res::Def(
@@ -533,8 +548,8 @@ impl<'a, 'ra, 'tcx> BuildReducedGraphVisitor<'a, 'ra, 'tcx> {
                 if target.name != kw::Underscore {
                     self.r.per_ns(|this, ns| {
                         if !type_ns_only || ns == TypeNS {
-                            let key = BindingKey::new(Macros20NormalizedIdent::new(target), ns);
-                            this.resolution_or_default(current_module, key)
+                            let key = BindingKey::new(IdentKey::new(target), ns);
+                            this.resolution_or_default(current_module, key, target.span)
                                 .borrow_mut(this)
                                 .single_imports
                                 .insert(import);
@@ -974,7 +989,7 @@ impl<'a, 'ra, 'tcx> BuildReducedGraphVisitor<'a, 'ra, 'tcx> {
         &mut self,
         orig_name: Option<Symbol>,
         item: &Item,
-        ident: Ident,
+        orig_ident: Ident,
         local_def_id: LocalDefId,
         vis: Visibility,
     ) {
@@ -983,7 +998,7 @@ impl<'a, 'ra, 'tcx> BuildReducedGraphVisitor<'a, 'ra, 'tcx> {
         let parent = parent_scope.module;
         let expansion = parent_scope.expansion;
 
-        let (used, module, decl) = if orig_name.is_none() && ident.name == kw::SelfLower {
+        let (used, module, decl) = if orig_name.is_none() && orig_ident.name == kw::SelfLower {
             self.r.dcx().emit_err(errors::ExternCrateSelfRequiresRenaming { span: sp });
             return;
         } else if orig_name == Some(kw::SelfLower) {
@@ -1008,7 +1023,7 @@ impl<'a, 'ra, 'tcx> BuildReducedGraphVisitor<'a, 'ra, 'tcx> {
         })
         .unwrap_or((true, None, self.r.dummy_decl));
         let import = self.r.arenas.alloc_import(ImportData {
-            kind: ImportKind::ExternCrate { source: orig_name, target: ident, id: item.id },
+            kind: ImportKind::ExternCrate { source: orig_name, target: orig_ident, id: item.id },
             root_id: item.id,
             parent_scope,
             imported_module: CmCell::new(module),
@@ -1026,7 +1041,7 @@ impl<'a, 'ra, 'tcx> BuildReducedGraphVisitor<'a, 'ra, 'tcx> {
         }
         self.r.potentially_unused_imports.push(import);
         let import_decl = self.r.new_import_decl(decl, import);
-        let ident = Macros20NormalizedIdent::new(ident);
+        let ident = IdentKey::new(orig_ident);
         if ident.name != kw::Underscore && parent == self.r.graph_root {
             // FIXME: this error is technically unnecessary now when extern prelude is split into
             // two scopes, remove it with lang team approval.
@@ -1045,20 +1060,20 @@ impl<'a, 'ra, 'tcx> BuildReducedGraphVisitor<'a, 'ra, 'tcx> {
                 Entry::Occupied(mut occupied) => {
                     let entry = occupied.get_mut();
                     if entry.item_decl.is_some() {
-                        let msg = format!("extern crate `{ident}` already in extern prelude");
+                        let msg = format!("extern crate `{orig_ident}` already in extern prelude");
                         self.r.tcx.dcx().span_delayed_bug(item.span, msg);
                     } else {
-                        entry.item_decl = Some((import_decl, orig_name.is_some()));
+                        entry.item_decl = Some((import_decl, orig_ident.span, orig_name.is_some()));
                     }
                     entry
                 }
                 Entry::Vacant(vacant) => vacant.insert(ExternPreludeEntry {
-                    item_decl: Some((import_decl, true)),
+                    item_decl: Some((import_decl, orig_ident.span, true)),
                     flag_decl: None,
                 }),
             };
         }
-        self.r.plant_decl_into_local_module(ident, TypeNS, import_decl);
+        self.r.plant_decl_into_local_module(ident, orig_ident.span, TypeNS, import_decl);
     }
 
     /// Constructs the reduced graph for one foreign item.
@@ -1159,7 +1174,7 @@ impl<'a, 'ra, 'tcx> BuildReducedGraphVisitor<'a, 'ra, 'tcx> {
         if let Some(span) = import_all {
             let import = macro_use_import(self, span, false);
             self.r.potentially_unused_imports.push(import);
-            module.for_each_child_mut(self, |this, ident, ns, binding| {
+            module.for_each_child_mut(self, |this, ident, _, ns, binding| {
                 if ns == MacroNS {
                     let import =
                         if this.r.is_accessible_from(binding.vis(), this.parent_scope.module) {
@@ -1270,7 +1285,7 @@ impl<'a, 'ra, 'tcx> BuildReducedGraphVisitor<'a, 'ra, 'tcx> {
         let expansion = parent_scope.expansion;
         let feed = self.r.feed(item.id);
         let def_id = feed.key();
-        let (res, ident, span, macro_rules) = match &item.kind {
+        let (res, orig_ident, span, macro_rules) = match &item.kind {
             ItemKind::MacroDef(ident, def) => {
                 (self.res(def_id), *ident, item.span, def.macro_rules)
             }
@@ -1293,8 +1308,8 @@ impl<'a, 'ra, 'tcx> BuildReducedGraphVisitor<'a, 'ra, 'tcx> {
         self.r.local_macro_def_scopes.insert(def_id, parent_scope.module);
 
         if macro_rules {
-            let ident = Macros20NormalizedIdent::new(ident);
-            self.r.macro_names.insert(ident.0);
+            let ident = IdentKey::new(orig_ident);
+            self.r.macro_names.insert(ident);
             let is_macro_export = ast::attr::contains_name(&item.attrs, sym::macro_export);
             let vis = if is_macro_export {
                 Visibility::Public
@@ -1326,10 +1341,10 @@ impl<'a, 'ra, 'tcx> BuildReducedGraphVisitor<'a, 'ra, 'tcx> {
                 });
                 self.r.import_use_map.insert(import, Used::Other);
                 let import_decl = self.r.new_import_decl(decl, import);
-                self.r.plant_decl_into_local_module(ident, MacroNS, import_decl);
+                self.r.plant_decl_into_local_module(ident, orig_ident.span, MacroNS, import_decl);
             } else {
-                self.r.check_reserved_macro_name(ident.0, res);
-                self.insert_unused_macro(ident.0, def_id, item.id);
+                self.r.check_reserved_macro_name(ident.name, orig_ident.span, res);
+                self.insert_unused_macro(orig_ident, def_id, item.id);
             }
             self.r.feed_visibility(feed, vis);
             let scope = self.r.arenas.alloc_macro_rules_scope(MacroRulesScope::Def(
@@ -1337,6 +1352,7 @@ impl<'a, 'ra, 'tcx> BuildReducedGraphVisitor<'a, 'ra, 'tcx> {
                     parent_macro_rules_scope: parent_scope.macro_rules,
                     decl,
                     ident,
+                    orig_ident_span: orig_ident.span,
                 }),
             ));
             self.r.macro_rules_scopes.insert(def_id, scope);
@@ -1352,9 +1368,9 @@ impl<'a, 'ra, 'tcx> BuildReducedGraphVisitor<'a, 'ra, 'tcx> {
                 _ => self.resolve_visibility(&item.vis),
             };
             if !vis.is_public() {
-                self.insert_unused_macro(ident, def_id, item.id);
+                self.insert_unused_macro(orig_ident, def_id, item.id);
             }
-            self.r.define_local(module, ident, MacroNS, res, vis, span, expansion);
+            self.r.define_local(module, orig_ident, MacroNS, res, vis, span, expansion);
             self.r.feed_visibility(feed, vis);
             self.parent_scope.macro_rules
         }
@@ -1496,7 +1512,7 @@ impl<'a, 'ra, 'tcx> Visitor<'a> for BuildReducedGraphVisitor<'a, 'ra, 'tcx> {
         {
             // Don't add underscore names, they cannot be looked up anyway.
             let impl_def_id = self.r.tcx.local_parent(local_def_id);
-            let key = BindingKey::new(Macros20NormalizedIdent::new(ident), ns);
+            let key = BindingKey::new(IdentKey::new(ident), ns);
             self.r.impl_binding_keys.entry(impl_def_id).or_default().insert(key);
         }
 
diff --git a/compiler/rustc_resolve/src/check_unused.rs b/compiler/rustc_resolve/src/check_unused.rs
index 3724fcfce40f..45fdea82d47b 100644
--- a/compiler/rustc_resolve/src/check_unused.rs
+++ b/compiler/rustc_resolve/src/check_unused.rs
@@ -33,10 +33,10 @@ use rustc_session::lint::BuiltinLintDiag;
 use rustc_session::lint::builtin::{
     MACRO_USE_EXTERN_CRATE, UNUSED_EXTERN_CRATES, UNUSED_IMPORTS, UNUSED_QUALIFICATIONS,
 };
-use rustc_span::{DUMMY_SP, Ident, Macros20NormalizedIdent, Span, kw};
+use rustc_span::{DUMMY_SP, Ident, Span, kw};
 
 use crate::imports::{Import, ImportKind};
-use crate::{DeclKind, LateDecl, Resolver, module_to_string};
+use crate::{DeclKind, IdentKey, LateDecl, Resolver, module_to_string};
 
 struct UnusedImport {
     use_tree: ast::UseTree,
@@ -203,7 +203,7 @@ impl<'a, 'ra, 'tcx> UnusedImportCheckVisitor<'a, 'ra, 'tcx> {
             if self
                 .r
                 .extern_prelude
-                .get(&Macros20NormalizedIdent::new(extern_crate.ident))
+                .get(&IdentKey::new(extern_crate.ident))
                 .is_none_or(|entry| entry.introduced_by_item())
             {
                 continue;
diff --git a/compiler/rustc_resolve/src/diagnostics.rs b/compiler/rustc_resolve/src/diagnostics.rs
index a5b3def4b5f8..5c401c3bf828 100644
--- a/compiler/rustc_resolve/src/diagnostics.rs
+++ b/compiler/rustc_resolve/src/diagnostics.rs
@@ -32,9 +32,7 @@ use rustc_span::edit_distance::find_best_match_for_name;
 use rustc_span::edition::Edition;
 use rustc_span::hygiene::MacroKind;
 use rustc_span::source_map::{SourceMap, Spanned};
-use rustc_span::{
-    BytePos, DUMMY_SP, Ident, Macros20NormalizedIdent, Span, Symbol, SyntaxContext, kw, sym,
-};
+use rustc_span::{BytePos, DUMMY_SP, Ident, Span, Symbol, SyntaxContext, kw, sym};
 use thin_vec::{ThinVec, thin_vec};
 use tracing::{debug, instrument};
 
@@ -47,10 +45,10 @@ use crate::imports::{Import, ImportKind};
 use crate::late::{DiagMetadata, PatternSource, Rib};
 use crate::{
     AmbiguityError, AmbiguityKind, AmbiguityWarning, BindingError, BindingKey, Decl, DeclKind,
-    Finalize, ForwardGenericParamBanReason, HasGenericParams, LateDecl, MacroRulesScope, Module,
-    ModuleKind, ModuleOrUniformRoot, ParentScope, PathResult, PrivacyError, ResolutionError,
-    Resolver, Scope, ScopeSet, Segment, UseError, Used, VisResolutionError, errors as errs,
-    path_names_to_string,
+    Finalize, ForwardGenericParamBanReason, HasGenericParams, IdentKey, LateDecl, MacroRulesScope,
+    Module, ModuleKind, ModuleOrUniformRoot, ParentScope, PathResult, PrivacyError,
+    ResolutionError, Resolver, Scope, ScopeSet, Segment, UseError, Used, VisResolutionError,
+    errors as errs, path_names_to_string,
 };
 
 type Res = def::Res<ast::NodeId>;
@@ -81,24 +79,14 @@ pub(crate) struct TypoSuggestion {
 }
 
 impl TypoSuggestion {
-    pub(crate) fn typo_from_ident(ident: Ident, res: Res) -> TypoSuggestion {
-        Self {
-            candidate: ident.name,
-            span: Some(ident.span),
-            res,
-            target: SuggestionTarget::SimilarlyNamed,
-        }
+    pub(crate) fn new(candidate: Symbol, span: Span, res: Res) -> TypoSuggestion {
+        Self { candidate, span: Some(span), res, target: SuggestionTarget::SimilarlyNamed }
     }
     pub(crate) fn typo_from_name(candidate: Symbol, res: Res) -> TypoSuggestion {
         Self { candidate, span: None, res, target: SuggestionTarget::SimilarlyNamed }
     }
-    pub(crate) fn single_item_from_ident(ident: Ident, res: Res) -> TypoSuggestion {
-        Self {
-            candidate: ident.name,
-            span: Some(ident.span),
-            res,
-            target: SuggestionTarget::SingleItem,
-        }
+    pub(crate) fn single_item(candidate: Symbol, span: Span, res: Res) -> TypoSuggestion {
+        Self { candidate, span: Some(span), res, target: SuggestionTarget::SingleItem }
     }
 }
 
@@ -212,7 +200,7 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> {
 
     pub(crate) fn report_conflict(
         &mut self,
-        ident: Ident,
+        ident: IdentKey,
         ns: Namespace,
         old_binding: Decl<'ra>,
         new_binding: Decl<'ra>,
@@ -324,10 +312,8 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> {
         // Check if the target of the use for both bindings is the same.
         let duplicate = new_binding.res().opt_def_id() == old_binding.res().opt_def_id();
         let has_dummy_span = new_binding.span.is_dummy() || old_binding.span.is_dummy();
-        let from_item = self
-            .extern_prelude
-            .get(&Macros20NormalizedIdent::new(ident))
-            .is_none_or(|entry| entry.introduced_by_item());
+        let from_item =
+            self.extern_prelude.get(&ident).is_none_or(|entry| entry.introduced_by_item());
         // Only suggest removing an import if both bindings are to the same def, if both spans
         // aren't dummy spans. Further, if both bindings are imports, then the ident must have
         // been introduced by an item.
@@ -531,10 +517,10 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> {
         filter_fn: &impl Fn(Res) -> bool,
         ctxt: Option<SyntaxContext>,
     ) {
-        module.for_each_child(self, |_this, ident, _ns, binding| {
+        module.for_each_child(self, |_this, ident, orig_ident_span, _ns, binding| {
             let res = binding.res();
-            if filter_fn(res) && ctxt.is_none_or(|ctxt| ctxt == ident.span.ctxt()) {
-                names.push(TypoSuggestion::typo_from_ident(ident.0, res));
+            if filter_fn(res) && ctxt.is_none_or(|ctxt| ctxt == *ident.ctxt) {
+                names.push(TypoSuggestion::new(ident.name, orig_ident_span, res));
             }
         });
     }
@@ -1187,11 +1173,11 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> {
                     let res = Res::NonMacroAttr(NonMacroAttrKind::DeriveHelper);
                     if filter_fn(res) {
                         suggestions.extend(
-                            this.helper_attrs
-                                .get(&expn_id)
-                                .into_iter()
-                                .flatten()
-                                .map(|(ident, _)| TypoSuggestion::typo_from_ident(ident.0, res)),
+                            this.helper_attrs.get(&expn_id).into_iter().flatten().map(
+                                |&(ident, orig_ident_span, _)| {
+                                    TypoSuggestion::new(ident.name, orig_ident_span, res)
+                                },
+                            ),
                         );
                     }
                 }
@@ -1202,8 +1188,11 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> {
                     if let MacroRulesScope::Def(macro_rules_def) = macro_rules_scope.get() {
                         let res = macro_rules_def.decl.res();
                         if filter_fn(res) {
-                            suggestions
-                                .push(TypoSuggestion::typo_from_ident(macro_rules_def.ident.0, res))
+                            suggestions.push(TypoSuggestion::new(
+                                macro_rules_def.ident.name,
+                                macro_rules_def.orig_ident_span,
+                                res,
+                            ))
                         }
                     }
                 }
@@ -1233,9 +1222,9 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> {
                 }
                 Scope::ExternPreludeItems => {
                     // Add idents from both item and flag scopes.
-                    suggestions.extend(this.extern_prelude.keys().filter_map(|ident| {
+                    suggestions.extend(this.extern_prelude.iter().filter_map(|(ident, entry)| {
                         let res = Res::Def(DefKind::Mod, CRATE_DEF_ID.to_def_id());
-                        filter_fn(res).then_some(TypoSuggestion::typo_from_ident(ident.0, res))
+                        filter_fn(res).then_some(TypoSuggestion::new(ident.name, entry.span(), res))
                     }));
                 }
                 Scope::ExternPreludeFlags => {}
@@ -1244,7 +1233,7 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> {
                     suggestions.extend(
                         this.registered_tools
                             .iter()
-                            .map(|ident| TypoSuggestion::typo_from_ident(*ident, res)),
+                            .map(|ident| TypoSuggestion::new(ident.name, ident.span, res)),
                     );
                 }
                 Scope::StdLibPrelude => {
@@ -1329,7 +1318,7 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> {
             }
         {
             let in_module_is_extern = !in_module.def_id().is_local();
-            in_module.for_each_child(self, |this, ident, ns, name_binding| {
+            in_module.for_each_child(self, |this, ident, orig_ident_span, ns, name_binding| {
                 // Avoid non-importable candidates.
                 if name_binding.is_assoc_item()
                     && !this.tcx.features().import_trait_associated_functions()
@@ -1382,7 +1371,7 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> {
                 if ident.name == lookup_ident.name
                     && ns == namespace
                     && in_module != parent_scope.module
-                    && !ident.span.normalize_to_macros_2_0().from_expansion()
+                    && ident.ctxt.is_root()
                     && filter_fn(res)
                 {
                     // create the path
@@ -1395,7 +1384,7 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> {
                     };
                     segms.append(&mut path_segments.clone());
 
-                    segms.push(ast::PathSegment::from_ident(ident.0));
+                    segms.push(ast::PathSegment::from_ident(ident.orig(orig_ident_span)));
                     let path = Path { span: name_binding.span, segments: segms, tokens: None };
 
                     if child_accessible
@@ -1468,7 +1457,7 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> {
                 if let Some(def_id) = name_binding.res().module_like_def_id() {
                     // form the path
                     let mut path_segments = path_segments.clone();
-                    path_segments.push(ast::PathSegment::from_ident(ident.0));
+                    path_segments.push(ast::PathSegment::from_ident(ident.orig(orig_ident_span)));
 
                     let alias_import = if let DeclKind::Import { import, .. } = name_binding.kind
                         && let ImportKind::ExternCrate { source: Some(_), .. } = import.kind
@@ -1557,8 +1546,8 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> {
         );
 
         if lookup_ident.span.at_least_rust_2018() {
-            for &ident in self.extern_prelude.keys() {
-                if ident.span.from_expansion() {
+            for (ident, entry) in &self.extern_prelude {
+                if entry.span().from_expansion() {
                     // Idents are adjusted to the root context before being
                     // resolved in the extern prelude, so reporting this to the
                     // user is no help. This skips the injected
@@ -1582,7 +1571,7 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> {
                     self.resolutions(parent_scope.module).borrow().iter().any(
                         |(key, name_resolution)| {
                             if key.ns == TypeNS
-                                && key.ident == ident
+                                && key.ident == *ident
                                 && let Some(decl) = name_resolution.borrow().best_decl()
                             {
                                 match decl.res() {
@@ -1601,7 +1590,7 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> {
                 if needs_disambiguation {
                     crate_path.push(ast::PathSegment::path_root(rustc_span::DUMMY_SP));
                 }
-                crate_path.push(ast::PathSegment::from_ident(ident.0));
+                crate_path.push(ast::PathSegment::from_ident(ident.orig(entry.span())));
 
                 suggestions.extend(self.lookup_import_candidates_from_module(
                     lookup_ident,
@@ -1777,7 +1766,7 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> {
             return;
         }
 
-        if self.macro_names.contains(&ident.normalize_to_macros_2_0()) {
+        if self.macro_names.contains(&IdentKey::new(ident)) {
             err.subdiagnostic(AddedMacroUse);
             return;
         }
@@ -2007,8 +1996,8 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> {
             matches!(scope2, Scope::ExternPreludeFlags)
                 && self
                     .extern_prelude
-                    .get(&Macros20NormalizedIdent::new(ident))
-                    .is_some_and(|entry| entry.item_decl.map(|(b, _)| b) == Some(b1))
+                    .get(&IdentKey::new(ident))
+                    .is_some_and(|entry| entry.item_decl.map(|(b, ..)| b) == Some(b1))
         };
         let (b1, b2, scope1, scope2, swapped) = if b2.span.is_dummy() && !b1.span.is_dummy() {
             // We have to print the span-less alternative first, otherwise formatting looks bad.
@@ -2914,7 +2903,7 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> {
             return None;
         }
 
-        let binding_key = BindingKey::new(Macros20NormalizedIdent::new(ident), MacroNS);
+        let binding_key = BindingKey::new(IdentKey::new(ident), MacroNS);
         let binding = self.resolution(crate_module, binding_key)?.binding()?;
         let Res::Def(DefKind::Macro(kinds), _) = binding.res() else {
             return None;
diff --git a/compiler/rustc_resolve/src/errors.rs b/compiler/rustc_resolve/src/errors.rs
index d614219e8eab..205f2c6aa539 100644
--- a/compiler/rustc_resolve/src/errors.rs
+++ b/compiler/rustc_resolve/src/errors.rs
@@ -601,7 +601,7 @@ pub(crate) struct ProcMacroDeriveResolutionFallback {
     #[label]
     pub span: Span,
     pub ns_descr: &'static str,
-    pub ident: Ident,
+    pub ident: Symbol,
 }
 
 #[derive(LintDiagnostic)]
@@ -1151,7 +1151,7 @@ pub(crate) struct CannotUseThroughAnImport {
 pub(crate) struct NameReservedInAttributeNamespace {
     #[primary_span]
     pub(crate) span: Span,
-    pub(crate) ident: Ident,
+    pub(crate) ident: Symbol,
 }
 
 #[derive(Diagnostic)]
diff --git a/compiler/rustc_resolve/src/ident.rs b/compiler/rustc_resolve/src/ident.rs
index 78c6cf39b630..26dca5e6e508 100644
--- a/compiler/rustc_resolve/src/ident.rs
+++ b/compiler/rustc_resolve/src/ident.rs
@@ -10,11 +10,12 @@ use rustc_session::lint::builtin::PROC_MACRO_DERIVE_RESOLUTION_FALLBACK;
 use rustc_session::parse::feature_err;
 use rustc_span::edition::Edition;
 use rustc_span::hygiene::{ExpnId, ExpnKind, LocalExpnId, MacroKind, SyntaxContext};
-use rustc_span::{Ident, Macros20NormalizedIdent, Span, kw, sym};
+use rustc_span::{Ident, Span, kw, sym};
 use smallvec::SmallVec;
 use tracing::{debug, instrument};
 
 use crate::errors::{ParamKindInEnumDiscriminant, ParamKindInNonTrivialAnonConst};
+use crate::hygiene::Macros20NormalizedSyntaxContext;
 use crate::imports::{Import, NameResolution};
 use crate::late::{
     ConstantHasGenerics, DiagMetadata, NoConstantGenericsReason, PathSource, Rib, RibKind,
@@ -22,7 +23,7 @@ use crate::late::{
 use crate::macros::{MacroRulesScope, sub_namespace_match};
 use crate::{
     AmbiguityError, AmbiguityKind, AmbiguityWarning, BindingKey, CmResolver, Decl, DeclKind,
-    Determinacy, Finalize, ImportKind, LateDecl, Module, ModuleKind, ModuleOrUniformRoot,
+    Determinacy, Finalize, IdentKey, ImportKind, LateDecl, Module, ModuleKind, ModuleOrUniformRoot,
     ParentScope, PathResult, PrivacyError, Res, ResolutionError, Resolver, Scope, ScopeSet,
     Segment, Stage, Used, errors,
 };
@@ -61,7 +62,7 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> {
             CmResolver<'_, 'ra, 'tcx>,
             Scope<'ra>,
             UsePrelude,
-            Span,
+            Macros20NormalizedSyntaxContext,
         ) -> ControlFlow<T>,
     ) -> Option<T> {
         // General principles:
@@ -127,7 +128,7 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> {
             TypeNS | ValueNS => Scope::ModuleNonGlobs(module, None),
             MacroNS => Scope::DeriveHelpers(parent_scope.expansion),
         };
-        let mut ctxt = orig_ctxt.normalize_to_macros_2_0();
+        let mut ctxt = Macros20NormalizedSyntaxContext::new(orig_ctxt.ctxt());
         let mut use_prelude = !module.no_implicit_prelude;
 
         loop {
@@ -198,7 +199,7 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> {
                 Scope::ModuleGlobs(..) if module_only => break,
                 Scope::ModuleGlobs(..) if module_and_extern_prelude => match ns {
                     TypeNS => {
-                        ctxt.adjust(ExpnId::root());
+                        ctxt.update_unchecked(|ctxt| ctxt.adjust(ExpnId::root()));
                         Scope::ExternPreludeItems
                     }
                     ValueNS | MacroNS => break,
@@ -210,7 +211,7 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> {
                             Scope::ModuleNonGlobs(parent_module, lint_id.or(prev_lint_id))
                         }
                         None => {
-                            ctxt.adjust(ExpnId::root());
+                            ctxt.update_unchecked(|ctxt| ctxt.adjust(ExpnId::root()));
                             match ns {
                                 TypeNS => Scope::ExternPreludeItems,
                                 ValueNS => Scope::StdLibPrelude,
@@ -240,12 +241,12 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> {
     fn hygienic_lexical_parent(
         &self,
         module: Module<'ra>,
-        span: &mut Span,
+        ctxt: &mut Macros20NormalizedSyntaxContext,
         derive_fallback_lint_id: Option<NodeId>,
     ) -> Option<(Module<'ra>, Option<NodeId>)> {
-        let ctxt = span.ctxt();
-        if !module.expansion.outer_expn_is_descendant_of(ctxt) {
-            return Some((self.expn_def_scope(span.remove_mark()), None));
+        if !module.expansion.outer_expn_is_descendant_of(**ctxt) {
+            let expn_id = ctxt.update_unchecked(|ctxt| ctxt.remove_mark());
+            return Some((self.expn_def_scope(expn_id), None));
         }
 
         if let ModuleKind::Block = module.kind {
@@ -275,7 +276,7 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> {
             let ext = &self.get_macro_by_def_id(def_id).ext;
             if ext.builtin_name.is_none()
                 && ext.macro_kinds() == MacroKinds::DERIVE
-                && parent.expansion.outer_expn_is_descendant_of(ctxt)
+                && parent.expansion.outer_expn_is_descendant_of(**ctxt)
             {
                 return Some((parent, derive_fallback_lint_id));
             }
@@ -439,11 +440,10 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> {
             orig_ident.span,
             derive_fallback_lint_id,
             |mut this, scope, use_prelude, ctxt| {
-                let ident = Ident::new(orig_ident.name, ctxt);
-                // The passed `ctxt` is already normalized, so avoid expensive double normalization.
-                let ident = Macros20NormalizedIdent(ident);
+                let ident = IdentKey { name: orig_ident.name, ctxt };
                 let res = match this.reborrow().resolve_ident_in_scope(
                     ident,
+                    orig_ident.span,
                     ns,
                     scope,
                     use_prelude,
@@ -515,7 +515,8 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> {
 
     fn resolve_ident_in_scope<'r>(
         mut self: CmResolver<'r, 'ra, 'tcx>,
-        ident: Macros20NormalizedIdent,
+        ident: IdentKey,
+        orig_ident_span: Span,
         ns: Namespace,
         scope: Scope<'ra>,
         use_prelude: UsePrelude,
@@ -531,7 +532,7 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> {
                 if let Some(decl) = self
                     .helper_attrs
                     .get(&expn_id)
-                    .and_then(|attrs| attrs.iter().rfind(|(i, _)| ident == *i).map(|(_, d)| *d))
+                    .and_then(|attrs| attrs.iter().rfind(|(i, ..)| ident == *i).map(|(.., d)| *d))
                 {
                     Ok(decl)
                 } else {
@@ -587,6 +588,7 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> {
                 let decl = self.reborrow().resolve_ident_in_module_non_globs_unadjusted(
                     module,
                     ident,
+                    orig_ident_span,
                     ns,
                     adjusted_parent_scope,
                     if matches!(scope_set, ScopeSet::Module(..)) {
@@ -604,11 +606,11 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> {
                             self.get_mut().lint_buffer.buffer_lint(
                                 PROC_MACRO_DERIVE_RESOLUTION_FALLBACK,
                                 lint_id,
-                                ident.span,
+                                orig_ident_span,
                                 errors::ProcMacroDeriveResolutionFallback {
-                                    span: ident.span,
+                                    span: orig_ident_span,
                                     ns_descr: ns.descr(),
-                                    ident: ident.0,
+                                    ident: ident.name,
                                 },
                             );
                         }
@@ -637,6 +639,7 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> {
                 let binding = self.reborrow().resolve_ident_in_module_globs_unadjusted(
                     module,
                     ident,
+                    orig_ident_span,
                     ns,
                     adjusted_parent_scope,
                     if matches!(scope_set, ScopeSet::Module(..)) {
@@ -654,11 +657,11 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> {
                             self.get_mut().lint_buffer.buffer_lint(
                                 PROC_MACRO_DERIVE_RESOLUTION_FALLBACK,
                                 lint_id,
-                                ident.span,
+                                orig_ident_span,
                                 errors::ProcMacroDeriveResolutionFallback {
-                                    span: ident.span,
+                                    span: orig_ident_span,
                                     ns_descr: ns.descr(),
-                                    ident: ident.0,
+                                    ident: ident.name,
                                 },
                             );
                         }
@@ -683,7 +686,11 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> {
                 None => Err(Determinacy::Determined),
             },
             Scope::ExternPreludeItems => {
-                match self.reborrow().extern_prelude_get_item(ident, finalize.is_some()) {
+                match self.reborrow().extern_prelude_get_item(
+                    ident,
+                    orig_ident_span,
+                    finalize.is_some(),
+                ) {
                     Some(decl) => Ok(decl),
                     None => Err(Determinacy::determined(
                         self.graph_root.unexpanded_invocations.borrow().is_empty(),
@@ -691,7 +698,7 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> {
                 }
             }
             Scope::ExternPreludeFlags => {
-                match self.extern_prelude_get_flag(ident, finalize.is_some()) {
+                match self.extern_prelude_get_flag(ident, orig_ident_span, finalize.is_some()) {
                     Some(decl) => Ok(decl),
                     None => Err(Determinacy::Determined),
                 }
@@ -704,7 +711,7 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> {
                 let mut result = Err(Determinacy::Determined);
                 if let Some(prelude) = self.prelude
                     && let Ok(decl) = self.reborrow().resolve_ident_in_scope_set(
-                        ident.0,
+                        ident.orig(orig_ident_span.with_ctxt(*ident.ctxt)),
                         ScopeSet::Module(ns, prelude),
                         parent_scope,
                         None,
@@ -723,26 +730,26 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> {
                 Some(decl) => {
                     if matches!(ident.name, sym::f16)
                         && !self.tcx.features().f16()
-                        && !ident.span.allows_unstable(sym::f16)
+                        && !orig_ident_span.allows_unstable(sym::f16)
                         && finalize.is_some()
                     {
                         feature_err(
                             self.tcx.sess,
                             sym::f16,
-                            ident.span,
+                            orig_ident_span,
                             "the type `f16` is unstable",
                         )
                         .emit();
                     }
                     if matches!(ident.name, sym::f128)
                         && !self.tcx.features().f128()
-                        && !ident.span.allows_unstable(sym::f128)
+                        && !orig_ident_span.allows_unstable(sym::f128)
                         && finalize.is_some()
                     {
                         feature_err(
                             self.tcx.sess,
                             sym::f128,
-                            ident.span,
+                            orig_ident_span,
                             "the type `f128` is unstable",
                         )
                         .emit();
@@ -1001,7 +1008,8 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> {
     fn resolve_ident_in_module_non_globs_unadjusted<'r>(
         mut self: CmResolver<'r, 'ra, 'tcx>,
         module: Module<'ra>,
-        ident: Macros20NormalizedIdent,
+        ident: IdentKey,
+        orig_ident_span: Span,
         ns: Namespace,
         parent_scope: &ParentScope<'ra>,
         shadowing: Shadowing,
@@ -1016,7 +1024,7 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> {
         // doesn't need to be mutable. It will fail when there is a cycle of imports, and without
         // the exclusive access infinite recursion will crash the compiler with stack overflow.
         let resolution = &*self
-            .resolution_or_default(module, key)
+            .resolution_or_default(module, key, orig_ident_span)
             .try_borrow_mut_unchecked()
             .map_err(|_| ControlFlow::Continue(Determined))?;
 
@@ -1024,7 +1032,8 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> {
 
         if let Some(finalize) = finalize {
             return self.get_mut().finalize_module_binding(
-                ident.0,
+                ident,
+                orig_ident_span,
                 binding,
                 parent_scope,
                 module,
@@ -1064,7 +1073,8 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> {
     fn resolve_ident_in_module_globs_unadjusted<'r>(
         mut self: CmResolver<'r, 'ra, 'tcx>,
         module: Module<'ra>,
-        ident: Macros20NormalizedIdent,
+        ident: IdentKey,
+        orig_ident_span: Span,
         ns: Namespace,
         parent_scope: &ParentScope<'ra>,
         shadowing: Shadowing,
@@ -1077,7 +1087,7 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> {
         // doesn't need to be mutable. It will fail when there is a cycle of imports, and without
         // the exclusive access infinite recursion will crash the compiler with stack overflow.
         let resolution = &*self
-            .resolution_or_default(module, key)
+            .resolution_or_default(module, key, orig_ident_span)
             .try_borrow_mut_unchecked()
             .map_err(|_| ControlFlow::Continue(Determined))?;
 
@@ -1085,7 +1095,8 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> {
 
         if let Some(finalize) = finalize {
             return self.get_mut().finalize_module_binding(
-                ident.0,
+                ident,
+                orig_ident_span,
                 binding,
                 parent_scope,
                 module,
@@ -1154,8 +1165,8 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> {
                 None => return Err(ControlFlow::Continue(Undetermined)),
             };
             let tmp_parent_scope;
-            let (mut adjusted_parent_scope, mut ident) = (parent_scope, ident);
-            match ident.0.span.glob_adjust(module.expansion, glob_import.span) {
+            let (mut adjusted_parent_scope, mut ctxt) = (parent_scope, *ident.ctxt);
+            match ctxt.glob_adjust(module.expansion, glob_import.span) {
                 Some(Some(def)) => {
                     tmp_parent_scope =
                         ParentScope { module: self.expn_def_scope(def), ..*parent_scope };
@@ -1165,7 +1176,7 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> {
                 None => continue,
             };
             let result = self.reborrow().resolve_ident_in_scope_set(
-                ident.0,
+                ident.orig(orig_ident_span.with_ctxt(ctxt)),
                 ScopeSet::Module(ns, module),
                 adjusted_parent_scope,
                 None,
@@ -1191,7 +1202,8 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> {
 
     fn finalize_module_binding(
         &mut self,
-        ident: Ident,
+        ident: IdentKey,
+        orig_ident_span: Span,
         binding: Option<Decl<'ra>>,
         parent_scope: &ParentScope<'ra>,
         module: Module<'ra>,
@@ -1204,6 +1216,7 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> {
             return Err(ControlFlow::Continue(Determined));
         };
 
+        let ident = ident.orig(orig_ident_span);
         if !self.is_accessible_from(binding.vis(), parent_scope.module) {
             if report_private {
                 self.privacy_errors.push(PrivacyError {
diff --git a/compiler/rustc_resolve/src/imports.rs b/compiler/rustc_resolve/src/imports.rs
index f5933afd0134..7ff24bc612df 100644
--- a/compiler/rustc_resolve/src/imports.rs
+++ b/compiler/rustc_resolve/src/imports.rs
@@ -20,7 +20,7 @@ use rustc_session::lint::builtin::{
 use rustc_session::parse::feature_err;
 use rustc_span::edit_distance::find_best_match_for_name;
 use rustc_span::hygiene::LocalExpnId;
-use rustc_span::{Ident, Macros20NormalizedIdent, Span, Symbol, kw, sym};
+use rustc_span::{Ident, Span, Symbol, kw, sym};
 use tracing::debug;
 
 use crate::Namespace::{self, *};
@@ -33,8 +33,8 @@ use crate::errors::{
 use crate::ref_mut::CmCell;
 use crate::{
     AmbiguityError, BindingKey, CmResolver, Decl, DeclData, DeclKind, Determinacy, Finalize,
-    ImportSuggestion, Module, ModuleOrUniformRoot, ParentScope, PathResult, PerNS, ResolutionError,
-    Resolver, ScopeSet, Segment, Used, module_to_string, names_to_string,
+    IdentKey, ImportSuggestion, Module, ModuleOrUniformRoot, ParentScope, PathResult, PerNS,
+    ResolutionError, Resolver, ScopeSet, Segment, Used, module_to_string, names_to_string,
 };
 
 type Res = def::Res<NodeId>;
@@ -239,18 +239,23 @@ impl<'ra> ImportData<'ra> {
 }
 
 /// Records information about the resolution of a name in a namespace of a module.
-#[derive(Clone, Default, Debug)]
+#[derive(Clone, Debug)]
 pub(crate) struct NameResolution<'ra> {
     /// Single imports that may define the name in the namespace.
     /// Imports are arena-allocated, so it's ok to use pointers as keys.
     pub single_imports: FxIndexSet<Import<'ra>>,
     /// The non-glob declaration for this name, if it is known to exist.
-    pub non_glob_decl: Option<Decl<'ra>>,
+    pub non_glob_decl: Option<Decl<'ra>> = None,
     /// The glob declaration for this name, if it is known to exist.
-    pub glob_decl: Option<Decl<'ra>>,
+    pub glob_decl: Option<Decl<'ra>> = None,
+    pub orig_ident_span: Span,
 }
 
 impl<'ra> NameResolution<'ra> {
+    pub(crate) fn new(orig_ident_span: Span) -> Self {
+        NameResolution { single_imports: FxIndexSet::default(), orig_ident_span, .. }
+    }
+
     /// Returns the binding for the name if it is known or None if it not known.
     pub(crate) fn binding(&self) -> Option<Decl<'ra>> {
         self.best_decl().and_then(|binding| {
@@ -417,14 +422,15 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> {
     /// and return existing declaration if there is a collision.
     pub(crate) fn try_plant_decl_into_local_module(
         &mut self,
-        ident: Macros20NormalizedIdent,
+        ident: IdentKey,
+        orig_ident_span: Span,
         ns: Namespace,
         decl: Decl<'ra>,
         warn_ambiguity: bool,
     ) -> Result<(), Decl<'ra>> {
         let module = decl.parent_module.unwrap();
         let res = decl.res();
-        self.check_reserved_macro_name(ident.0, res);
+        self.check_reserved_macro_name(ident.name, orig_ident_span, res);
         // Even if underscore names cannot be looked up, we still need to add them to modules,
         // because they can be fetched by glob imports from those modules, and bring traits
         // into scope both directly and through glob imports.
@@ -432,46 +438,52 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> {
             module.underscore_disambiguator.update_unchecked(|d| d + 1);
             module.underscore_disambiguator.get()
         });
-        self.update_local_resolution(module, key, warn_ambiguity, |this, resolution| {
-            if let Some(old_decl) = resolution.best_decl() {
-                assert_ne!(decl, old_decl);
-                assert!(!decl.warn_ambiguity.get());
-                if res == Res::Err && old_decl.res() != Res::Err {
-                    // Do not override real declarations with `Res::Err`s from error recovery.
-                    return Ok(());
-                }
-                match (old_decl.is_glob_import(), decl.is_glob_import()) {
-                    (true, true) => {
-                        resolution.glob_decl =
-                            Some(this.select_glob_decl(old_decl, decl, warn_ambiguity));
+        self.update_local_resolution(
+            module,
+            key,
+            orig_ident_span,
+            warn_ambiguity,
+            |this, resolution| {
+                if let Some(old_decl) = resolution.best_decl() {
+                    assert_ne!(decl, old_decl);
+                    assert!(!decl.warn_ambiguity.get());
+                    if res == Res::Err && old_decl.res() != Res::Err {
+                        // Do not override real declarations with `Res::Err`s from error recovery.
+                        return Ok(());
                     }
-                    (old_glob @ true, false) | (old_glob @ false, true) => {
-                        let (glob_decl, non_glob_decl) =
-                            if old_glob { (old_decl, decl) } else { (decl, old_decl) };
-                        resolution.non_glob_decl = Some(non_glob_decl);
-                        if let Some(old_glob_decl) = resolution.glob_decl
-                            && old_glob_decl != glob_decl
-                        {
+                    match (old_decl.is_glob_import(), decl.is_glob_import()) {
+                        (true, true) => {
                             resolution.glob_decl =
-                                Some(this.select_glob_decl(old_glob_decl, glob_decl, false));
-                        } else {
-                            resolution.glob_decl = Some(glob_decl);
+                                Some(this.select_glob_decl(old_decl, decl, warn_ambiguity));
+                        }
+                        (old_glob @ true, false) | (old_glob @ false, true) => {
+                            let (glob_decl, non_glob_decl) =
+                                if old_glob { (old_decl, decl) } else { (decl, old_decl) };
+                            resolution.non_glob_decl = Some(non_glob_decl);
+                            if let Some(old_glob_decl) = resolution.glob_decl
+                                && old_glob_decl != glob_decl
+                            {
+                                resolution.glob_decl =
+                                    Some(this.select_glob_decl(old_glob_decl, glob_decl, false));
+                            } else {
+                                resolution.glob_decl = Some(glob_decl);
+                            }
+                        }
+                        (false, false) => {
+                            return Err(old_decl);
                         }
                     }
-                    (false, false) => {
-                        return Err(old_decl);
+                } else {
+                    if decl.is_glob_import() {
+                        resolution.glob_decl = Some(decl);
+                    } else {
+                        resolution.non_glob_decl = Some(decl);
                     }
                 }
-            } else {
-                if decl.is_glob_import() {
-                    resolution.glob_decl = Some(decl);
-                } else {
-                    resolution.non_glob_decl = Some(decl);
-                }
-            }
 
-            Ok(())
-        })
+                Ok(())
+            },
+        )
     }
 
     // Use `f` to mutate the resolution of the name in the module.
@@ -480,6 +492,7 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> {
         &mut self,
         module: Module<'ra>,
         key: BindingKey,
+        orig_ident_span: Span,
         warn_ambiguity: bool,
         f: F,
     ) -> T
@@ -489,7 +502,9 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> {
         // Ensure that `resolution` isn't borrowed when defining in the module's glob importers,
         // during which the resolution might end up getting re-defined via a glob cycle.
         let (binding, t, warn_ambiguity) = {
-            let resolution = &mut *self.resolution_or_default(module, key).borrow_mut_unchecked();
+            let resolution = &mut *self
+                .resolution_or_default(module, key, orig_ident_span)
+                .borrow_mut_unchecked();
             let old_decl = resolution.binding();
 
             let t = f(self, resolution);
@@ -510,7 +525,10 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> {
         // Define or update `binding` in `module`s glob importers.
         for import in glob_importers.iter() {
             let mut ident = key.ident;
-            let scope = match ident.0.span.reverse_glob_adjust(module.expansion, import.span) {
+            let scope = match ident
+                .ctxt
+                .update_unchecked(|ctxt| ctxt.reverse_glob_adjust(module.expansion, import.span))
+            {
                 Some(Some(def)) => self.expn_def_scope(def),
                 Some(None) => import.parent_scope.module,
                 None => continue,
@@ -519,6 +537,7 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> {
                 let import_decl = self.new_import_decl(binding, *import);
                 let _ = self.try_plant_decl_into_local_module(
                     ident,
+                    orig_ident_span,
                     key.ns,
                     import_decl,
                     warn_ambiguity,
@@ -540,14 +559,26 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> {
             let dummy_decl = self.new_import_decl(dummy_decl, import);
             self.per_ns(|this, ns| {
                 let module = import.parent_scope.module;
-                let ident = Macros20NormalizedIdent::new(target);
-                let _ = this.try_plant_decl_into_local_module(ident, ns, dummy_decl, false);
+                let ident = IdentKey::new(target);
+                let _ = this.try_plant_decl_into_local_module(
+                    ident,
+                    target.span,
+                    ns,
+                    dummy_decl,
+                    false,
+                );
                 // Don't remove underscores from `single_imports`, they were never added.
                 if target.name != kw::Underscore {
                     let key = BindingKey::new(ident, ns);
-                    this.update_local_resolution(module, key, false, |_, resolution| {
-                        resolution.single_imports.swap_remove(&import);
-                    })
+                    this.update_local_resolution(
+                        module,
+                        key,
+                        target.span,
+                        false,
+                        |_, resolution| {
+                            resolution.single_imports.swap_remove(&import);
+                        },
+                    )
                 }
             });
             self.record_use(target, dummy_decl, Used::Other);
@@ -687,7 +718,7 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> {
                         import.root_id,
                         import.root_span,
                         BuiltinLintDiag::AmbiguousGlobReexports {
-                            name: key.ident.to_string(),
+                            name: key.ident.name.to_string(),
                             namespace: key.ns.descr().to_string(),
                             first_reexport_span: import.root_span,
                             duplicate_reexport_span: amb_binding.span,
@@ -922,7 +953,8 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> {
                         // We need the `target`, `source` can be extracted.
                         let import_decl = this.new_import_decl(binding, import);
                         this.get_mut_unchecked().plant_decl_into_local_module(
-                            Macros20NormalizedIdent::new(target),
+                            IdentKey::new(target),
+                            target.span,
                             ns,
                             import_decl,
                         );
@@ -931,10 +963,11 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> {
                     Err(Determinacy::Determined) => {
                         // Don't remove underscores from `single_imports`, they were never added.
                         if target.name != kw::Underscore {
-                            let key = BindingKey::new(Macros20NormalizedIdent::new(target), ns);
+                            let key = BindingKey::new(IdentKey::new(target), ns);
                             this.get_mut_unchecked().update_local_resolution(
                                 parent,
                                 key,
+                                target.span,
                                 false,
                                 |_, resolution| {
                                     resolution.single_imports.swap_remove(&import);
@@ -1531,15 +1564,19 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> {
             .borrow()
             .iter()
             .filter_map(|(key, resolution)| {
-                resolution.borrow().binding().map(|binding| (*key, binding))
+                let resolution = resolution.borrow();
+                resolution.binding().map(|binding| (*key, binding, resolution.orig_ident_span))
             })
             .collect::<Vec<_>>();
-        for (mut key, binding) in bindings {
-            let scope = match key.ident.0.span.reverse_glob_adjust(module.expansion, import.span) {
-                Some(Some(def)) => self.expn_def_scope(def),
-                Some(None) => import.parent_scope.module,
-                None => continue,
-            };
+        for (mut key, binding, orig_ident_span) in bindings {
+            let scope =
+                match key.ident.ctxt.update_unchecked(|ctxt| {
+                    ctxt.reverse_glob_adjust(module.expansion, import.span)
+                }) {
+                    Some(Some(def)) => self.expn_def_scope(def),
+                    Some(None) => import.parent_scope.module,
+                    None => continue,
+                };
             if self.is_accessible_from(binding.vis(), scope) {
                 let import_decl = self.new_import_decl(binding, import);
                 let warn_ambiguity = self
@@ -1548,6 +1585,7 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> {
                     .is_some_and(|binding| binding.warn_ambiguity_recursive());
                 let _ = self.try_plant_decl_into_local_module(
                     key.ident,
+                    orig_ident_span,
                     key.ns,
                     import_decl,
                     warn_ambiguity,
@@ -1575,19 +1613,16 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> {
         let mut children = Vec::new();
         let mut ambig_children = Vec::new();
 
-        module.for_each_child(self, |this, ident, _, binding| {
+        module.for_each_child(self, |this, ident, orig_ident_span, _, binding| {
             let res = binding.res().expect_non_local();
             if res != def::Res::Err {
-                let child = |reexport_chain| ModChild {
-                    ident: ident.0,
-                    res,
-                    vis: binding.vis(),
-                    reexport_chain,
-                };
+                let ident = ident.orig(orig_ident_span);
+                let child =
+                    |reexport_chain| ModChild { ident, res, vis: binding.vis(), reexport_chain };
                 if let Some((ambig_binding1, ambig_binding2)) = binding.descent_to_ambiguity() {
                     let main = child(ambig_binding1.reexport_chain(this));
                     let second = ModChild {
-                        ident: ident.0,
+                        ident,
                         res: ambig_binding2.res().expect_non_local(),
                         vis: ambig_binding2.vis(),
                         reexport_chain: ambig_binding2.reexport_chain(this),
diff --git a/compiler/rustc_resolve/src/late.rs b/compiler/rustc_resolve/src/late.rs
index 7a7261cf7b95..4faf7715de6e 100644
--- a/compiler/rustc_resolve/src/late.rs
+++ b/compiler/rustc_resolve/src/late.rs
@@ -37,15 +37,15 @@ use rustc_session::config::{CrateType, ResolveDocLinks};
 use rustc_session::lint;
 use rustc_session::parse::feature_err;
 use rustc_span::source_map::{Spanned, respan};
-use rustc_span::{BytePos, DUMMY_SP, Ident, Macros20NormalizedIdent, Span, Symbol, kw, sym};
+use rustc_span::{BytePos, DUMMY_SP, Ident, Span, Symbol, kw, sym};
 use smallvec::{SmallVec, smallvec};
 use thin_vec::ThinVec;
 use tracing::{debug, instrument, trace};
 
 use crate::{
-    BindingError, BindingKey, Decl, Finalize, LateDecl, Module, ModuleOrUniformRoot, ParentScope,
-    PathResult, ResolutionError, Resolver, Segment, Stage, TyCtxt, UseError, Used, errors,
-    path_names_to_string, rustdoc,
+    BindingError, BindingKey, Decl, Finalize, IdentKey, LateDecl, Module, ModuleOrUniformRoot,
+    ParentScope, PathResult, ResolutionError, Resolver, Segment, Stage, TyCtxt, UseError, Used,
+    errors, path_names_to_string, rustdoc,
 };
 
 mod diagnostics;
@@ -3650,7 +3650,7 @@ impl<'a, 'ast, 'ra, 'tcx> LateResolutionVisitor<'a, 'ast, 'ra, 'tcx> {
             return;
         };
         ident.span.normalize_to_macros_2_0_and_adjust(module.expansion);
-        let key = BindingKey::new(Macros20NormalizedIdent::new(ident), ns);
+        let key = BindingKey::new(IdentKey::new(ident), ns);
         let mut decl = self.r.resolution(module, key).and_then(|r| r.best_decl());
         debug!(?decl);
         if decl.is_none() {
@@ -3661,7 +3661,7 @@ impl<'a, 'ast, 'ra, 'tcx> LateResolutionVisitor<'a, 'ast, 'ra, 'tcx> {
                 TypeNS => ValueNS,
                 _ => ns,
             };
-            let key = BindingKey::new(Macros20NormalizedIdent::new(ident), ns);
+            let key = BindingKey::new(IdentKey::new(ident), ns);
             decl = self.r.resolution(module, key).and_then(|r| r.best_decl());
             debug!(?decl);
         }
diff --git a/compiler/rustc_resolve/src/late/diagnostics.rs b/compiler/rustc_resolve/src/late/diagnostics.rs
index c5d15dcc91af..a3ee17ec4a9a 100644
--- a/compiler/rustc_resolve/src/late/diagnostics.rs
+++ b/compiler/rustc_resolve/src/late/diagnostics.rs
@@ -1620,22 +1620,24 @@ impl<'ast, 'ra, 'tcx> LateResolutionVisitor<'_, 'ast, 'ra, 'tcx> {
             if let PathResult::Module(ModuleOrUniformRoot::Module(module)) =
                 self.resolve_path(mod_path, None, None, *source)
             {
-                let targets: Vec<_> =
-                    self.r
-                        .resolutions(module)
-                        .borrow()
-                        .iter()
-                        .filter_map(|(key, resolution)| {
-                            resolution.borrow().best_decl().map(|binding| binding.res()).and_then(
-                                |res| if filter_fn(res) { Some((*key, res)) } else { None },
-                            )
+                let targets: Vec<_> = self
+                    .r
+                    .resolutions(module)
+                    .borrow()
+                    .iter()
+                    .filter_map(|(key, resolution)| {
+                        let resolution = resolution.borrow();
+                        resolution.best_decl().map(|binding| binding.res()).and_then(|res| {
+                            if filter_fn(res) {
+                                Some((key.ident.name, resolution.orig_ident_span, res))
+                            } else {
+                                None
+                            }
                         })
-                        .collect();
-                if let [target] = targets.as_slice() {
-                    return Some(TypoSuggestion::single_item_from_ident(
-                        target.0.ident.0,
-                        target.1,
-                    ));
+                    })
+                    .collect();
+                if let &[(name, orig_ident_span, res)] = targets.as_slice() {
+                    return Some(TypoSuggestion::single_item(name, orig_ident_span, res));
                 }
             }
         }
@@ -2662,7 +2664,7 @@ impl<'ast, 'ra, 'tcx> LateResolutionVisitor<'_, 'ast, 'ra, 'tcx> {
                 // Locals and type parameters
                 for (ident, &res) in &rib.bindings {
                     if filter_fn(res) && ident.span.ctxt() == rib_ctxt {
-                        names.push(TypoSuggestion::typo_from_ident(*ident, res));
+                        names.push(TypoSuggestion::new(ident.name, ident.span, res));
                     }
                 }
 
@@ -2824,7 +2826,7 @@ impl<'ast, 'ra, 'tcx> LateResolutionVisitor<'_, 'ast, 'ra, 'tcx> {
                 break;
             }
 
-            in_module.for_each_child(self.r, |r, ident, _, name_binding| {
+            in_module.for_each_child(self.r, |r, ident, orig_ident_span, _, name_binding| {
                 // abort if the module is already found or if name_binding is private external
                 if result.is_some() || !name_binding.vis().is_visible_locally() {
                     return;
@@ -2832,7 +2834,7 @@ impl<'ast, 'ra, 'tcx> LateResolutionVisitor<'_, 'ast, 'ra, 'tcx> {
                 if let Some(module_def_id) = name_binding.res().module_like_def_id() {
                     // form the path
                     let mut path_segments = path_segments.clone();
-                    path_segments.push(ast::PathSegment::from_ident(ident.0));
+                    path_segments.push(ast::PathSegment::from_ident(ident.orig(orig_ident_span)));
                     let doc_visible = doc_visible
                         && (module_def_id.is_local() || !r.tcx.is_doc_hidden(module_def_id));
                     if module_def_id == def_id {
@@ -2868,10 +2870,10 @@ impl<'ast, 'ra, 'tcx> LateResolutionVisitor<'_, 'ast, 'ra, 'tcx> {
     fn collect_enum_ctors(&self, def_id: DefId) -> Option<Vec<(Path, DefId, CtorKind)>> {
         self.find_module(def_id).map(|(enum_module, enum_import_suggestion)| {
             let mut variants = Vec::new();
-            enum_module.for_each_child(self.r, |_, ident, _, name_binding| {
+            enum_module.for_each_child(self.r, |_, ident, orig_ident_span, _, name_binding| {
                 if let Res::Def(DefKind::Ctor(CtorOf::Variant, kind), def_id) = name_binding.res() {
                     let mut segms = enum_import_suggestion.path.segments.clone();
-                    segms.push(ast::PathSegment::from_ident(ident.0));
+                    segms.push(ast::PathSegment::from_ident(ident.orig(orig_ident_span)));
                     let path = Path { span: name_binding.span, segments: segms, tokens: None };
                     variants.push((path, def_id, kind));
                 }
diff --git a/compiler/rustc_resolve/src/lib.rs b/compiler/rustc_resolve/src/lib.rs
index c60b7aa50313..5fe1be039a88 100644
--- a/compiler/rustc_resolve/src/lib.rs
+++ b/compiler/rustc_resolve/src/lib.rs
@@ -33,6 +33,7 @@ use std::sync::Arc;
 use diagnostics::{ImportSuggestion, LabelSuggestion, Suggestion};
 use effective_visibilities::EffectiveVisibilitiesVisitor;
 use errors::{ParamKindInEnumDiscriminant, ParamKindInNonTrivialAnonConst};
+use hygiene::Macros20NormalizedSyntaxContext;
 use imports::{Import, ImportData, ImportKind, NameResolution, PendingDecl};
 use late::{
     ForwardGenericParamBanReason, HasGenericParams, PathSource, PatternSource,
@@ -75,7 +76,7 @@ use rustc_query_system::ich::StableHashingContext;
 use rustc_session::config::CrateType;
 use rustc_session::lint::builtin::PRIVATE_MACRO_USE;
 use rustc_span::hygiene::{ExpnId, LocalExpnId, MacroKind, SyntaxContext, Transparency};
-use rustc_span::{DUMMY_SP, Ident, Macros20NormalizedIdent, Span, Symbol, kw, sym};
+use rustc_span::{DUMMY_SP, Ident, Span, Symbol, kw, sym};
 use smallvec::{SmallVec, smallvec};
 use tracing::debug;
 
@@ -552,6 +553,40 @@ impl ModuleKind {
     }
 }
 
+/// Combination of a symbol and its macros 2.0 normalized hygiene context.
+/// Used as a key in various kinds of name containers, including modules (as a part of slightly
+/// larger `BindingKey`) and preludes.
+///
+/// Often passed around together with `orig_ident_span: Span`, which is an unnormalized span
+/// of the original `Ident` from which `IdentKey` was obtained. This span is not used in map keys,
+/// but used in a number of other scenarios - diagnostics, edition checks, `allow_unstable` checks
+/// and similar. This is required because macros 2.0 normalization is lossy and the normalized
+/// spans / syntax contexts no longer contain parts of macro backtraces, while the original span
+/// contains everything.
+#[derive(Clone, Copy, PartialEq, Eq, Hash, Debug)]
+struct IdentKey {
+    name: Symbol,
+    ctxt: Macros20NormalizedSyntaxContext,
+}
+
+impl IdentKey {
+    #[inline]
+    fn new(ident: Ident) -> IdentKey {
+        IdentKey { name: ident.name, ctxt: Macros20NormalizedSyntaxContext::new(ident.span.ctxt()) }
+    }
+
+    #[inline]
+    fn with_root_ctxt(name: Symbol) -> Self {
+        let ctxt = Macros20NormalizedSyntaxContext::new_unchecked(SyntaxContext::root());
+        IdentKey { name, ctxt }
+    }
+
+    #[inline]
+    fn orig(self, orig_ident_span: Span) -> Ident {
+        Ident::new(self.name, orig_ident_span)
+    }
+}
+
 /// A key that identifies a binding in a given `Module`.
 ///
 /// Multiple bindings in the same module can have the same key (in a valid
@@ -560,7 +595,7 @@ impl ModuleKind {
 struct BindingKey {
     /// The identifier for the binding, always the `normalize_to_macros_2_0` version of the
     /// identifier.
-    ident: Macros20NormalizedIdent,
+    ident: IdentKey,
     ns: Namespace,
     /// When we add an underscore binding (with ident `_`) to some module, this field has
     /// a non-zero value that uniquely identifies this binding in that module.
@@ -571,12 +606,12 @@ struct BindingKey {
 }
 
 impl BindingKey {
-    fn new(ident: Macros20NormalizedIdent, ns: Namespace) -> Self {
+    fn new(ident: IdentKey, ns: Namespace) -> Self {
         BindingKey { ident, ns, disambiguator: 0 }
     }
 
     fn new_disambiguated(
-        ident: Macros20NormalizedIdent,
+        ident: IdentKey,
         ns: Namespace,
         disambiguator: impl FnOnce() -> u32,
     ) -> BindingKey {
@@ -623,16 +658,7 @@ struct ModuleData<'ra> {
 
     /// Used to memoize the traits in this module for faster searches through all traits in scope.
     traits: CmRefCell<
-        Option<
-            Box<
-                [(
-                    Macros20NormalizedIdent,
-                    Decl<'ra>,
-                    Option<Module<'ra>>,
-                    bool, /* lint ambiguous */
-                )],
-            >,
-        >,
+        Option<Box<[(Symbol, Decl<'ra>, Option<Module<'ra>>, bool /* lint ambiguous */)]>>,
     >,
 
     /// Span of the module itself. Used for error reporting.
@@ -699,11 +725,12 @@ impl<'ra> Module<'ra> {
     fn for_each_child<'tcx, R: AsRef<Resolver<'ra, 'tcx>>>(
         self,
         resolver: &R,
-        mut f: impl FnMut(&R, Macros20NormalizedIdent, Namespace, Decl<'ra>),
+        mut f: impl FnMut(&R, IdentKey, Span, Namespace, Decl<'ra>),
     ) {
         for (key, name_resolution) in resolver.as_ref().resolutions(self).borrow().iter() {
-            if let Some(decl) = name_resolution.borrow().best_decl() {
-                f(resolver, key.ident, key.ns, decl);
+            let name_resolution = name_resolution.borrow();
+            if let Some(decl) = name_resolution.best_decl() {
+                f(resolver, key.ident, name_resolution.orig_ident_span, key.ns, decl);
             }
         }
     }
@@ -711,11 +738,12 @@ impl<'ra> Module<'ra> {
     fn for_each_child_mut<'tcx, R: AsMut<Resolver<'ra, 'tcx>>>(
         self,
         resolver: &mut R,
-        mut f: impl FnMut(&mut R, Macros20NormalizedIdent, Namespace, Decl<'ra>),
+        mut f: impl FnMut(&mut R, IdentKey, Span, Namespace, Decl<'ra>),
     ) {
         for (key, name_resolution) in resolver.as_mut().resolutions(self).borrow().iter() {
-            if let Some(decl) = name_resolution.borrow().best_decl() {
-                f(resolver, key.ident, key.ns, decl);
+            let name_resolution = name_resolution.borrow();
+            if let Some(decl) = name_resolution.best_decl() {
+                f(resolver, key.ident, name_resolution.orig_ident_span, key.ns, decl);
             }
         }
     }
@@ -725,13 +753,13 @@ impl<'ra> Module<'ra> {
         let mut traits = self.traits.borrow_mut(resolver.as_ref());
         if traits.is_none() {
             let mut collected_traits = Vec::new();
-            self.for_each_child(resolver, |r, name, ns, binding| {
+            self.for_each_child(resolver, |r, ident, _, ns, binding| {
                 if ns != TypeNS {
                     return;
                 }
                 if let Res::Def(DefKind::Trait | DefKind::TraitAlias, def_id) = binding.res() {
                     collected_traits.push((
-                        name,
+                        ident.name,
                         binding,
                         r.as_ref().get_module(def_id),
                         binding.is_ambiguity_recursive(),
@@ -1081,14 +1109,14 @@ struct ExternPreludeEntry<'ra> {
     /// Name declaration from an `extern crate` item.
     /// The boolean flag is true is `item_decl` is non-redundant, happens either when
     /// `flag_decl` is `None`, or when `extern crate` introducing `item_decl` used renaming.
-    item_decl: Option<(Decl<'ra>, /* introduced by item */ bool)>,
+    item_decl: Option<(Decl<'ra>, Span, /* introduced by item */ bool)>,
     /// Name declaration from an `--extern` flag, lazily populated on first use.
     flag_decl: Option<CacheCell<(PendingDecl<'ra>, /* finalized */ bool)>>,
 }
 
 impl ExternPreludeEntry<'_> {
     fn introduced_by_item(&self) -> bool {
-        matches!(self.item_decl, Some((_, true)))
+        matches!(self.item_decl, Some((.., true)))
     }
 
     fn flag() -> Self {
@@ -1097,11 +1125,18 @@ impl ExternPreludeEntry<'_> {
             flag_decl: Some(CacheCell::new((PendingDecl::Pending, false))),
         }
     }
+
+    fn span(&self) -> Span {
+        match self.item_decl {
+            Some((_, span, _)) => span,
+            None => DUMMY_SP,
+        }
+    }
 }
 
 struct DeriveData {
     resolutions: Vec<DeriveResolution>,
-    helper_attrs: Vec<(usize, Macros20NormalizedIdent)>,
+    helper_attrs: Vec<(usize, IdentKey, Span)>,
     has_derive_copy: bool,
 }
 
@@ -1137,7 +1172,7 @@ pub struct Resolver<'ra, 'tcx> {
     assert_speculative: bool,
 
     prelude: Option<Module<'ra>> = None,
-    extern_prelude: FxIndexMap<Macros20NormalizedIdent, ExternPreludeEntry<'ra>>,
+    extern_prelude: FxIndexMap<IdentKey, ExternPreludeEntry<'ra>>,
 
     /// N.B., this is used only for better diagnostics, not name resolution itself.
     field_names: LocalDefIdMap<Vec<Ident>> = Default::default(),
@@ -1228,8 +1263,8 @@ pub struct Resolver<'ra, 'tcx> {
     dummy_decl: Decl<'ra>,
     builtin_type_decls: FxHashMap<Symbol, Decl<'ra>>,
     builtin_attr_decls: FxHashMap<Symbol, Decl<'ra>>,
-    registered_tool_decls: FxHashMap<Ident, Decl<'ra>>,
-    macro_names: FxHashSet<Ident> = default::fx_hash_set(),
+    registered_tool_decls: FxHashMap<IdentKey, Decl<'ra>>,
+    macro_names: FxHashSet<IdentKey> = default::fx_hash_set(),
     builtin_macros: FxHashMap<Symbol, SyntaxExtensionKind> = default::fx_hash_map(),
     registered_tools: &'tcx RegisteredTools,
     macro_use_prelude: FxIndexMap<Symbol, Decl<'ra>>,
@@ -1265,7 +1300,7 @@ pub struct Resolver<'ra, 'tcx> {
     /// `macro_rules` scopes produced by `macro_rules` item definitions.
     macro_rules_scopes: FxHashMap<LocalDefId, MacroRulesScopeRef<'ra>> = default::fx_hash_map(),
     /// Helper attributes that are in scope for the given expansion.
-    helper_attrs: FxHashMap<LocalExpnId, Vec<(Macros20NormalizedIdent, Decl<'ra>)>> = default::fx_hash_map(),
+    helper_attrs: FxHashMap<LocalExpnId, Vec<(IdentKey, Span, Decl<'ra>)>> = default::fx_hash_map(),
     /// Ready or in-progress results of resolving paths inside the `#[derive(...)]` attribute
     /// with the given `ExpnId`.
     derive_data: FxHashMap<LocalExpnId, DeriveData> = default::fx_hash_map(),
@@ -1409,8 +1444,11 @@ impl<'ra> ResolverArenas<'ra> {
     fn alloc_import(&'ra self, import: ImportData<'ra>) -> Import<'ra> {
         Interned::new_unchecked(self.imports.alloc(import))
     }
-    fn alloc_name_resolution(&'ra self) -> &'ra CmRefCell<NameResolution<'ra>> {
-        self.name_resolutions.alloc(Default::default())
+    fn alloc_name_resolution(
+        &'ra self,
+        orig_ident_span: Span,
+    ) -> &'ra CmRefCell<NameResolution<'ra>> {
+        self.name_resolutions.alloc(CmRefCell::new(NameResolution::new(orig_ident_span)))
     }
     fn alloc_macro_rules_scope(&'ra self, scope: MacroRulesScope<'ra>) -> MacroRulesScopeRef<'ra> {
         self.dropless.alloc(CacheCell::new(scope))
@@ -1580,7 +1618,7 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> {
                     && let name = Symbol::intern(name)
                     && name.can_be_raw()
                 {
-                    let ident = Macros20NormalizedIdent::with_dummy_span(name);
+                    let ident = IdentKey::with_root_ctxt(name);
                     Some((ident, ExternPreludeEntry::flag()))
                 } else {
                     None
@@ -1589,10 +1627,10 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> {
             .collect();
 
         if !attr::contains_name(attrs, sym::no_core) {
-            let ident = Macros20NormalizedIdent::with_dummy_span(sym::core);
+            let ident = IdentKey::with_root_ctxt(sym::core);
             extern_prelude.insert(ident, ExternPreludeEntry::flag());
             if !attr::contains_name(attrs, sym::no_std) {
-                let ident = Macros20NormalizedIdent::with_dummy_span(sym::std);
+                let ident = IdentKey::with_root_ctxt(sym::std);
                 extern_prelude.insert(ident, ExternPreludeEntry::flag());
             }
         }
@@ -1637,10 +1675,10 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> {
                 .collect(),
             registered_tool_decls: registered_tools
                 .iter()
-                .map(|ident| {
+                .map(|&ident| {
                     let res = Res::ToolMod;
                     let decl = arenas.new_pub_def_decl(res, ident.span, LocalExpnId::ROOT);
-                    (*ident, decl)
+                    (IdentKey::new(ident), decl)
                 })
                 .collect(),
             registered_tools,
@@ -1940,7 +1978,7 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> {
         {
             if self.trait_may_have_item(trait_module, assoc_item) {
                 let def_id = trait_binding.res().def_id();
-                let import_ids = self.find_transitive_imports(&trait_binding.kind, trait_name.0);
+                let import_ids = self.find_transitive_imports(&trait_binding.kind, trait_name);
                 found_traits.push(TraitCandidate { def_id, import_ids, lint_ambiguous });
             }
         }
@@ -1969,7 +2007,7 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> {
     fn find_transitive_imports(
         &mut self,
         mut kind: &DeclKind<'_>,
-        trait_name: Ident,
+        trait_name: Symbol,
     ) -> SmallVec<[LocalDefId; 1]> {
         let mut import_ids = smallvec![];
         while let DeclKind::Import { import, source_decl, .. } = kind {
@@ -2004,11 +2042,12 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> {
         &self,
         module: Module<'ra>,
         key: BindingKey,
+        orig_ident_span: Span,
     ) -> &'ra CmRefCell<NameResolution<'ra>> {
         self.resolutions(module)
             .borrow_mut_unchecked()
             .entry(key)
-            .or_insert_with(|| self.arenas.alloc_name_resolution())
+            .or_insert_with(|| self.arenas.alloc_name_resolution(orig_ident_span))
     }
 
     /// Test if AmbiguityError ambi is any identical to any one inside ambiguity_errors
@@ -2082,8 +2121,9 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> {
             // Avoid marking `extern crate` items that refer to a name from extern prelude,
             // but not introduce it, as used if they are accessed from lexical scope.
             if used == Used::Scope
-                && let Some(entry) = self.extern_prelude.get(&Macros20NormalizedIdent::new(ident))
-                && entry.item_decl == Some((used_decl, false))
+                && let Some(entry) = self.extern_prelude.get(&IdentKey::new(ident))
+                && let Some((item_decl, _, false)) = entry.item_decl
+                && item_decl == used_decl
             {
                 return;
             }
@@ -2094,7 +2134,7 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> {
             if let Some(id) = import.id() {
                 self.used_imports.insert(id);
             }
-            self.add_to_glob_map(import, ident);
+            self.add_to_glob_map(import, ident.name);
             self.record_use_inner(
                 ident,
                 source_decl,
@@ -2105,10 +2145,10 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> {
     }
 
     #[inline]
-    fn add_to_glob_map(&mut self, import: Import<'_>, ident: Ident) {
+    fn add_to_glob_map(&mut self, import: Import<'_>, name: Symbol) {
         if let ImportKind::Glob { id, .. } = import.kind {
             let def_id = self.local_def_id(id);
-            self.glob_map.entry(def_id).or_default().insert(ident.name);
+            self.glob_map.entry(def_id).or_default().insert(name);
         }
     }
 
@@ -2230,13 +2270,14 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> {
 
     fn extern_prelude_get_item<'r>(
         mut self: CmResolver<'r, 'ra, 'tcx>,
-        ident: Macros20NormalizedIdent,
+        ident: IdentKey,
+        orig_ident_span: Span,
         finalize: bool,
     ) -> Option<Decl<'ra>> {
         let entry = self.extern_prelude.get(&ident);
-        entry.and_then(|entry| entry.item_decl).map(|(decl, _)| {
+        entry.and_then(|entry| entry.item_decl).map(|(decl, ..)| {
             if finalize {
-                self.get_mut().record_use(ident.0, decl, Used::Scope);
+                self.get_mut().record_use(ident.orig(orig_ident_span), decl, Used::Scope);
             }
             decl
         })
@@ -2244,7 +2285,8 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> {
 
     fn extern_prelude_get_flag(
         &self,
-        ident: Macros20NormalizedIdent,
+        ident: IdentKey,
+        orig_ident_span: Span,
         finalize: bool,
     ) -> Option<Decl<'ra>> {
         let entry = self.extern_prelude.get(&ident);
@@ -2253,14 +2295,18 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> {
             let decl = match pending_decl {
                 PendingDecl::Ready(decl) => {
                     if finalize && !finalized {
-                        self.cstore_mut().process_path_extern(self.tcx, ident.name, ident.span);
+                        self.cstore_mut().process_path_extern(
+                            self.tcx,
+                            ident.name,
+                            orig_ident_span,
+                        );
                     }
                     decl
                 }
                 PendingDecl::Pending => {
                     debug_assert!(!finalized);
                     let crate_id = if finalize {
-                        self.cstore_mut().process_path_extern(self.tcx, ident.name, ident.span)
+                        self.cstore_mut().process_path_extern(self.tcx, ident.name, orig_ident_span)
                     } else {
                         self.cstore_mut().maybe_process_path_extern(self.tcx, ident.name)
                     };
@@ -2675,3 +2721,40 @@ mod ref_mut {
         }
     }
 }
+
+mod hygiene {
+    use rustc_span::SyntaxContext;
+
+    /// A newtype around `SyntaxContext` that can only keep contexts produced by
+    /// [SyntaxContext::normalize_to_macros_2_0].
+    #[derive(Clone, Copy, PartialEq, Eq, Hash, Debug)]
+    pub(crate) struct Macros20NormalizedSyntaxContext(SyntaxContext);
+
+    impl Macros20NormalizedSyntaxContext {
+        #[inline]
+        pub(crate) fn new(ctxt: SyntaxContext) -> Macros20NormalizedSyntaxContext {
+            Macros20NormalizedSyntaxContext(ctxt.normalize_to_macros_2_0())
+        }
+
+        #[inline]
+        pub(crate) fn new_unchecked(ctxt: SyntaxContext) -> Macros20NormalizedSyntaxContext {
+            debug_assert_eq!(ctxt, ctxt.normalize_to_macros_2_0());
+            Macros20NormalizedSyntaxContext(ctxt)
+        }
+
+        /// The passed closure must preserve the context's normalized-ness.
+        #[inline]
+        pub(crate) fn update_unchecked<R>(&mut self, f: impl FnOnce(&mut SyntaxContext) -> R) -> R {
+            let ret = f(&mut self.0);
+            debug_assert_eq!(self.0, self.0.normalize_to_macros_2_0());
+            ret
+        }
+    }
+
+    impl std::ops::Deref for Macros20NormalizedSyntaxContext {
+        type Target = SyntaxContext;
+        fn deref(&self) -> &Self::Target {
+            &self.0
+        }
+    }
+}
diff --git a/compiler/rustc_resolve/src/macros.rs b/compiler/rustc_resolve/src/macros.rs
index 8f05ad7924e3..b7d83d9e130c 100644
--- a/compiler/rustc_resolve/src/macros.rs
+++ b/compiler/rustc_resolve/src/macros.rs
@@ -29,16 +29,17 @@ use rustc_session::parse::feature_err;
 use rustc_span::edit_distance::find_best_match_for_name;
 use rustc_span::edition::Edition;
 use rustc_span::hygiene::{self, AstPass, ExpnData, ExpnKind, LocalExpnId, MacroKind};
-use rustc_span::{DUMMY_SP, Ident, Macros20NormalizedIdent, Span, Symbol, kw, sym};
+use rustc_span::{DUMMY_SP, Ident, Span, Symbol, kw, sym};
 
 use crate::Namespace::*;
 use crate::errors::{
     self, AddAsNonDerive, CannotDetermineMacroResolution, CannotFindIdentInThisScope,
     MacroExpectedFound, RemoveSurroundingDerive,
 };
+use crate::hygiene::Macros20NormalizedSyntaxContext;
 use crate::imports::Import;
 use crate::{
-    BindingKey, CacheCell, CmResolver, Decl, DeclKind, DeriveData, Determinacy, Finalize,
+    BindingKey, CacheCell, CmResolver, Decl, DeclKind, DeriveData, Determinacy, Finalize, IdentKey,
     InvocationParent, MacroData, ModuleKind, ModuleOrUniformRoot, ParentScope, PathResult,
     ResolutionError, Resolver, ScopeSet, Segment, Used,
 };
@@ -52,7 +53,8 @@ pub(crate) struct MacroRulesDecl<'ra> {
     pub(crate) decl: Decl<'ra>,
     /// `macro_rules` scope into which the `macro_rules` item was planted.
     pub(crate) parent_macro_rules_scope: MacroRulesScopeRef<'ra>,
-    pub(crate) ident: Macros20NormalizedIdent,
+    pub(crate) ident: IdentKey,
+    pub(crate) orig_ident_span: Span,
 }
 
 /// The scope introduced by a `macro_rules!` macro.
@@ -412,9 +414,12 @@ impl<'ra, 'tcx> ResolverExpand for Resolver<'ra, 'tcx> {
                         Ok((Some(ext), _)) => {
                             if !ext.helper_attrs.is_empty() {
                                 let span = resolution.path.segments.last().unwrap().ident.span;
-                                entry.helper_attrs.extend(ext.helper_attrs.iter().map(|name| {
-                                    (i, Macros20NormalizedIdent::new(Ident::new(*name, span)))
-                                }));
+                                let ctxt = Macros20NormalizedSyntaxContext::new(span.ctxt());
+                                entry.helper_attrs.extend(
+                                    ext.helper_attrs
+                                        .iter()
+                                        .map(|&name| (i, IdentKey { name, ctxt }, span)),
+                                );
                             }
                             entry.has_derive_copy |= ext.builtin_name == Some(sym::Copy);
                             ext
@@ -430,13 +435,14 @@ impl<'ra, 'tcx> ResolverExpand for Resolver<'ra, 'tcx> {
             }
         }
         // Sort helpers in a stable way independent from the derive resolution order.
-        entry.helper_attrs.sort_by_key(|(i, _)| *i);
+        entry.helper_attrs.sort_by_key(|(i, ..)| *i);
         let helper_attrs = entry
             .helper_attrs
             .iter()
-            .map(|(_, ident)| {
+            .map(|&(_, ident, orig_ident_span)| {
                 let res = Res::NonMacroAttr(NonMacroAttrKind::DeriveHelper);
-                (*ident, self.arenas.new_pub_def_decl(res, ident.span, expn_id))
+                let decl = self.arenas.new_pub_def_decl(res, orig_ident_span, expn_id);
+                (ident, orig_ident_span, decl)
             })
             .collect();
         self.helper_attrs.insert(expn_id, helper_attrs);
@@ -532,14 +538,14 @@ impl<'ra, 'tcx> ResolverExpand for Resolver<'ra, 'tcx> {
         }
 
         let mut idents = Vec::new();
-        target_trait.for_each_child(self, |this, ident, ns, _binding| {
+        target_trait.for_each_child(self, |this, ident, orig_ident_span, ns, _binding| {
             // FIXME: Adjust hygiene for idents from globs, like for glob imports.
             if let Some(overriding_keys) = this.impl_binding_keys.get(&impl_def_id)
                 && overriding_keys.contains(&BindingKey::new(ident, ns))
             {
                 // The name is overridden, do not produce it from the glob delegation.
             } else {
-                idents.push((ident.0, None));
+                idents.push((ident.orig(orig_ident_span), None));
             }
         });
         Ok(idents)
@@ -1145,14 +1151,13 @@ impl<'ra, 'tcx> Resolver<'ra, 'tcx> {
         }
     }
 
-    pub(crate) fn check_reserved_macro_name(&self, ident: Ident, res: Res) {
+    pub(crate) fn check_reserved_macro_name(&self, name: Symbol, span: Span, res: Res) {
         // Reserve some names that are not quite covered by the general check
         // performed on `Resolver::builtin_attrs`.
-        if ident.name == sym::cfg || ident.name == sym::cfg_attr {
+        if name == sym::cfg || name == sym::cfg_attr {
             let macro_kinds = self.get_macro(res).map(|macro_data| macro_data.ext.macro_kinds());
             if macro_kinds.is_some() && sub_namespace_match(macro_kinds, Some(MacroKind::Attr)) {
-                self.dcx()
-                    .emit_err(errors::NameReservedInAttributeNamespace { span: ident.span, ident });
+                self.dcx().emit_err(errors::NameReservedInAttributeNamespace { span, ident: name });
             }
         }
     }
diff --git a/compiler/rustc_span/src/hygiene.rs b/compiler/rustc_span/src/hygiene.rs
index d94d82835d65..2e8037b3f9e4 100644
--- a/compiler/rustc_span/src/hygiene.rs
+++ b/compiler/rustc_span/src/hygiene.rs
@@ -837,11 +837,7 @@ impl SyntaxContext {
     /// ```
     /// This returns `None` if the context cannot be glob-adjusted.
     /// Otherwise, it returns the scope to use when privacy checking (see `adjust` for details).
-    pub(crate) fn glob_adjust(
-        &mut self,
-        expn_id: ExpnId,
-        glob_span: Span,
-    ) -> Option<Option<ExpnId>> {
+    pub fn glob_adjust(&mut self, expn_id: ExpnId, glob_span: Span) -> Option<Option<ExpnId>> {
         HygieneData::with(|data| {
             let mut scope = None;
             let mut glob_ctxt = data.normalize_to_macros_2_0(glob_span.ctxt());
@@ -865,7 +861,7 @@ impl SyntaxContext {
     ///     assert!(self.glob_adjust(expansion, glob_ctxt) == Some(privacy_checking_scope));
     /// }
     /// ```
-    pub(crate) fn reverse_glob_adjust(
+    pub fn reverse_glob_adjust(
         &mut self,
         expn_id: ExpnId,
         glob_span: Span,
diff --git a/compiler/rustc_span/src/lib.rs b/compiler/rustc_span/src/lib.rs
index 69f91cfab9e4..a178f3260d30 100644
--- a/compiler/rustc_span/src/lib.rs
+++ b/compiler/rustc_span/src/lib.rs
@@ -63,8 +63,7 @@ pub use span_encoding::{DUMMY_SP, Span};
 
 pub mod symbol;
 pub use symbol::{
-    ByteSymbol, Ident, MacroRulesNormalizedIdent, Macros20NormalizedIdent, STDLIB_STABLE_CRATES,
-    Symbol, kw, sym,
+    ByteSymbol, Ident, MacroRulesNormalizedIdent, STDLIB_STABLE_CRATES, Symbol, kw, sym,
 };
 
 mod analyze_source_file;
@@ -1312,30 +1311,6 @@ impl Span {
         mark
     }
 
-    #[inline]
-    pub fn glob_adjust(&mut self, expn_id: ExpnId, glob_span: Span) -> Option<Option<ExpnId>> {
-        let mut mark = None;
-        *self = self.map_ctxt(|mut ctxt| {
-            mark = ctxt.glob_adjust(expn_id, glob_span);
-            ctxt
-        });
-        mark
-    }
-
-    #[inline]
-    pub fn reverse_glob_adjust(
-        &mut self,
-        expn_id: ExpnId,
-        glob_span: Span,
-    ) -> Option<Option<ExpnId>> {
-        let mut mark = None;
-        *self = self.map_ctxt(|mut ctxt| {
-            mark = ctxt.reverse_glob_adjust(expn_id, glob_span);
-            ctxt
-        });
-        mark
-    }
-
     #[inline]
     pub fn normalize_to_macros_2_0(self) -> Span {
         self.map_ctxt(|ctxt| ctxt.normalize_to_macros_2_0())
diff --git a/compiler/rustc_span/src/symbol.rs b/compiler/rustc_span/src/symbol.rs
index c4391c3ec4fc..7a6c0c0d57bd 100644
--- a/compiler/rustc_span/src/symbol.rs
+++ b/compiler/rustc_span/src/symbol.rs
@@ -3,7 +3,6 @@
 //! type, and vice versa.
 
 use std::hash::{Hash, Hasher};
-use std::ops::Deref;
 use std::{fmt, str};
 
 use rustc_arena::DroplessArena;
@@ -2748,7 +2747,7 @@ impl fmt::Display for IdentPrinter {
     }
 }
 
-/// An newtype around `Ident` that calls [Ident::normalize_to_macro_rules] on
+/// A newtype around `Ident` that calls [Ident::normalize_to_macro_rules] on
 /// construction for "local variable hygiene" comparisons.
 ///
 /// Use this type when you need to compare identifiers according to macro_rules hygiene.
@@ -2775,48 +2774,6 @@ impl fmt::Display for MacroRulesNormalizedIdent {
     }
 }
 
-/// An newtype around `Ident` that calls [Ident::normalize_to_macros_2_0] on
-/// construction for "item hygiene" comparisons.
-///
-/// Identifiers with same string value become same if they came from the same macro 2.0 macro
-/// (e.g., `macro` item, but not `macro_rules` item) and stay different if they came from
-/// different macro 2.0 macros.
-#[derive(Copy, Clone, Eq, PartialEq, Hash)]
-pub struct Macros20NormalizedIdent(pub Ident);
-
-impl Macros20NormalizedIdent {
-    #[inline]
-    pub fn new(ident: Ident) -> Self {
-        Macros20NormalizedIdent(ident.normalize_to_macros_2_0())
-    }
-
-    // dummy_span does not need to be normalized, so we can use `Ident` directly
-    pub fn with_dummy_span(name: Symbol) -> Self {
-        Macros20NormalizedIdent(Ident::with_dummy_span(name))
-    }
-}
-
-impl fmt::Debug for Macros20NormalizedIdent {
-    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
-        fmt::Debug::fmt(&self.0, f)
-    }
-}
-
-impl fmt::Display for Macros20NormalizedIdent {
-    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
-        fmt::Display::fmt(&self.0, f)
-    }
-}
-
-/// By impl Deref, we can access the wrapped Ident as if it were a normal Ident
-/// such as `norm_ident.name` instead of `norm_ident.0.name`.
-impl Deref for Macros20NormalizedIdent {
-    type Target = Ident;
-    fn deref(&self) -> &Self::Target {
-        &self.0
-    }
-}
-
 /// An interned UTF-8 string.
 ///
 /// Internally, a `Symbol` is implemented as an index, and all operations
diff --git a/tests/ui/hygiene/cross-crate-name-hiding-2.stderr b/tests/ui/hygiene/cross-crate-name-hiding-2.stderr
index 336d35099c80..90dd40534ed1 100644
--- a/tests/ui/hygiene/cross-crate-name-hiding-2.stderr
+++ b/tests/ui/hygiene/cross-crate-name-hiding-2.stderr
@@ -1,13 +1,11 @@
 error[E0422]: cannot find struct, variant or union type `MyStruct` in this scope
   --> $DIR/cross-crate-name-hiding-2.rs:13:13
    |
+LL | my_struct!(define);
+   | ------------------ you might have meant to refer to this struct
+...
 LL |     let x = MyStruct {};
    |             ^^^^^^^^ not found in this scope
-   |
-  ::: $DIR/auxiliary/use_by_macro.rs:7:24
-   |
-LL |             pub struct MyStruct;
-   |                        -------- you might have meant to refer to this struct
 
 error: aborting due to 1 previous error
 
diff --git a/tests/ui/lint/unused/unused-macros.stderr b/tests/ui/lint/unused/unused-macros.stderr
index d0baf5becec4..50c80b61eb5b 100644
--- a/tests/ui/lint/unused/unused-macros.stderr
+++ b/tests/ui/lint/unused/unused-macros.stderr
@@ -15,6 +15,11 @@ error: unused macro definition: `m`
    |
 LL |         macro_rules! m {
    |                      ^
+...
+LL | create_macro!();
+   | --------------- in this macro invocation
+   |
+   = note: this error originates in the macro `create_macro` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error: unused macro definition: `unused`
   --> $DIR/unused-macros.rs:26:18
diff --git a/tests/ui/proc-macro/dollar-crate-issue-62325.stdout b/tests/ui/proc-macro/dollar-crate-issue-62325.stdout
index bfd013476f3a..d1b7227c138d 100644
--- a/tests/ui/proc-macro/dollar-crate-issue-62325.stdout
+++ b/tests/ui/proc-macro/dollar-crate-issue-62325.stdout
@@ -57,54 +57,54 @@ PRINT-ATTR INPUT (DISPLAY): struct B(identity! ($crate :: S));
 PRINT-ATTR INPUT (DEBUG): TokenStream [
     Ident {
         ident: "struct",
-        span: $DIR/auxiliary/dollar-crate-external.rs:21:5: 21:11 (#11),
+        span: $DIR/auxiliary/dollar-crate-external.rs:21:5: 21:11 (#12),
     },
     Ident {
         ident: "B",
-        span: $DIR/auxiliary/dollar-crate-external.rs:21:12: 21:13 (#11),
+        span: $DIR/auxiliary/dollar-crate-external.rs:21:12: 21:13 (#12),
     },
     Group {
         delimiter: Parenthesis,
         stream: TokenStream [
             Ident {
                 ident: "identity",
-                span: $DIR/auxiliary/dollar-crate-external.rs:21:14: 21:22 (#11),
+                span: $DIR/auxiliary/dollar-crate-external.rs:21:14: 21:22 (#12),
             },
             Punct {
                 ch: '!',
                 spacing: Alone,
-                span: $DIR/auxiliary/dollar-crate-external.rs:21:22: 21:23 (#11),
+                span: $DIR/auxiliary/dollar-crate-external.rs:21:22: 21:23 (#12),
             },
             Group {
                 delimiter: Parenthesis,
                 stream: TokenStream [
                     Ident {
                         ident: "$crate",
-                        span: $DIR/auxiliary/dollar-crate-external.rs:21:24: 21:30 (#11),
+                        span: $DIR/auxiliary/dollar-crate-external.rs:21:24: 21:30 (#12),
                     },
                     Punct {
                         ch: ':',
                         spacing: Joint,
-                        span: $DIR/auxiliary/dollar-crate-external.rs:21:30: 21:31 (#11),
+                        span: $DIR/auxiliary/dollar-crate-external.rs:21:30: 21:31 (#12),
                     },
                     Punct {
                         ch: ':',
                         spacing: Alone,
-                        span: $DIR/auxiliary/dollar-crate-external.rs:21:31: 21:32 (#11),
+                        span: $DIR/auxiliary/dollar-crate-external.rs:21:31: 21:32 (#12),
                     },
                     Ident {
                         ident: "S",
-                        span: $DIR/auxiliary/dollar-crate-external.rs:21:32: 21:33 (#11),
+                        span: $DIR/auxiliary/dollar-crate-external.rs:21:32: 21:33 (#12),
                     },
                 ],
-                span: $DIR/auxiliary/dollar-crate-external.rs:21:23: 21:34 (#11),
+                span: $DIR/auxiliary/dollar-crate-external.rs:21:23: 21:34 (#12),
             },
         ],
-        span: $DIR/auxiliary/dollar-crate-external.rs:21:13: 21:35 (#11),
+        span: $DIR/auxiliary/dollar-crate-external.rs:21:13: 21:35 (#12),
     },
     Punct {
         ch: ';',
         spacing: Alone,
-        span: $DIR/auxiliary/dollar-crate-external.rs:21:35: 21:36 (#11),
+        span: $DIR/auxiliary/dollar-crate-external.rs:21:35: 21:36 (#12),
     },
 ]
diff --git a/tests/ui/proc-macro/dollar-crate.stdout b/tests/ui/proc-macro/dollar-crate.stdout
index 0278ef1ad0fc..f39d03540916 100644
--- a/tests/ui/proc-macro/dollar-crate.stdout
+++ b/tests/ui/proc-macro/dollar-crate.stdout
@@ -122,119 +122,119 @@ PRINT-BANG INPUT (DISPLAY): struct M($crate :: S);
 PRINT-BANG INPUT (DEBUG): TokenStream [
     Ident {
         ident: "struct",
-        span: $DIR/auxiliary/dollar-crate-external.rs:7:13: 7:19 (#14),
+        span: $DIR/auxiliary/dollar-crate-external.rs:7:13: 7:19 (#15),
     },
     Ident {
         ident: "M",
-        span: $DIR/auxiliary/dollar-crate-external.rs:7:20: 7:21 (#14),
+        span: $DIR/auxiliary/dollar-crate-external.rs:7:20: 7:21 (#15),
     },
     Group {
         delimiter: Parenthesis,
         stream: TokenStream [
             Ident {
                 ident: "$crate",
-                span: $DIR/auxiliary/dollar-crate-external.rs:7:22: 7:28 (#14),
+                span: $DIR/auxiliary/dollar-crate-external.rs:7:22: 7:28 (#15),
             },
             Punct {
                 ch: ':',
                 spacing: Joint,
-                span: $DIR/auxiliary/dollar-crate-external.rs:7:28: 7:29 (#14),
+                span: $DIR/auxiliary/dollar-crate-external.rs:7:28: 7:29 (#15),
             },
             Punct {
                 ch: ':',
                 spacing: Alone,
-                span: $DIR/auxiliary/dollar-crate-external.rs:7:29: 7:30 (#14),
+                span: $DIR/auxiliary/dollar-crate-external.rs:7:29: 7:30 (#15),
             },
             Ident {
                 ident: "S",
-                span: $DIR/auxiliary/dollar-crate-external.rs:7:30: 7:31 (#14),
+                span: $DIR/auxiliary/dollar-crate-external.rs:7:30: 7:31 (#15),
             },
         ],
-        span: $DIR/auxiliary/dollar-crate-external.rs:7:21: 7:32 (#14),
+        span: $DIR/auxiliary/dollar-crate-external.rs:7:21: 7:32 (#15),
     },
     Punct {
         ch: ';',
         spacing: Alone,
-        span: $DIR/auxiliary/dollar-crate-external.rs:7:32: 7:33 (#14),
+        span: $DIR/auxiliary/dollar-crate-external.rs:7:32: 7:33 (#15),
     },
 ]
 PRINT-ATTR INPUT (DISPLAY): struct A($crate :: S);
 PRINT-ATTR INPUT (DEBUG): TokenStream [
     Ident {
         ident: "struct",
-        span: $DIR/auxiliary/dollar-crate-external.rs:11:9: 11:15 (#14),
+        span: $DIR/auxiliary/dollar-crate-external.rs:11:9: 11:15 (#15),
     },
     Ident {
         ident: "A",
-        span: $DIR/auxiliary/dollar-crate-external.rs:11:16: 11:17 (#14),
+        span: $DIR/auxiliary/dollar-crate-external.rs:11:16: 11:17 (#15),
     },
     Group {
         delimiter: Parenthesis,
         stream: TokenStream [
             Ident {
                 ident: "$crate",
-                span: $DIR/auxiliary/dollar-crate-external.rs:11:18: 11:24 (#14),
+                span: $DIR/auxiliary/dollar-crate-external.rs:11:18: 11:24 (#15),
             },
             Punct {
                 ch: ':',
                 spacing: Joint,
-                span: $DIR/auxiliary/dollar-crate-external.rs:11:24: 11:25 (#14),
+                span: $DIR/auxiliary/dollar-crate-external.rs:11:24: 11:25 (#15),
             },
             Punct {
                 ch: ':',
                 spacing: Alone,
-                span: $DIR/auxiliary/dollar-crate-external.rs:11:25: 11:26 (#14),
+                span: $DIR/auxiliary/dollar-crate-external.rs:11:25: 11:26 (#15),
             },
             Ident {
                 ident: "S",
-                span: $DIR/auxiliary/dollar-crate-external.rs:11:26: 11:27 (#14),
+                span: $DIR/auxiliary/dollar-crate-external.rs:11:26: 11:27 (#15),
             },
         ],
-        span: $DIR/auxiliary/dollar-crate-external.rs:11:17: 11:28 (#14),
+        span: $DIR/auxiliary/dollar-crate-external.rs:11:17: 11:28 (#15),
     },
     Punct {
         ch: ';',
         spacing: Alone,
-        span: $DIR/auxiliary/dollar-crate-external.rs:11:28: 11:29 (#14),
+        span: $DIR/auxiliary/dollar-crate-external.rs:11:28: 11:29 (#15),
     },
 ]
 PRINT-DERIVE INPUT (DISPLAY): struct D($crate :: S);
 PRINT-DERIVE INPUT (DEBUG): TokenStream [
     Ident {
         ident: "struct",
-        span: $DIR/auxiliary/dollar-crate-external.rs:14:9: 14:15 (#14),
+        span: $DIR/auxiliary/dollar-crate-external.rs:14:9: 14:15 (#15),
     },
     Ident {
         ident: "D",
-        span: $DIR/auxiliary/dollar-crate-external.rs:14:16: 14:17 (#14),
+        span: $DIR/auxiliary/dollar-crate-external.rs:14:16: 14:17 (#15),
     },
     Group {
         delimiter: Parenthesis,
         stream: TokenStream [
             Ident {
                 ident: "$crate",
-                span: $DIR/auxiliary/dollar-crate-external.rs:14:18: 14:24 (#14),
+                span: $DIR/auxiliary/dollar-crate-external.rs:14:18: 14:24 (#15),
             },
             Punct {
                 ch: ':',
                 spacing: Joint,
-                span: $DIR/auxiliary/dollar-crate-external.rs:14:24: 14:25 (#14),
+                span: $DIR/auxiliary/dollar-crate-external.rs:14:24: 14:25 (#15),
             },
             Punct {
                 ch: ':',
                 spacing: Alone,
-                span: $DIR/auxiliary/dollar-crate-external.rs:14:25: 14:26 (#14),
+                span: $DIR/auxiliary/dollar-crate-external.rs:14:25: 14:26 (#15),
             },
             Ident {
                 ident: "S",
-                span: $DIR/auxiliary/dollar-crate-external.rs:14:26: 14:27 (#14),
+                span: $DIR/auxiliary/dollar-crate-external.rs:14:26: 14:27 (#15),
             },
         ],
-        span: $DIR/auxiliary/dollar-crate-external.rs:14:17: 14:28 (#14),
+        span: $DIR/auxiliary/dollar-crate-external.rs:14:17: 14:28 (#15),
     },
     Punct {
         ch: ';',
         spacing: Alone,
-        span: $DIR/auxiliary/dollar-crate-external.rs:14:28: 14:29 (#14),
+        span: $DIR/auxiliary/dollar-crate-external.rs:14:28: 14:29 (#15),
     },
 ]
diff --git a/tests/ui/proc-macro/generate-mod.stderr b/tests/ui/proc-macro/generate-mod.stderr
index 371fd73e507b..af90df2c3dc3 100644
--- a/tests/ui/proc-macro/generate-mod.stderr
+++ b/tests/ui/proc-macro/generate-mod.stderr
@@ -47,6 +47,7 @@ LL | #[derive(generate_mod::CheckDerive)]
    = warning: this was previously accepted by the compiler but is being phased out; it will become a hard error in a future release!
    = note: for more information, see issue #83583 <https://github.com/rust-lang/rust/issues/83583>
    = note: `#[deny(proc_macro_derive_resolution_fallback)]` (part of `#[deny(future_incompatible)]`) on by default
+   = note: this error originates in the derive macro `generate_mod::CheckDerive` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error: cannot find type `OuterDerive` in this scope
   --> $DIR/generate-mod.rs:18:10
@@ -56,6 +57,7 @@ LL | #[derive(generate_mod::CheckDerive)]
    |
    = warning: this was previously accepted by the compiler but is being phased out; it will become a hard error in a future release!
    = note: for more information, see issue #83583 <https://github.com/rust-lang/rust/issues/83583>
+   = note: this error originates in the derive macro `generate_mod::CheckDerive` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error: cannot find type `FromOutside` in this scope
   --> $DIR/generate-mod.rs:25:14
@@ -65,6 +67,7 @@ LL |     #[derive(generate_mod::CheckDerive)]
    |
    = warning: this was previously accepted by the compiler but is being phased out; it will become a hard error in a future release!
    = note: for more information, see issue #83583 <https://github.com/rust-lang/rust/issues/83583>
+   = note: this error originates in the derive macro `generate_mod::CheckDerive` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error: cannot find type `OuterDerive` in this scope
   --> $DIR/generate-mod.rs:25:14
@@ -74,6 +77,7 @@ LL |     #[derive(generate_mod::CheckDerive)]
    |
    = warning: this was previously accepted by the compiler but is being phased out; it will become a hard error in a future release!
    = note: for more information, see issue #83583 <https://github.com/rust-lang/rust/issues/83583>
+   = note: this error originates in the derive macro `generate_mod::CheckDerive` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error: aborting due to 8 previous errors
 
@@ -88,6 +92,7 @@ LL | #[derive(generate_mod::CheckDerive)]
    = warning: this was previously accepted by the compiler but is being phased out; it will become a hard error in a future release!
    = note: for more information, see issue #83583 <https://github.com/rust-lang/rust/issues/83583>
    = note: `#[deny(proc_macro_derive_resolution_fallback)]` (part of `#[deny(future_incompatible)]`) on by default
+   = note: this error originates in the derive macro `generate_mod::CheckDerive` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 Future breakage diagnostic:
 error: cannot find type `OuterDerive` in this scope
@@ -99,6 +104,7 @@ LL | #[derive(generate_mod::CheckDerive)]
    = warning: this was previously accepted by the compiler but is being phased out; it will become a hard error in a future release!
    = note: for more information, see issue #83583 <https://github.com/rust-lang/rust/issues/83583>
    = note: `#[deny(proc_macro_derive_resolution_fallback)]` (part of `#[deny(future_incompatible)]`) on by default
+   = note: this error originates in the derive macro `generate_mod::CheckDerive` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 Future breakage diagnostic:
 error: cannot find type `FromOutside` in this scope
@@ -110,6 +116,7 @@ LL |     #[derive(generate_mod::CheckDerive)]
    = warning: this was previously accepted by the compiler but is being phased out; it will become a hard error in a future release!
    = note: for more information, see issue #83583 <https://github.com/rust-lang/rust/issues/83583>
    = note: `#[deny(proc_macro_derive_resolution_fallback)]` (part of `#[deny(future_incompatible)]`) on by default
+   = note: this error originates in the derive macro `generate_mod::CheckDerive` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 Future breakage diagnostic:
 error: cannot find type `OuterDerive` in this scope
@@ -121,6 +128,7 @@ LL |     #[derive(generate_mod::CheckDerive)]
    = warning: this was previously accepted by the compiler but is being phased out; it will become a hard error in a future release!
    = note: for more information, see issue #83583 <https://github.com/rust-lang/rust/issues/83583>
    = note: `#[deny(proc_macro_derive_resolution_fallback)]` (part of `#[deny(future_incompatible)]`) on by default
+   = note: this error originates in the derive macro `generate_mod::CheckDerive` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 Future breakage diagnostic:
 warning: cannot find type `FromOutside` in this scope
@@ -131,6 +139,7 @@ LL | #[derive(generate_mod::CheckDeriveLint)] // OK, lint is suppressed
    |
    = warning: this was previously accepted by the compiler but is being phased out; it will become a hard error in a future release!
    = note: for more information, see issue #83583 <https://github.com/rust-lang/rust/issues/83583>
+   = note: this warning originates in the derive macro `generate_mod::CheckDeriveLint` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 Future breakage diagnostic:
 warning: cannot find type `OuterDeriveLint` in this scope
@@ -141,4 +150,5 @@ LL | #[derive(generate_mod::CheckDeriveLint)] // OK, lint is suppressed
    |
    = warning: this was previously accepted by the compiler but is being phased out; it will become a hard error in a future release!
    = note: for more information, see issue #83583 <https://github.com/rust-lang/rust/issues/83583>
+   = note: this warning originates in the derive macro `generate_mod::CheckDeriveLint` (in Nightly builds, run with -Z macro-backtrace for more info)
 
diff --git a/tests/ui/proc-macro/nested-macro-rules.stdout b/tests/ui/proc-macro/nested-macro-rules.stdout
index 5b678554b9e0..89fb7b042218 100644
--- a/tests/ui/proc-macro/nested-macro-rules.stdout
+++ b/tests/ui/proc-macro/nested-macro-rules.stdout
@@ -2,45 +2,45 @@ PRINT-BANG INPUT (DISPLAY): FirstStruct
 PRINT-BANG INPUT (DEBUG): TokenStream [
     Ident {
         ident: "FirstStruct",
-        span: $DIR/auxiliary/nested-macro-rules.rs:16:14: 16:25 (#6),
+        span: $DIR/auxiliary/nested-macro-rules.rs:16:14: 16:25 (#7),
     },
 ]
 PRINT-ATTR INPUT (DISPLAY): struct FirstAttrStruct {}
 PRINT-ATTR INPUT (DEBUG): TokenStream [
     Ident {
         ident: "struct",
-        span: $DIR/auxiliary/nested-macro-rules.rs:10:32: 10:38 (#5),
+        span: $DIR/auxiliary/nested-macro-rules.rs:10:32: 10:38 (#6),
     },
     Ident {
         ident: "FirstAttrStruct",
-        span: $DIR/auxiliary/nested-macro-rules.rs:16:27: 16:42 (#6),
+        span: $DIR/auxiliary/nested-macro-rules.rs:16:27: 16:42 (#7),
     },
     Group {
         delimiter: Brace,
         stream: TokenStream [],
-        span: $DIR/auxiliary/nested-macro-rules.rs:10:57: 10:59 (#5),
+        span: $DIR/auxiliary/nested-macro-rules.rs:10:57: 10:59 (#6),
     },
 ]
 PRINT-BANG INPUT (DISPLAY): SecondStruct
 PRINT-BANG INPUT (DEBUG): TokenStream [
     Ident {
         ident: "SecondStruct",
-        span: $DIR/nested-macro-rules.rs:23:38: 23:50 (#15),
+        span: $DIR/nested-macro-rules.rs:23:38: 23:50 (#16),
     },
 ]
 PRINT-ATTR INPUT (DISPLAY): struct SecondAttrStruct {}
 PRINT-ATTR INPUT (DEBUG): TokenStream [
     Ident {
         ident: "struct",
-        span: $DIR/auxiliary/nested-macro-rules.rs:10:32: 10:38 (#14),
+        span: $DIR/auxiliary/nested-macro-rules.rs:10:32: 10:38 (#15),
     },
     Ident {
         ident: "SecondAttrStruct",
-        span: $DIR/nested-macro-rules.rs:23:52: 23:68 (#15),
+        span: $DIR/nested-macro-rules.rs:23:52: 23:68 (#16),
     },
     Group {
         delimiter: Brace,
         stream: TokenStream [],
-        span: $DIR/auxiliary/nested-macro-rules.rs:10:57: 10:59 (#14),
+        span: $DIR/auxiliary/nested-macro-rules.rs:10:57: 10:59 (#15),
     },
 ]

From 4ae692df6f1bf7497d4bd55d6d0d80e98d860a45 Mon Sep 17 00:00:00 2001
From: Guillaume Gomez <guillaume1.gomez@gmail.com>
Date: Tue, 27 Jan 2026 16:47:26 +0100
Subject: [PATCH 77/97] Update `askama` version to `0.15.2`

---
 Cargo.lock                              | 16 ++++++++--------
 src/ci/citool/Cargo.toml                |  2 +-
 src/librustdoc/Cargo.toml               |  2 +-
 src/tools/generate-copyright/Cargo.toml |  2 +-
 4 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/Cargo.lock b/Cargo.lock
index 1bc531ba916c..cfc0d254f6f0 100644
--- a/Cargo.lock
+++ b/Cargo.lock
@@ -184,9 +184,9 @@ checksum = "7c02d123df017efcdfbd739ef81735b36c5ba83ec3c59c80a9d7ecc718f92e50"
 
 [[package]]
 name = "askama"
-version = "0.15.1"
+version = "0.15.2"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "bb7125972258312e79827b60c9eb93938334100245081cf701a2dee981b17427"
+checksum = "03341eae1125472b0672fbf35cc9aa7b74cd8e0c3d02f02c28a04678f12aaa7a"
 dependencies = [
  "askama_macros",
  "itoa",
@@ -197,9 +197,9 @@ dependencies = [
 
 [[package]]
 name = "askama_derive"
-version = "0.15.1"
+version = "0.15.2"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "8ba5e7259a1580c61571e3116ebaaa01e3c001b2132b17c4cc5c70780ca3e994"
+checksum = "461bd78f3da90b5e44eee4272cfb1c4832aa3dcdb6c370aedd3eb253d2b9e3ca"
 dependencies = [
  "askama_parser",
  "basic-toml",
@@ -214,18 +214,18 @@ dependencies = [
 
 [[package]]
 name = "askama_macros"
-version = "0.15.1"
+version = "0.15.2"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "236ce20b77cb13506eaf5024899f4af6e12e8825f390bd943c4c37fd8f322e46"
+checksum = "ba49fb22ee3074574b8510abd9495d4f0bb9b8f87e8e45ee31e2cee508f7a8e5"
 dependencies = [
  "askama_derive",
 ]
 
 [[package]]
 name = "askama_parser"
-version = "0.15.1"
+version = "0.15.2"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "f3c63392767bb2df6aa65a6e1e3b80fd89bb7af6d58359b924c0695620f1512e"
+checksum = "7e33eb7484958aaa1f27e9adb556f5d557331cd891bdbb33781bc1f9550b6f6e"
 dependencies = [
  "rustc-hash 2.1.1",
  "serde",
diff --git a/src/ci/citool/Cargo.toml b/src/ci/citool/Cargo.toml
index 539edf60033a..b394c6fbefff 100644
--- a/src/ci/citool/Cargo.toml
+++ b/src/ci/citool/Cargo.toml
@@ -5,7 +5,7 @@ edition = "2024"
 
 [dependencies]
 anyhow = "1"
-askama = "0.15.1"
+askama = "0.15.2"
 clap = { version = "4.5", features = ["derive"] }
 csv = "1"
 diff = "0.1"
diff --git a/src/librustdoc/Cargo.toml b/src/librustdoc/Cargo.toml
index 3c5d01c7201b..43006435fcde 100644
--- a/src/librustdoc/Cargo.toml
+++ b/src/librustdoc/Cargo.toml
@@ -10,7 +10,7 @@ path = "lib.rs"
 [dependencies]
 # tidy-alphabetical-start
 arrayvec = { version = "0.7", default-features = false }
-askama = { version = "0.15.1", default-features = false, features = ["alloc", "config", "derive"] }
+askama = { version = "0.15.2", default-features = false, features = ["alloc", "config", "derive"] }
 base64 = "0.21.7"
 indexmap = { version = "2", features = ["serde"] }
 itertools = "0.12"
diff --git a/src/tools/generate-copyright/Cargo.toml b/src/tools/generate-copyright/Cargo.toml
index 66b9f394409b..e1a5ca31a1db 100644
--- a/src/tools/generate-copyright/Cargo.toml
+++ b/src/tools/generate-copyright/Cargo.toml
@@ -8,7 +8,7 @@ description = "Produces a manifest of all the copyrighted materials in the Rust
 
 [dependencies]
 anyhow = "1.0.65"
-askama = "0.15.1"
+askama = "0.15.2"
 cargo_metadata = "0.21"
 serde = { version = "1.0.147", features = ["derive"] }
 serde_json = "1.0.85"

From 354365a0e0055c6f908a2d1965a8b86ebf4f11d1 Mon Sep 17 00:00:00 2001
From: Reuben Cruise <reuben.cruise@arm.com>
Date: Wed, 14 Jan 2026 16:46:45 +0000
Subject: [PATCH 78/97] Adds some arm intrinsics to bring more up-to-date with
 acle

- Adds vluti2 intrinsics
- Adds famin/famax intrinsics
- Adds vstl1(q) intrinsics
- Adds vldap1(q) intrinsics
	- Excludes vldap1_lane_f64 as in testing it fails assert_intr. There seems to be some bad IR gen from rust.
- Adds vscale(q) intrinsics
- Adds new intrinsics to arm_intrinsics.json
	- Had to be done manually as intrinsics are not yet on developer.arm.com
---
 .../core_arch/src/aarch64/neon/generated.rs   |  669 +++++++-
 .../crates/intrinsic-test/missing_aarch64.txt |   52 +-
 .../intrinsic-test/missing_aarch64_be.txt     |   51 +-
 .../spec/neon/aarch64.spec.yml                |  235 ++-
 .../intrinsics_data/arm_intrinsics.json       | 1385 ++++++++++++++++-
 5 files changed, 2258 insertions(+), 134 deletions(-)

diff --git a/library/stdarch/crates/core_arch/src/aarch64/neon/generated.rs b/library/stdarch/crates/core_arch/src/aarch64/neon/generated.rs
index b042bd0c3c72..b763d64ca3bc 100644
--- a/library/stdarch/crates/core_arch/src/aarch64/neon/generated.rs
+++ b/library/stdarch/crates/core_arch/src/aarch64/neon/generated.rs
@@ -733,10 +733,42 @@ pub fn vaddvq_u64(a: uint64x2_t) -> u64 {
     unsafe { simd_reduce_add_ordered(a, 0) }
 }
 #[doc = "Multi-vector floating-point absolute maximum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vamax_f16)"]
+#[inline]
+#[target_feature(enable = "neon,faminmax")]
+#[cfg_attr(test, assert_instr(famax))]
+#[unstable(feature = "faminmax", issue = "137933")]
+pub fn vamax_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            any(target_arch = "aarch64", target_arch = "arm64ec"),
+            link_name = "llvm.aarch64.neon.famax.v4f16"
+        )]
+        fn _vamax_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t;
+    }
+    unsafe { _vamax_f16(a, b) }
+}
+#[doc = "Multi-vector floating-point absolute maximum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vamaxq_f16)"]
+#[inline]
+#[target_feature(enable = "neon,faminmax")]
+#[cfg_attr(test, assert_instr(famax))]
+#[unstable(feature = "faminmax", issue = "137933")]
+pub fn vamaxq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            any(target_arch = "aarch64", target_arch = "arm64ec"),
+            link_name = "llvm.aarch64.neon.famax.v8f16"
+        )]
+        fn _vamaxq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t;
+    }
+    unsafe { _vamaxq_f16(a, b) }
+}
+#[doc = "Multi-vector floating-point absolute maximum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vamax_f32)"]
 #[inline(always)]
 #[target_feature(enable = "neon,faminmax")]
-#[cfg_attr(test, assert_instr(nop))]
+#[cfg_attr(test, assert_instr(famax))]
 #[unstable(feature = "faminmax", issue = "137933")]
 pub fn vamax_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
     unsafe extern "unadjusted" {
@@ -752,7 +784,7 @@ pub fn vamax_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vamaxq_f32)"]
 #[inline(always)]
 #[target_feature(enable = "neon,faminmax")]
-#[cfg_attr(test, assert_instr(nop))]
+#[cfg_attr(test, assert_instr(famax))]
 #[unstable(feature = "faminmax", issue = "137933")]
 pub fn vamaxq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
     unsafe extern "unadjusted" {
@@ -768,7 +800,7 @@ pub fn vamaxq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vamaxq_f64)"]
 #[inline(always)]
 #[target_feature(enable = "neon,faminmax")]
-#[cfg_attr(test, assert_instr(nop))]
+#[cfg_attr(test, assert_instr(famax))]
 #[unstable(feature = "faminmax", issue = "137933")]
 pub fn vamaxq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
     unsafe extern "unadjusted" {
@@ -781,10 +813,42 @@ pub fn vamaxq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
     unsafe { _vamaxq_f64(a, b) }
 }
 #[doc = "Multi-vector floating-point absolute minimum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vamin_f16)"]
+#[inline]
+#[target_feature(enable = "neon,faminmax")]
+#[cfg_attr(test, assert_instr(famin))]
+#[unstable(feature = "faminmax", issue = "137933")]
+pub fn vamin_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            any(target_arch = "aarch64", target_arch = "arm64ec"),
+            link_name = "llvm.aarch64.neon.famin.v4f16"
+        )]
+        fn _vamin_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t;
+    }
+    unsafe { _vamin_f16(a, b) }
+}
+#[doc = "Multi-vector floating-point absolute minimum"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaminq_f16)"]
+#[inline]
+#[target_feature(enable = "neon,faminmax")]
+#[cfg_attr(test, assert_instr(famin))]
+#[unstable(feature = "faminmax", issue = "137933")]
+pub fn vaminq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            any(target_arch = "aarch64", target_arch = "arm64ec"),
+            link_name = "llvm.aarch64.neon.famin.v8f16"
+        )]
+        fn _vaminq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t;
+    }
+    unsafe { _vaminq_f16(a, b) }
+}
+#[doc = "Multi-vector floating-point absolute minimum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vamin_f32)"]
 #[inline(always)]
 #[target_feature(enable = "neon,faminmax")]
-#[cfg_attr(test, assert_instr(nop))]
+#[cfg_attr(test, assert_instr(famin))]
 #[unstable(feature = "faminmax", issue = "137933")]
 pub fn vamin_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
     unsafe extern "unadjusted" {
@@ -800,7 +864,7 @@ pub fn vamin_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaminq_f32)"]
 #[inline(always)]
 #[target_feature(enable = "neon,faminmax")]
-#[cfg_attr(test, assert_instr(nop))]
+#[cfg_attr(test, assert_instr(famin))]
 #[unstable(feature = "faminmax", issue = "137933")]
 pub fn vaminq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
     unsafe extern "unadjusted" {
@@ -816,7 +880,7 @@ pub fn vaminq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaminq_f64)"]
 #[inline(always)]
 #[target_feature(enable = "neon,faminmax")]
-#[cfg_attr(test, assert_instr(nop))]
+#[cfg_attr(test, assert_instr(famin))]
 #[unstable(feature = "faminmax", issue = "137933")]
 pub fn vaminq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
     unsafe extern "unadjusted" {
@@ -12847,6 +12911,237 @@ pub unsafe fn vld4q_u64(a: *const u64) -> uint64x2x4_t {
     ret_val.3 = unsafe { simd_shuffle!(ret_val.3, ret_val.3, [1, 0]) };
     ret_val
 }
+#[doc = "Load-acquire RCpc one single-element structure to one lane of one register"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldap1_lane_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * Neon instrinsic unsafe"]
+#[inline]
+#[target_feature(enable = "neon,rcpc3")]
+#[cfg_attr(test, assert_instr(ldap1, LANE = 0))]
+#[rustc_legacy_const_generics(2)]
+#[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")]
+pub unsafe fn vldap1_lane_s64<const LANE: i32>(ptr: *const i64, src: int64x1_t) -> int64x1_t {
+    static_assert!(LANE == 0);
+    let atomic_src = crate::sync::atomic::AtomicI64::from_ptr(ptr as *mut i64);
+    simd_insert!(
+        src,
+        LANE as u32,
+        atomic_src.load(crate::sync::atomic::Ordering::Acquire)
+    )
+}
+#[doc = "Load-acquire RCpc one single-element structure to one lane of one register"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldap1q_lane_s64)"]
+#[doc = "## Safety"]
+#[doc = "  * Neon instrinsic unsafe"]
+#[inline]
+#[target_feature(enable = "neon,rcpc3")]
+#[cfg_attr(test, assert_instr(ldap1, LANE = 0))]
+#[rustc_legacy_const_generics(2)]
+#[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")]
+pub unsafe fn vldap1q_lane_s64<const LANE: i32>(ptr: *const i64, src: int64x2_t) -> int64x2_t {
+    static_assert_uimm_bits!(LANE, 1);
+    let atomic_src = crate::sync::atomic::AtomicI64::from_ptr(ptr as *mut i64);
+    simd_insert!(
+        src,
+        LANE as u32,
+        atomic_src.load(crate::sync::atomic::Ordering::Acquire)
+    )
+}
+#[doc = "Load-acquire RCpc one single-element structure to one lane of one register"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldap1q_lane_f64)"]
+#[doc = "## Safety"]
+#[doc = "  * Neon instrinsic unsafe"]
+#[inline]
+#[rustc_legacy_const_generics(2)]
+#[target_feature(enable = "neon,rcpc3")]
+#[cfg_attr(test, assert_instr(ldap1, LANE = 0))]
+#[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")]
+pub unsafe fn vldap1q_lane_f64<const LANE: i32>(ptr: *const f64, src: float64x2_t) -> float64x2_t {
+    static_assert_uimm_bits!(LANE, 1);
+    transmute(vldap1q_lane_s64::<LANE>(ptr as *mut i64, transmute(src)))
+}
+#[doc = "Load-acquire RCpc one single-element structure to one lane of one register"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldap1_lane_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * Neon instrinsic unsafe"]
+#[inline]
+#[rustc_legacy_const_generics(2)]
+#[target_feature(enable = "neon,rcpc3")]
+#[cfg_attr(test, assert_instr(ldap1, LANE = 0))]
+#[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")]
+pub unsafe fn vldap1_lane_u64<const LANE: i32>(ptr: *const u64, src: uint64x1_t) -> uint64x1_t {
+    static_assert!(LANE == 0);
+    transmute(vldap1_lane_s64::<LANE>(ptr as *mut i64, transmute(src)))
+}
+#[doc = "Load-acquire RCpc one single-element structure to one lane of one register"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldap1q_lane_u64)"]
+#[doc = "## Safety"]
+#[doc = "  * Neon instrinsic unsafe"]
+#[inline]
+#[rustc_legacy_const_generics(2)]
+#[target_feature(enable = "neon,rcpc3")]
+#[cfg_attr(test, assert_instr(ldap1, LANE = 0))]
+#[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")]
+pub unsafe fn vldap1q_lane_u64<const LANE: i32>(ptr: *const u64, src: uint64x2_t) -> uint64x2_t {
+    static_assert_uimm_bits!(LANE, 1);
+    transmute(vldap1q_lane_s64::<LANE>(ptr as *mut i64, transmute(src)))
+}
+#[doc = "Load-acquire RCpc one single-element structure to one lane of one register"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldap1_lane_p64)"]
+#[doc = "## Safety"]
+#[doc = "  * Neon instrinsic unsafe"]
+#[inline]
+#[rustc_legacy_const_generics(2)]
+#[target_feature(enable = "neon,rcpc3")]
+#[cfg_attr(test, assert_instr(ldap1, LANE = 0))]
+#[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")]
+pub unsafe fn vldap1_lane_p64<const LANE: i32>(ptr: *const p64, src: poly64x1_t) -> poly64x1_t {
+    static_assert!(LANE == 0);
+    transmute(vldap1_lane_s64::<LANE>(ptr as *mut i64, transmute(src)))
+}
+#[doc = "Load-acquire RCpc one single-element structure to one lane of one register"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldap1q_lane_p64)"]
+#[doc = "## Safety"]
+#[doc = "  * Neon instrinsic unsafe"]
+#[inline]
+#[rustc_legacy_const_generics(2)]
+#[target_feature(enable = "neon,rcpc3")]
+#[cfg_attr(test, assert_instr(ldap1, LANE = 0))]
+#[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")]
+pub unsafe fn vldap1q_lane_p64<const LANE: i32>(ptr: *const p64, src: poly64x2_t) -> poly64x2_t {
+    static_assert_uimm_bits!(LANE, 1);
+    transmute(vldap1q_lane_s64::<LANE>(ptr as *mut i64, transmute(src)))
+}
+#[doc = "Lookup table read with 2-bit indices"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_f16)"]
+#[doc = "## Safety"]
+#[doc = "  * Neon instrinsic unsafe"]
+#[inline]
+#[target_feature(enable = "neon,lut")]
+#[cfg_attr(test, assert_instr(nop, INDEX = 1))]
+#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
+#[rustc_legacy_const_generics(2)]
+pub unsafe fn vluti2_lane_f16<const INDEX: i32>(a: float16x4_t, b: uint8x8_t) -> float16x8_t {
+    static_assert!(INDEX >= 0 && INDEX <= 3);
+    transmute(vluti2_lane_s16::<INDEX>(transmute(a), b))
+}
+#[doc = "Lookup table read with 2-bit indices"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_f16)"]
+#[doc = "## Safety"]
+#[doc = "  * Neon instrinsic unsafe"]
+#[inline]
+#[target_feature(enable = "neon,lut")]
+#[cfg_attr(test, assert_instr(nop, INDEX = 1))]
+#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
+#[rustc_legacy_const_generics(2)]
+pub unsafe fn vluti2q_lane_f16<const INDEX: i32>(a: float16x8_t, b: uint8x8_t) -> float16x8_t {
+    static_assert!(INDEX >= 0 && INDEX <= 3);
+    transmute(vluti2q_lane_s16::<INDEX>(transmute(a), b))
+}
+#[doc = "Lookup table read with 2-bit indices"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_u8)"]
+#[doc = "## Safety"]
+#[doc = "  * Neon instrinsic unsafe"]
+#[inline]
+#[target_feature(enable = "neon,lut")]
+#[cfg_attr(test, assert_instr(nop, INDEX = 1))]
+#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
+#[rustc_legacy_const_generics(2)]
+pub unsafe fn vluti2_lane_u8<const INDEX: i32>(a: uint8x8_t, b: uint8x8_t) -> uint8x16_t {
+    static_assert!(INDEX >= 0 && INDEX <= 1);
+    transmute(vluti2_lane_s8::<INDEX>(transmute(a), b))
+}
+#[doc = "Lookup table read with 2-bit indices"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_u8)"]
+#[doc = "## Safety"]
+#[doc = "  * Neon instrinsic unsafe"]
+#[inline]
+#[target_feature(enable = "neon,lut")]
+#[cfg_attr(test, assert_instr(nop, INDEX = 1))]
+#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
+#[rustc_legacy_const_generics(2)]
+pub unsafe fn vluti2q_lane_u8<const INDEX: i32>(a: uint8x16_t, b: uint8x8_t) -> uint8x16_t {
+    static_assert!(INDEX >= 0 && INDEX <= 1);
+    transmute(vluti2q_lane_s8::<INDEX>(transmute(a), b))
+}
+#[doc = "Lookup table read with 2-bit indices"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_u16)"]
+#[doc = "## Safety"]
+#[doc = "  * Neon instrinsic unsafe"]
+#[inline]
+#[target_feature(enable = "neon,lut")]
+#[cfg_attr(test, assert_instr(nop, INDEX = 1))]
+#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
+#[rustc_legacy_const_generics(2)]
+pub unsafe fn vluti2_lane_u16<const INDEX: i32>(a: uint16x4_t, b: uint8x8_t) -> uint16x8_t {
+    static_assert!(INDEX >= 0 && INDEX <= 3);
+    transmute(vluti2_lane_s16::<INDEX>(transmute(a), b))
+}
+#[doc = "Lookup table read with 2-bit indices"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_u16)"]
+#[doc = "## Safety"]
+#[doc = "  * Neon instrinsic unsafe"]
+#[inline]
+#[target_feature(enable = "neon,lut")]
+#[cfg_attr(test, assert_instr(nop, INDEX = 1))]
+#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
+#[rustc_legacy_const_generics(2)]
+pub unsafe fn vluti2q_lane_u16<const INDEX: i32>(a: uint16x8_t, b: uint8x8_t) -> uint16x8_t {
+    static_assert!(INDEX >= 0 && INDEX <= 3);
+    transmute(vluti2q_lane_s16::<INDEX>(transmute(a), b))
+}
+#[doc = "Lookup table read with 2-bit indices"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_p8)"]
+#[doc = "## Safety"]
+#[doc = "  * Neon instrinsic unsafe"]
+#[inline]
+#[target_feature(enable = "neon,lut")]
+#[cfg_attr(test, assert_instr(nop, INDEX = 1))]
+#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
+#[rustc_legacy_const_generics(2)]
+pub unsafe fn vluti2_lane_p8<const INDEX: i32>(a: poly8x8_t, b: uint8x8_t) -> poly8x16_t {
+    static_assert!(INDEX >= 0 && INDEX <= 1);
+    transmute(vluti2_lane_s8::<INDEX>(transmute(a), b))
+}
+#[doc = "Lookup table read with 2-bit indices"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_p8)"]
+#[doc = "## Safety"]
+#[doc = "  * Neon instrinsic unsafe"]
+#[inline]
+#[target_feature(enable = "neon,lut")]
+#[cfg_attr(test, assert_instr(nop, INDEX = 1))]
+#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
+#[rustc_legacy_const_generics(2)]
+pub unsafe fn vluti2q_lane_p8<const INDEX: i32>(a: poly8x16_t, b: uint8x8_t) -> poly8x16_t {
+    static_assert!(INDEX >= 0 && INDEX <= 1);
+    transmute(vluti2q_lane_s8::<INDEX>(transmute(a), b))
+}
+#[doc = "Lookup table read with 2-bit indices"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_p16)"]
+#[doc = "## Safety"]
+#[doc = "  * Neon instrinsic unsafe"]
+#[inline]
+#[target_feature(enable = "neon,lut")]
+#[cfg_attr(test, assert_instr(nop, INDEX = 1))]
+#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
+#[rustc_legacy_const_generics(2)]
+pub unsafe fn vluti2_lane_p16<const INDEX: i32>(a: poly16x4_t, b: uint8x8_t) -> poly16x8_t {
+    static_assert!(INDEX >= 0 && INDEX <= 3);
+    transmute(vluti2_lane_s16::<INDEX>(transmute(a), b))
+}
+#[doc = "Lookup table read with 2-bit indices"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_p16)"]
+#[doc = "## Safety"]
+#[doc = "  * Neon instrinsic unsafe"]
+#[inline]
+#[target_feature(enable = "neon,lut")]
+#[cfg_attr(test, assert_instr(nop, INDEX = 1))]
+#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
+#[rustc_legacy_const_generics(2)]
+pub unsafe fn vluti2q_lane_p16<const INDEX: i32>(a: poly16x8_t, b: uint8x8_t) -> poly16x8_t {
+    static_assert!(INDEX >= 0 && INDEX <= 3);
+    transmute(vluti2q_lane_s16::<INDEX>(transmute(a), b))
+}
 #[doc = "Lookup table read with 2-bit indices"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_s8)"]
 #[doc = "## Safety"]
@@ -12928,108 +13223,214 @@ pub unsafe fn vluti2q_lane_s16<const LANE: i32>(a: int16x8_t, b: uint8x8_t) -> i
     _vluti2q_lane_s16(a, b, LANE)
 }
 #[doc = "Lookup table read with 2-bit indices"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_u8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_laneq_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,lut")]
-#[cfg_attr(test, assert_instr(nop, LANE = 1))]
+#[cfg_attr(test, assert_instr(nop, INDEX = 1))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
 #[rustc_legacy_const_generics(2)]
-pub unsafe fn vluti2_lane_u8<const LANE: i32>(a: uint8x8_t, b: uint8x8_t) -> uint8x16_t {
-    static_assert!(LANE >= 0 && LANE <= 1);
-    transmute(vluti2_lane_s8::<LANE>(transmute(a), b))
+pub unsafe fn vluti2_laneq_f16<const INDEX: i32>(a: float16x4_t, b: uint8x16_t) -> float16x8_t {
+    static_assert!(INDEX >= 0 && INDEX <= 7);
+    transmute(vluti2_laneq_s16::<INDEX>(transmute(a), b))
 }
 #[doc = "Lookup table read with 2-bit indices"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_u8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_laneq_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,lut")]
-#[cfg_attr(test, assert_instr(nop, LANE = 1))]
+#[cfg_attr(test, assert_instr(nop, INDEX = 1))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
 #[rustc_legacy_const_generics(2)]
-pub unsafe fn vluti2q_lane_u8<const LANE: i32>(a: uint8x16_t, b: uint8x8_t) -> uint8x16_t {
-    static_assert!(LANE >= 0 && LANE <= 1);
-    transmute(vluti2q_lane_s8::<LANE>(transmute(a), b))
+pub unsafe fn vluti2q_laneq_f16<const INDEX: i32>(a: float16x8_t, b: uint8x16_t) -> float16x8_t {
+    static_assert!(INDEX >= 0 && INDEX <= 7);
+    transmute(vluti2q_laneq_s16::<INDEX>(transmute(a), b))
 }
 #[doc = "Lookup table read with 2-bit indices"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_u16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_laneq_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,lut")]
-#[cfg_attr(test, assert_instr(nop, LANE = 1))]
+#[cfg_attr(test, assert_instr(nop, INDEX = 1))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
 #[rustc_legacy_const_generics(2)]
-pub unsafe fn vluti2_lane_u16<const LANE: i32>(a: uint16x4_t, b: uint8x8_t) -> uint16x8_t {
-    static_assert!(LANE >= 0 && LANE <= 3);
-    transmute(vluti2_lane_s16::<LANE>(transmute(a), b))
+pub unsafe fn vluti2_laneq_u8<const INDEX: i32>(a: uint8x8_t, b: uint8x16_t) -> uint8x16_t {
+    static_assert!(INDEX >= 0 && INDEX <= 3);
+    transmute(vluti2_laneq_s8::<INDEX>(transmute(a), b))
 }
 #[doc = "Lookup table read with 2-bit indices"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_u16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_laneq_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,lut")]
-#[cfg_attr(test, assert_instr(nop, LANE = 1))]
+#[cfg_attr(test, assert_instr(nop, INDEX = 1))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
 #[rustc_legacy_const_generics(2)]
-pub unsafe fn vluti2q_lane_u16<const LANE: i32>(a: uint16x8_t, b: uint8x8_t) -> uint16x8_t {
-    static_assert!(LANE >= 0 && LANE <= 3);
-    transmute(vluti2q_lane_s16::<LANE>(transmute(a), b))
+pub unsafe fn vluti2q_laneq_u8<const INDEX: i32>(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
+    static_assert!(INDEX >= 0 && INDEX <= 3);
+    transmute(vluti2q_laneq_s8::<INDEX>(transmute(a), b))
 }
 #[doc = "Lookup table read with 2-bit indices"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_p8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_laneq_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,lut")]
-#[cfg_attr(test, assert_instr(nop, LANE = 1))]
+#[cfg_attr(test, assert_instr(nop, INDEX = 1))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
 #[rustc_legacy_const_generics(2)]
-pub unsafe fn vluti2_lane_p8<const LANE: i32>(a: poly8x8_t, b: uint8x8_t) -> poly8x16_t {
-    static_assert!(LANE >= 0 && LANE <= 1);
-    transmute(vluti2_lane_s8::<LANE>(transmute(a), b))
+pub unsafe fn vluti2_laneq_u16<const INDEX: i32>(a: uint16x4_t, b: uint8x16_t) -> uint16x8_t {
+    static_assert!(INDEX >= 0 && INDEX <= 7);
+    transmute(vluti2_laneq_s16::<INDEX>(transmute(a), b))
 }
 #[doc = "Lookup table read with 2-bit indices"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_p8)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_laneq_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,lut")]
-#[cfg_attr(test, assert_instr(nop, LANE = 1))]
+#[cfg_attr(test, assert_instr(nop, INDEX = 1))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
 #[rustc_legacy_const_generics(2)]
-pub unsafe fn vluti2q_lane_p8<const LANE: i32>(a: poly8x16_t, b: uint8x8_t) -> poly8x16_t {
-    static_assert!(LANE >= 0 && LANE <= 1);
-    transmute(vluti2q_lane_s8::<LANE>(transmute(a), b))
+pub unsafe fn vluti2q_laneq_u16<const INDEX: i32>(a: uint16x8_t, b: uint8x16_t) -> uint16x8_t {
+    static_assert!(INDEX >= 0 && INDEX <= 7);
+    transmute(vluti2q_laneq_s16::<INDEX>(transmute(a), b))
 }
 #[doc = "Lookup table read with 2-bit indices"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_p16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_laneq_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,lut")]
-#[cfg_attr(test, assert_instr(nop, LANE = 1))]
+#[cfg_attr(test, assert_instr(nop, INDEX = 1))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
 #[rustc_legacy_const_generics(2)]
-pub unsafe fn vluti2_lane_p16<const LANE: i32>(a: poly16x4_t, b: uint8x8_t) -> poly16x8_t {
-    static_assert!(LANE >= 0 && LANE <= 3);
-    transmute(vluti2_lane_s16::<LANE>(transmute(a), b))
+pub unsafe fn vluti2_laneq_p8<const INDEX: i32>(a: poly8x8_t, b: uint8x16_t) -> poly8x16_t {
+    static_assert!(INDEX >= 0 && INDEX <= 3);
+    transmute(vluti2_laneq_s8::<INDEX>(transmute(a), b))
 }
 #[doc = "Lookup table read with 2-bit indices"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_p16)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_laneq_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,lut")]
-#[cfg_attr(test, assert_instr(nop, LANE = 1))]
+#[cfg_attr(test, assert_instr(nop, INDEX = 1))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
 #[rustc_legacy_const_generics(2)]
-pub unsafe fn vluti2q_lane_p16<const LANE: i32>(a: poly16x8_t, b: uint8x8_t) -> poly16x8_t {
-    static_assert!(LANE >= 0 && LANE <= 3);
-    transmute(vluti2q_lane_s16::<LANE>(transmute(a), b))
+pub unsafe fn vluti2q_laneq_p8<const INDEX: i32>(a: poly8x16_t, b: uint8x16_t) -> poly8x16_t {
+    static_assert!(INDEX >= 0 && INDEX <= 3);
+    transmute(vluti2q_laneq_s8::<INDEX>(transmute(a), b))
+}
+#[doc = "Lookup table read with 2-bit indices"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_laneq_p16)"]
+#[doc = "## Safety"]
+#[doc = "  * Neon instrinsic unsafe"]
+#[inline]
+#[target_feature(enable = "neon,lut")]
+#[cfg_attr(test, assert_instr(nop, INDEX = 1))]
+#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
+#[rustc_legacy_const_generics(2)]
+pub unsafe fn vluti2_laneq_p16<const INDEX: i32>(a: poly16x4_t, b: uint8x16_t) -> poly16x8_t {
+    static_assert!(INDEX >= 0 && INDEX <= 7);
+    transmute(vluti2_laneq_s16::<INDEX>(transmute(a), b))
+}
+#[doc = "Lookup table read with 2-bit indices"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_laneq_p16)"]
+#[doc = "## Safety"]
+#[doc = "  * Neon instrinsic unsafe"]
+#[inline]
+#[target_feature(enable = "neon,lut")]
+#[cfg_attr(test, assert_instr(nop, INDEX = 1))]
+#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
+#[rustc_legacy_const_generics(2)]
+pub unsafe fn vluti2q_laneq_p16<const INDEX: i32>(a: poly16x8_t, b: uint8x16_t) -> poly16x8_t {
+    static_assert!(INDEX >= 0 && INDEX <= 7);
+    transmute(vluti2q_laneq_s16::<INDEX>(transmute(a), b))
+}
+#[doc = "Lookup table read with 2-bit indices"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_laneq_s8)"]
+#[doc = "## Safety"]
+#[doc = "  * Neon instrinsic unsafe"]
+#[inline]
+#[target_feature(enable = "neon,lut")]
+#[cfg_attr(test, assert_instr(nop, INDEX = 1))]
+#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
+#[rustc_legacy_const_generics(2)]
+pub unsafe fn vluti2_laneq_s8<const INDEX: i32>(a: int8x8_t, b: uint8x16_t) -> int8x16_t {
+    static_assert!(INDEX >= 0 && INDEX <= 3);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            any(target_arch = "aarch64", target_arch = "arm64ec"),
+            link_name = "llvm.aarch64.neon.vluti2.laneq.v16i8.v8i8"
+        )]
+        fn _vluti2_laneq_s8(a: int8x8_t, b: uint8x16_t, n: i32) -> int8x16_t;
+    }
+    _vluti2_laneq_s8(a, b, INDEX)
+}
+#[doc = "Lookup table read with 2-bit indices"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_laneq_s8)"]
+#[doc = "## Safety"]
+#[doc = "  * Neon instrinsic unsafe"]
+#[inline]
+#[target_feature(enable = "neon,lut")]
+#[cfg_attr(test, assert_instr(nop, INDEX = 1))]
+#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
+#[rustc_legacy_const_generics(2)]
+pub unsafe fn vluti2q_laneq_s8<const INDEX: i32>(a: int8x16_t, b: uint8x16_t) -> int8x16_t {
+    static_assert!(INDEX >= 0 && INDEX <= 3);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            any(target_arch = "aarch64", target_arch = "arm64ec"),
+            link_name = "llvm.aarch64.neon.vluti2.laneq.v16i8.v16i8"
+        )]
+        fn _vluti2q_laneq_s8(a: int8x16_t, b: uint8x16_t, n: i32) -> int8x16_t;
+    }
+    _vluti2q_laneq_s8(a, b, INDEX)
+}
+#[doc = "Lookup table read with 2-bit indices"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_laneq_s16)"]
+#[doc = "## Safety"]
+#[doc = "  * Neon instrinsic unsafe"]
+#[inline]
+#[target_feature(enable = "neon,lut")]
+#[cfg_attr(test, assert_instr(nop, INDEX = 1))]
+#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
+#[rustc_legacy_const_generics(2)]
+pub unsafe fn vluti2_laneq_s16<const INDEX: i32>(a: int16x4_t, b: uint8x16_t) -> int16x8_t {
+    static_assert!(INDEX >= 0 && INDEX <= 7);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            any(target_arch = "aarch64", target_arch = "arm64ec"),
+            link_name = "llvm.aarch64.neon.vluti2.laneq.v8i16.v4i16"
+        )]
+        fn _vluti2_laneq_s16(a: int16x4_t, b: uint8x16_t, n: i32) -> int16x8_t;
+    }
+    _vluti2_laneq_s16(a, b, INDEX)
+}
+#[doc = "Lookup table read with 2-bit indices"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_laneq_s16)"]
+#[doc = "## Safety"]
+#[doc = "  * Neon instrinsic unsafe"]
+#[inline]
+#[target_feature(enable = "neon,lut")]
+#[cfg_attr(test, assert_instr(nop, INDEX = 1))]
+#[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
+#[rustc_legacy_const_generics(2)]
+pub unsafe fn vluti2q_laneq_s16<const INDEX: i32>(a: int16x8_t, b: uint8x16_t) -> int16x8_t {
+    static_assert!(INDEX >= 0 && INDEX <= 7);
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            any(target_arch = "aarch64", target_arch = "arm64ec"),
+            link_name = "llvm.aarch64.neon.vluti2.laneq.v8i16.v8i16"
+        )]
+        fn _vluti2q_laneq_s16(a: int16x8_t, b: uint8x16_t, n: i32) -> int16x8_t;
+    }
+    _vluti2q_laneq_s16(a, b, INDEX)
 }
 #[doc = "Lookup table read with 4-bit indices"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_lane_f16_x2)"]
@@ -24113,6 +24514,86 @@ pub fn vrsubhn_high_u64(a: uint32x2_t, b: uint64x2_t, c: uint64x2_t) -> uint32x4
     let x: uint32x2_t = vrsubhn_u64(b, c);
     unsafe { simd_shuffle!(a, x, [0, 1, 2, 3]) }
 }
+#[doc = "Multi-vector floating-point adjust exponent"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vscale_f16)"]
+#[inline]
+#[unstable(feature = "stdarch_neon_fp8", issue = "none")]
+#[target_feature(enable = "neon,fp8")]
+#[cfg_attr(test, assert_instr(fscale))]
+pub fn vscale_f16(vn: float16x4_t, vm: int16x4_t) -> float16x4_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            any(target_arch = "aarch64", target_arch = "arm64ec"),
+            link_name = "llvm.aarch64.neon.fp8.fscale.v4f16"
+        )]
+        fn _vscale_f16(vn: float16x4_t, vm: int16x4_t) -> float16x4_t;
+    }
+    unsafe { _vscale_f16(vn, vm) }
+}
+#[doc = "Multi-vector floating-point adjust exponent"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vscaleq_f16)"]
+#[inline]
+#[unstable(feature = "stdarch_neon_fp8", issue = "none")]
+#[target_feature(enable = "neon,fp8")]
+#[cfg_attr(test, assert_instr(fscale))]
+pub fn vscaleq_f16(vn: float16x8_t, vm: int16x8_t) -> float16x8_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            any(target_arch = "aarch64", target_arch = "arm64ec"),
+            link_name = "llvm.aarch64.neon.fp8.fscale.v8f16"
+        )]
+        fn _vscaleq_f16(vn: float16x8_t, vm: int16x8_t) -> float16x8_t;
+    }
+    unsafe { _vscaleq_f16(vn, vm) }
+}
+#[doc = "Multi-vector floating-point adjust exponent"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vscale_f32)"]
+#[inline]
+#[unstable(feature = "stdarch_neon_fp8", issue = "none")]
+#[target_feature(enable = "neon,fp8")]
+#[cfg_attr(test, assert_instr(fscale))]
+pub fn vscale_f32(vn: float32x2_t, vm: int32x2_t) -> float32x2_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            any(target_arch = "aarch64", target_arch = "arm64ec"),
+            link_name = "llvm.aarch64.neon.fp8.fscale.v2f32"
+        )]
+        fn _vscale_f32(vn: float32x2_t, vm: int32x2_t) -> float32x2_t;
+    }
+    unsafe { _vscale_f32(vn, vm) }
+}
+#[doc = "Multi-vector floating-point adjust exponent"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vscaleq_f32)"]
+#[inline]
+#[unstable(feature = "stdarch_neon_fp8", issue = "none")]
+#[target_feature(enable = "neon,fp8")]
+#[cfg_attr(test, assert_instr(fscale))]
+pub fn vscaleq_f32(vn: float32x4_t, vm: int32x4_t) -> float32x4_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            any(target_arch = "aarch64", target_arch = "arm64ec"),
+            link_name = "llvm.aarch64.neon.fp8.fscale.v4f32"
+        )]
+        fn _vscaleq_f32(vn: float32x4_t, vm: int32x4_t) -> float32x4_t;
+    }
+    unsafe { _vscaleq_f32(vn, vm) }
+}
+#[doc = "Multi-vector floating-point adjust exponent"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vscaleq_f64)"]
+#[inline]
+#[unstable(feature = "stdarch_neon_fp8", issue = "none")]
+#[target_feature(enable = "neon,fp8")]
+#[cfg_attr(test, assert_instr(fscale))]
+pub fn vscaleq_f64(vn: float64x2_t, vm: int64x2_t) -> float64x2_t {
+    unsafe extern "unadjusted" {
+        #[cfg_attr(
+            any(target_arch = "aarch64", target_arch = "arm64ec"),
+            link_name = "llvm.aarch64.neon.fp8.fscale.v2f64"
+        )]
+        fn _vscaleq_f64(vn: float64x2_t, vm: int64x2_t) -> float64x2_t;
+    }
+    unsafe { _vscaleq_f64(vn, vm) }
+}
 #[doc = "Insert vector element from another vector element"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_f64)"]
 #[inline(always)]
@@ -26696,6 +27177,102 @@ pub unsafe fn vst4q_p64(a: *mut p64, b: poly64x2x4_t) {
 pub unsafe fn vst4q_u64(a: *mut u64, b: uint64x2x4_t) {
     vst4q_s64(transmute(a), transmute(b))
 }
+#[doc = "Store-Release a single-element structure from one lane of one register."]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1_lane_f64)"]
+#[inline]
+#[target_feature(enable = "neon,rcpc3")]
+#[cfg_attr(test, assert_instr(stl1, LANE = 0))]
+#[rustc_legacy_const_generics(2)]
+#[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")]
+pub fn vstl1_lane_f64<const LANE: i32>(ptr: *mut f64, val: float64x1_t) {
+    static_assert!(LANE == 0);
+    unsafe { vstl1_lane_s64::<LANE>(ptr as *mut i64, transmute(val)) }
+}
+#[doc = "Store-Release a single-element structure from one lane of one register."]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1q_lane_f64)"]
+#[inline]
+#[target_feature(enable = "neon,rcpc3")]
+#[cfg_attr(test, assert_instr(stl1, LANE = 0))]
+#[rustc_legacy_const_generics(2)]
+#[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")]
+pub fn vstl1q_lane_f64<const LANE: i32>(ptr: *mut f64, val: float64x2_t) {
+    static_assert_uimm_bits!(LANE, 1);
+    unsafe { vstl1q_lane_s64::<LANE>(ptr as *mut i64, transmute(val)) }
+}
+#[doc = "Store-Release a single-element structure from one lane of one register."]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1_lane_u64)"]
+#[inline]
+#[target_feature(enable = "neon,rcpc3")]
+#[cfg_attr(test, assert_instr(stl1, LANE = 0))]
+#[rustc_legacy_const_generics(2)]
+#[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")]
+pub fn vstl1_lane_u64<const LANE: i32>(ptr: *mut u64, val: uint64x1_t) {
+    static_assert!(LANE == 0);
+    unsafe { vstl1_lane_s64::<LANE>(ptr as *mut i64, transmute(val)) }
+}
+#[doc = "Store-Release a single-element structure from one lane of one register."]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1q_lane_u64)"]
+#[inline]
+#[target_feature(enable = "neon,rcpc3")]
+#[cfg_attr(test, assert_instr(stl1, LANE = 0))]
+#[rustc_legacy_const_generics(2)]
+#[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")]
+pub fn vstl1q_lane_u64<const LANE: i32>(ptr: *mut u64, val: uint64x2_t) {
+    static_assert_uimm_bits!(LANE, 1);
+    unsafe { vstl1q_lane_s64::<LANE>(ptr as *mut i64, transmute(val)) }
+}
+#[doc = "Store-Release a single-element structure from one lane of one register."]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1_lane_p64)"]
+#[inline]
+#[target_feature(enable = "neon,rcpc3")]
+#[cfg_attr(test, assert_instr(stl1, LANE = 0))]
+#[rustc_legacy_const_generics(2)]
+#[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")]
+pub fn vstl1_lane_p64<const LANE: i32>(ptr: *mut p64, val: poly64x1_t) {
+    static_assert!(LANE == 0);
+    unsafe { vstl1_lane_s64::<LANE>(ptr as *mut i64, transmute(val)) }
+}
+#[doc = "Store-Release a single-element structure from one lane of one register."]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1q_lane_p64)"]
+#[inline]
+#[target_feature(enable = "neon,rcpc3")]
+#[cfg_attr(test, assert_instr(stl1, LANE = 0))]
+#[rustc_legacy_const_generics(2)]
+#[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")]
+pub fn vstl1q_lane_p64<const LANE: i32>(ptr: *mut p64, val: poly64x2_t) {
+    static_assert_uimm_bits!(LANE, 1);
+    unsafe { vstl1q_lane_s64::<LANE>(ptr as *mut i64, transmute(val)) }
+}
+#[doc = "Store-Release a single-element structure from one lane of one register."]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1_lane_s64)"]
+#[inline]
+#[target_feature(enable = "neon,rcpc3")]
+#[cfg_attr(test, assert_instr(stl1, LANE = 0))]
+#[rustc_legacy_const_generics(2)]
+#[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")]
+pub fn vstl1_lane_s64<const LANE: i32>(ptr: *mut i64, val: int64x1_t) {
+    static_assert!(LANE == 0);
+    let atomic_dst = ptr as *mut crate::sync::atomic::AtomicI64;
+    unsafe {
+        let lane: i64 = simd_extract!(val, LANE as u32);
+        (*atomic_dst).store(transmute(lane), crate::sync::atomic::Ordering::Release)
+    }
+}
+#[doc = "Store-Release a single-element structure from one lane of one register."]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1q_lane_s64)"]
+#[inline]
+#[target_feature(enable = "neon,rcpc3")]
+#[cfg_attr(test, assert_instr(stl1, LANE = 0))]
+#[rustc_legacy_const_generics(2)]
+#[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")]
+pub fn vstl1q_lane_s64<const LANE: i32>(ptr: *mut i64, val: int64x2_t) {
+    static_assert_uimm_bits!(LANE, 1);
+    let atomic_dst = ptr as *mut crate::sync::atomic::AtomicI64;
+    unsafe {
+        let lane: i64 = simd_extract!(val, LANE as u32);
+        (*atomic_dst).store(transmute(lane), crate::sync::atomic::Ordering::Release)
+    }
+}
 #[doc = "Subtract"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_f64)"]
 #[inline(always)]
diff --git a/library/stdarch/crates/intrinsic-test/missing_aarch64.txt b/library/stdarch/crates/intrinsic-test/missing_aarch64.txt
index 814756cefa40..3c1ac59e910e 100644
--- a/library/stdarch/crates/intrinsic-test/missing_aarch64.txt
+++ b/library/stdarch/crates/intrinsic-test/missing_aarch64.txt
@@ -1,3 +1,43 @@
+# Not supported by qemu (will throw illegal instruction)
+vamax_f16
+vamaxq_f16
+vamin_f16
+vaminq_f16
+vscale_f16
+vscale_f32
+vscaleq_f16
+vscaleq_f32
+vscaleq_f64
+vluti2_lane_p16
+vluti2_lane_p8
+vluti2_lane_s16
+vluti2_lane_s8
+vluti2_lane_u16
+vluti2_lane_u8
+vluti2q_lane_p16
+vluti2q_lane_p8
+vluti2q_lane_s16
+vluti2q_lane_s8
+vluti2q_lane_u16
+vluti2_laneq_f16
+vluti2_lane_f16
+vluti2_laneq_f16
+vluti2_laneq_p16
+vluti2_laneq_p8
+vluti2_laneq_s16
+vluti2_laneq_s8
+vluti2_laneq_u16
+vluti2_laneq_u8
+vluti2q_lane_f16
+vluti2q_laneq_f16
+vluti2q_laneq_p16
+vluti2q_laneq_p8
+vluti2q_laneq_s16
+vluti2q_laneq_s8
+vluti2q_laneq_u16
+vluti2q_laneq_u8
+vluti2q_lane_u8
+
 # Not implemented in stdarch yet
 vbfdot_f32
 vbfdot_lane_f32
@@ -30,18 +70,6 @@ vrnd32x_f64
 vrnd32z_f64
 vrnd64x_f64
 vrnd64z_f64
-vluti2_lane_p16
-vluti2_lane_p8
-vluti2_lane_s16
-vluti2_lane_s8
-vluti2_lane_u16
-vluti2_lane_u8
-vluti2q_lane_p16
-vluti2q_lane_p8
-vluti2q_lane_s16
-vluti2q_lane_s8
-vluti2q_lane_u16
-vluti2q_lane_u8
 vluti4q_lane_f16_x2
 vluti4q_lane_p16_x2
 vluti4q_lane_p8
diff --git a/library/stdarch/crates/intrinsic-test/missing_aarch64_be.txt b/library/stdarch/crates/intrinsic-test/missing_aarch64_be.txt
index 1fa8fb7f1693..f3c4ffa3d064 100644
--- a/library/stdarch/crates/intrinsic-test/missing_aarch64_be.txt
+++ b/library/stdarch/crates/intrinsic-test/missing_aarch64_be.txt
@@ -38,6 +38,45 @@ vusdotq_lane_s32
 vusdotq_laneq_s32
 
 # Below are in common to missing_aarch64.txt
+# Not supported by qemu (will throw illegal instruction)
+vamax_f16
+vamaxq_f16
+vamin_f16
+vaminq_f16
+vscale_f16
+vscale_f32
+vscaleq_f16
+vscaleq_f32
+vscaleq_f64
+vluti2_lane_p16
+vluti2_lane_p8
+vluti2_lane_s16
+vluti2_lane_s8
+vluti2_lane_u16
+vluti2_lane_u8
+vluti2q_lane_p16
+vluti2q_lane_p8
+vluti2q_lane_s16
+vluti2q_lane_s8
+vluti2q_lane_u16
+vluti2_laneq_f16
+vluti2_lane_f16
+vluti2_laneq_f16
+vluti2_laneq_p16
+vluti2_laneq_p8
+vluti2_laneq_s16
+vluti2_laneq_s8
+vluti2_laneq_u16
+vluti2_laneq_u8
+vluti2q_lane_f16
+vluti2q_laneq_f16
+vluti2q_laneq_p16
+vluti2q_laneq_p8
+vluti2q_laneq_s16
+vluti2q_laneq_s8
+vluti2q_laneq_u16
+vluti2q_laneq_u8
+vluti2q_lane_u8
 
 # Not implemented in stdarch yet
 vbfdot_f32
@@ -71,18 +110,6 @@ vrnd32x_f64
 vrnd32z_f64
 vrnd64x_f64
 vrnd64z_f64
-vluti2_lane_p16
-vluti2_lane_p8
-vluti2_lane_s16
-vluti2_lane_s8
-vluti2_lane_u16
-vluti2_lane_u8
-vluti2q_lane_p16
-vluti2q_lane_p8
-vluti2q_lane_s16
-vluti2q_lane_s8
-vluti2q_lane_u16
-vluti2q_lane_u8
 vluti4q_lane_f16_x2
 vluti4q_lane_p16_x2
 vluti4q_lane_p8
diff --git a/library/stdarch/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml b/library/stdarch/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
index a951343e0183..10085422e8e8 100644
--- a/library/stdarch/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
+++ b/library/stdarch/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
@@ -66,6 +66,14 @@ neon-unstable-feat-lut: &neon-unstable-feat-lut
 aarch64-stable-jscvt: &aarch64-stable-jscvt
   FnCall: [stable, ['feature = "stdarch_aarch64_jscvt"', 'since = "CURRENT_RUSTC_VERSION"']]
 
+# #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")]
+neon-unstable-feat-lrcpc3: &neon-unstable-feat-lrcpc3
+  FnCall: [unstable, ['feature = "stdarch_neon_feat_lrcpc3"', 'issue = "none"']]
+
+# #[unstable(feature = "stdarch_neon_fp8", issue = "none")]
+neon-unstable-fp8: &neon-unstable-fp8
+  FnCall: [unstable, ['feature = "stdarch_neon_fp8"', 'issue = "none"']]
+
 # #[cfg(target_endian = "little")]
 little-endian: &little-endian
   FnCall: [cfg, ['target_endian = "little"']]
@@ -4398,6 +4406,116 @@ intrinsics:
                 - - FnCall: [transmute, [a]]
                   - FnCall: [transmute, [b]]
 
+  - name: "vldap1{neon_type[1].lane_nox}"
+    doc: "Load-acquire RCpc one single-element structure to one lane of one register"
+    arguments: ["ptr: {type[0]}", "src: {type[1]}"]
+    static_defs: ["const LANE: i32"]
+    return_type: "{type[1]}"
+    safety:
+      unsafe: [neon]
+    attr:
+      - FnCall: [target_feature, ['enable = "neon,rcpc3"']]
+      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [ldap1, 'LANE = 0']]}]]
+      - FnCall: [rustc_legacy_const_generics, ["2"]]
+      - *neon-unstable-feat-lrcpc3
+    types:
+      - ['*const i64', int64x1_t, 'static_assert!', 'LANE == 0']
+      - ['*const i64', int64x2_t,'static_assert_uimm_bits!', 'LANE, 1']
+    compose:
+      - FnCall: ['{type[2]}', ['{type[3]}']]
+      - Let:
+          - "atomic_src"
+          - FnCall: ["crate::sync::atomic::AtomicI64::from_ptr", ['ptr as *mut i64']]
+      - Identifier: [';', Symbol]
+      - FnCall:
+        - simd_insert!
+        - - src
+          - "LANE as u32"
+          - MethodCall:
+             - "atomic_src"
+             - load
+             - ["crate::sync::atomic::Ordering::Acquire"]
+
+  - name: "vldap1{neon_type[1].lane_nox}"
+    doc: "Load-acquire RCpc one single-element structure to one lane of one register"
+    arguments: ["ptr: {type[0]}","src: {type[1]}"]
+    static_defs: ["const LANE: i32"]
+    return_type: "{type[1]}"
+    safety:
+      unsafe: [neon]
+    attr:
+      - FnCall: [rustc_legacy_const_generics, ["2"]]
+      - FnCall: [target_feature, ['enable = "neon,rcpc3"']]
+      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [ldap1, 'LANE = 0']]}]]
+      - *neon-unstable-feat-lrcpc3
+    types:
+      - ['*const u64', uint64x1_t,'static_assert!', 'LANE == 0','']
+      #- ['*const f64', float64x1_t,'static_assert!', 'LANE == 0',''] # Fails due to bad IR gen from rust
+      - ['*const p64', poly64x1_t,'static_assert!', 'LANE == 0','']
+      - ['*const u64', uint64x2_t,'static_assert_uimm_bits!', 'LANE, 1','q']
+      - ['*const f64', float64x2_t,'static_assert_uimm_bits!', 'LANE, 1','q']
+      - ['*const p64', poly64x2_t,'static_assert_uimm_bits!', 'LANE, 1','q']
+    compose:
+      - FnCall: ['{type[2]}', ['{type[3]}']]
+      - FnCall:
+        - transmute
+        - - FnCall:
+            - 'vldap1{type[4]}_lane_s64::<LANE>'
+            - - "ptr as *mut i64"
+              - FnCall: [transmute,[src]]
+
+  - name: "vstl1{neon_type[1].lane_nox}"
+    doc: "Store-Release a single-element structure from one lane of one register."
+    arguments: ["ptr: {type[0]}", "val: {neon_type[1]}"]
+    static_defs: ["const LANE: i32"]
+    safety: safe
+    attr:
+      - FnCall: [target_feature, ['enable = "neon,rcpc3"']]
+      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [stl1, 'LANE = 0']]}]]
+      - FnCall: [rustc_legacy_const_generics, ["2"]]
+      - *neon-unstable-feat-lrcpc3
+    types:
+      - ['*mut i64', int64x1_t,'static_assert!', 'LANE == 0']
+      - ['*mut i64', int64x2_t,'static_assert_uimm_bits!', 'LANE, 1']
+    compose:
+      - FnCall: ['{type[2]}', ['{type[3]}']]
+      - Let:
+          - "atomic_dst"
+          - "ptr as *mut crate::sync::atomic::AtomicI64"
+      - Identifier: [';', Symbol]
+      - Let:
+        - "lane"
+        - i64
+        - FnCall: [simd_extract!, [val, 'LANE as u32']]
+      - MethodCall:
+        - "(*atomic_dst)"
+        - store
+        - [FnCall: [transmute, [lane]],"crate::sync::atomic::Ordering::Release"]
+
+  - name: "vstl1{neon_type[1].lane_nox}"
+    doc: "Store-Release a single-element structure from one lane of one register."
+    arguments: ["ptr: {type[0]}", "val: {neon_type[1]}"]
+    static_defs: ["const LANE: i32"]
+    safety: safe
+    attr:
+      - FnCall: [target_feature, ['enable = "neon,rcpc3"']]
+      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [stl1, 'LANE = 0']]}]]
+      - FnCall: [rustc_legacy_const_generics, ["2"]]
+      - *neon-unstable-feat-lrcpc3
+    types:
+      - ['*mut u64', uint64x1_t, 'static_assert!', 'LANE == 0','']
+      - ['*mut f64', float64x1_t,'static_assert!', 'LANE == 0','']
+      - ['*mut p64', poly64x1_t, 'static_assert!', 'LANE == 0','']
+      - ['*mut u64', uint64x2_t ,'static_assert_uimm_bits!', 'LANE, 1','q']
+      - ['*mut f64', float64x2_t,'static_assert_uimm_bits!', 'LANE, 1','q']
+      - ['*mut p64', poly64x2_t ,'static_assert_uimm_bits!', 'LANE, 1','q']
+    compose:
+      - FnCall: ['{type[2]}', ['{type[3]}']]
+      - FnCall:
+        - "vstl1{type[4]}_lane_s64::<LANE>"
+        - - "ptr as *mut i64"
+          - FnCall: [transmute, [val]]
+
   - name: "vst1{neon_type[1].lane_nox}"
     doc: "Store multiple single-element structures from one, two, three, or four registers"
     arguments: ["a: {type[0]}", "b: {neon_type[1]}"]
@@ -13966,10 +14084,12 @@ intrinsics:
     return_type: "{neon_type}"
     attr:
       - FnCall: [target_feature, ['enable = "neon,faminmax"']]
-      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [nop]]}]]
+      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [famax]]}]]
       - FnCall: [unstable, ['feature = "faminmax"', 'issue = "137933"']]
     safety: safe
     types:
+      - float16x4_t
+      - float16x8_t
       - float32x2_t
       - float32x4_t
       - float64x2_t
@@ -13986,10 +14106,12 @@ intrinsics:
     return_type: "{neon_type}"
     attr:
       - FnCall: [target_feature, ['enable = "neon,faminmax"']]
-      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [nop]]}]]
+      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [famin]]}]]
       - FnCall: [unstable, ['feature = "faminmax"', 'issue = "137933"']]
     safety: safe
     types:
+      - float16x4_t
+      - float16x8_t
       - float32x2_t
       - float32x4_t
       - float64x2_t
@@ -14030,36 +14152,101 @@ intrinsics:
               arch: aarch64,arm64ec
       - FnCall: ['_vluti2{neon_type[0].lane_nox}', [a, b, LANE]]
 
+  - name: "vluti2{neon_type[0].laneq_nox}"
+    doc: "Lookup table read with 2-bit indices"
+    arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"]
+    return_type: "{neon_type[2]}"
+    attr:
+      - FnCall: [target_feature, ['enable = {type[4]}']]
+      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [nop, 'INDEX = 1']]}]]
+      - *neon-unstable-feat-lut
+      - FnCall: [rustc_legacy_const_generics, ['2']]
+    static_defs: ["const INDEX: i32"]
+    safety:
+      unsafe: [neon]
+    types:
+      - [int8x8_t,   uint8x16_t, int8x16_t, 'INDEX >= 0 && INDEX <= 3', '"neon,lut"']
+      - [int8x16_t,  uint8x16_t, int8x16_t, 'INDEX >= 0 && INDEX <= 3', '"neon,lut"']
+      - [int16x4_t,  uint8x16_t, int16x8_t, 'INDEX >= 0 && INDEX <= 7', '"neon,lut"']
+      - [int16x8_t,  uint8x16_t, int16x8_t, 'INDEX >= 0 && INDEX <= 7', '"neon,lut"']
+    compose:
+      - FnCall: ['static_assert!', ['{type[3]}']]
+      - LLVMLink:
+          name: "vluti2{neon_type[0].laneq_nox}"
+          arguments:
+            - 'a: {neon_type[0]}'
+            - 'b: {neon_type[1]}'
+            - 'n: i32'
+          links:
+            - link: "llvm.aarch64.neon.vluti2.laneq.{neon_type[2]}.{neon_type[0]}"
+              arch: aarch64,arm64ec
+      - FnCall: ['_vluti2{neon_type[0].laneq_nox}', [a, b, INDEX]]
+
   - name: "vluti2{neon_type[0].lane_nox}"
     doc: "Lookup table read with 2-bit indices"
     arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"]
     return_type: "{neon_type[2]}"
     attr:
       - FnCall: [target_feature, ['enable = "neon,lut"']]
-      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [nop, 'LANE = 1']]}]]
+      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [nop, 'INDEX = 1']]}]]
       - *neon-unstable-feat-lut
       - FnCall: [rustc_legacy_const_generics, ['2']]
-    static_defs: ["const LANE: i32"]
+    static_defs: ["const INDEX: i32"]
     safety:
       unsafe: [neon]
     types:
-      - [uint8x8_t,  uint8x8_t, uint8x16_t, 'LANE >= 0 && LANE <= 1', 'int8x8_t']
-      - [uint8x16_t, uint8x8_t, uint8x16_t, 'LANE >= 0 && LANE <= 1', 'int8x16_t']
-      - [poly8x8_t,  uint8x8_t, poly8x16_t, 'LANE >= 0 && LANE <= 1', 'int8x8_t']
-      - [poly8x16_t, uint8x8_t, poly8x16_t, 'LANE >= 0 && LANE <= 1', 'int8x16_t']
-      - [uint16x4_t, uint8x8_t, uint16x8_t, 'LANE >= 0 && LANE <= 3', 'int16x4_t']
-      - [uint16x8_t, uint8x8_t, uint16x8_t, 'LANE >= 0 && LANE <= 3', 'int16x8_t']
-      - [poly16x4_t, uint8x8_t, poly16x8_t, 'LANE >= 0 && LANE <= 3', 'int16x4_t']
-      - [poly16x8_t, uint8x8_t, poly16x8_t, 'LANE >= 0 && LANE <= 3', 'int16x8_t']
+      - [uint8x8_t,  uint8x8_t, uint8x16_t, 'INDEX >= 0 && INDEX <= 1', 'int8x8_t']
+      - [uint8x16_t, uint8x8_t, uint8x16_t, 'INDEX >= 0 && INDEX <= 1', 'int8x16_t']
+      - [poly8x8_t,  uint8x8_t, poly8x16_t, 'INDEX >= 0 && INDEX <= 1', 'int8x8_t']
+      - [poly8x16_t, uint8x8_t, poly8x16_t, 'INDEX >= 0 && INDEX <= 1', 'int8x16_t']
+      - [uint16x4_t, uint8x8_t, uint16x8_t, 'INDEX >= 0 && INDEX <= 3', 'int16x4_t']
+      - [uint16x8_t, uint8x8_t, uint16x8_t, 'INDEX >= 0 && INDEX <= 3', 'int16x8_t']
+      - [poly16x4_t, uint8x8_t, poly16x8_t, 'INDEX >= 0 && INDEX <= 3', 'int16x4_t']
+      - [poly16x8_t, uint8x8_t, poly16x8_t, 'INDEX >= 0 && INDEX <= 3', 'int16x8_t']
+      - [float16x4_t, uint8x8_t, float16x8_t, 'INDEX >= 0 && INDEX <= 3', 'int16x4_t']
+      - [float16x8_t, uint8x8_t, float16x8_t, 'INDEX >= 0 && INDEX <= 3', 'int16x8_t']
     compose:
       - FnCall: ['static_assert!', ['{type[3]}']]
       - FnCall:
           - transmute
           - - FnCall:
-                - 'vluti2{neon_type[4].lane_nox}::<LANE>'
+                - 'vluti2{neon_type[4].lane_nox}::<INDEX>'
                 - - FnCall: [transmute, [a]]
                   - b
 
+  - name: "vluti2{neon_type[0].laneq_nox}"
+    doc: "Lookup table read with 2-bit indices"
+    arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"]
+    return_type: "{neon_type[2]}"
+    attr:
+      - FnCall: [target_feature, ['enable = "neon,lut"']]
+      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [nop, 'INDEX = 1']]}]]
+      - *neon-unstable-feat-lut
+      - FnCall: [rustc_legacy_const_generics, ['2']]
+    static_defs: ["const INDEX: i32"]
+    safety:
+      unsafe: [neon]
+    types:
+      - [uint8x8_t,  uint8x16_t, uint8x16_t, 'INDEX >= 0 && INDEX <= 3', 'int8x8_t']
+      - [uint8x16_t, uint8x16_t, uint8x16_t, 'INDEX >= 0 && INDEX <= 3', 'int8x16_t']
+      - [poly8x8_t,  uint8x16_t, poly8x16_t, 'INDEX >= 0 && INDEX <= 3', 'int8x8_t']
+      - [poly8x16_t, uint8x16_t, poly8x16_t, 'INDEX >= 0 && INDEX <= 3', 'int8x16_t']
+      - [uint16x4_t, uint8x16_t, uint16x8_t, 'INDEX >= 0 && INDEX <= 7', 'int16x4_t']
+      - [uint16x8_t, uint8x16_t, uint16x8_t, 'INDEX >= 0 && INDEX <= 7', 'int16x8_t']
+      - [poly16x4_t, uint8x16_t, poly16x8_t, 'INDEX >= 0 && INDEX <= 7', 'int16x4_t']
+      - [poly16x8_t, uint8x16_t, poly16x8_t, 'INDEX >= 0 && INDEX <= 7', 'int16x8_t']
+      - [float16x4_t, uint8x16_t, float16x8_t, 'INDEX >= 0 && INDEX <= 7', 'int16x4_t']
+      - [float16x8_t, uint8x16_t, float16x8_t, 'INDEX >= 0 && INDEX <= 7', 'int16x8_t']
+    compose:
+      - FnCall: ['static_assert!', ['{type[3]}']]
+      - FnCall:
+          - transmute
+          - - FnCall:
+                - 'vluti2{neon_type[4].laneq_nox}::<INDEX>'
+                - - FnCall: [transmute, [a]]
+                  - b
+
+
   - name: "vluti4{neon_type[0].lane_nox}"
     doc: "Lookup table read with 4-bit indices"
     arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"]
@@ -14268,6 +14455,28 @@ intrinsics:
                 - - FnCall: [transmute, [a]]
                   - b
 
+  - name: "vscale{neon_type[0].no}"
+    doc: "Multi-vector floating-point adjust exponent"
+    arguments: ["vn: {type[0]}", "vm: {type[1]}"]
+    return_type: "{type[0]}"
+    attr:
+      - *neon-unstable-fp8
+      - FnCall: [target_feature, ['enable = "neon,fp8"']]
+    assert_instr: [fscale]
+    safety: safe
+    types:
+      - [float16x4_t, int16x4_t]
+      - [float16x8_t, int16x8_t]
+      - [float32x2_t, int32x2_t]
+      - [float32x4_t, int32x4_t]
+      - [float64x2_t, int64x2_t]
+    compose:
+      - LLVMLink:
+          name: "vscale{neon_type[0].no}"
+          links:
+            - link: "llvm.aarch64.neon.fp8.fscale.{neon_type[0]}"
+              arch: aarch64,arm64ec
+
   - name: "__jcvt"
     doc: "Floating-point JavaScript convert to signed fixed-point, rounding toward zero"
     arguments: ["a: {type}"]
diff --git a/library/stdarch/intrinsics_data/arm_intrinsics.json b/library/stdarch/intrinsics_data/arm_intrinsics.json
index 19c655cd6d24..bce85d19a10f 100644
--- a/library/stdarch/intrinsics_data/arm_intrinsics.json
+++ b/library/stdarch/intrinsics_data/arm_intrinsics.json
@@ -223,6 +223,141 @@
       ]
     ]
   },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vscale_f16",
+    "arguments": [
+      "float16x4_t a",
+      "int16x4_t b"
+    ],
+    "return_type": {
+      "value": "float16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4H"
+      },
+      "b": {
+        "register": "Vm.4H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FSCALE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vscaleq_f16",
+    "arguments": [
+      "float16x8_t a",
+      "int16x8_t b"
+    ],
+    "return_type": {
+      "value": "float16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      },
+      "b": {
+        "register": "Vm.8H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FSCALE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vscale_f32",
+    "arguments": [
+      "float32x2_t a",
+      "int32x2_t b"
+    ],
+    "return_type": {
+      "value": "float32x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2S"
+      },
+      "b": {
+        "register": "Vm.2S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FSCALE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vscaleq_f32",
+    "arguments": [
+      "float32x4_t a",
+      "int32x4_t b"
+    ],
+    "return_type": {
+      "value": "float32x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4S"
+      },
+      "b": {
+        "register": "Vm.4S"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FSCALE"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vscaleq_f64",
+    "arguments": [
+      "float64x2_t a",
+      "int64x2_t b"
+    ],
+    "return_type": {
+      "value": "float64x2_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.2D"
+      },
+      "b": {
+        "register": "Vm.2D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FSCALE"
+      ]
+    ]
+  },
   {
     "SIMD_ISA": "Neon",
     "name": "vaba_s16",
@@ -34733,6 +34868,230 @@
       ]
     ]
   },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vldap1_lane_u64",
+    "arguments": [
+      "uint64_t const * ptr",
+      "uint64x1_t src",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "uint64x1_t"
+    },
+    "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 0
+      },
+      "ptr": {
+        "register": "Xn"
+      },
+      "src": {
+        "register": "Vt.1D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDAP1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vldap1_lane_s64",
+    "arguments": [
+      "int64_t const * ptr",
+      "int64x1_t src",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "int64x1_t"
+    },
+    "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 0
+      },
+      "ptr": {
+        "register": "Xn"
+      },
+      "src": {
+        "register": "Vt.1D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDAP1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vldap1q_lane_u64",
+    "arguments": [
+      "uint64_t const * ptr",
+      "uint64x2_t src",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "uint64x2_t"
+    },
+    "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "ptr": {
+        "register": "Xn"
+      },
+      "src": {
+        "register": "Vt.2D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDAP1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vldap1q_lane_s64",
+    "arguments": [
+      "int64_t const * ptr",
+      "int64x2_t src",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "int64x2_t"
+    },
+    "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "ptr": {
+        "register": "Xn"
+      },
+      "src": {
+        "register": "Vt.2D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDAP1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vldap1_lane_p64",
+    "arguments": [
+      "poly64_t const * ptr",
+      "poly64x1_t src",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "poly64x1_t"
+    },
+    "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 0
+      },
+      "ptr": {
+        "register": "Xn"
+      },
+      "src": {
+        "register": "Vt.1D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDAP1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vldap1q_lane_p64",
+    "arguments": [
+      "poly64_t const * ptr",
+      "poly64x2_t src",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "poly64x2_t"
+    },
+    "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "ptr": {
+        "register": "Xn"
+      },
+      "src": {
+        "register": "Vt.2D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDAP1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vldap1q_lane_f64",
+    "arguments": [
+      "float64_t const * ptr",
+      "float64x2_t src",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "float64x2_t"
+    },
+    "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "ptr": {
+        "register": "Xn"
+      },
+      "src": {
+        "register": "Vt.2D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LDAP1"
+      ]
+    ]
+  },
   {
     "SIMD_ISA": "Neon",
     "name": "vld1_dup_f16",
@@ -109193,6 +109552,262 @@
       ]
     ]
   },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vstl1_lane_f64",
+    "arguments": [
+      "float64_t * ptr",
+      "float64x1_t val",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 0
+      },
+      "ptr": {
+        "register": "Xn"
+      },
+      "val": {
+        "register": "Vt.1D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STL1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vstl1q_lane_f64",
+    "arguments": [
+      "float64_t * ptr",
+      "float64x2_t val",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "ptr": {
+        "register": "Xn"
+      },
+      "val": {
+        "register": "Vt.2D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STL1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vstl1_lane_p64",
+    "arguments": [
+      "poly64_t * ptr",
+      "poly64x1_t val",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 0
+      },
+      "ptr": {
+        "register": "Xn"
+      },
+      "val": {
+        "register": "Vt.1D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STL1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vstl1q_lane_p64",
+    "arguments": [
+      "poly64_t * ptr",
+      "poly64x2_t val",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "ptr": {
+        "register": "Xn"
+      },
+      "val": {
+        "register": "Vt.2D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STL1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vstl1_lane_u64",
+    "arguments": [
+      "uint64_t * ptr",
+      "uint64x1_t val",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 0
+      },
+      "ptr": {
+        "register": "Xn"
+      },
+      "val": {
+        "register": "Vt.1D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STL1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vstl1q_lane_u64",
+    "arguments": [
+      "uint64_t * ptr",
+      "uint64x2_t val",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "ptr": {
+        "register": "Xn"
+      },
+      "val": {
+        "register": "Vt.2D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STL1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vstl1_lane_s64",
+    "arguments": [
+      "int64_t * ptr",
+      "int64x1_t val",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 0
+      },
+      "ptr": {
+        "register": "Xn"
+      },
+      "val": {
+        "register": "Vt.1D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STL1"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vstl1q_lane_s64",
+    "arguments": [
+      "int64_t * ptr",
+      "int64x2_t val",
+      "const int lane"
+    ],
+    "return_type": {
+      "value": "void"
+    },
+    "Arguments_Preparation": {
+      "lane": {
+        "minimum": 0,
+        "maximum": 1
+      },
+      "ptr": {
+        "register": "Xn"
+      },
+      "val": {
+        "register": "Vt.2D"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "STL1"
+      ]
+    ]
+  },
   {
     "SIMD_ISA": "Neon",
     "name": "vsub_f16",
@@ -118682,6 +119297,60 @@
       ]
     ]
   },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vamin_f16",
+    "arguments": [
+      "float16x4_t a",
+      "float16x4_t b"
+    ],
+    "return_type": {
+      "value": "float16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4H"
+      },
+      "b": {
+        "register": "Vm.4H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FAMIN"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vaminq_f16",
+    "arguments": [
+      "float16x8_t a",
+      "float16x8_t b"
+    ],
+    "return_type": {
+      "value": "float16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      },
+      "b": {
+        "register": "Vm.8H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FAMIN"
+      ]
+    ]
+  },
   {
     "SIMD_ISA": "Neon",
     "name": "vamin_f32",
@@ -118763,6 +119432,60 @@
       ]
     ]
   },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vamax_f16",
+    "arguments": [
+      "float16x4_t a",
+      "float16x4_t b"
+    ],
+    "return_type": {
+      "value": "float16x4_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.4H"
+      },
+      "b": {
+        "register": "Vm.4H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FAMAX"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vamaxq_f16",
+    "arguments": [
+      "float16x8_t a",
+      "float16x8_t b"
+    ],
+    "return_type": {
+      "value": "float16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      },
+      "b": {
+        "register": "Vm.8H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "FAMAX"
+      ]
+    ]
+  },
   {
     "SIMD_ISA": "Neon",
     "name": "vamax_f32",
@@ -118844,6 +119567,531 @@
       ]
     ]
   },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vluti2_lane_f16",
+    "arguments": [
+      "float16x4_t a",
+      "uint8x8_t b",
+      "const int index"
+    ],
+    "return_type": {
+      "value": "float16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      },
+      "b": {
+        "register": "Vm"
+      },
+      "index": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "r": {
+        "register": "Vd.8H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LUTI2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vluti2_lane_s16",
+    "arguments": [
+      "int16x4_t a",
+      "uint8x8_t b",
+      "const int index"
+    ],
+    "return_type": {
+      "value": "int16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      },
+      "b": {
+        "register": "Vm"
+      },
+      "index": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "r": {
+        "register": "Vd.8H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LUTI2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vluti2_lane_u16",
+    "arguments": [
+      "uint16x4_t a",
+      "uint8x8_t b",
+      "const int index"
+    ],
+    "return_type": {
+      "value": "uint16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      },
+      "b": {
+        "register": "Vm"
+      },
+      "lane": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "r": {
+        "register": "Vd.8H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LUTI2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vluti2_lane_p16",
+    "arguments": [
+      "poly16x4_t a",
+      "uint8x8_t b",
+      "const int index"
+    ],
+    "return_type": {
+      "value": "poly16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      },
+      "b": {
+        "register": "Vm"
+      },
+      "index": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "r": {
+        "register": "Vd.8H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LUTI2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vluti2_laneq_f16",
+    "arguments": [
+      "float16x4_t a",
+      "uint8x16_t b",
+      "const int index"
+    ],
+    "return_type": {
+      "value": "float16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      },
+      "b": {
+        "register": "Vm"
+      },
+      "index": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "r": {
+        "register": "Vd.8H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LUTI2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vluti2_laneq_s16",
+    "arguments": [
+      "int16x4_t a",
+      "uint8x16_t b",
+      "const int index"
+    ],
+    "return_type": {
+      "value": "int16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      },
+      "b": {
+        "register": "Vm"
+      },
+      "index": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "r": {
+        "register": "Vd.8H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LUTI2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vluti2_laneq_u16",
+    "arguments": [
+      "uint16x4_t a",
+      "uint8x16_t b",
+      "const int index"
+    ],
+    "return_type": {
+      "value": "uint16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      },
+      "b": {
+        "register": "Vm"
+      },
+      "index": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "r": {
+        "register": "Vd.8H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LUTI2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vluti2_laneq_p16",
+    "arguments": [
+      "poly16x4_t a",
+      "uint8x16_t b",
+      "const int index"
+    ],
+    "return_type": {
+      "value": "poly16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      },
+      "b": {
+        "register": "Vm"
+      },
+      "index": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "r": {
+        "register": "Vd.8H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LUTI2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vluti2q_lane_f16",
+    "arguments": [
+      "float16x8_t a",
+      "uint8x8_t b",
+      "const int index"
+    ],
+    "return_type": {
+      "value": "float16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      },
+      "b": {
+        "register": "Vm"
+      },
+      "index": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "r": {
+        "register": "Vd.8H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LUTI2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vluti2q_lane_s16",
+    "arguments": [
+      "int16x8_t a",
+      "uint8x8_t b",
+      "const int index"
+    ],
+    "return_type": {
+      "value": "int16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      },
+      "b": {
+        "register": "Vm"
+      },
+      "index": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "r": {
+        "register": "Vd.8H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LUTI2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vluti2q_lane_u16",
+    "arguments": [
+      "uint16x8_t a",
+      "uint8x8_t b",
+      "const int index"
+    ],
+    "return_type": {
+      "value": "uint16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      },
+      "b": {
+        "register": "Vm"
+      },
+      "index": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "r": {
+        "register": "Vd.8H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LUTI2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vluti2q_lane_p16",
+    "arguments": [
+      "poly16x8_t a",
+      "uint8x8_t b",
+      "const int index"
+    ],
+    "return_type": {
+      "value": "poly16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      },
+      "b": {
+        "register": "Vm"
+      },
+      "index": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "r": {
+        "register": "Vd.8H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LUTI2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vluti2q_laneq_f16",
+    "arguments": [
+      "float16x8_t a",
+      "uint8x16_t b",
+      "const int index"
+    ],
+    "return_type": {
+      "value": "float16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      },
+      "b": {
+        "register": "Vm"
+      },
+      "index": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "r": {
+        "register": "Vd.8H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LUTI2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vluti2q_laneq_s16",
+    "arguments": [
+      "int16x8_t a",
+      "uint8x16_t b",
+      "const int index"
+    ],
+    "return_type": {
+      "value": "int16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      },
+      "b": {
+        "register": "Vm"
+      },
+      "index": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "r": {
+        "register": "Vd.8H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LUTI2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vluti2q_laneq_u16",
+    "arguments": [
+      "uint16x8_t a",
+      "uint8x16_t b",
+      "const int index"
+    ],
+    "return_type": {
+      "value": "uint16x8_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.8H"
+      },
+      "b": {
+        "register": "Vm"
+      },
+      "index": {
+        "minimum": 0,
+        "maximum": 7
+      },
+      "r": {
+        "register": "Vd.8H"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LUTI2"
+      ]
+    ]
+  },
   {
     "SIMD_ISA": "Neon",
     "name": "vluti2_lane_u8",
@@ -118862,7 +120110,7 @@
       "b": {
         "register": "Vm"
       },
-      "lane": {
+      "index": {
         "minimum": 0,
         "maximum": 1
       },
@@ -118897,7 +120145,7 @@
       "b": {
         "register": "Vm"
       },
-      "lane": {
+      "index": {
         "minimum": 0,
         "maximum": 1
       },
@@ -118932,7 +120180,7 @@
       "b": {
         "register": "Vm"
       },
-      "lane": {
+      "index": {
         "minimum": 0,
         "maximum": 1
       },
@@ -118967,7 +120215,7 @@
       "b": {
         "register": "Vm"
       },
-      "lane": {
+      "index": {
         "minimum": 0,
         "maximum": 1
       },
@@ -119002,7 +120250,7 @@
       "b": {
         "register": "Vm"
       },
-      "lane": {
+      "index": {
         "minimum": 0,
         "maximum": 1
       },
@@ -119037,7 +120285,7 @@
       "b": {
         "register": "Vm"
       },
-      "lane": {
+      "index": {
         "minimum": 0,
         "maximum": 1
       },
@@ -119056,28 +120304,28 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vluti2_lane_u16",
+    "name": "vluti2_laneq_u8",
     "arguments": [
-      "uint16x4_t a",
-      "uint8x8_t b",
-      "const int lane"
+      "uint8x8_t a",
+      "uint8x16_t b",
+      "const int index"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "uint8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
+        "register": "Vn.16B"
       },
       "b": {
         "register": "Vm"
       },
-      "lane": {
+      "index": {
         "minimum": 0,
         "maximum": 3
       },
       "r": {
-        "register": "Vd.8H"
+        "register": "Vd.16B"
       }
     },
     "Architectures": [
@@ -119091,28 +120339,28 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vluti2q_lane_u16",
+    "name": "vluti2q_laneq_u8",
     "arguments": [
-      "uint16x8_t a",
-      "uint8x8_t b",
-      "const int lane"
+      "uint8x16_t a",
+      "uint8x16_t b",
+      "const int index"
     ],
     "return_type": {
-      "value": "uint16x8_t"
+      "value": "uint8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
+        "register": "Vn.16B"
       },
       "b": {
         "register": "Vm"
       },
-      "lane": {
+      "index": {
         "minimum": 0,
         "maximum": 3
       },
       "r": {
-        "register": "Vd.8H"
+        "register": "Vd.16B"
       }
     },
     "Architectures": [
@@ -119126,28 +120374,28 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vluti2_lane_s16",
+    "name": "vluti2_laneq_s8",
     "arguments": [
-      "int16x4_t a",
-      "uint8x8_t b",
-      "const int lane"
+      "int8x8_t a",
+      "uint8x16_t b",
+      "const int index"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "int8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
+        "register": "Vn.16B"
       },
       "b": {
         "register": "Vm"
       },
-      "lane": {
+      "index": {
         "minimum": 0,
         "maximum": 3
       },
       "r": {
-        "register": "Vd.8H"
+        "register": "Vd.16B"
       }
     },
     "Architectures": [
@@ -119161,28 +120409,28 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vluti2q_lane_s16",
+    "name": "vluti2q_laneq_s8",
     "arguments": [
-      "int16x8_t a",
-      "uint8x8_t b",
-      "const int lane"
+      "int8x16_t a",
+      "uint8x16_t b",
+      "const int index"
     ],
     "return_type": {
-      "value": "int16x8_t"
+      "value": "int8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
+        "register": "Vn.16B"
       },
       "b": {
         "register": "Vm"
       },
-      "lane": {
+      "index": {
         "minimum": 0,
         "maximum": 3
       },
       "r": {
-        "register": "Vd.8H"
+        "register": "Vd.16B"
       }
     },
     "Architectures": [
@@ -119196,28 +120444,28 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vluti2_lane_p16",
+    "name": "vluti2_laneq_p8",
     "arguments": [
-      "poly16x4_t a",
-      "uint8x8_t b",
-      "const int lane"
+      "poly8x8_t a",
+      "uint8x16_t b",
+      "const int index"
     ],
     "return_type": {
-      "value": "poly16x8_t"
+      "value": "poly8x16_t"
     },
     "Arguments_Preparation": {
       "a": {
-        "register": "Vn.8H"
+        "register": "Vn.16B"
       },
       "b": {
         "register": "Vm"
       },
-      "lane": {
+      "index": {
         "minimum": 0,
         "maximum": 3
       },
       "r": {
-        "register": "Vd.8H"
+        "register": "Vd.16B"
       }
     },
     "Architectures": [
@@ -119231,11 +120479,46 @@
   },
   {
     "SIMD_ISA": "Neon",
-    "name": "vluti2q_lane_p16",
+    "name": "vluti2q_laneq_p8",
+    "arguments": [
+      "poly8x16_t a",
+      "uint8x16_t b",
+      "const int index"
+    ],
+    "return_type": {
+      "value": "poly8x16_t"
+    },
+    "Arguments_Preparation": {
+      "a": {
+        "register": "Vn.16B"
+      },
+      "b": {
+        "register": "Vm"
+      },
+      "index": {
+        "minimum": 0,
+        "maximum": 3
+      },
+      "r": {
+        "register": "Vd.16B"
+      }
+    },
+    "Architectures": [
+      "A64"
+    ],
+    "instructions": [
+      [
+        "LUTI2"
+      ]
+    ]
+  },
+  {
+    "SIMD_ISA": "Neon",
+    "name": "vluti2q_laneq_p16",
     "arguments": [
       "poly16x8_t a",
-      "uint8x8_t b",
-      "const int lane"
+      "uint8x16_t b",
+      "const int index"
     ],
     "return_type": {
       "value": "poly16x8_t"
@@ -119247,9 +120530,9 @@
       "b": {
         "register": "Vm"
       },
-      "lane": {
+      "index": {
         "minimum": 0,
-        "maximum": 3
+        "maximum": 7
       },
       "r": {
         "register": "Vd.8H"

From 57a42dbf5494d4375c9b8e1d52b39746656b7cd4 Mon Sep 17 00:00:00 2001
From: reucru01 <reuben.cruise@arm.com>
Date: Wed, 17 Dec 2025 09:41:31 +0000
Subject: [PATCH 79/97] Makes some A64 intrinsics available on A32

Moves the relevant defintions from the aarch64 yaml to the arm_shared.
---
 .../core_arch/src/aarch64/neon/generated.rs   | 204 +++--------
 .../src/arm_shared/neon/generated.rs          | 332 ++++++++++++++++++
 .../spec/neon/aarch64.spec.yml                | 111 ------
 .../spec/neon/arm_shared.spec.yml             | 126 +++++++
 4 files changed, 498 insertions(+), 275 deletions(-)

diff --git a/library/stdarch/crates/core_arch/src/aarch64/neon/generated.rs b/library/stdarch/crates/core_arch/src/aarch64/neon/generated.rs
index b763d64ca3bc..c4fd6a8cd9f9 100644
--- a/library/stdarch/crates/core_arch/src/aarch64/neon/generated.rs
+++ b/library/stdarch/crates/core_arch/src/aarch64/neon/generated.rs
@@ -734,7 +734,7 @@ pub fn vaddvq_u64(a: uint64x2_t) -> u64 {
 }
 #[doc = "Multi-vector floating-point absolute maximum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vamax_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,faminmax")]
 #[cfg_attr(test, assert_instr(famax))]
 #[unstable(feature = "faminmax", issue = "137933")]
@@ -750,7 +750,7 @@ pub fn vamax_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 }
 #[doc = "Multi-vector floating-point absolute maximum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vamaxq_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,faminmax")]
 #[cfg_attr(test, assert_instr(famax))]
 #[unstable(feature = "faminmax", issue = "137933")]
@@ -814,7 +814,7 @@ pub fn vamaxq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
 }
 #[doc = "Multi-vector floating-point absolute minimum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vamin_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,faminmax")]
 #[cfg_attr(test, assert_instr(famin))]
 #[unstable(feature = "faminmax", issue = "137933")]
@@ -830,7 +830,7 @@ pub fn vamin_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 }
 #[doc = "Multi-vector floating-point absolute minimum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaminq_f16)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,faminmax")]
 #[cfg_attr(test, assert_instr(famin))]
 #[unstable(feature = "faminmax", issue = "137933")]
@@ -9555,68 +9555,6 @@ pub fn vdivq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
 pub fn vdivh_f16(a: f16, b: f16) -> f16 {
     a / b
 }
-#[doc = "Dot product arithmetic (indexed)"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_laneq_s32)"]
-#[inline(always)]
-#[target_feature(enable = "neon,dotprod")]
-#[cfg_attr(test, assert_instr(sdot, LANE = 0))]
-#[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_neon_dotprod", issue = "117224")]
-pub fn vdot_laneq_s32<const LANE: i32>(a: int32x2_t, b: int8x8_t, c: int8x16_t) -> int32x2_t {
-    static_assert_uimm_bits!(LANE, 2);
-    let c: int32x4_t = vreinterpretq_s32_s8(c);
-    unsafe {
-        let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]);
-        vdot_s32(a, b, vreinterpret_s8_s32(c))
-    }
-}
-#[doc = "Dot product arithmetic (indexed)"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_laneq_s32)"]
-#[inline(always)]
-#[target_feature(enable = "neon,dotprod")]
-#[cfg_attr(test, assert_instr(sdot, LANE = 0))]
-#[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_neon_dotprod", issue = "117224")]
-pub fn vdotq_laneq_s32<const LANE: i32>(a: int32x4_t, b: int8x16_t, c: int8x16_t) -> int32x4_t {
-    static_assert_uimm_bits!(LANE, 2);
-    let c: int32x4_t = vreinterpretq_s32_s8(c);
-    unsafe {
-        let c: int32x4_t =
-            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
-        vdotq_s32(a, b, vreinterpretq_s8_s32(c))
-    }
-}
-#[doc = "Dot product arithmetic (indexed)"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_laneq_u32)"]
-#[inline(always)]
-#[target_feature(enable = "neon,dotprod")]
-#[cfg_attr(test, assert_instr(udot, LANE = 0))]
-#[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_neon_dotprod", issue = "117224")]
-pub fn vdot_laneq_u32<const LANE: i32>(a: uint32x2_t, b: uint8x8_t, c: uint8x16_t) -> uint32x2_t {
-    static_assert_uimm_bits!(LANE, 2);
-    let c: uint32x4_t = vreinterpretq_u32_u8(c);
-    unsafe {
-        let c: uint32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]);
-        vdot_u32(a, b, vreinterpret_u8_u32(c))
-    }
-}
-#[doc = "Dot product arithmetic (indexed)"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_laneq_u32)"]
-#[inline(always)]
-#[target_feature(enable = "neon,dotprod")]
-#[cfg_attr(test, assert_instr(udot, LANE = 0))]
-#[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_neon_dotprod", issue = "117224")]
-pub fn vdotq_laneq_u32<const LANE: i32>(a: uint32x4_t, b: uint8x16_t, c: uint8x16_t) -> uint32x4_t {
-    static_assert_uimm_bits!(LANE, 2);
-    let c: uint32x4_t = vreinterpretq_u32_u8(c);
-    unsafe {
-        let c: uint32x4_t =
-            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
-        vdotq_u32(a, b, vreinterpretq_u8_u32(c))
-    }
-}
 #[doc = "Set all vector lanes to the same value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_f64)"]
 #[inline(always)]
@@ -12915,7 +12853,7 @@ pub unsafe fn vld4q_u64(a: *const u64) -> uint64x2x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldap1_lane_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,rcpc3")]
 #[cfg_attr(test, assert_instr(ldap1, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -12933,7 +12871,7 @@ pub unsafe fn vldap1_lane_s64<const LANE: i32>(ptr: *const i64, src: int64x1_t)
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldap1q_lane_s64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,rcpc3")]
 #[cfg_attr(test, assert_instr(ldap1, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -12951,7 +12889,7 @@ pub unsafe fn vldap1q_lane_s64<const LANE: i32>(ptr: *const i64, src: int64x2_t)
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldap1q_lane_f64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[rustc_legacy_const_generics(2)]
 #[target_feature(enable = "neon,rcpc3")]
 #[cfg_attr(test, assert_instr(ldap1, LANE = 0))]
@@ -12964,7 +12902,7 @@ pub unsafe fn vldap1q_lane_f64<const LANE: i32>(ptr: *const f64, src: float64x2_
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldap1_lane_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[rustc_legacy_const_generics(2)]
 #[target_feature(enable = "neon,rcpc3")]
 #[cfg_attr(test, assert_instr(ldap1, LANE = 0))]
@@ -12977,7 +12915,7 @@ pub unsafe fn vldap1_lane_u64<const LANE: i32>(ptr: *const u64, src: uint64x1_t)
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldap1q_lane_u64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[rustc_legacy_const_generics(2)]
 #[target_feature(enable = "neon,rcpc3")]
 #[cfg_attr(test, assert_instr(ldap1, LANE = 0))]
@@ -12990,7 +12928,7 @@ pub unsafe fn vldap1q_lane_u64<const LANE: i32>(ptr: *const u64, src: uint64x2_t
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldap1_lane_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[rustc_legacy_const_generics(2)]
 #[target_feature(enable = "neon,rcpc3")]
 #[cfg_attr(test, assert_instr(ldap1, LANE = 0))]
@@ -13003,7 +12941,7 @@ pub unsafe fn vldap1_lane_p64<const LANE: i32>(ptr: *const p64, src: poly64x1_t)
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldap1q_lane_p64)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[rustc_legacy_const_generics(2)]
 #[target_feature(enable = "neon,rcpc3")]
 #[cfg_attr(test, assert_instr(ldap1, LANE = 0))]
@@ -13016,7 +12954,7 @@ pub unsafe fn vldap1q_lane_p64<const LANE: i32>(ptr: *const p64, src: poly64x2_t
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, INDEX = 1))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -13029,7 +12967,7 @@ pub unsafe fn vluti2_lane_f16<const INDEX: i32>(a: float16x4_t, b: uint8x8_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_f16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, INDEX = 1))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -13042,7 +12980,7 @@ pub unsafe fn vluti2q_lane_f16<const INDEX: i32>(a: float16x8_t, b: uint8x8_t) -
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, INDEX = 1))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -13055,7 +12993,7 @@ pub unsafe fn vluti2_lane_u8<const INDEX: i32>(a: uint8x8_t, b: uint8x8_t) -> ui
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_u8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, INDEX = 1))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -13068,7 +13006,7 @@ pub unsafe fn vluti2q_lane_u8<const INDEX: i32>(a: uint8x16_t, b: uint8x8_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, INDEX = 1))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -13081,7 +13019,7 @@ pub unsafe fn vluti2_lane_u16<const INDEX: i32>(a: uint16x4_t, b: uint8x8_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_u16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, INDEX = 1))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -13094,7 +13032,7 @@ pub unsafe fn vluti2q_lane_u16<const INDEX: i32>(a: uint16x8_t, b: uint8x8_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, INDEX = 1))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -13107,7 +13045,7 @@ pub unsafe fn vluti2_lane_p8<const INDEX: i32>(a: poly8x8_t, b: uint8x8_t) -> po
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_p8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, INDEX = 1))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -13120,7 +13058,7 @@ pub unsafe fn vluti2q_lane_p8<const INDEX: i32>(a: poly8x16_t, b: uint8x8_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, INDEX = 1))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -13133,7 +13071,7 @@ pub unsafe fn vluti2_lane_p16<const INDEX: i32>(a: poly16x4_t, b: uint8x8_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, INDEX = 1))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -13330,7 +13268,7 @@ pub unsafe fn vluti2q_laneq_p8<const INDEX: i32>(a: poly8x16_t, b: uint8x16_t) -
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_laneq_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, INDEX = 1))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -13343,7 +13281,7 @@ pub unsafe fn vluti2_laneq_p16<const INDEX: i32>(a: poly16x4_t, b: uint8x16_t) -
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_laneq_p16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, INDEX = 1))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -13356,7 +13294,7 @@ pub unsafe fn vluti2q_laneq_p16<const INDEX: i32>(a: poly16x8_t, b: uint8x16_t)
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_laneq_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, INDEX = 1))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -13376,7 +13314,7 @@ pub unsafe fn vluti2_laneq_s8<const INDEX: i32>(a: int8x8_t, b: uint8x16_t) -> i
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_laneq_s8)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, INDEX = 1))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -13396,7 +13334,7 @@ pub unsafe fn vluti2q_laneq_s8<const INDEX: i32>(a: int8x16_t, b: uint8x16_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_laneq_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, INDEX = 1))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -13416,7 +13354,7 @@ pub unsafe fn vluti2_laneq_s16<const INDEX: i32>(a: int16x4_t, b: uint8x16_t) ->
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_laneq_s16)"]
 #[doc = "## Safety"]
 #[doc = "  * Neon instrinsic unsafe"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, INDEX = 1))]
 #[unstable(feature = "stdarch_neon_feat_lut", issue = "138050")]
@@ -24516,7 +24454,7 @@ pub fn vrsubhn_high_u64(a: uint32x2_t, b: uint64x2_t, c: uint64x2_t) -> uint32x4
 }
 #[doc = "Multi-vector floating-point adjust exponent"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vscale_f16)"]
-#[inline]
+#[inline(always)]
 #[unstable(feature = "stdarch_neon_fp8", issue = "none")]
 #[target_feature(enable = "neon,fp8")]
 #[cfg_attr(test, assert_instr(fscale))]
@@ -24532,7 +24470,7 @@ pub fn vscale_f16(vn: float16x4_t, vm: int16x4_t) -> float16x4_t {
 }
 #[doc = "Multi-vector floating-point adjust exponent"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vscaleq_f16)"]
-#[inline]
+#[inline(always)]
 #[unstable(feature = "stdarch_neon_fp8", issue = "none")]
 #[target_feature(enable = "neon,fp8")]
 #[cfg_attr(test, assert_instr(fscale))]
@@ -24548,7 +24486,7 @@ pub fn vscaleq_f16(vn: float16x8_t, vm: int16x8_t) -> float16x8_t {
 }
 #[doc = "Multi-vector floating-point adjust exponent"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vscale_f32)"]
-#[inline]
+#[inline(always)]
 #[unstable(feature = "stdarch_neon_fp8", issue = "none")]
 #[target_feature(enable = "neon,fp8")]
 #[cfg_attr(test, assert_instr(fscale))]
@@ -24564,7 +24502,7 @@ pub fn vscale_f32(vn: float32x2_t, vm: int32x2_t) -> float32x2_t {
 }
 #[doc = "Multi-vector floating-point adjust exponent"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vscaleq_f32)"]
-#[inline]
+#[inline(always)]
 #[unstable(feature = "stdarch_neon_fp8", issue = "none")]
 #[target_feature(enable = "neon,fp8")]
 #[cfg_attr(test, assert_instr(fscale))]
@@ -24580,7 +24518,7 @@ pub fn vscaleq_f32(vn: float32x4_t, vm: int32x4_t) -> float32x4_t {
 }
 #[doc = "Multi-vector floating-point adjust exponent"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vscaleq_f64)"]
-#[inline]
+#[inline(always)]
 #[unstable(feature = "stdarch_neon_fp8", issue = "none")]
 #[target_feature(enable = "neon,fp8")]
 #[cfg_attr(test, assert_instr(fscale))]
@@ -27179,7 +27117,7 @@ pub unsafe fn vst4q_u64(a: *mut u64, b: uint64x2x4_t) {
 }
 #[doc = "Store-Release a single-element structure from one lane of one register."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1_lane_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,rcpc3")]
 #[cfg_attr(test, assert_instr(stl1, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -27190,7 +27128,7 @@ pub fn vstl1_lane_f64<const LANE: i32>(ptr: *mut f64, val: float64x1_t) {
 }
 #[doc = "Store-Release a single-element structure from one lane of one register."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1q_lane_f64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,rcpc3")]
 #[cfg_attr(test, assert_instr(stl1, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -27201,7 +27139,7 @@ pub fn vstl1q_lane_f64<const LANE: i32>(ptr: *mut f64, val: float64x2_t) {
 }
 #[doc = "Store-Release a single-element structure from one lane of one register."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1_lane_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,rcpc3")]
 #[cfg_attr(test, assert_instr(stl1, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -27212,7 +27150,7 @@ pub fn vstl1_lane_u64<const LANE: i32>(ptr: *mut u64, val: uint64x1_t) {
 }
 #[doc = "Store-Release a single-element structure from one lane of one register."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1q_lane_u64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,rcpc3")]
 #[cfg_attr(test, assert_instr(stl1, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -27223,7 +27161,7 @@ pub fn vstl1q_lane_u64<const LANE: i32>(ptr: *mut u64, val: uint64x2_t) {
 }
 #[doc = "Store-Release a single-element structure from one lane of one register."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1_lane_p64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,rcpc3")]
 #[cfg_attr(test, assert_instr(stl1, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -27234,7 +27172,7 @@ pub fn vstl1_lane_p64<const LANE: i32>(ptr: *mut p64, val: poly64x1_t) {
 }
 #[doc = "Store-Release a single-element structure from one lane of one register."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1q_lane_p64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,rcpc3")]
 #[cfg_attr(test, assert_instr(stl1, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -27245,7 +27183,7 @@ pub fn vstl1q_lane_p64<const LANE: i32>(ptr: *mut p64, val: poly64x2_t) {
 }
 #[doc = "Store-Release a single-element structure from one lane of one register."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1_lane_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,rcpc3")]
 #[cfg_attr(test, assert_instr(stl1, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -27260,7 +27198,7 @@ pub fn vstl1_lane_s64<const LANE: i32>(ptr: *mut i64, val: int64x1_t) {
 }
 #[doc = "Store-Release a single-element structure from one lane of one register."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1q_lane_s64)"]
-#[inline]
+#[inline(always)]
 #[target_feature(enable = "neon,rcpc3")]
 #[cfg_attr(test, assert_instr(stl1, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
@@ -27481,37 +27419,6 @@ pub fn vsubw_high_u32(a: uint64x2_t, b: uint32x4_t) -> uint64x2_t {
         simd_sub(a, simd_cast(c))
     }
 }
-#[doc = "Dot product index form with signed and unsigned integers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsudot_laneq_s32)"]
-#[inline(always)]
-#[target_feature(enable = "neon,i8mm")]
-#[cfg_attr(test, assert_instr(sudot, LANE = 3))]
-#[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_neon_i8mm", issue = "117223")]
-pub fn vsudot_laneq_s32<const LANE: i32>(a: int32x2_t, b: int8x8_t, c: uint8x16_t) -> int32x2_t {
-    static_assert_uimm_bits!(LANE, 2);
-    unsafe {
-        let c: uint32x4_t = transmute(c);
-        let c: uint32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]);
-        vusdot_s32(a, transmute(c), b)
-    }
-}
-#[doc = "Dot product index form with signed and unsigned integers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsudotq_laneq_s32)"]
-#[inline(always)]
-#[target_feature(enable = "neon,i8mm")]
-#[cfg_attr(test, assert_instr(sudot, LANE = 3))]
-#[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_neon_i8mm", issue = "117223")]
-pub fn vsudotq_laneq_s32<const LANE: i32>(a: int32x4_t, b: int8x16_t, c: uint8x16_t) -> int32x4_t {
-    static_assert_uimm_bits!(LANE, 2);
-    unsafe {
-        let c: uint32x4_t = transmute(c);
-        let c: uint32x4_t =
-            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
-        vusdotq_s32(a, transmute(c), b)
-    }
-}
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl1_s8)"]
 #[inline(always)]
@@ -28851,37 +28758,6 @@ pub fn vuqadds_s32(a: i32, b: u32) -> i32 {
     }
     unsafe { _vuqadds_s32(a, b) }
 }
-#[doc = "Dot product index form with unsigned and signed integers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdot_laneq_s32)"]
-#[inline(always)]
-#[target_feature(enable = "neon,i8mm")]
-#[cfg_attr(test, assert_instr(usdot, LANE = 3))]
-#[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_neon_i8mm", issue = "117223")]
-pub fn vusdot_laneq_s32<const LANE: i32>(a: int32x2_t, b: uint8x8_t, c: int8x16_t) -> int32x2_t {
-    static_assert_uimm_bits!(LANE, 2);
-    let c: int32x4_t = vreinterpretq_s32_s8(c);
-    unsafe {
-        let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]);
-        vusdot_s32(a, b, vreinterpret_s8_s32(c))
-    }
-}
-#[doc = "Dot product index form with unsigned and signed integers"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdotq_laneq_s32)"]
-#[inline(always)]
-#[target_feature(enable = "neon,i8mm")]
-#[cfg_attr(test, assert_instr(usdot, LANE = 3))]
-#[rustc_legacy_const_generics(3)]
-#[unstable(feature = "stdarch_neon_i8mm", issue = "117223")]
-pub fn vusdotq_laneq_s32<const LANE: i32>(a: int32x4_t, b: uint8x16_t, c: int8x16_t) -> int32x4_t {
-    static_assert_uimm_bits!(LANE, 2);
-    let c: int32x4_t = vreinterpretq_s32_s8(c);
-    unsafe {
-        let c: int32x4_t =
-            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
-        vusdotq_s32(a, b, vreinterpretq_s8_s32(c))
-    }
-}
 #[doc = "Unzip vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_f16)"]
 #[inline(always)]
diff --git a/library/stdarch/crates/core_arch/src/arm_shared/neon/generated.rs b/library/stdarch/crates/core_arch/src/arm_shared/neon/generated.rs
index 324ff73f62a1..ac3b649fbf2d 100644
--- a/library/stdarch/crates/core_arch/src/arm_shared/neon/generated.rs
+++ b/library/stdarch/crates/core_arch/src/arm_shared/neon/generated.rs
@@ -9816,6 +9816,200 @@ pub fn vdotq_lane_u32<const LANE: i32>(a: uint32x4_t, b: uint8x16_t, c: uint8x8_
         simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
 }
+#[doc = "Dot product arithmetic (indexed)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_laneq_s32)"]
+#[inline(always)]
+#[cfg(target_endian = "little")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon,dotprod")]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsdot, LANE = 0))]
+#[cfg_attr(
+    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    assert_instr(sdot, LANE = 0)
+)]
+#[rustc_legacy_const_generics(3)]
+#[unstable(feature = "stdarch_neon_dotprod", issue = "117224")]
+pub fn vdot_laneq_s32<const LANE: i32>(a: int32x2_t, b: int8x8_t, c: int8x16_t) -> int32x2_t {
+    static_assert_uimm_bits!(LANE, 2);
+    unsafe {
+        let c: int32x4_t = transmute(c);
+        let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]);
+        vdot_s32(a, b, transmute(c))
+    }
+}
+#[doc = "Dot product arithmetic (indexed)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_laneq_s32)"]
+#[inline(always)]
+#[cfg(target_endian = "big")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon,dotprod")]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsdot, LANE = 0))]
+#[cfg_attr(
+    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    assert_instr(sdot, LANE = 0)
+)]
+#[rustc_legacy_const_generics(3)]
+#[unstable(feature = "stdarch_neon_dotprod", issue = "117224")]
+pub fn vdot_laneq_s32<const LANE: i32>(a: int32x2_t, b: int8x8_t, c: int8x16_t) -> int32x2_t {
+    static_assert_uimm_bits!(LANE, 2);
+    let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
+    let b: int8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) };
+    let c: int8x16_t =
+        unsafe { simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
+    unsafe {
+        let c: int32x4_t = transmute(c);
+        let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]);
+        let ret_val: int32x2_t = vdot_s32(a, b, transmute(c));
+        simd_shuffle!(ret_val, ret_val, [1, 0])
+    }
+}
+#[doc = "Dot product arithmetic (indexed)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_laneq_s32)"]
+#[inline(always)]
+#[cfg(target_endian = "little")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon,dotprod")]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsdot, LANE = 0))]
+#[cfg_attr(
+    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    assert_instr(sdot, LANE = 0)
+)]
+#[rustc_legacy_const_generics(3)]
+#[unstable(feature = "stdarch_neon_dotprod", issue = "117224")]
+pub fn vdotq_laneq_s32<const LANE: i32>(a: int32x4_t, b: int8x16_t, c: int8x16_t) -> int32x4_t {
+    static_assert_uimm_bits!(LANE, 2);
+    unsafe {
+        let c: int32x4_t = transmute(c);
+        let c: int32x4_t =
+            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
+        vdotq_s32(a, b, transmute(c))
+    }
+}
+#[doc = "Dot product arithmetic (indexed)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_laneq_s32)"]
+#[inline(always)]
+#[cfg(target_endian = "big")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon,dotprod")]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsdot, LANE = 0))]
+#[cfg_attr(
+    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    assert_instr(sdot, LANE = 0)
+)]
+#[rustc_legacy_const_generics(3)]
+#[unstable(feature = "stdarch_neon_dotprod", issue = "117224")]
+pub fn vdotq_laneq_s32<const LANE: i32>(a: int32x4_t, b: int8x16_t, c: int8x16_t) -> int32x4_t {
+    static_assert_uimm_bits!(LANE, 2);
+    let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
+    let b: int8x16_t =
+        unsafe { simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
+    let c: int8x16_t =
+        unsafe { simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
+    unsafe {
+        let c: int32x4_t = transmute(c);
+        let c: int32x4_t =
+            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
+        let ret_val: int32x4_t = vdotq_s32(a, b, transmute(c));
+        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
+    }
+}
+#[doc = "Dot product arithmetic (indexed)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_laneq_u32)"]
+#[inline(always)]
+#[cfg(target_endian = "little")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon,dotprod")]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vudot, LANE = 0))]
+#[cfg_attr(
+    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    assert_instr(udot, LANE = 0)
+)]
+#[rustc_legacy_const_generics(3)]
+#[unstable(feature = "stdarch_neon_dotprod", issue = "117224")]
+pub fn vdot_laneq_u32<const LANE: i32>(a: uint32x2_t, b: uint8x8_t, c: uint8x16_t) -> uint32x2_t {
+    static_assert_uimm_bits!(LANE, 2);
+    unsafe {
+        let c: uint32x4_t = transmute(c);
+        let c: uint32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]);
+        vdot_u32(a, b, transmute(c))
+    }
+}
+#[doc = "Dot product arithmetic (indexed)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_laneq_u32)"]
+#[inline(always)]
+#[cfg(target_endian = "big")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon,dotprod")]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vudot, LANE = 0))]
+#[cfg_attr(
+    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    assert_instr(udot, LANE = 0)
+)]
+#[rustc_legacy_const_generics(3)]
+#[unstable(feature = "stdarch_neon_dotprod", issue = "117224")]
+pub fn vdot_laneq_u32<const LANE: i32>(a: uint32x2_t, b: uint8x8_t, c: uint8x16_t) -> uint32x2_t {
+    static_assert_uimm_bits!(LANE, 2);
+    let a: uint32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
+    let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) };
+    let c: uint8x16_t =
+        unsafe { simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
+    unsafe {
+        let c: uint32x4_t = transmute(c);
+        let c: uint32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]);
+        let ret_val: uint32x2_t = vdot_u32(a, b, transmute(c));
+        simd_shuffle!(ret_val, ret_val, [1, 0])
+    }
+}
+#[doc = "Dot product arithmetic (indexed)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_laneq_u32)"]
+#[inline(always)]
+#[cfg(target_endian = "little")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon,dotprod")]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vudot, LANE = 0))]
+#[cfg_attr(
+    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    assert_instr(udot, LANE = 0)
+)]
+#[rustc_legacy_const_generics(3)]
+#[unstable(feature = "stdarch_neon_dotprod", issue = "117224")]
+pub fn vdotq_laneq_u32<const LANE: i32>(a: uint32x4_t, b: uint8x16_t, c: uint8x16_t) -> uint32x4_t {
+    static_assert_uimm_bits!(LANE, 2);
+    unsafe {
+        let c: uint32x4_t = transmute(c);
+        let c: uint32x4_t =
+            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
+        vdotq_u32(a, b, transmute(c))
+    }
+}
+#[doc = "Dot product arithmetic (indexed)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_laneq_u32)"]
+#[inline(always)]
+#[cfg(target_endian = "big")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon,dotprod")]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vudot, LANE = 0))]
+#[cfg_attr(
+    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    assert_instr(udot, LANE = 0)
+)]
+#[rustc_legacy_const_generics(3)]
+#[unstable(feature = "stdarch_neon_dotprod", issue = "117224")]
+pub fn vdotq_laneq_u32<const LANE: i32>(a: uint32x4_t, b: uint8x16_t, c: uint8x16_t) -> uint32x4_t {
+    static_assert_uimm_bits!(LANE, 2);
+    let a: uint32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
+    let b: uint8x16_t =
+        unsafe { simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
+    let c: uint8x16_t =
+        unsafe { simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
+    unsafe {
+        let c: uint32x4_t = transmute(c);
+        let c: uint32x4_t =
+            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
+        let ret_val: uint32x4_t = vdotq_u32(a, b, transmute(c));
+        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
+    }
+}
 #[doc = "Dot product arithmetic (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_s32)"]
 #[inline(always)]
@@ -73395,6 +73589,47 @@ pub fn vsudotq_lane_s32<const LANE: i32>(a: int32x4_t, b: int8x16_t, c: uint8x8_
         simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
 }
+#[doc = "Dot product index form with signed and unsigned integers"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsudot_laneq_s32)"]
+#[inline(always)]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon,i8mm")]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsudot, LANE = 1))]
+#[cfg_attr(
+    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    assert_instr(sudot, LANE = 3)
+)]
+#[rustc_legacy_const_generics(3)]
+#[unstable(feature = "stdarch_neon_i8mm", issue = "117223")]
+pub fn vsudot_laneq_s32<const LANE: i32>(a: int32x2_t, b: int8x8_t, c: uint8x16_t) -> int32x2_t {
+    static_assert_uimm_bits!(LANE, 2);
+    unsafe {
+        let c: uint32x4_t = transmute(c);
+        let c: uint32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]);
+        vusdot_s32(a, transmute(c), b)
+    }
+}
+#[doc = "Dot product index form with signed and unsigned integers"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsudotq_laneq_s32)"]
+#[inline(always)]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon,i8mm")]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsudot, LANE = 1))]
+#[cfg_attr(
+    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    assert_instr(sudot, LANE = 3)
+)]
+#[rustc_legacy_const_generics(3)]
+#[unstable(feature = "stdarch_neon_i8mm", issue = "117223")]
+pub fn vsudotq_laneq_s32<const LANE: i32>(a: int32x4_t, b: int8x16_t, c: uint8x16_t) -> int32x4_t {
+    static_assert_uimm_bits!(LANE, 2);
+    unsafe {
+        let c: uint32x4_t = transmute(c);
+        let c: uint32x4_t =
+            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
+        vusdotq_s32(a, transmute(c), b)
+    }
+}
 #[doc = "Table look-up"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtbl1)"]
 #[inline(always)]
@@ -75397,6 +75632,103 @@ pub fn vusdotq_lane_s32<const LANE: i32>(a: int32x4_t, b: uint8x16_t, c: int8x8_
         simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
     }
 }
+#[doc = "Dot product index form with unsigned and signed integers"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdot_laneq_s32)"]
+#[inline(always)]
+#[cfg(target_endian = "little")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon,i8mm")]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vusdot, LANE = 3))]
+#[cfg_attr(
+    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    assert_instr(usdot, LANE = 3)
+)]
+#[rustc_legacy_const_generics(3)]
+#[unstable(feature = "stdarch_neon_i8mm", issue = "117223")]
+pub fn vusdot_laneq_s32<const LANE: i32>(a: int32x2_t, b: uint8x8_t, c: int8x16_t) -> int32x2_t {
+    static_assert_uimm_bits!(LANE, 2);
+    unsafe {
+        let c: int32x4_t = transmute(c);
+        let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]);
+        vusdot_s32(a, b, transmute(c))
+    }
+}
+#[doc = "Dot product index form with unsigned and signed integers"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdot_laneq_s32)"]
+#[inline(always)]
+#[cfg(target_endian = "big")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon,i8mm")]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vusdot, LANE = 3))]
+#[cfg_attr(
+    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    assert_instr(usdot, LANE = 3)
+)]
+#[rustc_legacy_const_generics(3)]
+#[unstable(feature = "stdarch_neon_i8mm", issue = "117223")]
+pub fn vusdot_laneq_s32<const LANE: i32>(a: int32x2_t, b: uint8x8_t, c: int8x16_t) -> int32x2_t {
+    static_assert_uimm_bits!(LANE, 2);
+    let a: int32x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
+    let b: uint8x8_t = unsafe { simd_shuffle!(b, b, [7, 6, 5, 4, 3, 2, 1, 0]) };
+    let c: int8x16_t =
+        unsafe { simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
+    unsafe {
+        let c: int32x4_t = transmute(c);
+        let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]);
+        let ret_val: int32x2_t = vusdot_s32(a, b, transmute(c));
+        simd_shuffle!(ret_val, ret_val, [1, 0])
+    }
+}
+#[doc = "Dot product index form with unsigned and signed integers"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdotq_laneq_s32)"]
+#[inline(always)]
+#[cfg(target_endian = "little")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon,i8mm")]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vusdot, LANE = 3))]
+#[cfg_attr(
+    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    assert_instr(usdot, LANE = 3)
+)]
+#[rustc_legacy_const_generics(3)]
+#[unstable(feature = "stdarch_neon_i8mm", issue = "117223")]
+pub fn vusdotq_laneq_s32<const LANE: i32>(a: int32x4_t, b: uint8x16_t, c: int8x16_t) -> int32x4_t {
+    static_assert_uimm_bits!(LANE, 2);
+    unsafe {
+        let c: int32x4_t = transmute(c);
+        let c: int32x4_t =
+            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
+        vusdotq_s32(a, b, transmute(c))
+    }
+}
+#[doc = "Dot product index form with unsigned and signed integers"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdotq_laneq_s32)"]
+#[inline(always)]
+#[cfg(target_endian = "big")]
+#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
+#[target_feature(enable = "neon,i8mm")]
+#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vusdot, LANE = 3))]
+#[cfg_attr(
+    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    assert_instr(usdot, LANE = 3)
+)]
+#[rustc_legacy_const_generics(3)]
+#[unstable(feature = "stdarch_neon_i8mm", issue = "117223")]
+pub fn vusdotq_laneq_s32<const LANE: i32>(a: int32x4_t, b: uint8x16_t, c: int8x16_t) -> int32x4_t {
+    static_assert_uimm_bits!(LANE, 2);
+    let a: int32x4_t = unsafe { simd_shuffle!(a, a, [3, 2, 1, 0]) };
+    let b: uint8x16_t =
+        unsafe { simd_shuffle!(b, b, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
+    let c: int8x16_t =
+        unsafe { simd_shuffle!(c, c, [15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0]) };
+    unsafe {
+        let c: int32x4_t = transmute(c);
+        let c: int32x4_t =
+            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]);
+        let ret_val: int32x4_t = vusdotq_s32(a, b, transmute(c));
+        simd_shuffle!(ret_val, ret_val, [3, 2, 1, 0])
+    }
+}
 #[doc = "Dot product vector form with unsigned and signed integers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdot_s32)"]
 #[inline(always)]
diff --git a/library/stdarch/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml b/library/stdarch/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
index 10085422e8e8..ec5bc8c954d7 100644
--- a/library/stdarch/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
+++ b/library/stdarch/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
@@ -5199,56 +5199,6 @@ intrinsics:
               arch: aarch64,arm64ec
       - FnCall: ['_vst4{neon_type[1].lane_nox}', ['b.0', 'b.1', 'b.2', 'b.3', 'LANE as i64', 'a as _']]
 
-  - name: "vusdot{neon_type[0].laneq_nox}"
-    doc: "Dot product index form with unsigned and signed integers"
-    arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[2]}"]
-    return_type: "{neon_type[0]}"
-    attr:
-      - *neon-i8mm
-      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [usdot, 'LANE = 3']]}]]
-      - FnCall: [rustc_legacy_const_generics, ['3']]
-      - FnCall: [unstable, ['feature = "stdarch_neon_i8mm"', 'issue = "117223"']]
-    static_defs: ["const LANE: i32"]
-    safety: safe
-    types:
-      - [int32x2_t, uint8x8_t, int8x16_t, '[LANE as u32, LANE as u32]','']
-      - [int32x4_t, uint8x16_t, int8x16_t, '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]','q']
-    compose:
-      - FnCall: [static_assert_uimm_bits!, [LANE, '2']]
-      - Let: [c, int32x4_t, {FnCall: ['vreinterpretq_s32_s8', [c]]}]
-      - Let: [c, "{neon_type[0]}", {FnCall: [simd_shuffle!, [c, c, "{type[3]}"]]}]
-      - FnCall: ["vusdot{neon_type[0].no}", [a, b, {FnCall: ['vreinterpret{type[4]}_s8_s32', [c]]}]]
-
-  - name: "vsudot{neon_type[0].laneq_nox}"
-    doc: "Dot product index form with signed and unsigned integers"
-    arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[2]}"]
-    return_type: "{neon_type[0]}"
-    attr:
-      - *neon-i8mm
-      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sudot, 'LANE = 3']]}]]
-      - FnCall: [rustc_legacy_const_generics, ['3']]
-      - FnCall: [unstable, ['feature = "stdarch_neon_i8mm"', 'issue = "117223"']]
-    static_defs: ["const LANE: i32"]
-    safety: safe
-    types:
-      - [int32x2_t, int8x8_t, uint8x16_t, '[LANE as u32, LANE as u32]', uint32x2_t]
-      - [int32x4_t, int8x16_t, uint8x16_t, '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]', uint32x4_t]
-    compose:
-      - FnCall: [static_assert_uimm_bits!, [LANE, 2]]
-      - Let:
-          - c
-          - uint32x4_t
-          - FnCall: [transmute, [c]]
-      - Let:
-          - c
-          - "{type[4]}"
-          - FnCall: [simd_shuffle!, [c, c, "{type[3]}"]]
-      - FnCall: 
-          - "vusdot{neon_type[0].no}"
-          - - a
-            - FnCall: [transmute, [c]]
-            - b
-
   - name: "vmul{neon_type.no}"
     doc: Multiply
     arguments: ["a: {neon_type}", "b: {neon_type}"]
@@ -6670,7 +6620,6 @@ intrinsics:
       - Let: [c, "{neon_type[0]}", {FnCall: [simd_shuffle!, [c, c, "{type[2]}"]]}]
       - FnCall: ["vcmla{neon_type[0].rot270}", [a, b, c]]
 
-
   - name: "vcmla{neon_type[0].rot270_lane}"
     doc: Floating-point complex multiply accumulate
     arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}", "c: {neon_type[1]}"]
@@ -6692,66 +6641,6 @@ intrinsics:
       - Let: [c, "{neon_type[0]}", {FnCall: [simd_shuffle!, [c, c, "{type[2]}"]]}]
       - FnCall: ["vcmla{neon_type[0].rot270}", [a, b, c]]
 
-  - name: "vdot{neon_type[0].laneq_nox}"
-    doc: Dot product arithmetic (indexed)
-    arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[2]}"]
-    return_type: "{neon_type[0]}"
-    static_defs: ["const LANE: i32"]
-    attr:
-      - FnCall: [target_feature, ['enable = "neon,dotprod"']]
-      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sdot, 'LANE = 0']]}]]
-      - FnCall: [rustc_legacy_const_generics, ['3']]
-      - FnCall: [unstable, ['feature = "stdarch_neon_dotprod"', 'issue = "117224"']]
-    safety: safe
-    types:
-      - [int32x2_t, int8x8_t, int8x16_t, int32x4_t, '[LANE as u32, LANE as u32]', '']
-      - [int32x4_t, int8x16_t, int8x16_t, int32x4_t, '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]','q']
-    compose:
-      - FnCall: [static_assert_uimm_bits!, [LANE, '2']]
-      - Let:
-          - c
-          - "{neon_type[3]}"
-          - FnCall: ['vreinterpretq_{neon_type[0]}_{neon_type[1]}', [c]]
-      - Let:
-          - c
-          - "{neon_type[0]}"
-          - FnCall: [simd_shuffle!, [c, c, '{type[4]}']]
-      - FnCall:
-          - "vdot{neon_type[0].no}"
-          - - a
-            - b
-            - FnCall: ['vreinterpret{type[5]}_{neon_type[1]}_{neon_type[0]}', [c]]
-
-  - name: "vdot{neon_type[0].laneq_nox}"
-    doc: Dot product arithmetic (indexed)
-    arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[2]}"]
-    return_type: "{neon_type[0]}"
-    static_defs: ["const LANE: i32"]
-    attr:
-      - FnCall: [target_feature, ['enable = "neon,dotprod"']]
-      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [udot, 'LANE = 0']]}]]
-      - FnCall: [rustc_legacy_const_generics, ['3']]
-      - FnCall: [unstable, ['feature = "stdarch_neon_dotprod"', 'issue = "117224"']]
-    safety: safe
-    types:
-      - [uint32x2_t, uint8x8_t, uint8x16_t, uint32x4_t, '[LANE as u32, LANE as u32]','']
-      - [uint32x4_t, uint8x16_t, uint8x16_t, uint32x4_t, '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]','q']
-    compose:
-      - FnCall: [static_assert_uimm_bits!, [LANE, '2']]
-      - Let:
-          - c
-          - "{neon_type[3]}"
-          - FnCall: ['vreinterpretq_{neon_type[0]}_{neon_type[1]}', [c]]
-      - Let:
-          - c
-          - "{neon_type[0]}"
-          - FnCall: [simd_shuffle!, [c, c, '{type[4]}']]
-      - FnCall:
-          - "vdot{neon_type[0].no}"
-          - - a
-            - b
-            - FnCall: ['vreinterpret{type[5]}_{neon_type[1]}_{neon_type[0]}', [c]]
-
   - name: "vmax{neon_type.no}"
     doc: Maximum (vector)
     arguments: ["a: {neon_type}", "b: {neon_type}"]
diff --git a/library/stdarch/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml b/library/stdarch/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
index c7a333d7f75e..2bd1bf2a53fa 100644
--- a/library/stdarch/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
+++ b/library/stdarch/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
@@ -7096,6 +7096,132 @@ intrinsics:
           - FnCall: [simd_cast, [b]]
       - FnCall: [simd_sub, [c, d]]
 
+  - name: "vusdot{neon_type[0].laneq_nox}"
+    doc: "Dot product index form with unsigned and signed integers"
+    arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[2]}"]
+    return_type: "{neon_type[0]}"
+    big_endian_inverse: true # TODO: Remove this attribute, and replace transmute with vreinterpret when https://github.com/llvm/llvm-project/pull/169337 is merged, LLVM inlining issue causing assertion failure.
+    attr:
+      - *neon-v8
+      - *neon-i8mm
+      - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vusdot, 'LANE = 3']]}]]
+      - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [usdot, 'LANE = 3']]}]]
+      - FnCall: [rustc_legacy_const_generics, ['3']]
+      - FnCall: [unstable, ['feature = "stdarch_neon_i8mm"', 'issue = "117223"']]
+    static_defs: ["const LANE: i32"]
+    safety: safe
+    types:
+      - [int32x2_t, uint8x8_t, int8x16_t, '[LANE as u32, LANE as u32]','']
+      - [int32x4_t, uint8x16_t, int8x16_t, '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]','q']
+    compose:
+      - FnCall: [static_assert_uimm_bits!, [LANE, '2']]
+      - Let: [c, int32x4_t, {FnCall: [transmute, [c]]}]
+      - Let: [c, "{neon_type[0]}", {FnCall: [simd_shuffle!, [c, c, "{type[3]}"]]}]
+      - FnCall: ["vusdot{neon_type[0].no}", [a, b, {FnCall: [transmute, [c]]}]]
+      #- FnCall: ["vusdot{neon_type[0].no}", [a, b, {FnCall: ['vreinterpret{type[4]}_s8_s32', [c]]}]] 
+
+  - name: "vsudot{neon_type[0].laneq_nox}"
+    doc: "Dot product index form with signed and unsigned integers"
+    arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[2]}"]
+    return_type: "{neon_type[0]}"
+    attr:
+      - *neon-v8
+      - *neon-i8mm
+      - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vsudot, 'LANE = 1']]}]]
+      - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [sudot, 'LANE = 3']]}]]
+      - FnCall: [rustc_legacy_const_generics, ['3']]
+      - FnCall: [unstable, ['feature = "stdarch_neon_i8mm"', 'issue = "117223"']]
+    static_defs: ["const LANE: i32"]
+    safety: safe
+    types:
+      - [int32x2_t, int8x8_t, uint8x16_t, '[LANE as u32, LANE as u32]', uint32x2_t]
+      - [int32x4_t, int8x16_t, uint8x16_t, '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]', uint32x4_t]
+    compose:
+      - FnCall: [static_assert_uimm_bits!, [LANE, 2]]
+      - Let:
+          - c
+          - uint32x4_t
+          - FnCall: [transmute, [c]]
+      - Let:
+          - c
+          - "{type[4]}"
+          - FnCall: [simd_shuffle!, [c, c, "{type[3]}"]]
+      - FnCall: 
+          - "vusdot{neon_type[0].no}"
+          - - a
+            - FnCall: [transmute, [c]]
+            - b
+
+  - name: "vdot{neon_type[0].laneq_nox}"
+    doc: Dot product arithmetic (indexed)
+    arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[2]}"]
+    return_type: "{neon_type[0]}"
+    static_defs: ["const LANE: i32"]
+    big_endian_inverse: true # TODO: Remove this attribute, and replace transmute with vreinterpret when https://github.com/llvm/llvm-project/pull/169337 is merged, LLVM inlining issue causing assertion failure.
+    attr:
+      - *neon-v8
+      - FnCall: [target_feature, ['enable = "neon,dotprod"']]
+      - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vsdot, 'LANE = 0']]}]]
+      - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [sdot, 'LANE = 0']]}]]
+      - FnCall: [rustc_legacy_const_generics, ['3']]
+      - FnCall: [unstable, ['feature = "stdarch_neon_dotprod"', 'issue = "117224"']]
+    safety: safe
+    types:
+      - [int32x2_t, int8x8_t, int8x16_t, int32x4_t, '[LANE as u32, LANE as u32]', '']
+      - [int32x4_t, int8x16_t, int8x16_t, int32x4_t, '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]','q']
+    compose:
+      - FnCall: [static_assert_uimm_bits!, [LANE, '2']]
+      - Let:
+          - c
+          - "{neon_type[3]}"
+          - FnCall: [transmute, [c]]
+          #- FnCall: ['vreinterpretq_{neon_type[0]}_{neon_type[1]}', [c]]
+      - Let:
+          - c
+          - "{neon_type[0]}"
+          - FnCall: [simd_shuffle!, [c, c, '{type[4]}']]
+      - FnCall:
+          - "vdot{neon_type[0].no}"
+          - - a
+            - b
+            - FnCall: [transmute, [c]]
+            #- FnCall: ['vreinterpret{type[5]}_{neon_type[1]}_{neon_type[0]}', [c]]
+
+  - name: "vdot{neon_type[0].laneq_nox}"
+    doc: Dot product arithmetic (indexed)
+    arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[2]}"]
+    return_type: "{neon_type[0]}"
+    static_defs: ["const LANE: i32"]
+    big_endian_inverse: true # TODO: Remove this attribute, and replace transmute with vreinterpret when https://github.com/llvm/llvm-project/pull/169337 is merged, LLVM inlining issue causing assertion failure.
+    attr:
+      - *neon-v8
+      - FnCall: [target_feature, ['enable = "neon,dotprod"']]
+      - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vudot, 'LANE = 0']]}]]
+      - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [udot, 'LANE = 0']]}]]
+      - FnCall: [rustc_legacy_const_generics, ['3']]
+      - FnCall: [unstable, ['feature = "stdarch_neon_dotprod"', 'issue = "117224"']]
+    safety: safe
+    types:
+      - [uint32x2_t, uint8x8_t, uint8x16_t, uint32x4_t, '[LANE as u32, LANE as u32]','']
+      - [uint32x4_t, uint8x16_t, uint8x16_t, uint32x4_t, '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]','q']
+    compose:
+      - FnCall: [static_assert_uimm_bits!, [LANE, '2']]
+      - Let:
+          - c
+          - "{neon_type[3]}"
+          - FnCall: [transmute, [c]]
+          #- FnCall: ['vreinterpretq_{neon_type[0]}_{neon_type[1]}', [c]]
+      - Let:
+          - c
+          - "{neon_type[0]}"
+          - FnCall: [simd_shuffle!, [c, c, '{type[4]}']]
+      - FnCall:
+          - "vdot{neon_type[0].no}"
+          - - a
+            - b
+            - FnCall: [transmute, [c]]
+            #- FnCall: ['vreinterpret{type[5]}_{neon_type[1]}_{neon_type[0]}', [c]]
+
   - name: "vdot{neon_type[0].no}"
     doc: Dot product arithmetic (vector)
     arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[1]}"]

From 9ce0ebf994e601ebed0c74e39ea6457a44d111ef Mon Sep 17 00:00:00 2001
From: reucru01 <reuben.cruise@arm.com>
Date: Wed, 14 Jan 2026 13:29:20 +0000
Subject: [PATCH 80/97] Disables `assert_instr` tests on windows msvc

The opcodes for these intructions are not recognised by the dissasembler on the windows msvc toolchain.
As such they are not translated to the relevant mneumonic and the `assert_instr` test fails.
Please see [failing test](https://github.com/rust-lang/stdarch/actions/runs/20992978794/job/60342796821?pr=1994#logs).
---
 .../core_arch/src/aarch64/neon/generated.rs   | 60 +++++++++----------
 .../spec/neon/aarch64.spec.yml                | 14 ++---
 2 files changed, 37 insertions(+), 37 deletions(-)

diff --git a/library/stdarch/crates/core_arch/src/aarch64/neon/generated.rs b/library/stdarch/crates/core_arch/src/aarch64/neon/generated.rs
index c4fd6a8cd9f9..68676ebd2c86 100644
--- a/library/stdarch/crates/core_arch/src/aarch64/neon/generated.rs
+++ b/library/stdarch/crates/core_arch/src/aarch64/neon/generated.rs
@@ -736,7 +736,7 @@ pub fn vaddvq_u64(a: uint64x2_t) -> u64 {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vamax_f16)"]
 #[inline(always)]
 #[target_feature(enable = "neon,faminmax")]
-#[cfg_attr(test, assert_instr(famax))]
+#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(famax))]
 #[unstable(feature = "faminmax", issue = "137933")]
 pub fn vamax_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
     unsafe extern "unadjusted" {
@@ -752,7 +752,7 @@ pub fn vamax_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vamaxq_f16)"]
 #[inline(always)]
 #[target_feature(enable = "neon,faminmax")]
-#[cfg_attr(test, assert_instr(famax))]
+#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(famax))]
 #[unstable(feature = "faminmax", issue = "137933")]
 pub fn vamaxq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
     unsafe extern "unadjusted" {
@@ -768,7 +768,7 @@ pub fn vamaxq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vamax_f32)"]
 #[inline(always)]
 #[target_feature(enable = "neon,faminmax")]
-#[cfg_attr(test, assert_instr(famax))]
+#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(famax))]
 #[unstable(feature = "faminmax", issue = "137933")]
 pub fn vamax_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
     unsafe extern "unadjusted" {
@@ -784,7 +784,7 @@ pub fn vamax_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vamaxq_f32)"]
 #[inline(always)]
 #[target_feature(enable = "neon,faminmax")]
-#[cfg_attr(test, assert_instr(famax))]
+#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(famax))]
 #[unstable(feature = "faminmax", issue = "137933")]
 pub fn vamaxq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
     unsafe extern "unadjusted" {
@@ -800,7 +800,7 @@ pub fn vamaxq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vamaxq_f64)"]
 #[inline(always)]
 #[target_feature(enable = "neon,faminmax")]
-#[cfg_attr(test, assert_instr(famax))]
+#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(famax))]
 #[unstable(feature = "faminmax", issue = "137933")]
 pub fn vamaxq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
     unsafe extern "unadjusted" {
@@ -816,7 +816,7 @@ pub fn vamaxq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vamin_f16)"]
 #[inline(always)]
 #[target_feature(enable = "neon,faminmax")]
-#[cfg_attr(test, assert_instr(famin))]
+#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(famin))]
 #[unstable(feature = "faminmax", issue = "137933")]
 pub fn vamin_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
     unsafe extern "unadjusted" {
@@ -832,7 +832,7 @@ pub fn vamin_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaminq_f16)"]
 #[inline(always)]
 #[target_feature(enable = "neon,faminmax")]
-#[cfg_attr(test, assert_instr(famin))]
+#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(famin))]
 #[unstable(feature = "faminmax", issue = "137933")]
 pub fn vaminq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
     unsafe extern "unadjusted" {
@@ -848,7 +848,7 @@ pub fn vaminq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vamin_f32)"]
 #[inline(always)]
 #[target_feature(enable = "neon,faminmax")]
-#[cfg_attr(test, assert_instr(famin))]
+#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(famin))]
 #[unstable(feature = "faminmax", issue = "137933")]
 pub fn vamin_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
     unsafe extern "unadjusted" {
@@ -864,7 +864,7 @@ pub fn vamin_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaminq_f32)"]
 #[inline(always)]
 #[target_feature(enable = "neon,faminmax")]
-#[cfg_attr(test, assert_instr(famin))]
+#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(famin))]
 #[unstable(feature = "faminmax", issue = "137933")]
 pub fn vaminq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
     unsafe extern "unadjusted" {
@@ -880,7 +880,7 @@ pub fn vaminq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaminq_f64)"]
 #[inline(always)]
 #[target_feature(enable = "neon,faminmax")]
-#[cfg_attr(test, assert_instr(famin))]
+#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(famin))]
 #[unstable(feature = "faminmax", issue = "137933")]
 pub fn vaminq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
     unsafe extern "unadjusted" {
@@ -12855,7 +12855,7 @@ pub unsafe fn vld4q_u64(a: *const u64) -> uint64x2x4_t {
 #[doc = "  * Neon instrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,rcpc3")]
-#[cfg_attr(test, assert_instr(ldap1, LANE = 0))]
+#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(ldap1, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")]
 pub unsafe fn vldap1_lane_s64<const LANE: i32>(ptr: *const i64, src: int64x1_t) -> int64x1_t {
@@ -12873,7 +12873,7 @@ pub unsafe fn vldap1_lane_s64<const LANE: i32>(ptr: *const i64, src: int64x1_t)
 #[doc = "  * Neon instrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,rcpc3")]
-#[cfg_attr(test, assert_instr(ldap1, LANE = 0))]
+#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(ldap1, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")]
 pub unsafe fn vldap1q_lane_s64<const LANE: i32>(ptr: *const i64, src: int64x2_t) -> int64x2_t {
@@ -12892,7 +12892,7 @@ pub unsafe fn vldap1q_lane_s64<const LANE: i32>(ptr: *const i64, src: int64x2_t)
 #[inline(always)]
 #[rustc_legacy_const_generics(2)]
 #[target_feature(enable = "neon,rcpc3")]
-#[cfg_attr(test, assert_instr(ldap1, LANE = 0))]
+#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(ldap1, LANE = 0))]
 #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")]
 pub unsafe fn vldap1q_lane_f64<const LANE: i32>(ptr: *const f64, src: float64x2_t) -> float64x2_t {
     static_assert_uimm_bits!(LANE, 1);
@@ -12905,7 +12905,7 @@ pub unsafe fn vldap1q_lane_f64<const LANE: i32>(ptr: *const f64, src: float64x2_
 #[inline(always)]
 #[rustc_legacy_const_generics(2)]
 #[target_feature(enable = "neon,rcpc3")]
-#[cfg_attr(test, assert_instr(ldap1, LANE = 0))]
+#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(ldap1, LANE = 0))]
 #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")]
 pub unsafe fn vldap1_lane_u64<const LANE: i32>(ptr: *const u64, src: uint64x1_t) -> uint64x1_t {
     static_assert!(LANE == 0);
@@ -12918,7 +12918,7 @@ pub unsafe fn vldap1_lane_u64<const LANE: i32>(ptr: *const u64, src: uint64x1_t)
 #[inline(always)]
 #[rustc_legacy_const_generics(2)]
 #[target_feature(enable = "neon,rcpc3")]
-#[cfg_attr(test, assert_instr(ldap1, LANE = 0))]
+#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(ldap1, LANE = 0))]
 #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")]
 pub unsafe fn vldap1q_lane_u64<const LANE: i32>(ptr: *const u64, src: uint64x2_t) -> uint64x2_t {
     static_assert_uimm_bits!(LANE, 1);
@@ -12931,7 +12931,7 @@ pub unsafe fn vldap1q_lane_u64<const LANE: i32>(ptr: *const u64, src: uint64x2_t
 #[inline(always)]
 #[rustc_legacy_const_generics(2)]
 #[target_feature(enable = "neon,rcpc3")]
-#[cfg_attr(test, assert_instr(ldap1, LANE = 0))]
+#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(ldap1, LANE = 0))]
 #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")]
 pub unsafe fn vldap1_lane_p64<const LANE: i32>(ptr: *const p64, src: poly64x1_t) -> poly64x1_t {
     static_assert!(LANE == 0);
@@ -12944,7 +12944,7 @@ pub unsafe fn vldap1_lane_p64<const LANE: i32>(ptr: *const p64, src: poly64x1_t)
 #[inline(always)]
 #[rustc_legacy_const_generics(2)]
 #[target_feature(enable = "neon,rcpc3")]
-#[cfg_attr(test, assert_instr(ldap1, LANE = 0))]
+#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(ldap1, LANE = 0))]
 #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")]
 pub unsafe fn vldap1q_lane_p64<const LANE: i32>(ptr: *const p64, src: poly64x2_t) -> poly64x2_t {
     static_assert_uimm_bits!(LANE, 1);
@@ -24457,7 +24457,7 @@ pub fn vrsubhn_high_u64(a: uint32x2_t, b: uint64x2_t, c: uint64x2_t) -> uint32x4
 #[inline(always)]
 #[unstable(feature = "stdarch_neon_fp8", issue = "none")]
 #[target_feature(enable = "neon,fp8")]
-#[cfg_attr(test, assert_instr(fscale))]
+#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(fscale))]
 pub fn vscale_f16(vn: float16x4_t, vm: int16x4_t) -> float16x4_t {
     unsafe extern "unadjusted" {
         #[cfg_attr(
@@ -24473,7 +24473,7 @@ pub fn vscale_f16(vn: float16x4_t, vm: int16x4_t) -> float16x4_t {
 #[inline(always)]
 #[unstable(feature = "stdarch_neon_fp8", issue = "none")]
 #[target_feature(enable = "neon,fp8")]
-#[cfg_attr(test, assert_instr(fscale))]
+#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(fscale))]
 pub fn vscaleq_f16(vn: float16x8_t, vm: int16x8_t) -> float16x8_t {
     unsafe extern "unadjusted" {
         #[cfg_attr(
@@ -24489,7 +24489,7 @@ pub fn vscaleq_f16(vn: float16x8_t, vm: int16x8_t) -> float16x8_t {
 #[inline(always)]
 #[unstable(feature = "stdarch_neon_fp8", issue = "none")]
 #[target_feature(enable = "neon,fp8")]
-#[cfg_attr(test, assert_instr(fscale))]
+#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(fscale))]
 pub fn vscale_f32(vn: float32x2_t, vm: int32x2_t) -> float32x2_t {
     unsafe extern "unadjusted" {
         #[cfg_attr(
@@ -24505,7 +24505,7 @@ pub fn vscale_f32(vn: float32x2_t, vm: int32x2_t) -> float32x2_t {
 #[inline(always)]
 #[unstable(feature = "stdarch_neon_fp8", issue = "none")]
 #[target_feature(enable = "neon,fp8")]
-#[cfg_attr(test, assert_instr(fscale))]
+#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(fscale))]
 pub fn vscaleq_f32(vn: float32x4_t, vm: int32x4_t) -> float32x4_t {
     unsafe extern "unadjusted" {
         #[cfg_attr(
@@ -24521,7 +24521,7 @@ pub fn vscaleq_f32(vn: float32x4_t, vm: int32x4_t) -> float32x4_t {
 #[inline(always)]
 #[unstable(feature = "stdarch_neon_fp8", issue = "none")]
 #[target_feature(enable = "neon,fp8")]
-#[cfg_attr(test, assert_instr(fscale))]
+#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(fscale))]
 pub fn vscaleq_f64(vn: float64x2_t, vm: int64x2_t) -> float64x2_t {
     unsafe extern "unadjusted" {
         #[cfg_attr(
@@ -27119,7 +27119,7 @@ pub unsafe fn vst4q_u64(a: *mut u64, b: uint64x2x4_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1_lane_f64)"]
 #[inline(always)]
 #[target_feature(enable = "neon,rcpc3")]
-#[cfg_attr(test, assert_instr(stl1, LANE = 0))]
+#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stl1, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")]
 pub fn vstl1_lane_f64<const LANE: i32>(ptr: *mut f64, val: float64x1_t) {
@@ -27130,7 +27130,7 @@ pub fn vstl1_lane_f64<const LANE: i32>(ptr: *mut f64, val: float64x1_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1q_lane_f64)"]
 #[inline(always)]
 #[target_feature(enable = "neon,rcpc3")]
-#[cfg_attr(test, assert_instr(stl1, LANE = 0))]
+#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stl1, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")]
 pub fn vstl1q_lane_f64<const LANE: i32>(ptr: *mut f64, val: float64x2_t) {
@@ -27141,7 +27141,7 @@ pub fn vstl1q_lane_f64<const LANE: i32>(ptr: *mut f64, val: float64x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1_lane_u64)"]
 #[inline(always)]
 #[target_feature(enable = "neon,rcpc3")]
-#[cfg_attr(test, assert_instr(stl1, LANE = 0))]
+#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stl1, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")]
 pub fn vstl1_lane_u64<const LANE: i32>(ptr: *mut u64, val: uint64x1_t) {
@@ -27152,7 +27152,7 @@ pub fn vstl1_lane_u64<const LANE: i32>(ptr: *mut u64, val: uint64x1_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1q_lane_u64)"]
 #[inline(always)]
 #[target_feature(enable = "neon,rcpc3")]
-#[cfg_attr(test, assert_instr(stl1, LANE = 0))]
+#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stl1, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")]
 pub fn vstl1q_lane_u64<const LANE: i32>(ptr: *mut u64, val: uint64x2_t) {
@@ -27163,7 +27163,7 @@ pub fn vstl1q_lane_u64<const LANE: i32>(ptr: *mut u64, val: uint64x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1_lane_p64)"]
 #[inline(always)]
 #[target_feature(enable = "neon,rcpc3")]
-#[cfg_attr(test, assert_instr(stl1, LANE = 0))]
+#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stl1, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")]
 pub fn vstl1_lane_p64<const LANE: i32>(ptr: *mut p64, val: poly64x1_t) {
@@ -27174,7 +27174,7 @@ pub fn vstl1_lane_p64<const LANE: i32>(ptr: *mut p64, val: poly64x1_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1q_lane_p64)"]
 #[inline(always)]
 #[target_feature(enable = "neon,rcpc3")]
-#[cfg_attr(test, assert_instr(stl1, LANE = 0))]
+#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stl1, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")]
 pub fn vstl1q_lane_p64<const LANE: i32>(ptr: *mut p64, val: poly64x2_t) {
@@ -27185,7 +27185,7 @@ pub fn vstl1q_lane_p64<const LANE: i32>(ptr: *mut p64, val: poly64x2_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1_lane_s64)"]
 #[inline(always)]
 #[target_feature(enable = "neon,rcpc3")]
-#[cfg_attr(test, assert_instr(stl1, LANE = 0))]
+#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stl1, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")]
 pub fn vstl1_lane_s64<const LANE: i32>(ptr: *mut i64, val: int64x1_t) {
@@ -27200,7 +27200,7 @@ pub fn vstl1_lane_s64<const LANE: i32>(ptr: *mut i64, val: int64x1_t) {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1q_lane_s64)"]
 #[inline(always)]
 #[target_feature(enable = "neon,rcpc3")]
-#[cfg_attr(test, assert_instr(stl1, LANE = 0))]
+#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stl1, LANE = 0))]
 #[rustc_legacy_const_generics(2)]
 #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")]
 pub fn vstl1q_lane_s64<const LANE: i32>(ptr: *mut i64, val: int64x2_t) {
diff --git a/library/stdarch/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml b/library/stdarch/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
index ec5bc8c954d7..a9bc377924dd 100644
--- a/library/stdarch/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
+++ b/library/stdarch/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
@@ -4415,7 +4415,7 @@ intrinsics:
       unsafe: [neon]
     attr:
       - FnCall: [target_feature, ['enable = "neon,rcpc3"']]
-      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [ldap1, 'LANE = 0']]}]]
+      - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env= "msvc"']]}]]}, {FnCall: [assert_instr, [ldap1, 'LANE = 0']]}]]
       - FnCall: [rustc_legacy_const_generics, ["2"]]
       - *neon-unstable-feat-lrcpc3
     types:
@@ -4446,7 +4446,7 @@ intrinsics:
     attr:
       - FnCall: [rustc_legacy_const_generics, ["2"]]
       - FnCall: [target_feature, ['enable = "neon,rcpc3"']]
-      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [ldap1, 'LANE = 0']]}]]
+      - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env= "msvc"']]}]]}, {FnCall: [assert_instr, [ldap1, 'LANE = 0']]}]]
       - *neon-unstable-feat-lrcpc3
     types:
       - ['*const u64', uint64x1_t,'static_assert!', 'LANE == 0','']
@@ -4471,7 +4471,7 @@ intrinsics:
     safety: safe
     attr:
       - FnCall: [target_feature, ['enable = "neon,rcpc3"']]
-      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [stl1, 'LANE = 0']]}]]
+      - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env= "msvc"']]}]]}, {FnCall: [assert_instr, [stl1, 'LANE = 0']]}]]
       - FnCall: [rustc_legacy_const_generics, ["2"]]
       - *neon-unstable-feat-lrcpc3
     types:
@@ -4499,7 +4499,7 @@ intrinsics:
     safety: safe
     attr:
       - FnCall: [target_feature, ['enable = "neon,rcpc3"']]
-      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [stl1, 'LANE = 0']]}]]
+      - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env= "msvc"']]}]]}, {FnCall: [assert_instr, [stl1, 'LANE = 0']]}]]
       - FnCall: [rustc_legacy_const_generics, ["2"]]
       - *neon-unstable-feat-lrcpc3
     types:
@@ -13973,7 +13973,7 @@ intrinsics:
     return_type: "{neon_type}"
     attr:
       - FnCall: [target_feature, ['enable = "neon,faminmax"']]
-      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [famax]]}]]
+      - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env= "msvc"']]}]]}, {FnCall: [assert_instr, [famax]]}]]
       - FnCall: [unstable, ['feature = "faminmax"', 'issue = "137933"']]
     safety: safe
     types:
@@ -13995,7 +13995,7 @@ intrinsics:
     return_type: "{neon_type}"
     attr:
       - FnCall: [target_feature, ['enable = "neon,faminmax"']]
-      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [famin]]}]]
+      - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env= "msvc"']]}]]}, {FnCall: [assert_instr, [famin]]}]]
       - FnCall: [unstable, ['feature = "faminmax"', 'issue = "137933"']]
     safety: safe
     types:
@@ -14351,7 +14351,7 @@ intrinsics:
     attr:
       - *neon-unstable-fp8
       - FnCall: [target_feature, ['enable = "neon,fp8"']]
-    assert_instr: [fscale]
+      - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env= "msvc"']]}]]}, {FnCall: [assert_instr, [fscale]]}]]
     safety: safe
     types:
       - [float16x4_t, int16x4_t]

From 9fddd28d38eda100b07b0b11fa578da64c09da6b Mon Sep 17 00:00:00 2001
From: reucru01 <reuben.cruise@arm.com>
Date: Wed, 14 Jan 2026 13:59:59 +0000
Subject: [PATCH 81/97] Ammends typo in generator & generated

---
 .../core_arch/src/aarch64/neon/generated.rs   |  484 ++---
 .../src/arm_shared/neon/generated.rs          | 1772 ++++++++---------
 .../crates/stdarch-gen-arm/src/intrinsic.rs   |    2 +-
 3 files changed, 1129 insertions(+), 1129 deletions(-)

diff --git a/library/stdarch/crates/core_arch/src/aarch64/neon/generated.rs b/library/stdarch/crates/core_arch/src/aarch64/neon/generated.rs
index 68676ebd2c86..9507b71106dd 100644
--- a/library/stdarch/crates/core_arch/src/aarch64/neon/generated.rs
+++ b/library/stdarch/crates/core_arch/src/aarch64/neon/generated.rs
@@ -11174,7 +11174,7 @@ pub fn vfmsd_laneq_f64<const LANE: i32>(a: f64, b: f64, c: float64x2_t) -> f64 {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(test, assert_instr(ldr))]
@@ -11186,7 +11186,7 @@ pub unsafe fn vld1_f16(ptr: *const f16) -> float16x4_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(test, assert_instr(ldr))]
@@ -11198,7 +11198,7 @@ pub unsafe fn vld1q_f16(ptr: *const f16) -> float16x8_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
@@ -11209,7 +11209,7 @@ pub unsafe fn vld1_f32(ptr: *const f32) -> float32x2_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
@@ -11220,7 +11220,7 @@ pub unsafe fn vld1q_f32(ptr: *const f32) -> float32x4_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
@@ -11231,7 +11231,7 @@ pub unsafe fn vld1_f64(ptr: *const f64) -> float64x1_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
@@ -11242,7 +11242,7 @@ pub unsafe fn vld1q_f64(ptr: *const f64) -> float64x2_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
@@ -11253,7 +11253,7 @@ pub unsafe fn vld1_s8(ptr: *const i8) -> int8x8_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
@@ -11264,7 +11264,7 @@ pub unsafe fn vld1q_s8(ptr: *const i8) -> int8x16_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
@@ -11275,7 +11275,7 @@ pub unsafe fn vld1_s16(ptr: *const i16) -> int16x4_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
@@ -11286,7 +11286,7 @@ pub unsafe fn vld1q_s16(ptr: *const i16) -> int16x8_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
@@ -11297,7 +11297,7 @@ pub unsafe fn vld1_s32(ptr: *const i32) -> int32x2_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
@@ -11308,7 +11308,7 @@ pub unsafe fn vld1q_s32(ptr: *const i32) -> int32x4_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
@@ -11319,7 +11319,7 @@ pub unsafe fn vld1_s64(ptr: *const i64) -> int64x1_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
@@ -11330,7 +11330,7 @@ pub unsafe fn vld1q_s64(ptr: *const i64) -> int64x2_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
@@ -11341,7 +11341,7 @@ pub unsafe fn vld1_u8(ptr: *const u8) -> uint8x8_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
@@ -11352,7 +11352,7 @@ pub unsafe fn vld1q_u8(ptr: *const u8) -> uint8x16_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
@@ -11363,7 +11363,7 @@ pub unsafe fn vld1_u16(ptr: *const u16) -> uint16x4_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
@@ -11374,7 +11374,7 @@ pub unsafe fn vld1q_u16(ptr: *const u16) -> uint16x8_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
@@ -11385,7 +11385,7 @@ pub unsafe fn vld1_u32(ptr: *const u32) -> uint32x2_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
@@ -11396,7 +11396,7 @@ pub unsafe fn vld1q_u32(ptr: *const u32) -> uint32x4_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
@@ -11407,7 +11407,7 @@ pub unsafe fn vld1_u64(ptr: *const u64) -> uint64x1_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
@@ -11418,7 +11418,7 @@ pub unsafe fn vld1q_u64(ptr: *const u64) -> uint64x2_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
@@ -11429,7 +11429,7 @@ pub unsafe fn vld1_p8(ptr: *const p8) -> poly8x8_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
@@ -11440,7 +11440,7 @@ pub unsafe fn vld1q_p8(ptr: *const p8) -> poly8x16_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
@@ -11451,7 +11451,7 @@ pub unsafe fn vld1_p16(ptr: *const p16) -> poly16x4_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ldr))]
@@ -11462,7 +11462,7 @@ pub unsafe fn vld1q_p16(ptr: *const p16) -> poly16x8_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(test, assert_instr(ldr))]
@@ -11473,7 +11473,7 @@ pub unsafe fn vld1_p64(ptr: *const p64) -> poly64x1_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(test, assert_instr(ldr))]
@@ -11484,7 +11484,7 @@ pub unsafe fn vld1q_p64(ptr: *const p64) -> poly64x2_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f64_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11502,7 +11502,7 @@ pub unsafe fn vld1_f64_x2(a: *const f64) -> float64x1x2_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f64_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11520,7 +11520,7 @@ pub unsafe fn vld1_f64_x3(a: *const f64) -> float64x1x3_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f64_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11538,7 +11538,7 @@ pub unsafe fn vld1_f64_x4(a: *const f64) -> float64x1x4_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f64_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11556,7 +11556,7 @@ pub unsafe fn vld1q_f64_x2(a: *const f64) -> float64x2x2_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f64_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11574,7 +11574,7 @@ pub unsafe fn vld1q_f64_x3(a: *const f64) -> float64x2x3_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f64_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11592,7 +11592,7 @@ pub unsafe fn vld1q_f64_x4(a: *const f64) -> float64x2x4_t {
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_f64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11610,7 +11610,7 @@ pub unsafe fn vld2_dup_f64(a: *const f64) -> float64x1x2_t {
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_f64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11628,7 +11628,7 @@ pub unsafe fn vld2q_dup_f64(a: *const f64) -> float64x2x2_t {
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11646,7 +11646,7 @@ pub unsafe fn vld2q_dup_s64(a: *const i64) -> int64x2x2_t {
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_f64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11664,7 +11664,7 @@ pub unsafe fn vld2_f64(a: *const f64) -> float64x1x2_t {
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_f64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld2, LANE = 0))]
@@ -11684,7 +11684,7 @@ pub unsafe fn vld2_lane_f64<const LANE: i32>(a: *const f64, b: float64x1x2_t) ->
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld2, LANE = 0))]
@@ -11704,7 +11704,7 @@ pub unsafe fn vld2_lane_s64<const LANE: i32>(a: *const i64, b: int64x1x2_t) -> i
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_p64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(test, assert_instr(ld2, LANE = 0))]
@@ -11717,7 +11717,7 @@ pub unsafe fn vld2_lane_p64<const LANE: i32>(a: *const p64, b: poly64x1x2_t) ->
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_u64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld2, LANE = 0))]
@@ -11730,7 +11730,7 @@ pub unsafe fn vld2_lane_u64<const LANE: i32>(a: *const u64, b: uint64x1x2_t) ->
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_p64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
@@ -11742,7 +11742,7 @@ pub unsafe fn vld2q_dup_p64(a: *const p64) -> poly64x2x2_t {
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_p64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
@@ -11757,7 +11757,7 @@ pub unsafe fn vld2q_dup_p64(a: *const p64) -> poly64x2x2_t {
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -11769,7 +11769,7 @@ pub unsafe fn vld2q_dup_u64(a: *const u64) -> uint64x2x2_t {
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -11784,7 +11784,7 @@ pub unsafe fn vld2q_dup_u64(a: *const u64) -> uint64x2x2_t {
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_f64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11802,7 +11802,7 @@ pub unsafe fn vld2q_f64(a: *const f64) -> float64x2x2_t {
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -11820,7 +11820,7 @@ pub unsafe fn vld2q_s64(a: *const i64) -> int64x2x2_t {
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_f64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld2, LANE = 0))]
@@ -11841,7 +11841,7 @@ pub unsafe fn vld2q_lane_f64<const LANE: i32>(a: *const f64, b: float64x2x2_t) -
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld2, LANE = 0))]
@@ -11861,7 +11861,7 @@ pub unsafe fn vld2q_lane_s8<const LANE: i32>(a: *const i8, b: int8x16x2_t) -> in
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_s64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld2, LANE = 0))]
@@ -11881,7 +11881,7 @@ pub unsafe fn vld2q_lane_s64<const LANE: i32>(a: *const i64, b: int64x2x2_t) ->
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_p64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(test, assert_instr(ld2, LANE = 0))]
@@ -11894,7 +11894,7 @@ pub unsafe fn vld2q_lane_p64<const LANE: i32>(a: *const p64, b: poly64x2x2_t) ->
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld2, LANE = 0))]
@@ -11907,7 +11907,7 @@ pub unsafe fn vld2q_lane_u8<const LANE: i32>(a: *const u8, b: uint8x16x2_t) -> u
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_u64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld2, LANE = 0))]
@@ -11920,7 +11920,7 @@ pub unsafe fn vld2q_lane_u64<const LANE: i32>(a: *const u64, b: uint64x2x2_t) ->
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld2, LANE = 0))]
@@ -11933,7 +11933,7 @@ pub unsafe fn vld2q_lane_p8<const LANE: i32>(a: *const p8, b: poly8x16x2_t) -> p
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_p64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
@@ -11945,7 +11945,7 @@ pub unsafe fn vld2q_p64(a: *const p64) -> poly64x2x2_t {
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_p64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
@@ -11960,7 +11960,7 @@ pub unsafe fn vld2q_p64(a: *const p64) -> poly64x2x2_t {
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -11972,7 +11972,7 @@ pub unsafe fn vld2q_u64(a: *const u64) -> uint64x2x2_t {
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -11987,7 +11987,7 @@ pub unsafe fn vld2q_u64(a: *const u64) -> uint64x2x2_t {
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_f64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -12005,7 +12005,7 @@ pub unsafe fn vld3_dup_f64(a: *const f64) -> float64x1x3_t {
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_f64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -12023,7 +12023,7 @@ pub unsafe fn vld3q_dup_f64(a: *const f64) -> float64x2x3_t {
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -12041,7 +12041,7 @@ pub unsafe fn vld3q_dup_s64(a: *const i64) -> int64x2x3_t {
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_f64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -12059,7 +12059,7 @@ pub unsafe fn vld3_f64(a: *const f64) -> float64x1x3_t {
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_f64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld3, LANE = 0))]
@@ -12085,7 +12085,7 @@ pub unsafe fn vld3_lane_f64<const LANE: i32>(a: *const f64, b: float64x1x3_t) ->
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_p64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(test, assert_instr(ld3, LANE = 0))]
@@ -12098,7 +12098,7 @@ pub unsafe fn vld3_lane_p64<const LANE: i32>(a: *const p64, b: poly64x1x3_t) ->
 #[doc = "Load multiple 3-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld3, LANE = 0))]
@@ -12124,7 +12124,7 @@ pub unsafe fn vld3_lane_s64<const LANE: i32>(a: *const i64, b: int64x1x3_t) -> i
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_u64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld3, LANE = 0))]
@@ -12137,7 +12137,7 @@ pub unsafe fn vld3_lane_u64<const LANE: i32>(a: *const u64, b: uint64x1x3_t) ->
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_p64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
@@ -12149,7 +12149,7 @@ pub unsafe fn vld3q_dup_p64(a: *const p64) -> poly64x2x3_t {
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_p64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
@@ -12165,7 +12165,7 @@ pub unsafe fn vld3q_dup_p64(a: *const p64) -> poly64x2x3_t {
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -12177,7 +12177,7 @@ pub unsafe fn vld3q_dup_u64(a: *const u64) -> uint64x2x3_t {
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -12193,7 +12193,7 @@ pub unsafe fn vld3q_dup_u64(a: *const u64) -> uint64x2x3_t {
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_f64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -12211,7 +12211,7 @@ pub unsafe fn vld3q_f64(a: *const f64) -> float64x2x3_t {
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -12229,7 +12229,7 @@ pub unsafe fn vld3q_s64(a: *const i64) -> int64x2x3_t {
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_f64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld3, LANE = 0))]
@@ -12255,7 +12255,7 @@ pub unsafe fn vld3q_lane_f64<const LANE: i32>(a: *const f64, b: float64x2x3_t) -
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_p64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(test, assert_instr(ld3, LANE = 0))]
@@ -12268,7 +12268,7 @@ pub unsafe fn vld3q_lane_p64<const LANE: i32>(a: *const p64, b: poly64x2x3_t) ->
 #[doc = "Load multiple 3-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld3, LANE = 0))]
@@ -12294,7 +12294,7 @@ pub unsafe fn vld3q_lane_s8<const LANE: i32>(a: *const i8, b: int8x16x3_t) -> in
 #[doc = "Load multiple 3-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_s64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld3, LANE = 0))]
@@ -12320,7 +12320,7 @@ pub unsafe fn vld3q_lane_s64<const LANE: i32>(a: *const i64, b: int64x2x3_t) ->
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld3, LANE = 0))]
@@ -12333,7 +12333,7 @@ pub unsafe fn vld3q_lane_u8<const LANE: i32>(a: *const u8, b: uint8x16x3_t) -> u
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_u64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld3, LANE = 0))]
@@ -12346,7 +12346,7 @@ pub unsafe fn vld3q_lane_u64<const LANE: i32>(a: *const u64, b: uint64x2x3_t) ->
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld3, LANE = 0))]
@@ -12359,7 +12359,7 @@ pub unsafe fn vld3q_lane_p8<const LANE: i32>(a: *const p8, b: poly8x16x3_t) -> p
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_p64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
@@ -12371,7 +12371,7 @@ pub unsafe fn vld3q_p64(a: *const p64) -> poly64x2x3_t {
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_p64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
@@ -12387,7 +12387,7 @@ pub unsafe fn vld3q_p64(a: *const p64) -> poly64x2x3_t {
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -12399,7 +12399,7 @@ pub unsafe fn vld3q_u64(a: *const u64) -> uint64x2x3_t {
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -12415,7 +12415,7 @@ pub unsafe fn vld3q_u64(a: *const u64) -> uint64x2x3_t {
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_f64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld4r))]
@@ -12433,7 +12433,7 @@ pub unsafe fn vld4_dup_f64(a: *const f64) -> float64x1x4_t {
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_f64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld4r))]
@@ -12451,7 +12451,7 @@ pub unsafe fn vld4q_dup_f64(a: *const f64) -> float64x2x4_t {
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld4r))]
@@ -12469,7 +12469,7 @@ pub unsafe fn vld4q_dup_s64(a: *const i64) -> int64x2x4_t {
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_f64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -12487,7 +12487,7 @@ pub unsafe fn vld4_f64(a: *const f64) -> float64x1x4_t {
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_f64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld4, LANE = 0))]
@@ -12514,7 +12514,7 @@ pub unsafe fn vld4_lane_f64<const LANE: i32>(a: *const f64, b: float64x1x4_t) ->
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld4, LANE = 0))]
@@ -12541,7 +12541,7 @@ pub unsafe fn vld4_lane_s64<const LANE: i32>(a: *const i64, b: int64x1x4_t) -> i
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_p64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(test, assert_instr(ld4, LANE = 0))]
@@ -12554,7 +12554,7 @@ pub unsafe fn vld4_lane_p64<const LANE: i32>(a: *const p64, b: poly64x1x4_t) ->
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_u64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld4, LANE = 0))]
@@ -12567,7 +12567,7 @@ pub unsafe fn vld4_lane_u64<const LANE: i32>(a: *const u64, b: uint64x1x4_t) ->
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_p64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
@@ -12579,7 +12579,7 @@ pub unsafe fn vld4q_dup_p64(a: *const p64) -> poly64x2x4_t {
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_p64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
@@ -12596,7 +12596,7 @@ pub unsafe fn vld4q_dup_p64(a: *const p64) -> poly64x2x4_t {
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -12608,7 +12608,7 @@ pub unsafe fn vld4q_dup_u64(a: *const u64) -> uint64x2x4_t {
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -12625,7 +12625,7 @@ pub unsafe fn vld4q_dup_u64(a: *const u64) -> uint64x2x4_t {
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_f64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -12643,7 +12643,7 @@ pub unsafe fn vld4q_f64(a: *const f64) -> float64x2x4_t {
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -12661,7 +12661,7 @@ pub unsafe fn vld4q_s64(a: *const i64) -> int64x2x4_t {
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_f64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld4, LANE = 0))]
@@ -12688,7 +12688,7 @@ pub unsafe fn vld4q_lane_f64<const LANE: i32>(a: *const f64, b: float64x2x4_t) -
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld4, LANE = 0))]
@@ -12715,7 +12715,7 @@ pub unsafe fn vld4q_lane_s8<const LANE: i32>(a: *const i8, b: int8x16x4_t) -> in
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_s64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld4, LANE = 0))]
@@ -12742,7 +12742,7 @@ pub unsafe fn vld4q_lane_s64<const LANE: i32>(a: *const i64, b: int64x2x4_t) ->
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_p64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(test, assert_instr(ld4, LANE = 0))]
@@ -12755,7 +12755,7 @@ pub unsafe fn vld4q_lane_p64<const LANE: i32>(a: *const p64, b: poly64x2x4_t) ->
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld4, LANE = 0))]
@@ -12768,7 +12768,7 @@ pub unsafe fn vld4q_lane_u8<const LANE: i32>(a: *const u8, b: uint8x16x4_t) -> u
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_u64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld4, LANE = 0))]
@@ -12781,7 +12781,7 @@ pub unsafe fn vld4q_lane_u64<const LANE: i32>(a: *const u64, b: uint64x2x4_t) ->
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(ld4, LANE = 0))]
@@ -12794,7 +12794,7 @@ pub unsafe fn vld4q_lane_p8<const LANE: i32>(a: *const p8, b: poly8x16x4_t) -> p
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_p64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -12806,7 +12806,7 @@ pub unsafe fn vld4q_p64(a: *const p64) -> poly64x2x4_t {
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_p64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -12823,7 +12823,7 @@ pub unsafe fn vld4q_p64(a: *const p64) -> poly64x2x4_t {
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -12835,7 +12835,7 @@ pub unsafe fn vld4q_u64(a: *const u64) -> uint64x2x4_t {
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -12852,7 +12852,7 @@ pub unsafe fn vld4q_u64(a: *const u64) -> uint64x2x4_t {
 #[doc = "Load-acquire RCpc one single-element structure to one lane of one register"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldap1_lane_s64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,rcpc3")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(ldap1, LANE = 0))]
@@ -12870,7 +12870,7 @@ pub unsafe fn vldap1_lane_s64<const LANE: i32>(ptr: *const i64, src: int64x1_t)
 #[doc = "Load-acquire RCpc one single-element structure to one lane of one register"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldap1q_lane_s64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,rcpc3")]
 #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(ldap1, LANE = 0))]
@@ -12888,7 +12888,7 @@ pub unsafe fn vldap1q_lane_s64<const LANE: i32>(ptr: *const i64, src: int64x2_t)
 #[doc = "Load-acquire RCpc one single-element structure to one lane of one register"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldap1q_lane_f64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[rustc_legacy_const_generics(2)]
 #[target_feature(enable = "neon,rcpc3")]
@@ -12901,7 +12901,7 @@ pub unsafe fn vldap1q_lane_f64<const LANE: i32>(ptr: *const f64, src: float64x2_
 #[doc = "Load-acquire RCpc one single-element structure to one lane of one register"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldap1_lane_u64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[rustc_legacy_const_generics(2)]
 #[target_feature(enable = "neon,rcpc3")]
@@ -12914,7 +12914,7 @@ pub unsafe fn vldap1_lane_u64<const LANE: i32>(ptr: *const u64, src: uint64x1_t)
 #[doc = "Load-acquire RCpc one single-element structure to one lane of one register"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldap1q_lane_u64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[rustc_legacy_const_generics(2)]
 #[target_feature(enable = "neon,rcpc3")]
@@ -12927,7 +12927,7 @@ pub unsafe fn vldap1q_lane_u64<const LANE: i32>(ptr: *const u64, src: uint64x2_t
 #[doc = "Load-acquire RCpc one single-element structure to one lane of one register"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldap1_lane_p64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[rustc_legacy_const_generics(2)]
 #[target_feature(enable = "neon,rcpc3")]
@@ -12940,7 +12940,7 @@ pub unsafe fn vldap1_lane_p64<const LANE: i32>(ptr: *const p64, src: poly64x1_t)
 #[doc = "Load-acquire RCpc one single-element structure to one lane of one register"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldap1q_lane_p64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[rustc_legacy_const_generics(2)]
 #[target_feature(enable = "neon,rcpc3")]
@@ -12953,7 +12953,7 @@ pub unsafe fn vldap1q_lane_p64<const LANE: i32>(ptr: *const p64, src: poly64x2_t
 #[doc = "Lookup table read with 2-bit indices"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, INDEX = 1))]
@@ -12966,7 +12966,7 @@ pub unsafe fn vluti2_lane_f16<const INDEX: i32>(a: float16x4_t, b: uint8x8_t) ->
 #[doc = "Lookup table read with 2-bit indices"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, INDEX = 1))]
@@ -12979,7 +12979,7 @@ pub unsafe fn vluti2q_lane_f16<const INDEX: i32>(a: float16x8_t, b: uint8x8_t) -
 #[doc = "Lookup table read with 2-bit indices"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, INDEX = 1))]
@@ -12992,7 +12992,7 @@ pub unsafe fn vluti2_lane_u8<const INDEX: i32>(a: uint8x8_t, b: uint8x8_t) -> ui
 #[doc = "Lookup table read with 2-bit indices"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, INDEX = 1))]
@@ -13005,7 +13005,7 @@ pub unsafe fn vluti2q_lane_u8<const INDEX: i32>(a: uint8x16_t, b: uint8x8_t) ->
 #[doc = "Lookup table read with 2-bit indices"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, INDEX = 1))]
@@ -13018,7 +13018,7 @@ pub unsafe fn vluti2_lane_u16<const INDEX: i32>(a: uint16x4_t, b: uint8x8_t) ->
 #[doc = "Lookup table read with 2-bit indices"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, INDEX = 1))]
@@ -13031,7 +13031,7 @@ pub unsafe fn vluti2q_lane_u16<const INDEX: i32>(a: uint16x8_t, b: uint8x8_t) ->
 #[doc = "Lookup table read with 2-bit indices"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, INDEX = 1))]
@@ -13044,7 +13044,7 @@ pub unsafe fn vluti2_lane_p8<const INDEX: i32>(a: poly8x8_t, b: uint8x8_t) -> po
 #[doc = "Lookup table read with 2-bit indices"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, INDEX = 1))]
@@ -13057,7 +13057,7 @@ pub unsafe fn vluti2q_lane_p8<const INDEX: i32>(a: poly8x16_t, b: uint8x8_t) ->
 #[doc = "Lookup table read with 2-bit indices"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, INDEX = 1))]
@@ -13070,7 +13070,7 @@ pub unsafe fn vluti2_lane_p16<const INDEX: i32>(a: poly16x4_t, b: uint8x8_t) ->
 #[doc = "Lookup table read with 2-bit indices"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, INDEX = 1))]
@@ -13083,7 +13083,7 @@ pub unsafe fn vluti2q_lane_p16<const INDEX: i32>(a: poly16x8_t, b: uint8x8_t) ->
 #[doc = "Lookup table read with 2-bit indices"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, LANE = 1))]
@@ -13103,7 +13103,7 @@ pub unsafe fn vluti2_lane_s8<const LANE: i32>(a: int8x8_t, b: uint8x8_t) -> int8
 #[doc = "Lookup table read with 2-bit indices"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, LANE = 1))]
@@ -13123,7 +13123,7 @@ pub unsafe fn vluti2q_lane_s8<const LANE: i32>(a: int8x16_t, b: uint8x8_t) -> in
 #[doc = "Lookup table read with 2-bit indices"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_lane_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, LANE = 1))]
@@ -13143,7 +13143,7 @@ pub unsafe fn vluti2_lane_s16<const LANE: i32>(a: int16x4_t, b: uint8x8_t) -> in
 #[doc = "Lookup table read with 2-bit indices"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_lane_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, LANE = 1))]
@@ -13163,7 +13163,7 @@ pub unsafe fn vluti2q_lane_s16<const LANE: i32>(a: int16x8_t, b: uint8x8_t) -> i
 #[doc = "Lookup table read with 2-bit indices"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_laneq_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, INDEX = 1))]
@@ -13176,7 +13176,7 @@ pub unsafe fn vluti2_laneq_f16<const INDEX: i32>(a: float16x4_t, b: uint8x16_t)
 #[doc = "Lookup table read with 2-bit indices"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_laneq_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, INDEX = 1))]
@@ -13189,7 +13189,7 @@ pub unsafe fn vluti2q_laneq_f16<const INDEX: i32>(a: float16x8_t, b: uint8x16_t)
 #[doc = "Lookup table read with 2-bit indices"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_laneq_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, INDEX = 1))]
@@ -13202,7 +13202,7 @@ pub unsafe fn vluti2_laneq_u8<const INDEX: i32>(a: uint8x8_t, b: uint8x16_t) ->
 #[doc = "Lookup table read with 2-bit indices"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_laneq_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, INDEX = 1))]
@@ -13215,7 +13215,7 @@ pub unsafe fn vluti2q_laneq_u8<const INDEX: i32>(a: uint8x16_t, b: uint8x16_t) -
 #[doc = "Lookup table read with 2-bit indices"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_laneq_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, INDEX = 1))]
@@ -13228,7 +13228,7 @@ pub unsafe fn vluti2_laneq_u16<const INDEX: i32>(a: uint16x4_t, b: uint8x16_t) -
 #[doc = "Lookup table read with 2-bit indices"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_laneq_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, INDEX = 1))]
@@ -13241,7 +13241,7 @@ pub unsafe fn vluti2q_laneq_u16<const INDEX: i32>(a: uint16x8_t, b: uint8x16_t)
 #[doc = "Lookup table read with 2-bit indices"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_laneq_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, INDEX = 1))]
@@ -13254,7 +13254,7 @@ pub unsafe fn vluti2_laneq_p8<const INDEX: i32>(a: poly8x8_t, b: uint8x16_t) ->
 #[doc = "Lookup table read with 2-bit indices"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_laneq_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, INDEX = 1))]
@@ -13267,7 +13267,7 @@ pub unsafe fn vluti2q_laneq_p8<const INDEX: i32>(a: poly8x16_t, b: uint8x16_t) -
 #[doc = "Lookup table read with 2-bit indices"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_laneq_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, INDEX = 1))]
@@ -13280,7 +13280,7 @@ pub unsafe fn vluti2_laneq_p16<const INDEX: i32>(a: poly16x4_t, b: uint8x16_t) -
 #[doc = "Lookup table read with 2-bit indices"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_laneq_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, INDEX = 1))]
@@ -13293,7 +13293,7 @@ pub unsafe fn vluti2q_laneq_p16<const INDEX: i32>(a: poly16x8_t, b: uint8x16_t)
 #[doc = "Lookup table read with 2-bit indices"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_laneq_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, INDEX = 1))]
@@ -13313,7 +13313,7 @@ pub unsafe fn vluti2_laneq_s8<const INDEX: i32>(a: int8x8_t, b: uint8x16_t) -> i
 #[doc = "Lookup table read with 2-bit indices"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_laneq_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, INDEX = 1))]
@@ -13333,7 +13333,7 @@ pub unsafe fn vluti2q_laneq_s8<const INDEX: i32>(a: int8x16_t, b: uint8x16_t) ->
 #[doc = "Lookup table read with 2-bit indices"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2_laneq_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, INDEX = 1))]
@@ -13353,7 +13353,7 @@ pub unsafe fn vluti2_laneq_s16<const INDEX: i32>(a: int16x4_t, b: uint8x16_t) ->
 #[doc = "Lookup table read with 2-bit indices"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti2q_laneq_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, INDEX = 1))]
@@ -13373,7 +13373,7 @@ pub unsafe fn vluti2q_laneq_s16<const INDEX: i32>(a: int16x8_t, b: uint8x16_t) -
 #[doc = "Lookup table read with 4-bit indices"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_lane_f16_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,lut,fp16")]
 #[cfg_attr(test, assert_instr(nop, LANE = 0))]
@@ -13386,7 +13386,7 @@ pub unsafe fn vluti4q_lane_f16_x2<const LANE: i32>(a: float16x8x2_t, b: uint8x8_
 #[doc = "Lookup table read with 4-bit indices"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_lane_u16_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, LANE = 0))]
@@ -13399,7 +13399,7 @@ pub unsafe fn vluti4q_lane_u16_x2<const LANE: i32>(a: uint16x8x2_t, b: uint8x8_t
 #[doc = "Lookup table read with 4-bit indices"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_lane_p16_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, LANE = 0))]
@@ -13412,7 +13412,7 @@ pub unsafe fn vluti4q_lane_p16_x2<const LANE: i32>(a: poly16x8x2_t, b: uint8x8_t
 #[doc = "Lookup table read with 4-bit indices"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_lane_s16_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, LANE = 0))]
@@ -13432,7 +13432,7 @@ pub unsafe fn vluti4q_lane_s16_x2<const LANE: i32>(a: int16x8x2_t, b: uint8x8_t)
 #[doc = "Lookup table read with 4-bit indices"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_lane_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, LANE = 0))]
@@ -13452,7 +13452,7 @@ pub unsafe fn vluti4q_lane_s8<const LANE: i32>(a: int8x16_t, b: uint8x8_t) -> in
 #[doc = "Lookup table read with 4-bit indices"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_lane_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, LANE = 0))]
@@ -13465,7 +13465,7 @@ pub unsafe fn vluti4q_lane_u8<const LANE: i32>(a: uint8x16_t, b: uint8x8_t) -> u
 #[doc = "Lookup table read with 4-bit indices"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_lane_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, LANE = 0))]
@@ -13478,7 +13478,7 @@ pub unsafe fn vluti4q_lane_p8<const LANE: i32>(a: poly8x16_t, b: uint8x8_t) -> p
 #[doc = "Lookup table read with 4-bit indices"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_laneq_f16_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,lut,fp16")]
 #[cfg_attr(test, assert_instr(nop, LANE = 3))]
@@ -13494,7 +13494,7 @@ pub unsafe fn vluti4q_laneq_f16_x2<const LANE: i32>(
 #[doc = "Lookup table read with 4-bit indices"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_laneq_u16_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, LANE = 3))]
@@ -13507,7 +13507,7 @@ pub unsafe fn vluti4q_laneq_u16_x2<const LANE: i32>(a: uint16x8x2_t, b: uint8x16
 #[doc = "Lookup table read with 4-bit indices"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_laneq_p16_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, LANE = 3))]
@@ -13520,7 +13520,7 @@ pub unsafe fn vluti4q_laneq_p16_x2<const LANE: i32>(a: poly16x8x2_t, b: uint8x16
 #[doc = "Lookup table read with 4-bit indices"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_laneq_s16_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, LANE = 3))]
@@ -13540,7 +13540,7 @@ pub unsafe fn vluti4q_laneq_s16_x2<const LANE: i32>(a: int16x8x2_t, b: uint8x16_
 #[doc = "Lookup table read with 4-bit indices"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_laneq_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, LANE = 0))]
@@ -13560,7 +13560,7 @@ pub unsafe fn vluti4q_laneq_s8<const LANE: i32>(a: int8x16_t, b: uint8x16_t) ->
 #[doc = "Lookup table read with 4-bit indices"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_laneq_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, LANE = 0))]
@@ -13573,7 +13573,7 @@ pub unsafe fn vluti4q_laneq_u8<const LANE: i32>(a: uint8x16_t, b: uint8x16_t) ->
 #[doc = "Lookup table read with 4-bit indices"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vluti4q_laneq_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,lut")]
 #[cfg_attr(test, assert_instr(nop, LANE = 0))]
@@ -25837,7 +25837,7 @@ pub fn vsrid_n_u64<const N: i32>(a: u64, b: u64) -> u64 {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(test, assert_instr(str))]
@@ -25850,7 +25850,7 @@ pub unsafe fn vst1_f16(ptr: *mut f16, a: float16x4_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,fp16")]
 #[cfg_attr(test, assert_instr(str))]
@@ -25863,7 +25863,7 @@ pub unsafe fn vst1q_f16(ptr: *mut f16, a: float16x8_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
@@ -25875,7 +25875,7 @@ pub unsafe fn vst1_f32(ptr: *mut f32, a: float32x2_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
@@ -25887,7 +25887,7 @@ pub unsafe fn vst1q_f32(ptr: *mut f32, a: float32x4_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
@@ -25899,7 +25899,7 @@ pub unsafe fn vst1_f64(ptr: *mut f64, a: float64x1_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
@@ -25911,7 +25911,7 @@ pub unsafe fn vst1q_f64(ptr: *mut f64, a: float64x2_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
@@ -25923,7 +25923,7 @@ pub unsafe fn vst1_s8(ptr: *mut i8, a: int8x8_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
@@ -25935,7 +25935,7 @@ pub unsafe fn vst1q_s8(ptr: *mut i8, a: int8x16_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
@@ -25947,7 +25947,7 @@ pub unsafe fn vst1_s16(ptr: *mut i16, a: int16x4_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
@@ -25959,7 +25959,7 @@ pub unsafe fn vst1q_s16(ptr: *mut i16, a: int16x8_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
@@ -25971,7 +25971,7 @@ pub unsafe fn vst1_s32(ptr: *mut i32, a: int32x2_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
@@ -25983,7 +25983,7 @@ pub unsafe fn vst1q_s32(ptr: *mut i32, a: int32x4_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
@@ -25995,7 +25995,7 @@ pub unsafe fn vst1_s64(ptr: *mut i64, a: int64x1_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
@@ -26007,7 +26007,7 @@ pub unsafe fn vst1q_s64(ptr: *mut i64, a: int64x2_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
@@ -26019,7 +26019,7 @@ pub unsafe fn vst1_u8(ptr: *mut u8, a: uint8x8_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
@@ -26031,7 +26031,7 @@ pub unsafe fn vst1q_u8(ptr: *mut u8, a: uint8x16_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
@@ -26043,7 +26043,7 @@ pub unsafe fn vst1_u16(ptr: *mut u16, a: uint16x4_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
@@ -26055,7 +26055,7 @@ pub unsafe fn vst1q_u16(ptr: *mut u16, a: uint16x8_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
@@ -26067,7 +26067,7 @@ pub unsafe fn vst1_u32(ptr: *mut u32, a: uint32x2_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
@@ -26079,7 +26079,7 @@ pub unsafe fn vst1q_u32(ptr: *mut u32, a: uint32x4_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
@@ -26091,7 +26091,7 @@ pub unsafe fn vst1_u64(ptr: *mut u64, a: uint64x1_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
@@ -26103,7 +26103,7 @@ pub unsafe fn vst1q_u64(ptr: *mut u64, a: uint64x2_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
@@ -26115,7 +26115,7 @@ pub unsafe fn vst1_p8(ptr: *mut p8, a: poly8x8_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
@@ -26127,7 +26127,7 @@ pub unsafe fn vst1q_p8(ptr: *mut p8, a: poly8x16_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
@@ -26139,7 +26139,7 @@ pub unsafe fn vst1_p16(ptr: *mut p16, a: poly16x4_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(str))]
@@ -26151,7 +26151,7 @@ pub unsafe fn vst1q_p16(ptr: *mut p16, a: poly16x8_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(test, assert_instr(str))]
@@ -26163,7 +26163,7 @@ pub unsafe fn vst1_p64(ptr: *mut p64, a: poly64x1_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(test, assert_instr(str))]
@@ -26175,7 +26175,7 @@ pub unsafe fn vst1q_p64(ptr: *mut p64, a: poly64x2_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f64_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st1))]
@@ -26193,7 +26193,7 @@ pub unsafe fn vst1_f64_x2(a: *mut f64, b: float64x1x2_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f64_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st1))]
@@ -26211,7 +26211,7 @@ pub unsafe fn vst1q_f64_x2(a: *mut f64, b: float64x2x2_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f64_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st1))]
@@ -26229,7 +26229,7 @@ pub unsafe fn vst1_f64_x3(a: *mut f64, b: float64x1x3_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f64_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st1))]
@@ -26247,7 +26247,7 @@ pub unsafe fn vst1q_f64_x3(a: *mut f64, b: float64x2x3_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f64_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st1))]
@@ -26271,7 +26271,7 @@ pub unsafe fn vst1_f64_x4(a: *mut f64, b: float64x1x4_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f64_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st1))]
@@ -26295,7 +26295,7 @@ pub unsafe fn vst1q_f64_x4(a: *mut f64, b: float64x2x4_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_f64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(nop, LANE = 0))]
@@ -26308,7 +26308,7 @@ pub unsafe fn vst1_lane_f64<const LANE: i32>(a: *mut f64, b: float64x1_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_f64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(nop, LANE = 0))]
@@ -26321,7 +26321,7 @@ pub unsafe fn vst1q_lane_f64<const LANE: i32>(a: *mut f64, b: float64x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_f64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -26339,7 +26339,7 @@ pub unsafe fn vst2_f64(a: *mut f64, b: float64x1x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_f64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st2, LANE = 0))]
@@ -26359,7 +26359,7 @@ pub unsafe fn vst2_lane_f64<const LANE: i32>(a: *mut f64, b: float64x1x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st2, LANE = 0))]
@@ -26379,7 +26379,7 @@ pub unsafe fn vst2_lane_s64<const LANE: i32>(a: *mut i64, b: int64x1x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_p64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(test, assert_instr(st2, LANE = 0))]
@@ -26392,7 +26392,7 @@ pub unsafe fn vst2_lane_p64<const LANE: i32>(a: *mut p64, b: poly64x1x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_u64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st2, LANE = 0))]
@@ -26405,7 +26405,7 @@ pub unsafe fn vst2_lane_u64<const LANE: i32>(a: *mut u64, b: uint64x1x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_f64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -26423,7 +26423,7 @@ pub unsafe fn vst2q_f64(a: *mut f64, b: float64x2x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -26441,7 +26441,7 @@ pub unsafe fn vst2q_s64(a: *mut i64, b: int64x2x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_f64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st2, LANE = 0))]
@@ -26461,7 +26461,7 @@ pub unsafe fn vst2q_lane_f64<const LANE: i32>(a: *mut f64, b: float64x2x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st2, LANE = 0))]
@@ -26481,7 +26481,7 @@ pub unsafe fn vst2q_lane_s8<const LANE: i32>(a: *mut i8, b: int8x16x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_s64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st2, LANE = 0))]
@@ -26501,7 +26501,7 @@ pub unsafe fn vst2q_lane_s64<const LANE: i32>(a: *mut i64, b: int64x2x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_p64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(test, assert_instr(st2, LANE = 0))]
@@ -26514,7 +26514,7 @@ pub unsafe fn vst2q_lane_p64<const LANE: i32>(a: *mut p64, b: poly64x2x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st2, LANE = 0))]
@@ -26527,7 +26527,7 @@ pub unsafe fn vst2q_lane_u8<const LANE: i32>(a: *mut u8, b: uint8x16x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_u64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st2, LANE = 0))]
@@ -26540,7 +26540,7 @@ pub unsafe fn vst2q_lane_u64<const LANE: i32>(a: *mut u64, b: uint64x2x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st2, LANE = 0))]
@@ -26553,7 +26553,7 @@ pub unsafe fn vst2q_lane_p8<const LANE: i32>(a: *mut p8, b: poly8x16x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_p64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(test, assert_instr(st2))]
@@ -26564,7 +26564,7 @@ pub unsafe fn vst2q_p64(a: *mut p64, b: poly64x2x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_u64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -26575,7 +26575,7 @@ pub unsafe fn vst2q_u64(a: *mut u64, b: uint64x2x2_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_f64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -26593,7 +26593,7 @@ pub unsafe fn vst3_f64(a: *mut f64, b: float64x1x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_f64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st3, LANE = 0))]
@@ -26613,7 +26613,7 @@ pub unsafe fn vst3_lane_f64<const LANE: i32>(a: *mut f64, b: float64x1x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st3, LANE = 0))]
@@ -26633,7 +26633,7 @@ pub unsafe fn vst3_lane_s64<const LANE: i32>(a: *mut i64, b: int64x1x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_p64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[target_feature(enable = "neon,aes")]
@@ -26646,7 +26646,7 @@ pub unsafe fn vst3_lane_p64<const LANE: i32>(a: *mut p64, b: poly64x1x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_u64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -26659,7 +26659,7 @@ pub unsafe fn vst3_lane_u64<const LANE: i32>(a: *mut u64, b: uint64x1x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_f64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -26677,7 +26677,7 @@ pub unsafe fn vst3q_f64(a: *mut f64, b: float64x2x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -26695,7 +26695,7 @@ pub unsafe fn vst3q_s64(a: *mut i64, b: int64x2x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_f64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st3, LANE = 0))]
@@ -26715,7 +26715,7 @@ pub unsafe fn vst3q_lane_f64<const LANE: i32>(a: *mut f64, b: float64x2x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st3, LANE = 0))]
@@ -26735,7 +26735,7 @@ pub unsafe fn vst3q_lane_s8<const LANE: i32>(a: *mut i8, b: int8x16x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_s64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st3, LANE = 0))]
@@ -26755,7 +26755,7 @@ pub unsafe fn vst3q_lane_s64<const LANE: i32>(a: *mut i64, b: int64x2x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_p64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[target_feature(enable = "neon,aes")]
@@ -26768,7 +26768,7 @@ pub unsafe fn vst3q_lane_p64<const LANE: i32>(a: *mut p64, b: poly64x2x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -26781,7 +26781,7 @@ pub unsafe fn vst3q_lane_u8<const LANE: i32>(a: *mut u8, b: uint8x16x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_u64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -26794,7 +26794,7 @@ pub unsafe fn vst3q_lane_u64<const LANE: i32>(a: *mut u64, b: uint64x2x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -26807,7 +26807,7 @@ pub unsafe fn vst3q_lane_p8<const LANE: i32>(a: *mut p8, b: poly8x16x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_p64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[target_feature(enable = "neon,aes")]
@@ -26818,7 +26818,7 @@ pub unsafe fn vst3q_p64(a: *mut p64, b: poly64x2x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_u64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -26829,7 +26829,7 @@ pub unsafe fn vst3q_u64(a: *mut u64, b: uint64x2x3_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_f64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -26847,7 +26847,7 @@ pub unsafe fn vst4_f64(a: *mut f64, b: float64x1x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_f64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st4, LANE = 0))]
@@ -26874,7 +26874,7 @@ pub unsafe fn vst4_lane_f64<const LANE: i32>(a: *mut f64, b: float64x1x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st4, LANE = 0))]
@@ -26901,7 +26901,7 @@ pub unsafe fn vst4_lane_s64<const LANE: i32>(a: *mut i64, b: int64x1x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_p64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[target_feature(enable = "neon,aes")]
@@ -26914,7 +26914,7 @@ pub unsafe fn vst4_lane_p64<const LANE: i32>(a: *mut p64, b: poly64x1x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_u64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -26927,7 +26927,7 @@ pub unsafe fn vst4_lane_u64<const LANE: i32>(a: *mut u64, b: uint64x1x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_f64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -26945,7 +26945,7 @@ pub unsafe fn vst4q_f64(a: *mut f64, b: float64x2x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -26963,7 +26963,7 @@ pub unsafe fn vst4q_s64(a: *mut i64, b: int64x2x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_f64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st4, LANE = 0))]
@@ -26990,7 +26990,7 @@ pub unsafe fn vst4q_lane_f64<const LANE: i32>(a: *mut f64, b: float64x2x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st4, LANE = 0))]
@@ -27017,7 +27017,7 @@ pub unsafe fn vst4q_lane_s8<const LANE: i32>(a: *mut i8, b: int8x16x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_s64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(test, assert_instr(st4, LANE = 0))]
@@ -27044,7 +27044,7 @@ pub unsafe fn vst4q_lane_s64<const LANE: i32>(a: *mut i64, b: int64x2x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_p64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[target_feature(enable = "neon,aes")]
@@ -27057,7 +27057,7 @@ pub unsafe fn vst4q_lane_p64<const LANE: i32>(a: *mut p64, b: poly64x2x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -27070,7 +27070,7 @@ pub unsafe fn vst4q_lane_u8<const LANE: i32>(a: *mut u8, b: uint8x16x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_u64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -27083,7 +27083,7 @@ pub unsafe fn vst4q_lane_u64<const LANE: i32>(a: *mut u64, b: uint64x2x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -27096,7 +27096,7 @@ pub unsafe fn vst4q_lane_p8<const LANE: i32>(a: *mut p8, b: poly8x16x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_p64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[target_feature(enable = "neon,aes")]
@@ -27107,7 +27107,7 @@ pub unsafe fn vst4q_p64(a: *mut p64, b: poly64x2x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_u64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
diff --git a/library/stdarch/crates/core_arch/src/arm_shared/neon/generated.rs b/library/stdarch/crates/core_arch/src/arm_shared/neon/generated.rs
index ac3b649fbf2d..5a415acc0c70 100644
--- a/library/stdarch/crates/core_arch/src/arm_shared/neon/generated.rs
+++ b/library/stdarch/crates/core_arch/src/arm_shared/neon/generated.rs
@@ -12370,7 +12370,7 @@ pub fn vext_u32<const N: i32>(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
 #[doc = "Extract vector from pair of vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_s64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -12395,7 +12395,7 @@ pub unsafe fn vext_s64<const N: i32>(a: int64x1_t, _b: int64x1_t) -> int64x1_t {
 #[doc = "Extract vector from pair of vectors"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_u64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -15133,7 +15133,7 @@ pub fn vhsubq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 #[doc = "Load one single-element structure and replicate to all lanes of one register"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -15152,7 +15152,7 @@ pub unsafe fn vld1_dup_f16(ptr: *const f16) -> float16x4_t {
 #[doc = "Load one single-element structure and replicate to all lanes of one register"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -15171,7 +15171,7 @@ pub unsafe fn vld1q_dup_f16(ptr: *const f16) -> float16x8_t {
 #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -15194,7 +15194,7 @@ pub unsafe fn vld1_dup_f32(ptr: *const f32) -> float32x2_t {
 #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -15217,7 +15217,7 @@ pub unsafe fn vld1_dup_p16(ptr: *const p16) -> poly16x4_t {
 #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -15240,7 +15240,7 @@ pub unsafe fn vld1_dup_p8(ptr: *const p8) -> poly8x8_t {
 #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -15263,7 +15263,7 @@ pub unsafe fn vld1_dup_s16(ptr: *const i16) -> int16x4_t {
 #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -15286,7 +15286,7 @@ pub unsafe fn vld1_dup_s32(ptr: *const i32) -> int32x2_t {
 #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -15309,7 +15309,7 @@ pub unsafe fn vld1_dup_s8(ptr: *const i8) -> int8x8_t {
 #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -15332,7 +15332,7 @@ pub unsafe fn vld1_dup_u16(ptr: *const u16) -> uint16x4_t {
 #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_u32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -15355,7 +15355,7 @@ pub unsafe fn vld1_dup_u32(ptr: *const u32) -> uint32x2_t {
 #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -15378,7 +15378,7 @@ pub unsafe fn vld1_dup_u8(ptr: *const u8) -> uint8x8_t {
 #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -15401,7 +15401,7 @@ pub unsafe fn vld1q_dup_f32(ptr: *const f32) -> float32x4_t {
 #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -15424,7 +15424,7 @@ pub unsafe fn vld1q_dup_p16(ptr: *const p16) -> poly16x8_t {
 #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -15447,7 +15447,7 @@ pub unsafe fn vld1q_dup_p8(ptr: *const p8) -> poly8x16_t {
 #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -15470,7 +15470,7 @@ pub unsafe fn vld1q_dup_s16(ptr: *const i16) -> int16x8_t {
 #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -15493,7 +15493,7 @@ pub unsafe fn vld1q_dup_s32(ptr: *const i32) -> int32x4_t {
 #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_s64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -15516,7 +15516,7 @@ pub unsafe fn vld1q_dup_s64(ptr: *const i64) -> int64x2_t {
 #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -15539,7 +15539,7 @@ pub unsafe fn vld1q_dup_s8(ptr: *const i8) -> int8x16_t {
 #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -15562,7 +15562,7 @@ pub unsafe fn vld1q_dup_u16(ptr: *const u16) -> uint16x8_t {
 #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_u32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -15585,7 +15585,7 @@ pub unsafe fn vld1q_dup_u32(ptr: *const u32) -> uint32x4_t {
 #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_u64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -15608,7 +15608,7 @@ pub unsafe fn vld1q_dup_u64(ptr: *const u64) -> uint64x2_t {
 #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -15631,7 +15631,7 @@ pub unsafe fn vld1q_dup_u8(ptr: *const u8) -> uint8x16_t {
 #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_p64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -15663,7 +15663,7 @@ pub unsafe fn vld1_dup_p64(ptr: *const p64) -> poly64x1_t {
 #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_s64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -15695,7 +15695,7 @@ pub unsafe fn vld1_dup_s64(ptr: *const i64) -> int64x1_t {
 #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_u64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -15727,7 +15727,7 @@ pub unsafe fn vld1_dup_u64(ptr: *const u64) -> uint64x1_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg(target_arch = "arm")]
@@ -15745,7 +15745,7 @@ pub unsafe fn vld1_f16(ptr: *const f16) -> float16x4_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg(target_arch = "arm")]
@@ -15764,7 +15764,7 @@ pub unsafe fn vld1_f16(ptr: *const f16) -> float16x4_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[cfg(target_arch = "arm")]
@@ -15782,7 +15782,7 @@ pub unsafe fn vld1q_f16(ptr: *const f16) -> float16x8_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[cfg(target_arch = "arm")]
@@ -15801,7 +15801,7 @@ pub unsafe fn vld1q_f16(ptr: *const f16) -> float16x8_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f16_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -15827,7 +15827,7 @@ pub unsafe fn vld1_f16_x2(a: *const f16) -> float16x4x2_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f16_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -15853,7 +15853,7 @@ pub unsafe fn vld1_f16_x3(a: *const f16) -> float16x4x3_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f16_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -15879,7 +15879,7 @@ pub unsafe fn vld1_f16_x4(a: *const f16) -> float16x4x4_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f16_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -15905,7 +15905,7 @@ pub unsafe fn vld1q_f16_x2(a: *const f16) -> float16x8x2_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f16_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -15931,7 +15931,7 @@ pub unsafe fn vld1q_f16_x3(a: *const f16) -> float16x8x3_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f16_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -15957,7 +15957,7 @@ pub unsafe fn vld1q_f16_x4(a: *const f16) -> float16x8x4_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -15970,7 +15970,7 @@ pub unsafe fn vld1_f32(ptr: *const f32) -> float32x2_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -15983,7 +15983,7 @@ pub unsafe fn vld1q_f32(ptr: *const f32) -> float32x4_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -15996,7 +15996,7 @@ pub unsafe fn vld1_u8(ptr: *const u8) -> uint8x8_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -16009,7 +16009,7 @@ pub unsafe fn vld1q_u8(ptr: *const u8) -> uint8x16_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -16022,7 +16022,7 @@ pub unsafe fn vld1_u16(ptr: *const u16) -> uint16x4_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -16035,7 +16035,7 @@ pub unsafe fn vld1q_u16(ptr: *const u16) -> uint16x8_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -16048,7 +16048,7 @@ pub unsafe fn vld1_u32(ptr: *const u32) -> uint32x2_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -16061,7 +16061,7 @@ pub unsafe fn vld1q_u32(ptr: *const u32) -> uint32x4_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -16074,7 +16074,7 @@ pub unsafe fn vld1_u64(ptr: *const u64) -> uint64x1_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -16087,7 +16087,7 @@ pub unsafe fn vld1q_u64(ptr: *const u64) -> uint64x2_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -16100,7 +16100,7 @@ pub unsafe fn vld1_p8(ptr: *const p8) -> poly8x8_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -16113,7 +16113,7 @@ pub unsafe fn vld1q_p8(ptr: *const p8) -> poly8x16_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -16126,7 +16126,7 @@ pub unsafe fn vld1_p16(ptr: *const p16) -> poly16x4_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -16139,7 +16139,7 @@ pub unsafe fn vld1q_p16(ptr: *const p16) -> poly16x8_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,aes")]
@@ -16152,7 +16152,7 @@ pub unsafe fn vld1q_p64(ptr: *const p64) -> poly64x2_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f32_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -16183,7 +16183,7 @@ pub unsafe fn vld1_f32_x2(a: *const f32) -> float32x2x2_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f32_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -16214,7 +16214,7 @@ pub unsafe fn vld1_f32_x3(a: *const f32) -> float32x2x3_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f32_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -16245,7 +16245,7 @@ pub unsafe fn vld1_f32_x4(a: *const f32) -> float32x2x4_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f32_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -16276,7 +16276,7 @@ pub unsafe fn vld1q_f32_x2(a: *const f32) -> float32x4x2_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f32_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -16307,7 +16307,7 @@ pub unsafe fn vld1q_f32_x3(a: *const f32) -> float32x4x3_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f32_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -16338,7 +16338,7 @@ pub unsafe fn vld1q_f32_x4(a: *const f32) -> float32x4x4_t {
 #[doc = "Load one single-element structure to one lane of one register"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -16358,7 +16358,7 @@ pub unsafe fn vld1_lane_f16<const LANE: i32>(ptr: *const f16, src: float16x4_t)
 #[doc = "Load one single-element structure to one lane of one register"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -16378,7 +16378,7 @@ pub unsafe fn vld1q_lane_f16<const LANE: i32>(ptr: *const f16, src: float16x8_t)
 #[doc = "Load one single-element structure to one lane of one register."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -16403,7 +16403,7 @@ pub unsafe fn vld1_lane_f32<const LANE: i32>(ptr: *const f32, src: float32x2_t)
 #[doc = "Load one single-element structure to one lane of one register."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -16428,7 +16428,7 @@ pub unsafe fn vld1_lane_p16<const LANE: i32>(ptr: *const p16, src: poly16x4_t) -
 #[doc = "Load one single-element structure to one lane of one register."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -16453,7 +16453,7 @@ pub unsafe fn vld1_lane_p8<const LANE: i32>(ptr: *const p8, src: poly8x8_t) -> p
 #[doc = "Load one single-element structure to one lane of one register."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -16478,7 +16478,7 @@ pub unsafe fn vld1_lane_s16<const LANE: i32>(ptr: *const i16, src: int16x4_t) ->
 #[doc = "Load one single-element structure to one lane of one register."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -16503,7 +16503,7 @@ pub unsafe fn vld1_lane_s32<const LANE: i32>(ptr: *const i32, src: int32x2_t) ->
 #[doc = "Load one single-element structure to one lane of one register."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_s64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -16528,7 +16528,7 @@ pub unsafe fn vld1_lane_s64<const LANE: i32>(ptr: *const i64, src: int64x1_t) ->
 #[doc = "Load one single-element structure to one lane of one register."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -16553,7 +16553,7 @@ pub unsafe fn vld1_lane_s8<const LANE: i32>(ptr: *const i8, src: int8x8_t) -> in
 #[doc = "Load one single-element structure to one lane of one register."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -16578,7 +16578,7 @@ pub unsafe fn vld1_lane_u16<const LANE: i32>(ptr: *const u16, src: uint16x4_t) -
 #[doc = "Load one single-element structure to one lane of one register."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_u32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -16603,7 +16603,7 @@ pub unsafe fn vld1_lane_u32<const LANE: i32>(ptr: *const u32, src: uint32x2_t) -
 #[doc = "Load one single-element structure to one lane of one register."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_u64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -16628,7 +16628,7 @@ pub unsafe fn vld1_lane_u64<const LANE: i32>(ptr: *const u64, src: uint64x1_t) -
 #[doc = "Load one single-element structure to one lane of one register."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -16653,7 +16653,7 @@ pub unsafe fn vld1_lane_u8<const LANE: i32>(ptr: *const u8, src: uint8x8_t) -> u
 #[doc = "Load one single-element structure to one lane of one register."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -16678,7 +16678,7 @@ pub unsafe fn vld1q_lane_f32<const LANE: i32>(ptr: *const f32, src: float32x4_t)
 #[doc = "Load one single-element structure to one lane of one register."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -16703,7 +16703,7 @@ pub unsafe fn vld1q_lane_p16<const LANE: i32>(ptr: *const p16, src: poly16x8_t)
 #[doc = "Load one single-element structure to one lane of one register."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -16728,7 +16728,7 @@ pub unsafe fn vld1q_lane_p8<const LANE: i32>(ptr: *const p8, src: poly8x16_t) ->
 #[doc = "Load one single-element structure to one lane of one register."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -16753,7 +16753,7 @@ pub unsafe fn vld1q_lane_s16<const LANE: i32>(ptr: *const i16, src: int16x8_t) -
 #[doc = "Load one single-element structure to one lane of one register."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -16778,7 +16778,7 @@ pub unsafe fn vld1q_lane_s32<const LANE: i32>(ptr: *const i32, src: int32x4_t) -
 #[doc = "Load one single-element structure to one lane of one register."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_s64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -16803,7 +16803,7 @@ pub unsafe fn vld1q_lane_s64<const LANE: i32>(ptr: *const i64, src: int64x2_t) -
 #[doc = "Load one single-element structure to one lane of one register."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -16828,7 +16828,7 @@ pub unsafe fn vld1q_lane_s8<const LANE: i32>(ptr: *const i8, src: int8x16_t) ->
 #[doc = "Load one single-element structure to one lane of one register."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -16853,7 +16853,7 @@ pub unsafe fn vld1q_lane_u16<const LANE: i32>(ptr: *const u16, src: uint16x8_t)
 #[doc = "Load one single-element structure to one lane of one register."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_u32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -16878,7 +16878,7 @@ pub unsafe fn vld1q_lane_u32<const LANE: i32>(ptr: *const u32, src: uint32x4_t)
 #[doc = "Load one single-element structure to one lane of one register."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_u64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -16903,7 +16903,7 @@ pub unsafe fn vld1q_lane_u64<const LANE: i32>(ptr: *const u64, src: uint64x2_t)
 #[doc = "Load one single-element structure to one lane of one register."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -16928,7 +16928,7 @@ pub unsafe fn vld1q_lane_u8<const LANE: i32>(ptr: *const u8, src: uint8x16_t) ->
 #[doc = "Load one single-element structure to one lane of one register."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_p64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -16953,7 +16953,7 @@ pub unsafe fn vld1_lane_p64<const LANE: i32>(ptr: *const p64, src: poly64x1_t) -
 #[doc = "Load one single-element structure to one lane of one register."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_p64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -16978,7 +16978,7 @@ pub unsafe fn vld1q_lane_p64<const LANE: i32>(ptr: *const p64, src: poly64x2_t)
 #[doc = "Load multiple single-element structures to one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,aes")]
@@ -16996,7 +16996,7 @@ pub unsafe fn vld1_p64(ptr: *const p64) -> poly64x1_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p64_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -17019,7 +17019,7 @@ pub unsafe fn vld1_p64_x2(a: *const p64) -> poly64x1x2_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p64_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -17042,7 +17042,7 @@ pub unsafe fn vld1_p64_x3(a: *const p64) -> poly64x1x3_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p64_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -17065,7 +17065,7 @@ pub unsafe fn vld1_p64_x4(a: *const p64) -> poly64x1x4_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
@@ -17089,7 +17089,7 @@ pub unsafe fn vld1q_p64_x2(a: *const p64) -> poly64x2x2_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
@@ -17116,7 +17116,7 @@ pub unsafe fn vld1q_p64_x2(a: *const p64) -> poly64x2x2_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
@@ -17140,7 +17140,7 @@ pub unsafe fn vld1q_p64_x3(a: *const p64) -> poly64x2x3_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
@@ -17168,7 +17168,7 @@ pub unsafe fn vld1q_p64_x3(a: *const p64) -> poly64x2x3_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon,aes")]
@@ -17192,7 +17192,7 @@ pub unsafe fn vld1q_p64_x4(a: *const p64) -> poly64x2x4_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon,aes")]
@@ -17221,7 +17221,7 @@ pub unsafe fn vld1q_p64_x4(a: *const p64) -> poly64x2x4_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -17234,7 +17234,7 @@ pub unsafe fn vld1_s8(ptr: *const i8) -> int8x8_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -17247,7 +17247,7 @@ pub unsafe fn vld1q_s8(ptr: *const i8) -> int8x16_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -17260,7 +17260,7 @@ pub unsafe fn vld1_s16(ptr: *const i16) -> int16x4_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -17273,7 +17273,7 @@ pub unsafe fn vld1q_s16(ptr: *const i16) -> int16x8_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -17286,7 +17286,7 @@ pub unsafe fn vld1_s32(ptr: *const i32) -> int32x2_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -17299,7 +17299,7 @@ pub unsafe fn vld1q_s32(ptr: *const i32) -> int32x4_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -17312,7 +17312,7 @@ pub unsafe fn vld1_s64(ptr: *const i64) -> int64x1_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -17325,7 +17325,7 @@ pub unsafe fn vld1q_s64(ptr: *const i64) -> int64x2_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s8_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -17356,7 +17356,7 @@ pub unsafe fn vld1_s8_x2(a: *const i8) -> int8x8x2_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s8_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -17387,7 +17387,7 @@ pub unsafe fn vld1_s8_x3(a: *const i8) -> int8x8x3_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s8_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -17418,7 +17418,7 @@ pub unsafe fn vld1_s8_x4(a: *const i8) -> int8x8x4_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s8_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -17449,7 +17449,7 @@ pub unsafe fn vld1q_s8_x2(a: *const i8) -> int8x16x2_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s8_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -17480,7 +17480,7 @@ pub unsafe fn vld1q_s8_x3(a: *const i8) -> int8x16x3_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s8_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -17511,7 +17511,7 @@ pub unsafe fn vld1q_s8_x4(a: *const i8) -> int8x16x4_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s16_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -17542,7 +17542,7 @@ pub unsafe fn vld1_s16_x2(a: *const i16) -> int16x4x2_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s16_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -17573,7 +17573,7 @@ pub unsafe fn vld1_s16_x3(a: *const i16) -> int16x4x3_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s16_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -17604,7 +17604,7 @@ pub unsafe fn vld1_s16_x4(a: *const i16) -> int16x4x4_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s16_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -17635,7 +17635,7 @@ pub unsafe fn vld1q_s16_x2(a: *const i16) -> int16x8x2_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s16_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -17666,7 +17666,7 @@ pub unsafe fn vld1q_s16_x3(a: *const i16) -> int16x8x3_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s16_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -17697,7 +17697,7 @@ pub unsafe fn vld1q_s16_x4(a: *const i16) -> int16x8x4_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s32_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -17728,7 +17728,7 @@ pub unsafe fn vld1_s32_x2(a: *const i32) -> int32x2x2_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s32_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -17759,7 +17759,7 @@ pub unsafe fn vld1_s32_x3(a: *const i32) -> int32x2x3_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s32_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -17790,7 +17790,7 @@ pub unsafe fn vld1_s32_x4(a: *const i32) -> int32x2x4_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s32_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -17821,7 +17821,7 @@ pub unsafe fn vld1q_s32_x2(a: *const i32) -> int32x4x2_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s32_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -17852,7 +17852,7 @@ pub unsafe fn vld1q_s32_x3(a: *const i32) -> int32x4x3_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s32_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -17883,7 +17883,7 @@ pub unsafe fn vld1q_s32_x4(a: *const i32) -> int32x4x4_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s64_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -17914,7 +17914,7 @@ pub unsafe fn vld1_s64_x2(a: *const i64) -> int64x1x2_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s64_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -17945,7 +17945,7 @@ pub unsafe fn vld1_s64_x3(a: *const i64) -> int64x1x3_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s64_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -17976,7 +17976,7 @@ pub unsafe fn vld1_s64_x4(a: *const i64) -> int64x1x4_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s64_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -18007,7 +18007,7 @@ pub unsafe fn vld1q_s64_x2(a: *const i64) -> int64x2x2_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s64_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -18038,7 +18038,7 @@ pub unsafe fn vld1q_s64_x3(a: *const i64) -> int64x2x3_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s64_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -18069,7 +18069,7 @@ pub unsafe fn vld1q_s64_x4(a: *const i64) -> int64x2x4_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -18093,7 +18093,7 @@ pub unsafe fn vld1_u8_x2(a: *const u8) -> uint8x8x2_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -18120,7 +18120,7 @@ pub unsafe fn vld1_u8_x2(a: *const u8) -> uint8x8x2_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -18144,7 +18144,7 @@ pub unsafe fn vld1_u8_x3(a: *const u8) -> uint8x8x3_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -18172,7 +18172,7 @@ pub unsafe fn vld1_u8_x3(a: *const u8) -> uint8x8x3_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -18196,7 +18196,7 @@ pub unsafe fn vld1_u8_x4(a: *const u8) -> uint8x8x4_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -18225,7 +18225,7 @@ pub unsafe fn vld1_u8_x4(a: *const u8) -> uint8x8x4_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -18249,7 +18249,7 @@ pub unsafe fn vld1q_u8_x2(a: *const u8) -> uint8x16x2_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -18288,7 +18288,7 @@ pub unsafe fn vld1q_u8_x2(a: *const u8) -> uint8x16x2_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -18312,7 +18312,7 @@ pub unsafe fn vld1q_u8_x3(a: *const u8) -> uint8x16x3_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -18358,7 +18358,7 @@ pub unsafe fn vld1q_u8_x3(a: *const u8) -> uint8x16x3_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -18382,7 +18382,7 @@ pub unsafe fn vld1q_u8_x4(a: *const u8) -> uint8x16x4_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -18435,7 +18435,7 @@ pub unsafe fn vld1q_u8_x4(a: *const u8) -> uint8x16x4_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -18459,7 +18459,7 @@ pub unsafe fn vld1_u16_x2(a: *const u16) -> uint16x4x2_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -18486,7 +18486,7 @@ pub unsafe fn vld1_u16_x2(a: *const u16) -> uint16x4x2_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -18510,7 +18510,7 @@ pub unsafe fn vld1_u16_x3(a: *const u16) -> uint16x4x3_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -18538,7 +18538,7 @@ pub unsafe fn vld1_u16_x3(a: *const u16) -> uint16x4x3_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -18562,7 +18562,7 @@ pub unsafe fn vld1_u16_x4(a: *const u16) -> uint16x4x4_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -18591,7 +18591,7 @@ pub unsafe fn vld1_u16_x4(a: *const u16) -> uint16x4x4_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -18615,7 +18615,7 @@ pub unsafe fn vld1q_u16_x2(a: *const u16) -> uint16x8x2_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -18642,7 +18642,7 @@ pub unsafe fn vld1q_u16_x2(a: *const u16) -> uint16x8x2_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -18666,7 +18666,7 @@ pub unsafe fn vld1q_u16_x3(a: *const u16) -> uint16x8x3_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -18694,7 +18694,7 @@ pub unsafe fn vld1q_u16_x3(a: *const u16) -> uint16x8x3_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -18718,7 +18718,7 @@ pub unsafe fn vld1q_u16_x4(a: *const u16) -> uint16x8x4_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -18747,7 +18747,7 @@ pub unsafe fn vld1q_u16_x4(a: *const u16) -> uint16x8x4_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -18771,7 +18771,7 @@ pub unsafe fn vld1_u32_x2(a: *const u32) -> uint32x2x2_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -18798,7 +18798,7 @@ pub unsafe fn vld1_u32_x2(a: *const u32) -> uint32x2x2_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -18822,7 +18822,7 @@ pub unsafe fn vld1_u32_x3(a: *const u32) -> uint32x2x3_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -18850,7 +18850,7 @@ pub unsafe fn vld1_u32_x3(a: *const u32) -> uint32x2x3_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -18874,7 +18874,7 @@ pub unsafe fn vld1_u32_x4(a: *const u32) -> uint32x2x4_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -18903,7 +18903,7 @@ pub unsafe fn vld1_u32_x4(a: *const u32) -> uint32x2x4_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -18927,7 +18927,7 @@ pub unsafe fn vld1q_u32_x2(a: *const u32) -> uint32x4x2_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -18954,7 +18954,7 @@ pub unsafe fn vld1q_u32_x2(a: *const u32) -> uint32x4x2_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -18978,7 +18978,7 @@ pub unsafe fn vld1q_u32_x3(a: *const u32) -> uint32x4x3_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -19006,7 +19006,7 @@ pub unsafe fn vld1q_u32_x3(a: *const u32) -> uint32x4x3_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -19030,7 +19030,7 @@ pub unsafe fn vld1q_u32_x4(a: *const u32) -> uint32x4x4_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -19059,7 +19059,7 @@ pub unsafe fn vld1q_u32_x4(a: *const u32) -> uint32x4x4_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u64_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -19082,7 +19082,7 @@ pub unsafe fn vld1_u64_x2(a: *const u64) -> uint64x1x2_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u64_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -19105,7 +19105,7 @@ pub unsafe fn vld1_u64_x3(a: *const u64) -> uint64x1x3_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u64_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -19128,7 +19128,7 @@ pub unsafe fn vld1_u64_x4(a: *const u64) -> uint64x1x4_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -19152,7 +19152,7 @@ pub unsafe fn vld1q_u64_x2(a: *const u64) -> uint64x2x2_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -19179,7 +19179,7 @@ pub unsafe fn vld1q_u64_x2(a: *const u64) -> uint64x2x2_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -19203,7 +19203,7 @@ pub unsafe fn vld1q_u64_x3(a: *const u64) -> uint64x2x3_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -19231,7 +19231,7 @@ pub unsafe fn vld1q_u64_x3(a: *const u64) -> uint64x2x3_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -19255,7 +19255,7 @@ pub unsafe fn vld1q_u64_x4(a: *const u64) -> uint64x2x4_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -19284,7 +19284,7 @@ pub unsafe fn vld1q_u64_x4(a: *const u64) -> uint64x2x4_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -19308,7 +19308,7 @@ pub unsafe fn vld1_p8_x2(a: *const p8) -> poly8x8x2_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -19335,7 +19335,7 @@ pub unsafe fn vld1_p8_x2(a: *const p8) -> poly8x8x2_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -19359,7 +19359,7 @@ pub unsafe fn vld1_p8_x3(a: *const p8) -> poly8x8x3_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -19387,7 +19387,7 @@ pub unsafe fn vld1_p8_x3(a: *const p8) -> poly8x8x3_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -19411,7 +19411,7 @@ pub unsafe fn vld1_p8_x4(a: *const p8) -> poly8x8x4_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -19440,7 +19440,7 @@ pub unsafe fn vld1_p8_x4(a: *const p8) -> poly8x8x4_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -19464,7 +19464,7 @@ pub unsafe fn vld1q_p8_x2(a: *const p8) -> poly8x16x2_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -19503,7 +19503,7 @@ pub unsafe fn vld1q_p8_x2(a: *const p8) -> poly8x16x2_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -19527,7 +19527,7 @@ pub unsafe fn vld1q_p8_x3(a: *const p8) -> poly8x16x3_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -19573,7 +19573,7 @@ pub unsafe fn vld1q_p8_x3(a: *const p8) -> poly8x16x3_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -19597,7 +19597,7 @@ pub unsafe fn vld1q_p8_x4(a: *const p8) -> poly8x16x4_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -19650,7 +19650,7 @@ pub unsafe fn vld1q_p8_x4(a: *const p8) -> poly8x16x4_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -19674,7 +19674,7 @@ pub unsafe fn vld1_p16_x2(a: *const p16) -> poly16x4x2_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -19701,7 +19701,7 @@ pub unsafe fn vld1_p16_x2(a: *const p16) -> poly16x4x2_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -19725,7 +19725,7 @@ pub unsafe fn vld1_p16_x3(a: *const p16) -> poly16x4x3_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -19753,7 +19753,7 @@ pub unsafe fn vld1_p16_x3(a: *const p16) -> poly16x4x3_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -19777,7 +19777,7 @@ pub unsafe fn vld1_p16_x4(a: *const p16) -> poly16x4x4_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -19806,7 +19806,7 @@ pub unsafe fn vld1_p16_x4(a: *const p16) -> poly16x4x4_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -19830,7 +19830,7 @@ pub unsafe fn vld1q_p16_x2(a: *const p16) -> poly16x8x2_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -19857,7 +19857,7 @@ pub unsafe fn vld1q_p16_x2(a: *const p16) -> poly16x8x2_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -19881,7 +19881,7 @@ pub unsafe fn vld1q_p16_x3(a: *const p16) -> poly16x8x3_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -19909,7 +19909,7 @@ pub unsafe fn vld1q_p16_x3(a: *const p16) -> poly16x8x3_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -19933,7 +19933,7 @@ pub unsafe fn vld1q_p16_x4(a: *const p16) -> poly16x8x4_t {
 #[doc = "Load multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -20120,7 +20120,7 @@ unsafe fn vld1q_v8f16(a: *const i8, b: i32) -> float16x8_t {
 #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_p64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -20144,7 +20144,7 @@ pub unsafe fn vld1q_dup_p64(ptr: *const p64) -> poly64x2_t {
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -20163,7 +20163,7 @@ pub unsafe fn vld2_dup_f16(a: *const f16) -> float16x4x2_t {
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -20182,7 +20182,7 @@ pub unsafe fn vld2q_dup_f16(a: *const f16) -> float16x8x2_t {
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -20206,7 +20206,7 @@ pub unsafe fn vld2_dup_f16(a: *const f16) -> float16x4x2_t {
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -20230,7 +20230,7 @@ pub unsafe fn vld2q_dup_f16(a: *const f16) -> float16x8x2_t {
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -20246,7 +20246,7 @@ pub unsafe fn vld2_dup_f32(a: *const f32) -> float32x2x2_t {
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -20262,7 +20262,7 @@ pub unsafe fn vld2q_dup_f32(a: *const f32) -> float32x4x2_t {
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -20278,7 +20278,7 @@ pub unsafe fn vld2_dup_s8(a: *const i8) -> int8x8x2_t {
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -20294,7 +20294,7 @@ pub unsafe fn vld2q_dup_s8(a: *const i8) -> int8x16x2_t {
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -20310,7 +20310,7 @@ pub unsafe fn vld2_dup_s16(a: *const i16) -> int16x4x2_t {
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -20326,7 +20326,7 @@ pub unsafe fn vld2q_dup_s16(a: *const i16) -> int16x8x2_t {
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -20342,7 +20342,7 @@ pub unsafe fn vld2_dup_s32(a: *const i32) -> int32x2x2_t {
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -20358,7 +20358,7 @@ pub unsafe fn vld2q_dup_s32(a: *const i32) -> int32x4x2_t {
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -20377,7 +20377,7 @@ pub unsafe fn vld2_dup_f32(a: *const f32) -> float32x2x2_t {
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -20396,7 +20396,7 @@ pub unsafe fn vld2q_dup_f32(a: *const f32) -> float32x4x2_t {
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -20415,7 +20415,7 @@ pub unsafe fn vld2_dup_s8(a: *const i8) -> int8x8x2_t {
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -20434,7 +20434,7 @@ pub unsafe fn vld2q_dup_s8(a: *const i8) -> int8x16x2_t {
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -20453,7 +20453,7 @@ pub unsafe fn vld2_dup_s16(a: *const i16) -> int16x4x2_t {
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -20472,7 +20472,7 @@ pub unsafe fn vld2q_dup_s16(a: *const i16) -> int16x8x2_t {
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -20491,7 +20491,7 @@ pub unsafe fn vld2_dup_s32(a: *const i32) -> int32x2x2_t {
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -20510,7 +20510,7 @@ pub unsafe fn vld2q_dup_s32(a: *const i32) -> int32x4x2_t {
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_p64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -20533,7 +20533,7 @@ pub unsafe fn vld2_dup_p64(a: *const p64) -> poly64x1x2_t {
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -20549,7 +20549,7 @@ pub unsafe fn vld2_dup_s64(a: *const i64) -> int64x1x2_t {
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -20568,7 +20568,7 @@ pub unsafe fn vld2_dup_s64(a: *const i64) -> int64x1x2_t {
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -20591,7 +20591,7 @@ pub unsafe fn vld2_dup_u64(a: *const u64) -> uint64x1x2_t {
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -20615,7 +20615,7 @@ pub unsafe fn vld2_dup_u8(a: *const u8) -> uint8x8x2_t {
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -20642,7 +20642,7 @@ pub unsafe fn vld2_dup_u8(a: *const u8) -> uint8x8x2_t {
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -20666,7 +20666,7 @@ pub unsafe fn vld2q_dup_u8(a: *const u8) -> uint8x16x2_t {
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -20705,7 +20705,7 @@ pub unsafe fn vld2q_dup_u8(a: *const u8) -> uint8x16x2_t {
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -20729,7 +20729,7 @@ pub unsafe fn vld2_dup_u16(a: *const u16) -> uint16x4x2_t {
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -20756,7 +20756,7 @@ pub unsafe fn vld2_dup_u16(a: *const u16) -> uint16x4x2_t {
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -20780,7 +20780,7 @@ pub unsafe fn vld2q_dup_u16(a: *const u16) -> uint16x8x2_t {
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -20807,7 +20807,7 @@ pub unsafe fn vld2q_dup_u16(a: *const u16) -> uint16x8x2_t {
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -20831,7 +20831,7 @@ pub unsafe fn vld2_dup_u32(a: *const u32) -> uint32x2x2_t {
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -20858,7 +20858,7 @@ pub unsafe fn vld2_dup_u32(a: *const u32) -> uint32x2x2_t {
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -20882,7 +20882,7 @@ pub unsafe fn vld2q_dup_u32(a: *const u32) -> uint32x4x2_t {
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -20909,7 +20909,7 @@ pub unsafe fn vld2q_dup_u32(a: *const u32) -> uint32x4x2_t {
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -20933,7 +20933,7 @@ pub unsafe fn vld2_dup_p8(a: *const p8) -> poly8x8x2_t {
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -20960,7 +20960,7 @@ pub unsafe fn vld2_dup_p8(a: *const p8) -> poly8x8x2_t {
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -20984,7 +20984,7 @@ pub unsafe fn vld2q_dup_p8(a: *const p8) -> poly8x16x2_t {
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -21023,7 +21023,7 @@ pub unsafe fn vld2q_dup_p8(a: *const p8) -> poly8x16x2_t {
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -21047,7 +21047,7 @@ pub unsafe fn vld2_dup_p16(a: *const p16) -> poly16x4x2_t {
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -21074,7 +21074,7 @@ pub unsafe fn vld2_dup_p16(a: *const p16) -> poly16x4x2_t {
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -21098,7 +21098,7 @@ pub unsafe fn vld2q_dup_p16(a: *const p16) -> poly16x8x2_t {
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -21125,7 +21125,7 @@ pub unsafe fn vld2q_dup_p16(a: *const p16) -> poly16x8x2_t {
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -21144,7 +21144,7 @@ pub unsafe fn vld2_f16(a: *const f16) -> float16x4x2_t {
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -21163,7 +21163,7 @@ pub unsafe fn vld2q_f16(a: *const f16) -> float16x8x2_t {
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -21187,7 +21187,7 @@ pub unsafe fn vld2_f16(a: *const f16) -> float16x4x2_t {
 #[doc = "Load single 2-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -21211,7 +21211,7 @@ pub unsafe fn vld2q_f16(a: *const f16) -> float16x8x2_t {
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -21227,7 +21227,7 @@ pub unsafe fn vld2_f32(a: *const f32) -> float32x2x2_t {
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -21243,7 +21243,7 @@ pub unsafe fn vld2q_f32(a: *const f32) -> float32x4x2_t {
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -21259,7 +21259,7 @@ pub unsafe fn vld2_s8(a: *const i8) -> int8x8x2_t {
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -21275,7 +21275,7 @@ pub unsafe fn vld2q_s8(a: *const i8) -> int8x16x2_t {
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -21291,7 +21291,7 @@ pub unsafe fn vld2_s16(a: *const i16) -> int16x4x2_t {
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -21307,7 +21307,7 @@ pub unsafe fn vld2q_s16(a: *const i16) -> int16x8x2_t {
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -21323,7 +21323,7 @@ pub unsafe fn vld2_s32(a: *const i32) -> int32x2x2_t {
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -21339,7 +21339,7 @@ pub unsafe fn vld2q_s32(a: *const i32) -> int32x4x2_t {
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -21358,7 +21358,7 @@ pub unsafe fn vld2_f32(a: *const f32) -> float32x2x2_t {
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -21377,7 +21377,7 @@ pub unsafe fn vld2q_f32(a: *const f32) -> float32x4x2_t {
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -21396,7 +21396,7 @@ pub unsafe fn vld2_s8(a: *const i8) -> int8x8x2_t {
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -21415,7 +21415,7 @@ pub unsafe fn vld2q_s8(a: *const i8) -> int8x16x2_t {
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -21434,7 +21434,7 @@ pub unsafe fn vld2_s16(a: *const i16) -> int16x4x2_t {
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -21453,7 +21453,7 @@ pub unsafe fn vld2q_s16(a: *const i16) -> int16x8x2_t {
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -21472,7 +21472,7 @@ pub unsafe fn vld2_s32(a: *const i32) -> int32x2x2_t {
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -21491,7 +21491,7 @@ pub unsafe fn vld2q_s32(a: *const i32) -> int32x4x2_t {
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -21517,7 +21517,7 @@ pub unsafe fn vld2_lane_f16<const LANE: i32>(a: *const f16, b: float16x4x2_t) ->
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -21543,7 +21543,7 @@ pub unsafe fn vld2q_lane_f16<const LANE: i32>(a: *const f16, b: float16x8x2_t) -
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -21570,7 +21570,7 @@ pub unsafe fn vld2_lane_f16<const LANE: i32>(a: *const f16, b: float16x4x2_t) ->
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -21601,7 +21601,7 @@ pub unsafe fn vld2q_lane_f16<const LANE: i32>(a: *const f16, b: float16x8x2_t) -
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -21622,7 +21622,7 @@ pub unsafe fn vld2_lane_f32<const LANE: i32>(a: *const f32, b: float32x2x2_t) ->
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -21644,7 +21644,7 @@ pub unsafe fn vld2q_lane_f32<const LANE: i32>(a: *const f32, b: float32x4x2_t) -
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -21665,7 +21665,7 @@ pub unsafe fn vld2_lane_s8<const LANE: i32>(a: *const i8, b: int8x8x2_t) -> int8
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -21686,7 +21686,7 @@ pub unsafe fn vld2_lane_s16<const LANE: i32>(a: *const i16, b: int16x4x2_t) -> i
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -21707,7 +21707,7 @@ pub unsafe fn vld2q_lane_s16<const LANE: i32>(a: *const i16, b: int16x8x2_t) ->
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -21728,7 +21728,7 @@ pub unsafe fn vld2_lane_s32<const LANE: i32>(a: *const i32, b: int32x2x2_t) -> i
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -21749,7 +21749,7 @@ pub unsafe fn vld2q_lane_s32<const LANE: i32>(a: *const i32, b: int32x4x2_t) ->
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -21773,7 +21773,7 @@ pub unsafe fn vld2_lane_f32<const LANE: i32>(a: *const f32, b: float32x2x2_t) ->
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -21797,7 +21797,7 @@ pub unsafe fn vld2q_lane_f32<const LANE: i32>(a: *const f32, b: float32x4x2_t) -
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -21821,7 +21821,7 @@ pub unsafe fn vld2q_lane_s16<const LANE: i32>(a: *const i16, b: int16x8x2_t) ->
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -21845,7 +21845,7 @@ pub unsafe fn vld2q_lane_s32<const LANE: i32>(a: *const i32, b: int32x4x2_t) ->
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -21864,7 +21864,7 @@ pub unsafe fn vld2_lane_s8<const LANE: i32>(a: *const i8, b: int8x8x2_t) -> int8
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -21888,7 +21888,7 @@ pub unsafe fn vld2_lane_s16<const LANE: i32>(a: *const i16, b: int16x4x2_t) -> i
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -21912,7 +21912,7 @@ pub unsafe fn vld2_lane_s32<const LANE: i32>(a: *const i32, b: int32x2x2_t) -> i
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -21937,7 +21937,7 @@ pub unsafe fn vld2_lane_u8<const LANE: i32>(a: *const u8, b: uint8x8x2_t) -> uin
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -21962,7 +21962,7 @@ pub unsafe fn vld2_lane_u16<const LANE: i32>(a: *const u16, b: uint16x4x2_t) ->
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -21987,7 +21987,7 @@ pub unsafe fn vld2q_lane_u16<const LANE: i32>(a: *const u16, b: uint16x8x2_t) ->
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_u32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -22012,7 +22012,7 @@ pub unsafe fn vld2_lane_u32<const LANE: i32>(a: *const u32, b: uint32x2x2_t) ->
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_u32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -22037,7 +22037,7 @@ pub unsafe fn vld2q_lane_u32<const LANE: i32>(a: *const u32, b: uint32x4x2_t) ->
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -22062,7 +22062,7 @@ pub unsafe fn vld2_lane_p8<const LANE: i32>(a: *const p8, b: poly8x8x2_t) -> pol
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -22087,7 +22087,7 @@ pub unsafe fn vld2_lane_p16<const LANE: i32>(a: *const p16, b: poly16x4x2_t) ->
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -22112,7 +22112,7 @@ pub unsafe fn vld2q_lane_p16<const LANE: i32>(a: *const p16, b: poly16x8x2_t) ->
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_p64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -22135,7 +22135,7 @@ pub unsafe fn vld2_p64(a: *const p64) -> poly64x1x2_t {
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -22151,7 +22151,7 @@ pub unsafe fn vld2_s64(a: *const i64) -> int64x1x2_t {
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -22170,7 +22170,7 @@ pub unsafe fn vld2_s64(a: *const i64) -> int64x1x2_t {
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -22193,7 +22193,7 @@ pub unsafe fn vld2_u64(a: *const u64) -> uint64x1x2_t {
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -22217,7 +22217,7 @@ pub unsafe fn vld2_u8(a: *const u8) -> uint8x8x2_t {
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -22244,7 +22244,7 @@ pub unsafe fn vld2_u8(a: *const u8) -> uint8x8x2_t {
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -22268,7 +22268,7 @@ pub unsafe fn vld2q_u8(a: *const u8) -> uint8x16x2_t {
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -22307,7 +22307,7 @@ pub unsafe fn vld2q_u8(a: *const u8) -> uint8x16x2_t {
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -22331,7 +22331,7 @@ pub unsafe fn vld2_u16(a: *const u16) -> uint16x4x2_t {
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -22358,7 +22358,7 @@ pub unsafe fn vld2_u16(a: *const u16) -> uint16x4x2_t {
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -22382,7 +22382,7 @@ pub unsafe fn vld2q_u16(a: *const u16) -> uint16x8x2_t {
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -22409,7 +22409,7 @@ pub unsafe fn vld2q_u16(a: *const u16) -> uint16x8x2_t {
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -22433,7 +22433,7 @@ pub unsafe fn vld2_u32(a: *const u32) -> uint32x2x2_t {
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -22460,7 +22460,7 @@ pub unsafe fn vld2_u32(a: *const u32) -> uint32x2x2_t {
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -22484,7 +22484,7 @@ pub unsafe fn vld2q_u32(a: *const u32) -> uint32x4x2_t {
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -22511,7 +22511,7 @@ pub unsafe fn vld2q_u32(a: *const u32) -> uint32x4x2_t {
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -22535,7 +22535,7 @@ pub unsafe fn vld2_p8(a: *const p8) -> poly8x8x2_t {
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -22562,7 +22562,7 @@ pub unsafe fn vld2_p8(a: *const p8) -> poly8x8x2_t {
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -22586,7 +22586,7 @@ pub unsafe fn vld2q_p8(a: *const p8) -> poly8x16x2_t {
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -22625,7 +22625,7 @@ pub unsafe fn vld2q_p8(a: *const p8) -> poly8x16x2_t {
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -22649,7 +22649,7 @@ pub unsafe fn vld2_p16(a: *const p16) -> poly16x4x2_t {
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -22676,7 +22676,7 @@ pub unsafe fn vld2_p16(a: *const p16) -> poly16x4x2_t {
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -22700,7 +22700,7 @@ pub unsafe fn vld2q_p16(a: *const p16) -> poly16x8x2_t {
 #[doc = "Load multiple 2-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -22727,7 +22727,7 @@ pub unsafe fn vld2q_p16(a: *const p16) -> poly16x8x2_t {
 #[doc = "Load single 3-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -22746,7 +22746,7 @@ pub unsafe fn vld3_dup_f16(a: *const f16) -> float16x4x3_t {
 #[doc = "Load single 3-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -22765,7 +22765,7 @@ pub unsafe fn vld3q_dup_f16(a: *const f16) -> float16x8x3_t {
 #[doc = "Load single 3-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -22789,7 +22789,7 @@ pub unsafe fn vld3_dup_f16(a: *const f16) -> float16x4x3_t {
 #[doc = "Load single 3-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -22813,7 +22813,7 @@ pub unsafe fn vld3q_dup_f16(a: *const f16) -> float16x8x3_t {
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -22832,7 +22832,7 @@ pub unsafe fn vld3_dup_f32(a: *const f32) -> float32x2x3_t {
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -22851,7 +22851,7 @@ pub unsafe fn vld3q_dup_f32(a: *const f32) -> float32x4x3_t {
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -22870,7 +22870,7 @@ pub unsafe fn vld3_dup_s8(a: *const i8) -> int8x8x3_t {
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -22889,7 +22889,7 @@ pub unsafe fn vld3q_dup_s8(a: *const i8) -> int8x16x3_t {
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -22908,7 +22908,7 @@ pub unsafe fn vld3_dup_s16(a: *const i16) -> int16x4x3_t {
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -22927,7 +22927,7 @@ pub unsafe fn vld3q_dup_s16(a: *const i16) -> int16x8x3_t {
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -22946,7 +22946,7 @@ pub unsafe fn vld3_dup_s32(a: *const i32) -> int32x2x3_t {
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -22965,7 +22965,7 @@ pub unsafe fn vld3q_dup_s32(a: *const i32) -> int32x4x3_t {
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -22984,7 +22984,7 @@ pub unsafe fn vld3_dup_s64(a: *const i64) -> int64x1x3_t {
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -23000,7 +23000,7 @@ pub unsafe fn vld3_dup_f32(a: *const f32) -> float32x2x3_t {
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -23016,7 +23016,7 @@ pub unsafe fn vld3q_dup_f32(a: *const f32) -> float32x4x3_t {
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -23032,7 +23032,7 @@ pub unsafe fn vld3_dup_s8(a: *const i8) -> int8x8x3_t {
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -23048,7 +23048,7 @@ pub unsafe fn vld3q_dup_s8(a: *const i8) -> int8x16x3_t {
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -23064,7 +23064,7 @@ pub unsafe fn vld3_dup_s16(a: *const i16) -> int16x4x3_t {
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -23080,7 +23080,7 @@ pub unsafe fn vld3q_dup_s16(a: *const i16) -> int16x8x3_t {
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -23096,7 +23096,7 @@ pub unsafe fn vld3_dup_s32(a: *const i32) -> int32x2x3_t {
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -23112,7 +23112,7 @@ pub unsafe fn vld3q_dup_s32(a: *const i32) -> int32x4x3_t {
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_p64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -23135,7 +23135,7 @@ pub unsafe fn vld3_dup_p64(a: *const p64) -> poly64x1x3_t {
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -23151,7 +23151,7 @@ pub unsafe fn vld3_dup_s64(a: *const i64) -> int64x1x3_t {
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -23174,7 +23174,7 @@ pub unsafe fn vld3_dup_u64(a: *const u64) -> uint64x1x3_t {
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -23198,7 +23198,7 @@ pub unsafe fn vld3_dup_u8(a: *const u8) -> uint8x8x3_t {
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -23226,7 +23226,7 @@ pub unsafe fn vld3_dup_u8(a: *const u8) -> uint8x8x3_t {
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -23250,7 +23250,7 @@ pub unsafe fn vld3q_dup_u8(a: *const u8) -> uint8x16x3_t {
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -23296,7 +23296,7 @@ pub unsafe fn vld3q_dup_u8(a: *const u8) -> uint8x16x3_t {
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -23320,7 +23320,7 @@ pub unsafe fn vld3_dup_u16(a: *const u16) -> uint16x4x3_t {
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -23348,7 +23348,7 @@ pub unsafe fn vld3_dup_u16(a: *const u16) -> uint16x4x3_t {
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -23372,7 +23372,7 @@ pub unsafe fn vld3q_dup_u16(a: *const u16) -> uint16x8x3_t {
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -23400,7 +23400,7 @@ pub unsafe fn vld3q_dup_u16(a: *const u16) -> uint16x8x3_t {
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -23424,7 +23424,7 @@ pub unsafe fn vld3_dup_u32(a: *const u32) -> uint32x2x3_t {
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -23452,7 +23452,7 @@ pub unsafe fn vld3_dup_u32(a: *const u32) -> uint32x2x3_t {
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -23476,7 +23476,7 @@ pub unsafe fn vld3q_dup_u32(a: *const u32) -> uint32x4x3_t {
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -23504,7 +23504,7 @@ pub unsafe fn vld3q_dup_u32(a: *const u32) -> uint32x4x3_t {
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -23528,7 +23528,7 @@ pub unsafe fn vld3_dup_p8(a: *const p8) -> poly8x8x3_t {
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -23556,7 +23556,7 @@ pub unsafe fn vld3_dup_p8(a: *const p8) -> poly8x8x3_t {
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -23580,7 +23580,7 @@ pub unsafe fn vld3q_dup_p8(a: *const p8) -> poly8x16x3_t {
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -23626,7 +23626,7 @@ pub unsafe fn vld3q_dup_p8(a: *const p8) -> poly8x16x3_t {
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -23650,7 +23650,7 @@ pub unsafe fn vld3_dup_p16(a: *const p16) -> poly16x4x3_t {
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -23678,7 +23678,7 @@ pub unsafe fn vld3_dup_p16(a: *const p16) -> poly16x4x3_t {
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -23702,7 +23702,7 @@ pub unsafe fn vld3q_dup_p16(a: *const p16) -> poly16x8x3_t {
 #[doc = "Load single 3-element structure and replicate to all lanes of three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -23730,7 +23730,7 @@ pub unsafe fn vld3q_dup_p16(a: *const p16) -> poly16x8x3_t {
 #[doc = "Load single 3-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -23749,7 +23749,7 @@ pub unsafe fn vld3_f16(a: *const f16) -> float16x4x3_t {
 #[doc = "Load single 3-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -23768,7 +23768,7 @@ pub unsafe fn vld3q_f16(a: *const f16) -> float16x8x3_t {
 #[doc = "Load single 3-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -23792,7 +23792,7 @@ pub unsafe fn vld3_f16(a: *const f16) -> float16x4x3_t {
 #[doc = "Load single 3-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -23816,7 +23816,7 @@ pub unsafe fn vld3q_f16(a: *const f16) -> float16x8x3_t {
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -23835,7 +23835,7 @@ pub unsafe fn vld3_f32(a: *const f32) -> float32x2x3_t {
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -23854,7 +23854,7 @@ pub unsafe fn vld3q_f32(a: *const f32) -> float32x4x3_t {
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -23873,7 +23873,7 @@ pub unsafe fn vld3_s8(a: *const i8) -> int8x8x3_t {
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -23892,7 +23892,7 @@ pub unsafe fn vld3q_s8(a: *const i8) -> int8x16x3_t {
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -23911,7 +23911,7 @@ pub unsafe fn vld3_s16(a: *const i16) -> int16x4x3_t {
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -23930,7 +23930,7 @@ pub unsafe fn vld3q_s16(a: *const i16) -> int16x8x3_t {
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -23949,7 +23949,7 @@ pub unsafe fn vld3_s32(a: *const i32) -> int32x2x3_t {
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -23968,7 +23968,7 @@ pub unsafe fn vld3q_s32(a: *const i32) -> int32x4x3_t {
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -23984,7 +23984,7 @@ pub unsafe fn vld3_f32(a: *const f32) -> float32x2x3_t {
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -24000,7 +24000,7 @@ pub unsafe fn vld3q_f32(a: *const f32) -> float32x4x3_t {
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -24016,7 +24016,7 @@ pub unsafe fn vld3_s8(a: *const i8) -> int8x8x3_t {
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -24032,7 +24032,7 @@ pub unsafe fn vld3q_s8(a: *const i8) -> int8x16x3_t {
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -24048,7 +24048,7 @@ pub unsafe fn vld3_s16(a: *const i16) -> int16x4x3_t {
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -24064,7 +24064,7 @@ pub unsafe fn vld3q_s16(a: *const i16) -> int16x8x3_t {
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -24080,7 +24080,7 @@ pub unsafe fn vld3_s32(a: *const i32) -> int32x2x3_t {
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -24096,7 +24096,7 @@ pub unsafe fn vld3q_s32(a: *const i32) -> int32x4x3_t {
 #[doc = "Load multiple 3-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -24123,7 +24123,7 @@ pub unsafe fn vld3_lane_f16<const LANE: i32>(a: *const f16, b: float16x4x3_t) ->
 #[doc = "Load multiple 3-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -24150,7 +24150,7 @@ pub unsafe fn vld3q_lane_f16<const LANE: i32>(a: *const f16, b: float16x8x3_t) -
 #[doc = "Load multiple 3-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -24182,7 +24182,7 @@ pub unsafe fn vld3_lane_f16<const LANE: i32>(a: *const f16, b: float16x4x3_t) ->
 #[doc = "Load multiple 3-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -24214,7 +24214,7 @@ pub unsafe fn vld3q_lane_f16<const LANE: i32>(a: *const f16, b: float16x8x3_t) -
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -24241,7 +24241,7 @@ pub unsafe fn vld3_lane_f32<const LANE: i32>(a: *const f32, b: float32x2x3_t) ->
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -24268,7 +24268,7 @@ pub unsafe fn vld3q_lane_f32<const LANE: i32>(a: *const f32, b: float32x4x3_t) -
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -24293,7 +24293,7 @@ pub unsafe fn vld3_lane_f32<const LANE: i32>(a: *const f32, b: float32x2x3_t) ->
 #[doc = "Load multiple 3-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -24320,7 +24320,7 @@ pub unsafe fn vld3_lane_s8<const LANE: i32>(a: *const i8, b: int8x8x3_t) -> int8
 #[doc = "Load multiple 3-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -24347,7 +24347,7 @@ pub unsafe fn vld3_lane_s16<const LANE: i32>(a: *const i16, b: int16x4x3_t) -> i
 #[doc = "Load multiple 3-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -24374,7 +24374,7 @@ pub unsafe fn vld3q_lane_s16<const LANE: i32>(a: *const i16, b: int16x8x3_t) ->
 #[doc = "Load multiple 3-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -24401,7 +24401,7 @@ pub unsafe fn vld3_lane_s32<const LANE: i32>(a: *const i32, b: int32x2x3_t) -> i
 #[doc = "Load multiple 3-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -24428,7 +24428,7 @@ pub unsafe fn vld3q_lane_s32<const LANE: i32>(a: *const i32, b: int32x4x3_t) ->
 #[doc = "Load multiple 3-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -24453,7 +24453,7 @@ pub unsafe fn vld3_lane_s8<const LANE: i32>(a: *const i8, b: int8x8x3_t) -> int8
 #[doc = "Load multiple 3-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -24478,7 +24478,7 @@ pub unsafe fn vld3_lane_s16<const LANE: i32>(a: *const i16, b: int16x4x3_t) -> i
 #[doc = "Load multiple 3-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -24503,7 +24503,7 @@ pub unsafe fn vld3q_lane_s16<const LANE: i32>(a: *const i16, b: int16x8x3_t) ->
 #[doc = "Load multiple 3-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -24528,7 +24528,7 @@ pub unsafe fn vld3_lane_s32<const LANE: i32>(a: *const i32, b: int32x2x3_t) -> i
 #[doc = "Load multiple 3-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -24553,7 +24553,7 @@ pub unsafe fn vld3q_lane_s32<const LANE: i32>(a: *const i32, b: int32x4x3_t) ->
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -24578,7 +24578,7 @@ pub unsafe fn vld3_lane_u8<const LANE: i32>(a: *const u8, b: uint8x8x3_t) -> uin
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -24603,7 +24603,7 @@ pub unsafe fn vld3_lane_u16<const LANE: i32>(a: *const u16, b: uint16x4x3_t) ->
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -24628,7 +24628,7 @@ pub unsafe fn vld3q_lane_u16<const LANE: i32>(a: *const u16, b: uint16x8x3_t) ->
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_u32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -24653,7 +24653,7 @@ pub unsafe fn vld3_lane_u32<const LANE: i32>(a: *const u32, b: uint32x2x3_t) ->
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_u32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -24678,7 +24678,7 @@ pub unsafe fn vld3q_lane_u32<const LANE: i32>(a: *const u32, b: uint32x4x3_t) ->
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -24703,7 +24703,7 @@ pub unsafe fn vld3_lane_p8<const LANE: i32>(a: *const p8, b: poly8x8x3_t) -> pol
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -24728,7 +24728,7 @@ pub unsafe fn vld3_lane_p16<const LANE: i32>(a: *const p16, b: poly16x4x3_t) ->
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -24753,7 +24753,7 @@ pub unsafe fn vld3q_lane_p16<const LANE: i32>(a: *const p16, b: poly16x8x3_t) ->
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_p64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -24776,7 +24776,7 @@ pub unsafe fn vld3_p64(a: *const p64) -> poly64x1x3_t {
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
@@ -24795,7 +24795,7 @@ pub unsafe fn vld3_s64(a: *const i64) -> int64x1x3_t {
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -24811,7 +24811,7 @@ pub unsafe fn vld3_s64(a: *const i64) -> int64x1x3_t {
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -24834,7 +24834,7 @@ pub unsafe fn vld3_u64(a: *const u64) -> uint64x1x3_t {
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -24858,7 +24858,7 @@ pub unsafe fn vld3_u8(a: *const u8) -> uint8x8x3_t {
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -24886,7 +24886,7 @@ pub unsafe fn vld3_u8(a: *const u8) -> uint8x8x3_t {
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -24910,7 +24910,7 @@ pub unsafe fn vld3q_u8(a: *const u8) -> uint8x16x3_t {
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -24956,7 +24956,7 @@ pub unsafe fn vld3q_u8(a: *const u8) -> uint8x16x3_t {
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -24980,7 +24980,7 @@ pub unsafe fn vld3_u16(a: *const u16) -> uint16x4x3_t {
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -25008,7 +25008,7 @@ pub unsafe fn vld3_u16(a: *const u16) -> uint16x4x3_t {
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -25032,7 +25032,7 @@ pub unsafe fn vld3q_u16(a: *const u16) -> uint16x8x3_t {
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -25060,7 +25060,7 @@ pub unsafe fn vld3q_u16(a: *const u16) -> uint16x8x3_t {
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -25084,7 +25084,7 @@ pub unsafe fn vld3_u32(a: *const u32) -> uint32x2x3_t {
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -25112,7 +25112,7 @@ pub unsafe fn vld3_u32(a: *const u32) -> uint32x2x3_t {
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -25136,7 +25136,7 @@ pub unsafe fn vld3q_u32(a: *const u32) -> uint32x4x3_t {
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -25164,7 +25164,7 @@ pub unsafe fn vld3q_u32(a: *const u32) -> uint32x4x3_t {
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -25188,7 +25188,7 @@ pub unsafe fn vld3_p8(a: *const p8) -> poly8x8x3_t {
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -25216,7 +25216,7 @@ pub unsafe fn vld3_p8(a: *const p8) -> poly8x8x3_t {
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -25240,7 +25240,7 @@ pub unsafe fn vld3q_p8(a: *const p8) -> poly8x16x3_t {
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -25286,7 +25286,7 @@ pub unsafe fn vld3q_p8(a: *const p8) -> poly8x16x3_t {
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -25310,7 +25310,7 @@ pub unsafe fn vld3_p16(a: *const p16) -> poly16x4x3_t {
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -25338,7 +25338,7 @@ pub unsafe fn vld3_p16(a: *const p16) -> poly16x4x3_t {
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -25362,7 +25362,7 @@ pub unsafe fn vld3q_p16(a: *const p16) -> poly16x8x3_t {
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -25390,7 +25390,7 @@ pub unsafe fn vld3q_p16(a: *const p16) -> poly16x8x3_t {
 #[doc = "Load multiple 3-element structures to three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -25415,7 +25415,7 @@ pub unsafe fn vld3q_lane_f32<const LANE: i32>(a: *const f32, b: float32x4x3_t) -
 #[doc = "Load single 4-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg(target_arch = "arm")]
@@ -25433,7 +25433,7 @@ pub unsafe fn vld4_dup_f16(a: *const f16) -> float16x4x4_t {
 #[doc = "Load single 4-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg(target_arch = "arm")]
@@ -25451,7 +25451,7 @@ pub unsafe fn vld4q_dup_f16(a: *const f16) -> float16x8x4_t {
 #[doc = "Load single 4-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(
@@ -25474,7 +25474,7 @@ pub unsafe fn vld4_dup_f16(a: *const f16) -> float16x4x4_t {
 #[doc = "Load single 4-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(
@@ -25497,7 +25497,7 @@ pub unsafe fn vld4q_dup_f16(a: *const f16) -> float16x8x4_t {
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -25513,7 +25513,7 @@ pub unsafe fn vld4_dup_f32(a: *const f32) -> float32x2x4_t {
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -25529,7 +25529,7 @@ pub unsafe fn vld4q_dup_f32(a: *const f32) -> float32x4x4_t {
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -25545,7 +25545,7 @@ pub unsafe fn vld4_dup_s8(a: *const i8) -> int8x8x4_t {
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -25561,7 +25561,7 @@ pub unsafe fn vld4q_dup_s8(a: *const i8) -> int8x16x4_t {
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -25577,7 +25577,7 @@ pub unsafe fn vld4_dup_s16(a: *const i16) -> int16x4x4_t {
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -25593,7 +25593,7 @@ pub unsafe fn vld4q_dup_s16(a: *const i16) -> int16x8x4_t {
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -25609,7 +25609,7 @@ pub unsafe fn vld4_dup_s32(a: *const i32) -> int32x2x4_t {
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -25625,7 +25625,7 @@ pub unsafe fn vld4q_dup_s32(a: *const i32) -> int32x4x4_t {
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -25644,7 +25644,7 @@ pub unsafe fn vld4_dup_f32(a: *const f32) -> float32x2x4_t {
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -25663,7 +25663,7 @@ pub unsafe fn vld4q_dup_f32(a: *const f32) -> float32x4x4_t {
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -25682,7 +25682,7 @@ pub unsafe fn vld4_dup_s8(a: *const i8) -> int8x8x4_t {
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -25701,7 +25701,7 @@ pub unsafe fn vld4q_dup_s8(a: *const i8) -> int8x16x4_t {
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -25720,7 +25720,7 @@ pub unsafe fn vld4_dup_s16(a: *const i16) -> int16x4x4_t {
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -25739,7 +25739,7 @@ pub unsafe fn vld4q_dup_s16(a: *const i16) -> int16x8x4_t {
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -25758,7 +25758,7 @@ pub unsafe fn vld4_dup_s32(a: *const i32) -> int32x2x4_t {
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -25777,7 +25777,7 @@ pub unsafe fn vld4q_dup_s32(a: *const i32) -> int32x4x4_t {
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -25796,7 +25796,7 @@ pub unsafe fn vld4_dup_s64(a: *const i64) -> int64x1x4_t {
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_p64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -25819,7 +25819,7 @@ pub unsafe fn vld4_dup_p64(a: *const p64) -> poly64x1x4_t {
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -25835,7 +25835,7 @@ pub unsafe fn vld4_dup_s64(a: *const i64) -> int64x1x4_t {
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -25858,7 +25858,7 @@ pub unsafe fn vld4_dup_u64(a: *const u64) -> uint64x1x4_t {
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -25882,7 +25882,7 @@ pub unsafe fn vld4_dup_u8(a: *const u8) -> uint8x8x4_t {
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -25911,7 +25911,7 @@ pub unsafe fn vld4_dup_u8(a: *const u8) -> uint8x8x4_t {
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -25935,7 +25935,7 @@ pub unsafe fn vld4q_dup_u8(a: *const u8) -> uint8x16x4_t {
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -25988,7 +25988,7 @@ pub unsafe fn vld4q_dup_u8(a: *const u8) -> uint8x16x4_t {
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -26012,7 +26012,7 @@ pub unsafe fn vld4_dup_u16(a: *const u16) -> uint16x4x4_t {
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -26041,7 +26041,7 @@ pub unsafe fn vld4_dup_u16(a: *const u16) -> uint16x4x4_t {
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -26065,7 +26065,7 @@ pub unsafe fn vld4q_dup_u16(a: *const u16) -> uint16x8x4_t {
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -26094,7 +26094,7 @@ pub unsafe fn vld4q_dup_u16(a: *const u16) -> uint16x8x4_t {
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -26118,7 +26118,7 @@ pub unsafe fn vld4_dup_u32(a: *const u32) -> uint32x2x4_t {
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -26147,7 +26147,7 @@ pub unsafe fn vld4_dup_u32(a: *const u32) -> uint32x2x4_t {
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -26171,7 +26171,7 @@ pub unsafe fn vld4q_dup_u32(a: *const u32) -> uint32x4x4_t {
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -26200,7 +26200,7 @@ pub unsafe fn vld4q_dup_u32(a: *const u32) -> uint32x4x4_t {
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -26224,7 +26224,7 @@ pub unsafe fn vld4_dup_p8(a: *const p8) -> poly8x8x4_t {
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -26253,7 +26253,7 @@ pub unsafe fn vld4_dup_p8(a: *const p8) -> poly8x8x4_t {
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -26277,7 +26277,7 @@ pub unsafe fn vld4q_dup_p8(a: *const p8) -> poly8x16x4_t {
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -26330,7 +26330,7 @@ pub unsafe fn vld4q_dup_p8(a: *const p8) -> poly8x16x4_t {
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -26354,7 +26354,7 @@ pub unsafe fn vld4_dup_p16(a: *const p16) -> poly16x4x4_t {
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -26383,7 +26383,7 @@ pub unsafe fn vld4_dup_p16(a: *const p16) -> poly16x4x4_t {
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -26407,7 +26407,7 @@ pub unsafe fn vld4q_dup_p16(a: *const p16) -> poly16x8x4_t {
 #[doc = "Load single 4-element structure and replicate to all lanes of four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -26436,7 +26436,7 @@ pub unsafe fn vld4q_dup_p16(a: *const p16) -> poly16x8x4_t {
 #[doc = "Load single 4-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg(target_arch = "arm")]
@@ -26454,7 +26454,7 @@ pub unsafe fn vld4_f16(a: *const f16) -> float16x4x4_t {
 #[doc = "Load single 4-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg(target_arch = "arm")]
@@ -26472,7 +26472,7 @@ pub unsafe fn vld4q_f16(a: *const f16) -> float16x8x4_t {
 #[doc = "Load single 4-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(
@@ -26495,7 +26495,7 @@ pub unsafe fn vld4_f16(a: *const f16) -> float16x4x4_t {
 #[doc = "Load single 4-element structure and replicate to all lanes of two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(
@@ -26518,7 +26518,7 @@ pub unsafe fn vld4q_f16(a: *const f16) -> float16x8x4_t {
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -26537,7 +26537,7 @@ pub unsafe fn vld4_f32(a: *const f32) -> float32x2x4_t {
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -26556,7 +26556,7 @@ pub unsafe fn vld4q_f32(a: *const f32) -> float32x4x4_t {
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -26575,7 +26575,7 @@ pub unsafe fn vld4_s8(a: *const i8) -> int8x8x4_t {
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -26594,7 +26594,7 @@ pub unsafe fn vld4q_s8(a: *const i8) -> int8x16x4_t {
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -26613,7 +26613,7 @@ pub unsafe fn vld4_s16(a: *const i16) -> int16x4x4_t {
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -26632,7 +26632,7 @@ pub unsafe fn vld4q_s16(a: *const i16) -> int16x8x4_t {
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -26651,7 +26651,7 @@ pub unsafe fn vld4_s32(a: *const i32) -> int32x2x4_t {
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -26670,7 +26670,7 @@ pub unsafe fn vld4q_s32(a: *const i32) -> int32x4x4_t {
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -26686,7 +26686,7 @@ pub unsafe fn vld4_f32(a: *const f32) -> float32x2x4_t {
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -26702,7 +26702,7 @@ pub unsafe fn vld4q_f32(a: *const f32) -> float32x4x4_t {
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -26718,7 +26718,7 @@ pub unsafe fn vld4_s8(a: *const i8) -> int8x8x4_t {
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -26734,7 +26734,7 @@ pub unsafe fn vld4q_s8(a: *const i8) -> int8x16x4_t {
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -26750,7 +26750,7 @@ pub unsafe fn vld4_s16(a: *const i16) -> int16x4x4_t {
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -26766,7 +26766,7 @@ pub unsafe fn vld4q_s16(a: *const i16) -> int16x8x4_t {
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -26782,7 +26782,7 @@ pub unsafe fn vld4_s32(a: *const i32) -> int32x2x4_t {
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -26798,7 +26798,7 @@ pub unsafe fn vld4q_s32(a: *const i32) -> int32x4x4_t {
 #[doc = "Load multiple 4-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -26826,7 +26826,7 @@ pub unsafe fn vld4_lane_f16<const LANE: i32>(a: *const f16, b: float16x4x4_t) ->
 #[doc = "Load multiple 4-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -26854,7 +26854,7 @@ pub unsafe fn vld4q_lane_f16<const LANE: i32>(a: *const f16, b: float16x8x4_t) -
 #[doc = "Load multiple 4-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(
@@ -26886,7 +26886,7 @@ pub unsafe fn vld4_lane_f16<const LANE: i32>(a: *const f16, b: float16x4x4_t) ->
 #[doc = "Load multiple 4-element structures to two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(
@@ -26918,7 +26918,7 @@ pub unsafe fn vld4q_lane_f16<const LANE: i32>(a: *const f16, b: float16x8x4_t) -
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -26946,7 +26946,7 @@ pub unsafe fn vld4_lane_f32<const LANE: i32>(a: *const f32, b: float32x2x4_t) ->
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -26974,7 +26974,7 @@ pub unsafe fn vld4q_lane_f32<const LANE: i32>(a: *const f32, b: float32x4x4_t) -
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -27002,7 +27002,7 @@ pub unsafe fn vld4_lane_s8<const LANE: i32>(a: *const i8, b: int8x8x4_t) -> int8
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -27030,7 +27030,7 @@ pub unsafe fn vld4_lane_s16<const LANE: i32>(a: *const i16, b: int16x4x4_t) -> i
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -27058,7 +27058,7 @@ pub unsafe fn vld4q_lane_s16<const LANE: i32>(a: *const i16, b: int16x8x4_t) ->
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -27086,7 +27086,7 @@ pub unsafe fn vld4_lane_s32<const LANE: i32>(a: *const i32, b: int32x2x4_t) -> i
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -27114,7 +27114,7 @@ pub unsafe fn vld4q_lane_s32<const LANE: i32>(a: *const i32, b: int32x4x4_t) ->
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -27140,7 +27140,7 @@ pub unsafe fn vld4_lane_f32<const LANE: i32>(a: *const f32, b: float32x2x4_t) ->
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -27166,7 +27166,7 @@ pub unsafe fn vld4q_lane_f32<const LANE: i32>(a: *const f32, b: float32x4x4_t) -
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -27192,7 +27192,7 @@ pub unsafe fn vld4_lane_s8<const LANE: i32>(a: *const i8, b: int8x8x4_t) -> int8
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -27218,7 +27218,7 @@ pub unsafe fn vld4_lane_s16<const LANE: i32>(a: *const i16, b: int16x4x4_t) -> i
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -27244,7 +27244,7 @@ pub unsafe fn vld4q_lane_s16<const LANE: i32>(a: *const i16, b: int16x8x4_t) ->
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -27270,7 +27270,7 @@ pub unsafe fn vld4_lane_s32<const LANE: i32>(a: *const i32, b: int32x2x4_t) -> i
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -27296,7 +27296,7 @@ pub unsafe fn vld4q_lane_s32<const LANE: i32>(a: *const i32, b: int32x4x4_t) ->
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -27321,7 +27321,7 @@ pub unsafe fn vld4_lane_u8<const LANE: i32>(a: *const u8, b: uint8x8x4_t) -> uin
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -27346,7 +27346,7 @@ pub unsafe fn vld4_lane_u16<const LANE: i32>(a: *const u16, b: uint16x4x4_t) ->
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -27371,7 +27371,7 @@ pub unsafe fn vld4q_lane_u16<const LANE: i32>(a: *const u16, b: uint16x8x4_t) ->
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_u32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -27396,7 +27396,7 @@ pub unsafe fn vld4_lane_u32<const LANE: i32>(a: *const u32, b: uint32x2x4_t) ->
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_u32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -27421,7 +27421,7 @@ pub unsafe fn vld4q_lane_u32<const LANE: i32>(a: *const u32, b: uint32x4x4_t) ->
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -27446,7 +27446,7 @@ pub unsafe fn vld4_lane_p8<const LANE: i32>(a: *const p8, b: poly8x8x4_t) -> pol
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -27471,7 +27471,7 @@ pub unsafe fn vld4_lane_p16<const LANE: i32>(a: *const p16, b: poly16x4x4_t) ->
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -27496,7 +27496,7 @@ pub unsafe fn vld4q_lane_p16<const LANE: i32>(a: *const p16, b: poly16x8x4_t) ->
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_p64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[target_feature(enable = "neon,aes")]
@@ -27519,7 +27519,7 @@ pub unsafe fn vld4_p64(a: *const p64) -> poly64x1x4_t {
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -27538,7 +27538,7 @@ pub unsafe fn vld4_s64(a: *const i64) -> int64x1x4_t {
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -27554,7 +27554,7 @@ pub unsafe fn vld4_s64(a: *const i64) -> int64x1x4_t {
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -27577,7 +27577,7 @@ pub unsafe fn vld4_u64(a: *const u64) -> uint64x1x4_t {
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -27601,7 +27601,7 @@ pub unsafe fn vld4_u8(a: *const u8) -> uint8x8x4_t {
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -27630,7 +27630,7 @@ pub unsafe fn vld4_u8(a: *const u8) -> uint8x8x4_t {
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -27654,7 +27654,7 @@ pub unsafe fn vld4q_u8(a: *const u8) -> uint8x16x4_t {
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -27707,7 +27707,7 @@ pub unsafe fn vld4q_u8(a: *const u8) -> uint8x16x4_t {
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -27731,7 +27731,7 @@ pub unsafe fn vld4_u16(a: *const u16) -> uint16x4x4_t {
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -27760,7 +27760,7 @@ pub unsafe fn vld4_u16(a: *const u16) -> uint16x4x4_t {
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -27784,7 +27784,7 @@ pub unsafe fn vld4q_u16(a: *const u16) -> uint16x8x4_t {
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -27813,7 +27813,7 @@ pub unsafe fn vld4q_u16(a: *const u16) -> uint16x8x4_t {
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -27837,7 +27837,7 @@ pub unsafe fn vld4_u32(a: *const u32) -> uint32x2x4_t {
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -27866,7 +27866,7 @@ pub unsafe fn vld4_u32(a: *const u32) -> uint32x2x4_t {
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -27890,7 +27890,7 @@ pub unsafe fn vld4q_u32(a: *const u32) -> uint32x4x4_t {
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -27919,7 +27919,7 @@ pub unsafe fn vld4q_u32(a: *const u32) -> uint32x4x4_t {
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -27943,7 +27943,7 @@ pub unsafe fn vld4_p8(a: *const p8) -> poly8x8x4_t {
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -27972,7 +27972,7 @@ pub unsafe fn vld4_p8(a: *const p8) -> poly8x8x4_t {
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -27996,7 +27996,7 @@ pub unsafe fn vld4q_p8(a: *const p8) -> poly8x16x4_t {
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -28049,7 +28049,7 @@ pub unsafe fn vld4q_p8(a: *const p8) -> poly8x16x4_t {
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -28073,7 +28073,7 @@ pub unsafe fn vld4_p16(a: *const p16) -> poly16x4x4_t {
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -28102,7 +28102,7 @@ pub unsafe fn vld4_p16(a: *const p16) -> poly16x4x4_t {
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
@@ -28126,7 +28126,7 @@ pub unsafe fn vld4q_p16(a: *const p16) -> poly16x8x4_t {
 #[doc = "Load multiple 4-element structures to four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_endian = "big")]
 #[target_feature(enable = "neon")]
@@ -28155,7 +28155,7 @@ pub unsafe fn vld4q_p16(a: *const p16) -> poly16x8x4_t {
 #[doc = "Store SIMD&FP register (immediate offset)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vldrq_p128)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -65084,7 +65084,7 @@ pub fn vsriq_n_p16<const N: i32>(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -65102,7 +65102,7 @@ pub unsafe fn vst1_f16(ptr: *mut f16, a: float16x4_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -65120,7 +65120,7 @@ pub unsafe fn vst1q_f16(ptr: *mut f16, a: float16x8_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f16_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -65138,7 +65138,7 @@ pub unsafe fn vst1_f16_x2(a: *mut f16, b: float16x4x2_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f16_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -65156,7 +65156,7 @@ pub unsafe fn vst1q_f16_x2(a: *mut f16, b: float16x8x2_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f16_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(st1))]
@@ -65176,7 +65176,7 @@ pub unsafe fn vst1_f16_x2(a: *mut f16, b: float16x4x2_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f16_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(st1))]
@@ -65196,7 +65196,7 @@ pub unsafe fn vst1q_f16_x2(a: *mut f16, b: float16x8x2_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f16_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -65214,7 +65214,7 @@ pub unsafe fn vst1_f16_x3(a: *mut f16, b: float16x4x3_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f16_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -65232,7 +65232,7 @@ pub unsafe fn vst1q_f16_x3(a: *mut f16, b: float16x8x3_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f16_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(st1))]
@@ -65252,7 +65252,7 @@ pub unsafe fn vst1_f16_x3(a: *mut f16, b: float16x4x3_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f16_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(st1))]
@@ -65272,7 +65272,7 @@ pub unsafe fn vst1q_f16_x3(a: *mut f16, b: float16x8x3_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f16_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -65297,7 +65297,7 @@ pub unsafe fn vst1_f16_x4(a: *mut f16, b: float16x4x4_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f16_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -65322,7 +65322,7 @@ pub unsafe fn vst1q_f16_x4(a: *mut f16, b: float16x8x4_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f16_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(st1))]
@@ -65348,7 +65348,7 @@ pub unsafe fn vst1_f16_x4(a: *mut f16, b: float16x4x4_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f16_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(not(target_arch = "arm"))]
 #[cfg_attr(test, assert_instr(st1))]
@@ -65374,7 +65374,7 @@ pub unsafe fn vst1q_f16_x4(a: *mut f16, b: float16x8x4_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -65388,7 +65388,7 @@ pub unsafe fn vst1_f32(ptr: *mut f32, a: float32x2_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -65402,7 +65402,7 @@ pub unsafe fn vst1q_f32(ptr: *mut f32, a: float32x4_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -65416,7 +65416,7 @@ pub unsafe fn vst1_s8(ptr: *mut i8, a: int8x8_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -65430,7 +65430,7 @@ pub unsafe fn vst1q_s8(ptr: *mut i8, a: int8x16_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -65444,7 +65444,7 @@ pub unsafe fn vst1_s16(ptr: *mut i16, a: int16x4_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -65458,7 +65458,7 @@ pub unsafe fn vst1q_s16(ptr: *mut i16, a: int16x8_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -65472,7 +65472,7 @@ pub unsafe fn vst1_s32(ptr: *mut i32, a: int32x2_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -65486,7 +65486,7 @@ pub unsafe fn vst1q_s32(ptr: *mut i32, a: int32x4_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -65500,7 +65500,7 @@ pub unsafe fn vst1_s64(ptr: *mut i64, a: int64x1_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -65514,7 +65514,7 @@ pub unsafe fn vst1q_s64(ptr: *mut i64, a: int64x2_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -65528,7 +65528,7 @@ pub unsafe fn vst1_u8(ptr: *mut u8, a: uint8x8_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -65542,7 +65542,7 @@ pub unsafe fn vst1q_u8(ptr: *mut u8, a: uint8x16_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -65556,7 +65556,7 @@ pub unsafe fn vst1_u16(ptr: *mut u16, a: uint16x4_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -65570,7 +65570,7 @@ pub unsafe fn vst1q_u16(ptr: *mut u16, a: uint16x8_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -65584,7 +65584,7 @@ pub unsafe fn vst1_u32(ptr: *mut u32, a: uint32x2_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -65598,7 +65598,7 @@ pub unsafe fn vst1q_u32(ptr: *mut u32, a: uint32x4_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -65612,7 +65612,7 @@ pub unsafe fn vst1_u64(ptr: *mut u64, a: uint64x1_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -65626,7 +65626,7 @@ pub unsafe fn vst1q_u64(ptr: *mut u64, a: uint64x2_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -65640,7 +65640,7 @@ pub unsafe fn vst1_p8(ptr: *mut p8, a: poly8x8_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -65654,7 +65654,7 @@ pub unsafe fn vst1q_p8(ptr: *mut p8, a: poly8x16_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -65668,7 +65668,7 @@ pub unsafe fn vst1_p16(ptr: *mut p16, a: poly16x4_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -65682,7 +65682,7 @@ pub unsafe fn vst1q_p16(ptr: *mut p16, a: poly16x8_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -65696,7 +65696,7 @@ pub unsafe fn vst1_p64(ptr: *mut p64, a: poly64x1_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -65710,7 +65710,7 @@ pub unsafe fn vst1q_p64(ptr: *mut p64, a: poly64x2_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -65726,7 +65726,7 @@ pub unsafe fn vst1_f32_x2(a: *mut f32, b: float32x2x2_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -65742,7 +65742,7 @@ pub unsafe fn vst1q_f32_x2(a: *mut f32, b: float32x4x2_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -65761,7 +65761,7 @@ pub unsafe fn vst1_f32_x2(a: *mut f32, b: float32x2x2_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -65780,7 +65780,7 @@ pub unsafe fn vst1q_f32_x2(a: *mut f32, b: float32x4x2_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -65799,7 +65799,7 @@ pub unsafe fn vst1_f32_x3(a: *mut f32, b: float32x2x3_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -65818,7 +65818,7 @@ pub unsafe fn vst1q_f32_x3(a: *mut f32, b: float32x4x3_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -65840,7 +65840,7 @@ pub unsafe fn vst1_f32_x4(a: *mut f32, b: float32x2x4_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -65862,7 +65862,7 @@ pub unsafe fn vst1q_f32_x4(a: *mut f32, b: float32x4x4_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -65887,7 +65887,7 @@ pub unsafe fn vst1_f32_x4(a: *mut f32, b: float32x2x4_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -65912,7 +65912,7 @@ pub unsafe fn vst1q_f32_x4(a: *mut f32, b: float32x4x4_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -65932,7 +65932,7 @@ pub unsafe fn vst1_lane_f16<const LANE: i32>(a: *mut f16, b: float16x4_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -65952,7 +65952,7 @@ pub unsafe fn vst1q_lane_f16<const LANE: i32>(a: *mut f16, b: float16x8_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -65977,7 +65977,7 @@ pub unsafe fn vst1_lane_f32<const LANE: i32>(a: *mut f32, b: float32x2_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -66002,7 +66002,7 @@ pub unsafe fn vst1q_lane_f32<const LANE: i32>(a: *mut f32, b: float32x4_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -66027,7 +66027,7 @@ pub unsafe fn vst1_lane_s8<const LANE: i32>(a: *mut i8, b: int8x8_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -66052,7 +66052,7 @@ pub unsafe fn vst1q_lane_s8<const LANE: i32>(a: *mut i8, b: int8x16_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -66077,7 +66077,7 @@ pub unsafe fn vst1_lane_s16<const LANE: i32>(a: *mut i16, b: int16x4_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -66102,7 +66102,7 @@ pub unsafe fn vst1q_lane_s16<const LANE: i32>(a: *mut i16, b: int16x8_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -66127,7 +66127,7 @@ pub unsafe fn vst1_lane_s32<const LANE: i32>(a: *mut i32, b: int32x2_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -66152,7 +66152,7 @@ pub unsafe fn vst1q_lane_s32<const LANE: i32>(a: *mut i32, b: int32x4_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_s64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -66177,7 +66177,7 @@ pub unsafe fn vst1q_lane_s64<const LANE: i32>(a: *mut i64, b: int64x2_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -66202,7 +66202,7 @@ pub unsafe fn vst1_lane_u8<const LANE: i32>(a: *mut u8, b: uint8x8_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -66227,7 +66227,7 @@ pub unsafe fn vst1q_lane_u8<const LANE: i32>(a: *mut u8, b: uint8x16_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -66252,7 +66252,7 @@ pub unsafe fn vst1_lane_u16<const LANE: i32>(a: *mut u16, b: uint16x4_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -66277,7 +66277,7 @@ pub unsafe fn vst1q_lane_u16<const LANE: i32>(a: *mut u16, b: uint16x8_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_u32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -66302,7 +66302,7 @@ pub unsafe fn vst1_lane_u32<const LANE: i32>(a: *mut u32, b: uint32x2_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_u32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -66327,7 +66327,7 @@ pub unsafe fn vst1q_lane_u32<const LANE: i32>(a: *mut u32, b: uint32x4_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_u64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -66352,7 +66352,7 @@ pub unsafe fn vst1q_lane_u64<const LANE: i32>(a: *mut u64, b: uint64x2_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -66377,7 +66377,7 @@ pub unsafe fn vst1_lane_p8<const LANE: i32>(a: *mut p8, b: poly8x8_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -66402,7 +66402,7 @@ pub unsafe fn vst1q_lane_p8<const LANE: i32>(a: *mut p8, b: poly8x16_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -66427,7 +66427,7 @@ pub unsafe fn vst1_lane_p16<const LANE: i32>(a: *mut p16, b: poly16x4_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -66452,7 +66452,7 @@ pub unsafe fn vst1q_lane_p16<const LANE: i32>(a: *mut p16, b: poly16x8_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_p64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[target_feature(enable = "neon,aes")]
@@ -66477,7 +66477,7 @@ pub unsafe fn vst1_lane_p64<const LANE: i32>(a: *mut p64, b: poly64x1_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_s64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -66502,7 +66502,7 @@ pub unsafe fn vst1_lane_s64<const LANE: i32>(a: *mut i64, b: int64x1_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_u64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -66527,7 +66527,7 @@ pub unsafe fn vst1_lane_u64<const LANE: i32>(a: *mut u64, b: uint64x1_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p64_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -66550,7 +66550,7 @@ pub unsafe fn vst1_p64_x2(a: *mut p64, b: poly64x1x2_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p64_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -66573,7 +66573,7 @@ pub unsafe fn vst1_p64_x3(a: *mut p64, b: poly64x1x3_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p64_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -66596,7 +66596,7 @@ pub unsafe fn vst1_p64_x4(a: *mut p64, b: poly64x1x4_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p64_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -66619,7 +66619,7 @@ pub unsafe fn vst1q_p64_x2(a: *mut p64, b: poly64x2x2_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p64_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -66642,7 +66642,7 @@ pub unsafe fn vst1q_p64_x3(a: *mut p64, b: poly64x2x3_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p64_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,aes")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
@@ -66665,7 +66665,7 @@ pub unsafe fn vst1q_p64_x4(a: *mut p64, b: poly64x2x4_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -66684,7 +66684,7 @@ pub unsafe fn vst1_s8_x2(a: *mut i8, b: int8x8x2_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -66703,7 +66703,7 @@ pub unsafe fn vst1q_s8_x2(a: *mut i8, b: int8x16x2_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -66722,7 +66722,7 @@ pub unsafe fn vst1_s16_x2(a: *mut i16, b: int16x4x2_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -66741,7 +66741,7 @@ pub unsafe fn vst1q_s16_x2(a: *mut i16, b: int16x8x2_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -66760,7 +66760,7 @@ pub unsafe fn vst1_s32_x2(a: *mut i32, b: int32x2x2_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -66779,7 +66779,7 @@ pub unsafe fn vst1q_s32_x2(a: *mut i32, b: int32x4x2_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -66798,7 +66798,7 @@ pub unsafe fn vst1_s64_x2(a: *mut i64, b: int64x1x2_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -66817,7 +66817,7 @@ pub unsafe fn vst1q_s64_x2(a: *mut i64, b: int64x2x2_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -66833,7 +66833,7 @@ pub unsafe fn vst1_s8_x2(a: *mut i8, b: int8x8x2_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -66849,7 +66849,7 @@ pub unsafe fn vst1q_s8_x2(a: *mut i8, b: int8x16x2_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -66865,7 +66865,7 @@ pub unsafe fn vst1_s16_x2(a: *mut i16, b: int16x4x2_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -66881,7 +66881,7 @@ pub unsafe fn vst1q_s16_x2(a: *mut i16, b: int16x8x2_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -66897,7 +66897,7 @@ pub unsafe fn vst1_s32_x2(a: *mut i32, b: int32x2x2_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -66913,7 +66913,7 @@ pub unsafe fn vst1q_s32_x2(a: *mut i32, b: int32x4x2_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -66929,7 +66929,7 @@ pub unsafe fn vst1_s64_x2(a: *mut i64, b: int64x1x2_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -66945,7 +66945,7 @@ pub unsafe fn vst1q_s64_x2(a: *mut i64, b: int64x2x2_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -66964,7 +66964,7 @@ pub unsafe fn vst1_s8_x3(a: *mut i8, b: int8x8x3_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -66983,7 +66983,7 @@ pub unsafe fn vst1q_s8_x3(a: *mut i8, b: int8x16x3_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -67002,7 +67002,7 @@ pub unsafe fn vst1_s16_x3(a: *mut i16, b: int16x4x3_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -67021,7 +67021,7 @@ pub unsafe fn vst1q_s16_x3(a: *mut i16, b: int16x8x3_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -67040,7 +67040,7 @@ pub unsafe fn vst1_s32_x3(a: *mut i32, b: int32x2x3_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -67059,7 +67059,7 @@ pub unsafe fn vst1q_s32_x3(a: *mut i32, b: int32x4x3_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -67078,7 +67078,7 @@ pub unsafe fn vst1_s64_x3(a: *mut i64, b: int64x1x3_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -67097,7 +67097,7 @@ pub unsafe fn vst1q_s64_x3(a: *mut i64, b: int64x2x3_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -67113,7 +67113,7 @@ pub unsafe fn vst1_s8_x3(a: *mut i8, b: int8x8x3_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -67129,7 +67129,7 @@ pub unsafe fn vst1q_s8_x3(a: *mut i8, b: int8x16x3_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -67145,7 +67145,7 @@ pub unsafe fn vst1_s16_x3(a: *mut i16, b: int16x4x3_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -67161,7 +67161,7 @@ pub unsafe fn vst1q_s16_x3(a: *mut i16, b: int16x8x3_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -67177,7 +67177,7 @@ pub unsafe fn vst1_s32_x3(a: *mut i32, b: int32x2x3_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -67193,7 +67193,7 @@ pub unsafe fn vst1q_s32_x3(a: *mut i32, b: int32x4x3_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -67209,7 +67209,7 @@ pub unsafe fn vst1_s64_x3(a: *mut i64, b: int64x1x3_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon,v7")]
 #[cfg(target_arch = "arm")]
@@ -67225,7 +67225,7 @@ pub unsafe fn vst1q_s64_x3(a: *mut i64, b: int64x2x3_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -67244,7 +67244,7 @@ pub unsafe fn vst1_s8_x4(a: *mut i8, b: int8x8x4_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -67263,7 +67263,7 @@ pub unsafe fn vst1q_s8_x4(a: *mut i8, b: int8x16x4_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -67282,7 +67282,7 @@ pub unsafe fn vst1_s16_x4(a: *mut i16, b: int16x4x4_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -67301,7 +67301,7 @@ pub unsafe fn vst1q_s16_x4(a: *mut i16, b: int16x8x4_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -67320,7 +67320,7 @@ pub unsafe fn vst1_s32_x4(a: *mut i32, b: int32x2x4_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -67339,7 +67339,7 @@ pub unsafe fn vst1q_s32_x4(a: *mut i32, b: int32x4x4_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -67358,7 +67358,7 @@ pub unsafe fn vst1_s64_x4(a: *mut i64, b: int64x1x4_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -67377,7 +67377,7 @@ pub unsafe fn vst1q_s64_x4(a: *mut i64, b: int64x2x4_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -67393,7 +67393,7 @@ pub unsafe fn vst1_s8_x4(a: *mut i8, b: int8x8x4_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -67409,7 +67409,7 @@ pub unsafe fn vst1q_s8_x4(a: *mut i8, b: int8x16x4_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -67425,7 +67425,7 @@ pub unsafe fn vst1_s16_x4(a: *mut i16, b: int16x4x4_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -67441,7 +67441,7 @@ pub unsafe fn vst1q_s16_x4(a: *mut i16, b: int16x8x4_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -67457,7 +67457,7 @@ pub unsafe fn vst1_s32_x4(a: *mut i32, b: int32x2x4_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -67473,7 +67473,7 @@ pub unsafe fn vst1q_s32_x4(a: *mut i32, b: int32x4x4_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -67489,7 +67489,7 @@ pub unsafe fn vst1_s64_x4(a: *mut i64, b: int64x1x4_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -67505,7 +67505,7 @@ pub unsafe fn vst1q_s64_x4(a: *mut i64, b: int64x2x4_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u8_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -67528,7 +67528,7 @@ pub unsafe fn vst1_u8_x2(a: *mut u8, b: uint8x8x2_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u8_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -67551,7 +67551,7 @@ pub unsafe fn vst1_u8_x3(a: *mut u8, b: uint8x8x3_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u8_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -67574,7 +67574,7 @@ pub unsafe fn vst1_u8_x4(a: *mut u8, b: uint8x8x4_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u8_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -67597,7 +67597,7 @@ pub unsafe fn vst1q_u8_x2(a: *mut u8, b: uint8x16x2_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u8_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -67620,7 +67620,7 @@ pub unsafe fn vst1q_u8_x3(a: *mut u8, b: uint8x16x3_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u8_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -67643,7 +67643,7 @@ pub unsafe fn vst1q_u8_x4(a: *mut u8, b: uint8x16x4_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u16_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -67666,7 +67666,7 @@ pub unsafe fn vst1_u16_x2(a: *mut u16, b: uint16x4x2_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u16_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -67689,7 +67689,7 @@ pub unsafe fn vst1_u16_x3(a: *mut u16, b: uint16x4x3_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u16_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -67712,7 +67712,7 @@ pub unsafe fn vst1_u16_x4(a: *mut u16, b: uint16x4x4_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u16_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -67735,7 +67735,7 @@ pub unsafe fn vst1q_u16_x2(a: *mut u16, b: uint16x8x2_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u16_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -67758,7 +67758,7 @@ pub unsafe fn vst1q_u16_x3(a: *mut u16, b: uint16x8x3_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u16_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -67781,7 +67781,7 @@ pub unsafe fn vst1q_u16_x4(a: *mut u16, b: uint16x8x4_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u32_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -67804,7 +67804,7 @@ pub unsafe fn vst1_u32_x2(a: *mut u32, b: uint32x2x2_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u32_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -67827,7 +67827,7 @@ pub unsafe fn vst1_u32_x3(a: *mut u32, b: uint32x2x3_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u32_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -67850,7 +67850,7 @@ pub unsafe fn vst1_u32_x4(a: *mut u32, b: uint32x2x4_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u32_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -67873,7 +67873,7 @@ pub unsafe fn vst1q_u32_x2(a: *mut u32, b: uint32x4x2_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u32_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -67896,7 +67896,7 @@ pub unsafe fn vst1q_u32_x3(a: *mut u32, b: uint32x4x3_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u32_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -67919,7 +67919,7 @@ pub unsafe fn vst1q_u32_x4(a: *mut u32, b: uint32x4x4_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u64_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -67942,7 +67942,7 @@ pub unsafe fn vst1_u64_x2(a: *mut u64, b: uint64x1x2_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u64_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -67965,7 +67965,7 @@ pub unsafe fn vst1_u64_x3(a: *mut u64, b: uint64x1x3_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u64_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -67988,7 +67988,7 @@ pub unsafe fn vst1_u64_x4(a: *mut u64, b: uint64x1x4_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u64_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -68011,7 +68011,7 @@ pub unsafe fn vst1q_u64_x2(a: *mut u64, b: uint64x2x2_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u64_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -68034,7 +68034,7 @@ pub unsafe fn vst1q_u64_x3(a: *mut u64, b: uint64x2x3_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u64_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -68057,7 +68057,7 @@ pub unsafe fn vst1q_u64_x4(a: *mut u64, b: uint64x2x4_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p8_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -68080,7 +68080,7 @@ pub unsafe fn vst1_p8_x2(a: *mut p8, b: poly8x8x2_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p8_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -68103,7 +68103,7 @@ pub unsafe fn vst1_p8_x3(a: *mut p8, b: poly8x8x3_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p8_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -68126,7 +68126,7 @@ pub unsafe fn vst1_p8_x4(a: *mut p8, b: poly8x8x4_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p8_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -68149,7 +68149,7 @@ pub unsafe fn vst1q_p8_x2(a: *mut p8, b: poly8x16x2_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p8_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -68172,7 +68172,7 @@ pub unsafe fn vst1q_p8_x3(a: *mut p8, b: poly8x16x3_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p8_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -68195,7 +68195,7 @@ pub unsafe fn vst1q_p8_x4(a: *mut p8, b: poly8x16x4_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p16_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -68218,7 +68218,7 @@ pub unsafe fn vst1_p16_x2(a: *mut p16, b: poly16x4x2_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p16_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -68241,7 +68241,7 @@ pub unsafe fn vst1_p16_x3(a: *mut p16, b: poly16x4x3_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p16_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -68264,7 +68264,7 @@ pub unsafe fn vst1_p16_x4(a: *mut p16, b: poly16x4x4_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p16_x2)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -68287,7 +68287,7 @@ pub unsafe fn vst1q_p16_x2(a: *mut p16, b: poly16x8x2_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p16_x3)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -68310,7 +68310,7 @@ pub unsafe fn vst1q_p16_x3(a: *mut p16, b: poly16x8x3_t) {
 #[doc = "Store multiple single-element structures to one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p16_x4)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -68473,7 +68473,7 @@ unsafe fn vst1q_v8i16<const ALIGN: i32>(addr: *const i8, val: int16x8_t) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_v4f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -68491,7 +68491,7 @@ unsafe fn vst1_v4f16(addr: *const i8, val: float16x4_t, align: i32) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_v8f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -68509,7 +68509,7 @@ unsafe fn vst1q_v8f16(addr: *const i8, val: float16x8_t, align: i32) {
 #[doc = "Store multiple single-element structures from one, two, three, or four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_p64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[target_feature(enable = "neon,aes")]
@@ -68534,7 +68534,7 @@ pub unsafe fn vst1q_lane_p64<const LANE: i32>(a: *mut p64, b: poly64x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -68555,7 +68555,7 @@ pub unsafe fn vst2_f16(a: *mut f16, b: float16x4x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -68576,7 +68576,7 @@ pub unsafe fn vst2q_f16(a: *mut f16, b: float16x8x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -68595,7 +68595,7 @@ pub unsafe fn vst2_f16(a: *mut f16, b: float16x4x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -68614,7 +68614,7 @@ pub unsafe fn vst2q_f16(a: *mut f16, b: float16x8x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -68633,7 +68633,7 @@ pub unsafe fn vst2_f32(a: *mut f32, b: float32x2x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -68652,7 +68652,7 @@ pub unsafe fn vst2q_f32(a: *mut f32, b: float32x4x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -68671,7 +68671,7 @@ pub unsafe fn vst2_s8(a: *mut i8, b: int8x8x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -68690,7 +68690,7 @@ pub unsafe fn vst2q_s8(a: *mut i8, b: int8x16x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -68709,7 +68709,7 @@ pub unsafe fn vst2_s16(a: *mut i16, b: int16x4x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -68728,7 +68728,7 @@ pub unsafe fn vst2q_s16(a: *mut i16, b: int16x8x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -68747,7 +68747,7 @@ pub unsafe fn vst2_s32(a: *mut i32, b: int32x2x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -68766,7 +68766,7 @@ pub unsafe fn vst2q_s32(a: *mut i32, b: int32x4x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -68782,7 +68782,7 @@ pub unsafe fn vst2_f32(a: *mut f32, b: float32x2x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -68798,7 +68798,7 @@ pub unsafe fn vst2q_f32(a: *mut f32, b: float32x4x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -68814,7 +68814,7 @@ pub unsafe fn vst2_s8(a: *mut i8, b: int8x8x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -68830,7 +68830,7 @@ pub unsafe fn vst2q_s8(a: *mut i8, b: int8x16x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -68846,7 +68846,7 @@ pub unsafe fn vst2_s16(a: *mut i16, b: int16x4x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -68862,7 +68862,7 @@ pub unsafe fn vst2q_s16(a: *mut i16, b: int16x8x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -68878,7 +68878,7 @@ pub unsafe fn vst2_s32(a: *mut i32, b: int32x2x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -68894,7 +68894,7 @@ pub unsafe fn vst2q_s32(a: *mut i32, b: int32x4x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -68917,7 +68917,7 @@ pub unsafe fn vst2_lane_f16<const LANE: i32>(a: *mut f16, b: float16x4x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -68940,7 +68940,7 @@ pub unsafe fn vst2q_lane_f16<const LANE: i32>(a: *mut f16, b: float16x8x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -68961,7 +68961,7 @@ pub unsafe fn vst2_lane_f16<const LANE: i32>(a: *mut f16, b: float16x4x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -68982,7 +68982,7 @@ pub unsafe fn vst2q_lane_f16<const LANE: i32>(a: *mut f16, b: float16x8x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -69003,7 +69003,7 @@ pub unsafe fn vst2_lane_f32<const LANE: i32>(a: *mut f32, b: float32x2x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -69024,7 +69024,7 @@ pub unsafe fn vst2q_lane_f32<const LANE: i32>(a: *mut f32, b: float32x4x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -69045,7 +69045,7 @@ pub unsafe fn vst2_lane_s8<const LANE: i32>(a: *mut i8, b: int8x8x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -69066,7 +69066,7 @@ pub unsafe fn vst2_lane_s16<const LANE: i32>(a: *mut i16, b: int16x4x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -69087,7 +69087,7 @@ pub unsafe fn vst2q_lane_s16<const LANE: i32>(a: *mut i16, b: int16x8x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -69108,7 +69108,7 @@ pub unsafe fn vst2_lane_s32<const LANE: i32>(a: *mut i32, b: int32x2x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -69129,7 +69129,7 @@ pub unsafe fn vst2q_lane_s32<const LANE: i32>(a: *mut i32, b: int32x4x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -69147,7 +69147,7 @@ pub unsafe fn vst2_lane_f32<const LANE: i32>(a: *mut f32, b: float32x2x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -69165,7 +69165,7 @@ pub unsafe fn vst2q_lane_f32<const LANE: i32>(a: *mut f32, b: float32x4x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -69183,7 +69183,7 @@ pub unsafe fn vst2_lane_s8<const LANE: i32>(a: *mut i8, b: int8x8x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -69201,7 +69201,7 @@ pub unsafe fn vst2_lane_s16<const LANE: i32>(a: *mut i16, b: int16x4x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -69219,7 +69219,7 @@ pub unsafe fn vst2q_lane_s16<const LANE: i32>(a: *mut i16, b: int16x8x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -69237,7 +69237,7 @@ pub unsafe fn vst2_lane_s32<const LANE: i32>(a: *mut i32, b: int32x2x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -69255,7 +69255,7 @@ pub unsafe fn vst2q_lane_s32<const LANE: i32>(a: *mut i32, b: int32x4x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -69280,7 +69280,7 @@ pub unsafe fn vst2_lane_u8<const LANE: i32>(a: *mut u8, b: uint8x8x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -69305,7 +69305,7 @@ pub unsafe fn vst2_lane_u16<const LANE: i32>(a: *mut u16, b: uint16x4x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -69330,7 +69330,7 @@ pub unsafe fn vst2q_lane_u16<const LANE: i32>(a: *mut u16, b: uint16x8x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_u32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -69355,7 +69355,7 @@ pub unsafe fn vst2_lane_u32<const LANE: i32>(a: *mut u32, b: uint32x2x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_u32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -69380,7 +69380,7 @@ pub unsafe fn vst2q_lane_u32<const LANE: i32>(a: *mut u32, b: uint32x4x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -69405,7 +69405,7 @@ pub unsafe fn vst2_lane_p8<const LANE: i32>(a: *mut p8, b: poly8x8x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -69430,7 +69430,7 @@ pub unsafe fn vst2_lane_p16<const LANE: i32>(a: *mut p16, b: poly16x4x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -69455,7 +69455,7 @@ pub unsafe fn vst2q_lane_p16<const LANE: i32>(a: *mut p16, b: poly16x8x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_p64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[target_feature(enable = "neon,aes")]
@@ -69478,7 +69478,7 @@ pub unsafe fn vst2_p64(a: *mut p64, b: poly64x1x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -69494,7 +69494,7 @@ pub unsafe fn vst2_s64(a: *mut i64, b: int64x1x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -69513,7 +69513,7 @@ pub unsafe fn vst2_s64(a: *mut i64, b: int64x1x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_u64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -69536,7 +69536,7 @@ pub unsafe fn vst2_u64(a: *mut u64, b: uint64x1x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -69559,7 +69559,7 @@ pub unsafe fn vst2_u8(a: *mut u8, b: uint8x8x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -69582,7 +69582,7 @@ pub unsafe fn vst2q_u8(a: *mut u8, b: uint8x16x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -69605,7 +69605,7 @@ pub unsafe fn vst2_u16(a: *mut u16, b: uint16x4x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -69628,7 +69628,7 @@ pub unsafe fn vst2q_u16(a: *mut u16, b: uint16x8x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_u32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -69651,7 +69651,7 @@ pub unsafe fn vst2_u32(a: *mut u32, b: uint32x2x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_u32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -69674,7 +69674,7 @@ pub unsafe fn vst2q_u32(a: *mut u32, b: uint32x4x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -69697,7 +69697,7 @@ pub unsafe fn vst2_p8(a: *mut p8, b: poly8x8x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -69720,7 +69720,7 @@ pub unsafe fn vst2q_p8(a: *mut p8, b: poly8x16x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -69743,7 +69743,7 @@ pub unsafe fn vst2_p16(a: *mut p16, b: poly16x4x2_t) {
 #[doc = "Store multiple 2-element structures from two registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -69766,7 +69766,7 @@ pub unsafe fn vst2q_p16(a: *mut p16, b: poly16x8x2_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -69785,7 +69785,7 @@ pub unsafe fn vst3_f16(a: *mut f16, b: float16x4x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -69804,7 +69804,7 @@ pub unsafe fn vst3q_f16(a: *mut f16, b: float16x8x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -69825,7 +69825,7 @@ pub unsafe fn vst3_f16(a: *mut f16, b: float16x4x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -69846,7 +69846,7 @@ pub unsafe fn vst3q_f16(a: *mut f16, b: float16x8x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -69862,7 +69862,7 @@ pub unsafe fn vst3_f32(a: *mut f32, b: float32x2x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -69878,7 +69878,7 @@ pub unsafe fn vst3q_f32(a: *mut f32, b: float32x4x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -69894,7 +69894,7 @@ pub unsafe fn vst3_s8(a: *mut i8, b: int8x8x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -69910,7 +69910,7 @@ pub unsafe fn vst3q_s8(a: *mut i8, b: int8x16x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -69926,7 +69926,7 @@ pub unsafe fn vst3_s16(a: *mut i16, b: int16x4x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -69942,7 +69942,7 @@ pub unsafe fn vst3q_s16(a: *mut i16, b: int16x8x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -69958,7 +69958,7 @@ pub unsafe fn vst3_s32(a: *mut i32, b: int32x2x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -69974,7 +69974,7 @@ pub unsafe fn vst3q_s32(a: *mut i32, b: int32x4x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -69993,7 +69993,7 @@ pub unsafe fn vst3_f32(a: *mut f32, b: float32x2x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -70012,7 +70012,7 @@ pub unsafe fn vst3q_f32(a: *mut f32, b: float32x4x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -70031,7 +70031,7 @@ pub unsafe fn vst3_s8(a: *mut i8, b: int8x8x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -70050,7 +70050,7 @@ pub unsafe fn vst3q_s8(a: *mut i8, b: int8x16x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -70069,7 +70069,7 @@ pub unsafe fn vst3_s16(a: *mut i16, b: int16x4x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -70088,7 +70088,7 @@ pub unsafe fn vst3q_s16(a: *mut i16, b: int16x8x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -70107,7 +70107,7 @@ pub unsafe fn vst3_s32(a: *mut i32, b: int32x2x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -70126,7 +70126,7 @@ pub unsafe fn vst3q_s32(a: *mut i32, b: int32x4x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -70154,7 +70154,7 @@ pub unsafe fn vst3_lane_f16<const LANE: i32>(a: *mut f16, b: float16x4x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -70182,7 +70182,7 @@ pub unsafe fn vst3q_lane_f16<const LANE: i32>(a: *mut f16, b: float16x8x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -70205,7 +70205,7 @@ pub unsafe fn vst3_lane_f16<const LANE: i32>(a: *mut f16, b: float16x4x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -70228,7 +70228,7 @@ pub unsafe fn vst3q_lane_f16<const LANE: i32>(a: *mut f16, b: float16x8x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -70253,7 +70253,7 @@ pub unsafe fn vst3_lane_f32<const LANE: i32>(a: *mut f32, b: float32x2x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -70278,7 +70278,7 @@ pub unsafe fn vst3q_lane_f32<const LANE: i32>(a: *mut f32, b: float32x4x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -70296,7 +70296,7 @@ pub unsafe fn vst3_lane_s8<const LANE: i32>(a: *mut i8, b: int8x8x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -70321,7 +70321,7 @@ pub unsafe fn vst3_lane_s16<const LANE: i32>(a: *mut i16, b: int16x4x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -70346,7 +70346,7 @@ pub unsafe fn vst3q_lane_s16<const LANE: i32>(a: *mut i16, b: int16x8x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -70371,7 +70371,7 @@ pub unsafe fn vst3_lane_s32<const LANE: i32>(a: *mut i32, b: int32x2x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -70396,7 +70396,7 @@ pub unsafe fn vst3q_lane_s32<const LANE: i32>(a: *mut i32, b: int32x4x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -70417,7 +70417,7 @@ pub unsafe fn vst3_lane_f32<const LANE: i32>(a: *mut f32, b: float32x2x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -70438,7 +70438,7 @@ pub unsafe fn vst3q_lane_f32<const LANE: i32>(a: *mut f32, b: float32x4x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -70459,7 +70459,7 @@ pub unsafe fn vst3_lane_s8<const LANE: i32>(a: *mut i8, b: int8x8x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -70480,7 +70480,7 @@ pub unsafe fn vst3_lane_s16<const LANE: i32>(a: *mut i16, b: int16x4x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -70501,7 +70501,7 @@ pub unsafe fn vst3q_lane_s16<const LANE: i32>(a: *mut i16, b: int16x8x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -70522,7 +70522,7 @@ pub unsafe fn vst3_lane_s32<const LANE: i32>(a: *mut i32, b: int32x2x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -70543,7 +70543,7 @@ pub unsafe fn vst3q_lane_s32<const LANE: i32>(a: *mut i32, b: int32x4x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -70568,7 +70568,7 @@ pub unsafe fn vst3_lane_u8<const LANE: i32>(a: *mut u8, b: uint8x8x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -70593,7 +70593,7 @@ pub unsafe fn vst3_lane_u16<const LANE: i32>(a: *mut u16, b: uint16x4x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -70618,7 +70618,7 @@ pub unsafe fn vst3q_lane_u16<const LANE: i32>(a: *mut u16, b: uint16x8x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_u32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -70643,7 +70643,7 @@ pub unsafe fn vst3_lane_u32<const LANE: i32>(a: *mut u32, b: uint32x2x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_u32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -70668,7 +70668,7 @@ pub unsafe fn vst3q_lane_u32<const LANE: i32>(a: *mut u32, b: uint32x4x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -70693,7 +70693,7 @@ pub unsafe fn vst3_lane_p8<const LANE: i32>(a: *mut p8, b: poly8x8x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -70718,7 +70718,7 @@ pub unsafe fn vst3_lane_p16<const LANE: i32>(a: *mut p16, b: poly16x4x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -70743,7 +70743,7 @@ pub unsafe fn vst3q_lane_p16<const LANE: i32>(a: *mut p16, b: poly16x8x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_p64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[target_feature(enable = "neon,aes")]
@@ -70766,7 +70766,7 @@ pub unsafe fn vst3_p64(a: *mut p64, b: poly64x1x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -70785,7 +70785,7 @@ pub unsafe fn vst3_s64(a: *mut i64, b: int64x1x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -70801,7 +70801,7 @@ pub unsafe fn vst3_s64(a: *mut i64, b: int64x1x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_u64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -70824,7 +70824,7 @@ pub unsafe fn vst3_u64(a: *mut u64, b: uint64x1x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -70847,7 +70847,7 @@ pub unsafe fn vst3_u8(a: *mut u8, b: uint8x8x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -70870,7 +70870,7 @@ pub unsafe fn vst3q_u8(a: *mut u8, b: uint8x16x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -70893,7 +70893,7 @@ pub unsafe fn vst3_u16(a: *mut u16, b: uint16x4x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -70916,7 +70916,7 @@ pub unsafe fn vst3q_u16(a: *mut u16, b: uint16x8x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_u32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -70939,7 +70939,7 @@ pub unsafe fn vst3_u32(a: *mut u32, b: uint32x2x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_u32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -70962,7 +70962,7 @@ pub unsafe fn vst3q_u32(a: *mut u32, b: uint32x4x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -70985,7 +70985,7 @@ pub unsafe fn vst3_p8(a: *mut p8, b: poly8x8x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -71008,7 +71008,7 @@ pub unsafe fn vst3q_p8(a: *mut p8, b: poly8x16x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -71031,7 +71031,7 @@ pub unsafe fn vst3_p16(a: *mut p16, b: poly16x4x3_t) {
 #[doc = "Store multiple 3-element structures from three registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -71054,7 +71054,7 @@ pub unsafe fn vst3q_p16(a: *mut p16, b: poly16x8x3_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -71080,7 +71080,7 @@ pub unsafe fn vst4_f16(a: *mut f16, b: float16x4x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -71106,7 +71106,7 @@ pub unsafe fn vst4q_f16(a: *mut f16, b: float16x8x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -71127,7 +71127,7 @@ pub unsafe fn vst4_f16(a: *mut f16, b: float16x4x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -71148,7 +71148,7 @@ pub unsafe fn vst4q_f16(a: *mut f16, b: float16x8x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -71171,7 +71171,7 @@ pub unsafe fn vst4_f32(a: *mut f32, b: float32x2x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -71194,7 +71194,7 @@ pub unsafe fn vst4q_f32(a: *mut f32, b: float32x4x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -71210,7 +71210,7 @@ pub unsafe fn vst4_s8(a: *mut i8, b: int8x8x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -71233,7 +71233,7 @@ pub unsafe fn vst4q_s8(a: *mut i8, b: int8x16x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -71256,7 +71256,7 @@ pub unsafe fn vst4_s16(a: *mut i16, b: int16x4x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -71279,7 +71279,7 @@ pub unsafe fn vst4q_s16(a: *mut i16, b: int16x8x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -71302,7 +71302,7 @@ pub unsafe fn vst4_s32(a: *mut i32, b: int32x2x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -71325,7 +71325,7 @@ pub unsafe fn vst4q_s32(a: *mut i32, b: int32x4x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -71344,7 +71344,7 @@ pub unsafe fn vst4_f32(a: *mut f32, b: float32x2x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -71363,7 +71363,7 @@ pub unsafe fn vst4q_f32(a: *mut f32, b: float32x4x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -71382,7 +71382,7 @@ pub unsafe fn vst4_s8(a: *mut i8, b: int8x8x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -71401,7 +71401,7 @@ pub unsafe fn vst4q_s8(a: *mut i8, b: int8x16x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -71420,7 +71420,7 @@ pub unsafe fn vst4_s16(a: *mut i16, b: int16x4x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -71439,7 +71439,7 @@ pub unsafe fn vst4q_s16(a: *mut i16, b: int16x8x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -71458,7 +71458,7 @@ pub unsafe fn vst4_s32(a: *mut i32, b: int32x2x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -71477,7 +71477,7 @@ pub unsafe fn vst4q_s32(a: *mut i32, b: int32x4x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -71506,7 +71506,7 @@ pub unsafe fn vst4_lane_f16<const LANE: i32>(a: *mut f16, b: float16x4x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(target_arch = "arm")]
@@ -71535,7 +71535,7 @@ pub unsafe fn vst4q_lane_f16<const LANE: i32>(a: *mut f16, b: float16x8x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -71565,7 +71565,7 @@ pub unsafe fn vst4_lane_f16<const LANE: i32>(a: *mut f16, b: float16x4x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_f16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -71595,7 +71595,7 @@ pub unsafe fn vst4q_lane_f16<const LANE: i32>(a: *mut f16, b: float16x8x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -71621,7 +71621,7 @@ pub unsafe fn vst4_lane_f32<const LANE: i32>(a: *mut f32, b: float32x2x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -71647,7 +71647,7 @@ pub unsafe fn vst4q_lane_f32<const LANE: i32>(a: *mut f32, b: float32x4x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -71673,7 +71673,7 @@ pub unsafe fn vst4_lane_s8<const LANE: i32>(a: *mut i8, b: int8x8x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -71699,7 +71699,7 @@ pub unsafe fn vst4_lane_s16<const LANE: i32>(a: *mut i16, b: int16x4x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -71725,7 +71725,7 @@ pub unsafe fn vst4q_lane_s16<const LANE: i32>(a: *mut i16, b: int16x8x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -71751,7 +71751,7 @@ pub unsafe fn vst4_lane_s32<const LANE: i32>(a: *mut i32, b: int32x2x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -71777,7 +71777,7 @@ pub unsafe fn vst4q_lane_s32<const LANE: i32>(a: *mut i32, b: int32x4x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -71805,7 +71805,7 @@ pub unsafe fn vst4_lane_f32<const LANE: i32>(a: *mut f32, b: float32x2x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_f32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -71833,7 +71833,7 @@ pub unsafe fn vst4q_lane_f32<const LANE: i32>(a: *mut f32, b: float32x4x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -71854,7 +71854,7 @@ pub unsafe fn vst4_lane_s8<const LANE: i32>(a: *mut i8, b: int8x8x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -71882,7 +71882,7 @@ pub unsafe fn vst4_lane_s16<const LANE: i32>(a: *mut i16, b: int16x4x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_s16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -71910,7 +71910,7 @@ pub unsafe fn vst4q_lane_s16<const LANE: i32>(a: *mut i16, b: int16x8x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -71938,7 +71938,7 @@ pub unsafe fn vst4_lane_s32<const LANE: i32>(a: *mut i32, b: int32x2x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_s32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -71966,7 +71966,7 @@ pub unsafe fn vst4q_lane_s32<const LANE: i32>(a: *mut i32, b: int32x4x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -71991,7 +71991,7 @@ pub unsafe fn vst4_lane_u8<const LANE: i32>(a: *mut u8, b: uint8x8x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -72016,7 +72016,7 @@ pub unsafe fn vst4_lane_u16<const LANE: i32>(a: *mut u16, b: uint16x4x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -72041,7 +72041,7 @@ pub unsafe fn vst4q_lane_u16<const LANE: i32>(a: *mut u16, b: uint16x8x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_u32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -72066,7 +72066,7 @@ pub unsafe fn vst4_lane_u32<const LANE: i32>(a: *mut u32, b: uint32x2x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_u32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -72091,7 +72091,7 @@ pub unsafe fn vst4q_lane_u32<const LANE: i32>(a: *mut u32, b: uint32x4x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -72116,7 +72116,7 @@ pub unsafe fn vst4_lane_p8<const LANE: i32>(a: *mut p8, b: poly8x8x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -72141,7 +72141,7 @@ pub unsafe fn vst4_lane_p16<const LANE: i32>(a: *mut p16, b: poly16x4x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -72166,7 +72166,7 @@ pub unsafe fn vst4q_lane_p16<const LANE: i32>(a: *mut p16, b: poly16x8x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_p64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[target_feature(enable = "neon,aes")]
@@ -72189,7 +72189,7 @@ pub unsafe fn vst4_p64(a: *mut p64, b: poly64x1x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[cfg(target_arch = "arm")]
 #[target_feature(enable = "neon,v7")]
@@ -72212,7 +72212,7 @@ pub unsafe fn vst4_s64(a: *mut i64, b: int64x1x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg(not(target_arch = "arm"))]
@@ -72231,7 +72231,7 @@ pub unsafe fn vst4_s64(a: *mut i64, b: int64x1x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_u64)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -72254,7 +72254,7 @@ pub unsafe fn vst4_u64(a: *mut u64, b: uint64x1x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -72277,7 +72277,7 @@ pub unsafe fn vst4_u8(a: *mut u8, b: uint8x8x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_u8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -72300,7 +72300,7 @@ pub unsafe fn vst4q_u8(a: *mut u8, b: uint8x16x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -72323,7 +72323,7 @@ pub unsafe fn vst4_u16(a: *mut u16, b: uint16x4x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_u16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -72346,7 +72346,7 @@ pub unsafe fn vst4q_u16(a: *mut u16, b: uint16x8x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_u32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -72369,7 +72369,7 @@ pub unsafe fn vst4_u32(a: *mut u32, b: uint32x2x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_u32)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -72392,7 +72392,7 @@ pub unsafe fn vst4q_u32(a: *mut u32, b: uint32x4x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -72415,7 +72415,7 @@ pub unsafe fn vst4_p8(a: *mut p8, b: poly8x8x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_p8)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -72438,7 +72438,7 @@ pub unsafe fn vst4q_p8(a: *mut p8, b: poly8x16x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -72461,7 +72461,7 @@ pub unsafe fn vst4_p16(a: *mut p16, b: poly16x4x4_t) {
 #[doc = "Store multiple 4-element structures from four registers"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_p16)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
@@ -72484,7 +72484,7 @@ pub unsafe fn vst4q_p16(a: *mut p16, b: poly16x8x4_t) {
 #[doc = "Store SIMD&FP register (immediate offset)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstrq_p128)"]
 #[doc = "## Safety"]
-#[doc = "  * Neon instrinsic unsafe"]
+#[doc = "  * Neon intrinsic unsafe"]
 #[inline(always)]
 #[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
diff --git a/library/stdarch/crates/stdarch-gen-arm/src/intrinsic.rs b/library/stdarch/crates/stdarch-gen-arm/src/intrinsic.rs
index 71301c5ba6ce..ce427d54b355 100644
--- a/library/stdarch/crates/stdarch-gen-arm/src/intrinsic.rs
+++ b/library/stdarch/crates/stdarch-gen-arm/src/intrinsic.rs
@@ -840,7 +840,7 @@ impl fmt::Display for UnsafetyComment {
     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
         match self {
             Self::Custom(s) => s.fmt(f),
-            Self::Neon => write!(f, "Neon instrinsic unsafe"),
+            Self::Neon => write!(f, "Neon intrinsic unsafe"),
             Self::Uninitialized => write!(
                 f,
                 "This creates an uninitialized value, and may be unsound (like \

From 4a0c044c63bde5ba242772bc8c712444c29e4176 Mon Sep 17 00:00:00 2001
From: Jonathan Brouwer <jonathantbrouwer@gmail.com>
Date: Tue, 27 Jan 2026 13:05:38 +0100
Subject: [PATCH 82/97] Update stderrs

---
 ...diagnostic-derive-doc-comment-field.stderr |   8 +-
 .../diagnostic-derive.stderr                  | 218 +++++++-------
 .../subdiagnostic-derive-2.rs                 |  37 +++
 .../subdiagnostic-derive-2.stderr             |   9 +
 .../subdiagnostic-derive.rs                   |  13 -
 .../subdiagnostic-derive.stderr               | 272 +++++++++---------
 6 files changed, 289 insertions(+), 268 deletions(-)
 create mode 100644 tests/ui-fulldeps/session-diagnostic/subdiagnostic-derive-2.rs
 create mode 100644 tests/ui-fulldeps/session-diagnostic/subdiagnostic-derive-2.stderr

diff --git a/tests/ui-fulldeps/session-diagnostic/diagnostic-derive-doc-comment-field.stderr b/tests/ui-fulldeps/session-diagnostic/diagnostic-derive-doc-comment-field.stderr
index 316f23888bc1..0b00e098f6d4 100644
--- a/tests/ui-fulldeps/session-diagnostic/diagnostic-derive-doc-comment-field.stderr
+++ b/tests/ui-fulldeps/session-diagnostic/diagnostic-derive-doc-comment-field.stderr
@@ -1,5 +1,5 @@
 error[E0277]: the trait bound `NotIntoDiagArg: IntoDiagArg` is not satisfied
-  --> $DIR/diagnostic-derive-doc-comment-field.rs:36:10
+  --> $DIR/diagnostic-derive-doc-comment-field.rs:37:10
    |
 LL | #[derive(Diagnostic)]
    |          ---------- required by a bound introduced by this call
@@ -8,7 +8,7 @@ LL |     arg: NotIntoDiagArg,
    |          ^^^^^^^^^^^^^^ unsatisfied trait bound
    |
 help: the nightly-only, unstable trait `IntoDiagArg` is not implemented for `NotIntoDiagArg`
-  --> $DIR/diagnostic-derive-doc-comment-field.rs:28:1
+  --> $DIR/diagnostic-derive-doc-comment-field.rs:29:1
    |
 LL | struct NotIntoDiagArg;
    | ^^^^^^^^^^^^^^^^^^^^^
@@ -21,7 +21,7 @@ note: required by a bound in `Diag::<'a, G>::arg`
    = note: this error originates in the macro `with_fn` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error[E0277]: the trait bound `NotIntoDiagArg: IntoDiagArg` is not satisfied
-  --> $DIR/diagnostic-derive-doc-comment-field.rs:46:10
+  --> $DIR/diagnostic-derive-doc-comment-field.rs:47:10
    |
 LL | #[derive(Subdiagnostic)]
    |          ------------- required by a bound introduced by this call
@@ -30,7 +30,7 @@ LL |     arg: NotIntoDiagArg,
    |          ^^^^^^^^^^^^^^ unsatisfied trait bound
    |
 help: the nightly-only, unstable trait `IntoDiagArg` is not implemented for `NotIntoDiagArg`
-  --> $DIR/diagnostic-derive-doc-comment-field.rs:28:1
+  --> $DIR/diagnostic-derive-doc-comment-field.rs:29:1
    |
 LL | struct NotIntoDiagArg;
    | ^^^^^^^^^^^^^^^^^^^^^
diff --git a/tests/ui-fulldeps/session-diagnostic/diagnostic-derive.stderr b/tests/ui-fulldeps/session-diagnostic/diagnostic-derive.stderr
index 77c48aceca8e..cf5c0c2e6491 100644
--- a/tests/ui-fulldeps/session-diagnostic/diagnostic-derive.stderr
+++ b/tests/ui-fulldeps/session-diagnostic/diagnostic-derive.stderr
@@ -1,11 +1,11 @@
 error: derive(Diagnostic): unsupported type attribute for diagnostic derive enum
-  --> $DIR/diagnostic-derive.rs:47:1
+  --> $DIR/diagnostic-derive.rs:49:1
    |
 LL | #[diag(no_crate_example, code = E0123)]
    | ^
 
 error: derive(Diagnostic): diagnostic slug not specified
-  --> $DIR/diagnostic-derive.rs:50:5
+  --> $DIR/diagnostic-derive.rs:52:5
    |
 LL |     Foo,
    |     ^^^
@@ -13,21 +13,27 @@ LL |     Foo,
    = help: specify the slug as the first argument to the `#[diag(...)]` attribute, such as `#[diag(hir_analysis_example_error)]`
 
 error: derive(Diagnostic): diagnostic slug not specified
-  --> $DIR/diagnostic-derive.rs:52:5
+  --> $DIR/diagnostic-derive.rs:54:5
    |
 LL |     Bar,
    |     ^^^
    |
    = help: specify the slug as the first argument to the `#[diag(...)]` attribute, such as `#[diag(hir_analysis_example_error)]`
 
+error: expected parentheses: #[diag(...)]
+  --> $DIR/diagnostic-derive.rs:60:8
+   |
+LL | #[diag = "E0123"]
+   |        ^
+
 error: derive(Diagnostic): `#[nonsense(...)]` is not a valid attribute
-  --> $DIR/diagnostic-derive.rs:63:1
+  --> $DIR/diagnostic-derive.rs:65:1
    |
 LL | #[nonsense(no_crate_example, code = E0123)]
    | ^
 
 error: derive(Diagnostic): diagnostic slug not specified
-  --> $DIR/diagnostic-derive.rs:63:1
+  --> $DIR/diagnostic-derive.rs:65:1
    |
 LL | #[nonsense(no_crate_example, code = E0123)]
    | ^
@@ -35,7 +41,7 @@ LL | #[nonsense(no_crate_example, code = E0123)]
    = help: specify the slug as the first argument to the `#[diag(...)]` attribute, such as `#[diag(hir_analysis_example_error)]`
 
 error: derive(Diagnostic): diagnostic slug not specified
-  --> $DIR/diagnostic-derive.rs:70:1
+  --> $DIR/diagnostic-derive.rs:72:1
    |
 LL | #[diag(code = E0123)]
    | ^
@@ -43,13 +49,13 @@ LL | #[diag(code = E0123)]
    = help: specify the slug as the first argument to the `#[diag(...)]` attribute, such as `#[diag(hir_analysis_example_error)]`
 
 error: derive(Diagnostic): diagnostic slug must be the first argument
-  --> $DIR/diagnostic-derive.rs:80:16
+  --> $DIR/diagnostic-derive.rs:82:16
    |
 LL | #[diag(nonsense("foo"), code = E0123, slug = "foo")]
    |                ^
 
 error: derive(Diagnostic): diagnostic slug not specified
-  --> $DIR/diagnostic-derive.rs:80:1
+  --> $DIR/diagnostic-derive.rs:82:1
    |
 LL | #[diag(nonsense("foo"), code = E0123, slug = "foo")]
    | ^
@@ -57,7 +63,7 @@ LL | #[diag(nonsense("foo"), code = E0123, slug = "foo")]
    = help: specify the slug as the first argument to the `#[diag(...)]` attribute, such as `#[diag(hir_analysis_example_error)]`
 
 error: derive(Diagnostic): unknown argument
-  --> $DIR/diagnostic-derive.rs:86:8
+  --> $DIR/diagnostic-derive.rs:88:8
    |
 LL | #[diag(nonsense = "...", code = E0123, slug = "foo")]
    |        ^^^^^^^^
@@ -65,7 +71,7 @@ LL | #[diag(nonsense = "...", code = E0123, slug = "foo")]
    = note: only the `code` parameter is valid after the slug
 
 error: derive(Diagnostic): diagnostic slug not specified
-  --> $DIR/diagnostic-derive.rs:86:1
+  --> $DIR/diagnostic-derive.rs:88:1
    |
 LL | #[diag(nonsense = "...", code = E0123, slug = "foo")]
    | ^
@@ -73,7 +79,7 @@ LL | #[diag(nonsense = "...", code = E0123, slug = "foo")]
    = help: specify the slug as the first argument to the `#[diag(...)]` attribute, such as `#[diag(hir_analysis_example_error)]`
 
 error: derive(Diagnostic): unknown argument
-  --> $DIR/diagnostic-derive.rs:92:8
+  --> $DIR/diagnostic-derive.rs:94:8
    |
 LL | #[diag(nonsense = 4, code = E0123, slug = "foo")]
    |        ^^^^^^^^
@@ -81,7 +87,7 @@ LL | #[diag(nonsense = 4, code = E0123, slug = "foo")]
    = note: only the `code` parameter is valid after the slug
 
 error: derive(Diagnostic): diagnostic slug not specified
-  --> $DIR/diagnostic-derive.rs:92:1
+  --> $DIR/diagnostic-derive.rs:94:1
    |
 LL | #[diag(nonsense = 4, code = E0123, slug = "foo")]
    | ^
@@ -89,7 +95,7 @@ LL | #[diag(nonsense = 4, code = E0123, slug = "foo")]
    = help: specify the slug as the first argument to the `#[diag(...)]` attribute, such as `#[diag(hir_analysis_example_error)]`
 
 error: derive(Diagnostic): unknown argument
-  --> $DIR/diagnostic-derive.rs:98:40
+  --> $DIR/diagnostic-derive.rs:100:40
    |
 LL | #[diag(no_crate_example, code = E0123, slug = "foo")]
    |                                        ^^^^
@@ -97,55 +103,55 @@ LL | #[diag(no_crate_example, code = E0123, slug = "foo")]
    = note: only the `code` parameter is valid after the slug
 
 error: derive(Diagnostic): `#[suggestion = ...]` is not a valid attribute
-  --> $DIR/diagnostic-derive.rs:105:5
+  --> $DIR/diagnostic-derive.rs:107:5
    |
 LL |     #[suggestion = "bar"]
    |     ^
 
 error: derive(Diagnostic): attribute specified multiple times
-  --> $DIR/diagnostic-derive.rs:112:8
+  --> $DIR/diagnostic-derive.rs:114:8
    |
 LL | #[diag(no_crate_example, code = E0456)]
    |        ^^^^^^^^^^^^^^^^
    |
 note: previously specified here
-  --> $DIR/diagnostic-derive.rs:111:8
+  --> $DIR/diagnostic-derive.rs:113:8
    |
 LL | #[diag(no_crate_example, code = E0123)]
    |        ^^^^^^^^^^^^^^^^
 
 error: derive(Diagnostic): attribute specified multiple times
-  --> $DIR/diagnostic-derive.rs:112:26
+  --> $DIR/diagnostic-derive.rs:114:26
    |
 LL | #[diag(no_crate_example, code = E0456)]
    |                          ^^^^
    |
 note: previously specified here
-  --> $DIR/diagnostic-derive.rs:111:26
+  --> $DIR/diagnostic-derive.rs:113:26
    |
 LL | #[diag(no_crate_example, code = E0123)]
    |                          ^^^^
 
 error: derive(Diagnostic): attribute specified multiple times
-  --> $DIR/diagnostic-derive.rs:118:40
+  --> $DIR/diagnostic-derive.rs:120:40
    |
 LL | #[diag(no_crate_example, code = E0123, code = E0456)]
    |                                        ^^^^
    |
 note: previously specified here
-  --> $DIR/diagnostic-derive.rs:118:26
+  --> $DIR/diagnostic-derive.rs:120:26
    |
 LL | #[diag(no_crate_example, code = E0123, code = E0456)]
    |                          ^^^^
 
 error: derive(Diagnostic): diagnostic slug must be the first argument
-  --> $DIR/diagnostic-derive.rs:123:43
+  --> $DIR/diagnostic-derive.rs:125:43
    |
 LL | #[diag(no_crate_example, no_crate::example, code = E0123)]
    |                                           ^
 
 error: derive(Diagnostic): diagnostic slug not specified
-  --> $DIR/diagnostic-derive.rs:128:1
+  --> $DIR/diagnostic-derive.rs:130:1
    |
 LL | struct KindNotProvided {}
    | ^^^^^^
@@ -153,7 +159,7 @@ LL | struct KindNotProvided {}
    = help: specify the slug as the first argument to the `#[diag(...)]` attribute, such as `#[diag(hir_analysis_example_error)]`
 
 error: derive(Diagnostic): diagnostic slug not specified
-  --> $DIR/diagnostic-derive.rs:131:1
+  --> $DIR/diagnostic-derive.rs:133:1
    |
 LL | #[diag(code = E0123)]
    | ^
@@ -161,31 +167,31 @@ LL | #[diag(code = E0123)]
    = help: specify the slug as the first argument to the `#[diag(...)]` attribute, such as `#[diag(hir_analysis_example_error)]`
 
 error: derive(Diagnostic): the `#[primary_span]` attribute can only be applied to fields of type `Span` or `MultiSpan`
-  --> $DIR/diagnostic-derive.rs:142:5
+  --> $DIR/diagnostic-derive.rs:144:5
    |
 LL |     #[primary_span]
    |     ^
 
 error: derive(Diagnostic): `#[nonsense]` is not a valid attribute
-  --> $DIR/diagnostic-derive.rs:150:5
+  --> $DIR/diagnostic-derive.rs:152:5
    |
 LL |     #[nonsense]
    |     ^
 
 error: derive(Diagnostic): the `#[label(...)]` attribute can only be applied to fields of type `Span` or `MultiSpan`
-  --> $DIR/diagnostic-derive.rs:167:5
+  --> $DIR/diagnostic-derive.rs:169:5
    |
 LL |     #[label(no_crate_label)]
    |     ^
 
 error: derive(Diagnostic): `name` doesn't refer to a field on this type
-  --> $DIR/diagnostic-derive.rs:175:46
+  --> $DIR/diagnostic-derive.rs:177:46
    |
 LL |     #[suggestion(no_crate_suggestion, code = "{name}")]
    |                                              ^^^^^^^^
 
 error: invalid format string: expected `}` but string was terminated
-  --> $DIR/diagnostic-derive.rs:180:10
+  --> $DIR/diagnostic-derive.rs:182:10
    |
 LL | #[derive(Diagnostic)]
    |          ^^^^^^^^^^ expected `}` in format string
@@ -194,7 +200,7 @@ LL | #[derive(Diagnostic)]
    = note: this error originates in the derive macro `Diagnostic` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error: invalid format string: unmatched `}` found
-  --> $DIR/diagnostic-derive.rs:190:10
+  --> $DIR/diagnostic-derive.rs:192:10
    |
 LL | #[derive(Diagnostic)]
    |          ^^^^^^^^^^ unmatched `}` in format string
@@ -203,19 +209,19 @@ LL | #[derive(Diagnostic)]
    = note: this error originates in the derive macro `Diagnostic` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error: derive(Diagnostic): the `#[label(...)]` attribute can only be applied to fields of type `Span` or `MultiSpan`
-  --> $DIR/diagnostic-derive.rs:210:5
+  --> $DIR/diagnostic-derive.rs:212:5
    |
 LL |     #[label(no_crate_label)]
    |     ^
 
 error: derive(Diagnostic): suggestion without `code = "..."`
-  --> $DIR/diagnostic-derive.rs:229:5
+  --> $DIR/diagnostic-derive.rs:231:5
    |
 LL |     #[suggestion(no_crate_suggestion)]
    |     ^
 
 error: derive(Diagnostic): invalid nested attribute
-  --> $DIR/diagnostic-derive.rs:237:18
+  --> $DIR/diagnostic-derive.rs:239:18
    |
 LL |     #[suggestion(nonsense = "bar")]
    |                  ^^^^^^^^
@@ -223,13 +229,13 @@ LL |     #[suggestion(nonsense = "bar")]
    = help: only `no_span`, `style`, `code` and `applicability` are valid nested attributes
 
 error: derive(Diagnostic): suggestion without `code = "..."`
-  --> $DIR/diagnostic-derive.rs:237:5
+  --> $DIR/diagnostic-derive.rs:239:5
    |
 LL |     #[suggestion(nonsense = "bar")]
    |     ^
 
 error: derive(Diagnostic): invalid nested attribute
-  --> $DIR/diagnostic-derive.rs:246:18
+  --> $DIR/diagnostic-derive.rs:248:18
    |
 LL |     #[suggestion(msg = "bar")]
    |                  ^^^
@@ -237,13 +243,13 @@ LL |     #[suggestion(msg = "bar")]
    = help: only `no_span`, `style`, `code` and `applicability` are valid nested attributes
 
 error: derive(Diagnostic): suggestion without `code = "..."`
-  --> $DIR/diagnostic-derive.rs:246:5
+  --> $DIR/diagnostic-derive.rs:248:5
    |
 LL |     #[suggestion(msg = "bar")]
    |     ^
 
 error: derive(Diagnostic): wrong field type for suggestion
-  --> $DIR/diagnostic-derive.rs:269:5
+  --> $DIR/diagnostic-derive.rs:271:5
    |
 LL |     #[suggestion(no_crate_suggestion, code = "This is suggested code")]
    |     ^
@@ -251,79 +257,79 @@ LL |     #[suggestion(no_crate_suggestion, code = "This is suggested code")]
    = help: `#[suggestion(...)]` should be applied to fields of type `Span` or `(Span, Applicability)`
 
 error: derive(Diagnostic): attribute specified multiple times
-  --> $DIR/diagnostic-derive.rs:285:24
+  --> $DIR/diagnostic-derive.rs:287:24
    |
 LL |     suggestion: (Span, Span, Applicability),
    |                        ^^^^
    |
 note: previously specified here
-  --> $DIR/diagnostic-derive.rs:285:18
+  --> $DIR/diagnostic-derive.rs:287:18
    |
 LL |     suggestion: (Span, Span, Applicability),
    |                  ^^^^
 
 error: derive(Diagnostic): attribute specified multiple times
-  --> $DIR/diagnostic-derive.rs:293:33
+  --> $DIR/diagnostic-derive.rs:295:33
    |
 LL |     suggestion: (Applicability, Applicability, Span),
    |                                 ^^^^^^^^^^^^^
    |
 note: previously specified here
-  --> $DIR/diagnostic-derive.rs:293:18
+  --> $DIR/diagnostic-derive.rs:295:18
    |
 LL |     suggestion: (Applicability, Applicability, Span),
    |                  ^^^^^^^^^^^^^
 
 error: derive(Diagnostic): `#[label = ...]` is not a valid attribute
-  --> $DIR/diagnostic-derive.rs:300:5
+  --> $DIR/diagnostic-derive.rs:302:5
    |
 LL |     #[label = "bar"]
    |     ^
 
 error: derive(Diagnostic): attribute specified multiple times
-  --> $DIR/diagnostic-derive.rs:451:5
+  --> $DIR/diagnostic-derive.rs:453:5
    |
 LL |     #[suggestion(no_crate_suggestion, code = "...", applicability = "maybe-incorrect")]
    |     ^
    |
 note: previously specified here
-  --> $DIR/diagnostic-derive.rs:453:24
+  --> $DIR/diagnostic-derive.rs:455:24
    |
 LL |     suggestion: (Span, Applicability),
    |                        ^^^^^^^^^^^^^
 
 error: derive(Diagnostic): invalid applicability
-  --> $DIR/diagnostic-derive.rs:459:69
+  --> $DIR/diagnostic-derive.rs:461:69
    |
 LL |     #[suggestion(no_crate_suggestion, code = "...", applicability = "batman")]
    |                                                                     ^^^^^^^^
 
 error: derive(Diagnostic): the `#[help(...)]` attribute can only be applied to fields of type `Span`, `MultiSpan`, `bool` or `()`
-  --> $DIR/diagnostic-derive.rs:526:5
+  --> $DIR/diagnostic-derive.rs:528:5
    |
 LL |     #[help(no_crate_help)]
    |     ^
 
 error: derive(Diagnostic): a diagnostic slug must be the first argument to the attribute
-  --> $DIR/diagnostic-derive.rs:535:32
+  --> $DIR/diagnostic-derive.rs:537:32
    |
 LL |     #[label(no_crate_label, foo)]
    |                                ^
 
 error: derive(Diagnostic): only `no_span` is a valid nested attribute
-  --> $DIR/diagnostic-derive.rs:543:29
+  --> $DIR/diagnostic-derive.rs:545:29
    |
 LL |     #[label(no_crate_label, foo = "...")]
    |                             ^^^
 
 error: derive(Diagnostic): only `no_span` is a valid nested attribute
-  --> $DIR/diagnostic-derive.rs:551:29
+  --> $DIR/diagnostic-derive.rs:553:29
    |
 LL |     #[label(no_crate_label, foo("..."))]
    |                             ^^^
 
 error: derive(Diagnostic): `#[primary_span]` is not a valid attribute
-  --> $DIR/diagnostic-derive.rs:563:5
+  --> $DIR/diagnostic-derive.rs:565:5
    |
 LL |     #[primary_span]
    |     ^
@@ -331,13 +337,13 @@ LL |     #[primary_span]
    = help: the `primary_span` field attribute is not valid for lint diagnostics
 
 error: derive(Diagnostic): `#[error(...)]` is not a valid attribute
-  --> $DIR/diagnostic-derive.rs:583:1
+  --> $DIR/diagnostic-derive.rs:585:1
    |
 LL | #[error(no_crate_example, code = E0123)]
    | ^
 
 error: derive(Diagnostic): diagnostic slug not specified
-  --> $DIR/diagnostic-derive.rs:583:1
+  --> $DIR/diagnostic-derive.rs:585:1
    |
 LL | #[error(no_crate_example, code = E0123)]
    | ^
@@ -345,13 +351,13 @@ LL | #[error(no_crate_example, code = E0123)]
    = help: specify the slug as the first argument to the `#[diag(...)]` attribute, such as `#[diag(hir_analysis_example_error)]`
 
 error: derive(Diagnostic): `#[warn_(...)]` is not a valid attribute
-  --> $DIR/diagnostic-derive.rs:590:1
+  --> $DIR/diagnostic-derive.rs:592:1
    |
 LL | #[warn_(no_crate_example, code = E0123)]
    | ^
 
 error: derive(Diagnostic): diagnostic slug not specified
-  --> $DIR/diagnostic-derive.rs:590:1
+  --> $DIR/diagnostic-derive.rs:592:1
    |
 LL | #[warn_(no_crate_example, code = E0123)]
    | ^
@@ -359,13 +365,13 @@ LL | #[warn_(no_crate_example, code = E0123)]
    = help: specify the slug as the first argument to the `#[diag(...)]` attribute, such as `#[diag(hir_analysis_example_error)]`
 
 error: derive(Diagnostic): `#[lint(...)]` is not a valid attribute
-  --> $DIR/diagnostic-derive.rs:597:1
+  --> $DIR/diagnostic-derive.rs:599:1
    |
 LL | #[lint(no_crate_example, code = E0123)]
    | ^
 
 error: derive(Diagnostic): diagnostic slug not specified
-  --> $DIR/diagnostic-derive.rs:597:1
+  --> $DIR/diagnostic-derive.rs:599:1
    |
 LL | #[lint(no_crate_example, code = E0123)]
    | ^
@@ -373,13 +379,13 @@ LL | #[lint(no_crate_example, code = E0123)]
    = help: specify the slug as the first argument to the `#[diag(...)]` attribute, such as `#[diag(hir_analysis_example_error)]`
 
 error: derive(Diagnostic): `#[lint(...)]` is not a valid attribute
-  --> $DIR/diagnostic-derive.rs:604:1
+  --> $DIR/diagnostic-derive.rs:606:1
    |
 LL | #[lint(no_crate_example, code = E0123)]
    | ^
 
 error: derive(Diagnostic): diagnostic slug not specified
-  --> $DIR/diagnostic-derive.rs:604:1
+  --> $DIR/diagnostic-derive.rs:606:1
    |
 LL | #[lint(no_crate_example, code = E0123)]
    | ^
@@ -387,19 +393,19 @@ LL | #[lint(no_crate_example, code = E0123)]
    = help: specify the slug as the first argument to the `#[diag(...)]` attribute, such as `#[diag(hir_analysis_example_error)]`
 
 error: derive(Diagnostic): attribute specified multiple times
-  --> $DIR/diagnostic-derive.rs:613:53
+  --> $DIR/diagnostic-derive.rs:615:53
    |
 LL |     #[suggestion(no_crate_suggestion, code = "...", code = ",,,")]
    |                                                     ^^^^
    |
 note: previously specified here
-  --> $DIR/diagnostic-derive.rs:613:39
+  --> $DIR/diagnostic-derive.rs:615:39
    |
 LL |     #[suggestion(no_crate_suggestion, code = "...", code = ",,,")]
    |                                       ^^^^
 
 error: derive(Diagnostic): wrong types for suggestion
-  --> $DIR/diagnostic-derive.rs:622:24
+  --> $DIR/diagnostic-derive.rs:624:24
    |
 LL |     suggestion: (Span, usize),
    |                        ^^^^^
@@ -407,7 +413,7 @@ LL |     suggestion: (Span, usize),
    = help: `#[suggestion(...)]` on a tuple field must be applied to fields of type `(Span, Applicability)`
 
 error: derive(Diagnostic): wrong types for suggestion
-  --> $DIR/diagnostic-derive.rs:630:17
+  --> $DIR/diagnostic-derive.rs:632:17
    |
 LL |     suggestion: (Span,),
    |                 ^^^^^^^
@@ -415,13 +421,13 @@ LL |     suggestion: (Span,),
    = help: `#[suggestion(...)]` on a tuple field must be applied to fields of type `(Span, Applicability)`
 
 error: derive(Diagnostic): suggestion without `code = "..."`
-  --> $DIR/diagnostic-derive.rs:637:5
+  --> $DIR/diagnostic-derive.rs:639:5
    |
 LL |     #[suggestion(no_crate_suggestion)]
    |     ^
 
 error: derive(Diagnostic): `#[multipart_suggestion(...)]` is not a valid attribute
-  --> $DIR/diagnostic-derive.rs:644:1
+  --> $DIR/diagnostic-derive.rs:646:1
    |
 LL | #[multipart_suggestion(no_crate_suggestion)]
    | ^
@@ -429,7 +435,7 @@ LL | #[multipart_suggestion(no_crate_suggestion)]
    = help: consider creating a `Subdiagnostic` instead
 
 error: derive(Diagnostic): `#[multipart_suggestion(...)]` is not a valid attribute
-  --> $DIR/diagnostic-derive.rs:647:1
+  --> $DIR/diagnostic-derive.rs:649:1
    |
 LL | #[multipart_suggestion()]
    | ^
@@ -437,7 +443,7 @@ LL | #[multipart_suggestion()]
    = help: consider creating a `Subdiagnostic` instead
 
 error: derive(Diagnostic): `#[multipart_suggestion(...)]` is not a valid attribute
-  --> $DIR/diagnostic-derive.rs:651:5
+  --> $DIR/diagnostic-derive.rs:653:5
    |
 LL |     #[multipart_suggestion(no_crate_suggestion)]
    |     ^
@@ -445,7 +451,7 @@ LL |     #[multipart_suggestion(no_crate_suggestion)]
    = help: consider creating a `Subdiagnostic` instead
 
 error: derive(Diagnostic): `#[suggestion(...)]` is not a valid attribute
-  --> $DIR/diagnostic-derive.rs:659:1
+  --> $DIR/diagnostic-derive.rs:661:1
    |
 LL | #[suggestion(no_crate_suggestion, code = "...")]
    | ^
@@ -453,7 +459,7 @@ LL | #[suggestion(no_crate_suggestion, code = "...")]
    = help: `#[label]` and `#[suggestion]` can only be applied to fields
 
 error: derive(Diagnostic): `#[label]` is not a valid attribute
-  --> $DIR/diagnostic-derive.rs:668:1
+  --> $DIR/diagnostic-derive.rs:670:1
    |
 LL | #[label]
    | ^
@@ -461,61 +467,73 @@ LL | #[label]
    = help: `#[label]` and `#[suggestion]` can only be applied to fields
 
 error: derive(Diagnostic): `#[subdiagnostic(...)]` is not a valid attribute
-  --> $DIR/diagnostic-derive.rs:702:5
+  --> $DIR/diagnostic-derive.rs:704:5
    |
 LL |     #[subdiagnostic(bad)]
    |     ^
 
 error: derive(Diagnostic): `#[subdiagnostic = ...]` is not a valid attribute
-  --> $DIR/diagnostic-derive.rs:710:5
+  --> $DIR/diagnostic-derive.rs:712:5
    |
 LL |     #[subdiagnostic = "bad"]
    |     ^
 
 error: derive(Diagnostic): `#[subdiagnostic(...)]` is not a valid attribute
-  --> $DIR/diagnostic-derive.rs:718:5
+  --> $DIR/diagnostic-derive.rs:720:5
    |
 LL |     #[subdiagnostic(bad, bad)]
    |     ^
 
 error: derive(Diagnostic): `#[subdiagnostic(...)]` is not a valid attribute
-  --> $DIR/diagnostic-derive.rs:726:5
+  --> $DIR/diagnostic-derive.rs:728:5
    |
 LL |     #[subdiagnostic("bad")]
    |     ^
 
 error: derive(Diagnostic): `#[subdiagnostic(...)]` is not a valid attribute
-  --> $DIR/diagnostic-derive.rs:734:5
+  --> $DIR/diagnostic-derive.rs:736:5
    |
 LL |     #[subdiagnostic(eager)]
    |     ^
 
 error: derive(Diagnostic): `#[subdiagnostic(...)]` is not a valid attribute
-  --> $DIR/diagnostic-derive.rs:742:5
+  --> $DIR/diagnostic-derive.rs:744:5
    |
 LL |     #[subdiagnostic(eager)]
    |     ^
 
 error: derive(Diagnostic): `#[subdiagnostic(...)]` is not a valid attribute
-  --> $DIR/diagnostic-derive.rs:763:5
+  --> $DIR/diagnostic-derive.rs:765:5
    |
 LL |     #[subdiagnostic(eager)]
    |     ^
 
 error: derive(Diagnostic): expected at least one string literal for `code(...)`
-  --> $DIR/diagnostic-derive.rs:794:23
+  --> $DIR/diagnostic-derive.rs:796:23
    |
 LL |     #[suggestion(code())]
    |                       ^
 
 error: derive(Diagnostic): `code(...)` must contain only string literals
-  --> $DIR/diagnostic-derive.rs:802:23
+  --> $DIR/diagnostic-derive.rs:804:23
    |
 LL |     #[suggestion(code(foo))]
    |                       ^^^
 
+error: unexpected token, expected `)`
+  --> $DIR/diagnostic-derive.rs:804:23
+   |
+LL |     #[suggestion(code(foo))]
+   |                       ^^^
+
+error: expected string literal
+  --> $DIR/diagnostic-derive.rs:813:25
+   |
+LL |     #[suggestion(code = 3)]
+   |                         ^
+
 error: derive(Diagnostic): `#[suggestion(...)]` is not a valid attribute
-  --> $DIR/diagnostic-derive.rs:826:5
+  --> $DIR/diagnostic-derive.rs:828:5
    |
 LL |     #[suggestion(no_crate_suggestion, code = "")]
    |     ^
@@ -524,38 +542,20 @@ LL |     #[suggestion(no_crate_suggestion, code = "")]
    = help: to show a suggestion consisting of multiple parts, use a `Subdiagnostic` annotated with `#[multipart_suggestion(...)]`
    = help: to show a variable set of suggestions, use a `Vec` of `Subdiagnostic`s annotated with `#[suggestion(...)]`
 
-error[E0433]: failed to resolve: you might be missing crate `core`
-  --> $DIR/diagnostic-derive.rs:58:8
-   |
-LL | #[diag = "E0123"]
-   |        ^ you might be missing crate `core`
-
-error[E0433]: failed to resolve: you might be missing crate `core`
-  --> $DIR/diagnostic-derive.rs:802:23
-   |
-LL |     #[suggestion(code(foo))]
-   |                       ^^^ you might be missing crate `core`
-
-error[E0433]: failed to resolve: you might be missing crate `core`
-  --> $DIR/diagnostic-derive.rs:811:25
-   |
-LL |     #[suggestion(code = 3)]
-   |                         ^ you might be missing crate `core`
-
 error: cannot find attribute `nonsense` in this scope
-  --> $DIR/diagnostic-derive.rs:63:3
+  --> $DIR/diagnostic-derive.rs:65:3
    |
 LL | #[nonsense(no_crate_example, code = E0123)]
    |   ^^^^^^^^
 
 error: cannot find attribute `nonsense` in this scope
-  --> $DIR/diagnostic-derive.rs:150:7
+  --> $DIR/diagnostic-derive.rs:152:7
    |
 LL |     #[nonsense]
    |       ^^^^^^^^
 
 error: cannot find attribute `error` in this scope
-  --> $DIR/diagnostic-derive.rs:583:3
+  --> $DIR/diagnostic-derive.rs:585:3
    |
 LL | #[error(no_crate_example, code = E0123)]
    |   ^^^^^
@@ -567,7 +567,7 @@ LL | struct ErrorAttribute {}
    |
 
 error: cannot find attribute `warn_` in this scope
-  --> $DIR/diagnostic-derive.rs:590:3
+  --> $DIR/diagnostic-derive.rs:592:3
    |
 LL | #[warn_(no_crate_example, code = E0123)]
    |   ^^^^^
@@ -579,7 +579,7 @@ LL + #[warn(no_crate_example, code = E0123)]
    |
 
 error: cannot find attribute `lint` in this scope
-  --> $DIR/diagnostic-derive.rs:597:3
+  --> $DIR/diagnostic-derive.rs:599:3
    |
 LL | #[lint(no_crate_example, code = E0123)]
    |   ^^^^
@@ -591,7 +591,7 @@ LL + #[link(no_crate_example, code = E0123)]
    |
 
 error: cannot find attribute `lint` in this scope
-  --> $DIR/diagnostic-derive.rs:604:3
+  --> $DIR/diagnostic-derive.rs:606:3
    |
 LL | #[lint(no_crate_example, code = E0123)]
    |   ^^^^
@@ -603,7 +603,7 @@ LL + #[link(no_crate_example, code = E0123)]
    |
 
 error: cannot find attribute `multipart_suggestion` in this scope
-  --> $DIR/diagnostic-derive.rs:644:3
+  --> $DIR/diagnostic-derive.rs:646:3
    |
 LL | #[multipart_suggestion(no_crate_suggestion)]
    |   ^^^^^^^^^^^^^^^^^^^^
@@ -615,7 +615,7 @@ LL | struct MultipartSuggestion {
    |
 
 error: cannot find attribute `multipart_suggestion` in this scope
-  --> $DIR/diagnostic-derive.rs:647:3
+  --> $DIR/diagnostic-derive.rs:649:3
    |
 LL | #[multipart_suggestion()]
    |   ^^^^^^^^^^^^^^^^^^^^
@@ -627,7 +627,7 @@ LL | struct MultipartSuggestion {
    |
 
 error: cannot find attribute `multipart_suggestion` in this scope
-  --> $DIR/diagnostic-derive.rs:651:7
+  --> $DIR/diagnostic-derive.rs:653:7
    |
 LL |     #[multipart_suggestion(no_crate_suggestion)]
    |       ^^^^^^^^^^^^^^^^^^^^
@@ -635,13 +635,13 @@ LL |     #[multipart_suggestion(no_crate_suggestion)]
    = note: `multipart_suggestion` is an attribute that can be used by the derive macro `Subdiagnostic`, you might be missing a `derive` attribute
 
 error[E0425]: cannot find value `nonsense` in module `crate::fluent_generated`
-  --> $DIR/diagnostic-derive.rs:75:8
+  --> $DIR/diagnostic-derive.rs:77:8
    |
 LL | #[diag(nonsense, code = E0123)]
    |        ^^^^^^^^ not found in `crate::fluent_generated`
 
 error[E0425]: cannot find value `__code_34` in this scope
-  --> $DIR/diagnostic-derive.rs:808:10
+  --> $DIR/diagnostic-derive.rs:810:10
    |
 LL | #[derive(Diagnostic)]
    |          ^^^^^^^^^^ not found in this scope
@@ -649,7 +649,7 @@ LL | #[derive(Diagnostic)]
    = note: this error originates in the derive macro `Diagnostic` (in Nightly builds, run with -Z macro-backtrace for more info)
 
 error[E0277]: the trait bound `Hello: IntoDiagArg` is not satisfied
-  --> $DIR/diagnostic-derive.rs:349:12
+  --> $DIR/diagnostic-derive.rs:351:12
    |
 LL | #[derive(Diagnostic)]
    |          ---------- required by a bound introduced by this call
@@ -658,7 +658,7 @@ LL |     other: Hello,
    |            ^^^^^ unsatisfied trait bound
    |
 help: the nightly-only, unstable trait `IntoDiagArg` is not implemented for `Hello`
-  --> $DIR/diagnostic-derive.rs:40:1
+  --> $DIR/diagnostic-derive.rs:42:1
    |
 LL | struct Hello {}
    | ^^^^^^^^^^^^
@@ -672,5 +672,5 @@ note: required by a bound in `Diag::<'a, G>::arg`
 
 error: aborting due to 85 previous errors
 
-Some errors have detailed explanations: E0277, E0425, E0433.
+Some errors have detailed explanations: E0277, E0425.
 For more information about an error, try `rustc --explain E0277`.
diff --git a/tests/ui-fulldeps/session-diagnostic/subdiagnostic-derive-2.rs b/tests/ui-fulldeps/session-diagnostic/subdiagnostic-derive-2.rs
new file mode 100644
index 000000000000..f42fe1689842
--- /dev/null
+++ b/tests/ui-fulldeps/session-diagnostic/subdiagnostic-derive-2.rs
@@ -0,0 +1,37 @@
+//@ check-fail
+// Tests error conditions for specifying subdiagnostics using #[derive(Subdiagnostic)].
+// This test is split off from the main `subdiagnostic-derive`,
+// because this error is generated post-expansion.
+
+// The proc_macro2 crate handles spans differently when on beta/stable release rather than nightly,
+// changing the output of this test. Since Subdiagnostic is strictly internal to the compiler
+// the test is just ignored on stable and beta:
+//@ ignore-stage1
+//@ ignore-beta
+//@ ignore-stable
+
+#![feature(rustc_private)]
+#![crate_type = "lib"]
+
+extern crate rustc_errors;
+extern crate rustc_fluent_macro;
+extern crate rustc_macros;
+extern crate rustc_session;
+extern crate rustc_span;
+extern crate core;
+
+use rustc_errors::{Applicability, DiagMessage, SubdiagMessage};
+use rustc_macros::Subdiagnostic;
+use rustc_span::Span;
+
+rustc_fluent_macro::fluent_messages! { "./example.ftl" }
+
+#[derive(Subdiagnostic)]
+#[label(slug)]
+//~^ ERROR cannot find value `slug` in module `crate::fluent_generated`
+//~^^ NOTE not found in `crate::fluent_generated`
+struct L {
+    #[primary_span]
+    span: Span,
+    var: String,
+}
diff --git a/tests/ui-fulldeps/session-diagnostic/subdiagnostic-derive-2.stderr b/tests/ui-fulldeps/session-diagnostic/subdiagnostic-derive-2.stderr
new file mode 100644
index 000000000000..37566e39fcd6
--- /dev/null
+++ b/tests/ui-fulldeps/session-diagnostic/subdiagnostic-derive-2.stderr
@@ -0,0 +1,9 @@
+error[E0425]: cannot find value `slug` in module `crate::fluent_generated`
+  --> $DIR/subdiagnostic-derive-2.rs:30:9
+   |
+LL | #[label(slug)]
+   |         ^^^^ not found in `crate::fluent_generated`
+
+error: aborting due to 1 previous error
+
+For more information about this error, try `rustc --explain E0425`.
diff --git a/tests/ui-fulldeps/session-diagnostic/subdiagnostic-derive.rs b/tests/ui-fulldeps/session-diagnostic/subdiagnostic-derive.rs
index 6481e8a3307c..941668ad602e 100644
--- a/tests/ui-fulldeps/session-diagnostic/subdiagnostic-derive.rs
+++ b/tests/ui-fulldeps/session-diagnostic/subdiagnostic-derive.rs
@@ -122,16 +122,6 @@ struct K {
     var: String,
 }
 
-#[derive(Subdiagnostic)]
-#[label(slug)]
-//~^ ERROR cannot find value `slug` in module `crate::fluent_generated`
-//~^^ NOTE not found in `crate::fluent_generated`
-struct L {
-    #[primary_span]
-    span: Span,
-    var: String,
-}
-
 #[derive(Subdiagnostic)]
 #[label()]
 //~^ ERROR diagnostic slug must be first argument of a `#[label(...)]` attribute
@@ -707,9 +697,6 @@ struct BP {
 }
 
 #[derive(Subdiagnostic)]
-//~^ ERROR cannot find value `__code_29` in this scope
-//~| NOTE in this expansion
-//~| NOTE not found in this scope
 #[multipart_suggestion(no_crate_example)]
 struct BQ {
     #[suggestion_part(code = 3)]
diff --git a/tests/ui-fulldeps/session-diagnostic/subdiagnostic-derive.stderr b/tests/ui-fulldeps/session-diagnostic/subdiagnostic-derive.stderr
index 0ae7ba4c4973..c31da4421d25 100644
--- a/tests/ui-fulldeps/session-diagnostic/subdiagnostic-derive.stderr
+++ b/tests/ui-fulldeps/session-diagnostic/subdiagnostic-derive.stderr
@@ -1,39 +1,45 @@
 error: derive(Diagnostic): label without `#[primary_span]` field
-  --> $DIR/subdiagnostic-derive.rs:51:1
+  --> $DIR/subdiagnostic-derive.rs:52:1
    |
 LL | #[label(no_crate_example)]
    | ^
 
 error: derive(Diagnostic): diagnostic slug must be first argument of a `#[label(...)]` attribute
-  --> $DIR/subdiagnostic-derive.rs:58:1
+  --> $DIR/subdiagnostic-derive.rs:59:1
    |
 LL | #[label]
    | ^
 
 error: derive(Diagnostic): `#[foo]` is not a valid attribute
-  --> $DIR/subdiagnostic-derive.rs:67:1
+  --> $DIR/subdiagnostic-derive.rs:68:1
    |
 LL | #[foo]
    | ^
 
 error: derive(Diagnostic): `#[label = ...]` is not a valid attribute
-  --> $DIR/subdiagnostic-derive.rs:77:1
+  --> $DIR/subdiagnostic-derive.rs:78:1
    |
 LL | #[label = "..."]
    | ^
 
 error: derive(Diagnostic): only `no_span` is a valid nested attribute
-  --> $DIR/subdiagnostic-derive.rs:86:9
+  --> $DIR/subdiagnostic-derive.rs:87:9
    |
 LL | #[label(bug = "...")]
    |         ^^^
 
 error: derive(Diagnostic): diagnostic slug must be first argument of a `#[label(...)]` attribute
-  --> $DIR/subdiagnostic-derive.rs:86:1
+  --> $DIR/subdiagnostic-derive.rs:87:1
    |
 LL | #[label(bug = "...")]
    | ^
 
+error: unexpected literal in nested attribute, expected ident
+  --> $DIR/subdiagnostic-derive.rs:97:9
+   |
+LL | #[label("...")]
+   |         ^^^^^
+
 error: derive(Diagnostic): only `no_span` is a valid nested attribute
   --> $DIR/subdiagnostic-derive.rs:106:9
    |
@@ -59,85 +65,85 @@ LL | #[label(slug("..."))]
    | ^
 
 error: derive(Diagnostic): diagnostic slug must be first argument of a `#[label(...)]` attribute
-  --> $DIR/subdiagnostic-derive.rs:136:1
+  --> $DIR/subdiagnostic-derive.rs:126:1
    |
 LL | #[label()]
    | ^
 
 error: derive(Diagnostic): only `no_span` is a valid nested attribute
-  --> $DIR/subdiagnostic-derive.rs:145:27
+  --> $DIR/subdiagnostic-derive.rs:135:27
    |
 LL | #[label(no_crate_example, code = "...")]
    |                           ^^^^
 
 error: derive(Diagnostic): only `no_span` is a valid nested attribute
-  --> $DIR/subdiagnostic-derive.rs:154:27
+  --> $DIR/subdiagnostic-derive.rs:144:27
    |
 LL | #[label(no_crate_example, applicability = "machine-applicable")]
    |                           ^^^^^^^^^^^^^
 
 error: derive(Diagnostic): unsupported type attribute for subdiagnostic enum
-  --> $DIR/subdiagnostic-derive.rs:163:1
+  --> $DIR/subdiagnostic-derive.rs:153:1
    |
 LL | #[foo]
    | ^
 
 error: derive(Diagnostic): `#[bar]` is not a valid attribute
-  --> $DIR/subdiagnostic-derive.rs:177:5
+  --> $DIR/subdiagnostic-derive.rs:167:5
    |
 LL |     #[bar]
    |     ^
 
 error: derive(Diagnostic): `#[bar = ...]` is not a valid attribute
-  --> $DIR/subdiagnostic-derive.rs:189:5
+  --> $DIR/subdiagnostic-derive.rs:179:5
    |
 LL |     #[bar = "..."]
    |     ^
 
 error: derive(Diagnostic): `#[bar = ...]` is not a valid attribute
-  --> $DIR/subdiagnostic-derive.rs:201:5
+  --> $DIR/subdiagnostic-derive.rs:191:5
    |
 LL |     #[bar = 4]
    |     ^
 
 error: derive(Diagnostic): `#[bar(...)]` is not a valid attribute
-  --> $DIR/subdiagnostic-derive.rs:213:5
+  --> $DIR/subdiagnostic-derive.rs:203:5
    |
 LL |     #[bar("...")]
    |     ^
 
 error: derive(Diagnostic): only `no_span` is a valid nested attribute
-  --> $DIR/subdiagnostic-derive.rs:225:13
+  --> $DIR/subdiagnostic-derive.rs:215:13
    |
 LL |     #[label(code = "...")]
    |             ^^^^
 
 error: derive(Diagnostic): diagnostic slug must be first argument of a `#[label(...)]` attribute
-  --> $DIR/subdiagnostic-derive.rs:225:5
+  --> $DIR/subdiagnostic-derive.rs:215:5
    |
 LL |     #[label(code = "...")]
    |     ^
 
 error: derive(Diagnostic): the `#[primary_span]` attribute can only be applied to fields of type `Span` or `MultiSpan`
-  --> $DIR/subdiagnostic-derive.rs:254:5
+  --> $DIR/subdiagnostic-derive.rs:244:5
    |
 LL |     #[primary_span]
    |     ^
 
 error: derive(Diagnostic): label without `#[primary_span]` field
-  --> $DIR/subdiagnostic-derive.rs:251:1
+  --> $DIR/subdiagnostic-derive.rs:241:1
    |
 LL | #[label(no_crate_example)]
    | ^
 
 error: derive(Diagnostic): `#[applicability]` is only valid on suggestions
-  --> $DIR/subdiagnostic-derive.rs:264:5
+  --> $DIR/subdiagnostic-derive.rs:254:5
    |
 LL |     #[applicability]
    |     ^
 
 error: derive(Diagnostic): `#[bar]` is not a valid attribute
-  --> $DIR/subdiagnostic-derive.rs:274:5
+  --> $DIR/subdiagnostic-derive.rs:264:5
    |
 LL |     #[bar]
    |     ^
@@ -145,111 +151,121 @@ LL |     #[bar]
    = help: only `primary_span`, `applicability` and `skip_arg` are valid field attributes
 
 error: derive(Diagnostic): `#[bar = ...]` is not a valid attribute
-  --> $DIR/subdiagnostic-derive.rs:285:5
+  --> $DIR/subdiagnostic-derive.rs:275:5
    |
 LL |     #[bar = "..."]
    |     ^
 
 error: derive(Diagnostic): `#[bar(...)]` is not a valid attribute
-  --> $DIR/subdiagnostic-derive.rs:296:5
+  --> $DIR/subdiagnostic-derive.rs:286:5
    |
 LL |     #[bar("...")]
    |     ^
    |
    = help: only `primary_span`, `applicability` and `skip_arg` are valid field attributes
 
+error: unexpected unsupported untagged union
+  --> $DIR/subdiagnostic-derive.rs:302:1
+   |
+LL | / union AC {
+LL | |
+LL | |     span: u32,
+LL | |     b: u64,
+LL | | }
+   | |_^
+
 error: derive(Diagnostic): a diagnostic slug must be the first argument to the attribute
-  --> $DIR/subdiagnostic-derive.rs:328:44
+  --> $DIR/subdiagnostic-derive.rs:317:44
    |
 LL | #[label(no_crate_example, no_crate::example)]
    |                                            ^
 
 error: derive(Diagnostic): attribute specified multiple times
-  --> $DIR/subdiagnostic-derive.rs:341:5
+  --> $DIR/subdiagnostic-derive.rs:330:5
    |
 LL |     #[primary_span]
    |     ^
    |
 note: previously specified here
-  --> $DIR/subdiagnostic-derive.rs:338:5
+  --> $DIR/subdiagnostic-derive.rs:327:5
    |
 LL |     #[primary_span]
    |     ^
 
 error: derive(Diagnostic): subdiagnostic kind not specified
-  --> $DIR/subdiagnostic-derive.rs:347:8
+  --> $DIR/subdiagnostic-derive.rs:336:8
    |
 LL | struct AG {
    |        ^^
 
 error: derive(Diagnostic): attribute specified multiple times
-  --> $DIR/subdiagnostic-derive.rs:384:46
+  --> $DIR/subdiagnostic-derive.rs:373:46
    |
 LL | #[suggestion(no_crate_example, code = "...", code = "...")]
    |                                              ^^^^
    |
 note: previously specified here
-  --> $DIR/subdiagnostic-derive.rs:384:32
+  --> $DIR/subdiagnostic-derive.rs:373:32
    |
 LL | #[suggestion(no_crate_example, code = "...", code = "...")]
    |                                ^^^^
 
 error: derive(Diagnostic): attribute specified multiple times
-  --> $DIR/subdiagnostic-derive.rs:402:5
+  --> $DIR/subdiagnostic-derive.rs:391:5
    |
 LL |     #[applicability]
    |     ^
    |
 note: previously specified here
-  --> $DIR/subdiagnostic-derive.rs:399:5
+  --> $DIR/subdiagnostic-derive.rs:388:5
    |
 LL |     #[applicability]
    |     ^
 
 error: derive(Diagnostic): the `#[applicability]` attribute can only be applied to fields of type `Applicability`
-  --> $DIR/subdiagnostic-derive.rs:412:5
+  --> $DIR/subdiagnostic-derive.rs:401:5
    |
 LL |     #[applicability]
    |     ^
 
 error: derive(Diagnostic): suggestion without `code = "..."`
-  --> $DIR/subdiagnostic-derive.rs:425:1
+  --> $DIR/subdiagnostic-derive.rs:414:1
    |
 LL | #[suggestion(no_crate_example)]
    | ^
 
 error: derive(Diagnostic): invalid applicability
-  --> $DIR/subdiagnostic-derive.rs:435:62
+  --> $DIR/subdiagnostic-derive.rs:424:62
    |
 LL | #[suggestion(no_crate_example, code = "...", applicability = "foo")]
    |                                                              ^^^^^
 
 error: derive(Diagnostic): suggestion without `#[primary_span]` field
-  --> $DIR/subdiagnostic-derive.rs:453:1
+  --> $DIR/subdiagnostic-derive.rs:442:1
    |
 LL | #[suggestion(no_crate_example, code = "...")]
    | ^
 
 error: derive(Diagnostic): unsupported type attribute for subdiagnostic enum
-  --> $DIR/subdiagnostic-derive.rs:467:1
+  --> $DIR/subdiagnostic-derive.rs:456:1
    |
 LL | #[label]
    | ^
 
 error: derive(Diagnostic): `var` doesn't refer to a field on this type
-  --> $DIR/subdiagnostic-derive.rs:487:39
+  --> $DIR/subdiagnostic-derive.rs:476:39
    |
 LL | #[suggestion(no_crate_example, code = "{var}", applicability = "machine-applicable")]
    |                                       ^^^^^^^
 
 error: derive(Diagnostic): `var` doesn't refer to a field on this type
-  --> $DIR/subdiagnostic-derive.rs:506:43
+  --> $DIR/subdiagnostic-derive.rs:495:43
    |
 LL |     #[suggestion(no_crate_example, code = "{var}", applicability = "machine-applicable")]
    |                                           ^^^^^^^
 
 error: derive(Diagnostic): `#[suggestion_part]` is not a valid attribute
-  --> $DIR/subdiagnostic-derive.rs:529:5
+  --> $DIR/subdiagnostic-derive.rs:518:5
    |
 LL |     #[suggestion_part]
    |     ^
@@ -257,7 +273,7 @@ LL |     #[suggestion_part]
    = help: `#[suggestion_part(...)]` is only valid in multipart suggestions, use `#[primary_span]` instead
 
 error: derive(Diagnostic): `#[suggestion_part(...)]` is not a valid attribute
-  --> $DIR/subdiagnostic-derive.rs:532:5
+  --> $DIR/subdiagnostic-derive.rs:521:5
    |
 LL |     #[suggestion_part(code = "...")]
    |     ^
@@ -265,13 +281,13 @@ LL |     #[suggestion_part(code = "...")]
    = help: `#[suggestion_part(...)]` is only valid in multipart suggestions
 
 error: derive(Diagnostic): suggestion without `#[primary_span]` field
-  --> $DIR/subdiagnostic-derive.rs:526:1
+  --> $DIR/subdiagnostic-derive.rs:515:1
    |
 LL | #[suggestion(no_crate_example, code = "...")]
    | ^
 
 error: derive(Diagnostic): invalid nested attribute
-  --> $DIR/subdiagnostic-derive.rs:541:42
+  --> $DIR/subdiagnostic-derive.rs:530:42
    |
 LL | #[multipart_suggestion(no_crate_example, code = "...", applicability = "machine-applicable")]
    |                                          ^^^^
@@ -279,25 +295,25 @@ LL | #[multipart_suggestion(no_crate_example, code = "...", applicability = "mac
    = help: only `no_span`, `style` and `applicability` are valid nested attributes
 
 error: derive(Diagnostic): multipart suggestion without any `#[suggestion_part(...)]` fields
-  --> $DIR/subdiagnostic-derive.rs:541:1
+  --> $DIR/subdiagnostic-derive.rs:530:1
    |
 LL | #[multipart_suggestion(no_crate_example, code = "...", applicability = "machine-applicable")]
    | ^
 
 error: derive(Diagnostic): `#[suggestion_part(...)]` attribute without `code = "..."`
-  --> $DIR/subdiagnostic-derive.rs:551:5
+  --> $DIR/subdiagnostic-derive.rs:540:5
    |
 LL |     #[suggestion_part]
    |     ^
 
 error: derive(Diagnostic): `#[suggestion_part(...)]` attribute without `code = "..."`
-  --> $DIR/subdiagnostic-derive.rs:559:5
+  --> $DIR/subdiagnostic-derive.rs:548:5
    |
 LL |     #[suggestion_part()]
    |     ^
 
 error: derive(Diagnostic): `#[primary_span]` is not a valid attribute
-  --> $DIR/subdiagnostic-derive.rs:568:5
+  --> $DIR/subdiagnostic-derive.rs:557:5
    |
 LL |     #[primary_span]
    |     ^
@@ -305,97 +321,127 @@ LL |     #[primary_span]
    = help: multipart suggestions use one or more `#[suggestion_part]`s rather than one `#[primary_span]`
 
 error: derive(Diagnostic): multipart suggestion without any `#[suggestion_part(...)]` fields
-  --> $DIR/subdiagnostic-derive.rs:565:1
+  --> $DIR/subdiagnostic-derive.rs:554:1
    |
 LL | #[multipart_suggestion(no_crate_example)]
    | ^
 
 error: derive(Diagnostic): `#[suggestion_part(...)]` attribute without `code = "..."`
-  --> $DIR/subdiagnostic-derive.rs:576:5
+  --> $DIR/subdiagnostic-derive.rs:565:5
    |
 LL |     #[suggestion_part]
    |     ^
 
 error: derive(Diagnostic): `#[suggestion_part(...)]` attribute without `code = "..."`
-  --> $DIR/subdiagnostic-derive.rs:579:5
+  --> $DIR/subdiagnostic-derive.rs:568:5
    |
 LL |     #[suggestion_part()]
    |     ^
 
 error: derive(Diagnostic): `code` is the only valid nested attribute
-  --> $DIR/subdiagnostic-derive.rs:582:23
+  --> $DIR/subdiagnostic-derive.rs:571:23
    |
 LL |     #[suggestion_part(foo = "bar")]
    |                       ^^^
 
 error: derive(Diagnostic): the `#[suggestion_part(...)]` attribute can only be applied to fields of type `Span` or `MultiSpan`
-  --> $DIR/subdiagnostic-derive.rs:587:5
+  --> $DIR/subdiagnostic-derive.rs:575:5
    |
 LL |     #[suggestion_part(code = "...")]
    |     ^
 
 error: derive(Diagnostic): the `#[suggestion_part(...)]` attribute can only be applied to fields of type `Span` or `MultiSpan`
-  --> $DIR/subdiagnostic-derive.rs:590:5
+  --> $DIR/subdiagnostic-derive.rs:578:5
    |
 LL |     #[suggestion_part()]
    |     ^
 
+error: expected `,`
+  --> $DIR/subdiagnostic-derive.rs:571:27
+   |
+LL |     #[suggestion_part(foo = "bar")]
+   |                           ^
+
 error: derive(Diagnostic): attribute specified multiple times
-  --> $DIR/subdiagnostic-derive.rs:598:37
+  --> $DIR/subdiagnostic-derive.rs:586:37
    |
 LL |     #[suggestion_part(code = "...", code = ",,,")]
    |                                     ^^^^
    |
 note: previously specified here
-  --> $DIR/subdiagnostic-derive.rs:598:23
+  --> $DIR/subdiagnostic-derive.rs:586:23
    |
 LL |     #[suggestion_part(code = "...", code = ",,,")]
    |                       ^^^^
 
 error: derive(Diagnostic): `#[applicability]` has no effect if all `#[suggestion]`/`#[multipart_suggestion]` attributes have a static `applicability = "..."`
-  --> $DIR/subdiagnostic-derive.rs:627:5
+  --> $DIR/subdiagnostic-derive.rs:615:5
    |
 LL |     #[applicability]
    |     ^
 
 error: derive(Diagnostic): expected exactly one string literal for `code = ...`
-  --> $DIR/subdiagnostic-derive.rs:675:34
+  --> $DIR/subdiagnostic-derive.rs:663:34
    |
 LL |     #[suggestion_part(code("foo"))]
    |                                  ^
 
+error: unexpected token, expected `)`
+  --> $DIR/subdiagnostic-derive.rs:663:28
+   |
+LL |     #[suggestion_part(code("foo"))]
+   |                            ^^^^^
+
 error: derive(Diagnostic): expected exactly one string literal for `code = ...`
-  --> $DIR/subdiagnostic-derive.rs:686:41
+  --> $DIR/subdiagnostic-derive.rs:673:41
    |
 LL |     #[suggestion_part(code("foo", "bar"))]
    |                                         ^
 
+error: unexpected token, expected `)`
+  --> $DIR/subdiagnostic-derive.rs:673:28
+   |
+LL |     #[suggestion_part(code("foo", "bar"))]
+   |                            ^^^^^
+
 error: derive(Diagnostic): expected exactly one string literal for `code = ...`
-  --> $DIR/subdiagnostic-derive.rs:697:30
+  --> $DIR/subdiagnostic-derive.rs:683:30
    |
 LL |     #[suggestion_part(code(3))]
    |                              ^
 
+error: unexpected token, expected `)`
+  --> $DIR/subdiagnostic-derive.rs:683:28
+   |
+LL |     #[suggestion_part(code(3))]
+   |                            ^
+
 error: derive(Diagnostic): expected exactly one string literal for `code = ...`
-  --> $DIR/subdiagnostic-derive.rs:708:29
+  --> $DIR/subdiagnostic-derive.rs:693:29
    |
 LL |     #[suggestion_part(code())]
    |                             ^
 
+error: expected string literal
+  --> $DIR/subdiagnostic-derive.rs:702:30
+   |
+LL |     #[suggestion_part(code = 3)]
+   |                              ^
+
 error: derive(Diagnostic): attribute specified multiple times
-  --> $DIR/subdiagnostic-derive.rs:763:1
+  --> $DIR/subdiagnostic-derive.rs:744:1
    |
 LL | #[suggestion(no_crate_example, code = "", style = "hidden", style = "normal")]
    | ^
    |
 note: previously specified here
-  --> $DIR/subdiagnostic-derive.rs:763:1
+  --> $DIR/subdiagnostic-derive.rs:744:1
    |
 LL | #[suggestion(no_crate_example, code = "", style = "hidden", style = "normal")]
    | ^
 
 error: derive(Diagnostic): `#[suggestion_hidden(...)]` is not a valid attribute
-  --> $DIR/subdiagnostic-derive.rs:772:1
+  --> $DIR/subdiagnostic-derive.rs:753:1
    |
 LL | #[suggestion_hidden(no_crate_example, code = "")]
    | ^
@@ -403,7 +449,7 @@ LL | #[suggestion_hidden(no_crate_example, code = "")]
    = help: Use `#[suggestion(..., style = "hidden")]` instead
 
 error: derive(Diagnostic): `#[suggestion_hidden(...)]` is not a valid attribute
-  --> $DIR/subdiagnostic-derive.rs:780:1
+  --> $DIR/subdiagnostic-derive.rs:761:1
    |
 LL | #[suggestion_hidden(no_crate_example, code = "", style = "normal")]
    | ^
@@ -411,7 +457,7 @@ LL | #[suggestion_hidden(no_crate_example, code = "", style = "normal")]
    = help: Use `#[suggestion(..., style = "hidden")]` instead
 
 error: derive(Diagnostic): invalid suggestion style
-  --> $DIR/subdiagnostic-derive.rs:788:51
+  --> $DIR/subdiagnostic-derive.rs:769:51
    |
 LL | #[suggestion(no_crate_example, code = "", style = "foo")]
    |                                                   ^^^^^
@@ -419,25 +465,31 @@ LL | #[suggestion(no_crate_example, code = "", style = "foo")]
    = help: valid styles are `normal`, `short`, `hidden`, `verbose` and `tool-only`
 
 error: derive(Diagnostic): expected `= "xxx"`
-  --> $DIR/subdiagnostic-derive.rs:796:49
+  --> $DIR/subdiagnostic-derive.rs:777:49
    |
 LL | #[suggestion(no_crate_example, code = "", style = 42)]
    |                                                 ^
 
 error: derive(Diagnostic): a diagnostic slug must be the first argument to the attribute
-  --> $DIR/subdiagnostic-derive.rs:804:48
+  --> $DIR/subdiagnostic-derive.rs:785:48
    |
 LL | #[suggestion(no_crate_example, code = "", style)]
    |                                                ^
 
 error: derive(Diagnostic): expected `= "xxx"`
-  --> $DIR/subdiagnostic-derive.rs:812:48
+  --> $DIR/subdiagnostic-derive.rs:793:48
+   |
+LL | #[suggestion(no_crate_example, code = "", style("foo"))]
+   |                                                ^
+
+error: expected `,`
+  --> $DIR/subdiagnostic-derive.rs:793:48
    |
 LL | #[suggestion(no_crate_example, code = "", style("foo"))]
    |                                                ^
 
 error: derive(Diagnostic): `#[primary_span]` is not a valid attribute
-  --> $DIR/subdiagnostic-derive.rs:825:5
+  --> $DIR/subdiagnostic-derive.rs:805:5
    |
 LL |     #[primary_span]
    |     ^
@@ -446,128 +498,64 @@ LL |     #[primary_span]
    = help: to create a suggestion with multiple spans, use `#[multipart_suggestion]` instead
 
 error: derive(Diagnostic): suggestion without `#[primary_span]` field
-  --> $DIR/subdiagnostic-derive.rs:822:1
+  --> $DIR/subdiagnostic-derive.rs:802:1
    |
 LL | #[suggestion(no_crate_example, code = "")]
    | ^
 
-error[E0433]: failed to resolve: you might be missing crate `core`
-  --> $DIR/subdiagnostic-derive.rs:96:9
-   |
-LL | #[label("...")]
-   |         ^^^^^ you might be missing crate `core`
-
-error[E0433]: failed to resolve: you might be missing crate `core`
-  --> $DIR/subdiagnostic-derive.rs:312:1
-   |
-LL | union AC {
-   | ^^^^^ you might be missing crate `core`
-
-error[E0433]: failed to resolve: you might be missing crate `core`
-  --> $DIR/subdiagnostic-derive.rs:582:27
-   |
-LL |     #[suggestion_part(foo = "bar")]
-   |                           ^ you might be missing crate `core`
-
-error[E0433]: failed to resolve: you might be missing crate `core`
-  --> $DIR/subdiagnostic-derive.rs:675:28
-   |
-LL |     #[suggestion_part(code("foo"))]
-   |                            ^^^^^ you might be missing crate `core`
-
-error[E0433]: failed to resolve: you might be missing crate `core`
-  --> $DIR/subdiagnostic-derive.rs:686:28
-   |
-LL |     #[suggestion_part(code("foo", "bar"))]
-   |                            ^^^^^ you might be missing crate `core`
-
-error[E0433]: failed to resolve: you might be missing crate `core`
-  --> $DIR/subdiagnostic-derive.rs:697:28
-   |
-LL |     #[suggestion_part(code(3))]
-   |                            ^ you might be missing crate `core`
-
-error[E0433]: failed to resolve: you might be missing crate `core`
-  --> $DIR/subdiagnostic-derive.rs:720:30
-   |
-LL |     #[suggestion_part(code = 3)]
-   |                              ^ you might be missing crate `core`
-
-error[E0433]: failed to resolve: you might be missing crate `core`
-  --> $DIR/subdiagnostic-derive.rs:812:48
-   |
-LL | #[suggestion(no_crate_example, code = "", style("foo"))]
-   |                                                ^ you might be missing crate `core`
-
 error: cannot find attribute `foo` in this scope
-  --> $DIR/subdiagnostic-derive.rs:67:3
+  --> $DIR/subdiagnostic-derive.rs:68:3
    |
 LL | #[foo]
    |   ^^^
 
 error: cannot find attribute `foo` in this scope
-  --> $DIR/subdiagnostic-derive.rs:163:3
+  --> $DIR/subdiagnostic-derive.rs:153:3
    |
 LL | #[foo]
    |   ^^^
 
 error: cannot find attribute `bar` in this scope
-  --> $DIR/subdiagnostic-derive.rs:177:7
+  --> $DIR/subdiagnostic-derive.rs:167:7
    |
 LL |     #[bar]
    |       ^^^
 
 error: cannot find attribute `bar` in this scope
-  --> $DIR/subdiagnostic-derive.rs:189:7
+  --> $DIR/subdiagnostic-derive.rs:179:7
    |
 LL |     #[bar = "..."]
    |       ^^^
 
 error: cannot find attribute `bar` in this scope
-  --> $DIR/subdiagnostic-derive.rs:201:7
+  --> $DIR/subdiagnostic-derive.rs:191:7
    |
 LL |     #[bar = 4]
    |       ^^^
 
 error: cannot find attribute `bar` in this scope
-  --> $DIR/subdiagnostic-derive.rs:213:7
+  --> $DIR/subdiagnostic-derive.rs:203:7
    |
 LL |     #[bar("...")]
    |       ^^^
 
 error: cannot find attribute `bar` in this scope
-  --> $DIR/subdiagnostic-derive.rs:274:7
+  --> $DIR/subdiagnostic-derive.rs:264:7
    |
 LL |     #[bar]
    |       ^^^
 
 error: cannot find attribute `bar` in this scope
-  --> $DIR/subdiagnostic-derive.rs:285:7
+  --> $DIR/subdiagnostic-derive.rs:275:7
    |
 LL |     #[bar = "..."]
    |       ^^^
 
 error: cannot find attribute `bar` in this scope
-  --> $DIR/subdiagnostic-derive.rs:296:7
+  --> $DIR/subdiagnostic-derive.rs:286:7
    |
 LL |     #[bar("...")]
    |       ^^^
 
-error[E0425]: cannot find value `slug` in module `crate::fluent_generated`
-  --> $DIR/subdiagnostic-derive.rs:126:9
-   |
-LL | #[label(slug)]
-   |         ^^^^ not found in `crate::fluent_generated`
+error: aborting due to 84 previous errors
 
-error[E0425]: cannot find value `__code_29` in this scope
-  --> $DIR/subdiagnostic-derive.rs:714:10
-   |
-LL | #[derive(Subdiagnostic)]
-   |          ^^^^^^^^^^^^^ not found in this scope
-   |
-   = note: this error originates in the derive macro `Subdiagnostic` (in Nightly builds, run with -Z macro-backtrace for more info)
-
-error: aborting due to 86 previous errors
-
-Some errors have detailed explanations: E0425, E0433.
-For more information about an error, try `rustc --explain E0425`.

From 7eae36f01734bfcb842b98e361012ed626ce489f Mon Sep 17 00:00:00 2001
From: Manuel Drehwald <git@manuel.drehwald.info>
Date: Fri, 9 Jan 2026 14:10:12 -0800
Subject: [PATCH 83/97] Add an early return if handling multiple offload calls

---
 compiler/rustc_codegen_llvm/src/builder/gpu_offload.rs | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/compiler/rustc_codegen_llvm/src/builder/gpu_offload.rs b/compiler/rustc_codegen_llvm/src/builder/gpu_offload.rs
index 0cf4c1d4f8c7..0cf5ac01d1a7 100644
--- a/compiler/rustc_codegen_llvm/src/builder/gpu_offload.rs
+++ b/compiler/rustc_codegen_llvm/src/builder/gpu_offload.rs
@@ -68,8 +68,15 @@ impl<'ll> OffloadGlobals<'ll> {
 // which we copy from clang, is to just have those two calls once, in the global ctor/dtor section
 // of the final binary.
 pub(crate) fn register_offload<'ll>(cx: &CodegenCx<'ll, '_>) {
+    // First we check quickly whether we already have done our setup, in which case we return early.
+    // Shouldn't be needed for correctness.
+    let register_lib_name = "__tgt_register_lib";
+    if cx.get_function(register_lib_name).is_some() {
+        return;
+    }
+
     let reg_lib_decl = cx.type_func(&[cx.type_ptr()], cx.type_void());
-    let register_lib = declare_offload_fn(&cx, "__tgt_register_lib", reg_lib_decl);
+    let register_lib = declare_offload_fn(&cx, register_lib_name, reg_lib_decl);
     let unregister_lib = declare_offload_fn(&cx, "__tgt_unregister_lib", reg_lib_decl);
 
     let ptr_null = cx.const_null(cx.type_ptr());

From 35ce8ab1204d1fe860d073c20c0f6c4e8012ccb8 Mon Sep 17 00:00:00 2001
From: Manuel Drehwald <git@manuel.drehwald.info>
Date: Fri, 9 Jan 2026 15:41:07 -0800
Subject: [PATCH 84/97] adjust testcase for new logic

---
 .../codegen-llvm/gpu_offload/control_flow.rs  |   3 +-
 tests/codegen-llvm/gpu_offload/gpu_host.rs    | 117 +++++++++---------
 2 files changed, 59 insertions(+), 61 deletions(-)

diff --git a/tests/codegen-llvm/gpu_offload/control_flow.rs b/tests/codegen-llvm/gpu_offload/control_flow.rs
index 28ee9c85b0ed..1a3d3cd7a778 100644
--- a/tests/codegen-llvm/gpu_offload/control_flow.rs
+++ b/tests/codegen-llvm/gpu_offload/control_flow.rs
@@ -12,8 +12,7 @@
 
 // CHECK: define{{( dso_local)?}} void @main()
 // CHECK-NOT: define
-// CHECK: %EmptyDesc = alloca %struct.__tgt_bin_desc, align 8
-// CHECK-NEXT: %.offload_baseptrs = alloca [1 x ptr], align 8
+// CHECK: %.offload_baseptrs = alloca [1 x ptr], align 8
 // CHECK-NEXT: %.offload_ptrs = alloca [1 x ptr], align 8
 // CHECK-NEXT: %.offload_sizes = alloca [1 x i64], align 8
 // CHECK-NEXT: %kernel_args = alloca %struct.__tgt_kernel_arguments, align 8
diff --git a/tests/codegen-llvm/gpu_offload/gpu_host.rs b/tests/codegen-llvm/gpu_offload/gpu_host.rs
index 27ff6f325aa0..d0bc34ec66b2 100644
--- a/tests/codegen-llvm/gpu_offload/gpu_host.rs
+++ b/tests/codegen-llvm/gpu_offload/gpu_host.rs
@@ -2,9 +2,10 @@
 //@ no-prefer-dynamic
 //@ needs-offload
 
-// This test is verifying that we generate __tgt_target_data_*_mapper before and after a call to the
-// kernel_1. Better documentation to what each global or variable means is available in the gpu
-// offload code, or the LLVM offload documentation.
+// This test is verifying that we generate __tgt_target_data_*_mapper before and after a call to
+// __tgt_target_kernel, and initialize all needed variables. It also verifies some related globals.
+// Better documentation to what each global or variable means is available in the gpu offload code,
+// or the LLVM offload documentation.
 
 #![feature(rustc_attrs)]
 #![feature(core_intrinsics)]
@@ -17,10 +18,8 @@ fn main() {
     core::hint::black_box(&x);
 }
 
-#[unsafe(no_mangle)]
-#[inline(never)]
 pub fn kernel_1(x: &mut [f32; 256]) {
-    core::intrinsics::offload(_kernel_1, [256, 1, 1], [32, 1, 1], (x,))
+    core::intrinsics::offload(kernel_1, [256, 1, 1], [32, 1, 1], (x,))
 }
 
 #[unsafe(no_mangle)]
@@ -33,75 +32,75 @@ pub fn _kernel_1(x: &mut [f32; 256]) {
 
 // CHECK: %struct.ident_t = type { i32, i32, i32, i32, ptr }
 // CHECK: %struct.__tgt_offload_entry = type { i64, i16, i16, i32, ptr, ptr, i64, i64, ptr }
-// CHECK: %struct.__tgt_bin_desc = type { i32, ptr, ptr, ptr }
 // CHECK: %struct.__tgt_kernel_arguments = type { i32, i32, ptr, ptr, ptr, ptr, ptr, ptr, i64, i64, [3 x i32], [3 x i32], i32 }
 
-// CHECK: @anon.{{.*}}.0 = private unnamed_addr constant [23 x i8] c";unknown;unknown;0;0;;\00", align 1
-// CHECK: @anon.{{.*}}.1 = private unnamed_addr constant %struct.ident_t { i32 0, i32 2, i32 0, i32 22, ptr @anon.{{.*}}.0 }, align 8
+// CHECK: @anon.[[ID:.*]].0 = private unnamed_addr constant [23 x i8] c";unknown;unknown;0;0;;\00", align 1
+// CHECK: @anon.{{.*}}.1 = private unnamed_addr constant %struct.ident_t { i32 0, i32 2, i32 0, i32 22, ptr @anon.[[ID]].0 }, align 8
 
-// CHECK: @.offload_sizes._kernel_1 = private unnamed_addr constant [1 x i64] [i64 1024]
-// CHECK: @.offload_maptypes._kernel_1 = private unnamed_addr constant [1 x i64] [i64 35]
-// CHECK: @._kernel_1.region_id = internal constant i8 0
-// CHECK: @.offloading.entry_name._kernel_1 = internal unnamed_addr constant [10 x i8] c"_kernel_1\00", section ".llvm.rodata.offloading", align 1
-// CHECK: @.offloading.entry._kernel_1 = internal constant %struct.__tgt_offload_entry { i64 0, i16 1, i16 1, i32 0, ptr @._kernel_1.region_id, ptr @.offloading.entry_name._kernel_1, i64 0, i64 0, ptr null }, section "llvm_offload_entries", align 8
+// CHECK-DAG: @.omp_offloading.descriptor = internal constant { i32, ptr, ptr, ptr } zeroinitializer
+// CHECK-DAG: @llvm.global_ctors = appending constant [1 x { i32, ptr, ptr }] [{ i32, ptr, ptr } { i32 101, ptr @.omp_offloading.descriptor_reg, ptr null }]
+// CHECK-DAG: @.offload_sizes.[[K:[^ ]*kernel_1]] = private unnamed_addr constant [1 x i64] [i64 1024]
+// CHECK-DAG: @.offload_maptypes.[[K]] = private unnamed_addr constant [1 x i64] [i64 35]
+// CHECK-DAG: @.[[K]].region_id = internal constant i8 0
+// CHECK-DAG: @.offloading.entry_name.[[K]] = internal unnamed_addr constant [{{[0-9]+}} x i8] c"[[K]]{{\\00}}", section ".llvm.rodata.offloading", align 1
+// CHECK-DAG: @.offloading.entry.[[K]] = internal constant %struct.__tgt_offload_entry { i64 0, i16 1, i16 1, i32 0, ptr @.[[K]].region_id, ptr @.offloading.entry_name.[[K]], i64 0, i64 0, ptr null }, section "llvm_offload_entries", align 8
 
 // CHECK: declare i32 @__tgt_target_kernel(ptr, i64, i32, i32, ptr, ptr)
-// CHECK: declare void @__tgt_register_lib(ptr) local_unnamed_addr
-// CHECK: declare void @__tgt_unregister_lib(ptr) local_unnamed_addr
 
-// CHECK: define{{( dso_local)?}} void @main()
+// CHECK-LABEL: define{{( dso_local)?}} void @main()
 // CHECK-NEXT: start:
-// CHECK-NEXT:   %0 = alloca [8 x i8], align 8
-// CHECK-NEXT:   %x = alloca [1024 x i8], align 16
-// CHECK:        call void @kernel_1(ptr noalias noundef nonnull align 4 dereferenceable(1024) %x)
-// CHECK-NEXT:   call void @llvm.lifetime.start.p0(i64 8, ptr nonnull %0)
-// CHECK-NEXT:   store ptr %x, ptr %0, align 8
-// CHECK-NEXT:   call void asm sideeffect "", "r,~{memory}"(ptr nonnull %0)
-// CHECK-NEXT:   call void @llvm.lifetime.end.p0(i64 8, ptr nonnull %0)
-// CHECK-NEXT:   call void @llvm.lifetime.end.p0(i64 1024, ptr nonnull %x)
-// CHECK-NEXT:   ret void
-// CHECK-NEXT: }
-
-// CHECK:      define{{( dso_local)?}} void @kernel_1(ptr noalias noundef align 4 dereferenceable(1024) %x)
-// CHECK-NEXT: start:
-// CHECK-NEXT:   %EmptyDesc = alloca %struct.__tgt_bin_desc, align 8
+// CHECK-NEXT:  %0 = alloca [8 x i8], align 8
+// CHECK-NEXT:  %x = alloca [1024 x i8], align 16
 // CHECK-NEXT:   %.offload_baseptrs = alloca [1 x ptr], align 8
 // CHECK-NEXT:   %.offload_ptrs = alloca [1 x ptr], align 8
 // CHECK-NEXT:   %.offload_sizes = alloca [1 x i64], align 8
 // CHECK-NEXT:   %kernel_args = alloca %struct.__tgt_kernel_arguments, align 8
-// CHECK-NEXT:   %dummy = load volatile ptr, ptr @.offload_sizes._kernel_1, align 8
-// CHECK-NEXT:   %dummy1 = load volatile ptr, ptr @.offloading.entry._kernel_1, align 8
-// CHECK-NEXT:   call void @llvm.memset.p0.i64(ptr noundef nonnull align 8 dereferenceable(32) %EmptyDesc, i8 0, i64 32, i1 false)
-// CHECK-NEXT:   call void @__tgt_register_lib(ptr nonnull %EmptyDesc)
+// CHECK:   %dummy = load volatile ptr, ptr @.offload_sizes.[[K]], align 8
+// CHECK-NEXT:   %dummy1 = load volatile ptr, ptr @.offloading.entry.[[K]], align 8
 // CHECK-NEXT:   call void @__tgt_init_all_rtls()
 // CHECK-NEXT:   store ptr %x, ptr %.offload_baseptrs, align 8
 // CHECK-NEXT:   store ptr %x, ptr %.offload_ptrs, align 8
 // CHECK-NEXT:   store i64 1024, ptr %.offload_sizes, align 8
-// CHECK-NEXT:   call void @__tgt_target_data_begin_mapper(ptr nonnull @anon.{{.*}}.1, i64 -1, i32 1, ptr nonnull %.offload_baseptrs, ptr nonnull %.offload_ptrs, ptr nonnull %.offload_sizes, ptr nonnull @.offload_maptypes._kernel_1, ptr null, ptr null)
+// CHECK-NEXT:   call void @__tgt_target_data_begin_mapper(ptr nonnull @anon.{{.*}}.1, i64 -1, i32 1, ptr nonnull %.offload_baseptrs, ptr nonnull %.offload_ptrs, ptr nonnull %.offload_sizes, ptr nonnull @.offload_maptypes.[[K]], ptr null, ptr null)
 // CHECK-NEXT:   store i32 3, ptr %kernel_args, align 8
-// CHECK-NEXT:   %0 = getelementptr inbounds nuw i8, ptr %kernel_args, i64 4
-// CHECK-NEXT:   store i32 1, ptr %0, align 4
-// CHECK-NEXT:   %1 = getelementptr inbounds nuw i8, ptr %kernel_args, i64 8
-// CHECK-NEXT:   store ptr %.offload_baseptrs, ptr %1, align 8
-// CHECK-NEXT:   %2 = getelementptr inbounds nuw i8, ptr %kernel_args, i64 16
-// CHECK-NEXT:   store ptr %.offload_ptrs, ptr %2, align 8
-// CHECK-NEXT:   %3 = getelementptr inbounds nuw i8, ptr %kernel_args, i64 24
-// CHECK-NEXT:   store ptr %.offload_sizes, ptr %3, align 8
-// CHECK-NEXT:   %4 = getelementptr inbounds nuw i8, ptr %kernel_args, i64 32
-// CHECK-NEXT:   store ptr @.offload_maptypes._kernel_1, ptr %4, align 8
-// CHECK-NEXT:   %5 = getelementptr inbounds nuw i8, ptr %kernel_args, i64 40
-// CHECK-NEXT:   %6 = getelementptr inbounds nuw i8, ptr %kernel_args, i64 72
-// CHECK-NEXT:   call void @llvm.memset.p0.i64(ptr noundef nonnull align 8 dereferenceable(32) %5, i8 0, i64 32, i1 false)
-// CHECK-NEXT:   store <4 x i32> <i32 256, i32 1, i32 1, i32 32>, ptr %6, align 8
-// CHECK-NEXT:   %.fca.1.gep5 = getelementptr inbounds nuw i8, ptr %kernel_args, i64 88
-// CHECK-NEXT:   store i32 1, ptr %.fca.1.gep5, align 8
-// CHECK-NEXT:   %.fca.2.gep7 = getelementptr inbounds nuw i8, ptr %kernel_args, i64 92
-// CHECK-NEXT:   store i32 1, ptr %.fca.2.gep7, align 4
-// CHECK-NEXT:   %7 = getelementptr inbounds nuw i8, ptr %kernel_args, i64 96
-// CHECK-NEXT:   store i32 0, ptr %7, align 8
-// CHECK-NEXT:   %8 = call i32 @__tgt_target_kernel(ptr nonnull @anon.{{.*}}.1, i64 -1, i32 256, i32 32, ptr nonnull @._kernel_1.region_id, ptr nonnull %kernel_args)
-// CHECK-NEXT:   call void @__tgt_target_data_end_mapper(ptr nonnull @anon.{{.*}}.1, i64 -1, i32 1, ptr nonnull %.offload_baseptrs, ptr nonnull %.offload_ptrs, ptr nonnull %.offload_sizes, ptr nonnull @.offload_maptypes._kernel_1, ptr null, ptr null)
-// CHECK-NEXT:   call void @__tgt_unregister_lib(ptr nonnull %EmptyDesc)
+// CHECK-NEXT:   [[P4:%[^ ]+]] = getelementptr inbounds nuw i8, ptr %kernel_args, i64 4
+// CHECK-NEXT:   store i32 1, ptr [[P4]], align 4
+// CHECK-NEXT:   [[P8:%[^ ]+]] = getelementptr inbounds nuw i8, ptr %kernel_args, i64 8
+// CHECK-NEXT:   store ptr %.offload_baseptrs, ptr [[P8]], align 8
+// CHECK-NEXT:   [[P16:%[^ ]+]] = getelementptr inbounds nuw i8, ptr %kernel_args, i64 16
+// CHECK-NEXT:   store ptr %.offload_ptrs, ptr [[P16]], align 8
+// CHECK-NEXT:   [[P24:%[^ ]+]] = getelementptr inbounds nuw i8, ptr %kernel_args, i64 24
+// CHECK-NEXT:   store ptr %.offload_sizes, ptr [[P24]], align 8
+// CHECK-NEXT:   [[P32:%[^ ]+]] = getelementptr inbounds nuw i8, ptr %kernel_args, i64 32
+// CHECK-NEXT:   store ptr @.offload_maptypes.[[K]], ptr [[P32]], align 8
+// CHECK-NEXT:   [[P40:%[^ ]+]] = getelementptr inbounds nuw i8, ptr %kernel_args, i64 40
+// CHECK-NEXT:   [[P72:%[^ ]+]] = getelementptr inbounds nuw i8, ptr %kernel_args, i64 72
+// CHECK-NEXT:   call void @llvm.memset.p0.i64(ptr noundef nonnull align 8 dereferenceable(32) [[P40]], i8 0, i64 32, i1 false)
+// CHECK-NEXT:   store <4 x i32> <i32 256, i32 1, i32 1, i32 32>, ptr [[P72]], align 8
+// CHECK-NEXT:   [[P88:%[^ ]+]] = getelementptr inbounds nuw i8, ptr %kernel_args, i64 88
+// CHECK-NEXT:   store i32 1, ptr [[P88]], align 8
+// CHECK-NEXT:   [[P92:%[^ ]+]] = getelementptr inbounds nuw i8, ptr %kernel_args, i64 92
+// CHECK-NEXT:   store i32 1, ptr [[P92]], align 4
+// CHECK-NEXT:   [[P96:%[^ ]+]] = getelementptr inbounds nuw i8, ptr %kernel_args, i64 96
+// CHECK-NEXT:   store i32 0, ptr [[P96]], align 8
+// CHECK-NEXT:   {{%[^ ]+}} = call i32 @__tgt_target_kernel(ptr nonnull @anon.{{.*}}.1, i64 -1, i32 256, i32 32, ptr nonnull @.[[K]].region_id, ptr nonnull %kernel_args)
+// CHECK-NEXT:   call void @__tgt_target_data_end_mapper(ptr nonnull @anon.{{.*}}.1, i64 -1, i32 1, ptr nonnull %.offload_baseptrs, ptr nonnull %.offload_ptrs, ptr nonnull %.offload_sizes, ptr nonnull @.offload_maptypes.[[K]], ptr null, ptr null)
+// CHECK:   ret void
+// CHECK-NEXT: }
+
+// CHECK: declare void @__tgt_register_lib(ptr) local_unnamed_addr
+// CHECK: declare void @__tgt_unregister_lib(ptr) local_unnamed_addr
+
+// CHECK-LABEL: define internal void @.omp_offloading.descriptor_reg() section ".text.startup" {
+// CHECK-NEXT: entry:
+// CHECK-NEXT:   call void @__tgt_register_lib(ptr nonnull @.omp_offloading.descriptor)
+// CHECK-NEXT:   %0 = {{tail }}call i32 @atexit(ptr nonnull @.omp_offloading.descriptor_unreg)
+// CHECK-NEXT:   ret void
+// CHECK-NEXT: }
+
+// CHECK-LABEL: define internal void @.omp_offloading.descriptor_unreg() section ".text.startup" {
+// CHECK-NEXT: entry:
+// CHECK-NEXT:   call void @__tgt_unregister_lib(ptr nonnull @.omp_offloading.descriptor)
 // CHECK-NEXT:   ret void
 // CHECK-NEXT: }
 

From 1f11bf66498150d930df2abef04552c174ab18aa Mon Sep 17 00:00:00 2001
From: Manuel Drehwald <git@manuel.drehwald.info>
Date: Tue, 13 Jan 2026 15:18:49 -0800
Subject: [PATCH 85/97] Leave note to drop tgt_init_all_rtls in the future

---
 compiler/rustc_codegen_llvm/src/builder/gpu_offload.rs | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/compiler/rustc_codegen_llvm/src/builder/gpu_offload.rs b/compiler/rustc_codegen_llvm/src/builder/gpu_offload.rs
index 0cf5ac01d1a7..402861eda870 100644
--- a/compiler/rustc_codegen_llvm/src/builder/gpu_offload.rs
+++ b/compiler/rustc_codegen_llvm/src/builder/gpu_offload.rs
@@ -29,6 +29,8 @@ pub(crate) struct OffloadGlobals<'ll> {
 
     pub ident_t_global: &'ll llvm::Value,
 
+    // FIXME(offload): Drop this, once we fully automated our offload compilation pipeline, since
+    // LLVM will initialize them for us if it sees gpu kernels being registered.
     pub init_rtls: &'ll llvm::Value,
 }
 

From 83dcfc8803225f2666ace25d8448be17351af9fd Mon Sep 17 00:00:00 2001
From: Guillaume Gomez <guillaume1.gomez@gmail.com>
Date: Tue, 27 Jan 2026 21:14:25 +0100
Subject: [PATCH 86/97] Update `browser-ui-test` version to `0.23.3`

---
 package.json | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/package.json b/package.json
index 1fe87b181669..66596cab4268 100644
--- a/package.json
+++ b/package.json
@@ -1,6 +1,6 @@
 {
   "dependencies": {
-    "browser-ui-test": "^0.23.2",
+    "browser-ui-test": "^0.23.3",
     "es-check": "^9.4.4",
     "eslint": "^8.57.1",
     "typescript": "^5.8.3"

From 31d011a399e7d105fb82283c788e55019ecdbaa2 Mon Sep 17 00:00:00 2001
From: andrewtkent <andrew_kent@brown.edu>
Date: Tue, 27 Jan 2026 13:27:30 -0800
Subject: [PATCH 87/97] Add FileCheck annotations to simplify_match.rs

Remove `skip-filecheck` and add FileCheck directives to verify that GVN
propagates the constant `false` and eliminates the match entirely.

The test now verifies:
- The debug info shows `x` as `const false` (constant propagation)
- No `switchInt` remains (match elimination)
- The function body is just `return` (dead code elimination)
---
 tests/mir-opt/simplify_match.rs | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/tests/mir-opt/simplify_match.rs b/tests/mir-opt/simplify_match.rs
index b035b6339fae..ca9dac40aa91 100644
--- a/tests/mir-opt/simplify_match.rs
+++ b/tests/mir-opt/simplify_match.rs
@@ -1,9 +1,15 @@
-// skip-filecheck
+//! Test that GVN propagates the constant `false` and eliminates the match.
 // EMIT_MIR_FOR_EACH_PANIC_STRATEGY
+
 #[inline(never)]
 fn noop() {}
 
 // EMIT_MIR simplify_match.main.GVN.diff
+// CHECK-LABEL: fn main(
+// CHECK: debug x => const false;
+// CHECK-NOT: switchInt
+// CHECK: bb0: {
+// CHECK-NEXT: return;
 fn main() {
     match {
         let x = false;

From 6165b72b5f1992c8290142cf2e99cffeb1d49d10 Mon Sep 17 00:00:00 2001
From: Jynn Nelson <jynn.nelson@ferrous-systems.com>
Date: Wed, 14 Jan 2026 11:38:58 -0500
Subject: [PATCH 88/97] Fix `x fix`, again

This was refactored incorrectly at some point and would run `cargo check`
even for `x fix`.
---
 src/bootstrap/src/core/build_steps/check.rs | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/bootstrap/src/core/build_steps/check.rs b/src/bootstrap/src/core/build_steps/check.rs
index f983c59f9bf8..8bbd03ac3afa 100644
--- a/src/bootstrap/src/core/build_steps/check.rs
+++ b/src/bootstrap/src/core/build_steps/check.rs
@@ -87,7 +87,7 @@ impl Step for Std {
             Mode::Std,
             SourceType::InTree,
             target,
-            Kind::Check,
+            builder.config.cmd.kind(),
         );
 
         std_cargo(builder, target, &mut cargo, &self.crates);
@@ -97,7 +97,7 @@ impl Step for Std {
         }
 
         let _guard = builder.msg(
-            Kind::Check,
+            builder.config.cmd.kind(),
             format_args!("library artifacts{}", crate_description(&self.crates)),
             Mode::Std,
             build_compiler,

From 35ccf1847726e3f0b62c6fa55f3979dfe5c1d533 Mon Sep 17 00:00:00 2001
From: Guillaume Gomez <guillaume1.gomez@gmail.com>
Date: Wed, 21 Jan 2026 11:46:49 +0100
Subject: [PATCH 89/97] Add regression test for #151411

---
 .../deprecated-note-from-reexported.rs        | 17 ++++++++++++
 .../deprecated-note-from-reexported.stderr    | 27 ++++++++++++++++++-
 2 files changed, 43 insertions(+), 1 deletion(-)

diff --git a/tests/rustdoc-ui/intra-doc/deprecated-note-from-reexported.rs b/tests/rustdoc-ui/intra-doc/deprecated-note-from-reexported.rs
index 3d1e48a4c638..91447e5fa166 100644
--- a/tests/rustdoc-ui/intra-doc/deprecated-note-from-reexported.rs
+++ b/tests/rustdoc-ui/intra-doc/deprecated-note-from-reexported.rs
@@ -14,3 +14,20 @@ pub mod bar {
     //~| ERROR: unresolved link
     pub fn sql_function_proc() {}
 }
+
+// From here, this is a regression test for <https://github.com/rust-lang/rust/issues/151411>.
+pub use fuzz_test_helpers::*;
+
+/// A type referenced in the deprecation note.
+pub struct Env;
+
+impl Env {
+    pub fn try_invoke(&self) {}
+}
+
+mod fuzz_test_helpers {
+    #[deprecated(note = "use [Env::try_invoke] instead")]
+    //~^ ERROR: unresolved link
+    //~| ERROR: unresolved link
+    pub fn fuzz_catch_panic() {}
+}
diff --git a/tests/rustdoc-ui/intra-doc/deprecated-note-from-reexported.stderr b/tests/rustdoc-ui/intra-doc/deprecated-note-from-reexported.stderr
index 25f10b24d9fb..cb7a5f0c6e02 100644
--- a/tests/rustdoc-ui/intra-doc/deprecated-note-from-reexported.stderr
+++ b/tests/rustdoc-ui/intra-doc/deprecated-note-from-reexported.stderr
@@ -16,6 +16,18 @@ note: the lint level is defined here
 LL | #![deny(rustdoc::broken_intra_doc_links)]
    |         ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
+error: unresolved link to `Env::try_invoke`
+  --> $DIR/deprecated-note-from-reexported.rs:29:25
+   |
+LL |     #[deprecated(note = "use [Env::try_invoke] instead")]
+   |                         ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+   |
+   = note: the link appears in this line:
+           
+           use [Env::try_invoke] instead
+                ^^^^^^^^^^^^^^^
+   = note: no item named `Env` in scope
+
 error: unresolved link to `define_sql_function`
   --> $DIR/deprecated-note-from-reexported.rs:12:25
    |
@@ -30,5 +42,18 @@ LL |     #[deprecated(note = "Use [`define_sql_function`] instead")]
    = help: to escape `[` and `]` characters, add '\' before them like `\[` or `\]`
    = note: duplicate diagnostic emitted due to `-Z deduplicate-diagnostics=no`
 
-error: aborting due to 2 previous errors
+error: unresolved link to `Env::try_invoke`
+  --> $DIR/deprecated-note-from-reexported.rs:29:25
+   |
+LL |     #[deprecated(note = "use [Env::try_invoke] instead")]
+   |                         ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+   |
+   = note: the link appears in this line:
+           
+           use [Env::try_invoke] instead
+                ^^^^^^^^^^^^^^^
+   = note: no item named `Env` in scope
+   = note: duplicate diagnostic emitted due to `-Z deduplicate-diagnostics=no`
+
+error: aborting due to 4 previous errors
 

From a1893d3187e2f983ff9d97a752d6a0c179f778b2 Mon Sep 17 00:00:00 2001
From: theiz <theizaboss@gmail.com>
Date: Tue, 27 Jan 2026 19:49:09 -0400
Subject: [PATCH 90/97] Add support for `trait object` types in `type_info`
 reflection

---
 .../src/const_eval/dyn_trait.rs               | 178 ++++++++++++++++++
 .../rustc_const_eval/src/const_eval/mod.rs    |   1 +
 .../src/const_eval/type_info.rs               |   7 +-
 compiler/rustc_span/src/symbol.rs             |   5 +
 library/core/src/mem/type_info.rs             |  32 ++++
 library/coretests/tests/mem/type_info.rs      | 129 +++++++++++++
 .../multiple-dep-versions.stderr              |  12 +-
 ...prefix-diagnostics.not-diag-in-deps.stderr |   2 +-
 ...-diagnostics.only-debuginfo-in-deps.stderr |   2 +-
 ...refix-diagnostics.only-diag-in-deps.stderr |   2 +-
 ...prefix-diagnostics.only-doc-in-deps.stderr |   2 +-
 ...efix-diagnostics.only-macro-in-deps.stderr |   2 +-
 ...-diagnostics.with-debuginfo-in-deps.stderr |   2 +-
 ...refix-diagnostics.with-diag-in-deps.stderr |   2 +-
 ...prefix-diagnostics.with-doc-in-deps.stderr |   2 +-
 ...efix-diagnostics.with-macro-in-deps.stderr |   2 +-
 tests/ui/privacy/private-inferred-type.rs     |   4 +-
 tests/ui/privacy/private-inferred-type.stderr |   4 +-
 .../suggest-maybe-sized-bound.stderr          |   2 +-
 .../bound/on-structs-and-enums-xc.stderr      |   8 +-
 .../bound/on-structs-and-enums-xc1.stderr     |   8 +-
 ...-multiple-different-versions-of-a-crate.rs |   4 +-
 ...tiple-different-versions-of-a-crate.stderr |   4 +-
 .../unresolved/unresolved-candidates.stderr   |   4 +-
 .../unstable_impl_coherence.disabled.stderr   |   4 +-
 .../unstable_impl_coherence.enabled.stderr    |   4 +-
 .../unstable_impl_coherence.rs                |   2 +-
 .../unstable_impl_method_selection.stderr     |   6 +-
 tests/ui/use/issue-18986.stderr               |   5 +
 29 files changed, 399 insertions(+), 42 deletions(-)
 create mode 100644 compiler/rustc_const_eval/src/const_eval/dyn_trait.rs

diff --git a/compiler/rustc_const_eval/src/const_eval/dyn_trait.rs b/compiler/rustc_const_eval/src/const_eval/dyn_trait.rs
new file mode 100644
index 000000000000..0976a7283ef3
--- /dev/null
+++ b/compiler/rustc_const_eval/src/const_eval/dyn_trait.rs
@@ -0,0 +1,178 @@
+use rustc_middle::mir::interpret::{CtfeProvenance, InterpResult, Scalar, interp_ok};
+use rustc_middle::ty::{Region, Ty};
+use rustc_middle::{span_bug, ty};
+use rustc_span::def_id::DefId;
+use rustc_span::sym;
+
+use crate::const_eval::CompileTimeMachine;
+use crate::interpret::{Immediate, InterpCx, MPlaceTy, MemoryKind, Writeable};
+impl<'tcx> InterpCx<'tcx, CompileTimeMachine<'tcx>> {
+    pub(crate) fn write_dyn_trait_type_info(
+        &mut self,
+        dyn_place: impl Writeable<'tcx, CtfeProvenance>,
+        data: &'tcx ty::List<ty::Binder<'tcx, ty::ExistentialPredicate<'tcx>>>,
+        region: Region<'tcx>,
+    ) -> InterpResult<'tcx> {
+        let tcx = self.tcx.tcx;
+
+        // Find the principal trait ref (for super trait collection), collect auto traits,
+        // and collect all projection predicates (used when computing TypeId for each supertrait).
+        let mut principal: Option<ty::Binder<'tcx, ty::ExistentialTraitRef<'tcx>>> = None;
+        let mut auto_traits_def_ids: Vec<ty::Binder<'tcx, DefId>> = Vec::new();
+        let mut projections: Vec<ty::Binder<'tcx, ty::ExistentialProjection<'tcx>>> = Vec::new();
+
+        for b in data.iter() {
+            match b.skip_binder() {
+                ty::ExistentialPredicate::Trait(tr) => principal = Some(b.rebind(tr)),
+                ty::ExistentialPredicate::AutoTrait(did) => auto_traits_def_ids.push(b.rebind(did)),
+                ty::ExistentialPredicate::Projection(p) => projections.push(b.rebind(p)),
+            }
+        }
+
+        // This is to make principal dyn type include Trait and projection predicates, excluding auto traits.
+        let principal_ty: Option<Ty<'tcx>> = principal.map(|_tr| {
+            let preds = tcx
+                .mk_poly_existential_predicates_from_iter(data.iter().filter(|b| {
+                    !matches!(b.skip_binder(), ty::ExistentialPredicate::AutoTrait(_))
+                }));
+            Ty::new_dynamic(tcx, preds, region)
+        });
+
+        // DynTrait { predicates: &'static [Trait] }
+        for (field_idx, field) in
+            dyn_place.layout().ty.ty_adt_def().unwrap().non_enum_variant().fields.iter_enumerated()
+        {
+            let field_place = self.project_field(&dyn_place, field_idx)?;
+            match field.name {
+                sym::predicates => {
+                    self.write_dyn_trait_predicates_slice(
+                        &field_place,
+                        principal_ty,
+                        &auto_traits_def_ids,
+                        region,
+                    )?;
+                }
+                other => {
+                    span_bug!(self.tcx.def_span(field.did), "unimplemented DynTrait field {other}")
+                }
+            }
+        }
+
+        interp_ok(())
+    }
+
+    fn mk_dyn_principal_auto_trait_ty(
+        &self,
+        auto_trait_def_id: ty::Binder<'tcx, DefId>,
+        region: Region<'tcx>,
+    ) -> Ty<'tcx> {
+        let tcx = self.tcx.tcx;
+
+        // Preserve the binder vars from the original auto-trait predicate.
+        let pred_inner = ty::ExistentialPredicate::AutoTrait(auto_trait_def_id.skip_binder());
+        let pred = ty::Binder::bind_with_vars(pred_inner, auto_trait_def_id.bound_vars());
+
+        let preds = tcx.mk_poly_existential_predicates_from_iter([pred].into_iter());
+        Ty::new_dynamic(tcx, preds, region)
+    }
+
+    fn write_dyn_trait_predicates_slice(
+        &mut self,
+        slice_place: &impl Writeable<'tcx, CtfeProvenance>,
+        principal_ty: Option<Ty<'tcx>>,
+        auto_trait_def_ids: &[ty::Binder<'tcx, DefId>],
+        region: Region<'tcx>,
+    ) -> InterpResult<'tcx> {
+        let tcx = self.tcx.tcx;
+
+        // total entries in DynTrait predicates
+        let total_len = principal_ty.map(|_| 1).unwrap_or(0) + auto_trait_def_ids.len();
+
+        // element type = DynTraitPredicate
+        let slice_ty = slice_place.layout().ty.builtin_deref(false).unwrap(); // [DynTraitPredicate]
+        let elem_ty = slice_ty.sequence_element_type(tcx); // DynTraitPredicate
+
+        let arr_layout = self.layout_of(Ty::new_array(tcx, elem_ty, total_len as u64))?;
+        let arr_place = self.allocate(arr_layout, MemoryKind::Stack)?;
+        let mut elems = self.project_array_fields(&arr_place)?;
+
+        // principal entry (if any) - NOT an auto trait
+        if let Some(principal_ty) = principal_ty {
+            let Some((_i, elem_place)) = elems.next(self)? else {
+                span_bug!(self.tcx.span, "DynTrait.predicates length computed wrong (principal)");
+            };
+            self.write_dyn_trait_predicate(elem_place, principal_ty, false)?;
+        }
+
+        // auto trait entries - these ARE auto traits
+        for auto in auto_trait_def_ids {
+            let Some((_i, elem_place)) = elems.next(self)? else {
+                span_bug!(self.tcx.span, "DynTrait.predicates length computed wrong (auto)");
+            };
+            let auto_ty = self.mk_dyn_principal_auto_trait_ty(*auto, region);
+            self.write_dyn_trait_predicate(elem_place, auto_ty, true)?;
+        }
+
+        let arr_place = arr_place.map_provenance(CtfeProvenance::as_immutable);
+        let imm = Immediate::new_slice(arr_place.ptr(), total_len as u64, self);
+        self.write_immediate(imm, slice_place)
+    }
+
+    fn write_dyn_trait_predicate(
+        &mut self,
+        predicate_place: MPlaceTy<'tcx>,
+        trait_ty: Ty<'tcx>,
+        is_auto: bool,
+    ) -> InterpResult<'tcx> {
+        // DynTraitPredicate { trait_ty: Trait }
+        for (field_idx, field) in predicate_place
+            .layout
+            .ty
+            .ty_adt_def()
+            .unwrap()
+            .non_enum_variant()
+            .fields
+            .iter_enumerated()
+        {
+            let field_place = self.project_field(&predicate_place, field_idx)?;
+            match field.name {
+                sym::trait_ty => {
+                    // Now write the Trait struct
+                    self.write_trait(field_place, trait_ty, is_auto)?;
+                }
+                other => {
+                    span_bug!(
+                        self.tcx.def_span(field.did),
+                        "unimplemented DynTraitPredicate field {other}"
+                    )
+                }
+            }
+        }
+        interp_ok(())
+    }
+    fn write_trait(
+        &mut self,
+        trait_place: MPlaceTy<'tcx>,
+        trait_ty: Ty<'tcx>,
+        is_auto: bool,
+    ) -> InterpResult<'tcx> {
+        // Trait { ty: TypeId, is_auto: bool }
+        for (field_idx, field) in
+            trait_place.layout.ty.ty_adt_def().unwrap().non_enum_variant().fields.iter_enumerated()
+        {
+            let field_place = self.project_field(&trait_place, field_idx)?;
+            match field.name {
+                sym::ty => {
+                    self.write_type_id(trait_ty, &field_place)?;
+                }
+                sym::is_auto => {
+                    self.write_scalar(Scalar::from_bool(is_auto), &field_place)?;
+                }
+                other => {
+                    span_bug!(self.tcx.def_span(field.did), "unimplemented Trait field {other}")
+                }
+            }
+        }
+        interp_ok(())
+    }
+}
diff --git a/compiler/rustc_const_eval/src/const_eval/mod.rs b/compiler/rustc_const_eval/src/const_eval/mod.rs
index e70488b81c4c..c17ff8621a50 100644
--- a/compiler/rustc_const_eval/src/const_eval/mod.rs
+++ b/compiler/rustc_const_eval/src/const_eval/mod.rs
@@ -9,6 +9,7 @@ use tracing::instrument;
 use crate::interpret::InterpCx;
 
 mod dummy_machine;
+mod dyn_trait;
 mod error;
 mod eval_queries;
 mod fn_queries;
diff --git a/compiler/rustc_const_eval/src/const_eval/type_info.rs b/compiler/rustc_const_eval/src/const_eval/type_info.rs
index 3fcf6f94b5bf..f8881f0968bb 100644
--- a/compiler/rustc_const_eval/src/const_eval/type_info.rs
+++ b/compiler/rustc_const_eval/src/const_eval/type_info.rs
@@ -129,13 +129,18 @@ impl<'tcx> InterpCx<'tcx, CompileTimeMachine<'tcx>> {
 
                             variant
                         }
+                        ty::Dynamic(predicates, region) => {
+                            let (variant, variant_place) = downcast(sym::DynTrait)?;
+                            let dyn_place = self.project_field(&variant_place, FieldIdx::ZERO)?;
+                            self.write_dyn_trait_type_info(dyn_place, *predicates, *region)?;
+                            variant
+                        }
                         ty::Adt(_, _)
                         | ty::Foreign(_)
                         | ty::Pat(_, _)
                         | ty::FnDef(..)
                         | ty::FnPtr(..)
                         | ty::UnsafeBinder(..)
-                        | ty::Dynamic(..)
                         | ty::Closure(..)
                         | ty::CoroutineClosure(..)
                         | ty::Coroutine(..)
diff --git a/compiler/rustc_span/src/symbol.rs b/compiler/rustc_span/src/symbol.rs
index c4391c3ec4fc..1ebada3c285e 100644
--- a/compiler/rustc_span/src/symbol.rs
+++ b/compiler/rustc_span/src/symbol.rs
@@ -186,6 +186,7 @@ symbols! {
         AtomicU64,
         AtomicU128,
         AtomicUsize,
+        AutoTrait,
         BTreeEntry,
         BTreeMap,
         BTreeSet,
@@ -231,6 +232,7 @@ symbols! {
         Display,
         DoubleEndedIterator,
         Duration,
+        DynTrait,
         Encodable,
         Encoder,
         Enumerate,
@@ -1297,6 +1299,7 @@ symbols! {
         io_stdout,
         irrefutable_let_patterns,
         is,
+        is_auto,
         is_val_statically_known,
         isa_attribute,
         isize,
@@ -1750,6 +1753,7 @@ symbols! {
         precise_capturing_in_traits,
         precise_pointer_size_matching,
         precision,
+        predicates,
         pref_align_of,
         prefetch_read_data,
         prefetch_read_instruction,
@@ -2297,6 +2301,7 @@ symbols! {
         trace_macros,
         track_caller,
         trait_alias,
+        trait_ty,
         trait_upcasting,
         transmute,
         transmute_generic_consts,
diff --git a/library/core/src/mem/type_info.rs b/library/core/src/mem/type_info.rs
index 30a70165b095..8b30803c97c9 100644
--- a/library/core/src/mem/type_info.rs
+++ b/library/core/src/mem/type_info.rs
@@ -47,6 +47,8 @@ pub enum TypeKind {
     Array(Array),
     /// Slices.
     Slice(Slice),
+    /// Dynamic Traits.
+    DynTrait(DynTrait),
     /// Primitive boolean type.
     Bool(Bool),
     /// Primitive character type.
@@ -105,6 +107,36 @@ pub struct Slice {
     pub element_ty: TypeId,
 }
 
+/// Compile-time type information about dynamic traits.
+/// FIXME(#146922): Add super traits and generics
+#[derive(Debug)]
+#[non_exhaustive]
+#[unstable(feature = "type_info", issue = "146922")]
+pub struct DynTrait {
+    /// The predicates of  a dynamic trait.
+    pub predicates: &'static [DynTraitPredicate],
+}
+
+/// Compile-time type information about a dynamic trait predicate.
+#[derive(Debug)]
+#[non_exhaustive]
+#[unstable(feature = "type_info", issue = "146922")]
+pub struct DynTraitPredicate {
+    /// The type of the trait as a dynamic trait type.
+    pub trait_ty: Trait,
+}
+
+/// Compile-time type information about a trait.
+#[derive(Debug)]
+#[non_exhaustive]
+#[unstable(feature = "type_info", issue = "146922")]
+pub struct Trait {
+    /// The TypeId of the trait as a dynamic type
+    pub ty: TypeId,
+    /// Whether the trait is an auto trait
+    pub is_auto: bool,
+}
+
 /// Compile-time type information about `bool`.
 #[derive(Debug)]
 #[non_exhaustive]
diff --git a/library/coretests/tests/mem/type_info.rs b/library/coretests/tests/mem/type_info.rs
index 0820e4f83993..87f2d5dd8289 100644
--- a/library/coretests/tests/mem/type_info.rs
+++ b/library/coretests/tests/mem/type_info.rs
@@ -163,3 +163,132 @@ fn test_pointers() {
         _ => unreachable!(),
     }
 }
+
+#[test]
+fn test_dynamic_traits() {
+    use std::collections::HashSet;
+    use std::mem::type_info::DynTraitPredicate;
+    trait A<T> {}
+
+    trait B<const CONST_NUM: i32> {
+        type Foo;
+    }
+
+    trait FooTrait<'a, 'b, const CONST_NUM: i32> {}
+
+    trait ProjectorTrait<'a, 'b> {}
+
+    fn preds_of<T: ?Sized + 'static>() -> &'static [DynTraitPredicate] {
+        match const { Type::of::<T>() }.kind {
+            TypeKind::DynTrait(d) => d.predicates,
+            _ => unreachable!(),
+        }
+    }
+
+    fn pred<'a>(preds: &'a [DynTraitPredicate], want: TypeId) -> &'a DynTraitPredicate {
+        preds
+            .iter()
+            .find(|p| p.trait_ty.ty == want)
+            .unwrap_or_else(|| panic!("missing predicate for {want:?}"))
+    }
+
+    fn assert_typeid_set_eq(actual: &[TypeId], expected: &[TypeId]) {
+        let actual_set: HashSet<TypeId> = actual.iter().copied().collect();
+        let expected_set: HashSet<TypeId> = expected.iter().copied().collect();
+        assert_eq!(actual.len(), actual_set.len(), "duplicates present: {actual:?}");
+        assert_eq!(
+            actual_set, expected_set,
+            "unexpected ids.\nactual: {actual:?}\nexpected: {expected:?}"
+        );
+    }
+
+    fn assert_predicates_exact(preds: &[DynTraitPredicate], expected_pred_ids: &[TypeId]) {
+        let actual_pred_ids: Vec<TypeId> = preds.iter().map(|p| p.trait_ty.ty).collect();
+        assert_typeid_set_eq(&actual_pred_ids, expected_pred_ids);
+    }
+
+    // dyn Send
+    {
+        let preds = preds_of::<dyn Send>();
+        assert_predicates_exact(preds, &[TypeId::of::<dyn Send>()]);
+
+        let p = pred(preds, TypeId::of::<dyn Send>());
+        assert!(p.trait_ty.is_auto);
+    }
+
+    // dyn A<i32>
+    {
+        let preds = preds_of::<dyn A<i32>>();
+        assert_predicates_exact(preds, &[TypeId::of::<dyn A<i32>>()]);
+
+        let p = pred(preds, TypeId::of::<dyn A<i32>>());
+        assert!(!p.trait_ty.is_auto);
+    }
+
+    // dyn B<5, Foo = i32>
+    {
+        let preds = preds_of::<dyn B<5, Foo = i32>>();
+        assert_predicates_exact(preds, &[TypeId::of::<dyn B<5, Foo = i32>>()]);
+
+        let e = pred(preds, TypeId::of::<dyn B<5, Foo = i32>>());
+        assert!(!e.trait_ty.is_auto);
+    }
+
+    // dyn for<'a> FooTrait<'a, 'a, 7>
+    {
+        let preds = preds_of::<dyn for<'a> FooTrait<'a, 'a, 7>>();
+        assert_predicates_exact(preds, &[TypeId::of::<dyn for<'a> FooTrait<'a, 'a, 7>>()]);
+
+        let foo = pred(preds, TypeId::of::<dyn for<'a> FooTrait<'a, 'a, 7>>());
+        assert!(!foo.trait_ty.is_auto);
+    }
+
+    // dyn FooTrait<'static, 'static, 7>
+    {
+        let preds = preds_of::<dyn FooTrait<'static, 'static, 7>>();
+        assert_predicates_exact(preds, &[TypeId::of::<dyn FooTrait<'static, 'static, 7>>()]);
+
+        let foo = pred(preds, TypeId::of::<dyn FooTrait<'static, 'static, 7>>());
+        assert!(!foo.trait_ty.is_auto);
+    }
+
+    // dyn for<'a, 'b> FooTrait<'a, 'b, 7>
+    {
+        let preds = preds_of::<dyn for<'a, 'b> FooTrait<'a, 'b, 7>>();
+        assert_predicates_exact(preds, &[TypeId::of::<dyn for<'a, 'b> FooTrait<'a, 'b, 7>>()]);
+
+        let foo = pred(preds, TypeId::of::<dyn for<'a, 'b> FooTrait<'a, 'b, 7>>());
+        assert!(!foo.trait_ty.is_auto);
+    }
+
+    // dyn for<'a, 'b> ProjectorTrait<'a, 'b>
+    {
+        let preds = preds_of::<dyn for<'a, 'b> ProjectorTrait<'a, 'b>>();
+        assert_predicates_exact(preds, &[TypeId::of::<dyn for<'a, 'b> ProjectorTrait<'a, 'b>>()]);
+
+        let proj = pred(preds, TypeId::of::<dyn for<'a, 'b> ProjectorTrait<'a, 'b>>());
+        assert!(!proj.trait_ty.is_auto);
+    }
+
+    // dyn for<'a> FooTrait<'a, 'a, 7> + Send + Sync
+    {
+        let preds = preds_of::<dyn for<'a> FooTrait<'a, 'a, 7> + Send + Sync>();
+        assert_predicates_exact(
+            preds,
+            &[
+                TypeId::of::<dyn for<'a> FooTrait<'a, 'a, 7>>(),
+                TypeId::of::<dyn Send>(),
+                TypeId::of::<dyn Sync>(),
+            ],
+        );
+
+        let foo = pred(preds, TypeId::of::<dyn for<'a> FooTrait<'a, 'a, 7>>());
+        assert!(!foo.trait_ty.is_auto);
+
+        let send = pred(preds, TypeId::of::<dyn Send>());
+        assert!(send.trait_ty.is_auto);
+
+        let sync = pred(preds, TypeId::of::<dyn Sync>());
+        assert!(sync.trait_ty.is_auto);
+    }
+}
diff --git a/tests/run-make/crate-loading/multiple-dep-versions.stderr b/tests/run-make/crate-loading/multiple-dep-versions.stderr
index f8f8bfaaff6f..ef7fb7082266 100644
--- a/tests/run-make/crate-loading/multiple-dep-versions.stderr
+++ b/tests/run-make/crate-loading/multiple-dep-versions.stderr
@@ -1,8 +1,8 @@
-error[E0277]: the trait bound `dep_2_reexport::Type: Trait` is not satisfied
+error[E0277]: the trait bound `dep_2_reexport::Type: dependency::Trait` is not satisfied
   --> replaced
    |
 LL |     do_something(Type);
-   |     ------------ ^^^^ the trait `Trait` is not implemented for `dep_2_reexport::Type`
+   |     ------------ ^^^^ the trait `dependency::Trait` is not implemented for `dep_2_reexport::Type`
    |     |
    |     required by a bound introduced by this call
    |
@@ -17,7 +17,7 @@ LL | pub trait Trait {
 LL | pub trait Trait {
    | --------------- this is the found trait
    = help: you can use `cargo tree` to explore your dependency tree
-help: the trait `Trait` is implemented for `dependency::Type`
+help: the trait `dependency::Trait` is implemented for `dependency::Type`
   --> replaced
    |
 LL | impl Trait for Type {
@@ -64,11 +64,11 @@ LL | pub trait Trait {
    | --------------- this is the trait that was imported
    = help: you can use `cargo tree` to explore your dependency tree
 
-error[E0277]: the trait bound `OtherType: Trait` is not satisfied
+error[E0277]: the trait bound `OtherType: dependency::Trait` is not satisfied
   --> replaced
    |
 LL |     do_something(OtherType);
-   |     ------------ ^^^^^^^^^ the trait `Trait` is not implemented for `OtherType`
+   |     ------------ ^^^^^^^^^ the trait `dependency::Trait` is not implemented for `OtherType`
    |     |
    |     required by a bound introduced by this call
    |
@@ -83,7 +83,7 @@ LL | pub trait Trait {
 LL | pub trait Trait {
    | --------------- this is the found trait
    = help: you can use `cargo tree` to explore your dependency tree
-help: the trait `Trait` is implemented for `dependency::Type`
+help: the trait `dependency::Trait` is implemented for `dependency::Type`
   --> replaced
    |
 LL | impl Trait for Type {
diff --git a/tests/ui/errors/remap-path-prefix-diagnostics.not-diag-in-deps.stderr b/tests/ui/errors/remap-path-prefix-diagnostics.not-diag-in-deps.stderr
index 234e251b2ad8..08c850cd8e24 100644
--- a/tests/ui/errors/remap-path-prefix-diagnostics.not-diag-in-deps.stderr
+++ b/tests/ui/errors/remap-path-prefix-diagnostics.not-diag-in-deps.stderr
@@ -9,7 +9,7 @@ help: the trait `std::fmt::Display` is not implemented for `A`
    |
 LL | struct A;
    | ^^^^^^^^
-note: required by a bound in `Trait`
+note: required by a bound in `r#trait::Trait`
   --> $DIR/auxiliary/trait.rs:LL:COL
    |
 LL | pub trait Trait: std::fmt::Display {}
diff --git a/tests/ui/errors/remap-path-prefix-diagnostics.only-debuginfo-in-deps.stderr b/tests/ui/errors/remap-path-prefix-diagnostics.only-debuginfo-in-deps.stderr
index 3b0d66e75e86..ebd7606815d0 100644
--- a/tests/ui/errors/remap-path-prefix-diagnostics.only-debuginfo-in-deps.stderr
+++ b/tests/ui/errors/remap-path-prefix-diagnostics.only-debuginfo-in-deps.stderr
@@ -9,7 +9,7 @@ help: the trait `std::fmt::Display` is not implemented for `A`
    |
 LL | struct A;
    | ^^^^^^^^
-note: required by a bound in `Trait`
+note: required by a bound in `r#trait::Trait`
   --> $DIR/auxiliary/trait-debuginfo.rs:LL:COL
    |
 LL | pub trait Trait: std::fmt::Display {}
diff --git a/tests/ui/errors/remap-path-prefix-diagnostics.only-diag-in-deps.stderr b/tests/ui/errors/remap-path-prefix-diagnostics.only-diag-in-deps.stderr
index 86c1140573e3..c21d49e325e2 100644
--- a/tests/ui/errors/remap-path-prefix-diagnostics.only-diag-in-deps.stderr
+++ b/tests/ui/errors/remap-path-prefix-diagnostics.only-diag-in-deps.stderr
@@ -9,7 +9,7 @@ help: the trait `std::fmt::Display` is not implemented for `A`
    |
 LL | struct A;
    | ^^^^^^^^
-note: required by a bound in `Trait`
+note: required by a bound in `r#trait::Trait`
   --> remapped/errors/auxiliary/trait-diag.rs:LL:COL
    |
 LL | pub trait Trait: std::fmt::Display {}
diff --git a/tests/ui/errors/remap-path-prefix-diagnostics.only-doc-in-deps.stderr b/tests/ui/errors/remap-path-prefix-diagnostics.only-doc-in-deps.stderr
index e1b93a1042f5..6ea6c16c5149 100644
--- a/tests/ui/errors/remap-path-prefix-diagnostics.only-doc-in-deps.stderr
+++ b/tests/ui/errors/remap-path-prefix-diagnostics.only-doc-in-deps.stderr
@@ -9,7 +9,7 @@ help: the trait `std::fmt::Display` is not implemented for `A`
    |
 LL | struct A;
    | ^^^^^^^^
-note: required by a bound in `Trait`
+note: required by a bound in `r#trait::Trait`
   --> $DIR/auxiliary/trait-doc.rs:LL:COL
    |
 LL | pub trait Trait: std::fmt::Display {}
diff --git a/tests/ui/errors/remap-path-prefix-diagnostics.only-macro-in-deps.stderr b/tests/ui/errors/remap-path-prefix-diagnostics.only-macro-in-deps.stderr
index 91c9cd90152b..9a0676ca0ea9 100644
--- a/tests/ui/errors/remap-path-prefix-diagnostics.only-macro-in-deps.stderr
+++ b/tests/ui/errors/remap-path-prefix-diagnostics.only-macro-in-deps.stderr
@@ -9,7 +9,7 @@ help: the trait `std::fmt::Display` is not implemented for `A`
    |
 LL | struct A;
    | ^^^^^^^^
-note: required by a bound in `Trait`
+note: required by a bound in `r#trait::Trait`
   --> $DIR/auxiliary/trait-macro.rs:LL:COL
    |
 LL | pub trait Trait: std::fmt::Display {}
diff --git a/tests/ui/errors/remap-path-prefix-diagnostics.with-debuginfo-in-deps.stderr b/tests/ui/errors/remap-path-prefix-diagnostics.with-debuginfo-in-deps.stderr
index 3b0d66e75e86..ebd7606815d0 100644
--- a/tests/ui/errors/remap-path-prefix-diagnostics.with-debuginfo-in-deps.stderr
+++ b/tests/ui/errors/remap-path-prefix-diagnostics.with-debuginfo-in-deps.stderr
@@ -9,7 +9,7 @@ help: the trait `std::fmt::Display` is not implemented for `A`
    |
 LL | struct A;
    | ^^^^^^^^
-note: required by a bound in `Trait`
+note: required by a bound in `r#trait::Trait`
   --> $DIR/auxiliary/trait-debuginfo.rs:LL:COL
    |
 LL | pub trait Trait: std::fmt::Display {}
diff --git a/tests/ui/errors/remap-path-prefix-diagnostics.with-diag-in-deps.stderr b/tests/ui/errors/remap-path-prefix-diagnostics.with-diag-in-deps.stderr
index 00a647df61f9..688db94a9753 100644
--- a/tests/ui/errors/remap-path-prefix-diagnostics.with-diag-in-deps.stderr
+++ b/tests/ui/errors/remap-path-prefix-diagnostics.with-diag-in-deps.stderr
@@ -9,7 +9,7 @@ help: the trait `std::fmt::Display` is not implemented for `A`
    |
 LL | struct A;
    | ^^^^^^^^
-note: required by a bound in `Trait`
+note: required by a bound in `r#trait::Trait`
   --> remapped/errors/auxiliary/trait-diag.rs:LL:COL
    |
 LL | pub trait Trait: std::fmt::Display {}
diff --git a/tests/ui/errors/remap-path-prefix-diagnostics.with-doc-in-deps.stderr b/tests/ui/errors/remap-path-prefix-diagnostics.with-doc-in-deps.stderr
index e1b93a1042f5..6ea6c16c5149 100644
--- a/tests/ui/errors/remap-path-prefix-diagnostics.with-doc-in-deps.stderr
+++ b/tests/ui/errors/remap-path-prefix-diagnostics.with-doc-in-deps.stderr
@@ -9,7 +9,7 @@ help: the trait `std::fmt::Display` is not implemented for `A`
    |
 LL | struct A;
    | ^^^^^^^^
-note: required by a bound in `Trait`
+note: required by a bound in `r#trait::Trait`
   --> $DIR/auxiliary/trait-doc.rs:LL:COL
    |
 LL | pub trait Trait: std::fmt::Display {}
diff --git a/tests/ui/errors/remap-path-prefix-diagnostics.with-macro-in-deps.stderr b/tests/ui/errors/remap-path-prefix-diagnostics.with-macro-in-deps.stderr
index 91c9cd90152b..9a0676ca0ea9 100644
--- a/tests/ui/errors/remap-path-prefix-diagnostics.with-macro-in-deps.stderr
+++ b/tests/ui/errors/remap-path-prefix-diagnostics.with-macro-in-deps.stderr
@@ -9,7 +9,7 @@ help: the trait `std::fmt::Display` is not implemented for `A`
    |
 LL | struct A;
    | ^^^^^^^^
-note: required by a bound in `Trait`
+note: required by a bound in `r#trait::Trait`
   --> $DIR/auxiliary/trait-macro.rs:LL:COL
    |
 LL | pub trait Trait: std::fmt::Display {}
diff --git a/tests/ui/privacy/private-inferred-type.rs b/tests/ui/privacy/private-inferred-type.rs
index 8c07226fe0e4..ed22ad44c449 100644
--- a/tests/ui/privacy/private-inferred-type.rs
+++ b/tests/ui/privacy/private-inferred-type.rs
@@ -115,11 +115,11 @@ fn main() {
 
     m::m!();
 
-    m::leak_anon1(); //~ ERROR trait `Trait` is private
+    m::leak_anon1(); //~ ERROR trait `m::Trait` is private
     m::leak_anon2(); //~ ERROR type `Priv` is private
     m::leak_anon3(); //~ ERROR type `Priv` is private
 
-    m::leak_dyn1(); //~ ERROR trait `Trait` is private
+    m::leak_dyn1(); //~ ERROR trait `m::Trait` is private
     m::leak_dyn2(); //~ ERROR type `Priv` is private
     m::leak_dyn3(); //~ ERROR type `Priv` is private
 
diff --git a/tests/ui/privacy/private-inferred-type.stderr b/tests/ui/privacy/private-inferred-type.stderr
index fc3f9ab62bfa..0dfa799a4d95 100644
--- a/tests/ui/privacy/private-inferred-type.stderr
+++ b/tests/ui/privacy/private-inferred-type.stderr
@@ -172,7 +172,7 @@ LL |     m::m!();
    |
    = note: this error originates in the macro `m::m` (in Nightly builds, run with -Z macro-backtrace for more info)
 
-error: trait `Trait` is private
+error: trait `m::Trait` is private
   --> $DIR/private-inferred-type.rs:118:5
    |
 LL |     m::leak_anon1();
@@ -190,7 +190,7 @@ error: type `Priv` is private
 LL |     m::leak_anon3();
    |     ^^^^^^^^^^^^^^^ private type
 
-error: trait `Trait` is private
+error: trait `m::Trait` is private
   --> $DIR/private-inferred-type.rs:122:5
    |
 LL |     m::leak_dyn1();
diff --git a/tests/ui/trait-bounds/suggest-maybe-sized-bound.stderr b/tests/ui/trait-bounds/suggest-maybe-sized-bound.stderr
index 4ce936582f43..b459ad47e067 100644
--- a/tests/ui/trait-bounds/suggest-maybe-sized-bound.stderr
+++ b/tests/ui/trait-bounds/suggest-maybe-sized-bound.stderr
@@ -22,7 +22,7 @@ LL |         type P<X> = [u8];
    |                     ^^^^ doesn't have a size known at compile-time
    |
    = help: the trait `Sized` is not implemented for `[u8]`
-note: required by a bound in `Trait::P`
+note: required by a bound in `main::Trait::P`
   --> $DIR/suggest-maybe-sized-bound.rs:13:9
    |
 LL |         type P<X>;
diff --git a/tests/ui/traits/bound/on-structs-and-enums-xc.stderr b/tests/ui/traits/bound/on-structs-and-enums-xc.stderr
index 5064b60bfd57..472ac187a966 100644
--- a/tests/ui/traits/bound/on-structs-and-enums-xc.stderr
+++ b/tests/ui/traits/bound/on-structs-and-enums-xc.stderr
@@ -1,8 +1,8 @@
-error[E0277]: the trait bound `usize: Trait` is not satisfied
+error[E0277]: the trait bound `usize: on_structs_and_enums_xc::Trait` is not satisfied
   --> $DIR/on-structs-and-enums-xc.rs:7:15
    |
 LL | fn explode(x: Foo<usize>) {}
-   |               ^^^^^^^^^^ the trait `Trait` is not implemented for `usize`
+   |               ^^^^^^^^^^ the trait `on_structs_and_enums_xc::Trait` is not implemented for `usize`
    |
 note: required by a bound in `Foo`
   --> $DIR/auxiliary/on_structs_and_enums_xc.rs:5:18
@@ -10,11 +10,11 @@ note: required by a bound in `Foo`
 LL | pub struct Foo<T:Trait> {
    |                  ^^^^^ required by this bound in `Foo`
 
-error[E0277]: the trait bound `f32: Trait` is not satisfied
+error[E0277]: the trait bound `f32: on_structs_and_enums_xc::Trait` is not satisfied
   --> $DIR/on-structs-and-enums-xc.rs:10:14
    |
 LL | fn kaboom(y: Bar<f32>) {}
-   |              ^^^^^^^^ the trait `Trait` is not implemented for `f32`
+   |              ^^^^^^^^ the trait `on_structs_and_enums_xc::Trait` is not implemented for `f32`
    |
 note: required by a bound in `Bar`
   --> $DIR/auxiliary/on_structs_and_enums_xc.rs:9:16
diff --git a/tests/ui/traits/bound/on-structs-and-enums-xc1.stderr b/tests/ui/traits/bound/on-structs-and-enums-xc1.stderr
index 1f46415e2436..5cf682a5045e 100644
--- a/tests/ui/traits/bound/on-structs-and-enums-xc1.stderr
+++ b/tests/ui/traits/bound/on-structs-and-enums-xc1.stderr
@@ -1,8 +1,8 @@
-error[E0277]: the trait bound `{integer}: Trait` is not satisfied
+error[E0277]: the trait bound `{integer}: on_structs_and_enums_xc::Trait` is not satisfied
   --> $DIR/on-structs-and-enums-xc1.rs:9:12
    |
 LL |         x: 3
-   |            ^ the trait `Trait` is not implemented for `{integer}`
+   |            ^ the trait `on_structs_and_enums_xc::Trait` is not implemented for `{integer}`
    |
 note: required by a bound in `Foo`
   --> $DIR/auxiliary/on_structs_and_enums_xc.rs:5:18
@@ -10,11 +10,11 @@ note: required by a bound in `Foo`
 LL | pub struct Foo<T:Trait> {
    |                  ^^^^^ required by this bound in `Foo`
 
-error[E0277]: the trait bound `f64: Trait` is not satisfied
+error[E0277]: the trait bound `f64: on_structs_and_enums_xc::Trait` is not satisfied
   --> $DIR/on-structs-and-enums-xc1.rs:12:14
    |
 LL |     let bar: Bar<f64> = return;
-   |              ^^^^^^^^ the trait `Trait` is not implemented for `f64`
+   |              ^^^^^^^^ the trait `on_structs_and_enums_xc::Trait` is not implemented for `f64`
    |
 note: required by a bound in `Bar`
   --> $DIR/auxiliary/on_structs_and_enums_xc.rs:9:16
diff --git a/tests/ui/traits/wrong-multiple-different-versions-of-a-crate.rs b/tests/ui/traits/wrong-multiple-different-versions-of-a-crate.rs
index ec6bb7bbcc59..35465183001a 100644
--- a/tests/ui/traits/wrong-multiple-different-versions-of-a-crate.rs
+++ b/tests/ui/traits/wrong-multiple-different-versions-of-a-crate.rs
@@ -5,8 +5,8 @@
 // Issue #148892.
 //@ aux-crate:crate1=crate1.rs
 
-struct MyStruct; //~ HELP  the trait `Trait` is not implemented for `MyStruct`
+struct MyStruct; //~ HELP the trait `crate1::Trait` is not implemented for `MyStruct`
 
 fn main() {
-    crate1::foo(MyStruct); //~ ERROR the trait bound `MyStruct: Trait` is not satisfied
+    crate1::foo(MyStruct); //~ ERROR the trait bound `MyStruct: crate1::Trait` is not satisfied
 }
diff --git a/tests/ui/traits/wrong-multiple-different-versions-of-a-crate.stderr b/tests/ui/traits/wrong-multiple-different-versions-of-a-crate.stderr
index 7fec237f54d4..5bcda9f2a95b 100644
--- a/tests/ui/traits/wrong-multiple-different-versions-of-a-crate.stderr
+++ b/tests/ui/traits/wrong-multiple-different-versions-of-a-crate.stderr
@@ -1,4 +1,4 @@
-error[E0277]: the trait bound `MyStruct: Trait` is not satisfied
+error[E0277]: the trait bound `MyStruct: crate1::Trait` is not satisfied
   --> $DIR/wrong-multiple-different-versions-of-a-crate.rs:11:17
    |
 LL |     crate1::foo(MyStruct);
@@ -6,7 +6,7 @@ LL |     crate1::foo(MyStruct);
    |     |
    |     required by a bound introduced by this call
    |
-help: the trait `Trait` is not implemented for `MyStruct`
+help: the trait `crate1::Trait` is not implemented for `MyStruct`
   --> $DIR/wrong-multiple-different-versions-of-a-crate.rs:8:1
    |
 LL | struct MyStruct;
diff --git a/tests/ui/unresolved/unresolved-candidates.stderr b/tests/ui/unresolved/unresolved-candidates.stderr
index 55b9d8ec6e8f..7d8e894a5582 100644
--- a/tests/ui/unresolved/unresolved-candidates.stderr
+++ b/tests/ui/unresolved/unresolved-candidates.stderr
@@ -4,8 +4,10 @@ error[E0432]: unresolved import `Trait`
 LL |     use Trait;
    |         ^^^^^ no `Trait` in the root
    |
-help: consider importing this trait instead
+help: consider importing one of these items instead
    |
+LL |     use std::mem::type_info::Trait;
+   |         +++++++++++++++++++++
 LL |     use a::Trait;
    |         +++
 
diff --git a/tests/ui/unstable-feature-bound/unstable_impl_coherence.disabled.stderr b/tests/ui/unstable-feature-bound/unstable_impl_coherence.disabled.stderr
index afef024e1b9c..60bb2117df24 100644
--- a/tests/ui/unstable-feature-bound/unstable_impl_coherence.disabled.stderr
+++ b/tests/ui/unstable-feature-bound/unstable_impl_coherence.disabled.stderr
@@ -1,11 +1,11 @@
-error[E0119]: conflicting implementations of trait `Trait` for type `LocalTy`
+error[E0119]: conflicting implementations of trait `aux::Trait` for type `LocalTy`
   --> $DIR/unstable_impl_coherence.rs:14:1
    |
 LL | impl aux::Trait for LocalTy {}
    | ^^^^^^^^^^^^^^^^^^^^^^^^^^^
    |
    = note: conflicting implementation in crate `unstable_impl_coherence_aux`:
-           - impl<T> Trait for T
+           - impl<T> aux::Trait for T
              where feature(foo) is enabled;
 
 error: aborting due to 1 previous error
diff --git a/tests/ui/unstable-feature-bound/unstable_impl_coherence.enabled.stderr b/tests/ui/unstable-feature-bound/unstable_impl_coherence.enabled.stderr
index afef024e1b9c..60bb2117df24 100644
--- a/tests/ui/unstable-feature-bound/unstable_impl_coherence.enabled.stderr
+++ b/tests/ui/unstable-feature-bound/unstable_impl_coherence.enabled.stderr
@@ -1,11 +1,11 @@
-error[E0119]: conflicting implementations of trait `Trait` for type `LocalTy`
+error[E0119]: conflicting implementations of trait `aux::Trait` for type `LocalTy`
   --> $DIR/unstable_impl_coherence.rs:14:1
    |
 LL | impl aux::Trait for LocalTy {}
    | ^^^^^^^^^^^^^^^^^^^^^^^^^^^
    |
    = note: conflicting implementation in crate `unstable_impl_coherence_aux`:
-           - impl<T> Trait for T
+           - impl<T> aux::Trait for T
              where feature(foo) is enabled;
 
 error: aborting due to 1 previous error
diff --git a/tests/ui/unstable-feature-bound/unstable_impl_coherence.rs b/tests/ui/unstable-feature-bound/unstable_impl_coherence.rs
index 22100f85f715..c36316dc5fa1 100644
--- a/tests/ui/unstable-feature-bound/unstable_impl_coherence.rs
+++ b/tests/ui/unstable-feature-bound/unstable_impl_coherence.rs
@@ -12,6 +12,6 @@ use aux::Trait;
 struct LocalTy;
 
 impl aux::Trait for LocalTy {}
-//~^ ERROR: conflicting implementations of trait `Trait` for type `LocalTy`
+//~^ ERROR: conflicting implementations of trait `aux::Trait` for type `LocalTy`
 
 fn main(){}
diff --git a/tests/ui/unstable-feature-bound/unstable_impl_method_selection.stderr b/tests/ui/unstable-feature-bound/unstable_impl_method_selection.stderr
index 840af730154d..b2e4eb730d84 100644
--- a/tests/ui/unstable-feature-bound/unstable_impl_method_selection.stderr
+++ b/tests/ui/unstable-feature-bound/unstable_impl_method_selection.stderr
@@ -4,9 +4,9 @@ error[E0283]: type annotations needed
 LL |     vec![].foo();
    |            ^^^ cannot infer type for struct `Vec<_>`
    |
-   = note: multiple `impl`s satisfying `Vec<_>: Trait` found in the `unstable_impl_method_selection_aux` crate:
-           - impl Trait for Vec<u32>;
-           - impl Trait for Vec<u64>
+   = note: multiple `impl`s satisfying `Vec<_>: aux::Trait` found in the `unstable_impl_method_selection_aux` crate:
+           - impl aux::Trait for Vec<u32>;
+           - impl aux::Trait for Vec<u64>
              where feature(bar) is enabled;
 
 error: aborting due to 1 previous error
diff --git a/tests/ui/use/issue-18986.stderr b/tests/ui/use/issue-18986.stderr
index 350cb18f9527..084fa80c3b6d 100644
--- a/tests/ui/use/issue-18986.stderr
+++ b/tests/ui/use/issue-18986.stderr
@@ -3,6 +3,11 @@ error[E0574]: expected struct, variant or union type, found trait `Trait`
    |
 LL |         Trait { x: 42 } => ()
    |         ^^^^^ not a struct, variant or union type
+   |
+help: consider importing this struct instead
+   |
+LL + use std::mem::type_info::Trait;
+   |
 
 error: aborting due to 1 previous error
 

From b0d96492d032f6107bbcad2a02895592034e5ab7 Mon Sep 17 00:00:00 2001
From: Jeremy Smart <jeremy3141592@gmail.com>
Date: Tue, 27 Jan 2026 19:30:37 -0500
Subject: [PATCH 91/97] fix undefined behavior in VecDeque::splice

---
 library/alloc/src/collections/vec_deque/splice.rs |  6 +++++-
 library/alloctests/tests/vec_deque.rs             | 11 +++++++++++
 2 files changed, 16 insertions(+), 1 deletion(-)

diff --git a/library/alloc/src/collections/vec_deque/splice.rs b/library/alloc/src/collections/vec_deque/splice.rs
index cd98af7341de..d7b9a96291c3 100644
--- a/library/alloc/src/collections/vec_deque/splice.rs
+++ b/library/alloc/src/collections/vec_deque/splice.rs
@@ -143,7 +143,11 @@ impl<T, A: Allocator> Drain<'_, T, A> {
 
         let new_tail_start = tail_start + additional;
         unsafe {
-            deque.wrap_copy(tail_start, new_tail_start, self.tail_len);
+            deque.wrap_copy(
+                deque.to_physical_idx(tail_start),
+                deque.to_physical_idx(new_tail_start),
+                self.tail_len,
+            );
         }
         self.drain_len += additional;
     }
diff --git a/library/alloctests/tests/vec_deque.rs b/library/alloctests/tests/vec_deque.rs
index e06d18250a51..92853fe00fd6 100644
--- a/library/alloctests/tests/vec_deque.rs
+++ b/library/alloctests/tests/vec_deque.rs
@@ -2336,3 +2336,14 @@ fn test_splice_forget() {
     std::mem::forget(v.splice(2..4, a));
     assert_eq!(v, &[1, 2]);
 }
+
+#[test]
+fn test_splice_wrapping() {
+    let mut vec = VecDeque::with_capacity(10);
+    vec.push_front(7u8);
+    vec.push_back(9);
+
+    vec.splice(1..1, [8]);
+
+    assert_eq!(Vec::from(vec), [7, 8, 9]);
+}

From 5ddb7f6dd2279d920b8277485afef4a1dee3270d Mon Sep 17 00:00:00 2001
From: dianne <diannes.gm@gmail.com>
Date: Tue, 27 Jan 2026 17:12:11 -0800
Subject: [PATCH 92/97] clean up checks for integer div/rem promotion

---
 .../rustc_mir_transform/src/promote_consts.rs | 62 +++++++------------
 1 file changed, 24 insertions(+), 38 deletions(-)

diff --git a/compiler/rustc_mir_transform/src/promote_consts.rs b/compiler/rustc_mir_transform/src/promote_consts.rs
index 6e7b93a5e719..3d1537b95efa 100644
--- a/compiler/rustc_mir_transform/src/promote_consts.rs
+++ b/compiler/rustc_mir_transform/src/promote_consts.rs
@@ -485,47 +485,33 @@ impl<'tcx> Validator<'_, 'tcx> {
                         if lhs_ty.is_integral() {
                             let sz = lhs_ty.primitive_size(self.tcx);
                             // Integer division: the RHS must be a non-zero const.
-                            let rhs_val = match rhs {
-                                Operand::Constant(c)
-                                    if self.should_evaluate_for_promotion_checks(c.const_) =>
-                                {
-                                    c.const_.try_eval_scalar_int(self.tcx, self.typing_env)
-                                }
-                                _ => None,
-                            };
-                            match rhs_val.map(|x| x.to_uint(sz)) {
+                            let rhs_val = if let Operand::Constant(rhs_c) = rhs
+                                && self.should_evaluate_for_promotion_checks(rhs_c.const_)
+                                && let Some(rhs_val) =
+                                    rhs_c.const_.try_eval_scalar_int(self.tcx, self.typing_env)
                                 // for the zero test, int vs uint does not matter
-                                Some(x) if x != 0 => {}        // okay
-                                _ => return Err(Unpromotable), // value not known or 0 -- not okay
-                            }
+                                && rhs_val.to_uint(sz) != 0
+                            {
+                                rhs_val
+                            } else {
+                                // value not known or 0 -- not okay
+                                return Err(Unpromotable);
+                            };
                             // Furthermore, for signed division, we also have to exclude `int::MIN /
                             // -1`.
-                            if lhs_ty.is_signed() {
-                                match rhs_val.map(|x| x.to_int(sz)) {
-                                    Some(-1) | None => {
-                                        // The RHS is -1 or unknown, so we have to be careful.
-                                        // But is the LHS int::MIN?
-                                        let lhs_val = match lhs {
-                                            Operand::Constant(c)
-                                                if self.should_evaluate_for_promotion_checks(
-                                                    c.const_,
-                                                ) =>
-                                            {
-                                                c.const_
-                                                    .try_eval_scalar_int(self.tcx, self.typing_env)
-                                            }
-                                            _ => None,
-                                        };
-                                        let lhs_min = sz.signed_int_min();
-                                        match lhs_val.map(|x| x.to_int(sz)) {
-                                            // okay
-                                            Some(x) if x != lhs_min => {}
-
-                                            // value not known or int::MIN -- not okay
-                                            _ => return Err(Unpromotable),
-                                        }
-                                    }
-                                    _ => {}
+                            if lhs_ty.is_signed() && rhs_val.to_int(sz) == -1 {
+                                // The RHS is -1, so we have to be careful. But is the LHS int::MIN?
+                                if let Operand::Constant(lhs_c) = lhs
+                                    && self.should_evaluate_for_promotion_checks(lhs_c.const_)
+                                    && let Some(lhs_val) =
+                                        lhs_c.const_.try_eval_scalar_int(self.tcx, self.typing_env)
+                                    && let lhs_min = sz.signed_int_min()
+                                    && lhs_val.to_int(sz) != lhs_min
+                                {
+                                    // okay
+                                } else {
+                                    // value not known or int::MIN -- not okay
+                                    return Err(Unpromotable);
                                 }
                             }
                         }

From 10e053dbb5c7ac3679044f222112682c9fc0758a Mon Sep 17 00:00:00 2001
From: Hood Chatham <roberthoodchatham@gmail.com>
Date: Mon, 26 Jan 2026 10:34:50 -0800
Subject: [PATCH 93/97] Implement `set_output_kind` for Emscripten linker

This makes cdylibs compile to working Emscripten dynamic libraries without passing extra
RUSTFLAGS. This was previously approved as PR 98358 but there were CI failures that I
never got around to fixing.
---
 compiler/rustc_codegen_ssa/src/back/linker.rs     | 15 ++++++++++++++-
 .../src/spec/targets/wasm32_unknown_emscripten.rs |  2 ++
 2 files changed, 16 insertions(+), 1 deletion(-)

diff --git a/compiler/rustc_codegen_ssa/src/back/linker.rs b/compiler/rustc_codegen_ssa/src/back/linker.rs
index 1b75db51140b..db49f92e39ac 100644
--- a/compiler/rustc_codegen_ssa/src/back/linker.rs
+++ b/compiler/rustc_codegen_ssa/src/back/linker.rs
@@ -1208,10 +1208,23 @@ impl<'a> Linker for EmLinker<'a> {
 
     fn set_output_kind(
         &mut self,
-        _output_kind: LinkOutputKind,
+        output_kind: LinkOutputKind,
         _crate_type: CrateType,
         _out_filename: &Path,
     ) {
+        match output_kind {
+            LinkOutputKind::DynamicNoPicExe | LinkOutputKind::DynamicPicExe => {
+                self.cmd.arg("-sMAIN_MODULE=2");
+            }
+            LinkOutputKind::DynamicDylib | LinkOutputKind::StaticDylib => {
+                self.cmd.arg("-sSIDE_MODULE=2");
+            }
+            // -fno-pie is the default on Emscripten.
+            LinkOutputKind::StaticNoPicExe | LinkOutputKind::StaticPicExe => {}
+            LinkOutputKind::WasiReactorExe => {
+                unreachable!();
+            }
+        }
     }
 
     fn link_dylib_by_name(&mut self, name: &str, _verbatim: bool, _as_needed: bool) {
diff --git a/compiler/rustc_target/src/spec/targets/wasm32_unknown_emscripten.rs b/compiler/rustc_target/src/spec/targets/wasm32_unknown_emscripten.rs
index 47623c34dce3..fb735b54dd82 100644
--- a/compiler/rustc_target/src/spec/targets/wasm32_unknown_emscripten.rs
+++ b/compiler/rustc_target/src/spec/targets/wasm32_unknown_emscripten.rs
@@ -19,6 +19,8 @@ pub(crate) fn target() -> Target {
         pre_link_args,
         post_link_args,
         relocation_model: RelocModel::Pic,
+        crt_static_respected: true,
+        crt_static_default: true,
         panic_strategy: PanicStrategy::Unwind,
         no_default_libraries: false,
         families: cvs!["unix", "wasm"],

From 11ae531ac82fd502a6de59e7508a4546960cbee4 Mon Sep 17 00:00:00 2001
From: Arseni Novikau <novikov.arsenij@gmail.com>
Date: Tue, 6 Jan 2026 01:22:43 +0300
Subject: [PATCH 94/97] diagnostics: don't suggest `#[derive]` if impl already
 exists

---
 .../rustc_hir_typeck/src/method/suggest.rs    | 88 +++++++++++++------
 ...rive-clone-already-present-issue-146515.rs | 20 +++++
 ...-clone-already-present-issue-146515.stderr | 23 +++++
 3 files changed, 102 insertions(+), 29 deletions(-)
 create mode 100644 tests/ui/suggestions/derive-clone-already-present-issue-146515.rs
 create mode 100644 tests/ui/suggestions/derive-clone-already-present-issue-146515.stderr

diff --git a/compiler/rustc_hir_typeck/src/method/suggest.rs b/compiler/rustc_hir_typeck/src/method/suggest.rs
index b2803f4347e3..5673d044ad2c 100644
--- a/compiler/rustc_hir_typeck/src/method/suggest.rs
+++ b/compiler/rustc_hir_typeck/src/method/suggest.rs
@@ -3281,6 +3281,63 @@ impl<'a, 'tcx> FnCtxt<'a, 'tcx> {
         }
     }
 
+    /// Checks if we can suggest a derive macro for the unmet trait bound.
+    /// Returns Some(list_of_derives) if possible, or None if not.
+    fn consider_suggesting_derives_for_ty(
+        &self,
+        trait_pred: ty::TraitPredicate<'tcx>,
+        adt: ty::AdtDef<'tcx>,
+    ) -> Option<Vec<(String, Span, Symbol)>> {
+        let diagnostic_name = self.tcx.get_diagnostic_name(trait_pred.def_id())?;
+
+        let can_derive = match diagnostic_name {
+            sym::Default
+            | sym::Eq
+            | sym::PartialEq
+            | sym::Ord
+            | sym::PartialOrd
+            | sym::Clone
+            | sym::Copy
+            | sym::Hash
+            | sym::Debug => true,
+            _ => false,
+        };
+
+        if !can_derive {
+            return None;
+        }
+
+        let trait_def_id = trait_pred.def_id();
+        let self_ty = trait_pred.self_ty();
+
+        // We need to check if there is already a manual implementation of the trait
+        // for this specific ADT to avoid suggesting `#[derive(..)]` that would conflict.
+        if self.tcx.non_blanket_impls_for_ty(trait_def_id, self_ty).any(|impl_def_id| {
+            self.tcx
+                .type_of(impl_def_id)
+                .instantiate_identity()
+                .ty_adt_def()
+                .is_some_and(|def| def.did() == adt.did())
+        }) {
+            return None;
+        }
+
+        let mut derives = Vec::new();
+        let self_name = self_ty.to_string();
+        let self_span = self.tcx.def_span(adt.did());
+
+        for super_trait in supertraits(self.tcx, ty::Binder::dummy(trait_pred.trait_ref)) {
+            if let Some(parent_diagnostic_name) = self.tcx.get_diagnostic_name(super_trait.def_id())
+            {
+                derives.push((self_name.clone(), self_span, parent_diagnostic_name));
+            }
+        }
+
+        derives.push((self_name, self_span, diagnostic_name));
+
+        Some(derives)
+    }
+
     fn note_predicate_source_and_get_derives(
         &self,
         err: &mut Diag<'_>,
@@ -3298,35 +3355,8 @@ impl<'a, 'tcx> FnCtxt<'a, 'tcx> {
                 Some(adt) if adt.did().is_local() => adt,
                 _ => continue,
             };
-            if let Some(diagnostic_name) = self.tcx.get_diagnostic_name(trait_pred.def_id()) {
-                let can_derive = match diagnostic_name {
-                    sym::Default
-                    | sym::Eq
-                    | sym::PartialEq
-                    | sym::Ord
-                    | sym::PartialOrd
-                    | sym::Clone
-                    | sym::Copy
-                    | sym::Hash
-                    | sym::Debug => true,
-                    _ => false,
-                };
-                if can_derive {
-                    let self_name = trait_pred.self_ty().to_string();
-                    let self_span = self.tcx.def_span(adt.did());
-                    for super_trait in
-                        supertraits(self.tcx, ty::Binder::dummy(trait_pred.trait_ref))
-                    {
-                        if let Some(parent_diagnostic_name) =
-                            self.tcx.get_diagnostic_name(super_trait.def_id())
-                        {
-                            derives.push((self_name.clone(), self_span, parent_diagnostic_name));
-                        }
-                    }
-                    derives.push((self_name, self_span, diagnostic_name));
-                } else {
-                    traits.push(trait_pred.def_id());
-                }
+            if let Some(new_derives) = self.consider_suggesting_derives_for_ty(trait_pred, adt) {
+                derives.extend(new_derives);
             } else {
                 traits.push(trait_pred.def_id());
             }
diff --git a/tests/ui/suggestions/derive-clone-already-present-issue-146515.rs b/tests/ui/suggestions/derive-clone-already-present-issue-146515.rs
new file mode 100644
index 000000000000..083d73711a51
--- /dev/null
+++ b/tests/ui/suggestions/derive-clone-already-present-issue-146515.rs
@@ -0,0 +1,20 @@
+// issue: https://github.com/rust-lang/rust/issues/146515
+
+use std::rc::Rc;
+
+#[derive(Clone)]
+struct ContainsRc<T> {
+    value: Rc<T>,
+}
+
+fn clone_me<T>(x: &ContainsRc<T>) -> ContainsRc<T> {
+    //~^ NOTE expected `ContainsRc<T>` because of return type
+    x.clone()
+    //~^ ERROR mismatched types
+    //~| NOTE expected `ContainsRc<T>`, found `&ContainsRc<T>`
+    //~| NOTE expected struct `ContainsRc<_>`
+    //~| NOTE `ContainsRc<T>` does not implement `Clone`, so `&ContainsRc<T>` was cloned instead
+    //~| NOTE the trait `Clone` must be implemented
+}
+
+fn main() {}
diff --git a/tests/ui/suggestions/derive-clone-already-present-issue-146515.stderr b/tests/ui/suggestions/derive-clone-already-present-issue-146515.stderr
new file mode 100644
index 000000000000..516ef38f668d
--- /dev/null
+++ b/tests/ui/suggestions/derive-clone-already-present-issue-146515.stderr
@@ -0,0 +1,23 @@
+error[E0308]: mismatched types
+  --> $DIR/derive-clone-already-present-issue-146515.rs:12:5
+   |
+LL | fn clone_me<T>(x: &ContainsRc<T>) -> ContainsRc<T> {
+   |                                      ------------- expected `ContainsRc<T>` because of return type
+LL |
+LL |     x.clone()
+   |     ^^^^^^^^^ expected `ContainsRc<T>`, found `&ContainsRc<T>`
+   |
+   = note: expected struct `ContainsRc<_>`
+           found reference `&ContainsRc<_>`
+note: `ContainsRc<T>` does not implement `Clone`, so `&ContainsRc<T>` was cloned instead
+  --> $DIR/derive-clone-already-present-issue-146515.rs:12:5
+   |
+LL |     x.clone()
+   |     ^
+   = help: `Clone` is not implemented because the trait bound `T: Clone` is not satisfied
+note: the trait `Clone` must be implemented
+  --> $SRC_DIR/core/src/clone.rs:LL:COL
+
+error: aborting due to 1 previous error
+
+For more information about this error, try `rustc --explain E0308`.

From f4b4ab3b23d0f5aac4de9c71ffb678ce25e52159 Mon Sep 17 00:00:00 2001
From: usamoi <usamoi@outlook.com>
Date: Sat, 10 Jan 2026 20:53:43 +0800
Subject: [PATCH 95/97] remove fp16 target feature from some vreinterpret
 intrinsics

---
 .../src/arm_shared/neon/generated.rs          | 200 +++++++++---------
 .../spec/neon/arm_shared.spec.yml             |   2 -
 2 files changed, 100 insertions(+), 102 deletions(-)

diff --git a/library/stdarch/crates/core_arch/src/arm_shared/neon/generated.rs b/library/stdarch/crates/core_arch/src/arm_shared/neon/generated.rs
index 0aeb740efcd0..1a994c153ade 100644
--- a/library/stdarch/crates/core_arch/src/arm_shared/neon/generated.rs
+++ b/library/stdarch/crates/core_arch/src/arm_shared/neon/generated.rs
@@ -42565,13 +42565,13 @@ pub fn vrecpsq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_f16)"]
 #[inline]
 #[cfg(target_endian = "little")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -42588,13 +42588,13 @@ pub fn vreinterpret_f32_f16(a: float16x4_t) -> float32x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_f16)"]
 #[inline]
 #[cfg(target_endian = "big")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -42615,13 +42615,13 @@ pub fn vreinterpret_f32_f16(a: float16x4_t) -> float32x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_f16)"]
 #[inline]
 #[cfg(target_endian = "little")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -42638,13 +42638,13 @@ pub fn vreinterpret_s8_f16(a: float16x4_t) -> int8x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_f16)"]
 #[inline]
 #[cfg(target_endian = "big")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -42665,13 +42665,13 @@ pub fn vreinterpret_s8_f16(a: float16x4_t) -> int8x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_f16)"]
 #[inline]
 #[cfg(target_endian = "little")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -42688,13 +42688,13 @@ pub fn vreinterpret_s16_f16(a: float16x4_t) -> int16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_f16)"]
 #[inline]
 #[cfg(target_endian = "big")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -42715,13 +42715,13 @@ pub fn vreinterpret_s16_f16(a: float16x4_t) -> int16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_f16)"]
 #[inline]
 #[cfg(target_endian = "little")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -42738,13 +42738,13 @@ pub fn vreinterpret_s32_f16(a: float16x4_t) -> int32x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_f16)"]
 #[inline]
 #[cfg(target_endian = "big")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -42765,13 +42765,13 @@ pub fn vreinterpret_s32_f16(a: float16x4_t) -> int32x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_f16)"]
 #[inline]
 #[cfg(target_endian = "little")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -42788,13 +42788,13 @@ pub fn vreinterpret_s64_f16(a: float16x4_t) -> int64x1_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_f16)"]
 #[inline]
 #[cfg(target_endian = "big")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -42812,13 +42812,13 @@ pub fn vreinterpret_s64_f16(a: float16x4_t) -> int64x1_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_f16)"]
 #[inline]
 #[cfg(target_endian = "little")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -42835,13 +42835,13 @@ pub fn vreinterpret_u8_f16(a: float16x4_t) -> uint8x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_f16)"]
 #[inline]
 #[cfg(target_endian = "big")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -42862,13 +42862,13 @@ pub fn vreinterpret_u8_f16(a: float16x4_t) -> uint8x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_f16)"]
 #[inline]
 #[cfg(target_endian = "little")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -42885,13 +42885,13 @@ pub fn vreinterpret_u16_f16(a: float16x4_t) -> uint16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_f16)"]
 #[inline]
 #[cfg(target_endian = "big")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -42912,13 +42912,13 @@ pub fn vreinterpret_u16_f16(a: float16x4_t) -> uint16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_f16)"]
 #[inline]
 #[cfg(target_endian = "little")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -42935,13 +42935,13 @@ pub fn vreinterpret_u32_f16(a: float16x4_t) -> uint32x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_f16)"]
 #[inline]
 #[cfg(target_endian = "big")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -42962,13 +42962,13 @@ pub fn vreinterpret_u32_f16(a: float16x4_t) -> uint32x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_f16)"]
 #[inline]
 #[cfg(target_endian = "little")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -42985,13 +42985,13 @@ pub fn vreinterpret_u64_f16(a: float16x4_t) -> uint64x1_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_f16)"]
 #[inline]
 #[cfg(target_endian = "big")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -43009,13 +43009,13 @@ pub fn vreinterpret_u64_f16(a: float16x4_t) -> uint64x1_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_f16)"]
 #[inline]
 #[cfg(target_endian = "little")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -43032,13 +43032,13 @@ pub fn vreinterpret_p8_f16(a: float16x4_t) -> poly8x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_f16)"]
 #[inline]
 #[cfg(target_endian = "big")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -43059,13 +43059,13 @@ pub fn vreinterpret_p8_f16(a: float16x4_t) -> poly8x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_f16)"]
 #[inline]
 #[cfg(target_endian = "little")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -43082,13 +43082,13 @@ pub fn vreinterpret_p16_f16(a: float16x4_t) -> poly16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_f16)"]
 #[inline]
 #[cfg(target_endian = "big")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -43109,13 +43109,13 @@ pub fn vreinterpret_p16_f16(a: float16x4_t) -> poly16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_f16)"]
 #[inline]
 #[cfg(target_endian = "little")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -43132,13 +43132,13 @@ pub fn vreinterpretq_f32_f16(a: float16x8_t) -> float32x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_f16)"]
 #[inline]
 #[cfg(target_endian = "big")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -43159,13 +43159,13 @@ pub fn vreinterpretq_f32_f16(a: float16x8_t) -> float32x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_f16)"]
 #[inline]
 #[cfg(target_endian = "little")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -43182,13 +43182,13 @@ pub fn vreinterpretq_s8_f16(a: float16x8_t) -> int8x16_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_f16)"]
 #[inline]
 #[cfg(target_endian = "big")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -43213,13 +43213,13 @@ pub fn vreinterpretq_s8_f16(a: float16x8_t) -> int8x16_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_f16)"]
 #[inline]
 #[cfg(target_endian = "little")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -43236,13 +43236,13 @@ pub fn vreinterpretq_s16_f16(a: float16x8_t) -> int16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_f16)"]
 #[inline]
 #[cfg(target_endian = "big")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -43263,13 +43263,13 @@ pub fn vreinterpretq_s16_f16(a: float16x8_t) -> int16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_f16)"]
 #[inline]
 #[cfg(target_endian = "little")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -43286,13 +43286,13 @@ pub fn vreinterpretq_s32_f16(a: float16x8_t) -> int32x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_f16)"]
 #[inline]
 #[cfg(target_endian = "big")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -43313,13 +43313,13 @@ pub fn vreinterpretq_s32_f16(a: float16x8_t) -> int32x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_f16)"]
 #[inline]
 #[cfg(target_endian = "little")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -43336,13 +43336,13 @@ pub fn vreinterpretq_s64_f16(a: float16x8_t) -> int64x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_f16)"]
 #[inline]
 #[cfg(target_endian = "big")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -43363,13 +43363,13 @@ pub fn vreinterpretq_s64_f16(a: float16x8_t) -> int64x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_f16)"]
 #[inline]
 #[cfg(target_endian = "little")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -43386,13 +43386,13 @@ pub fn vreinterpretq_u8_f16(a: float16x8_t) -> uint8x16_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_f16)"]
 #[inline]
 #[cfg(target_endian = "big")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -43417,13 +43417,13 @@ pub fn vreinterpretq_u8_f16(a: float16x8_t) -> uint8x16_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_f16)"]
 #[inline]
 #[cfg(target_endian = "little")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -43440,13 +43440,13 @@ pub fn vreinterpretq_u16_f16(a: float16x8_t) -> uint16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_f16)"]
 #[inline]
 #[cfg(target_endian = "big")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -43467,13 +43467,13 @@ pub fn vreinterpretq_u16_f16(a: float16x8_t) -> uint16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_f16)"]
 #[inline]
 #[cfg(target_endian = "little")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -43490,13 +43490,13 @@ pub fn vreinterpretq_u32_f16(a: float16x8_t) -> uint32x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_f16)"]
 #[inline]
 #[cfg(target_endian = "big")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -43517,13 +43517,13 @@ pub fn vreinterpretq_u32_f16(a: float16x8_t) -> uint32x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_f16)"]
 #[inline]
 #[cfg(target_endian = "little")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -43540,13 +43540,13 @@ pub fn vreinterpretq_u64_f16(a: float16x8_t) -> uint64x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_f16)"]
 #[inline]
 #[cfg(target_endian = "big")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -43567,13 +43567,13 @@ pub fn vreinterpretq_u64_f16(a: float16x8_t) -> uint64x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_f16)"]
 #[inline]
 #[cfg(target_endian = "little")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -43590,13 +43590,13 @@ pub fn vreinterpretq_p8_f16(a: float16x8_t) -> poly8x16_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_f16)"]
 #[inline]
 #[cfg(target_endian = "big")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -43621,13 +43621,13 @@ pub fn vreinterpretq_p8_f16(a: float16x8_t) -> poly8x16_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_f16)"]
 #[inline]
 #[cfg(target_endian = "little")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -43644,13 +43644,13 @@ pub fn vreinterpretq_p16_f16(a: float16x8_t) -> poly16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_f16)"]
 #[inline]
 #[cfg(target_endian = "big")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -43671,13 +43671,13 @@ pub fn vreinterpretq_p16_f16(a: float16x8_t) -> poly16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_f32)"]
 #[inline]
 #[cfg(target_endian = "little")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -43694,13 +43694,13 @@ pub fn vreinterpret_f16_f32(a: float32x2_t) -> float16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_f32)"]
 #[inline]
 #[cfg(target_endian = "big")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -43721,13 +43721,13 @@ pub fn vreinterpret_f16_f32(a: float32x2_t) -> float16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_f32)"]
 #[inline]
 #[cfg(target_endian = "little")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -43744,13 +43744,13 @@ pub fn vreinterpretq_f16_f32(a: float32x4_t) -> float16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_f32)"]
 #[inline]
 #[cfg(target_endian = "big")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -43771,13 +43771,13 @@ pub fn vreinterpretq_f16_f32(a: float32x4_t) -> float16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s8)"]
 #[inline]
 #[cfg(target_endian = "little")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -43794,13 +43794,13 @@ pub fn vreinterpret_f16_s8(a: int8x8_t) -> float16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s8)"]
 #[inline]
 #[cfg(target_endian = "big")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -43821,13 +43821,13 @@ pub fn vreinterpret_f16_s8(a: int8x8_t) -> float16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s8)"]
 #[inline]
 #[cfg(target_endian = "little")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -43844,13 +43844,13 @@ pub fn vreinterpretq_f16_s8(a: int8x16_t) -> float16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s8)"]
 #[inline]
 #[cfg(target_endian = "big")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -43872,13 +43872,13 @@ pub fn vreinterpretq_f16_s8(a: int8x16_t) -> float16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s16)"]
 #[inline]
 #[cfg(target_endian = "little")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -43895,13 +43895,13 @@ pub fn vreinterpret_f16_s16(a: int16x4_t) -> float16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s16)"]
 #[inline]
 #[cfg(target_endian = "big")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -43922,13 +43922,13 @@ pub fn vreinterpret_f16_s16(a: int16x4_t) -> float16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s16)"]
 #[inline]
 #[cfg(target_endian = "little")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -43945,13 +43945,13 @@ pub fn vreinterpretq_f16_s16(a: int16x8_t) -> float16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s16)"]
 #[inline]
 #[cfg(target_endian = "big")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -43972,13 +43972,13 @@ pub fn vreinterpretq_f16_s16(a: int16x8_t) -> float16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s32)"]
 #[inline]
 #[cfg(target_endian = "little")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -43995,13 +43995,13 @@ pub fn vreinterpret_f16_s32(a: int32x2_t) -> float16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s32)"]
 #[inline]
 #[cfg(target_endian = "big")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -44022,13 +44022,13 @@ pub fn vreinterpret_f16_s32(a: int32x2_t) -> float16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s32)"]
 #[inline]
 #[cfg(target_endian = "little")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -44045,13 +44045,13 @@ pub fn vreinterpretq_f16_s32(a: int32x4_t) -> float16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s32)"]
 #[inline]
 #[cfg(target_endian = "big")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -44072,13 +44072,13 @@ pub fn vreinterpretq_f16_s32(a: int32x4_t) -> float16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s64)"]
 #[inline]
 #[cfg(target_endian = "little")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -44095,13 +44095,13 @@ pub fn vreinterpret_f16_s64(a: int64x1_t) -> float16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_s64)"]
 #[inline]
 #[cfg(target_endian = "big")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -44121,13 +44121,13 @@ pub fn vreinterpret_f16_s64(a: int64x1_t) -> float16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s64)"]
 #[inline]
 #[cfg(target_endian = "little")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -44144,13 +44144,13 @@ pub fn vreinterpretq_f16_s64(a: int64x2_t) -> float16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_s64)"]
 #[inline]
 #[cfg(target_endian = "big")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -44171,13 +44171,13 @@ pub fn vreinterpretq_f16_s64(a: int64x2_t) -> float16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u8)"]
 #[inline]
 #[cfg(target_endian = "little")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -44194,13 +44194,13 @@ pub fn vreinterpret_f16_u8(a: uint8x8_t) -> float16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u8)"]
 #[inline]
 #[cfg(target_endian = "big")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -44221,13 +44221,13 @@ pub fn vreinterpret_f16_u8(a: uint8x8_t) -> float16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u8)"]
 #[inline]
 #[cfg(target_endian = "little")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -44244,13 +44244,13 @@ pub fn vreinterpretq_f16_u8(a: uint8x16_t) -> float16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u8)"]
 #[inline]
 #[cfg(target_endian = "big")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -44272,13 +44272,13 @@ pub fn vreinterpretq_f16_u8(a: uint8x16_t) -> float16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u16)"]
 #[inline]
 #[cfg(target_endian = "little")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -44295,13 +44295,13 @@ pub fn vreinterpret_f16_u16(a: uint16x4_t) -> float16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u16)"]
 #[inline]
 #[cfg(target_endian = "big")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -44322,13 +44322,13 @@ pub fn vreinterpret_f16_u16(a: uint16x4_t) -> float16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u16)"]
 #[inline]
 #[cfg(target_endian = "little")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -44345,13 +44345,13 @@ pub fn vreinterpretq_f16_u16(a: uint16x8_t) -> float16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u16)"]
 #[inline]
 #[cfg(target_endian = "big")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -44372,13 +44372,13 @@ pub fn vreinterpretq_f16_u16(a: uint16x8_t) -> float16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u32)"]
 #[inline]
 #[cfg(target_endian = "little")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -44395,13 +44395,13 @@ pub fn vreinterpret_f16_u32(a: uint32x2_t) -> float16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u32)"]
 #[inline]
 #[cfg(target_endian = "big")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -44422,13 +44422,13 @@ pub fn vreinterpret_f16_u32(a: uint32x2_t) -> float16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u32)"]
 #[inline]
 #[cfg(target_endian = "little")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -44445,13 +44445,13 @@ pub fn vreinterpretq_f16_u32(a: uint32x4_t) -> float16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u32)"]
 #[inline]
 #[cfg(target_endian = "big")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -44472,13 +44472,13 @@ pub fn vreinterpretq_f16_u32(a: uint32x4_t) -> float16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u64)"]
 #[inline]
 #[cfg(target_endian = "little")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -44495,13 +44495,13 @@ pub fn vreinterpret_f16_u64(a: uint64x1_t) -> float16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_u64)"]
 #[inline]
 #[cfg(target_endian = "big")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -44521,13 +44521,13 @@ pub fn vreinterpret_f16_u64(a: uint64x1_t) -> float16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u64)"]
 #[inline]
 #[cfg(target_endian = "little")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -44544,13 +44544,13 @@ pub fn vreinterpretq_f16_u64(a: uint64x2_t) -> float16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_u64)"]
 #[inline]
 #[cfg(target_endian = "big")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -44571,13 +44571,13 @@ pub fn vreinterpretq_f16_u64(a: uint64x2_t) -> float16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_p8)"]
 #[inline]
 #[cfg(target_endian = "little")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -44594,13 +44594,13 @@ pub fn vreinterpret_f16_p8(a: poly8x8_t) -> float16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_p8)"]
 #[inline]
 #[cfg(target_endian = "big")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -44621,13 +44621,13 @@ pub fn vreinterpret_f16_p8(a: poly8x8_t) -> float16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p8)"]
 #[inline]
 #[cfg(target_endian = "little")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -44644,13 +44644,13 @@ pub fn vreinterpretq_f16_p8(a: poly8x16_t) -> float16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p8)"]
 #[inline]
 #[cfg(target_endian = "big")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -44672,13 +44672,13 @@ pub fn vreinterpretq_f16_p8(a: poly8x16_t) -> float16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_p16)"]
 #[inline]
 #[cfg(target_endian = "little")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -44695,13 +44695,13 @@ pub fn vreinterpret_f16_p16(a: poly16x4_t) -> float16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_p16)"]
 #[inline]
 #[cfg(target_endian = "big")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -44722,13 +44722,13 @@ pub fn vreinterpret_f16_p16(a: poly16x4_t) -> float16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p16)"]
 #[inline]
 #[cfg(target_endian = "little")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -44745,13 +44745,13 @@ pub fn vreinterpretq_f16_p16(a: poly16x8_t) -> float16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p16)"]
 #[inline]
 #[cfg(target_endian = "big")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -44772,13 +44772,13 @@ pub fn vreinterpretq_f16_p16(a: poly16x8_t) -> float16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p128)"]
 #[inline]
 #[cfg(target_endian = "little")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -44795,13 +44795,13 @@ pub fn vreinterpretq_f16_p128(a: p128) -> float16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p128)"]
 #[inline]
 #[cfg(target_endian = "big")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -44821,13 +44821,13 @@ pub fn vreinterpretq_f16_p128(a: p128) -> float16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_f16)"]
 #[inline]
 #[cfg(target_endian = "little")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -44844,13 +44844,13 @@ pub fn vreinterpret_p64_f16(a: float16x4_t) -> poly64x1_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_f16)"]
 #[inline]
 #[cfg(target_endian = "big")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -44868,13 +44868,13 @@ pub fn vreinterpret_p64_f16(a: float16x4_t) -> poly64x1_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_f16)"]
 #[inline]
 #[cfg(target_endian = "little")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -44891,13 +44891,13 @@ pub fn vreinterpretq_p128_f16(a: float16x8_t) -> p128 {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_f16)"]
 #[inline]
 #[cfg(target_endian = "big")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -44915,13 +44915,13 @@ pub fn vreinterpretq_p128_f16(a: float16x8_t) -> p128 {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_f16)"]
 #[inline]
 #[cfg(target_endian = "little")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -44938,13 +44938,13 @@ pub fn vreinterpretq_p64_f16(a: float16x8_t) -> poly64x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_f16)"]
 #[inline]
 #[cfg(target_endian = "big")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -44965,13 +44965,13 @@ pub fn vreinterpretq_p64_f16(a: float16x8_t) -> poly64x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_p64)"]
 #[inline]
 #[cfg(target_endian = "little")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -44988,13 +44988,13 @@ pub fn vreinterpret_f16_p64(a: poly64x1_t) -> float16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f16_p64)"]
 #[inline]
 #[cfg(target_endian = "big")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -45014,13 +45014,13 @@ pub fn vreinterpret_f16_p64(a: poly64x1_t) -> float16x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p64)"]
 #[inline]
 #[cfg(target_endian = "little")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
@@ -45037,13 +45037,13 @@ pub fn vreinterpretq_f16_p64(a: poly64x2_t) -> float16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f16_p64)"]
 #[inline]
 #[cfg(target_endian = "big")]
+#[target_feature(enable = "neon")]
 #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
     assert_instr(nop)
 )]
-#[target_feature(enable = "neon,fp16")]
 #[cfg_attr(
     not(target_arch = "arm"),
     stable(feature = "stdarch_neon_fp16", since = "CURRENT_RUSTC_VERSION")
diff --git a/library/stdarch/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml b/library/stdarch/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
index c7a333d7f75e..d8e8cd0e7c11 100644
--- a/library/stdarch/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
+++ b/library/stdarch/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
@@ -8785,7 +8785,6 @@ intrinsics:
       - *neon-v7
       - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [nop]]}]]
       - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [nop]]}]]
-      - *neon-fp16
       - *neon-not-arm-stable-fp16
       - *neon-cfg-arm-unstable
       - *target-not-arm64ec
@@ -8849,7 +8848,6 @@ intrinsics:
       - *neon-v8
       - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [nop]]}]]
       - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [nop]]}]]
-      - *neon-fp16
       - *neon-not-arm-stable-fp16
       - *neon-cfg-arm-unstable
       - *target-not-arm64ec

From 18a4a3ace0afcce1e4be81dbd9954c58bf60e5aa Mon Sep 17 00:00:00 2001
From: usamoi <usamoi@outlook.com>
Date: Wed, 28 Jan 2026 19:15:25 +0800
Subject: [PATCH 96/97] fix overflowing_literals in avx512fp16 tests

---
 library/stdarch/crates/core_arch/src/x86/avx512fp16.rs | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/library/stdarch/crates/core_arch/src/x86/avx512fp16.rs b/library/stdarch/crates/core_arch/src/x86/avx512fp16.rs
index 57d47c0bb010..2b80215c41af 100644
--- a/library/stdarch/crates/core_arch/src/x86/avx512fp16.rs
+++ b/library/stdarch/crates/core_arch/src/x86/avx512fp16.rs
@@ -23993,16 +23993,16 @@ mod tests {
 
     #[simd_test(enable = "avx512fp16,avx512vl")]
     const fn test_mm256_reduce_mul_ph() {
-        let a = _mm256_set1_ph(2.0);
+        let a = _mm256_set1_ph(1.2);
         let r = _mm256_reduce_mul_ph(a);
-        assert_eq!(r, 65536.0);
+        assert_eq!(r, 18.5);
     }
 
     #[simd_test(enable = "avx512fp16")]
     const fn test_mm512_reduce_mul_ph() {
-        let a = _mm512_set1_ph(2.0);
+        let a = _mm512_set1_ph(1.2);
         let r = _mm512_reduce_mul_ph(a);
-        assert_eq!(r, 16777216.0);
+        assert_eq!(r, 342.3);
     }
 
     #[simd_test(enable = "avx512fp16,avx512vl")]

From 9ca8ed38eb3d1e138cd8b6a8f586baa7fe52e980 Mon Sep 17 00:00:00 2001
From: Usman Akinyemi <usmanakinyemi202@gmail.com>
Date: Wed, 28 Jan 2026 02:54:32 +0530
Subject: [PATCH 97/97] rustc_parse: improve the error diagnostic for "missing
 let in let chain"

Signed-off-by: Usman Akinyemi <usmanakinyemi202@gmail.com>
---
 compiler/rustc_parse/src/parser/expr.rs       | 55 ++++++++++++++-----
 tests/ui/expr/if/bad-if-let-suggestion.rs     |  4 +-
 tests/ui/expr/if/bad-if-let-suggestion.stderr | 30 ++--------
 tests/ui/missing/missing-let.rs               |  6 ++
 tests/ui/missing/missing-let.stderr           | 18 ++++++
 5 files changed, 73 insertions(+), 40 deletions(-)
 create mode 100644 tests/ui/missing/missing-let.rs
 create mode 100644 tests/ui/missing/missing-let.stderr

diff --git a/compiler/rustc_parse/src/parser/expr.rs b/compiler/rustc_parse/src/parser/expr.rs
index c31a4798b471..44c6acec8866 100644
--- a/compiler/rustc_parse/src/parser/expr.rs
+++ b/compiler/rustc_parse/src/parser/expr.rs
@@ -2760,9 +2760,13 @@ impl<'a> Parser<'a> {
         let (mut cond, _) =
             self.parse_expr_res(Restrictions::NO_STRUCT_LITERAL | Restrictions::ALLOW_LET, attrs)?;
 
-        CondChecker::new(self, let_chains_policy).visit_expr(&mut cond);
-
-        Ok(cond)
+        let mut checker = CondChecker::new(self, let_chains_policy);
+        checker.visit_expr(&mut cond);
+        Ok(if let Some(guar) = checker.found_incorrect_let_chain {
+            self.mk_expr_err(cond.span, guar)
+        } else {
+            cond
+        })
     }
 
     /// Parses a `let $pat = $expr` pseudo-expression.
@@ -3484,13 +3488,19 @@ impl<'a> Parser<'a> {
         let if_span = self.prev_token.span;
         let mut cond = self.parse_match_guard_condition()?;
 
-        CondChecker::new(self, LetChainsPolicy::AlwaysAllowed).visit_expr(&mut cond);
+        let mut checker = CondChecker::new(self, LetChainsPolicy::AlwaysAllowed);
+        checker.visit_expr(&mut cond);
 
         if has_let_expr(&cond) {
             let span = if_span.to(cond.span);
             self.psess.gated_spans.gate(sym::if_let_guard, span);
         }
-        Ok(Some(cond))
+
+        Ok(Some(if let Some(guar) = checker.found_incorrect_let_chain {
+            self.mk_expr_err(cond.span, guar)
+        } else {
+            cond
+        }))
     }
 
     fn parse_match_arm_pat_and_guard(&mut self) -> PResult<'a, (Pat, Option<Box<Expr>>)> {
@@ -3511,13 +3521,23 @@ impl<'a> Parser<'a> {
                 let ast::PatKind::Paren(subpat) = pat.kind else { unreachable!() };
                 let ast::PatKind::Guard(_, mut cond) = subpat.kind else { unreachable!() };
                 self.psess.gated_spans.ungate_last(sym::guard_patterns, cond.span);
-                CondChecker::new(self, LetChainsPolicy::AlwaysAllowed).visit_expr(&mut cond);
+                let mut checker = CondChecker::new(self, LetChainsPolicy::AlwaysAllowed);
+                checker.visit_expr(&mut cond);
+
                 let right = self.prev_token.span;
                 self.dcx().emit_err(errors::ParenthesesInMatchPat {
                     span: vec![left, right],
                     sugg: errors::ParenthesesInMatchPatSugg { left, right },
                 });
-                Ok((self.mk_pat(span, ast::PatKind::Wild), Some(cond)))
+
+                Ok((
+                    self.mk_pat(span, ast::PatKind::Wild),
+                    (if let Some(guar) = checker.found_incorrect_let_chain {
+                        Some(self.mk_expr_err(cond.span, guar))
+                    } else {
+                        Some(cond)
+                    }),
+                ))
             } else {
                 Ok((pat, self.parse_match_arm_guard()?))
             }
@@ -4208,6 +4228,7 @@ struct CondChecker<'a> {
     forbid_let_reason: Option<ForbiddenLetReason>,
     missing_let: Option<errors::MaybeMissingLet>,
     comparison: Option<errors::MaybeComparison>,
+    found_incorrect_let_chain: Option<ErrorGuaranteed>,
 }
 
 impl<'a> CondChecker<'a> {
@@ -4218,6 +4239,7 @@ impl<'a> CondChecker<'a> {
             missing_let: None,
             comparison: None,
             let_chains_policy,
+            found_incorrect_let_chain: None,
             depth: 0,
         }
     }
@@ -4236,12 +4258,19 @@ impl MutVisitor for CondChecker<'_> {
                         NotSupportedOr(or_span) => {
                             self.parser.dcx().emit_err(errors::OrInLetChain { span: or_span })
                         }
-                        _ => self.parser.dcx().emit_err(errors::ExpectedExpressionFoundLet {
-                            span,
-                            reason,
-                            missing_let: self.missing_let,
-                            comparison: self.comparison,
-                        }),
+                        _ => {
+                            let guar =
+                                self.parser.dcx().emit_err(errors::ExpectedExpressionFoundLet {
+                                    span,
+                                    reason,
+                                    missing_let: self.missing_let,
+                                    comparison: self.comparison,
+                                });
+                            if let Some(_) = self.missing_let {
+                                self.found_incorrect_let_chain = Some(guar);
+                            }
+                            guar
+                        }
                     };
                     *recovered = Recovered::Yes(error);
                 } else if self.depth > 1 {
diff --git a/tests/ui/expr/if/bad-if-let-suggestion.rs b/tests/ui/expr/if/bad-if-let-suggestion.rs
index b0d0676e1ea7..c462e32c9ef5 100644
--- a/tests/ui/expr/if/bad-if-let-suggestion.rs
+++ b/tests/ui/expr/if/bad-if-let-suggestion.rs
@@ -1,8 +1,6 @@
 fn a() {
     if let x = 1 && i = 2 {}
-    //~^ ERROR cannot find value `i` in this scope
-    //~| ERROR mismatched types
-    //~| ERROR expected expression, found `let` statement
+    //~^ ERROR expected expression, found `let` statement
 }
 
 fn b() {
diff --git a/tests/ui/expr/if/bad-if-let-suggestion.stderr b/tests/ui/expr/if/bad-if-let-suggestion.stderr
index 4244a3bb06ee..d0838fec67d6 100644
--- a/tests/ui/expr/if/bad-if-let-suggestion.stderr
+++ b/tests/ui/expr/if/bad-if-let-suggestion.stderr
@@ -15,13 +15,7 @@ LL |     if let x = 1 && i == 2 {}
    |                        +
 
 error[E0425]: cannot find value `i` in this scope
-  --> $DIR/bad-if-let-suggestion.rs:2:21
-   |
-LL |     if let x = 1 && i = 2 {}
-   |                     ^ not found in this scope
-
-error[E0425]: cannot find value `i` in this scope
-  --> $DIR/bad-if-let-suggestion.rs:9:9
+  --> $DIR/bad-if-let-suggestion.rs:7:9
    |
 LL | fn a() {
    | ------ similarly named function `a` defined here
@@ -36,7 +30,7 @@ LL +     if (a + j) = i {}
    |
 
 error[E0425]: cannot find value `j` in this scope
-  --> $DIR/bad-if-let-suggestion.rs:9:13
+  --> $DIR/bad-if-let-suggestion.rs:7:13
    |
 LL | fn a() {
    | ------ similarly named function `a` defined here
@@ -51,7 +45,7 @@ LL +     if (i + a) = i {}
    |
 
 error[E0425]: cannot find value `i` in this scope
-  --> $DIR/bad-if-let-suggestion.rs:9:18
+  --> $DIR/bad-if-let-suggestion.rs:7:18
    |
 LL | fn a() {
    | ------ similarly named function `a` defined here
@@ -66,7 +60,7 @@ LL +     if (i + j) = a {}
    |
 
 error[E0425]: cannot find value `x` in this scope
-  --> $DIR/bad-if-let-suggestion.rs:16:8
+  --> $DIR/bad-if-let-suggestion.rs:14:8
    |
 LL | fn a() {
    | ------ similarly named function `a` defined here
@@ -80,18 +74,6 @@ LL -     if x[0] = 1 {}
 LL +     if a[0] = 1 {}
    |
 
-error[E0308]: mismatched types
-  --> $DIR/bad-if-let-suggestion.rs:2:8
-   |
-LL |     if let x = 1 && i = 2 {}
-   |        ^^^^^^^^^^^^^^^^^^ expected `bool`, found `()`
-   |
-help: you might have meant to compare for equality
-   |
-LL |     if let x = 1 && i == 2 {}
-   |                        +
+error: aborting due to 5 previous errors
 
-error: aborting due to 7 previous errors
-
-Some errors have detailed explanations: E0308, E0425.
-For more information about an error, try `rustc --explain E0308`.
+For more information about this error, try `rustc --explain E0425`.
diff --git a/tests/ui/missing/missing-let.rs b/tests/ui/missing/missing-let.rs
new file mode 100644
index 000000000000..36db7bc95826
--- /dev/null
+++ b/tests/ui/missing/missing-let.rs
@@ -0,0 +1,6 @@
+fn main() {
+    let x = Some(42);
+    if let Some(_) = x
+        && Some(x) = x //~^ ERROR expected expression, found `let` statement
+    {}
+}
diff --git a/tests/ui/missing/missing-let.stderr b/tests/ui/missing/missing-let.stderr
new file mode 100644
index 000000000000..897ff6329d59
--- /dev/null
+++ b/tests/ui/missing/missing-let.stderr
@@ -0,0 +1,18 @@
+error: expected expression, found `let` statement
+  --> $DIR/missing-let.rs:3:8
+   |
+LL |     if let Some(_) = x
+   |        ^^^^^^^^^^^^^^^
+   |
+   = note: only supported directly in conditions of `if` and `while` expressions
+help: you might have meant to continue the let-chain
+   |
+LL |         && let Some(x) = x
+   |            +++
+help: you might have meant to compare for equality
+   |
+LL |         && Some(x) == x
+   |                     +
+
+error: aborting due to 1 previous error
+