From cf14e15b7f76a85f22dc5a530c8f992d323e73a4 Mon Sep 17 00:00:00 2001
From: Gijs Burghoorn <g.burghoorn@gmail.com>
Date: Fri, 25 Aug 2023 19:04:00 +0200
Subject: [PATCH] Impr: Remove pack instructions as instrinsics

---
 .../crates/core_arch/src/riscv64/zk.rs        | 34 -------------------
 .../crates/core_arch/src/riscv_shared/zk.rs   | 33 ------------------
 2 files changed, 67 deletions(-)

diff --git a/library/stdarch/crates/core_arch/src/riscv64/zk.rs b/library/stdarch/crates/core_arch/src/riscv64/zk.rs
index a6aae49f260f..38725caf5d33 100644
--- a/library/stdarch/crates/core_arch/src/riscv64/zk.rs
+++ b/library/stdarch/crates/core_arch/src/riscv64/zk.rs
@@ -189,40 +189,6 @@ pub unsafe fn aes64ks2(rs1: u64, rs2: u64) -> u64 {
     _aes64ks2(rs1 as i64, rs2 as i64) as u64
 }
 
-/// Pack the low 16-bits of rs1 and rs2 into rd on RV64
-///
-/// This instruction packs the low 16 bits of rs1 and rs2 into the 32 least-significant bits of
-/// rd, sign extending the 32-bit result to the rest of rd. This instruction only exists on
-/// RV64 based systems.
-///
-/// Source: RISC-V Cryptography Extensions Volume I: Scalar & Entropy Source Instructions
-///
-/// Version: v1.0.1
-///
-/// Section: 3.26
-///
-/// # Safety
-///
-/// This function is safe to use if the `zbkb` target feature is present.
-#[target_feature(enable = "zbkb")]
-#[cfg_attr(test, assert_instr(packw))]
-#[inline]
-pub unsafe fn packw(rs1: u64, rs2: u64) -> u64 {
-    // Note: There is no LLVM intrinsic for this instruction currently.
-
-    let value: u64;
-    unsafe {
-        asm!(
-            "packw {rd},{rs1},{rs2}",
-            rd = lateout(reg) value,
-            rs1 = in(reg) rs1,
-            rs2 = in(reg) rs2,
-            options(pure, nomem, nostack),
-        )
-    }
-    value
-}
-
 /// Implements the Sigma0 transformation function as used in the SHA2-512 hash function \[49\]
 /// (Section 4.1.3).
 ///
diff --git a/library/stdarch/crates/core_arch/src/riscv_shared/zk.rs b/library/stdarch/crates/core_arch/src/riscv_shared/zk.rs
index 035f22d0724f..acf24991d825 100644
--- a/library/stdarch/crates/core_arch/src/riscv_shared/zk.rs
+++ b/library/stdarch/crates/core_arch/src/riscv_shared/zk.rs
@@ -56,39 +56,6 @@ extern "unadjusted" {
     fn _xperm4_64(rs1: i64, rs2: i64) -> i64;
 }
 
-/// Pack the low bytes of rs1 and rs2 into rd.
-///
-/// And the packh instruction packs the least-significant bytes of rs1 and rs2 into the 16
-/// least-significant bits of rd, zero extending the rest of rd.
-///
-/// Source: RISC-V Cryptography Extensions Volume I: Scalar & Entropy Source Instructions
-///
-/// Version: v1.0.1
-///
-/// Section: 3.18
-///
-/// # Safety
-///
-/// This function is safe to use if the `zbkb` target feature is present.
-#[target_feature(enable = "zbkb")]
-#[cfg_attr(test, assert_instr(packh))]
-#[inline]
-pub unsafe fn packh(rs1: usize, rs2: usize) -> usize {
-    // Note: There is no LLVM intrinsic for this instruction currently.
-
-    let value: usize;
-    unsafe {
-        asm!(
-            "packh {rd},{rs1},{rs2}",
-            rd = lateout(reg) value,
-            rs1 = in(reg) rs1,
-            rs2 = in(reg) rs2,
-            options(pure, nomem, nostack),
-        )
-    }
-    value
-}
-
 /// Byte-wise lookup of indicies into a vector in registers.
 ///
 /// The xperm8 instruction operates on bytes. The rs1 register contains a vector of XLEN/8