Merge branch 'master' into sync_from_rust_2025_12_20
This commit is contained in:
Antoni Boucher
commit
cf522c098c
5 changed files with 124 additions and 64 deletions
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@ -6,7 +6,7 @@
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)]
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#![no_core]
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#![allow(dead_code, internal_features, non_camel_case_types)]
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#![rustfmt_skip]
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#![cfg_attr(rustfmt, rustfmt_skip)]
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extern crate mini_core;
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24
src/archive.rs
Normal file
24
src/archive.rs
Normal file
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@ -0,0 +1,24 @@
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use std::path::Path;
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use rustc_codegen_ssa::back::archive::{
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ArArchiveBuilder, ArchiveBuilder, ArchiveBuilderBuilder, DEFAULT_OBJECT_READER,
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};
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use rustc_session::Session;
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pub(crate) struct ArArchiveBuilderBuilder;
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impl ArchiveBuilderBuilder for ArArchiveBuilderBuilder {
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fn new_archive_builder<'a>(&self, sess: &'a Session) -> Box<dyn ArchiveBuilder + 'a> {
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Box::new(ArArchiveBuilder::new(sess, &DEFAULT_OBJECT_READER))
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}
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fn create_dll_import_lib(
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&self,
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_sess: &Session,
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_lib_name: &str,
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_import_name_and_ordinal_vector: Vec<(String, Option<u16>)>,
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_output_path: &Path,
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) {
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unimplemented!("creating dll imports is not yet supported");
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}
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}
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@ -70,10 +70,6 @@ fn map_arch_intrinsic(full_name: &str) -> &'static str {
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"sve.sm4e" => "__builtin_sve_svsm4e_u32",
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"sve.sm4ekey" => "__builtin_sve_svsm4ekey_u32",
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"sve.wrffr" => "__builtin_sve_svwrffr",
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"tcancel" => "__builtin_arm_tcancel",
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"tcommit" => "__builtin_arm_tcommit",
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"tstart" => "__builtin_arm_tstart",
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"ttest" => "__builtin_arm_ttest",
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_ => unimplemented!("***** unsupported LLVM intrinsic {full_name}"),
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}
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}
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@ -1632,6 +1628,14 @@ fn map_arch_intrinsic(full_name: &str) -> &'static str {
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"V6.vabs.f8.128B" => "__builtin_HEXAGON_V6_vabs_f8_128B",
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"V6.vabs.hf" => "__builtin_HEXAGON_V6_vabs_hf",
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"V6.vabs.hf.128B" => "__builtin_HEXAGON_V6_vabs_hf_128B",
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"V6.vabs.qf16.hf" => "__builtin_HEXAGON_V6_vabs_qf16_hf",
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"V6.vabs.qf16.hf.128B" => "__builtin_HEXAGON_V6_vabs_qf16_hf_128B",
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"V6.vabs.qf16.qf16" => "__builtin_HEXAGON_V6_vabs_qf16_qf16",
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"V6.vabs.qf16.qf16.128B" => "__builtin_HEXAGON_V6_vabs_qf16_qf16_128B",
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"V6.vabs.qf32.qf32" => "__builtin_HEXAGON_V6_vabs_qf32_qf32",
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"V6.vabs.qf32.qf32.128B" => "__builtin_HEXAGON_V6_vabs_qf32_qf32_128B",
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"V6.vabs.qf32.sf" => "__builtin_HEXAGON_V6_vabs_qf32_sf",
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"V6.vabs.qf32.sf.128B" => "__builtin_HEXAGON_V6_vabs_qf32_sf_128B",
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"V6.vabs.sf" => "__builtin_HEXAGON_V6_vabs_sf",
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"V6.vabs.sf.128B" => "__builtin_HEXAGON_V6_vabs_sf_128B",
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"V6.vabsb" => "__builtin_HEXAGON_V6_vabsb",
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@ -1744,6 +1748,8 @@ fn map_arch_intrinsic(full_name: &str) -> &'static str {
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"V6.vaddwsat.128B" => "__builtin_HEXAGON_V6_vaddwsat_128B",
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"V6.vaddwsat.dv" => "__builtin_HEXAGON_V6_vaddwsat_dv",
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"V6.vaddwsat.dv.128B" => "__builtin_HEXAGON_V6_vaddwsat_dv_128B",
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"V6.valign4" => "__builtin_HEXAGON_V6_valign4",
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"V6.valign4.128B" => "__builtin_HEXAGON_V6_valign4_128B",
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"V6.valignb" => "__builtin_HEXAGON_V6_valignb",
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"V6.valignb.128B" => "__builtin_HEXAGON_V6_valignb_128B",
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"V6.valignbi" => "__builtin_HEXAGON_V6_valignbi",
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@ -1862,14 +1868,30 @@ fn map_arch_intrinsic(full_name: &str) -> &'static str {
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"V6.vcl0w.128B" => "__builtin_HEXAGON_V6_vcl0w_128B",
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"V6.vcombine" => "__builtin_HEXAGON_V6_vcombine",
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"V6.vcombine.128B" => "__builtin_HEXAGON_V6_vcombine_128B",
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"V6.vconv.bf.qf32" => "__builtin_HEXAGON_V6_vconv_bf_qf32",
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"V6.vconv.bf.qf32.128B" => "__builtin_HEXAGON_V6_vconv_bf_qf32_128B",
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"V6.vconv.f8.qf16" => "__builtin_HEXAGON_V6_vconv_f8_qf16",
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"V6.vconv.f8.qf16.128B" => "__builtin_HEXAGON_V6_vconv_f8_qf16_128B",
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"V6.vconv.h.hf" => "__builtin_HEXAGON_V6_vconv_h_hf",
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"V6.vconv.h.hf.128B" => "__builtin_HEXAGON_V6_vconv_h_hf_128B",
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"V6.vconv.h.hf.rnd" => "__builtin_HEXAGON_V6_vconv_h_hf_rnd",
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"V6.vconv.h.hf.rnd.128B" => "__builtin_HEXAGON_V6_vconv_h_hf_rnd_128B",
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"V6.vconv.hf.h" => "__builtin_HEXAGON_V6_vconv_hf_h",
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"V6.vconv.hf.h.128B" => "__builtin_HEXAGON_V6_vconv_hf_h_128B",
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"V6.vconv.hf.qf16" => "__builtin_HEXAGON_V6_vconv_hf_qf16",
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"V6.vconv.hf.qf16.128B" => "__builtin_HEXAGON_V6_vconv_hf_qf16_128B",
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"V6.vconv.hf.qf32" => "__builtin_HEXAGON_V6_vconv_hf_qf32",
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"V6.vconv.hf.qf32.128B" => "__builtin_HEXAGON_V6_vconv_hf_qf32_128B",
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"V6.vconv.qf16.f8" => "__builtin_HEXAGON_V6_vconv_qf16_f8",
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"V6.vconv.qf16.f8.128B" => "__builtin_HEXAGON_V6_vconv_qf16_f8_128B",
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"V6.vconv.qf16.hf" => "__builtin_HEXAGON_V6_vconv_qf16_hf",
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"V6.vconv.qf16.hf.128B" => "__builtin_HEXAGON_V6_vconv_qf16_hf_128B",
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"V6.vconv.qf16.qf16" => "__builtin_HEXAGON_V6_vconv_qf16_qf16",
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"V6.vconv.qf16.qf16.128B" => "__builtin_HEXAGON_V6_vconv_qf16_qf16_128B",
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"V6.vconv.qf32.qf32" => "__builtin_HEXAGON_V6_vconv_qf32_qf32",
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"V6.vconv.qf32.qf32.128B" => "__builtin_HEXAGON_V6_vconv_qf32_qf32_128B",
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"V6.vconv.qf32.sf" => "__builtin_HEXAGON_V6_vconv_qf32_sf",
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"V6.vconv.qf32.sf.128B" => "__builtin_HEXAGON_V6_vconv_qf32_sf_128B",
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"V6.vconv.sf.qf32" => "__builtin_HEXAGON_V6_vconv_sf_qf32",
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"V6.vconv.sf.qf32.128B" => "__builtin_HEXAGON_V6_vconv_sf_qf32_128B",
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"V6.vconv.sf.w" => "__builtin_HEXAGON_V6_vconv_sf_w",
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@ -1984,6 +2006,22 @@ fn map_arch_intrinsic(full_name: &str) -> &'static str {
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"V6.veqh.or.128B" => "__builtin_HEXAGON_V6_veqh_or_128B",
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"V6.veqh.xor" => "__builtin_HEXAGON_V6_veqh_xor",
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"V6.veqh.xor.128B" => "__builtin_HEXAGON_V6_veqh_xor_128B",
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"V6.veqhf" => "__builtin_HEXAGON_V6_veqhf",
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"V6.veqhf.128B" => "__builtin_HEXAGON_V6_veqhf_128B",
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"V6.veqhf.and" => "__builtin_HEXAGON_V6_veqhf_and",
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"V6.veqhf.and.128B" => "__builtin_HEXAGON_V6_veqhf_and_128B",
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"V6.veqhf.or" => "__builtin_HEXAGON_V6_veqhf_or",
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"V6.veqhf.or.128B" => "__builtin_HEXAGON_V6_veqhf_or_128B",
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"V6.veqhf.xor" => "__builtin_HEXAGON_V6_veqhf_xor",
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"V6.veqhf.xor.128B" => "__builtin_HEXAGON_V6_veqhf_xor_128B",
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"V6.veqsf" => "__builtin_HEXAGON_V6_veqsf",
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"V6.veqsf.128B" => "__builtin_HEXAGON_V6_veqsf_128B",
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"V6.veqsf.and" => "__builtin_HEXAGON_V6_veqsf_and",
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"V6.veqsf.and.128B" => "__builtin_HEXAGON_V6_veqsf_and_128B",
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"V6.veqsf.or" => "__builtin_HEXAGON_V6_veqsf_or",
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"V6.veqsf.or.128B" => "__builtin_HEXAGON_V6_veqsf_or_128B",
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"V6.veqsf.xor" => "__builtin_HEXAGON_V6_veqsf_xor",
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"V6.veqsf.xor.128B" => "__builtin_HEXAGON_V6_veqsf_xor_128B",
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"V6.veqw" => "__builtin_HEXAGON_V6_veqw",
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"V6.veqw.128B" => "__builtin_HEXAGON_V6_veqw_128B",
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"V6.veqw.and" => "__builtin_HEXAGON_V6_veqw_and",
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@ -2096,6 +2134,14 @@ fn map_arch_intrinsic(full_name: &str) -> &'static str {
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"V6.vgtw.or.128B" => "__builtin_HEXAGON_V6_vgtw_or_128B",
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"V6.vgtw.xor" => "__builtin_HEXAGON_V6_vgtw_xor",
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"V6.vgtw.xor.128B" => "__builtin_HEXAGON_V6_vgtw_xor_128B",
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"V6.vilog2.hf" => "__builtin_HEXAGON_V6_vilog2_hf",
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"V6.vilog2.hf.128B" => "__builtin_HEXAGON_V6_vilog2_hf_128B",
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"V6.vilog2.qf16" => "__builtin_HEXAGON_V6_vilog2_qf16",
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"V6.vilog2.qf16.128B" => "__builtin_HEXAGON_V6_vilog2_qf16_128B",
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"V6.vilog2.qf32" => "__builtin_HEXAGON_V6_vilog2_qf32",
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"V6.vilog2.qf32.128B" => "__builtin_HEXAGON_V6_vilog2_qf32_128B",
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"V6.vilog2.sf" => "__builtin_HEXAGON_V6_vilog2_sf",
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"V6.vilog2.sf.128B" => "__builtin_HEXAGON_V6_vilog2_sf_128B",
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"V6.vinsertwr" => "__builtin_HEXAGON_V6_vinsertwr",
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"V6.vinsertwr.128B" => "__builtin_HEXAGON_V6_vinsertwr_128B",
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"V6.vlalignb" => "__builtin_HEXAGON_V6_vlalignb",
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@ -2350,6 +2396,14 @@ fn map_arch_intrinsic(full_name: &str) -> &'static str {
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"V6.vnavgub.128B" => "__builtin_HEXAGON_V6_vnavgub_128B",
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"V6.vnavgw" => "__builtin_HEXAGON_V6_vnavgw",
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"V6.vnavgw.128B" => "__builtin_HEXAGON_V6_vnavgw_128B",
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"V6.vneg.qf16.hf" => "__builtin_HEXAGON_V6_vneg_qf16_hf",
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"V6.vneg.qf16.hf.128B" => "__builtin_HEXAGON_V6_vneg_qf16_hf_128B",
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"V6.vneg.qf16.qf16" => "__builtin_HEXAGON_V6_vneg_qf16_qf16",
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"V6.vneg.qf16.qf16.128B" => "__builtin_HEXAGON_V6_vneg_qf16_qf16_128B",
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"V6.vneg.qf32.qf32" => "__builtin_HEXAGON_V6_vneg_qf32_qf32",
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"V6.vneg.qf32.qf32.128B" => "__builtin_HEXAGON_V6_vneg_qf32_qf32_128B",
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"V6.vneg.qf32.sf" => "__builtin_HEXAGON_V6_vneg_qf32_sf",
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"V6.vneg.qf32.sf.128B" => "__builtin_HEXAGON_V6_vneg_qf32_sf_128B",
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"V6.vnormamth" => "__builtin_HEXAGON_V6_vnormamth",
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"V6.vnormamth.128B" => "__builtin_HEXAGON_V6_vnormamth_128B",
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"V6.vnormamtw" => "__builtin_HEXAGON_V6_vnormamtw",
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@ -2684,6 +2738,24 @@ fn map_arch_intrinsic(full_name: &str) -> &'static str {
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"iocsrwr.d" => "__builtin_loongarch_iocsrwr_d",
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"iocsrwr.h" => "__builtin_loongarch_iocsrwr_h",
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"iocsrwr.w" => "__builtin_loongarch_iocsrwr_w",
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"lasx.cast.128" => "__builtin_lasx_cast_128",
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"lasx.cast.128.d" => "__builtin_lasx_cast_128_d",
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"lasx.cast.128.s" => "__builtin_lasx_cast_128_s",
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"lasx.concat.128" => "__builtin_lasx_concat_128",
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"lasx.concat.128.d" => "__builtin_lasx_concat_128_d",
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"lasx.concat.128.s" => "__builtin_lasx_concat_128_s",
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"lasx.extract.128.hi" => "__builtin_lasx_extract_128_hi",
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"lasx.extract.128.hi.d" => "__builtin_lasx_extract_128_hi_d",
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"lasx.extract.128.hi.s" => "__builtin_lasx_extract_128_hi_s",
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"lasx.extract.128.lo" => "__builtin_lasx_extract_128_lo",
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"lasx.extract.128.lo.d" => "__builtin_lasx_extract_128_lo_d",
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"lasx.extract.128.lo.s" => "__builtin_lasx_extract_128_lo_s",
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"lasx.insert.128.hi" => "__builtin_lasx_insert_128_hi",
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"lasx.insert.128.hi.d" => "__builtin_lasx_insert_128_hi_d",
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"lasx.insert.128.hi.s" => "__builtin_lasx_insert_128_hi_s",
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"lasx.insert.128.lo" => "__builtin_lasx_insert_128_lo",
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"lasx.insert.128.lo.d" => "__builtin_lasx_insert_128_lo_d",
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"lasx.insert.128.lo.s" => "__builtin_lasx_insert_128_lo_s",
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"lasx.vext2xv.d.b" => "__builtin_lasx_vext2xv_d_b",
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"lasx.vext2xv.d.h" => "__builtin_lasx_vext2xv_d_h",
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"lasx.vext2xv.d.w" => "__builtin_lasx_vext2xv_d_w",
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@ -4950,8 +5022,20 @@ fn map_arch_intrinsic(full_name: &str) -> &'static str {
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"f16x2.to.e5m2x2.rn.relu" => "__nvvm_f16x2_to_e5m2x2_rn_relu",
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"f2bf16.rn" => "__nvvm_f2bf16_rn",
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"f2bf16.rn.relu" => "__nvvm_f2bf16_rn_relu",
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"f2bf16.rn.relu.satfinite" => "__nvvm_f2bf16_rn_relu_satfinite",
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"f2bf16.rn.satfinite" => "__nvvm_f2bf16_rn_satfinite",
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"f2bf16.rz" => "__nvvm_f2bf16_rz",
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"f2bf16.rz.relu" => "__nvvm_f2bf16_rz_relu",
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"f2bf16.rz.relu.satfinite" => "__nvvm_f2bf16_rz_relu_satfinite",
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"f2bf16.rz.satfinite" => "__nvvm_f2bf16_rz_satfinite",
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"f2f16.rn" => "__nvvm_f2f16_rn",
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"f2f16.rn.relu" => "__nvvm_f2f16_rn_relu",
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"f2f16.rn.relu.satfinite" => "__nvvm_f2f16_rn_relu_satfinite",
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"f2f16.rn.satfinite" => "__nvvm_f2f16_rn_satfinite",
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"f2f16.rz" => "__nvvm_f2f16_rz",
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"f2f16.rz.relu" => "__nvvm_f2f16_rz_relu",
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||||
"f2f16.rz.relu.satfinite" => "__nvvm_f2f16_rz_relu_satfinite",
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"f2f16.rz.satfinite" => "__nvvm_f2f16_rz_satfinite",
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"f2h.rn" => "__nvvm_f2h_rn",
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"f2h.rn.ftz" => "__nvvm_f2h_rn_ftz",
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"f2i.rm" => "__nvvm_f2i_rm",
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|
@ -5035,20 +5119,28 @@ fn map_arch_intrinsic(full_name: &str) -> &'static str {
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"ff.to.ue8m0x2.rz.satfinite" => "__nvvm_ff_to_ue8m0x2_rz_satfinite",
|
||||
"ff2bf16x2.rn" => "__nvvm_ff2bf16x2_rn",
|
||||
"ff2bf16x2.rn.relu" => "__nvvm_ff2bf16x2_rn_relu",
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||||
"ff2bf16x2.rn.relu.satfinite" => "__nvvm_ff2bf16x2_rn_relu_satfinite",
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||||
"ff2bf16x2.rn.satfinite" => "__nvvm_ff2bf16x2_rn_satfinite",
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"ff2bf16x2.rs" => "__nvvm_ff2bf16x2_rs",
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"ff2bf16x2.rs.relu" => "__nvvm_ff2bf16x2_rs_relu",
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"ff2bf16x2.rs.relu.satfinite" => "__nvvm_ff2bf16x2_rs_relu_satfinite",
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"ff2bf16x2.rs.satfinite" => "__nvvm_ff2bf16x2_rs_satfinite",
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"ff2bf16x2.rz" => "__nvvm_ff2bf16x2_rz",
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"ff2bf16x2.rz.relu" => "__nvvm_ff2bf16x2_rz_relu",
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"ff2bf16x2.rz.relu.satfinite" => "__nvvm_ff2bf16x2_rz_relu_satfinite",
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"ff2bf16x2.rz.satfinite" => "__nvvm_ff2bf16x2_rz_satfinite",
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"ff2f16x2.rn" => "__nvvm_ff2f16x2_rn",
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"ff2f16x2.rn.relu" => "__nvvm_ff2f16x2_rn_relu",
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"ff2f16x2.rn.relu.satfinite" => "__nvvm_ff2f16x2_rn_relu_satfinite",
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"ff2f16x2.rn.satfinite" => "__nvvm_ff2f16x2_rn_satfinite",
|
||||
"ff2f16x2.rs" => "__nvvm_ff2f16x2_rs",
|
||||
"ff2f16x2.rs.relu" => "__nvvm_ff2f16x2_rs_relu",
|
||||
"ff2f16x2.rs.relu.satfinite" => "__nvvm_ff2f16x2_rs_relu_satfinite",
|
||||
"ff2f16x2.rs.satfinite" => "__nvvm_ff2f16x2_rs_satfinite",
|
||||
"ff2f16x2.rz" => "__nvvm_ff2f16x2_rz",
|
||||
"ff2f16x2.rz.relu" => "__nvvm_ff2f16x2_rz_relu",
|
||||
"ff2f16x2.rz.relu.satfinite" => "__nvvm_ff2f16x2_rz_relu_satfinite",
|
||||
"ff2f16x2.rz.satfinite" => "__nvvm_ff2f16x2_rz_satfinite",
|
||||
"floor.d" => "__nvvm_floor_d",
|
||||
"floor.f" => "__nvvm_floor_f",
|
||||
"floor.ftz.f" => "__nvvm_floor_ftz_f",
|
||||
|
|
@ -5942,6 +6034,8 @@ fn map_arch_intrinsic(full_name: &str) -> &'static str {
|
|||
"altivec.vupklsb" => "__builtin_altivec_vupklsb",
|
||||
"altivec.vupklsh" => "__builtin_altivec_vupklsh",
|
||||
"altivec.vupklsw" => "__builtin_altivec_vupklsw",
|
||||
"amo.ldat" => "__builtin_amo_ldat",
|
||||
"amo.lwat" => "__builtin_amo_lwat",
|
||||
"bcdadd" => "__builtin_ppc_bcdadd",
|
||||
"bcdadd.p" => "__builtin_ppc_bcdadd_p",
|
||||
"bcdcopysign" => "__builtin_ppc_bcdcopysign",
|
||||
|
|
@ -6202,6 +6296,7 @@ fn map_arch_intrinsic(full_name: &str) -> &'static str {
|
|||
"vsx.xvminsp" => "__builtin_vsx_xvminsp",
|
||||
"vsx.xvredp" => "__builtin_vsx_xvredp",
|
||||
"vsx.xvresp" => "__builtin_vsx_xvresp",
|
||||
"vsx.xvrlw" => "__builtin_vsx_xvrlw",
|
||||
"vsx.xvrsqrtedp" => "__builtin_vsx_xvrsqrtedp",
|
||||
"vsx.xvrsqrtesp" => "__builtin_vsx_xvrsqrtesp",
|
||||
"vsx.xvtdivdp" => "__builtin_vsx_xvtdivdp",
|
||||
|
|
@ -10158,24 +10253,16 @@ fn map_arch_intrinsic(full_name: &str) -> &'static str {
|
|||
"stui" => "__builtin_ia32_stui",
|
||||
"subborrow.u32" => "__builtin_ia32_subborrow_u32",
|
||||
"subborrow.u64" => "__builtin_ia32_subborrow_u64",
|
||||
"t2rpntlvwz0" => "__builtin_ia32_t2rpntlvwz0",
|
||||
"t2rpntlvwz0rs" => "__builtin_ia32_t2rpntlvwz0rs",
|
||||
"t2rpntlvwz0rst1" => "__builtin_ia32_t2rpntlvwz0rst1",
|
||||
"t2rpntlvwz0t1" => "__builtin_ia32_t2rpntlvwz0t1",
|
||||
"t2rpntlvwz1" => "__builtin_ia32_t2rpntlvwz1",
|
||||
"t2rpntlvwz1rs" => "__builtin_ia32_t2rpntlvwz1rs",
|
||||
"t2rpntlvwz1rst1" => "__builtin_ia32_t2rpntlvwz1rst1",
|
||||
"t2rpntlvwz1t1" => "__builtin_ia32_t2rpntlvwz1t1",
|
||||
"tbm.bextri.u32" => "__builtin_ia32_bextri_u32",
|
||||
"tbm.bextri.u64" => "__builtin_ia32_bextri_u64",
|
||||
"tcmmimfp16ps" => "__builtin_ia32_tcmmimfp16ps",
|
||||
"tcmmimfp16ps.internal" => "__builtin_ia32_tcmmimfp16ps_internal",
|
||||
"tcmmrlfp16ps" => "__builtin_ia32_tcmmrlfp16ps",
|
||||
"tcmmrlfp16ps.internal" => "__builtin_ia32_tcmmrlfp16ps_internal",
|
||||
"tconjtcmmimfp16ps" => "__builtin_ia32_tconjtcmmimfp16ps",
|
||||
"tconjtcmmimfp16ps.internal" => "__builtin_ia32_tconjtcmmimfp16ps_internal",
|
||||
"tconjtfp16" => "__builtin_ia32_tconjtfp16",
|
||||
"tconjtfp16.internal" => "__builtin_ia32_tconjtfp16_internal",
|
||||
"tcvtrowd2ps" => "__builtin_ia32_tcvtrowd2ps",
|
||||
"tcvtrowd2ps.internal" => "__builtin_ia32_tcvtrowd2ps_internal",
|
||||
"tcvtrowps2bf16h" => "__builtin_ia32_tcvtrowps2bf16h",
|
||||
|
|
@ -10225,18 +10312,6 @@ fn map_arch_intrinsic(full_name: &str) -> &'static str {
|
|||
"tmmultf32ps" => "__builtin_ia32_tmmultf32ps",
|
||||
"tmmultf32ps.internal" => "__builtin_ia32_tmmultf32ps_internal",
|
||||
"tpause" => "__builtin_ia32_tpause",
|
||||
"ttcmmimfp16ps" => "__builtin_ia32_ttcmmimfp16ps",
|
||||
"ttcmmimfp16ps.internal" => "__builtin_ia32_ttcmmimfp16ps_internal",
|
||||
"ttcmmrlfp16ps" => "__builtin_ia32_ttcmmrlfp16ps",
|
||||
"ttcmmrlfp16ps.internal" => "__builtin_ia32_ttcmmrlfp16ps_internal",
|
||||
"ttdpbf16ps" => "__builtin_ia32_ttdpbf16ps",
|
||||
"ttdpbf16ps.internal" => "__builtin_ia32_ttdpbf16ps_internal",
|
||||
"ttdpfp16ps" => "__builtin_ia32_ttdpfp16ps",
|
||||
"ttdpfp16ps.internal" => "__builtin_ia32_ttdpfp16ps_internal",
|
||||
"ttmmultf32ps" => "__builtin_ia32_ttmmultf32ps",
|
||||
"ttmmultf32ps.internal" => "__builtin_ia32_ttmmultf32ps_internal",
|
||||
"ttransposed" => "__builtin_ia32_ttransposed",
|
||||
"ttransposed.internal" => "__builtin_ia32_ttransposed_internal",
|
||||
"umonitor" => "__builtin_ia32_umonitor",
|
||||
"umwait" => "__builtin_ia32_umwait",
|
||||
"urdmsr" => "__builtin_ia32_urdmsr",
|
||||
|
|
|
|||
|
|
@ -73,44 +73,8 @@ fn get_simple_intrinsic<'gcc, 'tcx>(
|
|||
sym::fabsf64 => "fabs",
|
||||
sym::minnumf32 => "fminf",
|
||||
sym::minnumf64 => "fmin",
|
||||
sym::minimumf32 => "fminimumf",
|
||||
sym::minimumf64 => "fminimum",
|
||||
sym::minimumf128 => {
|
||||
// GCC doesn't have the intrinsic we want so we use the compiler-builtins one
|
||||
// https://docs.rs/compiler_builtins/latest/compiler_builtins/math/full_availability/fn.fminimumf128.html
|
||||
let f128_type = cx.type_f128();
|
||||
return Some(cx.context.new_function(
|
||||
None,
|
||||
FunctionType::Extern,
|
||||
f128_type,
|
||||
&[
|
||||
cx.context.new_parameter(None, f128_type, "a"),
|
||||
cx.context.new_parameter(None, f128_type, "b"),
|
||||
],
|
||||
"fminimumf128",
|
||||
false,
|
||||
));
|
||||
}
|
||||
sym::maxnumf32 => "fmaxf",
|
||||
sym::maxnumf64 => "fmax",
|
||||
sym::maximumf32 => "fmaximumf",
|
||||
sym::maximumf64 => "fmaximum",
|
||||
sym::maximumf128 => {
|
||||
// GCC doesn't have the intrinsic we want so we use the compiler-builtins one
|
||||
// https://docs.rs/compiler_builtins/latest/compiler_builtins/math/full_availability/fn.fmaximumf128.html
|
||||
let f128_type = cx.type_f128();
|
||||
return Some(cx.context.new_function(
|
||||
None,
|
||||
FunctionType::Extern,
|
||||
f128_type,
|
||||
&[
|
||||
cx.context.new_parameter(None, f128_type, "a"),
|
||||
cx.context.new_parameter(None, f128_type, "b"),
|
||||
],
|
||||
"fmaximumf128",
|
||||
false,
|
||||
));
|
||||
}
|
||||
sym::copysignf32 => "copysignf",
|
||||
sym::copysignf64 => "copysign",
|
||||
sym::floorf32 => "floorf",
|
||||
|
|
|
|||
|
|
@ -2,6 +2,3 @@
|
|||
|
||||
# Prevents un-canonicalized issue links (to avoid wrong issues being linked in r-l/rust)
|
||||
[issue-links]
|
||||
|
||||
# Prevents mentions in commits to avoid users being spammed
|
||||
[no-mentions]
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue