mark BMI1 intrinsics as safe

Mark all BMI1 intrinsics as safe.

library/stdarch/crates/core_arch/src/x86/bmi1.rs

@@ -20,7 +20,7 @@ use stdarch_test::assert_instr;
 #[target_feature(enable = "bmi1")]
 #[cfg_attr(test, assert_instr(bextr))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub unsafe fn _bextr_u32(a: u32, start: u32, len: u32) -> u32 {
+pub fn _bextr_u32(a: u32, start: u32, len: u32) -> u32 {
     _bextr2_u32(a, (start & 0xff_u32) | ((len & 0xff_u32) << 8_u32))
 }
 
@@ -35,8 +35,8 @@ pub unsafe fn _bextr_u32(a: u32, start: u32, len: u32) -> u32 {
 #[target_feature(enable = "bmi1")]
 #[cfg_attr(test, assert_instr(bextr))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub unsafe fn _bextr2_u32(a: u32, control: u32) -> u32 {
-    x86_bmi_bextr_32(a, control)
+pub fn _bextr2_u32(a: u32, control: u32) -> u32 {
+    unsafe { x86_bmi_bextr_32(a, control) }
 }
 
 /// Bitwise logical `AND` of inverted `a` with `b`.
@@ -46,7 +46,7 @@ pub unsafe fn _bextr2_u32(a: u32, control: u32) -> u32 {
 #[target_feature(enable = "bmi1")]
 #[cfg_attr(test, assert_instr(andn))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub unsafe fn _andn_u32(a: u32, b: u32) -> u32 {
+pub fn _andn_u32(a: u32, b: u32) -> u32 {
     !a & b
 }
 
@@ -57,7 +57,7 @@ pub unsafe fn _andn_u32(a: u32, b: u32) -> u32 {
 #[target_feature(enable = "bmi1")]
 #[cfg_attr(test, assert_instr(blsi))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub unsafe fn _blsi_u32(x: u32) -> u32 {
+pub fn _blsi_u32(x: u32) -> u32 {
     x & x.wrapping_neg()
 }
 
@@ -68,7 +68,7 @@ pub unsafe fn _blsi_u32(x: u32) -> u32 {
 #[target_feature(enable = "bmi1")]
 #[cfg_attr(test, assert_instr(blsmsk))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub unsafe fn _blsmsk_u32(x: u32) -> u32 {
+pub fn _blsmsk_u32(x: u32) -> u32 {
     x ^ (x.wrapping_sub(1_u32))
 }
 
@@ -81,7 +81,7 @@ pub unsafe fn _blsmsk_u32(x: u32) -> u32 {
 #[target_feature(enable = "bmi1")]
 #[cfg_attr(test, assert_instr(blsr))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub unsafe fn _blsr_u32(x: u32) -> u32 {
+pub fn _blsr_u32(x: u32) -> u32 {
     x & (x.wrapping_sub(1))
 }
 
@@ -94,7 +94,7 @@ pub unsafe fn _blsr_u32(x: u32) -> u32 {
 #[target_feature(enable = "bmi1")]
 #[cfg_attr(test, assert_instr(tzcnt))]
 #[stable(feature = "simd_x86_updates", since = "1.82.0")]
-pub unsafe fn _tzcnt_u16(x: u16) -> u16 {
+pub fn _tzcnt_u16(x: u16) -> u16 {
     x.trailing_zeros() as u16
 }
 
@@ -107,7 +107,7 @@ pub unsafe fn _tzcnt_u16(x: u16) -> u16 {
 #[target_feature(enable = "bmi1")]
 #[cfg_attr(test, assert_instr(tzcnt))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub unsafe fn _tzcnt_u32(x: u32) -> u32 {
+pub fn _tzcnt_u32(x: u32) -> u32 {
     x.trailing_zeros()
 }
 
@@ -120,7 +120,7 @@ pub unsafe fn _tzcnt_u32(x: u32) -> u32 {
 #[target_feature(enable = "bmi1")]
 #[cfg_attr(test, assert_instr(tzcnt))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub unsafe fn _mm_tzcnt_32(x: u32) -> i32 {
+pub fn _mm_tzcnt_32(x: u32) -> i32 {
     x.trailing_zeros() as i32
 }
 

library/stdarch/crates/core_arch/src/x86_64/bmi.rs

@@ -21,7 +21,7 @@ use stdarch_test::assert_instr;
 #[cfg_attr(test, assert_instr(bextr))]
 #[cfg(not(target_arch = "x86"))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub unsafe fn _bextr_u64(a: u64, start: u32, len: u32) -> u64 {
+pub fn _bextr_u64(a: u64, start: u32, len: u32) -> u64 {
     _bextr2_u64(a, ((start & 0xff) | ((len & 0xff) << 8)) as u64)
 }
 
@@ -37,8 +37,8 @@ pub unsafe fn _bextr_u64(a: u64, start: u32, len: u32) -> u64 {
 #[cfg_attr(test, assert_instr(bextr))]
 #[cfg(not(target_arch = "x86"))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub unsafe fn _bextr2_u64(a: u64, control: u64) -> u64 {
-    x86_bmi_bextr_64(a, control)
+pub fn _bextr2_u64(a: u64, control: u64) -> u64 {
+    unsafe { x86_bmi_bextr_64(a, control) }
 }
 
 /// Bitwise logical `AND` of inverted `a` with `b`.
@@ -48,7 +48,7 @@ pub unsafe fn _bextr2_u64(a: u64, control: u64) -> u64 {
 #[target_feature(enable = "bmi1")]
 #[cfg_attr(test, assert_instr(andn))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub unsafe fn _andn_u64(a: u64, b: u64) -> u64 {
+pub fn _andn_u64(a: u64, b: u64) -> u64 {
     !a & b
 }
 
@@ -60,7 +60,7 @@ pub unsafe fn _andn_u64(a: u64, b: u64) -> u64 {
 #[cfg_attr(test, assert_instr(blsi))]
 #[cfg(not(target_arch = "x86"))] // generates lots of instructions
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub unsafe fn _blsi_u64(x: u64) -> u64 {
+pub fn _blsi_u64(x: u64) -> u64 {
     x & x.wrapping_neg()
 }
 
@@ -72,7 +72,7 @@ pub unsafe fn _blsi_u64(x: u64) -> u64 {
 #[cfg_attr(test, assert_instr(blsmsk))]
 #[cfg(not(target_arch = "x86"))] // generates lots of instructions
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub unsafe fn _blsmsk_u64(x: u64) -> u64 {
+pub fn _blsmsk_u64(x: u64) -> u64 {
     x ^ (x.wrapping_sub(1_u64))
 }
 
@@ -86,7 +86,7 @@ pub unsafe fn _blsmsk_u64(x: u64) -> u64 {
 #[cfg_attr(test, assert_instr(blsr))]
 #[cfg(not(target_arch = "x86"))] // generates lots of instructions
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub unsafe fn _blsr_u64(x: u64) -> u64 {
+pub fn _blsr_u64(x: u64) -> u64 {
     x & (x.wrapping_sub(1))
 }
 
@@ -99,7 +99,7 @@ pub unsafe fn _blsr_u64(x: u64) -> u64 {
 #[target_feature(enable = "bmi1")]
 #[cfg_attr(test, assert_instr(tzcnt))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub unsafe fn _tzcnt_u64(x: u64) -> u64 {
+pub fn _tzcnt_u64(x: u64) -> u64 {
     x.trailing_zeros() as u64
 }
 
@@ -112,7 +112,7 @@ pub unsafe fn _tzcnt_u64(x: u64) -> u64 {
 #[target_feature(enable = "bmi1")]
 #[cfg_attr(test, assert_instr(tzcnt))]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub unsafe fn _mm_tzcnt_64(x: u64) -> i64 {
+pub fn _mm_tzcnt_64(x: u64) -> i64 {
     x.trailing_zeros() as i64
 }