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Support crc32 even if on arm32 (#834)

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CRC32 is supported on A32 and T32.
This commit is contained in:
Makoto Kato 2020-03-31 00:38:23 +09:00 • committed by GitHub
parent b852344de5
commit d5d3117b9b
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GPG key ID: 4AEE18F83AFDEB23
3 changed files with 126 additions and 96 deletions
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96
library/stdarch/crates/core_arch/src/aarch64/crc.rs
View file

@ -1,19 +1,7 @@
extern "C" {
#[link_name = "llvm.aarch64.crc32b"]
fn crc32b_(crc: u32, data: u32) -> u32;
#[link_name = "llvm.aarch64.crc32h"]
fn crc32h_(crc: u32, data: u32) -> u32;
#[link_name = "llvm.aarch64.crc32w"]
fn crc32w_(crc: u32, data: u32) -> u32;
#[link_name = "llvm.aarch64.crc32x"]
fn crc32x_(crc: u32, data: u64) -> u32;
#[link_name = "llvm.aarch64.crc32cb"]
fn crc32cb_(crc: u32, data: u32) -> u32;
#[link_name = "llvm.aarch64.crc32ch"]
fn crc32ch_(crc: u32, data: u32) -> u32;
#[link_name = "llvm.aarch64.crc32cw"]
fn crc32cw_(crc: u32, data: u32) -> u32;
#[link_name = "llvm.aarch64.crc32cx"]
fn crc32cx_(crc: u32, data: u64) -> u32;
}
@ -21,30 +9,6 @@ extern "C" {
#[cfg(test)]
use stdarch_test::assert_instr;
/// CRC32 single round checksum for bytes (8 bits).
#[inline]
#[target_feature(enable = "crc")]
#[cfg_attr(test, assert_instr(crc32b))]
pub unsafe fn __crc32b(crc: u32, data: u8) -> u32 {
crc32b_(crc, data as u32)
}
/// CRC32 single round checksum for half words (16 bits).
#[inline]
#[target_feature(enable = "crc")]
#[cfg_attr(test, assert_instr(crc32h))]
pub unsafe fn __crc32h(crc: u32, data: u16) -> u32 {
crc32h_(crc, data as u32)
}
/// CRC32 single round checksum for words (32 bits).
#[inline]
#[target_feature(enable = "crc")]
#[cfg_attr(test, assert_instr(crc32w))]
pub unsafe fn __crc32w(crc: u32, data: u32) -> u32 {
crc32w_(crc, data)
}
/// CRC32 single round checksum for quad words (64 bits).
#[inline]
#[target_feature(enable = "crc")]
@ -53,30 +17,6 @@ pub unsafe fn __crc32d(crc: u32, data: u64) -> u32 {
crc32x_(crc, data)
}
/// CRC32-C single round checksum for bytes (8 bits).
#[inline]
#[target_feature(enable = "crc")]
#[cfg_attr(test, assert_instr(crc32cb))]
pub unsafe fn __crc32cb(crc: u32, data: u8) -> u32 {
crc32cb_(crc, data as u32)
}
/// CRC32-C single round checksum for half words (16 bits).
#[inline]
#[target_feature(enable = "crc")]
#[cfg_attr(test, assert_instr(crc32ch))]
pub unsafe fn __crc32ch(crc: u32, data: u16) -> u32 {
crc32ch_(crc, data as u32)
}
/// CRC32-C single round checksum for words (32 bits).
#[inline]
#[target_feature(enable = "crc")]
#[cfg_attr(test, assert_instr(crc32cw))]
pub unsafe fn __crc32cw(crc: u32, data: u32) -> u32 {
crc32cw_(crc, data)
}
/// CRC32-C single round checksum for quad words (64 bits).
#[inline]
#[target_feature(enable = "crc")]
@ -91,48 +31,12 @@ mod tests {
use std::mem;
use stdarch_test::simd_test;
#[simd_test(enable = "crc")]
unsafe fn test_crc32b() {
assert_eq!(__crc32b(0, 0), 0);
assert_eq!(__crc32b(0, 255), 755167117);
}
#[simd_test(enable = "crc")]
unsafe fn test_crc32h() {
assert_eq!(__crc32h(0, 0), 0);
assert_eq!(__crc32h(0, 16384), 1994146192);
}
#[simd_test(enable = "crc")]
unsafe fn test_crc32w() {
assert_eq!(__crc32w(0, 0), 0);
assert_eq!(__crc32w(0, 4294967295), 3736805603);
}
#[simd_test(enable = "crc")]
unsafe fn test_crc32d() {
assert_eq!(__crc32d(0, 0), 0);
assert_eq!(__crc32d(0, 18446744073709551615), 1147535477);
}
#[simd_test(enable = "crc")]
unsafe fn test_crc32cb() {
assert_eq!(__crc32cb(0, 0), 0);
assert_eq!(__crc32cb(0, 255), 2910671697);
}
#[simd_test(enable = "crc")]
unsafe fn test_crc32ch() {
assert_eq!(__crc32ch(0, 0), 0);
assert_eq!(__crc32ch(0, 16384), 1098587580);
}
#[simd_test(enable = "crc")]
unsafe fn test_crc32cw() {
assert_eq!(__crc32cw(0, 0), 0);
assert_eq!(__crc32cw(0, 4294967295), 3080238136);
}
#[simd_test(enable = "crc")]
unsafe fn test_crc32cd() {
assert_eq!(__crc32cd(0, 0), 0);

121
library/stdarch/crates/core_arch/src/arm/crc.rs Normal file
View file

@ -0,0 +1,121 @@
extern "C" {
#[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.crc32b")]
#[cfg_attr(target_arch = "arm", link_name = "llvm.arm.crc32b")]
fn crc32b_(crc: u32, data: u32) -> u32;
#[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.crc32h")]
#[cfg_attr(target_arch = "arm", link_name = "llvm.arm.crc32h")]
fn crc32h_(crc: u32, data: u32) -> u32;
#[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.crc32w")]
#[cfg_attr(target_arch = "arm", link_name = "llvm.arm.crc32w")]
fn crc32w_(crc: u32, data: u32) -> u32;
#[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.crc32cb")]
#[cfg_attr(target_arch = "arm", link_name = "llvm.arm.crc32cb")]
fn crc32cb_(crc: u32, data: u32) -> u32;
#[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.crc32ch")]
#[cfg_attr(target_arch = "arm", link_name = "llvm.arm.crc32ch")]
fn crc32ch_(crc: u32, data: u32) -> u32;
#[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.crc32cw")]
#[cfg_attr(target_arch = "arm", link_name = "llvm.arm.crc32cw")]
fn crc32cw_(crc: u32, data: u32) -> u32;
}
#[cfg(test)]
use stdarch_test::assert_instr;
/// CRC32 single round checksum for bytes (8 bits).
#[inline]
#[target_feature(enable = "crc")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(test, assert_instr(crc32b))]
pub unsafe fn __crc32b(crc: u32, data: u8) -> u32 {
crc32b_(crc, data as u32)
}
/// CRC32 single round checksum for half words (16 bits).
#[inline]
#[target_feature(enable = "crc")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(test, assert_instr(crc32h))]
pub unsafe fn __crc32h(crc: u32, data: u16) -> u32 {
crc32h_(crc, data as u32)
}
/// CRC32 single round checksum for words (32 bits).
#[inline]
#[target_feature(enable = "crc")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(test, assert_instr(crc32w))]
pub unsafe fn __crc32w(crc: u32, data: u32) -> u32 {
crc32w_(crc, data)
}
/// CRC32-C single round checksum for bytes (8 bits).
#[inline]
#[target_feature(enable = "crc")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(test, assert_instr(crc32cb))]
pub unsafe fn __crc32cb(crc: u32, data: u8) -> u32 {
crc32cb_(crc, data as u32)
}
/// CRC32-C single round checksum for half words (16 bits).
#[inline]
#[target_feature(enable = "crc")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(test, assert_instr(crc32ch))]
pub unsafe fn __crc32ch(crc: u32, data: u16) -> u32 {
crc32ch_(crc, data as u32)
}
/// CRC32-C single round checksum for words (32 bits).
#[inline]
#[target_feature(enable = "crc")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(test, assert_instr(crc32cw))]
pub unsafe fn __crc32cw(crc: u32, data: u32) -> u32 {
crc32cw_(crc, data)
}
#[cfg(test)]
mod tests {
use crate::core_arch::{arm::*, simd::*};
use std::mem;
use stdarch_test::simd_test;
#[simd_test(enable = "crc")]
unsafe fn test_crc32b() {
assert_eq!(__crc32b(0, 0), 0);
assert_eq!(__crc32b(0, 255), 755167117);
}
#[simd_test(enable = "crc")]
unsafe fn test_crc32h() {
assert_eq!(__crc32h(0, 0), 0);
assert_eq!(__crc32h(0, 16384), 1994146192);
}
#[simd_test(enable = "crc")]
unsafe fn test_crc32w() {
assert_eq!(__crc32w(0, 0), 0);
assert_eq!(__crc32w(0, 4294967295), 3736805603);
}
#[simd_test(enable = "crc")]
unsafe fn test_crc32cb() {
assert_eq!(__crc32cb(0, 0), 0);
assert_eq!(__crc32cb(0, 255), 2910671697);
}
#[simd_test(enable = "crc")]
unsafe fn test_crc32ch() {
assert_eq!(__crc32ch(0, 0), 0);
assert_eq!(__crc32ch(0, 16384), 1098587580);
}
#[simd_test(enable = "crc")]
unsafe fn test_crc32cw() {
assert_eq!(__crc32cw(0, 0), 0);
assert_eq!(__crc32cw(0, 4294967295), 3080238136);
}
}

5
library/stdarch/crates/core_arch/src/arm/mod.rs
View file

@ -34,6 +34,11 @@ mod neon;
))]
pub use self::neon::*;
#[cfg(any(target_arch = "aarch64", target_feature = "v7"))]
mod crc;
#[cfg(any(target_arch = "aarch64", target_feature = "v7"))]
pub use self::crc::*;
pub use crate::core_arch::acle::*;
#[cfg(test)]