From d94f7cf7d3f610351aa3a013687829f445f361b1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?R=C3=A9my=20Rakic?= Date: Thu, 4 Mar 2021 22:44:58 +0100 Subject: [PATCH] convert `_mm512_cmp_epi8_mask` to const generics --- .../crates/core_arch/src/x86/avx512bw.rs | 26 ++++++++----------- 1 file changed, 11 insertions(+), 15 deletions(-) diff --git a/library/stdarch/crates/core_arch/src/x86/avx512bw.rs b/library/stdarch/crates/core_arch/src/x86/avx512bw.rs index e2cfe4b0ac2a..59e63727118a 100644 --- a/library/stdarch/crates/core_arch/src/x86/avx512bw.rs +++ b/library/stdarch/crates/core_arch/src/x86/avx512bw.rs @@ -4005,22 +4005,18 @@ pub unsafe fn _mm_mask_cmp_epi16_mask( /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cmp_epi8_mask&expand=709) #[inline] #[target_feature(enable = "avx512bw")] -#[rustc_args_required_const(2)] -#[cfg_attr(test, assert_instr(vpcmp, imm8 = 0))] -pub unsafe fn _mm512_cmp_epi8_mask(a: __m512i, b: __m512i, imm8: i32) -> __mmask64 { +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(vpcmp, IMM8 = 0))] +pub unsafe fn _mm512_cmp_epi8_mask(a: __m512i, b: __m512i) -> __mmask64 { + static_assert_imm3!(IMM8); let a = a.as_i8x64(); let b = b.as_i8x64(); - macro_rules! call { - ($imm3:expr) => { - vpcmpb( - a, - b, - $imm3, - 0b11111111_11111111_11111111_11111111_11111111_11111111_11111111_11111111, - ) - }; - } - let r = constify_imm3!(imm8, call); + let r = vpcmpb( + a, + b, + IMM8, + 0b11111111_11111111_11111111_11111111_11111111_11111111_11111111_11111111, + ); transmute(r) } @@ -13544,7 +13540,7 @@ mod tests { unsafe fn test_mm512_cmp_epi8_mask() { let a = _mm512_set1_epi8(0); let b = _mm512_set1_epi8(1); - let m = _mm512_cmp_epi8_mask(a, b, _MM_CMPINT_LT); + let m = _mm512_cmp_epi8_mask::<_MM_CMPINT_LT>(a, b); assert_eq!( m, 0b11111111_11111111_11111111_11111111_11111111_11111111_11111111_11111111