user0/rust
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

Rollup merge of #152174 - folkertdev:stdarch-sync-2026-02-05, r=folkertdev

Browse source 
stdarch subtree update

Subtree update of `stdarch` to 1a7cc47efc.

Created using https://github.com/rust-lang/josh-sync.

r? @ghost
This commit is contained in:
许杰友 Jieyou Xu (Joe) 2026-02-06 10:25:42 +08:00 • committed by GitHub
commit de68f27bc1
No known key found for this signature in database
GPG key ID: B5690EEEBB952194
16 changed files with 874 additions and 1656 deletions
Download patch file Download diff file Expand all files Collapse all files

78
library/stdarch/crates/core_arch/src/aarch64/neon/generated.rs
View file

@ -4092,7 +4092,7 @@ pub fn vcmlaq_rot90_laneq_f32<const LANE: i32>(
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_f32)"]
#[inline(always)]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
#[rustc_legacy_const_generics(1, 3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcopy_lane_f32<const LANE1: i32, const LANE2: i32>(
@ -4113,7 +4113,7 @@ pub fn vcopy_lane_f32<const LANE1: i32, const LANE2: i32>(
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_s8)"]
#[inline(always)]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
#[rustc_legacy_const_generics(1, 3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcopy_lane_s8<const LANE1: i32, const LANE2: i32>(a: int8x8_t, b: int8x8_t) -> int8x8_t {
@ -4137,7 +4137,7 @@ pub fn vcopy_lane_s8<const LANE1: i32, const LANE2: i32>(a: int8x8_t, b: int8x8_
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_s16)"]
#[inline(always)]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
#[rustc_legacy_const_generics(1, 3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcopy_lane_s16<const LANE1: i32, const LANE2: i32>(a: int16x4_t, b: int16x4_t) -> int16x4_t {
@ -4157,7 +4157,7 @@ pub fn vcopy_lane_s16<const LANE1: i32, const LANE2: i32>(a: int16x4_t, b: int16
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_s32)"]
#[inline(always)]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
#[rustc_legacy_const_generics(1, 3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcopy_lane_s32<const LANE1: i32, const LANE2: i32>(a: int32x2_t, b: int32x2_t) -> int32x2_t {
@ -4175,7 +4175,7 @@ pub fn vcopy_lane_s32<const LANE1: i32, const LANE2: i32>(a: int32x2_t, b: int32
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_u8)"]
#[inline(always)]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
#[rustc_legacy_const_generics(1, 3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcopy_lane_u8<const LANE1: i32, const LANE2: i32>(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
@ -4199,7 +4199,7 @@ pub fn vcopy_lane_u8<const LANE1: i32, const LANE2: i32>(a: uint8x8_t, b: uint8x
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_u16)"]
#[inline(always)]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
#[rustc_legacy_const_generics(1, 3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcopy_lane_u16<const LANE1: i32, const LANE2: i32>(
@ -4222,7 +4222,7 @@ pub fn vcopy_lane_u16<const LANE1: i32, const LANE2: i32>(
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_u32)"]
#[inline(always)]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
#[rustc_legacy_const_generics(1, 3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcopy_lane_u32<const LANE1: i32, const LANE2: i32>(
@ -4243,7 +4243,7 @@ pub fn vcopy_lane_u32<const LANE1: i32, const LANE2: i32>(
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_p8)"]
#[inline(always)]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
#[rustc_legacy_const_generics(1, 3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcopy_lane_p8<const LANE1: i32, const LANE2: i32>(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
@ -4267,7 +4267,7 @@ pub fn vcopy_lane_p8<const LANE1: i32, const LANE2: i32>(a: poly8x8_t, b: poly8x
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_p16)"]
#[inline(always)]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
#[rustc_legacy_const_generics(1, 3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcopy_lane_p16<const LANE1: i32, const LANE2: i32>(
@ -4290,7 +4290,7 @@ pub fn vcopy_lane_p16<const LANE1: i32, const LANE2: i32>(
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_f32)"]
#[inline(always)]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
#[rustc_legacy_const_generics(1, 3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcopy_laneq_f32<const LANE1: i32, const LANE2: i32>(
@ -4312,7 +4312,7 @@ pub fn vcopy_laneq_f32<const LANE1: i32, const LANE2: i32>(
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_s8)"]
#[inline(always)]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
#[rustc_legacy_const_generics(1, 3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcopy_laneq_s8<const LANE1: i32, const LANE2: i32>(a: int8x8_t, b: int8x16_t) -> int8x8_t {
@ -4338,7 +4338,7 @@ pub fn vcopy_laneq_s8<const LANE1: i32, const LANE2: i32>(a: int8x8_t, b: int8x1
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_s16)"]
#[inline(always)]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
#[rustc_legacy_const_generics(1, 3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcopy_laneq_s16<const LANE1: i32, const LANE2: i32>(
@ -4362,7 +4362,7 @@ pub fn vcopy_laneq_s16<const LANE1: i32, const LANE2: i32>(
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_s32)"]
#[inline(always)]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
#[rustc_legacy_const_generics(1, 3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcopy_laneq_s32<const LANE1: i32, const LANE2: i32>(
@ -4384,7 +4384,7 @@ pub fn vcopy_laneq_s32<const LANE1: i32, const LANE2: i32>(
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_u8)"]
#[inline(always)]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
#[rustc_legacy_const_generics(1, 3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcopy_laneq_u8<const LANE1: i32, const LANE2: i32>(
@ -4413,7 +4413,7 @@ pub fn vcopy_laneq_u8<const LANE1: i32, const LANE2: i32>(
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_u16)"]
#[inline(always)]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
#[rustc_legacy_const_generics(1, 3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcopy_laneq_u16<const LANE1: i32, const LANE2: i32>(
@ -4437,7 +4437,7 @@ pub fn vcopy_laneq_u16<const LANE1: i32, const LANE2: i32>(
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_u32)"]
#[inline(always)]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
#[rustc_legacy_const_generics(1, 3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcopy_laneq_u32<const LANE1: i32, const LANE2: i32>(
@ -4459,7 +4459,7 @@ pub fn vcopy_laneq_u32<const LANE1: i32, const LANE2: i32>(
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_p8)"]
#[inline(always)]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
#[rustc_legacy_const_generics(1, 3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcopy_laneq_p8<const LANE1: i32, const LANE2: i32>(
@ -4488,7 +4488,7 @@ pub fn vcopy_laneq_p8<const LANE1: i32, const LANE2: i32>(
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_p16)"]
#[inline(always)]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
#[rustc_legacy_const_generics(1, 3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcopy_laneq_p16<const LANE1: i32, const LANE2: i32>(
@ -4624,7 +4624,7 @@ pub fn vcopyq_lane_p64<const LANE1: i32, const LANE2: i32>(
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_s8)"]
#[inline(always)]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
#[rustc_legacy_const_generics(1, 3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcopyq_lane_s8<const LANE1: i32, const LANE2: i32>(a: int8x16_t, b: int8x8_t) -> int8x16_t {
@ -4994,7 +4994,7 @@ pub fn vcopyq_lane_s8<const LANE1: i32, const LANE2: i32>(a: int8x16_t, b: int8x
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_s16)"]
#[inline(always)]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
#[rustc_legacy_const_generics(1, 3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcopyq_lane_s16<const LANE1: i32, const LANE2: i32>(
@ -5022,7 +5022,7 @@ pub fn vcopyq_lane_s16<const LANE1: i32, const LANE2: i32>(
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_s32)"]
#[inline(always)]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
#[rustc_legacy_const_generics(1, 3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcopyq_lane_s32<const LANE1: i32, const LANE2: i32>(
@ -5046,7 +5046,7 @@ pub fn vcopyq_lane_s32<const LANE1: i32, const LANE2: i32>(
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_u8)"]
#[inline(always)]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
#[rustc_legacy_const_generics(1, 3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcopyq_lane_u8<const LANE1: i32, const LANE2: i32>(
@ -5419,7 +5419,7 @@ pub fn vcopyq_lane_u8<const LANE1: i32, const LANE2: i32>(
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_u16)"]
#[inline(always)]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
#[rustc_legacy_const_generics(1, 3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcopyq_lane_u16<const LANE1: i32, const LANE2: i32>(
@ -5447,7 +5447,7 @@ pub fn vcopyq_lane_u16<const LANE1: i32, const LANE2: i32>(
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_u32)"]
#[inline(always)]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
#[rustc_legacy_const_generics(1, 3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcopyq_lane_u32<const LANE1: i32, const LANE2: i32>(
@ -5471,7 +5471,7 @@ pub fn vcopyq_lane_u32<const LANE1: i32, const LANE2: i32>(
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_p8)"]
#[inline(always)]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
#[rustc_legacy_const_generics(1, 3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcopyq_lane_p8<const LANE1: i32, const LANE2: i32>(
@ -5844,7 +5844,7 @@ pub fn vcopyq_lane_p8<const LANE1: i32, const LANE2: i32>(
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_p16)"]
#[inline(always)]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
#[rustc_legacy_const_generics(1, 3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcopyq_lane_p16<const LANE1: i32, const LANE2: i32>(
@ -5872,7 +5872,7 @@ pub fn vcopyq_lane_p16<const LANE1: i32, const LANE2: i32>(
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_f32)"]
#[inline(always)]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
#[rustc_legacy_const_generics(1, 3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcopyq_laneq_f32<const LANE1: i32, const LANE2: i32>(
@ -5895,7 +5895,7 @@ pub fn vcopyq_laneq_f32<const LANE1: i32, const LANE2: i32>(
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_f64)"]
#[inline(always)]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
#[rustc_legacy_const_generics(1, 3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcopyq_laneq_f64<const LANE1: i32, const LANE2: i32>(
@ -5916,7 +5916,7 @@ pub fn vcopyq_laneq_f64<const LANE1: i32, const LANE2: i32>(
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_s8)"]
#[inline(always)]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
#[rustc_legacy_const_generics(1, 3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcopyq_laneq_s8<const LANE1: i32, const LANE2: i32>(
@ -6287,7 +6287,7 @@ pub fn vcopyq_laneq_s8<const LANE1: i32, const LANE2: i32>(
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_s16)"]
#[inline(always)]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
#[rustc_legacy_const_generics(1, 3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcopyq_laneq_s16<const LANE1: i32, const LANE2: i32>(
@ -6314,7 +6314,7 @@ pub fn vcopyq_laneq_s16<const LANE1: i32, const LANE2: i32>(
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_s32)"]
#[inline(always)]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
#[rustc_legacy_const_generics(1, 3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcopyq_laneq_s32<const LANE1: i32, const LANE2: i32>(
@ -6337,7 +6337,7 @@ pub fn vcopyq_laneq_s32<const LANE1: i32, const LANE2: i32>(
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_s64)"]
#[inline(always)]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
#[rustc_legacy_const_generics(1, 3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcopyq_laneq_s64<const LANE1: i32, const LANE2: i32>(
@ -6358,7 +6358,7 @@ pub fn vcopyq_laneq_s64<const LANE1: i32, const LANE2: i32>(
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_u8)"]
#[inline(always)]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
#[rustc_legacy_const_generics(1, 3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcopyq_laneq_u8<const LANE1: i32, const LANE2: i32>(
@ -6729,7 +6729,7 @@ pub fn vcopyq_laneq_u8<const LANE1: i32, const LANE2: i32>(
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_u16)"]
#[inline(always)]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
#[rustc_legacy_const_generics(1, 3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcopyq_laneq_u16<const LANE1: i32, const LANE2: i32>(
@ -6756,7 +6756,7 @@ pub fn vcopyq_laneq_u16<const LANE1: i32, const LANE2: i32>(
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_u32)"]
#[inline(always)]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
#[rustc_legacy_const_generics(1, 3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcopyq_laneq_u32<const LANE1: i32, const LANE2: i32>(
@ -6779,7 +6779,7 @@ pub fn vcopyq_laneq_u32<const LANE1: i32, const LANE2: i32>(
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_u64)"]
#[inline(always)]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
#[rustc_legacy_const_generics(1, 3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcopyq_laneq_u64<const LANE1: i32, const LANE2: i32>(
@ -6800,7 +6800,7 @@ pub fn vcopyq_laneq_u64<const LANE1: i32, const LANE2: i32>(
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_p8)"]
#[inline(always)]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
#[rustc_legacy_const_generics(1, 3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcopyq_laneq_p8<const LANE1: i32, const LANE2: i32>(
@ -7171,7 +7171,7 @@ pub fn vcopyq_laneq_p8<const LANE1: i32, const LANE2: i32>(
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_p16)"]
#[inline(always)]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
#[rustc_legacy_const_generics(1, 3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcopyq_laneq_p16<const LANE1: i32, const LANE2: i32>(
@ -7198,7 +7198,7 @@ pub fn vcopyq_laneq_p16<const LANE1: i32, const LANE2: i32>(
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_p64)"]
#[inline(always)]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
#[rustc_legacy_const_generics(1, 3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcopyq_laneq_p64<const LANE1: i32, const LANE2: i32>(

420
library/stdarch/crates/core_arch/src/aarch64/neon/mod.rs
View file

@ -569,47 +569,46 @@ mod tests {
use crate::core_arch::aarch64::test_support::*;
use crate::core_arch::arm_shared::test_support::*;
use crate::core_arch::{aarch64::neon::*, aarch64::*, simd::*};
use std::mem::transmute;
use stdarch_test::simd_test;
#[simd_test(enable = "neon")]
unsafe fn test_vadd_f64() {
let a = 1.;
let b = 8.;
let e = 9.;
let r: f64 = transmute(vadd_f64(transmute(a), transmute(b)));
fn test_vadd_f64() {
let a = f64x1::from_array([1.]);
let b = f64x1::from_array([8.]);
let e = f64x1::from_array([9.]);
let r = f64x1::from(vadd_f64(a.into(), b.into()));
assert_eq!(r, e);
}
#[simd_test(enable = "neon")]
unsafe fn test_vaddq_f64() {
fn test_vaddq_f64() {
let a = f64x2::new(1., 2.);
let b = f64x2::new(8., 7.);
let e = f64x2::new(9., 9.);
let r: f64x2 = transmute(vaddq_f64(transmute(a), transmute(b)));
let r = f64x2::from(vaddq_f64(a.into(), b.into()));
assert_eq!(r, e);
}
#[simd_test(enable = "neon")]
unsafe fn test_vadd_s64() {
let a = 1_i64;
let b = 8_i64;
let e = 9_i64;
let r: i64 = transmute(vadd_s64(transmute(a), transmute(b)));
fn test_vadd_s64() {
let a = i64x1::from_array([1]);
let b = i64x1::from_array([8]);
let e = i64x1::from_array([9]);
let r = i64x1::from(vadd_s64(a.into(), b.into()));
assert_eq!(r, e);
}
#[simd_test(enable = "neon")]
unsafe fn test_vadd_u64() {
let a = 1_u64;
let b = 8_u64;
let e = 9_u64;
let r: u64 = transmute(vadd_u64(transmute(a), transmute(b)));
fn test_vadd_u64() {
let a = u64x1::from_array([1]);
let b = u64x1::from_array([8]);
let e = u64x1::from_array([9]);
let r = u64x1::from(vadd_u64(a.into(), b.into()));
assert_eq!(r, e);
}
#[simd_test(enable = "neon")]
unsafe fn test_vaddd_s64() {
fn test_vaddd_s64() {
let a = 1_i64;
let b = 8_i64;
let e = 9_i64;
@ -618,7 +617,7 @@ mod tests {
}
#[simd_test(enable = "neon")]
unsafe fn test_vaddd_u64() {
fn test_vaddd_u64() {
let a = 1_u64;
let b = 8_u64;
let e = 9_u64;
@ -627,25 +626,25 @@ mod tests {
}
#[simd_test(enable = "neon")]
unsafe fn test_vext_p64() {
let a: i64x1 = i64x1::new(0);
let b: i64x1 = i64x1::new(1);
let e: i64x1 = i64x1::new(0);
let r: i64x1 = transmute(vext_p64::<0>(transmute(a), transmute(b)));
fn test_vext_p64() {
let a = u64x1::new(0);
let b = u64x1::new(1);
let e = u64x1::new(0);
let r = u64x1::from(vext_p64::<0>(a.into(), b.into()));
assert_eq!(r, e);
}
#[simd_test(enable = "neon")]
unsafe fn test_vext_f64() {
let a: f64x1 = f64x1::new(0.);
let b: f64x1 = f64x1::new(1.);
let e: f64x1 = f64x1::new(0.);
let r: f64x1 = transmute(vext_f64::<0>(transmute(a), transmute(b)));
fn test_vext_f64() {
let a = f64x1::new(0.);
let b = f64x1::new(1.);
let e = f64x1::new(0.);
let r = f64x1::from(vext_f64::<0>(a.into(), b.into()));
assert_eq!(r, e);
}
#[simd_test(enable = "neon")]
unsafe fn test_vshld_n_s64() {
fn test_vshld_n_s64() {
let a: i64 = 1;
let e: i64 = 4;
let r: i64 = vshld_n_s64::<2>(a);
@ -653,7 +652,7 @@ mod tests {
}
#[simd_test(enable = "neon")]
unsafe fn test_vshld_n_u64() {
fn test_vshld_n_u64() {
let a: u64 = 1;
let e: u64 = 4;
let r: u64 = vshld_n_u64::<2>(a);
@ -661,7 +660,7 @@ mod tests {
}
#[simd_test(enable = "neon")]
unsafe fn test_vshrd_n_s64() {
fn test_vshrd_n_s64() {
let a: i64 = 4;
let e: i64 = 1;
let r: i64 = vshrd_n_s64::<2>(a);
@ -669,7 +668,7 @@ mod tests {
}
#[simd_test(enable = "neon")]
unsafe fn test_vshrd_n_u64() {
fn test_vshrd_n_u64() {
let a: u64 = 4;
let e: u64 = 1;
let r: u64 = vshrd_n_u64::<2>(a);
@ -677,7 +676,7 @@ mod tests {
}
#[simd_test(enable = "neon")]
unsafe fn test_vsrad_n_s64() {
fn test_vsrad_n_s64() {
let a: i64 = 1;
let b: i64 = 4;
let e: i64 = 2;
@ -686,7 +685,7 @@ mod tests {
}
#[simd_test(enable = "neon")]
unsafe fn test_vsrad_n_u64() {
fn test_vsrad_n_u64() {
let a: u64 = 1;
let b: u64 = 4;
let e: u64 = 2;
@ -695,298 +694,461 @@ mod tests {
}
#[simd_test(enable = "neon")]
unsafe fn test_vdup_n_f64() {
fn test_vdup_n_f64() {
let a: f64 = 3.3;
let e = f64x1::new(3.3);
let r: f64x1 = transmute(vdup_n_f64(a));
let r = f64x1::from(vdup_n_f64(a));
assert_eq!(r, e);
}
#[simd_test(enable = "neon")]
unsafe fn test_vdup_n_p64() {
fn test_vdup_n_p64() {
let a: u64 = 3;
let e = u64x1::new(3);
let r: u64x1 = transmute(vdup_n_p64(a));
let r = u64x1::from(vdup_n_p64(a));
assert_eq!(r, e);
}
#[simd_test(enable = "neon")]
unsafe fn test_vdupq_n_f64() {
fn test_vdupq_n_f64() {
let a: f64 = 3.3;
let e = f64x2::new(3.3, 3.3);
let r: f64x2 = transmute(vdupq_n_f64(a));
let r = f64x2::from(vdupq_n_f64(a));
assert_eq!(r, e);
}
#[simd_test(enable = "neon")]
unsafe fn test_vdupq_n_p64() {
fn test_vdupq_n_p64() {
let a: u64 = 3;
let e = u64x2::new(3, 3);
let r: u64x2 = transmute(vdupq_n_p64(a));
let r = u64x2::from(vdupq_n_p64(a));
assert_eq!(r, e);
}
#[simd_test(enable = "neon")]
unsafe fn test_vmov_n_p64() {
fn test_vmov_n_p64() {
let a: u64 = 3;
let e = u64x1::new(3);
let r: u64x1 = transmute(vmov_n_p64(a));
let r = u64x1::from(vmov_n_p64(a));
assert_eq!(r, e);
}
#[simd_test(enable = "neon")]
unsafe fn test_vmov_n_f64() {
fn test_vmov_n_f64() {
let a: f64 = 3.3;
let e = f64x1::new(3.3);
let r: f64x1 = transmute(vmov_n_f64(a));
let r = f64x1::from(vmov_n_f64(a));
assert_eq!(r, e);
}
#[simd_test(enable = "neon")]
unsafe fn test_vmovq_n_p64() {
fn test_vmovq_n_p64() {
let a: u64 = 3;
let e = u64x2::new(3, 3);
let r: u64x2 = transmute(vmovq_n_p64(a));
let r = u64x2::from(vmovq_n_p64(a));
assert_eq!(r, e);
}
#[simd_test(enable = "neon")]
unsafe fn test_vmovq_n_f64() {
fn test_vmovq_n_f64() {
let a: f64 = 3.3;
let e = f64x2::new(3.3, 3.3);
let r: f64x2 = transmute(vmovq_n_f64(a));
let r = f64x2::from(vmovq_n_f64(a));
assert_eq!(r, e);
}
#[simd_test(enable = "neon")]
unsafe fn test_vget_high_f64() {
fn test_vget_high_f64() {
let a = f64x2::new(1.0, 2.0);
let e = f64x1::new(2.0);
let r: f64x1 = transmute(vget_high_f64(transmute(a)));
let r = f64x1::from(vget_high_f64(a.into()));
assert_eq!(r, e);
}
#[simd_test(enable = "neon")]
unsafe fn test_vget_high_p64() {
fn test_vget_high_p64() {
let a = u64x2::new(1, 2);
let e = u64x1::new(2);
let r: u64x1 = transmute(vget_high_p64(transmute(a)));
let r = u64x1::from(vget_high_p64(a.into()));
assert_eq!(r, e);
}
#[simd_test(enable = "neon")]
unsafe fn test_vget_low_f64() {
fn test_vget_low_f64() {
let a = f64x2::new(1.0, 2.0);
let e = f64x1::new(1.0);
let r: f64x1 = transmute(vget_low_f64(transmute(a)));
let r = f64x1::from(vget_low_f64(a.into()));
assert_eq!(r, e);
}
#[simd_test(enable = "neon")]
unsafe fn test_vget_low_p64() {
fn test_vget_low_p64() {
let a = u64x2::new(1, 2);
let e = u64x1::new(1);
let r: u64x1 = transmute(vget_low_p64(transmute(a)));
let r = u64x1::from(vget_low_p64(a.into()));
assert_eq!(r, e);
}
#[simd_test(enable = "neon")]
unsafe fn test_vget_lane_f64() {
fn test_vget_lane_f64() {
let v = f64x1::new(1.0);
let r = vget_lane_f64::<0>(transmute(v));
let r = vget_lane_f64::<0>(v.into());
assert_eq!(r, 1.0);
}
#[simd_test(enable = "neon")]
unsafe fn test_vgetq_lane_f64() {
fn test_vgetq_lane_f64() {
let v = f64x2::new(0.0, 1.0);
let r = vgetq_lane_f64::<1>(transmute(v));
let r = vgetq_lane_f64::<1>(v.into());
assert_eq!(r, 1.0);
let r = vgetq_lane_f64::<0>(transmute(v));
let r = vgetq_lane_f64::<0>(v.into());
assert_eq!(r, 0.0);
}
#[simd_test(enable = "neon")]
unsafe fn test_vcopy_lane_s64() {
let a: i64x1 = i64x1::new(1);
let b: i64x1 = i64x1::new(0x7F_FF_FF_FF_FF_FF_FF_FF);
let e: i64x1 = i64x1::new(0x7F_FF_FF_FF_FF_FF_FF_FF);
let r: i64x1 = transmute(vcopy_lane_s64::<0, 0>(transmute(a), transmute(b)));
fn test_vcopy_lane_s64() {
let a = i64x1::new(1);
let b = i64x1::new(0x7F_FF_FF_FF_FF_FF_FF_FF);
let e = i64x1::new(0x7F_FF_FF_FF_FF_FF_FF_FF);
let r = i64x1::from(vcopy_lane_s64::<0, 0>(a.into(), b.into()));
assert_eq!(r, e);
}
#[simd_test(enable = "neon")]
unsafe fn test_vcopy_lane_u64() {
let a: u64x1 = u64x1::new(1);
let b: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF);
let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF);
let r: u64x1 = transmute(vcopy_lane_u64::<0, 0>(transmute(a), transmute(b)));
fn test_vcopy_lane_u64() {
let a = u64x1::new(1);
let b = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF);
let e = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF);
let r = u64x1::from(vcopy_lane_u64::<0, 0>(a.into(), b.into()));
assert_eq!(r, e);
}
#[simd_test(enable = "neon")]
unsafe fn test_vcopy_lane_p64() {
let a: i64x1 = i64x1::new(1);
let b: i64x1 = i64x1::new(0x7F_FF_FF_FF_FF_FF_FF_FF);
let e: i64x1 = i64x1::new(0x7F_FF_FF_FF_FF_FF_FF_FF);
let r: i64x1 = transmute(vcopy_lane_p64::<0, 0>(transmute(a), transmute(b)));
fn test_vcopy_lane_p64() {
let a = u64x1::new(1);
let b = u64x1::new(0x7F_FF_FF_FF_FF_FF_FF_FF);
let e = u64x1::new(0x7F_FF_FF_FF_FF_FF_FF_FF);
let r = u64x1::from(vcopy_lane_p64::<0, 0>(a.into(), b.into()));
assert_eq!(r, e);
}
#[simd_test(enable = "neon")]
unsafe fn test_vcopy_lane_f64() {
let a: f64 = 1.;
let b: f64 = 0.;
let e: f64 = 0.;
let r: f64 = transmute(vcopy_lane_f64::<0, 0>(transmute(a), transmute(b)));
fn test_vcopy_lane_f64() {
let a = f64x1::from_array([1.]);
let b = f64x1::from_array([0.]);
let e = f64x1::from_array([0.]);
let r = f64x1::from(vcopy_lane_f64::<0, 0>(a.into(), b.into()));
assert_eq!(r, e);
}
#[simd_test(enable = "neon")]
unsafe fn test_vcopy_laneq_s64() {
let a: i64x1 = i64x1::new(1);
let b: i64x2 = i64x2::new(0, 0x7F_FF_FF_FF_FF_FF_FF_FF);
let e: i64x1 = i64x1::new(0x7F_FF_FF_FF_FF_FF_FF_FF);
let r: i64x1 = transmute(vcopy_laneq_s64::<0, 1>(transmute(a), transmute(b)));
fn test_vcopy_laneq_s64() {
let a = i64x1::new(1);
let b = i64x2::new(0, 0x7F_FF_FF_FF_FF_FF_FF_FF);
let e = i64x1::new(0x7F_FF_FF_FF_FF_FF_FF_FF);
let r = i64x1::from(vcopy_laneq_s64::<0, 1>(a.into(), b.into()));
assert_eq!(r, e);
}
#[simd_test(enable = "neon")]
unsafe fn test_vcopy_laneq_u64() {
let a: u64x1 = u64x1::new(1);
let b: u64x2 = u64x2::new(0, 0xFF_FF_FF_FF_FF_FF_FF_FF);
let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF);
let r: u64x1 = transmute(vcopy_laneq_u64::<0, 1>(transmute(a), transmute(b)));
fn test_vcopy_laneq_u64() {
let a = u64x1::new(1);
let b = u64x2::new(0, 0xFF_FF_FF_FF_FF_FF_FF_FF);
let e = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF);
let r = u64x1::from(vcopy_laneq_u64::<0, 1>(a.into(), b.into()));
assert_eq!(r, e);
}
#[simd_test(enable = "neon")]
unsafe fn test_vcopy_laneq_p64() {
let a: i64x1 = i64x1::new(1);
let b: i64x2 = i64x2::new(0, 0x7F_FF_FF_FF_FF_FF_FF_FF);
let e: i64x1 = i64x1::new(0x7F_FF_FF_FF_FF_FF_FF_FF);
let r: i64x1 = transmute(vcopy_laneq_p64::<0, 1>(transmute(a), transmute(b)));
fn test_vcopy_laneq_p64() {
let a = u64x1::new(1);
let b = u64x2::new(0, 0x7F_FF_FF_FF_FF_FF_FF_FF);
let e = u64x1::new(0x7F_FF_FF_FF_FF_FF_FF_FF);
let r = u64x1::from(vcopy_laneq_p64::<0, 1>(a.into(), b.into()));
assert_eq!(r, e);
}
#[simd_test(enable = "neon")]
unsafe fn test_vcopy_laneq_f64() {
let a: f64 = 1.;
let b: f64x2 = f64x2::new(0., 0.5);
let e: f64 = 0.5;
let r: f64 = transmute(vcopy_laneq_f64::<0, 1>(transmute(a), transmute(b)));
fn test_vcopy_laneq_f64() {
let a = f64x1::from_array([1.]);
let b = f64x2::from_array([0., 0.5]);
let e = f64x1::from_array([0.5]);
let r = f64x1::from(vcopy_laneq_f64::<0, 1>(a.into(), b.into()));
assert_eq!(r, e);
}
#[simd_test(enable = "neon")]
unsafe fn test_vbsl_f64() {
fn test_vbsl_f64() {
let a = u64x1::new(0x8000000000000000);
let b = f64x1::new(-1.23f64);
let c = f64x1::new(2.34f64);
let e = f64x1::new(-2.34f64);
let r: f64x1 = transmute(vbsl_f64(transmute(a), transmute(b), transmute(c)));
let r = f64x1::from(vbsl_f64(a.into(), b.into(), c.into()));
assert_eq!(r, e);
}
#[simd_test(enable = "neon")]
unsafe fn test_vbsl_p64() {
fn test_vbsl_p64() {
let a = u64x1::new(1);
let b = u64x1::new(u64::MAX);
let c = u64x1::new(u64::MIN);
let e = u64x1::new(1);
let r: u64x1 = transmute(vbsl_p64(transmute(a), transmute(b), transmute(c)));
let r = u64x1::from(vbsl_p64(a.into(), b.into(), c.into()));
assert_eq!(r, e);
}
#[simd_test(enable = "neon")]
unsafe fn test_vbslq_f64() {
fn test_vbslq_f64() {
let a = u64x2::new(1, 0x8000000000000000);
let b = f64x2::new(f64::MAX, -1.23f64);
let c = f64x2::new(f64::MIN, 2.34f64);
let e = f64x2::new(f64::MIN, -2.34f64);
let r: f64x2 = transmute(vbslq_f64(transmute(a), transmute(b), transmute(c)));
let r = f64x2::from(vbslq_f64(a.into(), b.into(), c.into()));
assert_eq!(r, e);
}
#[simd_test(enable = "neon")]
unsafe fn test_vbslq_p64() {
fn test_vbslq_p64() {
let a = u64x2::new(u64::MAX, 1);
let b = u64x2::new(u64::MAX, u64::MAX);
let c = u64x2::new(u64::MIN, u64::MIN);
let e = u64x2::new(u64::MAX, 1);
let r: u64x2 = transmute(vbslq_p64(transmute(a), transmute(b), transmute(c)));
let r = u64x2::from(vbslq_p64(a.into(), b.into(), c.into()));
assert_eq!(r, e);
}
#[simd_test(enable = "neon")]
unsafe fn test_vld1_f64() {
fn test_vld1_f64() {
let a: [f64; 2] = [0., 1.];
let e = f64x1::new(1.);
let r: f64x1 = transmute(vld1_f64(a[1..].as_ptr()));
let r = unsafe { f64x1::from(vld1_f64(a[1..].as_ptr())) };
assert_eq!(r, e)
}
#[simd_test(enable = "neon")]
unsafe fn test_vld1q_f64() {
fn test_vld1q_f64() {
let a: [f64; 3] = [0., 1., 2.];
let e = f64x2::new(1., 2.);
let r: f64x2 = transmute(vld1q_f64(a[1..].as_ptr()));
let r = unsafe { f64x2::from(vld1q_f64(a[1..].as_ptr())) };
assert_eq!(r, e)
}
#[simd_test(enable = "neon")]
unsafe fn test_vld1_dup_f64() {
fn test_vld1_dup_f64() {
let a: [f64; 2] = [1., 42.];
let e = f64x1::new(42.);
let r: f64x1 = transmute(vld1_dup_f64(a[1..].as_ptr()));
let r = unsafe { f64x1::from(vld1_dup_f64(a[1..].as_ptr())) };
assert_eq!(r, e)
}
#[simd_test(enable = "neon")]
unsafe fn test_vld1q_dup_f64() {
fn test_vld1q_dup_f64() {
let elem: f64 = 42.;
let e = f64x2::new(42., 42.);
let r: f64x2 = transmute(vld1q_dup_f64(&elem));
let r = unsafe { f64x2::from(vld1q_dup_f64(&elem)) };
assert_eq!(r, e)
}
#[simd_test(enable = "neon")]
unsafe fn test_vld1_lane_f64() {
fn test_vld1_lane_f64() {
let a = f64x1::new(0.);
let elem: f64 = 42.;
let e = f64x1::new(42.);
let r: f64x1 = transmute(vld1_lane_f64::<0>(&elem, transmute(a)));
let r = unsafe { f64x1::from(vld1_lane_f64::<0>(&elem, a.into())) };
assert_eq!(r, e)
}
#[simd_test(enable = "neon")]
unsafe fn test_vld1q_lane_f64() {
fn test_vld1q_lane_f64() {
let a = f64x2::new(0., 1.);
let elem: f64 = 42.;
let e = f64x2::new(0., 42.);
let r: f64x2 = transmute(vld1q_lane_f64::<1>(&elem, transmute(a)));
let r = unsafe { f64x2::from(vld1q_lane_f64::<1>(&elem, a.into())) };
assert_eq!(r, e)
}
#[simd_test(enable = "neon")]
unsafe fn test_vst1_f64() {
fn test_vst1_f64() {
let mut vals = [0_f64; 2];
let a = f64x1::new(1.);
vst1_f64(vals[1..].as_mut_ptr(), transmute(a));
unsafe {
vst1_f64(vals[1..].as_mut_ptr(), a.into());
}
assert_eq!(vals[0], 0.);
assert_eq!(vals[1], 1.);
}
#[simd_test(enable = "neon")]
unsafe fn test_vst1q_f64() {
fn test_vst1q_f64() {
let mut vals = [0_f64; 3];
let a = f64x2::new(1., 2.);
vst1q_f64(vals[1..].as_mut_ptr(), transmute(a));
unsafe {
vst1q_f64(vals[1..].as_mut_ptr(), a.into());
}
assert_eq!(vals[0], 0.);
assert_eq!(vals[1], 1.);
assert_eq!(vals[2], 2.);
}
macro_rules! wide_store_load_roundtrip {
($elem_ty:ty, $len:expr, $vec_ty:ty, $store:expr, $load:expr) => {
let vals: [$elem_ty; $len] = crate::array::from_fn(|i| i as $elem_ty);
let a: $vec_ty = transmute(vals);
let mut tmp = [0 as $elem_ty; $len];
$store(tmp.as_mut_ptr().cast(), a);
let r: $vec_ty = $load(tmp.as_ptr().cast());
let out: [$elem_ty; $len] = transmute(r);
assert_eq!(out, vals);
};
}
macro_rules! wide_store_load_roundtrip_fp16 {
($( $name:ident $args:tt);* $(;)?) => {
$(
#[simd_test(enable = "neon,fp16")]
#[cfg(not(target_arch = "arm64ec"))]
unsafe fn $name() {
wide_store_load_roundtrip! $args;
}
)*
};
}
wide_store_load_roundtrip_fp16! {
test_vld1_f16_x2(f16, 8, float16x4x2_t, vst1_f16_x2, vld1_f16_x2);
test_vld1_f16_x3(f16, 12, float16x4x3_t, vst1_f16_x3, vld1_f16_x3);
test_vld1_f16_x4(f16, 16, float16x4x4_t, vst1_f16_x4, vld1_f16_x4);
test_vld1q_f16_x2(f16, 16, float16x8x2_t, vst1q_f16_x2, vld1q_f16_x2);
test_vld1q_f16_x3(f16, 24, float16x8x3_t, vst1q_f16_x3, vld1q_f16_x3);
test_vld1q_f16_x4(f16, 32, float16x8x4_t, vst1q_f16_x4, vld1q_f16_x4);
}
macro_rules! wide_store_load_roundtrip_aes {
($( $name:ident $args:tt);* $(;)?) => {
$(
#[simd_test(enable = "neon,aes")]
unsafe fn $name() {
wide_store_load_roundtrip! $args;
}
)*
};
}
wide_store_load_roundtrip_aes! {
test_vld1_p64_x2(p64, 2, poly64x1x2_t, vst1_p64_x2, vld1_p64_x2);
test_vld1_p64_x3(p64, 3, poly64x1x3_t, vst1_p64_x3, vld1_p64_x3);
test_vld1_p64_x4(p64, 4, poly64x1x4_t, vst1_p64_x4, vld1_p64_x4);
test_vld1q_p64_x2(p64, 4, poly64x2x2_t, vst1q_p64_x2, vld1q_p64_x2);
test_vld1q_p64_x3(p64, 6, poly64x2x3_t, vst1q_p64_x3, vld1q_p64_x3);
test_vld1q_p64_x4(p64, 8, poly64x2x4_t, vst1q_p64_x4, vld1q_p64_x4);
}
macro_rules! wide_store_load_roundtrip_neon {
($( $name:ident $args:tt);* $(;)?) => {
$(
#[simd_test(enable = "neon")]
unsafe fn $name() {
wide_store_load_roundtrip! $args;
}
)*
};
}
wide_store_load_roundtrip_neon! {
test_vld1_f32_x2(f32, 4, float32x2x2_t, vst1_f32_x2, vld1_f32_x2);
test_vld1_f32_x3(f32, 6, float32x2x3_t, vst1_f32_x3, vld1_f32_x3);
test_vld1_f32_x4(f32, 8, float32x2x4_t, vst1_f32_x4, vld1_f32_x4);
test_vld1q_f32_x2(f32, 8, float32x4x2_t, vst1q_f32_x2, vld1q_f32_x2);
test_vld1q_f32_x3(f32, 12, float32x4x3_t, vst1q_f32_x3, vld1q_f32_x3);
test_vld1q_f32_x4(f32, 16, float32x4x4_t, vst1q_f32_x4, vld1q_f32_x4);
test_vld1_s8_x2(i8, 16, int8x8x2_t, vst1_s8_x2, vld1_s8_x2);
test_vld1_s8_x3(i8, 24, int8x8x3_t, vst1_s8_x3, vld1_s8_x3);
test_vld1_s8_x4(i8, 32, int8x8x4_t, vst1_s8_x4, vld1_s8_x4);
test_vld1q_s8_x2(i8, 32, int8x16x2_t, vst1q_s8_x2, vld1q_s8_x2);
test_vld1q_s8_x3(i8, 48, int8x16x3_t, vst1q_s8_x3, vld1q_s8_x3);
test_vld1q_s8_x4(i8, 64, int8x16x4_t, vst1q_s8_x4, vld1q_s8_x4);
test_vld1_s16_x2(i16, 8, int16x4x2_t, vst1_s16_x2, vld1_s16_x2);
test_vld1_s16_x3(i16, 12, int16x4x3_t, vst1_s16_x3, vld1_s16_x3);
test_vld1_s16_x4(i16, 16, int16x4x4_t, vst1_s16_x4, vld1_s16_x4);
test_vld1q_s16_x2(i16, 16, int16x8x2_t, vst1q_s16_x2, vld1q_s16_x2);
test_vld1q_s16_x3(i16, 24, int16x8x3_t, vst1q_s16_x3, vld1q_s16_x3);
test_vld1q_s16_x4(i16, 32, int16x8x4_t, vst1q_s16_x4, vld1q_s16_x4);
test_vld1_s32_x2(i32, 4, int32x2x2_t, vst1_s32_x2, vld1_s32_x2);
test_vld1_s32_x3(i32, 6, int32x2x3_t, vst1_s32_x3, vld1_s32_x3);
test_vld1_s32_x4(i32, 8, int32x2x4_t, vst1_s32_x4, vld1_s32_x4);
test_vld1q_s32_x2(i32, 8, int32x4x2_t, vst1q_s32_x2, vld1q_s32_x2);
test_vld1q_s32_x3(i32, 12, int32x4x3_t, vst1q_s32_x3, vld1q_s32_x3);
test_vld1q_s32_x4(i32, 16, int32x4x4_t, vst1q_s32_x4, vld1q_s32_x4);
test_vld1_s64_x2(i64, 2, int64x1x2_t, vst1_s64_x2, vld1_s64_x2);
test_vld1_s64_x3(i64, 3, int64x1x3_t, vst1_s64_x3, vld1_s64_x3);
test_vld1_s64_x4(i64, 4, int64x1x4_t, vst1_s64_x4, vld1_s64_x4);
test_vld1q_s64_x2(i64, 4, int64x2x2_t, vst1q_s64_x2, vld1q_s64_x2);
test_vld1q_s64_x3(i64, 6, int64x2x3_t, vst1q_s64_x3, vld1q_s64_x3);
test_vld1q_s64_x4(i64, 8, int64x2x4_t, vst1q_s64_x4, vld1q_s64_x4);
test_vld1_u8_x2(u8, 16, uint8x8x2_t, vst1_u8_x2, vld1_u8_x2);
test_vld1_u8_x3(u8, 24, uint8x8x3_t, vst1_u8_x3, vld1_u8_x3);
test_vld1_u8_x4(u8, 32, uint8x8x4_t, vst1_u8_x4, vld1_u8_x4);
test_vld1q_u8_x2(u8, 32, uint8x16x2_t, vst1q_u8_x2, vld1q_u8_x2);
test_vld1q_u8_x3(u8, 48, uint8x16x3_t, vst1q_u8_x3, vld1q_u8_x3);
test_vld1q_u8_x4(u8, 64, uint8x16x4_t, vst1q_u8_x4, vld1q_u8_x4);
test_vld1_u16_x2(u16, 8, uint16x4x2_t, vst1_u16_x2, vld1_u16_x2);
test_vld1_u16_x3(u16, 12, uint16x4x3_t, vst1_u16_x3, vld1_u16_x3);
test_vld1_u16_x4(u16, 16, uint16x4x4_t, vst1_u16_x4, vld1_u16_x4);
test_vld1q_u16_x2(u16, 16, uint16x8x2_t, vst1q_u16_x2, vld1q_u16_x2);
test_vld1q_u16_x3(u16, 24, uint16x8x3_t, vst1q_u16_x3, vld1q_u16_x3);
test_vld1q_u16_x4(u16, 32, uint16x8x4_t, vst1q_u16_x4, vld1q_u16_x4);
test_vld1_u32_x2(u32, 4, uint32x2x2_t, vst1_u32_x2, vld1_u32_x2);
test_vld1_u32_x3(u32, 6, uint32x2x3_t, vst1_u32_x3, vld1_u32_x3);
test_vld1_u32_x4(u32, 8, uint32x2x4_t, vst1_u32_x4, vld1_u32_x4);
test_vld1q_u32_x2(u32, 8, uint32x4x2_t, vst1q_u32_x2, vld1q_u32_x2);
test_vld1q_u32_x3(u32, 12, uint32x4x3_t, vst1q_u32_x3, vld1q_u32_x3);
test_vld1q_u32_x4(u32, 16, uint32x4x4_t, vst1q_u32_x4, vld1q_u32_x4);
test_vld1_u64_x2(u64, 2, uint64x1x2_t, vst1_u64_x2, vld1_u64_x2);
test_vld1_u64_x3(u64, 3, uint64x1x3_t, vst1_u64_x3, vld1_u64_x3);
test_vld1_u64_x4(u64, 4, uint64x1x4_t, vst1_u64_x4, vld1_u64_x4);
test_vld1q_u64_x2(u64, 4, uint64x2x2_t, vst1q_u64_x2, vld1q_u64_x2);
test_vld1q_u64_x3(u64, 6, uint64x2x3_t, vst1q_u64_x3, vld1q_u64_x3);
test_vld1q_u64_x4(u64, 8, uint64x2x4_t, vst1q_u64_x4, vld1q_u64_x4);
test_vld1_p8_x2(p8, 16, poly8x8x2_t, vst1_p8_x2, vld1_p8_x2);
test_vld1_p8_x3(p8, 24, poly8x8x3_t, vst1_p8_x3, vld1_p8_x3);
test_vld1_p8_x4(p8, 32, poly8x8x4_t, vst1_p8_x4, vld1_p8_x4);
test_vld1q_p8_x2(p8, 32, poly8x16x2_t, vst1q_p8_x2, vld1q_p8_x2);
test_vld1q_p8_x3(p8, 48, poly8x16x3_t, vst1q_p8_x3, vld1q_p8_x3);
test_vld1q_p8_x4(p8, 64, poly8x16x4_t, vst1q_p8_x4, vld1q_p8_x4);
test_vld1_p16_x2(p16, 8, poly16x4x2_t, vst1_p16_x2, vld1_p16_x2);
test_vld1_p16_x3(p16, 12, poly16x4x3_t, vst1_p16_x3, vld1_p16_x3);
test_vld1_p16_x4(p16, 16, poly16x4x4_t, vst1_p16_x4, vld1_p16_x4);
test_vld1q_p16_x2(p16, 16, poly16x8x2_t, vst1q_p16_x2, vld1q_p16_x2);
test_vld1q_p16_x3(p16, 24, poly16x8x3_t, vst1q_p16_x3, vld1q_p16_x3);
test_vld1q_p16_x4(p16, 32, poly16x8x4_t, vst1q_p16_x4, vld1q_p16_x4);
}
}
#[cfg(test)]

1152
library/stdarch/crates/core_arch/src/arm_shared/neon/generated.rs
View file

File diff suppressed because it is too large Load diff

540
library/stdarch/crates/core_arch/src/powerpc/altivec.rs
View file

@ -47,6 +47,54 @@ types! {
pub struct vector_float(4 x f32);
}
#[unstable(feature = "stdarch_powerpc", issue = "111145")]
impl From<m8x16> for vector_bool_char {
#[inline]
fn from(value: m8x16) -> Self {
unsafe { transmute(value) }
}
}
#[unstable(feature = "stdarch_powerpc", issue = "111145")]
impl From<vector_bool_char> for m8x16 {
#[inline]
fn from(value: vector_bool_char) -> Self {
unsafe { transmute(value) }
}
}
#[unstable(feature = "stdarch_powerpc", issue = "111145")]
impl From<m16x8> for vector_bool_short {
#[inline]
fn from(value: m16x8) -> Self {
unsafe { transmute(value) }
}
}
#[unstable(feature = "stdarch_powerpc", issue = "111145")]
impl From<vector_bool_short> for m16x8 {
#[inline]
fn from(value: vector_bool_short) -> Self {
unsafe { transmute(value) }
}
}
#[unstable(feature = "stdarch_powerpc", issue = "111145")]
impl From<m32x4> for vector_bool_int {
#[inline]
fn from(value: m32x4) -> Self {
unsafe { transmute(value) }
}
}
#[unstable(feature = "stdarch_powerpc", issue = "111145")]
impl From<vector_bool_int> for m32x4 {
#[inline]
fn from(value: vector_bool_int) -> Self {
unsafe { transmute(value) }
}
}
#[allow(improper_ctypes)]
unsafe extern "C" {
#[link_name = "llvm.ppc.altivec.lvx"]
@ -129,8 +177,6 @@ unsafe extern "C" {
b: vector_signed_short,
c: vector_signed_int,
) -> vector_signed_int;
#[link_name = "llvm.ppc.altivec.vnmsubfp"]
fn vnmsubfp(a: vector_float, b: vector_float, c: vector_float) -> vector_float;
#[link_name = "llvm.ppc.altivec.vsum2sws"]
fn vsum2sws(a: vector_signed_int, b: vector_signed_int) -> vector_signed_int;
#[link_name = "llvm.ppc.altivec.vsum4ubs"]
@ -1881,9 +1927,9 @@ mod sealed {
#[inline]
#[target_feature(enable = "altivec")]
#[cfg_attr(test, assert_instr(vnmsubfp))]
unsafe fn vec_vnmsubfp(a: vector_float, b: vector_float, c: vector_float) -> vector_float {
vnmsubfp(a, b, c)
#[cfg_attr(test, assert_instr(xvnmsubasp))]
pub unsafe fn vec_vnmsubfp(a: vector_float, b: vector_float, c: vector_float) -> vector_float {
simd_neg(simd_fma(a, b, simd_neg(c)))
}
#[inline]
@ -3249,7 +3295,7 @@ mod sealed {
unsafe fn vec_round(self) -> Self;
}
test_impl! { vec_vrfin(a: vector_float) -> vector_float [vrfin, xvrspic] }
test_impl! { vec_vrfin(a: vector_float) -> vector_float [vrfin, vrfin] }
#[unstable(feature = "stdarch_powerpc", issue = "111145")]
impl VectorRound for vector_float {
@ -4281,7 +4327,7 @@ pub unsafe fn vec_madd(a: vector_float, b: vector_float, c: vector_float) -> vec
#[target_feature(enable = "altivec")]
#[unstable(feature = "stdarch_powerpc", issue = "111145")]
pub unsafe fn vec_nmsub(a: vector_float, b: vector_float, c: vector_float) -> vector_float {
vnmsubfp(a, b, c)
sealed::vec_vnmsubfp(a, b, c)
}
/// Vector Select
@ -4653,22 +4699,22 @@ mod tests {
};
{ $name: ident, $fn:ident, $ty: ident -> $ty_out: ident, [$($a:expr),+], [$($b:expr),+], [$($d:expr),+] } => {
#[simd_test(enable = "altivec")]
unsafe fn $name() {
let a: s_t_l!($ty) = transmute($ty::new($($a),+));
let b: s_t_l!($ty) = transmute($ty::new($($b),+));
fn $name() {
let a: s_t_l!($ty) = $ty::new($($a),+).into();
let b: s_t_l!($ty) = $ty::new($($b),+).into();
let d = $ty_out::new($($d),+);
let r : $ty_out = transmute($fn(a, b));
let r = $ty_out::from(unsafe { $fn(a, b) });
assert_eq!(d, r);
}
};
{ $name: ident, $fn:ident, $ty: ident -> $ty_out: ident, [$($a:expr),+], [$($b:expr),+], $d:expr } => {
#[simd_test(enable = "altivec")]
unsafe fn $name() {
let a: s_t_l!($ty) = transmute($ty::new($($a),+));
let b: s_t_l!($ty) = transmute($ty::new($($b),+));
fn $name() {
let a: s_t_l!($ty) = $ty::new($($a),+).into();
let b: s_t_l!($ty) = $ty::new($($b),+).into();
let r : $ty_out = transmute($fn(a, b));
let r = $ty_out::from(unsafe { $fn(a, b) });
assert_eq!($d, r);
}
}
@ -4677,11 +4723,11 @@ mod tests {
macro_rules! test_vec_1 {
{ $name: ident, $fn:ident, f32x4, [$($a:expr),+], ~[$($d:expr),+] } => {
#[simd_test(enable = "altivec")]
unsafe fn $name() {
let a: vector_float = transmute(f32x4::new($($a),+));
fn $name() {
let a = vector_float::from(f32x4::new($($a),+));
let d: vector_float = transmute(f32x4::new($($d),+));
let r = transmute(vec_cmple(vec_abs(vec_sub($fn(a), d)), vec_splats(f32::EPSILON)));
let d = vector_float::from(f32x4::new($($d),+));
let r = m32x4::from(unsafe { vec_cmple(vec_abs(vec_sub($fn(a), d)), vec_splats(f32::EPSILON)) });
let e = m32x4::new(true, true, true, true);
assert_eq!(e, r);
}
@ -4691,18 +4737,18 @@ mod tests {
};
{ $name: ident, $fn:ident, $ty: ident -> $ty_out: ident, [$($a:expr),+], [$($d:expr),+] } => {
#[simd_test(enable = "altivec")]
unsafe fn $name() {
let a: s_t_l!($ty) = transmute($ty::new($($a),+));
fn $name() {
let a: s_t_l!($ty) = $ty::new($($a),+).into();
let d = $ty_out::new($($d),+);
let r : $ty_out = transmute($fn(a));
let r = $ty_out::from(unsafe { $fn(a) });
assert_eq!(d, r);
}
}
}
#[simd_test(enable = "altivec")]
unsafe fn test_vec_ld() {
fn test_vec_ld() {
let pat = [
u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15),
u8x16::new(
@ -4711,14 +4757,14 @@ mod tests {
];
for off in 0..16 {
let v: u8x16 = transmute(vec_ld(0, (pat.as_ptr() as *const u8).offset(off)));
let v = u8x16::from(unsafe { vec_ld(0, (pat.as_ptr() as *const u8).offset(off)) });
assert_eq!(
v,
u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
);
}
for off in 16..32 {
let v: u8x16 = transmute(vec_ld(0, (pat.as_ptr() as *const u8).offset(off)));
let v = u8x16::from(unsafe { vec_ld(0, (pat.as_ptr() as *const u8).offset(off)) });
assert_eq!(
v,
u8x16::new(
@ -4729,7 +4775,7 @@ mod tests {
}
#[simd_test(enable = "altivec")]
unsafe fn test_vec_xl() {
fn test_vec_xl() {
let pat = [
u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15),
u8x16::new(
@ -4738,7 +4784,7 @@ mod tests {
];
for off in 0..16 {
let val: u8x16 = transmute(vec_xl(0, (pat.as_ptr() as *const u8).offset(off)));
let val = u8x16::from(unsafe { vec_xl(0, (pat.as_ptr() as *const u8).offset(off)) });
for i in 0..16 {
let v = val.extract_dyn(i);
assert_eq!(off as usize + i, v as usize);
@ -4747,14 +4793,16 @@ mod tests {
}
#[simd_test(enable = "altivec")]
unsafe fn test_vec_xst() {
let v: vector_unsigned_char = transmute(u8x16::new(
fn test_vec_xst() {
let v = vector_unsigned_char::from(u8x16::new(
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
));
for off in 0..16 {
let mut buf = [0u8; 32];
vec_xst(v, 0, (buf.as_mut_ptr() as *mut u8).offset(off));
unsafe {
vec_xst(v, 0, (buf.as_mut_ptr() as *mut u8).offset(off));
}
for i in 0..16 {
assert_eq!(i as u8, buf[off as usize..][i]);
}
@ -4762,7 +4810,7 @@ mod tests {
}
#[simd_test(enable = "altivec")]
unsafe fn test_vec_ldl() {
fn test_vec_ldl() {
let pat = [
u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15),
u8x16::new(
@ -4771,14 +4819,14 @@ mod tests {
];
for off in 0..16 {
let v: u8x16 = transmute(vec_ldl(0, (pat.as_ptr() as *const u8).offset(off)));
let v = u8x16::from(unsafe { vec_ldl(0, (pat.as_ptr() as *const u8).offset(off)) });
assert_eq!(
v,
u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
);
}
for off in 16..32 {
let v: u8x16 = transmute(vec_ldl(0, (pat.as_ptr() as *const u8).offset(off)));
let v = u8x16::from(unsafe { vec_ldl(0, (pat.as_ptr() as *const u8).offset(off)) });
assert_eq!(
v,
u8x16::new(
@ -4789,30 +4837,30 @@ mod tests {
}
#[simd_test(enable = "altivec")]
unsafe fn test_vec_lde_u8() {
fn test_vec_lde_u8() {
let pat = [u8x16::new(
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
)];
for off in 0..16 {
let v: u8x16 = transmute(vec_lde(off, pat.as_ptr() as *const u8));
let v = u8x16::from(unsafe { vec_lde(off, pat.as_ptr() as *const u8) });
assert_eq!(off as u8, v.extract_dyn(off as _));
}
}
#[simd_test(enable = "altivec")]
unsafe fn test_vec_lde_u16() {
fn test_vec_lde_u16() {
let pat = [u16x8::new(0, 1, 2, 3, 4, 5, 6, 7)];
for off in 0..8 {
let v: u16x8 = transmute(vec_lde(off * 2, pat.as_ptr() as *const u16));
let v = u16x8::from(unsafe { vec_lde(off * 2, pat.as_ptr() as *const u16) });
assert_eq!(off as u16, v.extract_dyn(off as _));
}
}
#[simd_test(enable = "altivec")]
unsafe fn test_vec_lde_u32() {
fn test_vec_lde_u32() {
let pat = [u32x4::new(0, 1, 2, 3)];
for off in 0..4 {
let v: u32x4 = transmute(vec_lde(off * 4, pat.as_ptr() as *const u32));
let v = u32x4::from(unsafe { vec_lde(off * 4, pat.as_ptr() as *const u32) });
assert_eq!(off as u32, v.extract_dyn(off as _));
}
}
@ -5818,9 +5866,9 @@ mod tests {
}
#[simd_test(enable = "altivec")]
unsafe fn test_vec_cmpb() {
let a: vector_float = transmute(f32x4::new(0.1, 0.5, 0.6, 0.9));
let b: vector_float = transmute(f32x4::new(-0.1, 0.5, -0.6, 0.9));
fn test_vec_cmpb() {
let a = vector_float::from(f32x4::new(0.1, 0.5, 0.6, 0.9));
let b = vector_float::from(f32x4::new(-0.1, 0.5, -0.6, 0.9));
let d = i32x4::new(
-0b10000000000000000000000000000000,
0,
@ -5828,15 +5876,15 @@ mod tests {
0,
);
assert_eq!(d, transmute(vec_cmpb(a, b)));
assert_eq!(d, i32x4::from(unsafe { vec_cmpb(a, b) }));
}
#[simd_test(enable = "altivec")]
unsafe fn test_vec_ceil() {
let a: vector_float = transmute(f32x4::new(0.1, 0.5, 0.6, 0.9));
fn test_vec_ceil() {
let a = vector_float::from(f32x4::new(0.1, 0.5, 0.6, 0.9));
let d = f32x4::new(1.0, 1.0, 1.0, 1.0);
assert_eq!(d, transmute(vec_ceil(a)));
assert_eq!(d, f32x4::from(unsafe { vec_ceil(a) }));
}
test_vec_2! { test_vec_andc, vec_andc, i32x4,
@ -5926,11 +5974,11 @@ mod tests {
macro_rules! test_vec_abs {
{ $name: ident, $ty: ident, $a: expr, $d: expr } => {
#[simd_test(enable = "altivec")]
unsafe fn $name() {
let a = vec_splats($a);
let a: s_t_l!($ty) = vec_abs(a);
fn $name() {
let a = unsafe { vec_splats($a) };
let a: s_t_l!($ty) = unsafe { vec_abs(a) };
let d = $ty::splat($d);
assert_eq!(d, transmute(a));
assert_eq!(d, $ty::from(a));
}
}
}
@ -5943,11 +5991,11 @@ mod tests {
macro_rules! test_vec_abss {
{ $name: ident, $ty: ident, $a: expr, $d: expr } => {
#[simd_test(enable = "altivec")]
unsafe fn $name() {
let a = vec_splats($a);
let a: s_t_l!($ty) = vec_abss(a);
fn $name() {
let a = unsafe { vec_splats($a) };
let a: s_t_l!($ty) = unsafe { vec_abss(a) };
let d = $ty::splat($d);
assert_eq!(d, transmute(a));
assert_eq!(d, $ty::from(a));
}
}
}
@ -5959,10 +6007,10 @@ mod tests {
macro_rules! test_vec_splats {
{ $name: ident, $ty: ident, $a: expr } => {
#[simd_test(enable = "altivec")]
unsafe fn $name() {
let a: s_t_l!($ty) = vec_splats($a);
fn $name() {
let a: s_t_l!($ty) = unsafe { vec_splats($a) };
let d = $ty::splat($a);
assert_eq!(d, transmute(a));
assert_eq!(d, $ty::from(a));
}
}
}
@ -5978,10 +6026,10 @@ mod tests {
macro_rules! test_vec_splat {
{ $name: ident, $fun: ident, $ty: ident, $a: expr, $b: expr} => {
#[simd_test(enable = "altivec")]
unsafe fn $name() {
let a = $fun::<$a>();
fn $name() {
let a = unsafe { $fun::<$a>() };
let d = $ty::splat($b);
assert_eq!(d, transmute(a));
assert_eq!(d, $ty::from(a));
}
}
}
@ -6073,12 +6121,12 @@ mod tests {
macro_rules! test_vec_min {
{ $name: ident, $ty: ident, [$($a:expr),+], [$($b:expr),+], [$($d:expr),+] } => {
#[simd_test(enable = "altivec")]
unsafe fn $name() {
let a: s_t_l!($ty) = transmute($ty::new($($a),+));
let b: s_t_l!($ty) = transmute($ty::new($($b),+));
fn $name() {
let a: s_t_l!($ty) = $ty::new($($a),+).into();
let b: s_t_l!($ty) = $ty::new($($b),+).into();
let d = $ty::new($($d),+);
let r : $ty = transmute(vec_min(a, b));
let r = $ty::from(unsafe { vec_min(a, b) });
assert_eq!(d, r);
}
}
@ -6117,12 +6165,12 @@ mod tests {
macro_rules! test_vec_max {
{ $name: ident, $ty: ident, [$($a:expr),+], [$($b:expr),+], [$($d:expr),+] } => {
#[simd_test(enable = "altivec")]
unsafe fn $name() {
let a: s_t_l!($ty) = transmute($ty::new($($a),+));
let b: s_t_l!($ty) = transmute($ty::new($($b),+));
fn $name() {
let a: s_t_l!($ty) = $ty::new($($a),+).into();
let b: s_t_l!($ty) = $ty::new($($b),+).into();
let d = $ty::new($($d),+);
let r : $ty = transmute(vec_max(a, b));
let r = $ty::from(unsafe { vec_max(a, b) });
assert_eq!(d, r);
}
}
@ -6163,13 +6211,13 @@ mod tests {
$shorttype:ident, $longtype:ident,
[$($a:expr),+], [$($b:expr),+], [$($c:expr),+], [$($d:expr),+]} => {
#[simd_test(enable = "altivec")]
unsafe fn $name() {
let a: $longtype = transmute($shorttype::new($($a),+));
let b: $longtype = transmute($shorttype::new($($b),+));
let c: vector_unsigned_char = transmute(u8x16::new($($c),+));
fn $name() {
let a = $longtype::from($shorttype::new($($a),+));
let b = $longtype::from($shorttype::new($($b),+));
let c = vector_unsigned_char::from(u8x16::new($($c),+));
let d = $shorttype::new($($d),+);
let r: $shorttype = transmute(vec_perm(a, b, c));
let r = $shorttype::from(unsafe { vec_perm(a, b, c) });
assert_eq!(d, r);
}
}
@ -6249,8 +6297,8 @@ mod tests {
[0.0, 1.0, 1.0, 1.1]}
#[simd_test(enable = "altivec")]
unsafe fn test_vec_madds() {
let a: vector_signed_short = transmute(i16x8::new(
fn test_vec_madds() {
let a = vector_signed_short::from(i16x8::new(
0 * 256,
1 * 256,
2 * 256,
@ -6260,19 +6308,19 @@ mod tests {
6 * 256,
7 * 256,
));
let b: vector_signed_short = transmute(i16x8::new(256, 256, 256, 256, 256, 256, 256, 256));
let c: vector_signed_short = transmute(i16x8::new(0, 1, 2, 3, 4, 5, 6, 7));
let b = vector_signed_short::from(i16x8::new(256, 256, 256, 256, 256, 256, 256, 256));
let c = vector_signed_short::from(i16x8::new(0, 1, 2, 3, 4, 5, 6, 7));
let d = i16x8::new(0, 3, 6, 9, 12, 15, 18, 21);
assert_eq!(d, transmute(vec_madds(a, b, c)));
assert_eq!(d, i16x8::from(unsafe { vec_madds(a, b, c) }));
}
#[simd_test(enable = "altivec")]
unsafe fn test_vec_madd_float() {
let a: vector_float = transmute(f32x4::new(0.1, 0.2, 0.3, 0.4));
let b: vector_float = transmute(f32x4::new(0.1, 0.2, 0.3, 0.4));
let c: vector_float = transmute(f32x4::new(0.1, 0.2, 0.3, 0.4));
fn test_vec_madd_float() {
let a = vector_float::from(f32x4::new(0.1, 0.2, 0.3, 0.4));
let b = vector_float::from(f32x4::new(0.1, 0.2, 0.3, 0.4));
let c = vector_float::from(f32x4::new(0.1, 0.2, 0.3, 0.4));
let d = f32x4::new(
0.1 * 0.1 + 0.1,
0.2 * 0.2 + 0.2,
@ -6280,26 +6328,26 @@ mod tests {
0.4 * 0.4 + 0.4,
);
assert_eq!(d, transmute(vec_madd(a, b, c)));
assert_eq!(d, f32x4::from(unsafe { vec_madd(a, b, c) }));
}
#[simd_test(enable = "altivec")]
unsafe fn test_vec_nmsub_float() {
let a: vector_float = transmute(f32x4::new(0.1, 0.2, 0.3, 0.4));
let b: vector_float = transmute(f32x4::new(0.1, 0.2, 0.3, 0.4));
let c: vector_float = transmute(f32x4::new(0.1, 0.2, 0.3, 0.4));
fn test_vec_nmsub_float() {
let a = vector_float::from(f32x4::new(0.1, 0.2, 0.3, 0.4));
let b = vector_float::from(f32x4::new(0.1, 0.2, 0.3, 0.4));
let c = vector_float::from(f32x4::new(0.1, 0.2, 0.3, 0.4));
let d = f32x4::new(
-(0.1 * 0.1 - 0.1),
-(0.2 * 0.2 - 0.2),
-(0.3 * 0.3 - 0.3),
-(0.4 * 0.4 - 0.4),
);
assert_eq!(d, transmute(vec_nmsub(a, b, c)));
assert_eq!(d, f32x4::from(unsafe { vec_nmsub(a, b, c) }));
}
#[simd_test(enable = "altivec")]
unsafe fn test_vec_mradds() {
let a: vector_signed_short = transmute(i16x8::new(
fn test_vec_mradds() {
let a = vector_signed_short::from(i16x8::new(
0 * 256,
1 * 256,
2 * 256,
@ -6309,25 +6357,25 @@ mod tests {
6 * 256,
7 * 256,
));
let b: vector_signed_short = transmute(i16x8::new(256, 256, 256, 256, 256, 256, 256, 256));
let c: vector_signed_short = transmute(i16x8::new(0, 1, 2, 3, 4, 5, 6, i16::MAX - 1));
let b = vector_signed_short::from(i16x8::new(256, 256, 256, 256, 256, 256, 256, 256));
let c = vector_signed_short::from(i16x8::new(0, 1, 2, 3, 4, 5, 6, i16::MAX - 1));
let d = i16x8::new(0, 3, 6, 9, 12, 15, 18, i16::MAX);
assert_eq!(d, transmute(vec_mradds(a, b, c)));
assert_eq!(d, i16x8::from(unsafe { vec_mradds(a, b, c) }));
}
macro_rules! test_vec_mladd {
{$name:ident, $sa:ident, $la:ident, $sbc:ident, $lbc:ident, $sd:ident,
[$($a:expr),+], [$($b:expr),+], [$($c:expr),+], [$($d:expr),+]} => {
#[simd_test(enable = "altivec")]
unsafe fn $name() {
let a: $la = transmute($sa::new($($a),+));
let b: $lbc = transmute($sbc::new($($b),+));
let c = transmute($sbc::new($($c),+));
fn $name() {
let a = $la::from($sa::new($($a),+));
let b = $lbc::from($sbc::new($($b),+));
let c = $sbc::new($($c),+).into();
let d = $sd::new($($d),+);
assert_eq!(d, transmute(vec_mladd(a, b, c)));
assert_eq!(d, $sd::from(unsafe { vec_mladd(a, b, c) }));
}
}
}
@ -6335,24 +6383,24 @@ mod tests {
test_vec_mladd! { test_vec_mladd_u16x8_u16x8, u16x8, vector_unsigned_short, u16x8, vector_unsigned_short, u16x8,
[0, 1, 2, 3, 4, 5, 6, 7], [0, 1, 2, 3, 4, 5, 6, 7], [0, 1, 2, 3, 4, 5, 6, 7], [0, 2, 6, 12, 20, 30, 42, 56]
}
test_vec_mladd! { test_vec_mladd_u16x8_i16x8, u16x8, vector_unsigned_short, i16x8, vector_unsigned_short, i16x8,
test_vec_mladd! { test_vec_mladd_u16x8_i16x8, u16x8, vector_unsigned_short, i16x8, vector_signed_short, i16x8,
[0, 1, 2, 3, 4, 5, 6, 7], [0, 1, 2, 3, 4, 5, 6, 7], [0, 1, 2, 3, 4, 5, 6, 7], [0, 2, 6, 12, 20, 30, 42, 56]
}
test_vec_mladd! { test_vec_mladd_i16x8_u16x8, i16x8, vector_signed_short, u16x8, vector_unsigned_short, i16x8,
[0, 1, 2, 3, 4, 5, 6, 7], [0, 1, 2, 3, 4, 5, 6, 7], [0, 1, 2, 3, 4, 5, 6, 7], [0, 2, 6, 12, 20, 30, 42, 56]
}
test_vec_mladd! { test_vec_mladd_i16x8_i16x8, i16x8, vector_signed_short, i16x8, vector_unsigned_short, i16x8,
test_vec_mladd! { test_vec_mladd_i16x8_i16x8, i16x8, vector_signed_short, i16x8, vector_signed_short, i16x8,
[0, 1, 2, 3, 4, 5, 6, 7], [0, 1, 2, 3, 4, 5, 6, 7], [0, 1, 2, 3, 4, 5, 6, 7], [0, 2, 6, 12, 20, 30, 42, 56]
}
#[simd_test(enable = "altivec")]
unsafe fn test_vec_msum_unsigned_char() {
let a: vector_unsigned_char =
transmute(u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7));
let b: vector_unsigned_char = transmute(u8x16::new(
fn test_vec_msum_unsigned_char() {
let a =
vector_unsigned_char::from(u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7));
let b = vector_unsigned_char::from(u8x16::new(
255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255,
));
let c: vector_unsigned_int = transmute(u32x4::new(0, 1, 2, 3));
let c = vector_unsigned_int::from(u32x4::new(0, 1, 2, 3));
let d = u32x4::new(
(0 + 1 + 2 + 3) * 255 + 0,
(4 + 5 + 6 + 7) * 255 + 1,
@ -6360,17 +6408,17 @@ mod tests {
(4 + 5 + 6 + 7) * 255 + 3,
);
assert_eq!(d, transmute(vec_msum(a, b, c)));
assert_eq!(d, u32x4::from(unsafe { vec_msum(a, b, c) }));
}
#[simd_test(enable = "altivec")]
unsafe fn test_vec_msum_signed_char() {
let a: vector_signed_char = transmute(i8x16::new(
fn test_vec_msum_signed_char() {
let a = vector_signed_char::from(i8x16::new(
0, -1, 2, -3, 1, -1, 1, -1, 0, 1, 2, 3, 4, -5, -6, -7,
));
let b: vector_unsigned_char =
transmute(i8x16::new(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1));
let c: vector_signed_int = transmute(u32x4::new(0, 1, 2, 3));
let b =
vector_unsigned_char::from(u8x16::new(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1));
let c = vector_signed_int::from(i32x4::new(0, 1, 2, 3));
let d = i32x4::new(
(0 - 1 + 2 - 3) + 0,
(0) + 1,
@ -6378,11 +6426,12 @@ mod tests {
(4 - 5 - 6 - 7) + 3,
);
assert_eq!(d, transmute(vec_msum(a, b, c)));
assert_eq!(d, i32x4::from(unsafe { vec_msum(a, b, c) }));
}
#[simd_test(enable = "altivec")]
unsafe fn test_vec_msum_unsigned_short() {
let a: vector_unsigned_short = transmute(u16x8::new(
fn test_vec_msum_unsigned_short() {
let a = vector_unsigned_short::from(u16x8::new(
0 * 256,
1 * 256,
2 * 256,
@ -6392,9 +6441,8 @@ mod tests {
6 * 256,
7 * 256,
));
let b: vector_unsigned_short =
transmute(u16x8::new(256, 256, 256, 256, 256, 256, 256, 256));
let c: vector_unsigned_int = transmute(u32x4::new(0, 1, 2, 3));
let b = vector_unsigned_short::from(u16x8::new(256, 256, 256, 256, 256, 256, 256, 256));
let c = vector_unsigned_int::from(u32x4::new(0, 1, 2, 3));
let d = u32x4::new(
(0 + 1) * 256 * 256 + 0,
(2 + 3) * 256 * 256 + 1,
@ -6402,12 +6450,12 @@ mod tests {
(6 + 7) * 256 * 256 + 3,
);
assert_eq!(d, transmute(vec_msum(a, b, c)));
assert_eq!(d, u32x4::from(unsafe { vec_msum(a, b, c) }));
}
#[simd_test(enable = "altivec")]
unsafe fn test_vec_msum_signed_short() {
let a: vector_signed_short = transmute(i16x8::new(
fn test_vec_msum_signed_short() {
let a = vector_signed_short::from(i16x8::new(
0 * 256,
-1 * 256,
2 * 256,
@ -6417,8 +6465,8 @@ mod tests {
6 * 256,
-7 * 256,
));
let b: vector_signed_short = transmute(i16x8::new(256, 256, 256, 256, 256, 256, 256, 256));
let c: vector_signed_int = transmute(i32x4::new(0, 1, 2, 3));
let b = vector_signed_short::from(i16x8::new(256, 256, 256, 256, 256, 256, 256, 256));
let c = vector_signed_int::from(i32x4::new(0, 1, 2, 3));
let d = i32x4::new(
(0 - 1) * 256 * 256 + 0,
(2 - 3) * 256 * 256 + 1,
@ -6426,12 +6474,12 @@ mod tests {
(6 - 7) * 256 * 256 + 3,
);
assert_eq!(d, transmute(vec_msum(a, b, c)));
assert_eq!(d, i32x4::from(unsafe { vec_msum(a, b, c) }));
}
#[simd_test(enable = "altivec")]
unsafe fn test_vec_msums_unsigned() {
let a: vector_unsigned_short = transmute(u16x8::new(
fn test_vec_msums_unsigned() {
let a = vector_unsigned_short::from(u16x8::new(
0 * 256,
1 * 256,
2 * 256,
@ -6441,9 +6489,8 @@ mod tests {
6 * 256,
7 * 256,
));
let b: vector_unsigned_short =
transmute(u16x8::new(256, 256, 256, 256, 256, 256, 256, 256));
let c: vector_unsigned_int = transmute(u32x4::new(0, 1, 2, 3));
let b = vector_unsigned_short::from(u16x8::new(256, 256, 256, 256, 256, 256, 256, 256));
let c = vector_unsigned_int::from(u32x4::new(0, 1, 2, 3));
let d = u32x4::new(
(0 + 1) * 256 * 256 + 0,
(2 + 3) * 256 * 256 + 1,
@ -6451,12 +6498,12 @@ mod tests {
(6 + 7) * 256 * 256 + 3,
);
assert_eq!(d, transmute(vec_msums(a, b, c)));
assert_eq!(d, u32x4::from(unsafe { vec_msums(a, b, c) }));
}
#[simd_test(enable = "altivec")]
unsafe fn test_vec_msums_signed() {
let a: vector_signed_short = transmute(i16x8::new(
fn test_vec_msums_signed() {
let a = vector_signed_short::from(i16x8::new(
0 * 256,
-1 * 256,
2 * 256,
@ -6466,8 +6513,8 @@ mod tests {
6 * 256,
-7 * 256,
));
let b: vector_signed_short = transmute(i16x8::new(256, 256, 256, 256, 256, 256, 256, 256));
let c: vector_signed_int = transmute(i32x4::new(0, 1, 2, 3));
let b = vector_signed_short::from(i16x8::new(256, 256, 256, 256, 256, 256, 256, 256));
let c = vector_signed_int::from(i32x4::new(0, 1, 2, 3));
let d = i32x4::new(
(0 - 1) * 256 * 256 + 0,
(2 - 3) * 256 * 256 + 1,
@ -6475,23 +6522,23 @@ mod tests {
(6 - 7) * 256 * 256 + 3,
);
assert_eq!(d, transmute(vec_msums(a, b, c)));
assert_eq!(d, i32x4::from(unsafe { vec_msums(a, b, c) }));
}
#[simd_test(enable = "altivec")]
unsafe fn test_vec_sum2s() {
let a: vector_signed_int = transmute(i32x4::new(0, 1, 2, 3));
let b: vector_signed_int = transmute(i32x4::new(0, 1, 2, 3));
fn test_vec_sum2s() {
let a = vector_signed_int::from(i32x4::new(0, 1, 2, 3));
let b = vector_signed_int::from(i32x4::new(0, 1, 2, 3));
let d = i32x4::new(0, 0 + 1 + 1, 0, 2 + 3 + 3);
assert_eq!(d, transmute(vec_sum2s(a, b)));
assert_eq!(d, i32x4::from(unsafe { vec_sum2s(a, b) }));
}
#[simd_test(enable = "altivec")]
unsafe fn test_vec_sum4s_unsigned_char() {
let a: vector_unsigned_char =
transmute(u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7));
let b: vector_unsigned_int = transmute(u32x4::new(0, 1, 2, 3));
fn test_vec_sum4s_unsigned_char() {
let a =
vector_unsigned_char::from(u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7));
let b = vector_unsigned_int::from(u32x4::new(0, 1, 2, 3));
let d = u32x4::new(
0 + 1 + 2 + 3 + 0,
4 + 5 + 6 + 7 + 1,
@ -6499,13 +6546,13 @@ mod tests {
4 + 5 + 6 + 7 + 3,
);
assert_eq!(d, transmute(vec_sum4s(a, b)));
assert_eq!(d, u32x4::from(unsafe { vec_sum4s(a, b) }));
}
#[simd_test(enable = "altivec")]
unsafe fn test_vec_sum4s_signed_char() {
let a: vector_signed_char =
transmute(i8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7));
let b: vector_signed_int = transmute(i32x4::new(0, 1, 2, 3));
fn test_vec_sum4s_signed_char() {
let a =
vector_signed_char::from(i8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7));
let b = vector_signed_int::from(i32x4::new(0, 1, 2, 3));
let d = i32x4::new(
0 + 1 + 2 + 3 + 0,
4 + 5 + 6 + 7 + 1,
@ -6513,109 +6560,110 @@ mod tests {
4 + 5 + 6 + 7 + 3,
);
assert_eq!(d, transmute(vec_sum4s(a, b)));
assert_eq!(d, i32x4::from(unsafe { vec_sum4s(a, b) }));
}
#[simd_test(enable = "altivec")]
unsafe fn test_vec_sum4s_signed_short() {
let a: vector_signed_short = transmute(i16x8::new(0, 1, 2, 3, 4, 5, 6, 7));
let b: vector_signed_int = transmute(i32x4::new(0, 1, 2, 3));
fn test_vec_sum4s_signed_short() {
let a = vector_signed_short::from(i16x8::new(0, 1, 2, 3, 4, 5, 6, 7));
let b = vector_signed_int::from(i32x4::new(0, 1, 2, 3));
let d = i32x4::new(0 + 1 + 0, 2 + 3 + 1, 4 + 5 + 2, 6 + 7 + 3);
assert_eq!(d, transmute(vec_sum4s(a, b)));
assert_eq!(d, i32x4::from(unsafe { vec_sum4s(a, b) }));
}
#[simd_test(enable = "altivec")]
unsafe fn test_vec_mule_unsigned_char() {
let a: vector_unsigned_char =
transmute(u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7));
fn test_vec_mule_unsigned_char() {
let a =
vector_unsigned_char::from(u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7));
let d = u16x8::new(0 * 0, 2 * 2, 4 * 4, 6 * 6, 0 * 0, 2 * 2, 4 * 4, 6 * 6);
assert_eq!(d, transmute(vec_mule(a, a)));
assert_eq!(d, u16x8::from(unsafe { vec_mule(a, a) }));
}
#[simd_test(enable = "altivec")]
unsafe fn test_vec_mule_signed_char() {
let a: vector_signed_char = transmute(i8x16::new(
fn test_vec_mule_signed_char() {
let a = vector_signed_char::from(i8x16::new(
0, 1, -2, 3, -4, 5, -6, 7, 0, 1, 2, 3, 4, 5, 6, 7,
));
let d = i16x8::new(0 * 0, 2 * 2, 4 * 4, 6 * 6, 0 * 0, 2 * 2, 4 * 4, 6 * 6);
assert_eq!(d, transmute(vec_mule(a, a)));
assert_eq!(d, i16x8::from(unsafe { vec_mule(a, a) }));
}
#[simd_test(enable = "altivec")]
unsafe fn test_vec_mule_unsigned_short() {
let a: vector_unsigned_short = transmute(u16x8::new(0, 1, 2, 3, 4, 5, 6, 7));
fn test_vec_mule_unsigned_short() {
let a = vector_unsigned_short::from(u16x8::new(0, 1, 2, 3, 4, 5, 6, 7));
let d = u32x4::new(0 * 0, 2 * 2, 4 * 4, 6 * 6);
assert_eq!(d, transmute(vec_mule(a, a)));
assert_eq!(d, u32x4::from(unsafe { vec_mule(a, a) }));
}
#[simd_test(enable = "altivec")]
unsafe fn test_vec_mule_signed_short() {
let a: vector_signed_short = transmute(i16x8::new(0, 1, -2, 3, -4, 5, -6, 7));
fn test_vec_mule_signed_short() {
let a = vector_signed_short::from(i16x8::new(0, 1, -2, 3, -4, 5, -6, 7));
let d = i32x4::new(0 * 0, 2 * 2, 4 * 4, 6 * 6);
assert_eq!(d, transmute(vec_mule(a, a)));
assert_eq!(d, i32x4::from(unsafe { vec_mule(a, a) }));
}
#[simd_test(enable = "altivec")]
unsafe fn test_vec_mulo_unsigned_char() {
let a: vector_unsigned_char =
transmute(u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7));
fn test_vec_mulo_unsigned_char() {
let a =
vector_unsigned_char::from(u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7));
let d = u16x8::new(1 * 1, 3 * 3, 5 * 5, 7 * 7, 1 * 1, 3 * 3, 5 * 5, 7 * 7);
assert_eq!(d, transmute(vec_mulo(a, a)));
assert_eq!(d, u16x8::from(unsafe { vec_mulo(a, a) }));
}
#[simd_test(enable = "altivec")]
unsafe fn test_vec_mulo_signed_char() {
let a: vector_signed_char = transmute(i8x16::new(
fn test_vec_mulo_signed_char() {
let a = vector_signed_char::from(i8x16::new(
0, 1, -2, 3, -4, 5, -6, 7, 0, 1, 2, 3, 4, 5, 6, 7,
));
let d = i16x8::new(1 * 1, 3 * 3, 5 * 5, 7 * 7, 1 * 1, 3 * 3, 5 * 5, 7 * 7);
assert_eq!(d, transmute(vec_mulo(a, a)));
assert_eq!(d, i16x8::from(unsafe { vec_mulo(a, a) }));
}
#[simd_test(enable = "altivec")]
unsafe fn test_vec_mulo_unsigned_short() {
let a: vector_unsigned_short = transmute(u16x8::new(0, 1, 2, 3, 4, 5, 6, 7));
fn test_vec_mulo_unsigned_short() {
let a = vector_unsigned_short::from(u16x8::new(0, 1, 2, 3, 4, 5, 6, 7));
let d = u32x4::new(1 * 1, 3 * 3, 5 * 5, 7 * 7);
assert_eq!(d, transmute(vec_mulo(a, a)));
assert_eq!(d, u32x4::from(unsafe { vec_mulo(a, a) }));
}
#[simd_test(enable = "altivec")]
unsafe fn test_vec_mulo_signed_short() {
let a: vector_signed_short = transmute(i16x8::new(0, 1, -2, 3, -4, 5, -6, 7));
fn test_vec_mulo_signed_short() {
let a = vector_signed_short::from(i16x8::new(0, 1, -2, 3, -4, 5, -6, 7));
let d = i32x4::new(1 * 1, 3 * 3, 5 * 5, 7 * 7);
assert_eq!(d, transmute(vec_mulo(a, a)));
assert_eq!(d, i32x4::from(unsafe { vec_mulo(a, a) }));
}
#[simd_test(enable = "altivec")]
unsafe fn vec_add_i32x4_i32x4() {
fn vec_add_i32x4_i32x4() {
let x = i32x4::new(1, 2, 3, 4);
let y = i32x4::new(4, 3, 2, 1);
let x: vector_signed_int = transmute(x);
let y: vector_signed_int = transmute(y);
let z = vec_add(x, y);
assert_eq!(i32x4::splat(5), transmute(z));
let x = vector_signed_int::from(x);
let y = vector_signed_int::from(y);
let z = unsafe { vec_add(x, y) };
assert_eq!(i32x4::splat(5), i32x4::from(z));
}
#[simd_test(enable = "altivec")]
unsafe fn vec_ctf_u32() {
let v: vector_unsigned_int = transmute(u32x4::new(u32::MIN, u32::MAX, u32::MAX, 42));
let v2 = vec_ctf::<1, _>(v);
let r2: vector_float = transmute(f32x4::new(0.0, 2147483600.0, 2147483600.0, 21.0));
let v4 = vec_ctf::<2, _>(v);
let r4: vector_float = transmute(f32x4::new(0.0, 1073741800.0, 1073741800.0, 10.5));
let v8 = vec_ctf::<3, _>(v);
let r8: vector_float = transmute(f32x4::new(0.0, 536870900.0, 536870900.0, 5.25));
fn vec_ctf_u32() {
let v = vector_unsigned_int::from(u32x4::new(u32::MIN, u32::MAX, u32::MAX, 42));
let v2 = unsafe { vec_ctf::<1, _>(v) };
let r2 = vector_float::from(f32x4::new(0.0, 2147483600.0, 2147483600.0, 21.0));
let v4 = unsafe { vec_ctf::<2, _>(v) };
let r4 = vector_float::from(f32x4::new(0.0, 1073741800.0, 1073741800.0, 10.5));
let v8 = unsafe { vec_ctf::<3, _>(v) };
let r8 = vector_float::from(f32x4::new(0.0, 536870900.0, 536870900.0, 5.25));
let check = |a, b| {
let r = transmute(vec_cmple(vec_abs(vec_sub(a, b)), vec_splats(f32::EPSILON)));
let r =
m32x4::from(unsafe { vec_cmple(vec_abs(vec_sub(a, b)), vec_splats(f32::EPSILON)) });
let e = m32x4::new(true, true, true, true);
assert_eq!(e, r);
};
@ -6626,26 +6674,32 @@ mod tests {
}
#[simd_test(enable = "altivec")]
unsafe fn test_vec_ctu() {
fn test_vec_ctu() {
let v = u32x4::new(u32::MIN, u32::MAX, u32::MAX, 42);
let v2: u32x4 = transmute(vec_ctu::<1>(transmute(f32x4::new(
0.0,
2147483600.0,
2147483600.0,
21.0,
))));
let v4: u32x4 = transmute(vec_ctu::<2>(transmute(f32x4::new(
0.0,
1073741800.0,
1073741800.0,
10.5,
))));
let v8: u32x4 = transmute(vec_ctu::<3>(transmute(f32x4::new(
0.0,
536870900.0,
536870900.0,
5.25,
))));
let v2 = u32x4::from(unsafe {
vec_ctu::<1>(vector_float::from(f32x4::new(
0.0,
2147483600.0,
2147483600.0,
21.0,
)))
});
let v4 = u32x4::from(unsafe {
vec_ctu::<2>(vector_float::from(f32x4::new(
0.0,
1073741800.0,
1073741800.0,
10.5,
)))
});
let v8 = u32x4::from(unsafe {
vec_ctu::<3>(vector_float::from(f32x4::new(
0.0,
536870900.0,
536870900.0,
5.25,
)))
});
assert_eq!(v2, v);
assert_eq!(v4, v);
@ -6653,18 +6707,18 @@ mod tests {
}
#[simd_test(enable = "altivec")]
unsafe fn vec_ctf_i32() {
let v: vector_signed_int = transmute(i32x4::new(i32::MIN, i32::MAX, i32::MAX - 42, 42));
let v2 = vec_ctf::<1, _>(v);
let r2: vector_float =
transmute(f32x4::new(-1073741800.0, 1073741800.0, 1073741800.0, 21.0));
let v4 = vec_ctf::<2, _>(v);
let r4: vector_float = transmute(f32x4::new(-536870900.0, 536870900.0, 536870900.0, 10.5));
let v8 = vec_ctf::<3, _>(v);
let r8: vector_float = transmute(f32x4::new(-268435460.0, 268435460.0, 268435460.0, 5.25));
fn vec_ctf_i32() {
let v = vector_signed_int::from(i32x4::new(i32::MIN, i32::MAX, i32::MAX - 42, 42));
let v2 = unsafe { vec_ctf::<1, _>(v) };
let r2 = vector_float::from(f32x4::new(-1073741800.0, 1073741800.0, 1073741800.0, 21.0));
let v4 = unsafe { vec_ctf::<2, _>(v) };
let r4 = vector_float::from(f32x4::new(-536870900.0, 536870900.0, 536870900.0, 10.5));
let v8 = unsafe { vec_ctf::<3, _>(v) };
let r8 = vector_float::from(f32x4::new(-268435460.0, 268435460.0, 268435460.0, 5.25));
let check = |a, b| {
let r = transmute(vec_cmple(vec_abs(vec_sub(a, b)), vec_splats(f32::EPSILON)));
let r =
m32x4::from(unsafe { vec_cmple(vec_abs(vec_sub(a, b)), vec_splats(f32::EPSILON)) });
println!("{:?} {:?}", a, b);
let e = m32x4::new(true, true, true, true);
assert_eq!(e, r);
@ -6676,26 +6730,32 @@ mod tests {
}
#[simd_test(enable = "altivec")]
unsafe fn test_vec_cts() {
fn test_vec_cts() {
let v = i32x4::new(i32::MIN, i32::MAX, i32::MAX, 42);
let v2: i32x4 = transmute(vec_cts::<1>(transmute(f32x4::new(
-1073741800.0,
1073741800.0,
1073741800.0,
21.0,
))));
let v4: i32x4 = transmute(vec_cts::<2>(transmute(f32x4::new(
-536870900.0,
536870900.0,
536870900.0,
10.5,
))));
let v8: i32x4 = transmute(vec_cts::<3>(transmute(f32x4::new(
-268435460.0,
268435460.0,
268435460.0,
5.25,
))));
let v2 = i32x4::from(unsafe {
vec_cts::<1>(transmute(f32x4::new(
-1073741800.0,
1073741800.0,
1073741800.0,
21.0,
)))
});
let v4 = i32x4::from(unsafe {
vec_cts::<2>(transmute(f32x4::new(
-536870900.0,
536870900.0,
536870900.0,
10.5,
)))
});
let v8 = i32x4::from(unsafe {
vec_cts::<3>(transmute(f32x4::new(
-268435460.0,
268435460.0,
268435460.0,
5.25,
)))
});
assert_eq!(v2, v);
assert_eq!(v4, v);

34
library/stdarch/crates/core_arch/src/powerpc/vsx.rs
View file

@ -9,6 +9,7 @@
#![allow(non_camel_case_types)]
use crate::core_arch::powerpc::*;
use crate::core_arch::simd::*;
#[cfg(test)]
use stdarch_test::assert_instr;
@ -34,6 +35,22 @@ types! {
// pub struct vector_unsigned___int128 = i128x1;
}
#[unstable(feature = "stdarch_powerpc", issue = "111145")]
impl From<m64x2> for vector_bool_long {
#[inline]
fn from(value: m64x2) -> Self {
unsafe { transmute(value) }
}
}
#[unstable(feature = "stdarch_powerpc", issue = "111145")]
impl From<vector_bool_long> for m64x2 {
#[inline]
fn from(value: vector_bool_long) -> Self {
unsafe { transmute(value) }
}
}
#[allow(improper_ctypes)]
unsafe extern "C" {
#[link_name = "llvm.ppc.altivec.vperm"]
@ -46,7 +63,6 @@ unsafe extern "C" {
mod sealed {
use super::*;
use crate::core_arch::simd::*;
#[unstable(feature = "stdarch_powerpc", issue = "111145")]
pub trait VectorPermDI {
@ -221,14 +237,16 @@ mod tests {
macro_rules! test_vec_xxpermdi {
{$name:ident, $shorttype:ident, $longtype:ident, [$($a:expr),+], [$($b:expr),+], [$($c:expr),+], [$($d:expr),+]} => {
#[simd_test(enable = "vsx")]
unsafe fn $name() {
let a: $longtype = transmute($shorttype::new($($a),+, $($b),+));
let b = transmute($shorttype::new($($c),+, $($d),+));
fn $name() {
let a = $longtype::from($shorttype::new($($a),+, $($b),+));
let b = $longtype::from($shorttype::new($($c),+, $($d),+));
assert_eq!($shorttype::new($($a),+, $($c),+), transmute(vec_xxpermdi::<_, 0>(a, b)));
assert_eq!($shorttype::new($($b),+, $($c),+), transmute(vec_xxpermdi::<_, 1>(a, b)));
assert_eq!($shorttype::new($($a),+, $($d),+), transmute(vec_xxpermdi::<_, 2>(a, b)));
assert_eq!($shorttype::new($($b),+, $($d),+), transmute(vec_xxpermdi::<_, 3>(a, b)));
unsafe {
assert_eq!($shorttype::new($($a),+, $($c),+), $shorttype::from(vec_xxpermdi::<_, 0>(a, b)));
assert_eq!($shorttype::new($($b),+, $($c),+), $shorttype::from(vec_xxpermdi::<_, 1>(a, b)));
assert_eq!($shorttype::new($($a),+, $($d),+), $shorttype::from(vec_xxpermdi::<_, 2>(a, b)));
assert_eq!($shorttype::new($($b),+, $($d),+), $shorttype::from(vec_xxpermdi::<_, 3>(a, b)));
}
}
}
}

5
library/stdarch/crates/core_arch/src/s390x/mod.rs
View file

@ -2,6 +2,11 @@
pub(crate) mod macros;
/// the float and vector registers overlap therefore we cannot use any vector
/// extensions if softfloat is enabled.
#[cfg(not(target_abi = "softfloat"))]
mod vector;
#[cfg(not(target_abi = "softfloat"))]
#[unstable(feature = "stdarch_s390x", issue = "130869")]
pub use self::vector::*;

135
library/stdarch/crates/core_arch/src/s390x/vector.rs
View file

@ -51,6 +51,54 @@ types! {
pub struct vector_double(2 x f64);
}
#[unstable(feature = "stdarch_s390x", issue = "135681")]
impl From<m8x16> for vector_bool_char {
#[inline]
fn from(value: m8x16) -> Self {
unsafe { transmute(value) }
}
}
#[unstable(feature = "stdarch_s390x", issue = "135681")]
impl From<vector_bool_char> for m8x16 {
#[inline]
fn from(value: vector_bool_char) -> Self {
unsafe { transmute(value) }
}
}
#[unstable(feature = "stdarch_s390x", issue = "135681")]
impl From<m16x8> for vector_bool_short {
#[inline]
fn from(value: m16x8) -> Self {
unsafe { transmute(value) }
}
}
#[unstable(feature = "stdarch_s390x", issue = "135681")]
impl From<vector_bool_short> for m16x8 {
#[inline]
fn from(value: vector_bool_short) -> Self {
unsafe { transmute(value) }
}
}
#[unstable(feature = "stdarch_s390x", issue = "135681")]
impl From<m32x4> for vector_bool_int {
#[inline]
fn from(value: m32x4) -> Self {
unsafe { transmute(value) }
}
}
#[unstable(feature = "stdarch_s390x", issue = "135681")]
impl From<vector_bool_int> for m32x4 {
#[inline]
fn from(value: vector_bool_int) -> Self {
unsafe { transmute(value) }
}
}
#[repr(C, packed)]
struct PackedTuple<T, U> {
x: T,
@ -6051,27 +6099,16 @@ mod tests {
}
macro_rules! test_vec_1 {
{ $name: ident, $fn:ident, f32x4, [$($a:expr),+], ~[$($d:expr),+] } => {
#[simd_test(enable = "vector")]
unsafe fn $name() {
let a: vector_float = transmute(f32x4::new($($a),+));
let d: vector_float = transmute(f32x4::new($($d),+));
let r = transmute(vec_cmple(vec_abs(vec_sub($fn(a), d)), vec_splats(f32::EPSILON)));
let e = m32x4::new(true, true, true, true);
assert_eq!(e, r);
}
};
{ $name: ident, $fn:ident, $ty: ident, [$($a:expr),+], [$($d:expr),+] } => {
test_vec_1! { $name, $fn, $ty -> $ty, [$($a),+], [$($d),+] }
};
{ $name: ident, $fn:ident, $ty: ident -> $ty_out: ident, [$($a:expr),+], [$($d:expr),+] } => {
#[simd_test(enable = "vector")]
unsafe fn $name() {
let a: s_t_l!($ty) = transmute($ty::new($($a),+));
fn $name() {
let a: s_t_l!($ty) = $ty::new($($a),+).into();
let d = $ty_out::new($($d),+);
let r : $ty_out = transmute($fn(a));
let r = $ty_out::from(unsafe { $fn(a) });
assert_eq!(d, r);
}
}
@ -6086,35 +6123,23 @@ mod tests {
};
{ $name: ident, $fn:ident, $ty1: ident, $ty2: ident -> $ty_out: ident, [$($a:expr),+], [$($b:expr),+], [$($d:expr),+] } => {
#[simd_test(enable = "vector")]
unsafe fn $name() {
let a: s_t_l!($ty1) = transmute($ty1::new($($a),+));
let b: s_t_l!($ty2) = transmute($ty2::new($($b),+));
fn $name() {
let a: s_t_l!($ty1) = $ty1::new($($a),+).into();
let b: s_t_l!($ty2) = $ty2::new($($b),+).into();
let d = $ty_out::new($($d),+);
let r : $ty_out = transmute($fn(a, b));
let r = $ty_out::from(unsafe { $fn(a, b) });
assert_eq!(d, r);
}
};
{ $name: ident, $fn:ident, $ty: ident -> $ty_out: ident, [$($a:expr),+], [$($b:expr),+], $d:expr } => {
#[simd_test(enable = "vector")]
unsafe fn $name() {
let a: s_t_l!($ty) = transmute($ty::new($($a),+));
let b: s_t_l!($ty) = transmute($ty::new($($b),+));
let r : $ty_out = transmute($fn(a, b));
assert_eq!($d, r);
}
}
}
#[simd_test(enable = "vector")]
unsafe fn vec_add_i32x4_i32x4() {
let x = i32x4::new(1, 2, 3, 4);
let y = i32x4::new(4, 3, 2, 1);
let x: vector_signed_int = transmute(x);
let y: vector_signed_int = transmute(y);
let z = vec_add(x, y);
assert_eq!(i32x4::splat(5), transmute(z));
fn vec_add_i32x4_i32x4() {
let x = vector_signed_int::from(i32x4::new(1, 2, 3, 4));
let y = vector_signed_int::from(i32x4::new(4, 3, 2, 1));
let z = unsafe { vec_add(x, y) };
assert_eq!(i32x4::splat(5), i32x4::from(z));
}
macro_rules! test_vec_sub {
@ -6232,11 +6257,11 @@ mod tests {
macro_rules! test_vec_abs {
{ $name: ident, $ty: ident, $a: expr, $d: expr } => {
#[simd_test(enable = "vector")]
unsafe fn $name() {
let a: s_t_l!($ty) = vec_splats($a);
let a: s_t_l!($ty) = vec_abs(a);
fn $name() {
let a: s_t_l!($ty) = unsafe { vec_splats($a) };
let a: s_t_l!($ty) = unsafe { vec_abs(a) };
let d = $ty::splat($d);
assert_eq!(d, transmute(a));
assert_eq!(d, $ty::from(a));
}
}
}
@ -6386,7 +6411,7 @@ mod tests {
[0, 0, 0, 1, 0, 0, 0, 2, 0, 0, 0, 3, 0, 0, 0, 16],
[4, 2, 1, 8] }
test_vec_2! { test_vec_sral_pos, vec_sral, u32x4, u8x16 -> i32x4,
test_vec_2! { test_vec_sral_pos, vec_sral, u32x4, u8x16 -> u32x4,
[0b1000, 0b1000, 0b1000, 0b1000],
[0, 0, 0, 1, 0, 0, 0, 2, 0, 0, 0, 3, 0, 0, 0, 16],
[4, 2, 1, 8] }
@ -6423,13 +6448,13 @@ mod tests {
$shorttype:ident, $longtype:ident,
[$($a:expr),+], [$($b:expr),+], [$($c:expr),+], [$($d:expr),+]} => {
#[simd_test(enable = "vector")]
unsafe fn $name() {
let a: $longtype = transmute($shorttype::new($($a),+));
let b: $longtype = transmute($shorttype::new($($b),+));
let c: vector_unsigned_char = transmute(u8x16::new($($c),+));
fn $name() {
let a = $longtype::from($shorttype::new($($a),+));
let b = $longtype::from($shorttype::new($($b),+));
let c = vector_unsigned_char::from(u8x16::new($($c),+));
let d = $shorttype::new($($d),+);
let r: $shorttype = transmute(vec_perm(a, b, c));
let r = $shorttype::from(unsafe { vec_perm(a, b, c) });
assert_eq!(d, r);
}
}
@ -6512,46 +6537,46 @@ mod tests {
[core::f32::consts::PI, 1.0, 25.0, 2.0],
[core::f32::consts::PI.sqrt(), 1.0, 5.0, core::f32::consts::SQRT_2] }
test_vec_2! { test_vec_find_any_eq, vec_find_any_eq, i32x4, i32x4 -> u32x4,
test_vec_2! { test_vec_find_any_eq, vec_find_any_eq, i32x4, i32x4 -> i32x4,
[1, -2, 3, -4],
[-5, 3, -7, 8],
[0, 0, 0xFFFFFFFF, 0]
[0, 0, !0, 0]
}
test_vec_2! { test_vec_find_any_ne, vec_find_any_ne, i32x4, i32x4 -> u32x4,
test_vec_2! { test_vec_find_any_ne, vec_find_any_ne, i32x4, i32x4 -> i32x4,
[1, -2, 3, -4],
[-5, 3, -7, 8],
[0xFFFFFFFF, 0xFFFFFFFF, 0, 0xFFFFFFFF]
[!0, !0, 0, !0]
}
test_vec_2! { test_vec_find_any_eq_idx_1, vec_find_any_eq_idx, i32x4, i32x4 -> u32x4,
test_vec_2! { test_vec_find_any_eq_idx_1, vec_find_any_eq_idx, i32x4, i32x4 -> i32x4,
[1, 2, 3, 4],
[5, 3, 7, 8],
[0, 8, 0, 0]
}
test_vec_2! { test_vec_find_any_eq_idx_2, vec_find_any_eq_idx, i32x4, i32x4 -> u32x4,
test_vec_2! { test_vec_find_any_eq_idx_2, vec_find_any_eq_idx, i32x4, i32x4 -> i32x4,
[1, 2, 3, 4],
[5, 6, 7, 8],
[0, 16, 0, 0]
}
test_vec_2! { test_vec_find_any_ne_idx_1, vec_find_any_ne_idx, i32x4, i32x4 -> u32x4,
test_vec_2! { test_vec_find_any_ne_idx_1, vec_find_any_ne_idx, i32x4, i32x4 -> i32x4,
[1, 2, 3, 4],
[1, 5, 3, 4],
[0, 4, 0, 0]
}
test_vec_2! { test_vec_find_any_ne_idx_2, vec_find_any_ne_idx, i32x4, i32x4 -> u32x4,
test_vec_2! { test_vec_find_any_ne_idx_2, vec_find_any_ne_idx, i32x4, i32x4 -> i32x4,
[1, 2, 3, 4],
[1, 2, 3, 4],
[0, 16, 0, 0]
}
test_vec_2! { test_vec_find_any_eq_or_0_idx_1, vec_find_any_eq_or_0_idx, i32x4, i32x4 -> u32x4,
test_vec_2! { test_vec_find_any_eq_or_0_idx_1, vec_find_any_eq_or_0_idx, i32x4, i32x4 -> i32x4,
[1, 2, 0, 4],
[5, 6, 7, 8],
[0, 8, 0, 0]
}
test_vec_2! { test_vec_find_any_ne_or_0_idx_1, vec_find_any_ne_or_0_idx, i32x4, i32x4 -> u32x4,
test_vec_2! { test_vec_find_any_ne_or_0_idx_1, vec_find_any_ne_or_0_idx, i32x4, i32x4 -> i32x4,
[1, 2, 0, 4],
[1, 2, 3, 4],
[0, 8, 0, 0]

72
library/stdarch/crates/core_arch/src/wasm32/simd128.rs
View file

@ -86,10 +86,6 @@ unsafe extern "unadjusted" {
fn llvm_i8x16_all_true(x: simd::i8x16) -> i32;
#[link_name = "llvm.wasm.bitmask.v16i8"]
fn llvm_bitmask_i8x16(a: simd::i8x16) -> i32;
#[link_name = "llvm.wasm.narrow.signed.v16i8.v8i16"]
fn llvm_narrow_i8x16_s(a: simd::i16x8, b: simd::i16x8) -> simd::i8x16;
#[link_name = "llvm.wasm.narrow.unsigned.v16i8.v8i16"]
fn llvm_narrow_i8x16_u(a: simd::i16x8, b: simd::i16x8) -> simd::i8x16;
#[link_name = "llvm.wasm.avgr.unsigned.v16i8"]
fn llvm_avgr_u_i8x16(a: simd::i8x16, b: simd::i8x16) -> simd::i8x16;
@ -103,10 +99,6 @@ unsafe extern "unadjusted" {
fn llvm_i16x8_all_true(x: simd::i16x8) -> i32;
#[link_name = "llvm.wasm.bitmask.v8i16"]
fn llvm_bitmask_i16x8(a: simd::i16x8) -> i32;
#[link_name = "llvm.wasm.narrow.signed.v8i16.v4i32"]
fn llvm_narrow_i16x8_s(a: simd::i32x4, b: simd::i32x4) -> simd::i16x8;
#[link_name = "llvm.wasm.narrow.unsigned.v8i16.v4i32"]
fn llvm_narrow_i16x8_u(a: simd::i32x4, b: simd::i32x4) -> simd::i16x8;
#[link_name = "llvm.wasm.avgr.unsigned.v8i16"]
fn llvm_avgr_u_i16x8(a: simd::i16x8, b: simd::i16x8) -> simd::i16x8;
@ -2281,7 +2273,23 @@ pub use i8x16_bitmask as u8x16_bitmask;
#[doc(alias("i8x16.narrow_i16x8_s"))]
#[stable(feature = "wasm_simd", since = "1.54.0")]
pub fn i8x16_narrow_i16x8(a: v128, b: v128) -> v128 {
unsafe { llvm_narrow_i8x16_s(a.as_i16x8(), b.as_i16x8()).v128() }
unsafe {
let v: simd::i16x16 = simd_shuffle!(
a.as_i16x8(),
b.as_i16x8(),
[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
);
let max = simd_splat(i16::from(i8::MAX));
let min = simd_splat(i16::from(i8::MIN));
let v = simd_select(simd_gt::<_, simd::i16x16>(v, max), max, v);
let v = simd_select(simd_lt::<_, simd::i16x16>(v, min), min, v);
let v: simd::i8x16 = simd_cast(v);
v.v128()
}
}
/// Converts two input vectors into a smaller lane vector by narrowing each
@ -2295,7 +2303,23 @@ pub fn i8x16_narrow_i16x8(a: v128, b: v128) -> v128 {
#[doc(alias("i8x16.narrow_i16x8_u"))]
#[stable(feature = "wasm_simd", since = "1.54.0")]
pub fn u8x16_narrow_i16x8(a: v128, b: v128) -> v128 {
unsafe { llvm_narrow_i8x16_u(a.as_i16x8(), b.as_i16x8()).v128() }
unsafe {
let v: simd::i16x16 = simd_shuffle!(
a.as_i16x8(),
b.as_i16x8(),
[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
);
let max = simd_splat(i16::from(u8::MAX));
let min = simd_splat(i16::from(u8::MIN));
let v = simd_select(simd_gt::<_, simd::i16x16>(v, max), max, v);
let v = simd_select(simd_lt::<_, simd::i16x16>(v, min), min, v);
let v: simd::u8x16 = simd_cast(v);
v.v128()
}
}
/// Shifts each lane to the left by the specified number of bits.
@ -2593,7 +2617,19 @@ pub use i16x8_bitmask as u16x8_bitmask;
#[doc(alias("i16x8.narrow_i32x4_s"))]
#[stable(feature = "wasm_simd", since = "1.54.0")]
pub fn i16x8_narrow_i32x4(a: v128, b: v128) -> v128 {
unsafe { llvm_narrow_i16x8_s(a.as_i32x4(), b.as_i32x4()).v128() }
unsafe {
let v: simd::i32x8 = simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]);
let max = simd_splat(i32::from(i16::MAX));
let min = simd_splat(i32::from(i16::MIN));
let v = simd_select(simd_gt::<_, simd::i32x8>(v, max), max, v);
let v = simd_select(simd_lt::<_, simd::i32x8>(v, min), min, v);
let v: simd::i16x8 = simd_cast(v);
v.v128()
}
}
/// Converts two input vectors into a smaller lane vector by narrowing each
@ -2607,7 +2643,19 @@ pub fn i16x8_narrow_i32x4(a: v128, b: v128) -> v128 {
#[doc(alias("i16x8.narrow_i32x4_u"))]
#[stable(feature = "wasm_simd", since = "1.54.0")]
pub fn u16x8_narrow_i32x4(a: v128, b: v128) -> v128 {
unsafe { llvm_narrow_i16x8_u(a.as_i32x4(), b.as_i32x4()).v128() }
unsafe {
let v: simd::i32x8 = simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]);
let max = simd_splat(i32::from(u16::MAX));
let min = simd_splat(i32::from(u16::MIN));
let v = simd_select(simd_gt::<_, simd::i32x8>(v, max), max, v);
let v = simd_select(simd_lt::<_, simd::i32x8>(v, min), min, v);
let v: simd::u16x8 = simd_cast(v);
v.v128()
}
}
/// Converts low half of the smaller lane vector to a larger lane

1
library/stdarch/crates/core_arch/src/x86/avx.rs
View file

@ -2426,7 +2426,6 @@ pub const fn _mm256_setzero_si256() -> __m256i {
#[inline]
#[target_feature(enable = "avx")]
// This intrinsic has no corresponding instruction.
#[cfg_attr(test, assert_instr(vinsertf128))]
#[stable(feature = "simd_x86", since = "1.27.0")]
#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
pub const fn _mm256_set_pd(a: f64, b: f64, c: f64, d: f64) -> __m256d {

56
library/stdarch/crates/core_arch/src/x86/avx2.rs
View file

@ -991,7 +991,21 @@ pub const fn _mm256_hadd_epi32(a: __m256i, b: __m256i) -> __m256i {
#[cfg_attr(test, assert_instr(vphaddsw))]
#[stable(feature = "simd_x86", since = "1.27.0")]
pub fn _mm256_hadds_epi16(a: __m256i, b: __m256i) -> __m256i {
unsafe { transmute(phaddsw(a.as_i16x16(), b.as_i16x16())) }
let a = a.as_i16x16();
let b = b.as_i16x16();
unsafe {
let even: i16x16 = simd_shuffle!(
a,
b,
[0, 2, 4, 6, 16, 18, 20, 22, 8, 10, 12, 14, 24, 26, 28, 30]
);
let odd: i16x16 = simd_shuffle!(
a,
b,
[1, 3, 5, 7, 17, 19, 21, 23, 9, 11, 13, 15, 25, 27, 29, 31]
);
simd_saturating_add(even, odd).as_m256i()
}
}
/// Horizontally subtract adjacent pairs of 16-bit integers in `a` and `b`.
@ -1047,7 +1061,21 @@ pub const fn _mm256_hsub_epi32(a: __m256i, b: __m256i) -> __m256i {
#[cfg_attr(test, assert_instr(vphsubsw))]
#[stable(feature = "simd_x86", since = "1.27.0")]
pub fn _mm256_hsubs_epi16(a: __m256i, b: __m256i) -> __m256i {
unsafe { transmute(phsubsw(a.as_i16x16(), b.as_i16x16())) }
let a = a.as_i16x16();
let b = b.as_i16x16();
unsafe {
let even: i16x16 = simd_shuffle!(
a,
b,
[0, 2, 4, 6, 16, 18, 20, 22, 8, 10, 12, 14, 24, 26, 28, 30]
);
let odd: i16x16 = simd_shuffle!(
a,
b,
[1, 3, 5, 7, 17, 19, 21, 23, 9, 11, 13, 15, 25, 27, 29, 31]
);
simd_saturating_sub(even, odd).as_m256i()
}
}
/// Returns values from `slice` at offsets determined by `offsets * scale`,
@ -3791,10 +3819,6 @@ pub const fn _mm256_extract_epi16<const INDEX: i32>(a: __m256i) -> i32 {
#[allow(improper_ctypes)]
unsafe extern "C" {
#[link_name = "llvm.x86.avx2.phadd.sw"]
fn phaddsw(a: i16x16, b: i16x16) -> i16x16;
#[link_name = "llvm.x86.avx2.phsub.sw"]
fn phsubsw(a: i16x16, b: i16x16) -> i16x16;
#[link_name = "llvm.x86.avx2.pmadd.wd"]
fn pmaddwd(a: i16x16, b: i16x16) -> i32x8;
#[link_name = "llvm.x86.avx2.pmadd.ub.sw"]
@ -4653,6 +4677,26 @@ mod tests {
assert_eq_m256i(r, e);
}
#[target_feature(enable = "avx2")]
#[cfg_attr(test, assert_instr(vpmaddwd))]
unsafe fn test_mm256_madd_epi16_mul_one(v: __m256i) -> __m256i {
// This is a trick used in the adler32 algorithm to get a widening addition. The
// multiplication by 1 is trivial, but must not be optimized out because then the vpmaddwd
// instruction is no longer selected. The assert_instr verifies that this is the case.
let one_v = _mm256_set1_epi16(1);
_mm256_madd_epi16(v, one_v)
}
#[target_feature(enable = "avx2")]
#[cfg_attr(test, assert_instr(vpmaddwd))]
unsafe fn test_mm256_madd_epi16_shl(v: __m256i) -> __m256i {
// This is a trick used in the base64 algorithm to get a widening addition. Instead of a
// multiplication, a vector shl is used. In LLVM 22 that breaks the pattern recognition
// for the automatic optimization to vpmaddwd.
let shift_value = _mm256_set1_epi32(12i32);
_mm256_madd_epi16(v, shift_value)
}
#[simd_test(enable = "avx2")]
const fn test_mm256_inserti128_si256() {
let a = _mm256_setr_epi64x(1, 2, 3, 4);

2
library/stdarch/crates/core_arch/src/x86/sse.rs
View file

@ -968,7 +968,7 @@ pub const fn _mm_set_ps1(a: f32) -> __m128 {
/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_set_ps)
#[inline]
#[target_feature(enable = "sse")]
#[cfg_attr(test, assert_instr(unpcklps))]
// This intrinsic has no corresponding instruction.
#[stable(feature = "simd_x86", since = "1.27.0")]
#[rustc_const_unstable(feature = "stdarch_const_x86", issue = "149298")]
pub const fn _mm_set_ps(a: f32, b: f32, c: f32, d: f32) -> __m128 {

22
library/stdarch/crates/core_arch/src/x86/ssse3.rs
View file

@ -188,7 +188,13 @@ pub const fn _mm_hadd_epi16(a: __m128i, b: __m128i) -> __m128i {
#[cfg_attr(test, assert_instr(phaddsw))]
#[stable(feature = "simd_x86", since = "1.27.0")]
pub fn _mm_hadds_epi16(a: __m128i, b: __m128i) -> __m128i {
unsafe { transmute(phaddsw128(a.as_i16x8(), b.as_i16x8())) }
let a = a.as_i16x8();
let b = b.as_i16x8();
unsafe {
let even: i16x8 = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]);
let odd: i16x8 = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]);
simd_saturating_add(even, odd).as_m128i()
}
}
/// Horizontally adds the adjacent pairs of values contained in 2 packed
@ -240,7 +246,13 @@ pub const fn _mm_hsub_epi16(a: __m128i, b: __m128i) -> __m128i {
#[cfg_attr(test, assert_instr(phsubsw))]
#[stable(feature = "simd_x86", since = "1.27.0")]
pub fn _mm_hsubs_epi16(a: __m128i, b: __m128i) -> __m128i {
unsafe { transmute(phsubsw128(a.as_i16x8(), b.as_i16x8())) }
let a = a.as_i16x8();
let b = b.as_i16x8();
unsafe {
let even: i16x8 = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]);
let odd: i16x8 = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]);
simd_saturating_sub(even, odd).as_m128i()
}
}
/// Horizontally subtract the adjacent pairs of values contained in 2
@ -337,12 +349,6 @@ unsafe extern "C" {
#[link_name = "llvm.x86.ssse3.pshuf.b.128"]
fn pshufb128(a: u8x16, b: u8x16) -> u8x16;
#[link_name = "llvm.x86.ssse3.phadd.sw.128"]
fn phaddsw128(a: i16x8, b: i16x8) -> i16x8;
#[link_name = "llvm.x86.ssse3.phsub.sw.128"]
fn phsubsw128(a: i16x8, b: i16x8) -> i16x8;
#[link_name = "llvm.x86.ssse3.pmadd.ub.sw.128"]
fn pmaddubsw128(a: u8x16, b: i8x16) -> i16x8;

8
library/stdarch/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml
View file

@ -8958,7 +8958,7 @@ intrinsics:
arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"]
return_type: "{neon_type[2]}"
attr:
- FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [mov, 'LANE1 = 0', 'LANE2 = 1']]}]]
- FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [mov, 'LANE1 = 0', 'LANE2 = 0']]}]]
- FnCall: [rustc_legacy_const_generics, ['1', '3']]
- FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
static_defs: ['const LANE1: i32, const LANE2: i32']
@ -8983,7 +8983,7 @@ intrinsics:
arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"]
return_type: "{neon_type[2]}"
attr:
- FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [mov, 'LANE1 = 0', 'LANE2 = 1']]}]]
- FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [mov, 'LANE1 = 0', 'LANE2 = 0']]}]]
- FnCall: [rustc_legacy_const_generics, ['1', '3']]
- FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
static_defs: ['const LANE1: i32, const LANE2: i32']
@ -9008,7 +9008,7 @@ intrinsics:
arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"]
return_type: "{neon_type[2]}"
attr:
- FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [mov, 'LANE1 = 0', 'LANE2 = 1']]}]]
- FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [mov, 'LANE1 = 0', 'LANE2 = 0']]}]]
- FnCall: [rustc_legacy_const_generics, ['1', '3']]
- FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
static_defs: ['const LANE1: i32, const LANE2: i32']
@ -9037,7 +9037,7 @@ intrinsics:
arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"]
return_type: "{neon_type[2]}"
attr:
- FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [mov, 'LANE1 = 0', 'LANE2 = 1']]}]]
- FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [mov, 'LANE1 = 0', 'LANE2 = 0']]}]]
- FnCall: [rustc_legacy_const_generics, ['1', '3']]
- FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
static_defs: ['const LANE1: i32, const LANE2: i32']

2
library/stdarch/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml
View file

@ -2681,6 +2681,7 @@ intrinsics:
- FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [ld1]]}]]
- *neon-not-arm-stable
- *neon-cfg-arm-unstable
big_endian_inverse: false
safety:
unsafe: [neon]
types:
@ -2740,6 +2741,7 @@ intrinsics:
- FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [ld1]]}]]
- *neon-not-arm-stable
- *neon-cfg-arm-unstable
big_endian_inverse: false
safety:
unsafe: [neon]
types:

1
library/stdarch/crates/stdarch-gen-arm/src/main.rs
View file

@ -139,6 +139,7 @@ fn parse_args() -> Vec<(PathBuf, Option<PathBuf>)> {
.into_iter()
.filter_map(Result::ok)
.filter(|f| f.file_type().is_file())
.filter(|f| f.file_name().to_string_lossy().ends_with(".yml"))
.map(|f| (f.into_path(), out_dir.clone()))
.collect()
}

2
library/stdarch/rust-version
View file

@ -1 +1 @@
873d4682c7d285540b8f28bfe637006cef8918a6
db3e99bbab28c6ca778b13222becdea54533d908