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Rollup merge of #50819 - cjkenn:cjkenn/div-by-zero, r=kennytm

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Fix potential divide by zero

This should fix #50761

I had trouble reproducing with the provided code, but looking at the stack trace would indicate that this code is the likely cause. I made a number of assumptions here, because I don't have enough context on how the register size is set:

1. I assumed `rest.unit.size.bytes()` can be 0, and it's ok if it's set to 0 before this function is called
2. I assumed that if `rest.unit.size.bytes()` is 0, that we want `rest_count` to also be 0.
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kennytm 2018-05-20 04:17:41 +08:00
commit e1f031e5d4
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2 changed files with 39 additions and 2 deletions
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8
src/librustc_codegen_llvm/abi.rs
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@ -127,8 +127,12 @@ impl LlvmType for Reg {
impl LlvmType for CastTarget {
fn llvm_type(&self, cx: &CodegenCx) -> Type {
let rest_ll_unit = self.rest.unit.llvm_type(cx);
let rest_count = self.rest.total.bytes() / self.rest.unit.size.bytes();
let rem_bytes = self.rest.total.bytes() % self.rest.unit.size.bytes();
let (rest_count, rem_bytes) = if self.rest.unit.size.bytes() == 0 {
(0, 0)
} else {
(self.rest.total.bytes() / self.rest.unit.size.bytes(),
self.rest.total.bytes() % self.rest.unit.size.bytes())
};
if self.prefix.iter().all(|x| x.is_none()) {
// Simplify to a single unit when there is no prefix and size <= unit size