diff --git a/library/stdarch/intrinsics_data/arm_intrinsics.json b/library/stdarch/intrinsics_data/arm_intrinsics.json index a46356493234..754c8f909aef 100644 --- a/library/stdarch/intrinsics_data/arm_intrinsics.json +++ b/library/stdarch/intrinsics_data/arm_intrinsics.json @@ -1003,6 +1003,34 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vabd_f16", + "arguments": [ + "float16x4_t a", + "float16x4_t b" + ], + "return_type": { + "value": "float16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.4H" + }, + "b": { + "register": "Vm.4H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FABD" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vabd_f32", @@ -1260,6 +1288,33 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vabdh_f16", + "arguments": [ + "float16_t a", + "float16_t b" + ], + "return_type": { + "value": "float16_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Hn" + }, + "b": { + "register": "Hm" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FABD" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vabdl_high_s16", @@ -1596,6 +1651,34 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vabdq_f16", + "arguments": [ + "float16x8_t a", + "float16x8_t b" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + }, + "b": { + "register": "Vm.8H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FABD" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vabdq_f32", @@ -1853,6 +1936,30 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vabs_f16", + "arguments": [ + "float16x4_t a" + ], + "return_type": { + "value": "float16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.4H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FABS" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vabs_f32", @@ -2022,6 +2129,54 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vabsh_f16", + "arguments": [ + "float16_t a" + ], + "return_type": { + "value": "float16_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Hn" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FABS" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vabsq_f16", + "arguments": [ + "float16x8_t a" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FABS" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vabsq_f32", @@ -2168,6 +2323,34 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vadd_f16", + "arguments": [ + "float16x4_t a", + "float16x4_t b" + ], + "return_type": { + "value": "float16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.4H" + }, + "b": { + "register": "Vm.4H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FADD" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vadd_f32", @@ -2597,6 +2780,34 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vaddh_f16", + "arguments": [ + "float16_t a", + "float16_t b" + ], + "return_type": { + "value": "float16_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Hn" + }, + "b": { + "register": "Hm" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FADD" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vaddhn_high_s16", @@ -3569,6 +3780,34 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vaddq_f16", + "arguments": [ + "float16x8_t a", + "float16x8_t b" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + }, + "b": { + "register": "Vm.8H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FADD" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vaddq_f32", @@ -5949,6 +6188,39 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vbsl_f16", + "arguments": [ + "uint16x4_t a", + "float16x4_t b", + "float16x4_t c" + ], + "return_type": { + "value": "float16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vd.8B" + }, + "b": { + "register": "Vn.8B" + }, + "c": { + "register": "Vm.8B" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "BSL" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vbsl_f32", @@ -6375,6 +6647,39 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vbslq_f16", + "arguments": [ + "uint16x8_t a", + "float16x8_t b", + "float16x8_t c" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vd.16B" + }, + "b": { + "register": "Vn.16B" + }, + "c": { + "register": "Vm.16B" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "BSL" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vbslq_f32", @@ -6801,6 +7106,34 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vcadd_rot270_f16", + "arguments": [ + "float16x4_t a", + "float16x4_t b" + ], + "return_type": { + "value": "float16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.4H " + }, + "b": { + "register": "Vm.4H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FCADD" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vcadd_rot270_f32", @@ -6829,6 +7162,34 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vcadd_rot90_f16", + "arguments": [ + "float16x4_t a", + "float16x4_t b" + ], + "return_type": { + "value": "float16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.4H " + }, + "b": { + "register": "Vm.4H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FCADD" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vcadd_rot90_f32", @@ -6857,6 +7218,34 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vcaddq_rot270_f16", + "arguments": [ + "float16x8_t a", + "float16x8_t b" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H " + }, + "b": { + "register": "Vm.8H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FCADD" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vcaddq_rot270_f32", @@ -6912,6 +7301,34 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vcaddq_rot90_f16", + "arguments": [ + "float16x8_t a", + "float16x8_t b" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H " + }, + "b": { + "register": "Vm.8H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FCADD" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vcaddq_rot90_f32", @@ -6967,6 +7384,34 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vcage_f16", + "arguments": [ + "float16x4_t a", + "float16x4_t b" + ], + "return_type": { + "value": "uint16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.4H" + }, + "b": { + "register": "Vm.4H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FACGE" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vcage_f32", @@ -7050,6 +7495,61 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vcageh_f16", + "arguments": [ + "float16_t a", + "float16_t b" + ], + "return_type": { + "value": "uint16_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Hn" + }, + "b": { + "register": "Hm" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FACGE" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vcageq_f16", + "arguments": [ + "float16x8_t a", + "float16x8_t b" + ], + "return_type": { + "value": "uint16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + }, + "b": { + "register": "Vm.8H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FACGE" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vcageq_f32", @@ -7133,6 +7633,34 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vcagt_f16", + "arguments": [ + "float16x4_t a", + "float16x4_t b" + ], + "return_type": { + "value": "uint16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.4H" + }, + "b": { + "register": "Vm.4H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FACGT" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vcagt_f32", @@ -7216,6 +7744,61 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vcagth_f16", + "arguments": [ + "float16_t a", + "float16_t b" + ], + "return_type": { + "value": "uint16_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Hn" + }, + "b": { + "register": "Hm" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FACGT" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vcagtq_f16", + "arguments": [ + "float16x8_t a", + "float16x8_t b" + ], + "return_type": { + "value": "uint16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + }, + "b": { + "register": "Vm.8H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FACGT" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vcagtq_f32", @@ -7299,6 +7882,34 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vcale_f16", + "arguments": [ + "float16x4_t a", + "float16x4_t b" + ], + "return_type": { + "value": "uint16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.4H" + }, + "b": { + "register": "Vm.4H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FACGE" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vcale_f32", @@ -7382,6 +7993,61 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vcaleh_f16", + "arguments": [ + "float16_t a", + "float16_t b" + ], + "return_type": { + "value": "uint16_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Hn" + }, + "b": { + "register": "Hm" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FACGE" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vcaleq_f16", + "arguments": [ + "float16x8_t a", + "float16x8_t b" + ], + "return_type": { + "value": "uint16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + }, + "b": { + "register": "Vm.8H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FACGE" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vcaleq_f32", @@ -7465,6 +8131,34 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vcalt_f16", + "arguments": [ + "float16x4_t a", + "float16x4_t b" + ], + "return_type": { + "value": "uint16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.4H" + }, + "b": { + "register": "Vm.4H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FACGT" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vcalt_f32", @@ -7548,6 +8242,61 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vcalth_f16", + "arguments": [ + "float16_t a", + "float16_t b" + ], + "return_type": { + "value": "uint16_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Hn" + }, + "b": { + "register": "Hm" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FACGT" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vcaltq_f16", + "arguments": [ + "float16x8_t a", + "float16x8_t b" + ], + "return_type": { + "value": "uint16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + }, + "b": { + "register": "Vm.8H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FACGT" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vcaltq_f32", @@ -7631,6 +8380,34 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vceq_f16", + "arguments": [ + "float16x4_t a", + "float16x4_t b" + ], + "return_type": { + "value": "uint16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.4H" + }, + "b": { + "register": "Vm.4H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FCMEQ" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vceq_f32", @@ -8053,6 +8830,61 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vceqh_f16", + "arguments": [ + "float16_t a", + "float16_t b" + ], + "return_type": { + "value": "uint16_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Hn" + }, + "b": { + "register": "Hm" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCMEQ" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vceqq_f16", + "arguments": [ + "float16x8_t a", + "float16x8_t b" + ], + "return_type": { + "value": "uint16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + }, + "b": { + "register": "Vm.8H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FCMEQ" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vceqq_f32", @@ -8421,6 +9253,30 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vceqz_f16", + "arguments": [ + "float16x4_t a" + ], + "return_type": { + "value": "uint16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.4H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FCMEQ" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vceqz_f32", @@ -8767,6 +9623,53 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vceqzh_f16", + "arguments": [ + "float16_t a" + ], + "return_type": { + "value": "uint16_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Hn" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCMEQ" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vceqzq_f16", + "arguments": [ + "float16x8_t a" + ], + "return_type": { + "value": "uint16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FCMEQ" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vceqzq_f32", @@ -9067,6 +9970,34 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vcge_f16", + "arguments": [ + "float16x4_t a", + "float16x4_t b" + ], + "return_type": { + "value": "uint16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.4H" + }, + "b": { + "register": "Vm.4H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FCMGE" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vcge_f32", @@ -9432,6 +10363,61 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vcgeh_f16", + "arguments": [ + "float16_t a", + "float16_t b" + ], + "return_type": { + "value": "uint16_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Hn" + }, + "b": { + "register": "Hm" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCMGE" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vcgeq_f16", + "arguments": [ + "float16x8_t a", + "float16x8_t b" + ], + "return_type": { + "value": "uint16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + }, + "b": { + "register": "Vm.8H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FCMGE" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vcgeq_f32", @@ -9743,6 +10729,30 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vcgez_f16", + "arguments": [ + "float16x4_t a" + ], + "return_type": { + "value": "uint16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.4H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FCMGE" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vcgez_f32", @@ -9927,6 +10937,53 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vcgezh_f16", + "arguments": [ + "float16_t a" + ], + "return_type": { + "value": "uint16_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Hn" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCMGE" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vcgezq_f16", + "arguments": [ + "float16x8_t a" + ], + "return_type": { + "value": "uint16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FCMGE" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vcgezq_f32", @@ -10088,6 +11145,34 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vcgt_f16", + "arguments": [ + "float16x4_t a", + "float16x4_t b" + ], + "return_type": { + "value": "uint16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.4H" + }, + "b": { + "register": "Vm.4H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FCMGT" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vcgt_f32", @@ -10453,6 +11538,61 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vcgth_f16", + "arguments": [ + "float16_t a", + "float16_t b" + ], + "return_type": { + "value": "uint16_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Hn" + }, + "b": { + "register": "Hm" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCMGT" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vcgtq_f16", + "arguments": [ + "float16x8_t a", + "float16x8_t b" + ], + "return_type": { + "value": "uint16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + }, + "b": { + "register": "Vm.8H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FCMGT" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vcgtq_f32", @@ -10764,6 +11904,30 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vcgtz_f16", + "arguments": [ + "float16x4_t a" + ], + "return_type": { + "value": "uint16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.4H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FCMGT" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vcgtz_f32", @@ -10948,6 +12112,53 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vcgtzh_f16", + "arguments": [ + "float16_t a" + ], + "return_type": { + "value": "uint16_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Hn" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCMGT" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vcgtzq_f16", + "arguments": [ + "float16x8_t a" + ], + "return_type": { + "value": "uint16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FCMGT" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vcgtzq_f32", @@ -11109,6 +12320,34 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vcle_f16", + "arguments": [ + "float16x4_t a", + "float16x4_t b" + ], + "return_type": { + "value": "uint16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.4H" + }, + "b": { + "register": "Vm.4H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FCMGE" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vcle_f32", @@ -11474,6 +12713,61 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vcleh_f16", + "arguments": [ + "float16_t a", + "float16_t b" + ], + "return_type": { + "value": "uint16_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Hn" + }, + "b": { + "register": "Hm" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCMGE" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vcleq_f16", + "arguments": [ + "float16x8_t a", + "float16x8_t b" + ], + "return_type": { + "value": "uint16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + }, + "b": { + "register": "Vm.8H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FCMGE" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vcleq_f32", @@ -11785,6 +13079,30 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vclez_f16", + "arguments": [ + "float16x4_t a" + ], + "return_type": { + "value": "uint16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.4H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FCMLE" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vclez_f32", @@ -11969,6 +13287,53 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vclezh_f16", + "arguments": [ + "float16_t a" + ], + "return_type": { + "value": "uint16_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Hn" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCMLE" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vclezq_f16", + "arguments": [ + "float16x8_t a" + ], + "return_type": { + "value": "uint16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FCMLE" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vclezq_f32", @@ -12430,6 +13795,34 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vclt_f16", + "arguments": [ + "float16x4_t a", + "float16x4_t b" + ], + "return_type": { + "value": "uint16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.4H" + }, + "b": { + "register": "Vm.4H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FCMGT" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vclt_f32", @@ -12795,6 +14188,61 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vclth_f16", + "arguments": [ + "float16_t a", + "float16_t b" + ], + "return_type": { + "value": "uint16_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Hn" + }, + "b": { + "register": "Hm" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCMGT" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vcltq_f16", + "arguments": [ + "float16x8_t a", + "float16x8_t b" + ], + "return_type": { + "value": "uint16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + }, + "b": { + "register": "Vm.8H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FCMGT" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vcltq_f32", @@ -13106,6 +14554,30 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vcltz_f16", + "arguments": [ + "float16x4_t a" + ], + "return_type": { + "value": "uint16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.4H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FCMLT" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vcltz_f32", @@ -13290,6 +14762,53 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vcltzh_f16", + "arguments": [ + "float16_t a" + ], + "return_type": { + "value": "uint16_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Hn" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCMLT" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vcltzq_f16", + "arguments": [ + "float16x8_t a" + ], + "return_type": { + "value": "uint16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FCMLT" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vcltzq_f32", @@ -13751,6 +15270,34 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vcmla_f16", + "arguments": [ + "float16x4_t r", + "float16x4_t a", + "float16x4_t b" + ], + "return_type": { + "value": "float16x4_t" + }, + "Arguments_Preparation": { + "a": {}, + "b": {}, + "r": { + "register": "Vd.4H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FCMLA" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vcmla_f32", @@ -13779,6 +15326,39 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vcmla_lane_f16", + "arguments": [ + "float16x4_t r", + "float16x4_t a", + "float16x4_t b", + "const int lane" + ], + "return_type": { + "value": "float16x4_t" + }, + "Arguments_Preparation": { + "a": {}, + "b": {}, + "lane": { + "minimum": 0, + "maximum": 1 + }, + "r": { + "register": "Vd.4H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FCMLA" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vcmla_lane_f32", @@ -13812,6 +15392,39 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vcmla_laneq_f16", + "arguments": [ + "float16x4_t r", + "float16x4_t a", + "float16x8_t b", + "const int lane" + ], + "return_type": { + "value": "float16x4_t" + }, + "Arguments_Preparation": { + "a": {}, + "b": {}, + "lane": { + "minimum": 0, + "maximum": 1 + }, + "r": { + "register": "Vd.4H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FCMLA" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vcmla_laneq_f32", @@ -13846,6 +15459,34 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vcmla_rot180_f16", + "arguments": [ + "float16x4_t r", + "float16x4_t a", + "float16x4_t b" + ], + "return_type": { + "value": "float16x4_t" + }, + "Arguments_Preparation": { + "a": {}, + "b": {}, + "r": { + "register": "Vd.4H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FCMLA" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vcmla_rot180_f32", @@ -13874,6 +15515,39 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vcmla_rot180_lane_f16", + "arguments": [ + "float16x4_t r", + "float16x4_t a", + "float16x4_t b", + "const int lane" + ], + "return_type": { + "value": "float16x4_t" + }, + "Arguments_Preparation": { + "a": {}, + "b": {}, + "lane": { + "minimum": 0, + "maximum": 1 + }, + "r": { + "register": "Vd.4H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FCMLA" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vcmla_rot180_lane_f32", @@ -13907,6 +15581,39 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vcmla_rot180_laneq_f16", + "arguments": [ + "float16x4_t r", + "float16x4_t a", + "float16x8_t b", + "const int lane" + ], + "return_type": { + "value": "float16x4_t" + }, + "Arguments_Preparation": { + "a": {}, + "b": {}, + "lane": { + "minimum": 0, + "maximum": 1 + }, + "r": { + "register": "Vd.4H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FCMLA" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vcmla_rot180_laneq_f32", @@ -13941,6 +15648,34 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vcmla_rot270_f16", + "arguments": [ + "float16x4_t r", + "float16x4_t a", + "float16x4_t b" + ], + "return_type": { + "value": "float16x4_t" + }, + "Arguments_Preparation": { + "a": {}, + "b": {}, + "r": { + "register": "Vd.4H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FCMLA" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vcmla_rot270_f32", @@ -13969,6 +15704,39 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vcmla_rot270_lane_f16", + "arguments": [ + "float16x4_t r", + "float16x4_t a", + "float16x4_t b", + "const int lane" + ], + "return_type": { + "value": "float16x4_t" + }, + "Arguments_Preparation": { + "a": {}, + "b": {}, + "lane": { + "minimum": 0, + "maximum": 1 + }, + "r": { + "register": "Vd.4H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FCMLA" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vcmla_rot270_lane_f32", @@ -14002,6 +15770,39 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vcmla_rot270_laneq_f16", + "arguments": [ + "float16x4_t r", + "float16x4_t a", + "float16x8_t b", + "const int lane" + ], + "return_type": { + "value": "float16x4_t" + }, + "Arguments_Preparation": { + "a": {}, + "b": {}, + "lane": { + "minimum": 0, + "maximum": 1 + }, + "r": { + "register": "Vd.4H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FCMLA" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vcmla_rot270_laneq_f32", @@ -14036,6 +15837,34 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vcmla_rot90_f16", + "arguments": [ + "float16x4_t r", + "float16x4_t a", + "float16x4_t b" + ], + "return_type": { + "value": "float16x4_t" + }, + "Arguments_Preparation": { + "a": {}, + "b": {}, + "r": { + "register": "Vd.4H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FCMLA" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vcmla_rot90_f32", @@ -14064,6 +15893,39 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vcmla_rot90_lane_f16", + "arguments": [ + "float16x4_t r", + "float16x4_t a", + "float16x4_t b", + "const int lane" + ], + "return_type": { + "value": "float16x4_t" + }, + "Arguments_Preparation": { + "a": {}, + "b": {}, + "lane": { + "minimum": 0, + "maximum": 1 + }, + "r": { + "register": "Vd.4H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FCMLA" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vcmla_rot90_lane_f32", @@ -14097,6 +15959,39 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vcmla_rot90_laneq_f16", + "arguments": [ + "float16x4_t r", + "float16x4_t a", + "float16x8_t b", + "const int lane" + ], + "return_type": { + "value": "float16x4_t" + }, + "Arguments_Preparation": { + "a": {}, + "b": {}, + "lane": { + "minimum": 0, + "maximum": 1 + }, + "r": { + "register": "Vd.4H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FCMLA" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vcmla_rot90_laneq_f32", @@ -14131,6 +16026,34 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vcmlaq_f16", + "arguments": [ + "float16x8_t r", + "float16x8_t a", + "float16x8_t b" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "a": {}, + "b": {}, + "r": { + "register": "Vd.8H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FCMLA" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vcmlaq_f32", @@ -14186,6 +16109,39 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vcmlaq_lane_f16", + "arguments": [ + "float16x8_t r", + "float16x8_t a", + "float16x4_t b", + "const int lane" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "a": {}, + "b": {}, + "lane": { + "minimum": 0, + "maximum": 1 + }, + "r": { + "register": "Vd.8H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FCMLA" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vcmlaq_lane_f32", @@ -14219,6 +16175,39 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vcmlaq_laneq_f16", + "arguments": [ + "float16x8_t r", + "float16x8_t a", + "float16x8_t b", + "const int lane" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "a": {}, + "b": {}, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "r": { + "register": "Vd.8H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FCMLA" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vcmlaq_laneq_f32", @@ -14252,6 +16241,34 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vcmlaq_rot180_f16", + "arguments": [ + "float16x8_t r", + "float16x8_t a", + "float16x8_t b" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "a": {}, + "b": {}, + "r": { + "register": "Vd.8H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FCMLA" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vcmlaq_rot180_f32", @@ -14307,6 +16324,39 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vcmlaq_rot180_lane_f16", + "arguments": [ + "float16x8_t r", + "float16x8_t a", + "float16x4_t b", + "const int lane" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "a": {}, + "b": {}, + "lane": { + "minimum": 0, + "maximum": 1 + }, + "r": { + "register": "Vd.8H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FCMLA" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vcmlaq_rot180_lane_f32", @@ -14340,6 +16390,39 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vcmlaq_rot180_laneq_f16", + "arguments": [ + "float16x8_t r", + "float16x8_t a", + "float16x8_t b", + "const int lane" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "a": {}, + "b": {}, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "r": { + "register": "Vd.8H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FCMLA" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vcmlaq_rot180_laneq_f32", @@ -14373,6 +16456,34 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vcmlaq_rot270_f16", + "arguments": [ + "float16x8_t r", + "float16x8_t a", + "float16x8_t b" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "a": {}, + "b": {}, + "r": { + "register": "Vd.8H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FCMLA" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vcmlaq_rot270_f32", @@ -14428,6 +16539,39 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vcmlaq_rot270_lane_f16", + "arguments": [ + "float16x8_t r", + "float16x8_t a", + "float16x4_t b", + "const int lane" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "a": {}, + "b": {}, + "lane": { + "minimum": 0, + "maximum": 1 + }, + "r": { + "register": "Vd.8H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FCMLA" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vcmlaq_rot270_lane_f32", @@ -14461,6 +16605,39 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vcmlaq_rot270_laneq_f16", + "arguments": [ + "float16x8_t r", + "float16x8_t a", + "float16x8_t b", + "const int lane" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "a": {}, + "b": {}, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "r": { + "register": "Vd.8H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FCMLA" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vcmlaq_rot270_laneq_f32", @@ -14494,6 +16671,34 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vcmlaq_rot90_f16", + "arguments": [ + "float16x8_t r", + "float16x8_t a", + "float16x8_t b" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "a": {}, + "b": {}, + "r": { + "register": "Vd.8H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FCMLA" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vcmlaq_rot90_f32", @@ -14549,6 +16754,39 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vcmlaq_rot90_lane_f16", + "arguments": [ + "float16x8_t r", + "float16x8_t a", + "float16x4_t b", + "const int lane" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "a": {}, + "b": {}, + "lane": { + "minimum": 0, + "maximum": 1 + }, + "r": { + "register": "Vd.8H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FCMLA" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vcmlaq_rot90_lane_f32", @@ -14582,6 +16820,39 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vcmlaq_rot90_laneq_f16", + "arguments": [ + "float16x8_t r", + "float16x8_t a", + "float16x8_t b", + "const int lane" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "a": {}, + "b": {}, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "r": { + "register": "Vd.8H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FCMLA" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vcmlaq_rot90_laneq_f32", @@ -14765,6 +17036,36 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vcombine_f16", + "arguments": [ + "float16x4_t low", + "float16x4_t high" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "high": { + "register": "Vm.4H" + }, + "low": { + "register": "Vn.4H" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "DUP", + "INS" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vcombine_f32", @@ -17080,6 +19381,31 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vcreate_f16", + "arguments": [ + "uint64_t a" + ], + "return_type": { + "value": "float16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Xn" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "INS" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vcreate_f32", @@ -17402,6 +19728,104 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vcvt_f16_f32", + "arguments": [ + "float32x4_t a" + ], + "return_type": { + "value": "float16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.4S" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "FCVTN" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vcvt_f16_s16", + "arguments": [ + "int16x4_t a" + ], + "return_type": { + "value": "float16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.4H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "SCVTF" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vcvt_f16_u16", + "arguments": [ + "uint16x4_t a" + ], + "return_type": { + "value": "float16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.4H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "UCVTF" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vcvt_f32_f16", + "arguments": [ + "float16x4_t a" + ], + "return_type": { + "value": "float32x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.4H" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "FCVTL" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vcvt_f32_f64", @@ -17544,6 +19968,56 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vcvt_high_f16_f32", + "arguments": [ + "float16x4_t r", + "float32x4_t a" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.4S" + }, + "r": { + "register": "Vd.4H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCVTN2" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vcvt_high_f32_f16", + "arguments": [ + "float16x8_t a" + ], + "return_type": { + "value": "float32x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCVTL2" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vcvt_high_f32_f64", @@ -17594,6 +20068,64 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vcvt_n_f16_s16", + "arguments": [ + "int16x4_t a", + "const int n" + ], + "return_type": { + "value": "float16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.4H" + }, + "n": { + "minimum": 1, + "maximum": 16 + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "SCVTF" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vcvt_n_f16_u16", + "arguments": [ + "uint16x4_t a", + "const int n" + ], + "return_type": { + "value": "float16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.4H" + }, + "n": { + "minimum": 1, + "maximum": 16 + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "UCVTF" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vcvt_n_f32_s32", @@ -17710,6 +20242,35 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vcvt_n_s16_f16", + "arguments": [ + "float16x4_t a", + "const int n" + ], + "return_type": { + "value": "int16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.4H" + }, + "n": { + "minimum": 1, + "maximum": 16 + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FCVTZS" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vcvt_n_s32_f32", @@ -17768,6 +20329,35 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vcvt_n_u16_f16", + "arguments": [ + "float16x4_t a", + "const int n" + ], + "return_type": { + "value": "uint16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.4H" + }, + "n": { + "minimum": 1, + "maximum": 16 + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FCVTZU" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vcvt_n_u32_f32", @@ -17826,6 +20416,30 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vcvt_s16_f16", + "arguments": [ + "float16x4_t a" + ], + "return_type": { + "value": "int16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.4H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FCVTZS" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vcvt_s32_f32", @@ -17874,6 +20488,30 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vcvt_u16_f16", + "arguments": [ + "float16x4_t a" + ], + "return_type": { + "value": "uint16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.4H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FCVTZS" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vcvt_u32_f32", @@ -17922,6 +20560,30 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vcvta_s16_f16", + "arguments": [ + "float16x4_t a" + ], + "return_type": { + "value": "int16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.4H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FCVTAS" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vcvta_s32_f32", @@ -17969,6 +20631,30 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vcvta_u16_f16", + "arguments": [ + "float16x4_t a" + ], + "return_type": { + "value": "uint16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.4H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FCVTAU" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vcvta_u32_f32", @@ -18062,6 +20748,170 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vcvtah_s16_f16", + "arguments": [ + "float16_t a" + ], + "return_type": { + "value": "int16_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Hn" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCVTAS" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vcvtah_s32_f16", + "arguments": [ + "float16_t a" + ], + "return_type": { + "value": "int32_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Hn" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FCVTAS" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vcvtah_s64_f16", + "arguments": [ + "float16_t a" + ], + "return_type": { + "value": "int64_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Hn" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCVTAS" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vcvtah_u16_f16", + "arguments": [ + "float16_t a" + ], + "return_type": { + "value": "uint16_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Hn" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCVTAU" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vcvtah_u32_f16", + "arguments": [ + "float16_t a" + ], + "return_type": { + "value": "uint32_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Hn" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FCVTAU" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vcvtah_u64_f16", + "arguments": [ + "float16_t a" + ], + "return_type": { + "value": "uint64_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Hn" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCVTAU" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vcvtaq_s16_f16", + "arguments": [ + "float16x8_t a" + ], + "return_type": { + "value": "int16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FCVTAS" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vcvtaq_s32_f32", @@ -18109,6 +20959,30 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vcvtaq_u16_f16", + "arguments": [ + "float16x8_t a" + ], + "return_type": { + "value": "uint16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FCVTAU" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vcvtaq_u32_f32", @@ -18406,6 +21280,650 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vcvth_f16_s16", + "arguments": [ + "int16_t a" + ], + "return_type": { + "value": "float16_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Hn" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SCVTF" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vcvth_f16_s32", + "arguments": [ + "int32_t a" + ], + "return_type": { + "value": "float16_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Hn" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "SCVTF" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vcvth_f16_s64", + "arguments": [ + "int64_t a" + ], + "return_type": { + "value": "float16_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Hn" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SCVTF" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vcvth_f16_u16", + "arguments": [ + "uint16_t a" + ], + "return_type": { + "value": "float16_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Hn" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UCVTF" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vcvth_f16_u32", + "arguments": [ + "uint32_t a" + ], + "return_type": { + "value": "float16_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Hn" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "UCVTF" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vcvth_f16_u64", + "arguments": [ + "uint64_t a" + ], + "return_type": { + "value": "float16_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Hn" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UCVTF" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vcvth_n_f16_s16", + "arguments": [ + "int16_t a", + "const int n" + ], + "return_type": { + "value": "float16_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Hn" + }, + "n": { + "minimum": 1, + "maximum": 16 + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SCVTF" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vcvth_n_f16_s32", + "arguments": [ + "int32_t a", + "const int n" + ], + "return_type": { + "value": "float16_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Hn" + }, + "n": { + "minimum": 1, + "maximum": 16 + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "SCVTF" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vcvth_n_f16_s64", + "arguments": [ + "int64_t a", + "const int n" + ], + "return_type": { + "value": "float16_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Hn" + }, + "n": { + "minimum": 1, + "maximum": 16 + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SCVTF" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vcvth_n_f16_u16", + "arguments": [ + "uint16_t a", + "const int n" + ], + "return_type": { + "value": "float16_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Hn" + }, + "n": { + "minimum": 1, + "maximum": 16 + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UCVTF" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vcvth_n_f16_u32", + "arguments": [ + "uint32_t a", + "const int n" + ], + "return_type": { + "value": "float16_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Hn" + }, + "n": { + "minimum": 1, + "maximum": 16 + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "UCVTF" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vcvth_n_f16_u64", + "arguments": [ + "uint64_t a", + "const int n" + ], + "return_type": { + "value": "float16_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Hn" + }, + "n": { + "minimum": 1, + "maximum": 16 + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UCVTF" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vcvth_n_s16_f16", + "arguments": [ + "float16_t a", + "const int n" + ], + "return_type": { + "value": "int16_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Hn" + }, + "n": { + "minimum": 1, + "maximum": 16 + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCVTZS" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vcvth_n_s32_f16", + "arguments": [ + "float16_t a", + "const int n" + ], + "return_type": { + "value": "int32_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Hn" + }, + "n": { + "minimum": 1, + "maximum": 16 + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FCVTZS" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vcvth_n_s64_f16", + "arguments": [ + "float16_t a", + "const int n" + ], + "return_type": { + "value": "int64_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Hn" + }, + "n": { + "minimum": 1, + "maximum": 16 + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCVTZS" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vcvth_n_u16_f16", + "arguments": [ + "float16_t a", + "const int n" + ], + "return_type": { + "value": "uint16_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Hn" + }, + "n": { + "minimum": 1, + "maximum": 16 + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCVTZU" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vcvth_n_u32_f16", + "arguments": [ + "float16_t a", + "const int n" + ], + "return_type": { + "value": "uint32_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Hn" + }, + "n": { + "minimum": 1, + "maximum": 16 + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FCVTZU" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vcvth_n_u64_f16", + "arguments": [ + "float16_t a", + "const int n" + ], + "return_type": { + "value": "uint64_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Hn" + }, + "n": { + "minimum": 1, + "maximum": 16 + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCVTZU" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vcvth_s16_f16", + "arguments": [ + "float16_t a" + ], + "return_type": { + "value": "int16_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Hn" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCVTZS" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vcvth_s32_f16", + "arguments": [ + "float16_t a" + ], + "return_type": { + "value": "int32_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Hn" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FCVTZS" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vcvth_s64_f16", + "arguments": [ + "float16_t a" + ], + "return_type": { + "value": "int64_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Hn" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCVTZS" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vcvth_u16_f16", + "arguments": [ + "float16_t a" + ], + "return_type": { + "value": "uint16_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Hn" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCVTZU" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vcvth_u32_f16", + "arguments": [ + "float16_t a" + ], + "return_type": { + "value": "uint32_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Hn" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FCVTZU" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vcvth_u64_f16", + "arguments": [ + "float16_t a" + ], + "return_type": { + "value": "uint64_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Hn" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCVTZU" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vcvtm_s16_f16", + "arguments": [ + "float16x4_t a" + ], + "return_type": { + "value": "int16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.4H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FCVTMS" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vcvtm_s32_f32", @@ -18453,6 +21971,30 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vcvtm_u16_f16", + "arguments": [ + "float16x4_t a" + ], + "return_type": { + "value": "uint16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.4H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FCVTMU" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vcvtm_u32_f32", @@ -18546,6 +22088,170 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vcvtmh_s16_f16", + "arguments": [ + "float16_t a" + ], + "return_type": { + "value": "int16_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Hn" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCVTMS" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vcvtmh_s32_f16", + "arguments": [ + "float16_t a" + ], + "return_type": { + "value": "int32_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Hn" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FCVTMS" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vcvtmh_s64_f16", + "arguments": [ + "float16_t a" + ], + "return_type": { + "value": "int64_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Hn" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCVTMS" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vcvtmh_u16_f16", + "arguments": [ + "float16_t a" + ], + "return_type": { + "value": "uint16_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Hn" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCVTMU" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vcvtmh_u32_f16", + "arguments": [ + "float16_t a" + ], + "return_type": { + "value": "uint32_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Hn" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FCVTMU" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vcvtmh_u64_f16", + "arguments": [ + "float16_t a" + ], + "return_type": { + "value": "uint64_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Hn" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCVTMU" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vcvtmq_s16_f16", + "arguments": [ + "float16x8_t a" + ], + "return_type": { + "value": "int16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FCVTMS" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vcvtmq_s32_f32", @@ -18593,6 +22299,30 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vcvtmq_u16_f16", + "arguments": [ + "float16x8_t a" + ], + "return_type": { + "value": "uint16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FCVTMU" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vcvtmq_u32_f32", @@ -18686,6 +22416,30 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vcvtn_s16_f16", + "arguments": [ + "float16x4_t a" + ], + "return_type": { + "value": "int16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.4H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FCVTNS" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vcvtn_s32_f32", @@ -18733,6 +22487,30 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vcvtn_u16_f16", + "arguments": [ + "float16x4_t a" + ], + "return_type": { + "value": "uint16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.4H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FCVTNU" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vcvtn_u32_f32", @@ -18826,6 +22604,170 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vcvtnh_s16_f16", + "arguments": [ + "float16_t a" + ], + "return_type": { + "value": "int16_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Hn" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCVTNS" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vcvtnh_s32_f16", + "arguments": [ + "float16_t a" + ], + "return_type": { + "value": "int32_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Hn" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FCVTNS" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vcvtnh_s64_f16", + "arguments": [ + "float16_t a" + ], + "return_type": { + "value": "int64_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Hn" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCVTNS" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vcvtnh_u16_f16", + "arguments": [ + "float16_t a" + ], + "return_type": { + "value": "uint16_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Hn" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCVTNU" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vcvtnh_u32_f16", + "arguments": [ + "float16_t a" + ], + "return_type": { + "value": "uint32_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Hn" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FCVTNU" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vcvtnh_u64_f16", + "arguments": [ + "float16_t a" + ], + "return_type": { + "value": "uint64_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Hn" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCVTNU" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vcvtnq_s16_f16", + "arguments": [ + "float16x8_t a" + ], + "return_type": { + "value": "int16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FCVTNS" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vcvtnq_s32_f32", @@ -18873,6 +22815,30 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vcvtnq_u16_f16", + "arguments": [ + "float16x8_t a" + ], + "return_type": { + "value": "uint16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FCVTNU" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vcvtnq_u32_f32", @@ -18966,6 +22932,30 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vcvtp_s16_f16", + "arguments": [ + "float16x4_t a" + ], + "return_type": { + "value": "int16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.4H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FCVTPS" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vcvtp_s32_f32", @@ -19013,6 +23003,30 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vcvtp_u16_f16", + "arguments": [ + "float16x4_t a" + ], + "return_type": { + "value": "uint16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.4H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FCVTPU" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vcvtp_u32_f32", @@ -19106,6 +23120,170 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vcvtph_s16_f16", + "arguments": [ + "float16_t a" + ], + "return_type": { + "value": "int16_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Hn" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCVTPS" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vcvtph_s32_f16", + "arguments": [ + "float16_t a" + ], + "return_type": { + "value": "int32_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Hn" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FCVTPS" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vcvtph_s64_f16", + "arguments": [ + "float16_t a" + ], + "return_type": { + "value": "int64_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Hn" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCVTPS" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vcvtph_u16_f16", + "arguments": [ + "float16_t a" + ], + "return_type": { + "value": "uint16_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Hn" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCVTPU" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vcvtph_u32_f16", + "arguments": [ + "float16_t a" + ], + "return_type": { + "value": "uint32_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Hn" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FCVTPU" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vcvtph_u64_f16", + "arguments": [ + "float16_t a" + ], + "return_type": { + "value": "uint64_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Hn" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FCVTPU" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vcvtpq_s16_f16", + "arguments": [ + "float16x8_t a" + ], + "return_type": { + "value": "int16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FCVTPS" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vcvtpq_s32_f32", @@ -19153,6 +23331,30 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vcvtpq_u16_f16", + "arguments": [ + "float16x8_t a" + ], + "return_type": { + "value": "uint16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FCVTPU" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vcvtpq_u32_f32", @@ -19246,6 +23448,54 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vcvtq_f16_s16", + "arguments": [ + "int16x8_t a" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "SCVTF" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vcvtq_f16_u16", + "arguments": [ + "uint16x8_t a" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "UCVTF" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vcvtq_f32_s32", @@ -19342,6 +23592,64 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vcvtq_n_f16_s16", + "arguments": [ + "int16x8_t a", + "const int n" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + }, + "n": { + "minimum": 1, + "maximum": 16 + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "SCVTF" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vcvtq_n_f16_u16", + "arguments": [ + "uint16x8_t a", + "const int n" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + }, + "n": { + "minimum": 1, + "maximum": 16 + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "UCVTF" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vcvtq_n_f32_s32", @@ -19458,6 +23766,35 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vcvtq_n_s16_f16", + "arguments": [ + "float16x8_t a", + "const int n" + ], + "return_type": { + "value": "int16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + }, + "n": { + "minimum": 1, + "maximum": 16 + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FCVTZS" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vcvtq_n_s32_f32", @@ -19516,6 +23853,35 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vcvtq_n_u16_f16", + "arguments": [ + "float16x8_t a", + "const int n" + ], + "return_type": { + "value": "uint16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + }, + "n": { + "minimum": 1, + "maximum": 16 + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FCVTZU" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vcvtq_n_u32_f32", @@ -19574,6 +23940,30 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vcvtq_s16_f16", + "arguments": [ + "float16x8_t a" + ], + "return_type": { + "value": "int16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FCVTZS" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vcvtq_s32_f32", @@ -19622,6 +24012,30 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vcvtq_u16_f16", + "arguments": [ + "float16x8_t a" + ], + "return_type": { + "value": "uint16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FCVTZS" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vcvtq_u32_f32", @@ -19947,6 +24361,33 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vdiv_f16", + "arguments": [ + "float16x4_t a", + "float16x4_t b" + ], + "return_type": { + "value": "float16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.4H" + }, + "b": { + "register": "Vm.4H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FDIV" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vdiv_f32", @@ -20001,6 +24442,61 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vdivh_f16", + "arguments": [ + "float16_t a", + "float16_t b" + ], + "return_type": { + "value": "float16_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Hn" + }, + "b": { + "register": "Hm" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FDIV" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vdivq_f16", + "arguments": [ + "float16x8_t a", + "float16x8_t b" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + }, + "b": { + "register": "Vm.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FDIV" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vdivq_f32", @@ -20475,6 +24971,36 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vdup_lane_f16", + "arguments": [ + "float16x4_t vec", + "const int lane" + ], + "return_type": { + "value": "float16x4_t" + }, + "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 3 + }, + "vec": { + "register": "Vn.4H" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "DUP" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vdup_lane_f32", @@ -20862,6 +25388,34 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vdup_laneq_f16", + "arguments": [ + "float16x8_t vec", + "const int lane" + ], + "return_type": { + "value": "float16x4_t" + }, + "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 7 + }, + "vec": { + "register": "Vn.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "DUP" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vdup_laneq_f32", @@ -21226,6 +25780,31 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vdup_n_f16", + "arguments": [ + "float16_t value" + ], + "return_type": { + "value": "float16x4_t" + }, + "Arguments_Preparation": { + "value": { + "register": "rn" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "DUP" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vdup_n_f32", @@ -21884,6 +26463,34 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vduph_lane_f16", + "arguments": [ + "float16x4_t vec", + "const int lane" + ], + "return_type": { + "value": "float16_t" + }, + "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 3 + }, + "vec": { + "register": "Vn.4H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "DUP" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vduph_lane_p16", @@ -21968,6 +26575,34 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vduph_laneq_f16", + "arguments": [ + "float16x8_t vec", + "const int lane" + ], + "return_type": { + "value": "float16_t" + }, + "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 7 + }, + "vec": { + "register": "Vn.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "DUP" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vduph_laneq_p16", @@ -22052,6 +26687,36 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vdupq_lane_f16", + "arguments": [ + "float16x4_t vec", + "const int lane" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 3 + }, + "vec": { + "register": "Vn.4H" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "DUP" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vdupq_lane_f32", @@ -22439,6 +27104,34 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vdupq_laneq_f16", + "arguments": [ + "float16x8_t vec", + "const int lane" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 7 + }, + "vec": { + "register": "Vn.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "DUP" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vdupq_laneq_f32", @@ -22803,6 +27496,31 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vdupq_n_f16", + "arguments": [ + "float16_t value" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "value": { + "register": "rn" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "DUP" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vdupq_n_f32", @@ -23973,6 +28691,40 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vext_f16", + "arguments": [ + "float16x4_t a", + "float16x4_t b", + "const int n" + ], + "return_type": { + "value": "float16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8B" + }, + "b": { + "register": "Vm.8B" + }, + "n": { + "minimum": 0, + "maximum": 3 + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "EXT" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vext_f32", @@ -24412,6 +29164,40 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vextq_f16", + "arguments": [ + "float16x8_t a", + "float16x8_t b", + "const int n" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.16B" + }, + "b": { + "register": "Vm.16B" + }, + "n": { + "minimum": 0, + "maximum": 7 + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "EXT" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vextq_f32", @@ -24851,6 +29637,38 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vfma_f16", + "arguments": [ + "float16x4_t a", + "float16x4_t b", + "float16x4_t c" + ], + "return_type": { + "value": "float16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vd.4H" + }, + "b": { + "register": "Vn.4H" + }, + "c": { + "register": "Vm.4H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FMLA" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vfma_f32", @@ -24915,6 +29733,42 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vfma_lane_f16", + "arguments": [ + "float16x4_t a", + "float16x4_t b", + "float16x4_t v", + "const int lane" + ], + "return_type": { + "value": "float16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vd.4H" + }, + "b": { + "register": "Vn.4H" + }, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMLA" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vfma_lane_f32", @@ -24987,6 +29841,42 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vfma_laneq_f16", + "arguments": [ + "float16x4_t a", + "float16x4_t b", + "float16x8_t v", + "const int lane" + ], + "return_type": { + "value": "float16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vd.4H" + }, + "b": { + "register": "Vn.4H" + }, + "lane": { + "minimum": 0, + "maximum": 7 + }, + "v": { + "register": "Vm.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMLA" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vfma_laneq_f32", @@ -25059,6 +29949,37 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vfma_n_f16", + "arguments": [ + "float16x4_t a", + "float16x4_t b", + "float16_t n" + ], + "return_type": { + "value": "float16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vd.4H " + }, + "b": { + "register": "Vn.4H" + }, + "n": { + "register": "Vm.H[0]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMLA" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vfma_n_f32", @@ -25195,6 +30116,142 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vfmah_f16", + "arguments": [ + "float16_t a", + "float16_t b", + "float16_t c" + ], + "return_type": { + "value": "float16_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Ha" + }, + "b": { + "register": "Hn" + }, + "c": { + "register": "Hm" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FMADD" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vfmah_lane_f16", + "arguments": [ + "float16_t a", + "float16_t b", + "float16x4_t v", + "const int lane" + ], + "return_type": { + "value": "float16_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Hd" + }, + "b": { + "register": "Hn" + }, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMLA" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vfmah_laneq_f16", + "arguments": [ + "float16_t a", + "float16_t b", + "float16x8_t v", + "const int lane" + ], + "return_type": { + "value": "float16_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Hd" + }, + "b": { + "register": "Hn" + }, + "lane": { + "minimum": 0, + "maximum": 7 + }, + "v": { + "register": "Vm.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMLA" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vfmaq_f16", + "arguments": [ + "float16x8_t a", + "float16x8_t b", + "float16x8_t c" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vd.8H" + }, + "b": { + "register": "Vn.8H" + }, + "c": { + "register": "Vm.8H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FMLA" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vfmaq_f32", @@ -25259,6 +30316,42 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vfmaq_lane_f16", + "arguments": [ + "float16x8_t a", + "float16x8_t b", + "float16x4_t v", + "const int lane" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vd.8H" + }, + "b": { + "register": "Vn.8H" + }, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMLA" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vfmaq_lane_f32", @@ -25331,6 +30424,42 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vfmaq_laneq_f16", + "arguments": [ + "float16x8_t a", + "float16x8_t b", + "float16x8_t v", + "const int lane" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vd.8H" + }, + "b": { + "register": "Vn.8H" + }, + "lane": { + "minimum": 0, + "maximum": 7 + }, + "v": { + "register": "Vm.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMLA" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vfmaq_laneq_f32", @@ -25403,6 +30532,37 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vfmaq_n_f16", + "arguments": [ + "float16x8_t a", + "float16x8_t b", + "float16_t n" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vd.8H " + }, + "b": { + "register": "Vn.8H" + }, + "n": { + "register": "Vm.H[0]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMLA" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vfmaq_n_f32", @@ -25539,6 +30699,790 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vfmlal_high_f16", + "arguments": [ + "float32x2_t r", + "float16x4_t a", + "float16x4_t b" + ], + "return_type": { + "value": "float32x2_t" + }, + "Arguments_Preparation": { + "a": {}, + "b": {}, + "r": { + "register": "Vd.2S" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FMLAL2" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vfmlal_lane_high_f16", + "arguments": [ + "float32x2_t r", + "float16x4_t a", + "float16x4_t b", + "const int lane" + ], + "return_type": { + "value": "float32x2_t" + }, + "Arguments_Preparation": { + "a": {}, + "b": {}, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "r": { + "register": "Vd.2S" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FMLAL2" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vfmlal_lane_low_f16", + "arguments": [ + "float32x2_t r", + "float16x4_t a", + "float16x4_t b", + "const int lane" + ], + "return_type": { + "value": "float32x2_t" + }, + "Arguments_Preparation": { + "a": {}, + "b": {}, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "r": { + "register": "Vd.2S" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FMLAL" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vfmlal_laneq_high_f16", + "arguments": [ + "float32x2_t r", + "float16x4_t a", + "float16x8_t b", + "const int lane" + ], + "return_type": { + "value": "float32x2_t" + }, + "Arguments_Preparation": { + "a": {}, + "b": {}, + "lane": { + "minimum": 0, + "maximum": 7 + }, + "r": { + "register": "Vd.2S" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FMLAL2" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vfmlal_laneq_low_f16", + "arguments": [ + "float32x2_t r", + "float16x4_t a", + "float16x8_t b", + "const int lane" + ], + "return_type": { + "value": "float32x2_t" + }, + "Arguments_Preparation": { + "a": {}, + "b": {}, + "lane": { + "minimum": 0, + "maximum": 7 + }, + "r": { + "register": "Vd.2S" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FMLAL" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vfmlal_low_f16", + "arguments": [ + "float32x2_t r", + "float16x4_t a", + "float16x4_t b" + ], + "return_type": { + "value": "float32x2_t" + }, + "Arguments_Preparation": { + "a": {}, + "b": {}, + "r": { + "register": "Vd.2S" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FMLAL" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vfmlalq_high_f16", + "arguments": [ + "float32x4_t r", + "float16x8_t a", + "float16x8_t b" + ], + "return_type": { + "value": "float32x4_t" + }, + "Arguments_Preparation": { + "a": {}, + "b": {}, + "r": { + "register": "Vd.4S" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FMLAL2" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vfmlalq_lane_high_f16", + "arguments": [ + "float32x4_t r", + "float16x8_t a", + "float16x4_t b", + "const int lane" + ], + "return_type": { + "value": "float32x4_t" + }, + "Arguments_Preparation": { + "a": {}, + "b": {}, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "r": { + "register": "Vd.4S" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FMLAL2" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vfmlalq_lane_low_f16", + "arguments": [ + "float32x4_t r", + "float16x8_t a", + "float16x4_t b", + "const int lane" + ], + "return_type": { + "value": "float32x4_t" + }, + "Arguments_Preparation": { + "a": {}, + "b": {}, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "r": { + "register": "Vd.4S" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FMLAL" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vfmlalq_laneq_high_f16", + "arguments": [ + "float32x4_t r", + "float16x8_t a", + "float16x8_t b", + "const int lane" + ], + "return_type": { + "value": "float32x4_t" + }, + "Arguments_Preparation": { + "a": {}, + "b": {}, + "lane": { + "minimum": 0, + "maximum": 7 + }, + "r": { + "register": "Vd.4S" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FMLAL2" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vfmlalq_laneq_low_f16", + "arguments": [ + "float32x4_t r", + "float16x8_t a", + "float16x8_t b", + "const int lane" + ], + "return_type": { + "value": "float32x4_t" + }, + "Arguments_Preparation": { + "a": {}, + "b": {}, + "lane": { + "minimum": 0, + "maximum": 7 + }, + "r": { + "register": "Vd.4S" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FMLAL" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vfmlalq_low_f16", + "arguments": [ + "float32x4_t r", + "float16x8_t a", + "float16x8_t b" + ], + "return_type": { + "value": "float32x4_t" + }, + "Arguments_Preparation": { + "a": {}, + "b": {}, + "r": { + "register": "Vd.4S" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FMLAL" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vfmlsl_high_f16", + "arguments": [ + "float32x2_t r", + "float16x4_t a", + "float16x4_t b" + ], + "return_type": { + "value": "float32x2_t" + }, + "Arguments_Preparation": { + "a": {}, + "b": {}, + "r": { + "register": "Vd.2S" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FMLSL2" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vfmlsl_lane_high_f16", + "arguments": [ + "float32x2_t r", + "float16x4_t a", + "float16x4_t b", + "const int lane" + ], + "return_type": { + "value": "float32x2_t" + }, + "Arguments_Preparation": { + "a": {}, + "b": {}, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "r": { + "register": "Vd.2S" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FMLSL2" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vfmlsl_lane_low_f16", + "arguments": [ + "float32x2_t r", + "float16x4_t a", + "float16x4_t b", + "const int lane" + ], + "return_type": { + "value": "float32x2_t" + }, + "Arguments_Preparation": { + "a": {}, + "b": {}, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "r": { + "register": "Vd.2S" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FMLSL" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vfmlsl_laneq_high_f16", + "arguments": [ + "float32x2_t r", + "float16x4_t a", + "float16x8_t b", + "const int lane" + ], + "return_type": { + "value": "float32x2_t" + }, + "Arguments_Preparation": { + "a": {}, + "b": {}, + "lane": { + "minimum": 0, + "maximum": 7 + }, + "r": { + "register": "Vd.2S" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FMLSL2" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vfmlsl_laneq_low_f16", + "arguments": [ + "float32x2_t r", + "float16x4_t a", + "float16x8_t b", + "const int lane" + ], + "return_type": { + "value": "float32x2_t" + }, + "Arguments_Preparation": { + "a": {}, + "b": {}, + "lane": { + "minimum": 0, + "maximum": 7 + }, + "r": { + "register": "Vd.2S" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FMLSL" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vfmlsl_low_f16", + "arguments": [ + "float32x2_t r", + "float16x4_t a", + "float16x4_t b" + ], + "return_type": { + "value": "float32x2_t" + }, + "Arguments_Preparation": { + "a": {}, + "b": {}, + "r": { + "register": "Vd.2S" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FMLSL" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vfmlslq_high_f16", + "arguments": [ + "float32x4_t r", + "float16x8_t a", + "float16x8_t b" + ], + "return_type": { + "value": "float32x4_t" + }, + "Arguments_Preparation": { + "a": {}, + "b": {}, + "r": { + "register": "Vd.4S" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FMLSL2" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vfmlslq_lane_high_f16", + "arguments": [ + "float32x4_t r", + "float16x8_t a", + "float16x4_t b", + "const int lane" + ], + "return_type": { + "value": "float32x4_t" + }, + "Arguments_Preparation": { + "a": {}, + "b": {}, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "r": { + "register": "Vd.4S" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FMLSL2" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vfmlslq_lane_low_f16", + "arguments": [ + "float32x4_t r", + "float16x8_t a", + "float16x4_t b", + "const int lane" + ], + "return_type": { + "value": "float32x4_t" + }, + "Arguments_Preparation": { + "a": {}, + "b": {}, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "r": { + "register": "Vd.4S" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FMLSL" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vfmlslq_laneq_high_f16", + "arguments": [ + "float32x4_t r", + "float16x8_t a", + "float16x8_t b", + "const int lane" + ], + "return_type": { + "value": "float32x4_t" + }, + "Arguments_Preparation": { + "a": {}, + "b": {}, + "lane": { + "minimum": 0, + "maximum": 7 + }, + "r": { + "register": "Vd.4S" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FMLSL2" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vfmlslq_laneq_low_f16", + "arguments": [ + "float32x4_t r", + "float16x8_t a", + "float16x8_t b", + "const int lane" + ], + "return_type": { + "value": "float32x4_t" + }, + "Arguments_Preparation": { + "a": {}, + "b": {}, + "lane": { + "minimum": 0, + "maximum": 7 + }, + "r": { + "register": "Vd.4S" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FMLSL" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vfmlslq_low_f16", + "arguments": [ + "float32x4_t r", + "float16x8_t a", + "float16x8_t b" + ], + "return_type": { + "value": "float32x4_t" + }, + "Arguments_Preparation": { + "a": {}, + "b": {}, + "r": { + "register": "Vd.4S" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FMLSL" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vfms_f16", + "arguments": [ + "float16x4_t a", + "float16x4_t b", + "float16x4_t c" + ], + "return_type": { + "value": "float16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vd.4H" + }, + "b": { + "register": "Vn.4H" + }, + "c": { + "register": "Vm.4H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FMLS" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vfms_f32", @@ -25603,6 +31547,42 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vfms_lane_f16", + "arguments": [ + "float16x4_t a", + "float16x4_t b", + "float16x4_t v", + "const int lane" + ], + "return_type": { + "value": "float16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vd.4H" + }, + "b": { + "register": "Vn.4H" + }, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMLS" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vfms_lane_f32", @@ -25675,6 +31655,42 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vfms_laneq_f16", + "arguments": [ + "float16x4_t a", + "float16x4_t b", + "float16x8_t v", + "const int lane" + ], + "return_type": { + "value": "float16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vd.4H" + }, + "b": { + "register": "Vn.4H" + }, + "lane": { + "minimum": 0, + "maximum": 7 + }, + "v": { + "register": "Vm.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMLS" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vfms_laneq_f32", @@ -25747,6 +31763,37 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vfms_n_f16", + "arguments": [ + "float16x4_t a", + "float16x4_t b", + "float16_t n" + ], + "return_type": { + "value": "float16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vd.4H " + }, + "b": { + "register": "Vn.4H" + }, + "n": { + "register": "Vm.H[0]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMLS" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vfms_n_f32", @@ -25881,6 +31928,142 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vfmsh_f16", + "arguments": [ + "float16_t a", + "float16_t b", + "float16_t c" + ], + "return_type": { + "value": "float16_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Ha" + }, + "b": { + "register": "Hn" + }, + "c": { + "register": "Hm" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FMSUB" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vfmsh_lane_f16", + "arguments": [ + "float16_t a", + "float16_t b", + "float16x4_t v", + "const int lane" + ], + "return_type": { + "value": "float16_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Hd" + }, + "b": { + "register": "Hn" + }, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMLS" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vfmsh_laneq_f16", + "arguments": [ + "float16_t a", + "float16_t b", + "float16x8_t v", + "const int lane" + ], + "return_type": { + "value": "float16_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Hd" + }, + "b": { + "register": "Hn" + }, + "lane": { + "minimum": 0, + "maximum": 7 + }, + "v": { + "register": "Vm.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMLS" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vfmsq_f16", + "arguments": [ + "float16x8_t a", + "float16x8_t b", + "float16x8_t c" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vd.8H" + }, + "b": { + "register": "Vn.8H" + }, + "c": { + "register": "Vm.8H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FMLS" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vfmsq_f32", @@ -25945,6 +32128,42 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vfmsq_lane_f16", + "arguments": [ + "float16x8_t a", + "float16x8_t b", + "float16x4_t v", + "const int lane" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vd.8H" + }, + "b": { + "register": "Vn.8H" + }, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMLS" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vfmsq_lane_f32", @@ -26017,6 +32236,42 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vfmsq_laneq_f16", + "arguments": [ + "float16x8_t a", + "float16x8_t b", + "float16x8_t v", + "const int lane" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vd.8H" + }, + "b": { + "register": "Vn.8H" + }, + "lane": { + "minimum": 0, + "maximum": 7 + }, + "v": { + "register": "Vm.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMLS" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vfmsq_laneq_f32", @@ -26089,6 +32344,37 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vfmsq_n_f16", + "arguments": [ + "float16x8_t a", + "float16x8_t b", + "float16_t n" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vd.8H " + }, + "b": { + "register": "Vn.8H" + }, + "n": { + "register": "Vm.H[0]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMLS" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vfmsq_n_f32", @@ -26223,6 +32509,31 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vget_high_f16", + "arguments": [ + "float16x8_t a" + ], + "return_type": { + "value": "float16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "DUP" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vget_high_f32", @@ -26545,6 +32856,36 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vget_lane_f16", + "arguments": [ + "float16x4_t v", + "const int lane" + ], + "return_type": { + "value": "float16_t" + }, + "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vn.4H" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "DUP" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vget_lane_f32", @@ -26932,6 +33273,31 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vget_low_f16", + "arguments": [ + "float16x8_t a" + ], + "return_type": { + "value": "float16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "DUP" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vget_low_f32", @@ -27254,6 +33620,36 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vgetq_lane_f16", + "arguments": [ + "float16x8_t v", + "const int lane" + ], + "return_type": { + "value": "float16_t" + }, + "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 7 + }, + "v": { + "register": "Vn.8H" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "DUP" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vgetq_lane_f32", @@ -28337,6 +34733,31 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vld1_dup_f16", + "arguments": [ + "float16_t const * ptr" + ], + "return_type": { + "value": "float16x4_t" + }, + "Arguments_Preparation": { + "ptr": { + "register": "Xn" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "LD1R" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vld1_dup_f32", @@ -28659,6 +35080,106 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vld1_f16", + "arguments": [ + "float16_t const * ptr" + ], + "return_type": { + "value": "float16x4_t" + }, + "Arguments_Preparation": { + "ptr": { + "register": "Xn" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "LD1" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vld1_f16_x2", + "arguments": [ + "float16_t const * ptr" + ], + "return_type": { + "value": "float16x4x2_t" + }, + "Arguments_Preparation": { + "ptr": { + "register": "Xn" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "LD1" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vld1_f16_x3", + "arguments": [ + "float16_t const * ptr" + ], + "return_type": { + "value": "float16x4x3_t" + }, + "Arguments_Preparation": { + "ptr": { + "register": "Xn" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "LD1" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vld1_f16_x4", + "arguments": [ + "float16_t const * ptr" + ], + "return_type": { + "value": "float16x4x4_t" + }, + "Arguments_Preparation": { + "ptr": { + "register": "Xn" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "LD1" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vld1_f32", @@ -28851,6 +35372,40 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vld1_lane_f16", + "arguments": [ + "float16_t const * ptr", + "float16x4_t src", + "const int lane" + ], + "return_type": { + "value": "float16x4_t" + }, + "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 3 + }, + "ptr": { + "register": "Xn" + }, + "src": { + "register": "Vt.4H" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "LD1" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vld1_lane_f32", @@ -30386,6 +36941,31 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vld1q_dup_f16", + "arguments": [ + "float16_t const * ptr" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "ptr": { + "register": "Xn" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "LD1R" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vld1q_dup_f32", @@ -30708,6 +37288,106 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vld1q_f16", + "arguments": [ + "float16_t const * ptr" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "ptr": { + "register": "Xn" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "LD1" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vld1q_f16_x2", + "arguments": [ + "float16_t const * ptr" + ], + "return_type": { + "value": "float16x8x2_t" + }, + "Arguments_Preparation": { + "ptr": { + "register": "Xn" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "LD1" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vld1q_f16_x3", + "arguments": [ + "float16_t const * ptr" + ], + "return_type": { + "value": "float16x8x3_t" + }, + "Arguments_Preparation": { + "ptr": { + "register": "Xn" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "LD1" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vld1q_f16_x4", + "arguments": [ + "float16_t const * ptr" + ], + "return_type": { + "value": "float16x8x4_t" + }, + "Arguments_Preparation": { + "ptr": { + "register": "Xn" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "LD1" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vld1q_f32", @@ -30900,6 +37580,40 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vld1q_lane_f16", + "arguments": [ + "float16_t const * ptr", + "float16x8_t src", + "const int lane" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 7 + }, + "ptr": { + "register": "Xn" + }, + "src": { + "register": "Vt.8H" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "LD1" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vld1q_lane_f32", @@ -32435,6 +39149,31 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vld2_dup_f16", + "arguments": [ + "float16_t const * ptr" + ], + "return_type": { + "value": "float16x4x2_t" + }, + "Arguments_Preparation": { + "ptr": { + "register": "Xn" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "LD2R" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vld2_dup_f32", @@ -32757,6 +39496,31 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vld2_f16", + "arguments": [ + "float16_t const * ptr" + ], + "return_type": { + "value": "float16x4x2_t" + }, + "Arguments_Preparation": { + "ptr": { + "register": "Xn" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "LD2" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vld2_f32", @@ -32805,6 +39569,40 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vld2_lane_f16", + "arguments": [ + "float16_t const * ptr", + "float16x4x2_t src", + "const int lane" + ], + "return_type": { + "value": "float16x4x2_t" + }, + "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 3 + }, + "ptr": { + "register": "Xn" + }, + "src": { + "register": "Vt2.4H" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "LD2" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vld2_lane_f32", @@ -33513,6 +40311,31 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vld2q_dup_f16", + "arguments": [ + "float16_t const * ptr" + ], + "return_type": { + "value": "float16x8x2_t" + }, + "Arguments_Preparation": { + "ptr": { + "register": "Xn" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "LD2R" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vld2q_dup_f32", @@ -33830,6 +40653,31 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vld2q_f16", + "arguments": [ + "float16_t const * ptr" + ], + "return_type": { + "value": "float16x8x2_t" + }, + "Arguments_Preparation": { + "ptr": { + "register": "Xn" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "LD2" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vld2q_f32", @@ -33878,6 +40726,40 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vld2q_lane_f16", + "arguments": [ + "float16_t const * ptr", + "float16x8x2_t src", + "const int lane" + ], + "return_type": { + "value": "float16x8x2_t" + }, + "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 7 + }, + "ptr": { + "register": "Xn" + }, + "src": { + "register": "Vt2.8H" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "LD2" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vld2q_lane_f32", @@ -34575,6 +41457,31 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vld3_dup_f16", + "arguments": [ + "float16_t const * ptr" + ], + "return_type": { + "value": "float16x4x3_t" + }, + "Arguments_Preparation": { + "ptr": { + "register": "Xn" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "LD3R" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vld3_dup_f32", @@ -34897,6 +41804,31 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vld3_f16", + "arguments": [ + "float16_t const * ptr" + ], + "return_type": { + "value": "float16x4x3_t" + }, + "Arguments_Preparation": { + "ptr": { + "register": "Xn" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "LD3" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vld3_f32", @@ -34945,6 +41877,40 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vld3_lane_f16", + "arguments": [ + "float16_t const * ptr", + "float16x4x3_t src", + "const int lane" + ], + "return_type": { + "value": "float16x4x3_t" + }, + "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 3 + }, + "ptr": { + "register": "Xn" + }, + "src": { + "register": "Vt3.4H" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "LD3" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vld3_lane_f32", @@ -35653,6 +42619,31 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vld3q_dup_f16", + "arguments": [ + "float16_t const * ptr" + ], + "return_type": { + "value": "float16x8x3_t" + }, + "Arguments_Preparation": { + "ptr": { + "register": "Xn" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "LD3R" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vld3q_dup_f32", @@ -35970,6 +42961,31 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vld3q_f16", + "arguments": [ + "float16_t const * ptr" + ], + "return_type": { + "value": "float16x8x3_t" + }, + "Arguments_Preparation": { + "ptr": { + "register": "Xn" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "LD3" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vld3q_f32", @@ -36018,6 +43034,40 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vld3q_lane_f16", + "arguments": [ + "float16_t const * ptr", + "float16x8x3_t src", + "const int lane" + ], + "return_type": { + "value": "float16x8x3_t" + }, + "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 7 + }, + "ptr": { + "register": "Xn" + }, + "src": { + "register": "Vt3.8H" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "LD3" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vld3q_lane_f32", @@ -36715,6 +43765,31 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vld4_dup_f16", + "arguments": [ + "float16_t const * ptr" + ], + "return_type": { + "value": "float16x4x4_t" + }, + "Arguments_Preparation": { + "ptr": { + "register": "Xn" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "LD4R" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vld4_dup_f32", @@ -37037,6 +44112,31 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vld4_f16", + "arguments": [ + "float16_t const * ptr" + ], + "return_type": { + "value": "float16x4x4_t" + }, + "Arguments_Preparation": { + "ptr": { + "register": "Xn" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "LD4" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vld4_f32", @@ -37085,6 +44185,40 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vld4_lane_f16", + "arguments": [ + "float16_t const * ptr", + "float16x4x4_t src", + "const int lane" + ], + "return_type": { + "value": "float16x4x4_t" + }, + "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 3 + }, + "ptr": { + "register": "Xn" + }, + "src": { + "register": "Vt4.4H" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "LD4" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vld4_lane_f32", @@ -37793,6 +44927,31 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vld4q_dup_f16", + "arguments": [ + "float16_t const * ptr" + ], + "return_type": { + "value": "float16x8x4_t" + }, + "Arguments_Preparation": { + "ptr": { + "register": "Xn" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "LD4R" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vld4q_dup_f32", @@ -38110,6 +45269,31 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vld4q_f16", + "arguments": [ + "float16_t const * ptr" + ], + "return_type": { + "value": "float16x8x4_t" + }, + "Arguments_Preparation": { + "ptr": { + "register": "Xn" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "LD4" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vld4q_f32", @@ -38158,6 +45342,40 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vld4q_lane_f16", + "arguments": [ + "float16_t const * ptr", + "float16x8x4_t src", + "const int lane" + ], + "return_type": { + "value": "float16x8x4_t" + }, + "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 7 + }, + "ptr": { + "register": "Xn" + }, + "src": { + "register": "Vt4.8H" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "LD4" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vld4q_lane_f32", @@ -38879,6 +46097,34 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vmax_f16", + "arguments": [ + "float16x4_t a", + "float16x4_t b" + ], + "return_type": { + "value": "float16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.4H" + }, + "b": { + "register": "Vm.4H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FMAX" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vmax_f32", @@ -39109,6 +46355,61 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vmaxh_f16", + "arguments": [ + "float16_t a", + "float16_t b" + ], + "return_type": { + "value": "float16_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Hn" + }, + "b": { + "register": "Hm" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMAX" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vmaxnm_f16", + "arguments": [ + "float16x4_t a", + "float16x4_t b" + ], + "return_type": { + "value": "float16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.4H" + }, + "b": { + "register": "Vm.4H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FMAXNM" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vmaxnm_f32", @@ -39164,6 +46465,62 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vmaxnmh_f16", + "arguments": [ + "float16_t a", + "float16_t b" + ], + "return_type": { + "value": "float16_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Hn" + }, + "b": { + "register": "Hm" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FMAXNM" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vmaxnmq_f16", + "arguments": [ + "float16x8_t a", + "float16x8_t b" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + }, + "b": { + "register": "Vm.8H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FMAXNM" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vmaxnmq_f32", @@ -39219,6 +46576,29 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vmaxnmv_f16", + "arguments": [ + "float16x4_t a" + ], + "return_type": { + "value": "float16_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.4H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMAXNMP" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vmaxnmv_f32", @@ -39242,6 +46622,29 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vmaxnmvq_f16", + "arguments": [ + "float16x8_t a" + ], + "return_type": { + "value": "float16_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMAXNMP" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vmaxnmvq_f32", @@ -39288,6 +46691,34 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vmaxq_f16", + "arguments": [ + "float16x8_t a", + "float16x8_t b" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + }, + "b": { + "register": "Vm.8H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FMAX" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vmaxq_f32", @@ -39518,6 +46949,29 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vmaxv_f16", + "arguments": [ + "float16x4_t a" + ], + "return_type": { + "value": "float16_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.4H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMAXP" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vmaxv_f32", @@ -39679,6 +47133,29 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vmaxvq_f16", + "arguments": [ + "float16x8_t a" + ], + "return_type": { + "value": "float16_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMAXP" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vmaxvq_f32", @@ -39863,6 +47340,34 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vmin_f16", + "arguments": [ + "float16x4_t a", + "float16x4_t b" + ], + "return_type": { + "value": "float16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.4H" + }, + "b": { + "register": "Vm.4H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FMIN" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vmin_f32", @@ -40093,6 +47598,61 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vminh_f16", + "arguments": [ + "float16_t a", + "float16_t b" + ], + "return_type": { + "value": "float16_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Hn" + }, + "b": { + "register": "Hm" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMIN" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vminnm_f16", + "arguments": [ + "float16x4_t a", + "float16x4_t b" + ], + "return_type": { + "value": "float16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.4H" + }, + "b": { + "register": "Vm.4H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FMINNM" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vminnm_f32", @@ -40148,6 +47708,62 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vminnmh_f16", + "arguments": [ + "float16_t a", + "float16_t b" + ], + "return_type": { + "value": "float16_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Hn" + }, + "b": { + "register": "Hm" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FMINNM" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vminnmq_f16", + "arguments": [ + "float16x8_t a", + "float16x8_t b" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + }, + "b": { + "register": "Vm.8H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FMINNM" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vminnmq_f32", @@ -40203,6 +47819,29 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vminnmv_f16", + "arguments": [ + "float16x4_t a" + ], + "return_type": { + "value": "float16_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.4H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMINNMP" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vminnmv_f32", @@ -40226,6 +47865,29 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vminnmvq_f16", + "arguments": [ + "float16x8_t a" + ], + "return_type": { + "value": "float16_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMINNMP" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vminnmvq_f32", @@ -40272,6 +47934,34 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vminq_f16", + "arguments": [ + "float16x8_t a", + "float16x8_t b" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + }, + "b": { + "register": "Vm.8H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FMIN" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vminq_f32", @@ -40502,6 +48192,29 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vminv_f16", + "arguments": [ + "float16x4_t a" + ], + "return_type": { + "value": "float16_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.4H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMINP" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vminv_f32", @@ -40663,6 +48376,29 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vminvq_f16", + "arguments": [ + "float16x8_t a" + ], + "return_type": { + "value": "float16_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMINP" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vminvq_f32", @@ -46499,6 +54235,31 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vmov_n_f16", + "arguments": [ + "float16_t value" + ], + "return_type": { + "value": "float16x4_t" + }, + "Arguments_Preparation": { + "value": { + "register": "rn" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "DUP" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vmov_n_f32", @@ -47409,6 +55170,31 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vmovq_n_f16", + "arguments": [ + "float16_t value" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "value": { + "register": "rn" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "DUP" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vmovq_n_f32", @@ -47707,6 +55493,34 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vmul_f16", + "arguments": [ + "float16x4_t a", + "float16x4_t b" + ], + "return_type": { + "value": "float16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.4H" + }, + "b": { + "register": "Vm.4H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FMUL" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vmul_f32", @@ -47763,6 +55577,39 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vmul_lane_f16", + "arguments": [ + "float16x4_t a", + "float16x4_t v", + "const int lane" + ], + "return_type": { + "value": "float16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.4H" + }, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FMUL" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vmul_lane_f32", @@ -47965,6 +55812,38 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vmul_laneq_f16", + "arguments": [ + "float16x4_t a", + "float16x8_t v", + "const int lane" + ], + "return_type": { + "value": "float16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.4H" + }, + "lane": { + "minimum": 0, + "maximum": 7 + }, + "v": { + "register": "Vm.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMUL" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vmul_laneq_f32", @@ -48157,6 +56036,34 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vmul_n_f16", + "arguments": [ + "float16x4_t a", + "float16_t n" + ], + "return_type": { + "value": "float16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.4H" + }, + "n": { + "register": "Vm.H[0]" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FMUL" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vmul_n_f32", @@ -48596,6 +56503,98 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vmulh_f16", + "arguments": [ + "float16_t a", + "float16_t b" + ], + "return_type": { + "value": "float16_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Hn" + }, + "b": { + "register": "Hm" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FMUL" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vmulh_lane_f16", + "arguments": [ + "float16_t a", + "float16x4_t v", + "const int lane" + ], + "return_type": { + "value": "float16_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Hn" + }, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMUL" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vmulh_laneq_f16", + "arguments": [ + "float16_t a", + "float16x8_t v", + "const int lane" + ], + "return_type": { + "value": "float16_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Hn" + }, + "lane": { + "minimum": 0, + "maximum": 7 + }, + "v": { + "register": "Vm.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMUL" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vmull_high_lane_s16", @@ -49788,6 +57787,34 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vmulq_f16", + "arguments": [ + "float16x8_t a", + "float16x8_t b" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + }, + "b": { + "register": "Vm.8H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FMUL" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vmulq_f32", @@ -49844,6 +57871,39 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vmulq_lane_f16", + "arguments": [ + "float16x8_t a", + "float16x4_t v", + "const int lane" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + }, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FMUL" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vmulq_lane_f32", @@ -50046,6 +58106,38 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vmulq_laneq_f16", + "arguments": [ + "float16x8_t a", + "float16x8_t v", + "const int lane" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + }, + "lane": { + "minimum": 0, + "maximum": 7 + }, + "v": { + "register": "Vm.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMUL" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vmulq_laneq_f32", @@ -50238,6 +58330,34 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vmulq_n_f16", + "arguments": [ + "float16x8_t a", + "float16_t n" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + }, + "n": { + "register": "Vm.H[0]" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FMUL" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vmulq_n_f32", @@ -50677,6 +58797,33 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vmulx_f16", + "arguments": [ + "float16x4_t a", + "float16x4_t b" + ], + "return_type": { + "value": "float16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.4H" + }, + "b": { + "register": "Vm.4H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMULX" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vmulx_f32", @@ -50731,6 +58878,38 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vmulx_lane_f16", + "arguments": [ + "float16x4_t a", + "float16x4_t v", + "const int lane" + ], + "return_type": { + "value": "float16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.4H" + }, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMULX" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vmulx_lane_f32", @@ -50795,6 +58974,38 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vmulx_laneq_f16", + "arguments": [ + "float16x4_t a", + "float16x8_t v", + "const int lane" + ], + "return_type": { + "value": "float16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.4H" + }, + "lane": { + "minimum": 0, + "maximum": 7 + }, + "v": { + "register": "Vm.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMULX" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vmulx_laneq_f32", @@ -50859,6 +59070,33 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vmulx_n_f16", + "arguments": [ + "float16x4_t a", + "float16_t n" + ], + "return_type": { + "value": "float16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.4H" + }, + "n": { + "register": "Vm.H[0]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMULX" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vmulxd_f64", @@ -50950,6 +59188,124 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vmulxh_f16", + "arguments": [ + "float16_t a", + "float16_t b" + ], + "return_type": { + "value": "float16_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Hn" + }, + "b": { + "register": "Hm" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMULX" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vmulxh_lane_f16", + "arguments": [ + "float16_t a", + "float16x4_t v", + "const int lane" + ], + "return_type": { + "value": "float16_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Hn" + }, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMULX" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vmulxh_laneq_f16", + "arguments": [ + "float16_t a", + "float16x8_t v", + "const int lane" + ], + "return_type": { + "value": "float16_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Hn" + }, + "lane": { + "minimum": 0, + "maximum": 7 + }, + "v": { + "register": "Vm.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMULX" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vmulxq_f16", + "arguments": [ + "float16x8_t a", + "float16x8_t b" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + }, + "b": { + "register": "Vm.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMULX" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vmulxq_f32", @@ -51004,6 +59360,38 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vmulxq_lane_f16", + "arguments": [ + "float16x8_t a", + "float16x4_t v", + "const int lane" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + }, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vm.4H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMULX" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vmulxq_lane_f32", @@ -51068,6 +59456,38 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vmulxq_laneq_f16", + "arguments": [ + "float16x8_t a", + "float16x8_t v", + "const int lane" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + }, + "lane": { + "minimum": 0, + "maximum": 7 + }, + "v": { + "register": "Vm.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMULX" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vmulxq_laneq_f32", @@ -51132,6 +59552,33 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vmulxq_n_f16", + "arguments": [ + "float16x8_t a", + "float16_t n" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + }, + "n": { + "register": "Vm.H[0]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMULX" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vmulxs_f32", @@ -51573,6 +60020,30 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vneg_f16", + "arguments": [ + "float16x4_t a" + ], + "return_type": { + "value": "float16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.4H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FNEG" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vneg_f32", @@ -51742,6 +60213,54 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vnegh_f16", + "arguments": [ + "float16_t a" + ], + "return_type": { + "value": "float16_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Hn" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FNEG" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vnegq_f16", + "arguments": [ + "float16x8_t a" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FNEG" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vnegq_f32", @@ -53164,6 +61683,34 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vpadd_f16", + "arguments": [ + "float16x4_t a", + "float16x4_t b" + ], + "return_type": { + "value": "float16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.4H" + }, + "b": { + "register": "Vm.4H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FADDP" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vpadd_f32", @@ -53736,6 +62283,33 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vpaddq_f16", + "arguments": [ + "float16x8_t a", + "float16x8_t b" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + }, + "b": { + "register": "Vm.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FADDP" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vpaddq_f32", @@ -54029,6 +62603,34 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vpmax_f16", + "arguments": [ + "float16x4_t a", + "float16x4_t b" + ], + "return_type": { + "value": "float16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.4H" + }, + "b": { + "register": "Vm.4H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FMAXP" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vpmax_f32", @@ -54232,6 +62834,33 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vpmaxnm_f16", + "arguments": [ + "float16x4_t a", + "float16x4_t b" + ], + "return_type": { + "value": "float16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.4H" + }, + "b": { + "register": "Vm.4H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMAXNMP" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vpmaxnm_f32", @@ -54259,6 +62888,33 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vpmaxnmq_f16", + "arguments": [ + "float16x8_t a", + "float16x8_t b" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + }, + "b": { + "register": "Vm.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMAXNMP" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vpmaxnmq_f32", @@ -54359,6 +63015,33 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vpmaxq_f16", + "arguments": [ + "float16x8_t a", + "float16x8_t b" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + }, + "b": { + "register": "Vm.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMAXP" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vpmaxq_f32", @@ -54621,6 +63304,34 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vpmin_f16", + "arguments": [ + "float16x4_t a", + "float16x4_t b" + ], + "return_type": { + "value": "float16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.4H" + }, + "b": { + "register": "Vm.4H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FMINP" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vpmin_f32", @@ -54824,6 +63535,33 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vpminnm_f16", + "arguments": [ + "float16x4_t a", + "float16x4_t b" + ], + "return_type": { + "value": "float16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.4H" + }, + "b": { + "register": "Vm.4H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMINNMP" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vpminnm_f32", @@ -54851,6 +63589,33 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vpminnmq_f16", + "arguments": [ + "float16x8_t a", + "float16x8_t b" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + }, + "b": { + "register": "Vm.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMINNMP" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vpminnmq_f32", @@ -54951,6 +63716,33 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vpminq_f16", + "arguments": [ + "float16x8_t a", + "float16x8_t b" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + }, + "b": { + "register": "Vm.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FMINP" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vpminq_f32", @@ -68541,6 +77333,30 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vrecpe_f16", + "arguments": [ + "float16x4_t a" + ], + "return_type": { + "value": "float16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.4H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FRECPE" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vrecpe_f32", @@ -68637,6 +77453,53 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vrecpeh_f16", + "arguments": [ + "float16_t a" + ], + "return_type": { + "value": "float16_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Hn" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FRECPE" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vrecpeq_f16", + "arguments": [ + "float16x8_t a" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FRECPE" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vrecpeq_f32", @@ -68733,6 +77596,34 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vrecps_f16", + "arguments": [ + "float16x4_t a", + "float16x4_t b" + ], + "return_type": { + "value": "float16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.4H" + }, + "b": { + "register": "Vm.4H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FRECPS" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vrecps_f32", @@ -68816,6 +77707,61 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vrecpsh_f16", + "arguments": [ + "float16_t a", + "float16_t b" + ], + "return_type": { + "value": "float16_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Hn" + }, + "b": { + "register": "Hm" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FRECPS" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vrecpsq_f16", + "arguments": [ + "float16x8_t a", + "float16x8_t b" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + }, + "b": { + "register": "Vm.8H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FRECPS" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vrecpsq_f32", @@ -68922,6 +77868,29 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vrecpxh_f16", + "arguments": [ + "float16_t a" + ], + "return_type": { + "value": "float16_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Hn" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FRECPX" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vrecpxs_f32", @@ -68945,6 +77914,353 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vreinterpret_f16_f32", + "arguments": [ + "float32x2_t a" + ], + "return_type": { + "value": "float16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vd.2S" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "NOP" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vreinterpret_f16_f64", + "arguments": [ + "float64x1_t a" + ], + "return_type": { + "value": "float16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vd.1D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "NOP" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vreinterpret_f16_p16", + "arguments": [ + "poly16x4_t a" + ], + "return_type": { + "value": "float16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vd.4H" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "NOP" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vreinterpret_f16_p64", + "arguments": [ + "poly64x1_t a" + ], + "return_type": { + "value": "float16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vd.1D" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "NOP" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vreinterpret_f16_p8", + "arguments": [ + "poly8x8_t a" + ], + "return_type": { + "value": "float16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vd.8B" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "NOP" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vreinterpret_f16_s16", + "arguments": [ + "int16x4_t a" + ], + "return_type": { + "value": "float16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vd.4H" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "NOP" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vreinterpret_f16_s32", + "arguments": [ + "int32x2_t a" + ], + "return_type": { + "value": "float16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vd.2S" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "NOP" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vreinterpret_f16_s64", + "arguments": [ + "int64x1_t a" + ], + "return_type": { + "value": "float16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vd.1D" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "NOP" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vreinterpret_f16_s8", + "arguments": [ + "int8x8_t a" + ], + "return_type": { + "value": "float16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vd.8B" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "NOP" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vreinterpret_f16_u16", + "arguments": [ + "uint16x4_t a" + ], + "return_type": { + "value": "float16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vd.4H" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "NOP" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vreinterpret_f16_u32", + "arguments": [ + "uint32x2_t a" + ], + "return_type": { + "value": "float16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vd.2S" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "NOP" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vreinterpret_f16_u64", + "arguments": [ + "uint64x1_t a" + ], + "return_type": { + "value": "float16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vd.1D" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "NOP" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vreinterpret_f16_u8", + "arguments": [ + "uint8x8_t a" + ], + "return_type": { + "value": "float16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vd.8B" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "NOP" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vreinterpret_f32_f16", + "arguments": [ + "float16x4_t a" + ], + "return_type": { + "value": "float32x2_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vd.4H" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "NOP" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vreinterpret_f32_f64", @@ -69218,6 +78534,29 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vreinterpret_f64_f16", + "arguments": [ + "float16x4_t a" + ], + "return_type": { + "value": "float64x1_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vd.4H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "NOP" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vreinterpret_f64_f32", @@ -69494,6 +78833,31 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vreinterpret_p16_f16", + "arguments": [ + "float16x4_t a" + ], + "return_type": { + "value": "poly16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vd.4H" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "NOP" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vreinterpret_p16_f32", @@ -69791,6 +79155,30 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vreinterpret_p64_f16", + "arguments": [ + "float16x4_t a" + ], + "return_type": { + "value": "poly64x1_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vd.4H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "NOP" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vreinterpret_p64_f32", @@ -70054,6 +79442,31 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vreinterpret_p8_f16", + "arguments": [ + "float16x4_t a" + ], + "return_type": { + "value": "poly8x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vd.4H" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "NOP" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vreinterpret_p8_f32", @@ -70351,6 +79764,31 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vreinterpret_s16_f16", + "arguments": [ + "float16x4_t a" + ], + "return_type": { + "value": "int16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vd.4H" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "NOP" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vreinterpret_s16_f32", @@ -70648,6 +80086,31 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vreinterpret_s32_f16", + "arguments": [ + "float16x4_t a" + ], + "return_type": { + "value": "int32x2_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vd.4H" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "NOP" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vreinterpret_s32_f32", @@ -70945,6 +80408,31 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vreinterpret_s64_f16", + "arguments": [ + "float16x4_t a" + ], + "return_type": { + "value": "int64x1_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vd.4H" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "NOP" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vreinterpret_s64_f32", @@ -71242,6 +80730,31 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vreinterpret_s8_f16", + "arguments": [ + "float16x4_t a" + ], + "return_type": { + "value": "int8x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vd.4H" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "NOP" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vreinterpret_s8_f32", @@ -71539,6 +81052,31 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vreinterpret_u16_f16", + "arguments": [ + "float16x4_t a" + ], + "return_type": { + "value": "uint16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vd.4H" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "NOP" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vreinterpret_u16_f32", @@ -71836,6 +81374,31 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vreinterpret_u32_f16", + "arguments": [ + "float16x4_t a" + ], + "return_type": { + "value": "uint32x2_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vd.4H" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "NOP" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vreinterpret_u32_f32", @@ -72133,6 +81696,31 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vreinterpret_u64_f16", + "arguments": [ + "float16x4_t a" + ], + "return_type": { + "value": "uint64x1_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vd.4H" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "NOP" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vreinterpret_u64_f32", @@ -72430,6 +82018,31 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vreinterpret_u8_f16", + "arguments": [ + "float16x4_t a" + ], + "return_type": { + "value": "uint8x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vd.4H" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "NOP" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vreinterpret_u8_f32", @@ -72727,6 +82340,377 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vreinterpretq_f16_f32", + "arguments": [ + "float32x4_t a" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vd.4S" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "NOP" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vreinterpretq_f16_f64", + "arguments": [ + "float64x2_t a" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vd.2D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "NOP" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vreinterpretq_f16_p128", + "arguments": [ + "poly128_t a" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vd.1Q" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "NOP" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vreinterpretq_f16_p16", + "arguments": [ + "poly16x8_t a" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vd.8H" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "NOP" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vreinterpretq_f16_p64", + "arguments": [ + "poly64x2_t a" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vd.2D" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "NOP" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vreinterpretq_f16_p8", + "arguments": [ + "poly8x16_t a" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vd.16B" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "NOP" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vreinterpretq_f16_s16", + "arguments": [ + "int16x8_t a" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vd.8H" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "NOP" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vreinterpretq_f16_s32", + "arguments": [ + "int32x4_t a" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vd.4S" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "NOP" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vreinterpretq_f16_s64", + "arguments": [ + "int64x2_t a" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vd.2D" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "NOP" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vreinterpretq_f16_s8", + "arguments": [ + "int8x16_t a" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vd.16B" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "NOP" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vreinterpretq_f16_u16", + "arguments": [ + "uint16x8_t a" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vd.8H" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "NOP" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vreinterpretq_f16_u32", + "arguments": [ + "uint32x4_t a" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vd.4S" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "NOP" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vreinterpretq_f16_u64", + "arguments": [ + "uint64x2_t a" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vd.2D" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "NOP" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vreinterpretq_f16_u8", + "arguments": [ + "uint8x16_t a" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vd.16B" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "NOP" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vreinterpretq_f32_f16", + "arguments": [ + "float16x8_t a" + ], + "return_type": { + "value": "float32x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vd.8H" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "NOP" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vreinterpretq_f32_f64", @@ -73000,6 +82984,29 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vreinterpretq_f64_f16", + "arguments": [ + "float16x8_t a" + ], + "return_type": { + "value": "float64x2_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vd.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "NOP" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vreinterpretq_f64_f32", @@ -73301,6 +83308,30 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vreinterpretq_p128_f16", + "arguments": [ + "float16x8_t a" + ], + "return_type": { + "value": "poly128_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vd.8H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "NOP" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vreinterpretq_p128_f32", @@ -73588,6 +83619,31 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vreinterpretq_p16_f16", + "arguments": [ + "float16x8_t a" + ], + "return_type": { + "value": "poly16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vd.8H" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "NOP" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vreinterpretq_p16_f32", @@ -73909,6 +83965,30 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vreinterpretq_p64_f16", + "arguments": [ + "float16x8_t a" + ], + "return_type": { + "value": "poly64x2_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vd.8H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "NOP" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vreinterpretq_p64_f32", @@ -74196,6 +84276,31 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vreinterpretq_p8_f16", + "arguments": [ + "float16x8_t a" + ], + "return_type": { + "value": "poly8x16_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vd.8H" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "NOP" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vreinterpretq_p8_f32", @@ -74517,6 +84622,31 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vreinterpretq_s16_f16", + "arguments": [ + "float16x8_t a" + ], + "return_type": { + "value": "int16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vd.8H" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "NOP" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vreinterpretq_s16_f32", @@ -74838,6 +84968,31 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vreinterpretq_s32_f16", + "arguments": [ + "float16x8_t a" + ], + "return_type": { + "value": "int32x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vd.8H" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "NOP" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vreinterpretq_s32_f32", @@ -75159,6 +85314,31 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vreinterpretq_s64_f16", + "arguments": [ + "float16x8_t a" + ], + "return_type": { + "value": "int64x2_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vd.8H" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "NOP" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vreinterpretq_s64_f32", @@ -75480,6 +85660,31 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vreinterpretq_s8_f16", + "arguments": [ + "float16x8_t a" + ], + "return_type": { + "value": "int8x16_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vd.8H" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "NOP" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vreinterpretq_s8_f32", @@ -75801,6 +86006,31 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vreinterpretq_u16_f16", + "arguments": [ + "float16x8_t a" + ], + "return_type": { + "value": "uint16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vd.8H" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "NOP" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vreinterpretq_u16_f32", @@ -76122,6 +86352,31 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vreinterpretq_u32_f16", + "arguments": [ + "float16x8_t a" + ], + "return_type": { + "value": "uint32x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vd.8H" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "NOP" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vreinterpretq_u32_f32", @@ -76443,6 +86698,31 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vreinterpretq_u64_f16", + "arguments": [ + "float16x8_t a" + ], + "return_type": { + "value": "uint64x2_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vd.8H" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "NOP" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vreinterpretq_u64_f32", @@ -76764,6 +87044,31 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vreinterpretq_u8_f16", + "arguments": [ + "float16x8_t a" + ], + "return_type": { + "value": "uint8x16_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vd.8H" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "NOP" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vreinterpretq_u8_f32", @@ -77535,6 +87840,31 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vrev64_f16", + "arguments": [ + "float16x4_t vec" + ], + "return_type": { + "value": "float16x4_t" + }, + "Arguments_Preparation": { + "vec": { + "register": "Vn.4H" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "REV64" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vrev64_f32", @@ -77760,6 +88090,31 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vrev64q_f16", + "arguments": [ + "float16x8_t vec" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "vec": { + "register": "Vn.8H" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "REV64" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vrev64q_f32", @@ -78701,6 +89056,30 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vrnd_f16", + "arguments": [ + "float16x4_t a" + ], + "return_type": { + "value": "float16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.4H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FRINTZ" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vrnd_f32", @@ -78748,6 +89127,30 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vrnda_f16", + "arguments": [ + "float16x4_t a" + ], + "return_type": { + "value": "float16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.4H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FRINTA" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vrnda_f32", @@ -78795,6 +89198,54 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vrndah_f16", + "arguments": [ + "float16_t a" + ], + "return_type": { + "value": "float16_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Hn" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FRINTA" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vrndaq_f16", + "arguments": [ + "float16x8_t a" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FRINTA" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vrndaq_f32", @@ -78842,6 +89293,53 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vrndh_f16", + "arguments": [ + "float16_t a" + ], + "return_type": { + "value": "float16_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Hn" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FRINTZ" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vrndi_f16", + "arguments": [ + "float16x4_t a" + ], + "return_type": { + "value": "float16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.4H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FRINTI" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vrndi_f32", @@ -78889,6 +89387,53 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vrndih_f16", + "arguments": [ + "float16_t a" + ], + "return_type": { + "value": "float16_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Hn" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FRINTI" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vrndiq_f16", + "arguments": [ + "float16x8_t a" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FRINTI" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vrndiq_f32", @@ -78936,6 +89481,30 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vrndm_f16", + "arguments": [ + "float16x4_t a" + ], + "return_type": { + "value": "float16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.4H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FRINTM" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vrndm_f32", @@ -78983,6 +89552,54 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vrndmh_f16", + "arguments": [ + "float16_t a" + ], + "return_type": { + "value": "float16_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Hn" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FRINTM" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vrndmq_f16", + "arguments": [ + "float16x8_t a" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FRINTM" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vrndmq_f32", @@ -79030,6 +89647,30 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vrndn_f16", + "arguments": [ + "float16x4_t a" + ], + "return_type": { + "value": "float16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.4H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FRINTN" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vrndn_f32", @@ -79078,6 +89719,54 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vrndnh_f16", + "arguments": [ + "float16_t a" + ], + "return_type": { + "value": "float16_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Hn" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FRINTN" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vrndnq_f16", + "arguments": [ + "float16x8_t a" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FRINTN" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vrndnq_f32", @@ -79150,6 +89839,30 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vrndp_f16", + "arguments": [ + "float16x4_t a" + ], + "return_type": { + "value": "float16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.4H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FRINTP" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vrndp_f32", @@ -79197,6 +89910,54 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vrndph_f16", + "arguments": [ + "float16_t a" + ], + "return_type": { + "value": "float16_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Hn" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FRINTP" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vrndpq_f16", + "arguments": [ + "float16x8_t a" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FRINTP" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vrndpq_f32", @@ -79244,6 +90005,30 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vrndq_f16", + "arguments": [ + "float16x8_t a" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FRINTZ" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vrndq_f32", @@ -79291,6 +90076,30 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vrndx_f16", + "arguments": [ + "float16x4_t a" + ], + "return_type": { + "value": "float16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.4H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FRINTX" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vrndx_f32", @@ -79338,6 +90147,54 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vrndxh_f16", + "arguments": [ + "float16_t a" + ], + "return_type": { + "value": "float16_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Hn" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FRINTX" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vrndxq_f16", + "arguments": [ + "float16x8_t a" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FRINTX" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vrndxq_f32", @@ -80811,6 +91668,30 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vrsqrte_f16", + "arguments": [ + "float16x4_t a" + ], + "return_type": { + "value": "float16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.4H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FRSQRTE" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vrsqrte_f32", @@ -80907,6 +91788,53 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vrsqrteh_f16", + "arguments": [ + "float16_t a" + ], + "return_type": { + "value": "float16_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Hn" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FRSQRTE" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vrsqrteq_f16", + "arguments": [ + "float16x8_t a" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FRSQRTE" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vrsqrteq_f32", @@ -81003,6 +91931,34 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vrsqrts_f16", + "arguments": [ + "float16x4_t a", + "float16x4_t b" + ], + "return_type": { + "value": "float16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.4H" + }, + "b": { + "register": "Vm.4H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FRSQRTS" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vrsqrts_f32", @@ -81086,6 +92042,61 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vrsqrtsh_f16", + "arguments": [ + "float16_t a", + "float16_t b" + ], + "return_type": { + "value": "float16_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Hn" + }, + "b": { + "register": "Hm" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FRSQRTS" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vrsqrtsq_f16", + "arguments": [ + "float16x8_t a", + "float16x8_t b" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + }, + "b": { + "register": "Vm.8H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FRSQRTS" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vrsqrtsq_f32", @@ -82137,6 +93148,40 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vset_lane_f16", + "arguments": [ + "float16_t a", + "float16x4_t v", + "const int lane" + ], + "return_type": { + "value": "float16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "VnH" + }, + "lane": { + "minimum": 0, + "maximum": 3 + }, + "v": { + "register": "Vd.4H" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "MOV" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vset_lane_f32", @@ -82576,6 +93621,40 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vsetq_lane_f16", + "arguments": [ + "float16_t a", + "float16x8_t v", + "const int lane" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "VnH" + }, + "lane": { + "minimum": 0, + "maximum": 7 + }, + "v": { + "register": "Vd.8H" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "MOV" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vsetq_lane_f32", @@ -84031,7 +95110,7 @@ }, "n": { "minimum": 0, - "maximum": 15 + "maximum": 16 } }, "Architectures": [ @@ -84059,7 +95138,7 @@ }, "n": { "minimum": 0, - "maximum": 31 + "maximum": 32 } }, "Architectures": [ @@ -84087,7 +95166,7 @@ }, "n": { "minimum": 0, - "maximum": 7 + "maximum": 8 } }, "Architectures": [ @@ -84115,7 +95194,7 @@ }, "n": { "minimum": 0, - "maximum": 15 + "maximum": 16 } }, "Architectures": [ @@ -84143,7 +95222,7 @@ }, "n": { "minimum": 0, - "maximum": 31 + "maximum": 32 } }, "Architectures": [ @@ -84171,7 +95250,7 @@ }, "n": { "minimum": 0, - "maximum": 7 + "maximum": 8 } }, "Architectures": [ @@ -84199,7 +95278,7 @@ }, "n": { "minimum": 0, - "maximum": 15 + "maximum": 16 } }, "Architectures": [ @@ -84229,7 +95308,7 @@ }, "n": { "minimum": 0, - "maximum": 31 + "maximum": 32 } }, "Architectures": [ @@ -84259,7 +95338,7 @@ }, "n": { "minimum": 0, - "maximum": 7 + "maximum": 8 } }, "Architectures": [ @@ -84289,7 +95368,7 @@ }, "n": { "minimum": 0, - "maximum": 15 + "maximum": 16 } }, "Architectures": [ @@ -84319,7 +95398,7 @@ }, "n": { "minimum": 0, - "maximum": 31 + "maximum": 32 } }, "Architectures": [ @@ -84349,7 +95428,7 @@ }, "n": { "minimum": 0, - "maximum": 7 + "maximum": 8 } }, "Architectures": [ @@ -87136,6 +98215,29 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vsqrt_f16", + "arguments": [ + "float16x4_t a" + ], + "return_type": { + "value": "float16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.4H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FSQRT" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vsqrt_f32", @@ -87182,6 +98284,53 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vsqrth_f16", + "arguments": [ + "float16_t a" + ], + "return_type": { + "value": "float16_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Hn" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FSQRT" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vsqrtq_f16", + "arguments": [ + "float16x8_t a" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "FSQRT" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vsqrtq_f32", @@ -88646,6 +99795,122 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vst1_f16", + "arguments": [ + "float16_t * ptr", + "float16x4_t val" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "ptr": { + "register": "Xn" + }, + "val": { + "register": "Vt.4H" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "ST1" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vst1_f16_x2", + "arguments": [ + "float16_t * ptr", + "float16x4x2_t val" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "ptr": { + "register": "Xn" + }, + "val": { + "register": "Vt2.4H" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "ST1" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vst1_f16_x3", + "arguments": [ + "float16_t * ptr", + "float16x4x3_t val" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "ptr": { + "register": "Xn" + }, + "val": { + "register": "Vt3.4H" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "ST1" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vst1_f16_x4", + "arguments": [ + "float16_t * ptr", + "float16x4x4_t val" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "ptr": { + "register": "Xn" + }, + "val": { + "register": "Vt4.4H" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "ST1" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vst1_f32", @@ -88870,6 +100135,40 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vst1_lane_f16", + "arguments": [ + "float16_t * ptr", + "float16x4_t val", + "const int lane" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 3 + }, + "ptr": { + "register": "Xn" + }, + "val": { + "register": "Vt.4H" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "ST1" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vst1_lane_f32", @@ -90581,6 +101880,122 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vst1q_f16", + "arguments": [ + "float16_t * ptr", + "float16x8_t val" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "ptr": { + "register": "Xn" + }, + "val": { + "register": "Vt.8H" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "ST1" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vst1q_f16_x2", + "arguments": [ + "float16_t * ptr", + "float16x8x2_t val" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "ptr": { + "register": "Xn" + }, + "val": { + "register": "Vt2.8H" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "ST1" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vst1q_f16_x3", + "arguments": [ + "float16_t * ptr", + "float16x8x3_t val" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "ptr": { + "register": "Xn" + }, + "val": { + "register": "Vt3.8H" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "ST1" + ] + ] + }, + { + "SIMD_ISA": "Neon", + "name": "vst1q_f16_x4", + "arguments": [ + "float16_t * ptr", + "float16x8x4_t val" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "ptr": { + "register": "Xn" + }, + "val": { + "register": "Vt4.8H" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "ST1" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vst1q_f32", @@ -90805,6 +102220,40 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vst1q_lane_f16", + "arguments": [ + "float16_t * ptr", + "float16x8_t val", + "const int lane" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 7 + }, + "ptr": { + "register": "Xn" + }, + "val": { + "register": "Vt.8H" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "ST1" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vst1q_lane_f32", @@ -92517,6 +103966,35 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vst2_f16", + "arguments": [ + "float16_t * ptr", + "float16x4x2_t val" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "ptr": { + "register": "Xn" + }, + "val": { + "register": "Vt2.4H" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "ST2" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vst2_f32", @@ -92573,6 +104051,40 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vst2_lane_f16", + "arguments": [ + "float16_t * ptr", + "float16x4x2_t val", + "const int lane" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 3 + }, + "ptr": { + "register": "Xn" + }, + "val": { + "register": "Vt2.4H" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "ST2" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vst2_lane_f32", @@ -93325,6 +104837,35 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vst2q_f16", + "arguments": [ + "float16_t * ptr", + "float16x8x2_t val" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "ptr": { + "register": "Xn" + }, + "val": { + "register": "Vt2.8H" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "ST2" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vst2q_f32", @@ -93381,6 +104922,40 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vst2q_lane_f16", + "arguments": [ + "float16_t * ptr", + "float16x8x2_t val", + "const int lane" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 7 + }, + "ptr": { + "register": "Xn" + }, + "val": { + "register": "Vt2.8H" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "ST2" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vst2q_lane_f32", @@ -94122,6 +105697,35 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vst3_f16", + "arguments": [ + "float16_t * ptr", + "float16x4x3_t val" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "ptr": { + "register": "Xn" + }, + "val": { + "register": "Vt3.4H" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "ST3" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vst3_f32", @@ -94178,6 +105782,40 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vst3_lane_f16", + "arguments": [ + "float16_t * ptr", + "float16x4x3_t val", + "const int lane" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 3 + }, + "ptr": { + "register": "Xn" + }, + "val": { + "register": "Vt3.4H" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "ST3" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vst3_lane_f32", @@ -94930,6 +106568,35 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vst3q_f16", + "arguments": [ + "float16_t * ptr", + "float16x8x3_t val" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "ptr": { + "register": "Xn" + }, + "val": { + "register": "Vt3.8H" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "ST3" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vst3q_f32", @@ -94986,6 +106653,40 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vst3q_lane_f16", + "arguments": [ + "float16_t * ptr", + "float16x8x3_t val", + "const int lane" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 7 + }, + "ptr": { + "register": "Xn" + }, + "val": { + "register": "Vt3.8H" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "ST3" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vst3q_lane_f32", @@ -95733,6 +107434,35 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vst4_f16", + "arguments": [ + "float16_t * ptr", + "float16x4x4_t val" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "ptr": { + "register": "Xn" + }, + "val": { + "register": "Vt4.4H" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "ST4" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vst4_f32", @@ -95789,6 +107519,40 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vst4_lane_f16", + "arguments": [ + "float16_t * ptr", + "float16x4x4_t val", + "const int lane" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 3 + }, + "ptr": { + "register": "Xn" + }, + "val": { + "register": "Vt4.4H" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "ST4" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vst4_lane_f32", @@ -96541,6 +108305,35 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vst4q_f16", + "arguments": [ + "float16_t * ptr", + "float16x8x4_t val" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "ptr": { + "register": "Xn" + }, + "val": { + "register": "Vt4.8H" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "ST4" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vst4q_f32", @@ -96597,6 +108390,40 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vst4q_lane_f16", + "arguments": [ + "float16_t * ptr", + "float16x8x4_t val", + "const int lane" + ], + "return_type": { + "value": "void" + }, + "Arguments_Preparation": { + "lane": { + "minimum": 0, + "maximum": 7 + }, + "ptr": { + "register": "Xn" + }, + "val": { + "register": "Vt4.8H" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "ST4" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vst4q_lane_f32", @@ -97366,6 +109193,34 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vsub_f16", + "arguments": [ + "float16x4_t a", + "float16x4_t b" + ], + "return_type": { + "value": "float16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.4H" + }, + "b": { + "register": "Vm.4H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FSUB" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vsub_f32", @@ -97708,6 +109563,34 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vsubh_f16", + "arguments": [ + "float16_t a", + "float16_t b" + ], + "return_type": { + "value": "float16_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Hn" + }, + "b": { + "register": "Hm" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FSUB" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vsubhn_high_s16", @@ -98404,6 +110287,34 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vsubq_f16", + "arguments": [ + "float16x8_t a", + "float16x8_t b" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + }, + "b": { + "register": "Vm.8H" + } + }, + "Architectures": [ + "A32", + "A64" + ], + "instructions": [ + [ + "FSUB" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vsubq_f32", @@ -99864,6 +111775,33 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vtrn1_f16", + "arguments": [ + "float16x4_t a", + "float16x4_t b" + ], + "return_type": { + "value": "float16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.4H" + }, + "b": { + "register": "Vm.4H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "TRN1" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vtrn1_f32", @@ -100107,6 +112045,33 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vtrn1q_f16", + "arguments": [ + "float16x8_t a", + "float16x8_t b" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + }, + "b": { + "register": "Vm.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "TRN1" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vtrn1q_f32", @@ -100458,6 +112423,33 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vtrn2_f16", + "arguments": [ + "float16x4_t a", + "float16x4_t b" + ], + "return_type": { + "value": "float16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.4H" + }, + "b": { + "register": "Vm.4H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "TRN2" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vtrn2_f32", @@ -100701,6 +112693,33 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vtrn2q_f16", + "arguments": [ + "float16x8_t a", + "float16x8_t b" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + }, + "b": { + "register": "Vm.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "TRN2" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vtrn2q_f32", @@ -101052,6 +113071,36 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vtrn_f16", + "arguments": [ + "float16x4_t a", + "float16x4_t b" + ], + "return_type": { + "value": "float16x4x2_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.4H" + }, + "b": { + "register": "Vm.4H" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "TRN1", + "TRN2" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vtrn_f32", @@ -101322,6 +113371,36 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vtrnq_f16", + "arguments": [ + "float16x8_t a", + "float16x8_t b" + ], + "return_type": { + "value": "float16x8x2_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + }, + "b": { + "register": "Vm.8H" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "TRN1", + "TRN2" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vtrnq_f32", @@ -102781,6 +114860,33 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vuzp1_f16", + "arguments": [ + "float16x4_t a", + "float16x4_t b" + ], + "return_type": { + "value": "float16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.4H" + }, + "b": { + "register": "Vm.4H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UZP1" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vuzp1_f32", @@ -103024,6 +115130,33 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vuzp1q_f16", + "arguments": [ + "float16x8_t a", + "float16x8_t b" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + }, + "b": { + "register": "Vm.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UZP1" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vuzp1q_f32", @@ -103375,6 +115508,33 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vuzp2_f16", + "arguments": [ + "float16x4_t a", + "float16x4_t b" + ], + "return_type": { + "value": "float16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.4H" + }, + "b": { + "register": "Vm.4H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UZP2" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vuzp2_f32", @@ -103618,6 +115778,33 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vuzp2q_f16", + "arguments": [ + "float16x8_t a", + "float16x8_t b" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + }, + "b": { + "register": "Vm.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UZP2" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vuzp2q_f32", @@ -103969,6 +116156,36 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vuzp_f16", + "arguments": [ + "float16x4_t a", + "float16x4_t b" + ], + "return_type": { + "value": "float16x4x2_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.4H" + }, + "b": { + "register": "Vm.4H" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "UZP1", + "UZP2" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vuzp_f32", @@ -104239,6 +116456,36 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vuzpq_f16", + "arguments": [ + "float16x8_t a", + "float16x8_t b" + ], + "return_type": { + "value": "float16x8x2_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + }, + "b": { + "register": "Vm.8H" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "UZP1", + "UZP2" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vuzpq_f32", @@ -104539,6 +116786,33 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vzip1_f16", + "arguments": [ + "float16x4_t a", + "float16x4_t b" + ], + "return_type": { + "value": "float16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.4H" + }, + "b": { + "register": "Vm.4H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP1" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vzip1_f32", @@ -104782,6 +117056,33 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vzip1q_f16", + "arguments": [ + "float16x8_t a", + "float16x8_t b" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + }, + "b": { + "register": "Vm.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP1" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vzip1q_f32", @@ -105133,6 +117434,33 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vzip2_f16", + "arguments": [ + "float16x4_t a", + "float16x4_t b" + ], + "return_type": { + "value": "float16x4_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.4H" + }, + "b": { + "register": "Vm.4H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP2" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vzip2_f32", @@ -105376,6 +117704,33 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vzip2q_f16", + "arguments": [ + "float16x8_t a", + "float16x8_t b" + ], + "return_type": { + "value": "float16x8_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + }, + "b": { + "register": "Vm.8H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP2" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vzip2q_f32", @@ -105727,6 +118082,36 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vzip_f16", + "arguments": [ + "float16x4_t a", + "float16x4_t b" + ], + "return_type": { + "value": "float16x4x2_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.4H" + }, + "b": { + "register": "Vm.4H" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "ZIP1", + "ZIP2" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vzip_f32", @@ -105997,6 +118382,36 @@ ] ] }, + { + "SIMD_ISA": "Neon", + "name": "vzipq_f16", + "arguments": [ + "float16x8_t a", + "float16x8_t b" + ], + "return_type": { + "value": "float16x8x2_t" + }, + "Arguments_Preparation": { + "a": { + "register": "Vn.8H" + }, + "b": { + "register": "Vm.8H" + } + }, + "Architectures": [ + "v7", + "A32", + "A64" + ], + "instructions": [ + [ + "ZIP1", + "ZIP2" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vzipq_f32",