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RISC-V: tidying: Handling of base ISA

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This commit makes handling of the base ISA a separate block.

Co-Authored-By: Taiki Endo <te316e89@gmail.com>
This commit is contained in:
Tsukasa OI 2025-04-11 01:13:44 +00:00 • committed by Amanieu d'Antras
parent c36e9de178
commit e35bc48a60
1 changed files with 16 additions and 12 deletions
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28
library/stdarch/crates/std_detect/src/detect/os/linux/riscv.rs
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@ -44,18 +44,6 @@ pub(crate) fn detect_features() -> cache::Initializer {
&[Feature::f, Feature::zicsr],
bit::test(auxv.hwcap, (b'f' - b'a').into()),
);
let has_i = bit::test(auxv.hwcap, (b'i' - b'a').into());
// If future RV128I is supported, implement with `enable_feature` here
#[cfg(target_pointer_width = "64")]
enable_feature(&mut value, Feature::rv64i, has_i);
#[cfg(target_pointer_width = "32")]
enable_feature(&mut value, Feature::rv32i, has_i);
#[cfg(target_pointer_width = "32")]
enable_feature(
&mut value,
Feature::rv32e,
bit::test(auxv.hwcap, (b'e' - b'a').into()),
);
enable_feature(
&mut value,
Feature::h,
@ -66,6 +54,22 @@ pub(crate) fn detect_features() -> cache::Initializer {
Feature::m,
bit::test(auxv.hwcap, (b'm' - b'a').into()),
);
// Handle base ISA.
let has_i = bit::test(auxv.hwcap, (b'i' - b'a').into());
// If future RV128I is supported, implement with `enable_feature` here
#[cfg(target_pointer_width = "64")]
enable_feature(&mut value, Feature::rv64i, has_i);
#[cfg(target_pointer_width = "32")]
enable_feature(&mut value, Feature::rv32i, has_i);
// FIXME: e is not exposed in any of asm/hwcap.h, uapi/asm/hwcap.h, uapi/asm/hwprobe.h
#[cfg(target_pointer_width = "32")]
enable_feature(
&mut value,
Feature::rv32e,
bit::test(auxv.hwcap, (b'e' - b'a').into()),
);
// FIXME: Auxvec does not show supervisor feature support, but this mode may be useful
// to detect when Rust is used to write Linux kernel modules.
// These should be more than Auxvec way to detect supervisor features.