diff --git a/library/stdarch/crates/core_arch/src/x86/avx512f.rs b/library/stdarch/crates/core_arch/src/x86/avx512f.rs index 151bfe6481a4..4c07451a30ff 100644 --- a/library/stdarch/crates/core_arch/src/x86/avx512f.rs +++ b/library/stdarch/crates/core_arch/src/x86/avx512f.rs @@ -6259,27 +6259,25 @@ pub unsafe fn _mm_maskz_ternarylogic_epi64( /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_getmant_ps&expand=2880) #[inline] #[target_feature(enable = "avx512f")] -#[cfg_attr(test, assert_instr(vgetmantps, norm = 0, sign = 0))] -#[rustc_args_required_const(1, 2)] -pub unsafe fn _mm512_getmant_ps( +#[cfg_attr(test, assert_instr(vgetmantps, NORM = 0, SIGN = 0))] +#[rustc_legacy_const_generics(1, 2)] +pub unsafe fn _mm512_getmant_ps< + const NORM: _MM_MANTISSA_NORM_ENUM, + const SIGN: _MM_MANTISSA_SIGN_ENUM, +>( a: __m512, - norm: _MM_MANTISSA_NORM_ENUM, - sign: _MM_MANTISSA_SIGN_ENUM, ) -> __m512 { + static_assert_imm4!(NORM); + static_assert_imm2!(SIGN); let a = a.as_f32x16(); let zero = _mm512_setzero_ps().as_f32x16(); - macro_rules! call { - ($imm4:expr, $imm2:expr) => { - vgetmantps( - a, - $imm2 << 2 | $imm4, - zero, - 0b11111111_11111111, - _MM_FROUND_CUR_DIRECTION, - ) - }; - } - let r = constify_imm4_mantissas!(norm, sign, call); + let r = vgetmantps( + a, + SIGN << 2 | NORM, + zero, + 0b11111111_11111111, + _MM_FROUND_CUR_DIRECTION, + ); transmute(r) } @@ -6297,23 +6295,21 @@ pub unsafe fn _mm512_getmant_ps( /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_getmant_ps&expand=2881) #[inline] #[target_feature(enable = "avx512f")] -#[cfg_attr(test, assert_instr(vgetmantps, norm = 0, sign = 0))] -#[rustc_args_required_const(3, 4)] -pub unsafe fn _mm512_mask_getmant_ps( +#[cfg_attr(test, assert_instr(vgetmantps, NORM = 0, SIGN = 0))] +#[rustc_legacy_const_generics(3, 4)] +pub unsafe fn _mm512_mask_getmant_ps< + const NORM: _MM_MANTISSA_NORM_ENUM, + const SIGN: _MM_MANTISSA_SIGN_ENUM, +>( src: __m512, k: __mmask16, a: __m512, - norm: _MM_MANTISSA_NORM_ENUM, - sign: _MM_MANTISSA_SIGN_ENUM, ) -> __m512 { + static_assert_imm4!(NORM); + static_assert_imm2!(SIGN); let a = a.as_f32x16(); let src = src.as_f32x16(); - macro_rules! call { - ($imm4:expr, $imm2:expr) => { - vgetmantps(a, $imm2 << 2 | $imm4, src, k, _MM_FROUND_CUR_DIRECTION) - }; - } - let r = constify_imm4_mantissas!(norm, sign, call); + let r = vgetmantps(a, SIGN << 2 | NORM, src, k, _MM_FROUND_CUR_DIRECTION); transmute(r) } @@ -6331,22 +6327,20 @@ pub unsafe fn _mm512_mask_getmant_ps( /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_getmant_ps&expand=2882) #[inline] #[target_feature(enable = "avx512f")] -#[cfg_attr(test, assert_instr(vgetmantps, norm = 0, sign = 0))] -#[rustc_args_required_const(2, 3)] -pub unsafe fn _mm512_maskz_getmant_ps( +#[cfg_attr(test, assert_instr(vgetmantps, NORM = 0, SIGN = 0))] +#[rustc_legacy_const_generics(2, 3)] +pub unsafe fn _mm512_maskz_getmant_ps< + const NORM: _MM_MANTISSA_NORM_ENUM, + const SIGN: _MM_MANTISSA_SIGN_ENUM, +>( k: __mmask16, a: __m512, - norm: _MM_MANTISSA_NORM_ENUM, - sign: _MM_MANTISSA_SIGN_ENUM, ) -> __m512 { + static_assert_imm4!(NORM); + static_assert_imm2!(SIGN); let a = a.as_f32x16(); let zero = _mm512_setzero_ps().as_f32x16(); - macro_rules! call { - ($imm4:expr, $imm2:expr) => { - vgetmantps(a, $imm2 << 2 | $imm4, zero, k, _MM_FROUND_CUR_DIRECTION) - }; - } - let r = constify_imm4_mantissas!(norm, sign, call); + let r = vgetmantps(a, SIGN << 2 | NORM, zero, k, _MM_FROUND_CUR_DIRECTION); transmute(r) } @@ -6364,21 +6358,19 @@ pub unsafe fn _mm512_maskz_getmant_ps( /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_getmant_ps&expand=2877) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[cfg_attr(test, assert_instr(vgetmantps, norm = 0, sign = 0))] -#[rustc_args_required_const(1, 2)] -pub unsafe fn _mm256_getmant_ps( +#[cfg_attr(test, assert_instr(vgetmantps, NORM = 0, SIGN = 0))] +#[rustc_legacy_const_generics(1, 2)] +pub unsafe fn _mm256_getmant_ps< + const NORM: _MM_MANTISSA_NORM_ENUM, + const SIGN: _MM_MANTISSA_SIGN_ENUM, +>( a: __m256, - norm: _MM_MANTISSA_NORM_ENUM, - sign: _MM_MANTISSA_SIGN_ENUM, ) -> __m256 { + static_assert_imm4!(NORM); + static_assert_imm2!(SIGN); let a = a.as_f32x8(); let zero = _mm256_setzero_ps().as_f32x8(); - macro_rules! call { - ($imm4:expr, $imm2:expr) => { - vgetmantps256(a, $imm2 << 2 | $imm4, zero, 0b11111111) - }; - } - let r = constify_imm4_mantissas!(norm, sign, call); + let r = vgetmantps256(a, SIGN << 2 | NORM, zero, 0b11111111); transmute(r) } @@ -6396,23 +6388,21 @@ pub unsafe fn _mm256_getmant_ps( /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mask_getmant_ps&expand=2878) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[cfg_attr(test, assert_instr(vgetmantps, norm = 0, sign = 0))] -#[rustc_args_required_const(3, 4)] -pub unsafe fn _mm256_mask_getmant_ps( +#[cfg_attr(test, assert_instr(vgetmantps, NORM = 0, SIGN = 0))] +#[rustc_legacy_const_generics(3, 4)] +pub unsafe fn _mm256_mask_getmant_ps< + const NORM: _MM_MANTISSA_NORM_ENUM, + const SIGN: _MM_MANTISSA_SIGN_ENUM, +>( src: __m256, k: __mmask8, a: __m256, - norm: _MM_MANTISSA_NORM_ENUM, - sign: _MM_MANTISSA_SIGN_ENUM, ) -> __m256 { + static_assert_imm4!(NORM); + static_assert_imm2!(SIGN); let a = a.as_f32x8(); let src = src.as_f32x8(); - macro_rules! call { - ($imm4:expr, $imm2:expr) => { - vgetmantps256(a, $imm2 << 2 | $imm4, src, k) - }; - } - let r = constify_imm4_mantissas!(norm, sign, call); + let r = vgetmantps256(a, SIGN << 2 | NORM, src, k); transmute(r) } @@ -6430,22 +6420,20 @@ pub unsafe fn _mm256_mask_getmant_ps( /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_maskz_getmant_ps&expand=2879) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[cfg_attr(test, assert_instr(vgetmantps, norm = 0, sign = 0))] -#[rustc_args_required_const(2, 3)] -pub unsafe fn _mm256_maskz_getmant_ps( +#[cfg_attr(test, assert_instr(vgetmantps, NORM = 0, SIGN = 0))] +#[rustc_legacy_const_generics(2, 3)] +pub unsafe fn _mm256_maskz_getmant_ps< + const NORM: _MM_MANTISSA_NORM_ENUM, + const SIGN: _MM_MANTISSA_SIGN_ENUM, +>( k: __mmask8, a: __m256, - norm: _MM_MANTISSA_NORM_ENUM, - sign: _MM_MANTISSA_SIGN_ENUM, ) -> __m256 { + static_assert_imm4!(NORM); + static_assert_imm2!(SIGN); let a = a.as_f32x8(); let zero = _mm256_setzero_ps().as_f32x8(); - macro_rules! call { - ($imm4:expr, $imm2:expr) => { - vgetmantps256(a, $imm2 << 2 | $imm4, zero, k) - }; - } - let r = constify_imm4_mantissas!(norm, sign, call); + let r = vgetmantps256(a, SIGN << 2 | NORM, zero, k); transmute(r) } @@ -6463,21 +6451,19 @@ pub unsafe fn _mm256_maskz_getmant_ps( /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_getmant_ps&expand=2874) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[cfg_attr(test, assert_instr(vgetmantps, norm = 0, sign = 0))] -#[rustc_args_required_const(1, 2)] -pub unsafe fn _mm_getmant_ps( +#[cfg_attr(test, assert_instr(vgetmantps, NORM = 0, SIGN = 0))] +#[rustc_legacy_const_generics(1, 2)] +pub unsafe fn _mm_getmant_ps< + const NORM: _MM_MANTISSA_NORM_ENUM, + const SIGN: _MM_MANTISSA_SIGN_ENUM, +>( a: __m128, - norm: _MM_MANTISSA_NORM_ENUM, - sign: _MM_MANTISSA_SIGN_ENUM, ) -> __m128 { + static_assert_imm4!(NORM); + static_assert_imm2!(SIGN); let a = a.as_f32x4(); let zero = _mm_setzero_ps().as_f32x4(); - macro_rules! call { - ($imm4:expr, $imm2:expr) => { - vgetmantps128(a, $imm2 << 2 | $imm4, zero, 0b00001111) - }; - } - let r = constify_imm4_mantissas!(norm, sign, call); + let r = vgetmantps128(a, SIGN << 2 | NORM, zero, 0b00001111); transmute(r) } @@ -6495,23 +6481,21 @@ pub unsafe fn _mm_getmant_ps( /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_getmant_ps&expand=2875) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[cfg_attr(test, assert_instr(vgetmantps, norm = 0, sign = 0))] -#[rustc_args_required_const(3, 4)] -pub unsafe fn _mm_mask_getmant_ps( +#[cfg_attr(test, assert_instr(vgetmantps, NORM = 0, SIGN = 0))] +#[rustc_legacy_const_generics(3, 4)] +pub unsafe fn _mm_mask_getmant_ps< + const NORM: _MM_MANTISSA_NORM_ENUM, + const SIGN: _MM_MANTISSA_SIGN_ENUM, +>( src: __m128, k: __mmask8, a: __m128, - norm: _MM_MANTISSA_NORM_ENUM, - sign: _MM_MANTISSA_SIGN_ENUM, ) -> __m128 { + static_assert_imm4!(NORM); + static_assert_imm2!(SIGN); let a = a.as_f32x4(); let src = src.as_f32x4(); - macro_rules! call { - ($imm4:expr, $imm2:expr) => { - vgetmantps128(a, $imm2 << 2 | $imm4, src, k) - }; - } - let r = constify_imm4_mantissas!(norm, sign, call); + let r = vgetmantps128(a, SIGN << 2 | NORM, src, k); transmute(r) } @@ -6529,22 +6513,20 @@ pub unsafe fn _mm_mask_getmant_ps( /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_getmant_ps&expand=2876) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[cfg_attr(test, assert_instr(vgetmantps, norm = 0, sign = 0))] -#[rustc_args_required_const(2, 3)] -pub unsafe fn _mm_maskz_getmant_ps( +#[cfg_attr(test, assert_instr(vgetmantps, NORM = 0, SIGN = 0))] +#[rustc_legacy_const_generics(2, 3)] +pub unsafe fn _mm_maskz_getmant_ps< + const NORM: _MM_MANTISSA_NORM_ENUM, + const SIGN: _MM_MANTISSA_SIGN_ENUM, +>( k: __mmask8, a: __m128, - norm: _MM_MANTISSA_NORM_ENUM, - sign: _MM_MANTISSA_SIGN_ENUM, ) -> __m128 { + static_assert_imm4!(NORM); + static_assert_imm2!(SIGN); let a = a.as_f32x4(); let zero = _mm_setzero_ps().as_f32x4(); - macro_rules! call { - ($imm4:expr, $imm2:expr) => { - vgetmantps128(a, $imm2 << 2 | $imm4, zero, k) - }; - } - let r = constify_imm4_mantissas!(norm, sign, call); + let r = vgetmantps128(a, SIGN << 2 | NORM, zero, k); transmute(r) } @@ -6562,27 +6544,25 @@ pub unsafe fn _mm_maskz_getmant_ps( /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_getmant_pd&expand=2871) #[inline] #[target_feature(enable = "avx512f")] -#[cfg_attr(test, assert_instr(vgetmantpd, norm = 0, sign = 0))] -#[rustc_args_required_const(1, 2)] -pub unsafe fn _mm512_getmant_pd( +#[cfg_attr(test, assert_instr(vgetmantpd, NORM = 0, SIGN = 0))] +#[rustc_legacy_const_generics(1, 2)] +pub unsafe fn _mm512_getmant_pd< + const NORM: _MM_MANTISSA_NORM_ENUM, + const SIGN: _MM_MANTISSA_SIGN_ENUM, +>( a: __m512d, - norm: _MM_MANTISSA_NORM_ENUM, - sign: _MM_MANTISSA_SIGN_ENUM, ) -> __m512d { + static_assert_imm4!(NORM); + static_assert_imm2!(SIGN); let a = a.as_f64x8(); let zero = _mm512_setzero_pd().as_f64x8(); - macro_rules! call { - ($imm4:expr, $imm2:expr) => { - vgetmantpd( - a, - $imm2 << 2 | $imm4, - zero, - 0b11111111, - _MM_FROUND_CUR_DIRECTION, - ) - }; - } - let r = constify_imm4_mantissas!(norm, sign, call); + let r = vgetmantpd( + a, + SIGN << 2 | NORM, + zero, + 0b11111111, + _MM_FROUND_CUR_DIRECTION, + ); transmute(r) } @@ -6600,23 +6580,21 @@ pub unsafe fn _mm512_getmant_pd( /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_getmant_pd&expand=2872) #[inline] #[target_feature(enable = "avx512f")] -#[cfg_attr(test, assert_instr(vgetmantpd, norm = 0, sign = 0))] -#[rustc_args_required_const(3, 4)] -pub unsafe fn _mm512_mask_getmant_pd( +#[cfg_attr(test, assert_instr(vgetmantpd, NORM = 0, SIGN = 0))] +#[rustc_legacy_const_generics(3, 4)] +pub unsafe fn _mm512_mask_getmant_pd< + const NORM: _MM_MANTISSA_NORM_ENUM, + const SIGN: _MM_MANTISSA_SIGN_ENUM, +>( src: __m512d, k: __mmask8, a: __m512d, - norm: _MM_MANTISSA_NORM_ENUM, - sign: _MM_MANTISSA_SIGN_ENUM, ) -> __m512d { + static_assert_imm4!(NORM); + static_assert_imm2!(SIGN); let a = a.as_f64x8(); let src = src.as_f64x8(); - macro_rules! call { - ($imm4:expr, $imm2:expr) => { - vgetmantpd(a, $imm2 << 2 | $imm4, src, k, _MM_FROUND_CUR_DIRECTION) - }; - } - let r = constify_imm4_mantissas!(norm, sign, call); + let r = vgetmantpd(a, SIGN << 2 | NORM, src, k, _MM_FROUND_CUR_DIRECTION); transmute(r) } @@ -6634,22 +6612,20 @@ pub unsafe fn _mm512_mask_getmant_pd( /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_getmant_pd&expand=2873) #[inline] #[target_feature(enable = "avx512f")] -#[cfg_attr(test, assert_instr(vgetmantpd, norm = 0, sign = 0))] -#[rustc_args_required_const(2, 3)] -pub unsafe fn _mm512_maskz_getmant_pd( +#[cfg_attr(test, assert_instr(vgetmantpd, NORM = 0, SIGN = 0))] +#[rustc_legacy_const_generics(2, 3)] +pub unsafe fn _mm512_maskz_getmant_pd< + const NORM: _MM_MANTISSA_NORM_ENUM, + const SIGN: _MM_MANTISSA_SIGN_ENUM, +>( k: __mmask8, a: __m512d, - norm: _MM_MANTISSA_NORM_ENUM, - sign: _MM_MANTISSA_SIGN_ENUM, ) -> __m512d { + static_assert_imm4!(NORM); + static_assert_imm2!(SIGN); let a = a.as_f64x8(); let zero = _mm512_setzero_pd().as_f64x8(); - macro_rules! call { - ($imm4:expr, $imm2:expr) => { - vgetmantpd(a, $imm2 << 2 | $imm4, zero, k, _MM_FROUND_CUR_DIRECTION) - }; - } - let r = constify_imm4_mantissas!(norm, sign, call); + let r = vgetmantpd(a, SIGN << 2 | NORM, zero, k, _MM_FROUND_CUR_DIRECTION); transmute(r) } @@ -6667,21 +6643,19 @@ pub unsafe fn _mm512_maskz_getmant_pd( /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_getmant_pd&expand=2868) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[cfg_attr(test, assert_instr(vgetmantpd, norm = 0, sign = 0))] -#[rustc_args_required_const(1, 2)] -pub unsafe fn _mm256_getmant_pd( +#[cfg_attr(test, assert_instr(vgetmantpd, NORM = 0, SIGN = 0))] +#[rustc_legacy_const_generics(1, 2)] +pub unsafe fn _mm256_getmant_pd< + const NORM: _MM_MANTISSA_NORM_ENUM, + const SIGN: _MM_MANTISSA_SIGN_ENUM, +>( a: __m256d, - norm: _MM_MANTISSA_NORM_ENUM, - sign: _MM_MANTISSA_SIGN_ENUM, ) -> __m256d { + static_assert_imm4!(NORM); + static_assert_imm2!(SIGN); let a = a.as_f64x4(); let zero = _mm256_setzero_pd().as_f64x4(); - macro_rules! call { - ($imm4:expr, $imm2:expr) => { - vgetmantpd256(a, $imm2 << 2 | $imm4, zero, 0b00001111) - }; - } - let r = constify_imm4_mantissas!(norm, sign, call); + let r = vgetmantpd256(a, SIGN << 2 | NORM, zero, 0b00001111); transmute(r) } @@ -6699,23 +6673,21 @@ pub unsafe fn _mm256_getmant_pd( /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mask_getmant_pd&expand=2869) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[cfg_attr(test, assert_instr(vgetmantpd, norm = 0, sign = 0))] -#[rustc_args_required_const(3, 4)] -pub unsafe fn _mm256_mask_getmant_pd( +#[cfg_attr(test, assert_instr(vgetmantpd, NORM = 0, SIGN = 0))] +#[rustc_legacy_const_generics(3, 4)] +pub unsafe fn _mm256_mask_getmant_pd< + const NORM: _MM_MANTISSA_NORM_ENUM, + const SIGN: _MM_MANTISSA_SIGN_ENUM, +>( src: __m256d, k: __mmask8, a: __m256d, - norm: _MM_MANTISSA_NORM_ENUM, - sign: _MM_MANTISSA_SIGN_ENUM, ) -> __m256d { + static_assert_imm4!(NORM); + static_assert_imm2!(SIGN); let a = a.as_f64x4(); let src = src.as_f64x4(); - macro_rules! call { - ($imm4:expr, $imm2:expr) => { - vgetmantpd256(a, $imm2 << 2 | $imm4, src, k) - }; - } - let r = constify_imm4_mantissas!(norm, sign, call); + let r = vgetmantpd256(a, SIGN << 2 | NORM, src, k); transmute(r) } @@ -6733,22 +6705,20 @@ pub unsafe fn _mm256_mask_getmant_pd( /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_maskz_getmant_pd&expand=2870) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[cfg_attr(test, assert_instr(vgetmantpd, norm = 0, sign = 0))] -#[rustc_args_required_const(2, 3)] -pub unsafe fn _mm256_maskz_getmant_pd( +#[cfg_attr(test, assert_instr(vgetmantpd, NORM = 0, SIGN = 0))] +#[rustc_legacy_const_generics(2, 3)] +pub unsafe fn _mm256_maskz_getmant_pd< + const NORM: _MM_MANTISSA_NORM_ENUM, + const SIGN: _MM_MANTISSA_SIGN_ENUM, +>( k: __mmask8, a: __m256d, - norm: _MM_MANTISSA_NORM_ENUM, - sign: _MM_MANTISSA_SIGN_ENUM, ) -> __m256d { + static_assert_imm4!(NORM); + static_assert_imm2!(SIGN); let a = a.as_f64x4(); let zero = _mm256_setzero_pd().as_f64x4(); - macro_rules! call { - ($imm4:expr, $imm2:expr) => { - vgetmantpd256(a, $imm2 << 2 | $imm4, zero, k) - }; - } - let r = constify_imm4_mantissas!(norm, sign, call); + let r = vgetmantpd256(a, SIGN << 2 | NORM, zero, k); transmute(r) } @@ -6766,21 +6736,19 @@ pub unsafe fn _mm256_maskz_getmant_pd( /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_getmant_pd&expand=2865) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[cfg_attr(test, assert_instr(vgetmantpd, norm = 0, sign = 0))] -#[rustc_args_required_const(1, 2)] -pub unsafe fn _mm_getmant_pd( +#[cfg_attr(test, assert_instr(vgetmantpd, NORM = 0, SIGN = 0))] +#[rustc_legacy_const_generics(1, 2)] +pub unsafe fn _mm_getmant_pd< + const NORM: _MM_MANTISSA_NORM_ENUM, + const SIGN: _MM_MANTISSA_SIGN_ENUM, +>( a: __m128d, - norm: _MM_MANTISSA_NORM_ENUM, - sign: _MM_MANTISSA_SIGN_ENUM, ) -> __m128d { + static_assert_imm4!(NORM); + static_assert_imm2!(SIGN); let a = a.as_f64x2(); let zero = _mm_setzero_pd().as_f64x2(); - macro_rules! call { - ($imm4:expr, $imm2:expr) => { - vgetmantpd128(a, $imm2 << 2 | $imm4, zero, 0b00000011) - }; - } - let r = constify_imm4_mantissas!(norm, sign, call); + let r = vgetmantpd128(a, SIGN << 2 | NORM, zero, 0b00000011); transmute(r) } @@ -6798,23 +6766,21 @@ pub unsafe fn _mm_getmant_pd( /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_getmant_pd&expand=2866) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[cfg_attr(test, assert_instr(vgetmantpd, norm = 0, sign = 0))] -#[rustc_args_required_const(3, 4)] -pub unsafe fn _mm_mask_getmant_pd( +#[cfg_attr(test, assert_instr(vgetmantpd, NORM = 0, SIGN = 0))] +#[rustc_legacy_const_generics(3, 4)] +pub unsafe fn _mm_mask_getmant_pd< + const NORM: _MM_MANTISSA_NORM_ENUM, + const SIGN: _MM_MANTISSA_SIGN_ENUM, +>( src: __m128d, k: __mmask8, a: __m128d, - norm: _MM_MANTISSA_NORM_ENUM, - sign: _MM_MANTISSA_SIGN_ENUM, ) -> __m128d { + static_assert_imm4!(NORM); + static_assert_imm2!(SIGN); let a = a.as_f64x2(); let src = src.as_f64x2(); - macro_rules! call { - ($imm4:expr, $imm2:expr) => { - vgetmantpd128(a, $imm2 << 2 | $imm4, src, k) - }; - } - let r = constify_imm4_mantissas!(norm, sign, call); + let r = vgetmantpd128(a, SIGN << 2 | NORM, src, k); transmute(r) } @@ -6832,22 +6798,20 @@ pub unsafe fn _mm_mask_getmant_pd( /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_getmant_pd&expand=2867) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[cfg_attr(test, assert_instr(vgetmantpd, norm = 0, sign = 0))] -#[rustc_args_required_const(2, 3)] -pub unsafe fn _mm_maskz_getmant_pd( +#[cfg_attr(test, assert_instr(vgetmantpd, NORM = 0, SIGN = 0))] +#[rustc_legacy_const_generics(2, 3)] +pub unsafe fn _mm_maskz_getmant_pd< + const NORM: _MM_MANTISSA_NORM_ENUM, + const SIGN: _MM_MANTISSA_SIGN_ENUM, +>( k: __mmask8, a: __m128d, - norm: _MM_MANTISSA_NORM_ENUM, - sign: _MM_MANTISSA_SIGN_ENUM, ) -> __m128d { + static_assert_imm4!(NORM); + static_assert_imm2!(SIGN); let a = a.as_f64x2(); let zero = _mm_setzero_pd().as_f64x2(); - macro_rules! call { - ($imm4:expr, $imm2:expr) => { - vgetmantpd128(a, $imm2 << 2 | $imm4, zero, k) - }; - } - let r = constify_imm4_mantissas!(norm, sign, call); + let r = vgetmantpd128(a, SIGN << 2 | NORM, zero, k); transmute(r) } @@ -9320,17 +9284,14 @@ pub unsafe fn _mm512_maskz_getexp_round_pd(k: __mmask8, a: __m51 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_roundscale_round_ps&expand=4790) #[inline] #[target_feature(enable = "avx512f")] -#[cfg_attr(test, assert_instr(vrndscaleps, imm8 = 0, sae = 8))] -#[rustc_args_required_const(1, 2)] -pub unsafe fn _mm512_roundscale_round_ps(a: __m512, imm8: i32, sae: i32) -> __m512 { +#[cfg_attr(test, assert_instr(vrndscaleps, IMM8 = 0, SAE = 8))] +#[rustc_legacy_const_generics(1, 2)] +pub unsafe fn _mm512_roundscale_round_ps(a: __m512) -> __m512 { + static_assert_imm8!(IMM8); + static_assert_mantissas_sae!(SAE); let a = a.as_f32x16(); let zero = _mm512_setzero_ps().as_f32x16(); - macro_rules! call { - ($imm8:expr, $imm4:expr) => { - vrndscaleps(a, $imm8, zero, 0b11111111_11111111, $imm4) - }; - } - let r = constify_imm8_roundscale!(imm8, sae, call); + let r = vrndscaleps(a, IMM8, zero, 0b11111111_11111111, SAE); transmute(r) } @@ -9346,23 +9307,18 @@ pub unsafe fn _mm512_roundscale_round_ps(a: __m512, imm8: i32, sae: i32) -> __m5 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_roundscale_round_ps&expand=4788) #[inline] #[target_feature(enable = "avx512f")] -#[cfg_attr(test, assert_instr(vrndscaleps, imm8 = 0, sae = 8))] -#[rustc_args_required_const(3, 4)] -pub unsafe fn _mm512_mask_roundscale_round_ps( +#[cfg_attr(test, assert_instr(vrndscaleps, IMM8 = 0, SAE = 8))] +#[rustc_legacy_const_generics(3, 4)] +pub unsafe fn _mm512_mask_roundscale_round_ps( src: __m512, k: __mmask16, a: __m512, - imm8: i32, - sae: i32, ) -> __m512 { + static_assert_imm8!(IMM8); + static_assert_mantissas_sae!(SAE); let a = a.as_f32x16(); let src = src.as_f32x16(); - macro_rules! call { - ($imm8:expr, $imm4:expr) => { - vrndscaleps(a, $imm8, src, k, $imm4) - }; - } - let r = constify_imm8_roundscale!(imm8, sae, call); + let r = vrndscaleps(a, IMM8, src, k, SAE); transmute(r) } @@ -9378,22 +9334,17 @@ pub unsafe fn _mm512_mask_roundscale_round_ps( /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_roundscale_round_ps&expand=4789) #[inline] #[target_feature(enable = "avx512f")] -#[cfg_attr(test, assert_instr(vrndscaleps, imm8 = 0, sae = 8))] -#[rustc_args_required_const(2, 3)] -pub unsafe fn _mm512_maskz_roundscale_round_ps( +#[cfg_attr(test, assert_instr(vrndscaleps, IMM8 = 0, SAE = 8))] +#[rustc_legacy_const_generics(2, 3)] +pub unsafe fn _mm512_maskz_roundscale_round_ps( k: __mmask16, a: __m512, - imm8: i32, - sae: i32, ) -> __m512 { + static_assert_imm8!(IMM8); + static_assert_mantissas_sae!(SAE); let a = a.as_f32x16(); let zero = _mm512_setzero_ps().as_f32x16(); - macro_rules! call { - ($imm8:expr, $imm4:expr) => { - vrndscaleps(a, $imm8, zero, k, $imm4) - }; - } - let r = constify_imm8_roundscale!(imm8, sae, call); + let r = vrndscaleps(a, IMM8, zero, k, SAE); transmute(r) } @@ -9409,17 +9360,14 @@ pub unsafe fn _mm512_maskz_roundscale_round_ps( /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_roundscale_round_pd&expand=4787) #[inline] #[target_feature(enable = "avx512f")] -#[cfg_attr(test, assert_instr(vrndscalepd, imm8 = 0, sae = 8))] -#[rustc_args_required_const(1, 2)] -pub unsafe fn _mm512_roundscale_round_pd(a: __m512d, imm8: i32, sae: i32) -> __m512d { +#[cfg_attr(test, assert_instr(vrndscalepd, IMM8 = 0, SAE = 8))] +#[rustc_legacy_const_generics(1, 2)] +pub unsafe fn _mm512_roundscale_round_pd(a: __m512d) -> __m512d { + static_assert_imm8!(IMM8); + static_assert_mantissas_sae!(SAE); let a = a.as_f64x8(); let zero = _mm512_setzero_pd().as_f64x8(); - macro_rules! call { - ($imm8:expr, $imm4:expr) => { - vrndscalepd(a, $imm8, zero, 0b11111111, $imm4) - }; - } - let r = constify_imm8_roundscale!(imm8, sae, call); + let r = vrndscalepd(a, IMM8, zero, 0b11111111, SAE); transmute(r) } @@ -9435,23 +9383,18 @@ pub unsafe fn _mm512_roundscale_round_pd(a: __m512d, imm8: i32, sae: i32) -> __m /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_roundscale_round_pd&expand=4785) #[inline] #[target_feature(enable = "avx512f")] -#[cfg_attr(test, assert_instr(vrndscalepd, imm8 = 0, sae = 8))] -#[rustc_args_required_const(3, 4)] -pub unsafe fn _mm512_mask_roundscale_round_pd( +#[cfg_attr(test, assert_instr(vrndscalepd, IMM8 = 0, SAE = 8))] +#[rustc_legacy_const_generics(3, 4)] +pub unsafe fn _mm512_mask_roundscale_round_pd( src: __m512d, k: __mmask8, a: __m512d, - imm8: i32, - sae: i32, ) -> __m512d { + static_assert_imm8!(IMM8); + static_assert_mantissas_sae!(SAE); let a = a.as_f64x8(); let src = src.as_f64x8(); - macro_rules! call { - ($imm8:expr, $imm4:expr) => { - vrndscalepd(a, $imm8, src, k, $imm4) - }; - } - let r = constify_imm8_roundscale!(imm8, sae, call); + let r = vrndscalepd(a, IMM8, src, k, SAE); transmute(r) } @@ -9467,22 +9410,17 @@ pub unsafe fn _mm512_mask_roundscale_round_pd( /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_roundscale_round_pd&expand=4786) #[inline] #[target_feature(enable = "avx512f")] -#[cfg_attr(test, assert_instr(vrndscalepd, imm8 = 0, sae = 8))] -#[rustc_args_required_const(2, 3)] -pub unsafe fn _mm512_maskz_roundscale_round_pd( +#[cfg_attr(test, assert_instr(vrndscalepd, IMM8 = 0, SAE = 8))] +#[rustc_legacy_const_generics(2, 3)] +pub unsafe fn _mm512_maskz_roundscale_round_pd( k: __mmask8, a: __m512d, - imm8: i32, - sae: i32, ) -> __m512d { + static_assert_imm8!(IMM8); + static_assert_mantissas_sae!(SAE); let a = a.as_f64x8(); let zero = _mm512_setzero_pd().as_f64x8(); - macro_rules! call { - ($imm8:expr, $imm4:expr) => { - vrndscalepd(a, $imm8, zero, k, $imm4) - }; - } - let r = constify_imm8_roundscale!(imm8, sae, call); + let r = vrndscalepd(a, IMM8, zero, k, SAE); transmute(r) } @@ -9648,24 +9586,19 @@ pub unsafe fn _mm512_maskz_scalef_round_pd( /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_fixupimm_round_ps&expand=2505) #[inline] #[target_feature(enable = "avx512f")] -#[cfg_attr(test, assert_instr(vfixupimmps, imm8 = 0, sae = 8))] -#[rustc_args_required_const(3, 4)] -pub unsafe fn _mm512_fixupimm_round_ps( +#[cfg_attr(test, assert_instr(vfixupimmps, IMM8 = 0, SAE = 8))] +#[rustc_legacy_const_generics(3, 4)] +pub unsafe fn _mm512_fixupimm_round_ps( a: __m512, b: __m512, c: __m512i, - imm8: i32, - sae: i32, ) -> __m512 { + static_assert_imm8!(IMM8); + static_assert_mantissas_sae!(SAE); let a = a.as_f32x16(); let b = b.as_f32x16(); let c = c.as_i32x16(); - macro_rules! call { - ($imm8:expr, $imm4:expr) => { - vfixupimmps(a, b, c, $imm8, 0b11111111_11111111, $imm4) - }; - } - let r = constify_imm8_roundscale!(imm8, sae, call); + let r = vfixupimmps(a, b, c, IMM8, 0b11111111_11111111, SAE); transmute(r) } @@ -9675,25 +9608,20 @@ pub unsafe fn _mm512_fixupimm_round_ps( /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_fixupimm_round_ps&expand=2506) #[inline] #[target_feature(enable = "avx512f")] -#[cfg_attr(test, assert_instr(vfixupimmps, imm8 = 0, sae = 8))] -#[rustc_args_required_const(4, 5)] -pub unsafe fn _mm512_mask_fixupimm_round_ps( +#[cfg_attr(test, assert_instr(vfixupimmps, IMM8 = 0, SAE = 8))] +#[rustc_legacy_const_generics(4, 5)] +pub unsafe fn _mm512_mask_fixupimm_round_ps( a: __m512, k: __mmask16, b: __m512, c: __m512i, - imm8: i32, - sae: i32, ) -> __m512 { + static_assert_imm8!(IMM8); + static_assert_mantissas_sae!(SAE); let a = a.as_f32x16(); let b = b.as_f32x16(); let c = c.as_i32x16(); - macro_rules! call { - ($imm8:expr, $imm4:expr) => { - vfixupimmps(a, b, c, $imm8, k, $imm4) - }; - } - let r = constify_imm8_roundscale!(imm8, sae, call); + let r = vfixupimmps(a, b, c, IMM8, k, SAE); transmute(r) } @@ -9703,25 +9631,20 @@ pub unsafe fn _mm512_mask_fixupimm_round_ps( /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_fixupimm_round_ps&expand=2507) #[inline] #[target_feature(enable = "avx512f")] -#[cfg_attr(test, assert_instr(vfixupimmps, imm8 = 0, sae = 8))] -#[rustc_args_required_const(4, 5)] -pub unsafe fn _mm512_maskz_fixupimm_round_ps( +#[cfg_attr(test, assert_instr(vfixupimmps, IMM8 = 0, SAE = 8))] +#[rustc_legacy_const_generics(4, 5)] +pub unsafe fn _mm512_maskz_fixupimm_round_ps( k: __mmask16, a: __m512, b: __m512, c: __m512i, - imm8: i32, - sae: i32, ) -> __m512 { + static_assert_imm8!(IMM8); + static_assert_mantissas_sae!(SAE); let a = a.as_f32x16(); let b = b.as_f32x16(); let c = c.as_i32x16(); - macro_rules! call { - ($imm8:expr, $imm4:expr) => { - vfixupimmpsz(a, b, c, $imm8, k, $imm4) - }; - } - let r = constify_imm8_roundscale!(imm8, sae, call); + let r = vfixupimmpsz(a, b, c, IMM8, k, SAE); transmute(r) } @@ -9731,24 +9654,19 @@ pub unsafe fn _mm512_maskz_fixupimm_round_ps( /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_fixupimm_round_pd&expand=2502) #[inline] #[target_feature(enable = "avx512f")] -#[cfg_attr(test, assert_instr(vfixupimmpd, imm8 = 0, sae = 8))] -#[rustc_args_required_const(3, 4)] -pub unsafe fn _mm512_fixupimm_round_pd( +#[cfg_attr(test, assert_instr(vfixupimmpd, IMM8 = 0, SAE = 8))] +#[rustc_legacy_const_generics(3, 4)] +pub unsafe fn _mm512_fixupimm_round_pd( a: __m512d, b: __m512d, c: __m512i, - imm8: i32, - sae: i32, ) -> __m512d { + static_assert_imm8!(IMM8); + static_assert_mantissas_sae!(SAE); let a = a.as_f64x8(); let b = b.as_f64x8(); let c = c.as_i64x8(); - macro_rules! call { - ($imm8:expr, $imm4:expr) => { - vfixupimmpd(a, b, c, $imm8, 0b11111111, $imm4) - }; - } - let r = constify_imm8_roundscale!(imm8, sae, call); + let r = vfixupimmpd(a, b, c, IMM8, 0b11111111, SAE); transmute(r) } @@ -9758,25 +9676,20 @@ pub unsafe fn _mm512_fixupimm_round_pd( /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_fixupimm_round_pd&expand=2503) #[inline] #[target_feature(enable = "avx512f")] -#[cfg_attr(test, assert_instr(vfixupimmpd, imm8 = 0, sae = 8))] -#[rustc_args_required_const(4, 5)] -pub unsafe fn _mm512_mask_fixupimm_round_pd( +#[cfg_attr(test, assert_instr(vfixupimmpd, IMM8 = 0, SAE = 8))] +#[rustc_legacy_const_generics(4, 5)] +pub unsafe fn _mm512_mask_fixupimm_round_pd( a: __m512d, k: __mmask8, b: __m512d, c: __m512i, - imm8: i32, - sae: i32, ) -> __m512d { + static_assert_imm8!(IMM8); + static_assert_mantissas_sae!(SAE); let a = a.as_f64x8(); let b = b.as_f64x8(); let c = c.as_i64x8(); - macro_rules! call { - ($imm8:expr, $imm4:expr) => { - vfixupimmpd(a, b, c, $imm8, k, $imm4) - }; - } - let r = constify_imm8_roundscale!(imm8, sae, call); + let r = vfixupimmpd(a, b, c, IMM8, k, SAE); transmute(r) } @@ -9786,25 +9699,20 @@ pub unsafe fn _mm512_mask_fixupimm_round_pd( /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_fixupimm_round_pd&expand=2504) #[inline] #[target_feature(enable = "avx512f")] -#[cfg_attr(test, assert_instr(vfixupimmpd, imm8 = 0, sae = 8))] -#[rustc_args_required_const(4, 5)] -pub unsafe fn _mm512_maskz_fixupimm_round_pd( +#[cfg_attr(test, assert_instr(vfixupimmpd, IMM8 = 0, SAE = 8))] +#[rustc_legacy_const_generics(4, 5)] +pub unsafe fn _mm512_maskz_fixupimm_round_pd( k: __mmask8, a: __m512d, b: __m512d, c: __m512i, - imm8: i32, - sae: i32, ) -> __m512d { + static_assert_imm8!(IMM8); + static_assert_mantissas_sae!(SAE); let a = a.as_f64x8(); let b = b.as_f64x8(); let c = c.as_i64x8(); - macro_rules! call { - ($imm8:expr, $imm4:expr) => { - vfixupimmpdz(a, b, c, $imm8, k, $imm4) - }; - } - let r = constify_imm8_roundscale!(imm8, sae, call); + let r = vfixupimmpdz(a, b, c, IMM8, k, SAE); transmute(r) } @@ -9823,22 +9731,21 @@ pub unsafe fn _mm512_maskz_fixupimm_round_pd( /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_getmant_round_ps&expand=2886) #[inline] #[target_feature(enable = "avx512f")] -#[cfg_attr(test, assert_instr(vgetmantps, norm = 0, sign = 0, sae = 4))] -#[rustc_args_required_const(1, 2, 3)] -pub unsafe fn _mm512_getmant_round_ps( +#[cfg_attr(test, assert_instr(vgetmantps, NORM = 0, SIGN = 0, SAE = 4))] +#[rustc_legacy_const_generics(1, 2, 3)] +pub unsafe fn _mm512_getmant_round_ps< + const NORM: _MM_MANTISSA_NORM_ENUM, + const SIGN: _MM_MANTISSA_SIGN_ENUM, + const SAE: i32, +>( a: __m512, - norm: _MM_MANTISSA_NORM_ENUM, - sign: _MM_MANTISSA_SIGN_ENUM, - sae: i32, ) -> __m512 { + static_assert_imm4!(NORM); + static_assert_imm2!(SIGN); + static_assert_mantissas_sae!(SAE); let a = a.as_f32x16(); let zero = _mm512_setzero_ps().as_f32x16(); - macro_rules! call { - ($imm4_1:expr, $imm2:expr, $imm4_2:expr) => { - vgetmantps(a, $imm2 << 2 | $imm4_1, zero, 0b11111111_11111111, $imm4_2) - }; - } - let r = constify_imm4_mantissas_sae!(norm, sign, sae, call); + let r = vgetmantps(a, SIGN << 2 | NORM, zero, 0b11111111_11111111, SAE); transmute(r) } @@ -9857,24 +9764,23 @@ pub unsafe fn _mm512_getmant_round_ps( /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_getmant_round_ps&expand=2887) #[inline] #[target_feature(enable = "avx512f")] -#[cfg_attr(test, assert_instr(vgetmantps, norm = 0, sign = 0, sae = 4))] -#[rustc_args_required_const(3, 4, 5)] -pub unsafe fn _mm512_mask_getmant_round_ps( +#[cfg_attr(test, assert_instr(vgetmantps, NORM = 0, SIGN = 0, SAE = 4))] +#[rustc_legacy_const_generics(3, 4, 5)] +pub unsafe fn _mm512_mask_getmant_round_ps< + const NORM: _MM_MANTISSA_NORM_ENUM, + const SIGN: _MM_MANTISSA_SIGN_ENUM, + const SAE: i32, +>( src: __m512, k: __mmask16, a: __m512, - norm: _MM_MANTISSA_NORM_ENUM, - sign: _MM_MANTISSA_SIGN_ENUM, - sae: i32, ) -> __m512 { + static_assert_imm4!(NORM); + static_assert_imm2!(SIGN); + static_assert_mantissas_sae!(SAE); let a = a.as_f32x16(); let src = src.as_f32x16(); - macro_rules! call { - ($imm4_1:expr, $imm2:expr, $imm4_2:expr) => { - vgetmantps(a, $imm2 << 2 | $imm4_1, src, k, $imm4_2) - }; - } - let r = constify_imm4_mantissas_sae!(norm, sign, sae, call); + let r = vgetmantps(a, SIGN << 2 | NORM, src, k, SAE); transmute(r) } @@ -9893,23 +9799,22 @@ pub unsafe fn _mm512_mask_getmant_round_ps( /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_getmant_round_ps&expand=2888) #[inline] #[target_feature(enable = "avx512f")] -#[cfg_attr(test, assert_instr(vgetmantps, norm = 0, sign = 0, sae = 4))] -#[rustc_args_required_const(2, 3, 4)] -pub unsafe fn _mm512_maskz_getmant_round_ps( +#[cfg_attr(test, assert_instr(vgetmantps, NORM = 0, SIGN = 0, SAE = 4))] +#[rustc_legacy_const_generics(2, 3, 4)] +pub unsafe fn _mm512_maskz_getmant_round_ps< + const NORM: _MM_MANTISSA_NORM_ENUM, + const SIGN: _MM_MANTISSA_SIGN_ENUM, + const SAE: i32, +>( k: __mmask16, a: __m512, - norm: _MM_MANTISSA_NORM_ENUM, - sign: _MM_MANTISSA_SIGN_ENUM, - sae: i32, ) -> __m512 { + static_assert_imm4!(NORM); + static_assert_imm2!(SIGN); + static_assert_mantissas_sae!(SAE); let a = a.as_f32x16(); let zero = _mm512_setzero_ps().as_f32x16(); - macro_rules! call { - ($imm4_1:expr, $imm2:expr, $imm4_2:expr) => { - vgetmantps(a, $imm2 << 2 | $imm4_1, zero, k, $imm4_2) - }; - } - let r = constify_imm4_mantissas_sae!(norm, sign, sae, call); + let r = vgetmantps(a, SIGN << 2 | NORM, zero, k, SAE); transmute(r) } @@ -9928,22 +9833,21 @@ pub unsafe fn _mm512_maskz_getmant_round_ps( /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_getmant_round_pd&expand=2883) #[inline] #[target_feature(enable = "avx512f")] -#[cfg_attr(test, assert_instr(vgetmantpd, norm = 0, sign = 0, sae = 4))] -#[rustc_args_required_const(1, 2, 3)] -pub unsafe fn _mm512_getmant_round_pd( +#[cfg_attr(test, assert_instr(vgetmantpd, NORM = 0, SIGN = 0, SAE = 4))] +#[rustc_legacy_const_generics(1, 2, 3)] +pub unsafe fn _mm512_getmant_round_pd< + const NORM: _MM_MANTISSA_NORM_ENUM, + const SIGN: _MM_MANTISSA_SIGN_ENUM, + const SAE: i32, +>( a: __m512d, - norm: _MM_MANTISSA_NORM_ENUM, - sign: _MM_MANTISSA_SIGN_ENUM, - sae: i32, ) -> __m512d { + static_assert_imm4!(NORM); + static_assert_imm2!(SIGN); + static_assert_mantissas_sae!(SAE); let a = a.as_f64x8(); let zero = _mm512_setzero_pd().as_f64x8(); - macro_rules! call { - ($imm4_1:expr, $imm2:expr, $imm4_2:expr) => { - vgetmantpd(a, $imm2 << 2 | $imm4_1, zero, 0b11111111, $imm4_2) - }; - } - let r = constify_imm4_mantissas_sae!(norm, sign, sae, call); + let r = vgetmantpd(a, SIGN << 2 | NORM, zero, 0b11111111, SAE); transmute(r) } @@ -9962,24 +9866,23 @@ pub unsafe fn _mm512_getmant_round_pd( /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_getmant_round_pd&expand=2884) #[inline] #[target_feature(enable = "avx512f")] -#[cfg_attr(test, assert_instr(vgetmantpd, norm = 0, sign = 0, sae = 4))] -#[rustc_args_required_const(3, 4, 5)] -pub unsafe fn _mm512_mask_getmant_round_pd( +#[cfg_attr(test, assert_instr(vgetmantpd, NORM = 0, SIGN = 0, SAE = 4))] +#[rustc_legacy_const_generics(3, 4, 5)] +pub unsafe fn _mm512_mask_getmant_round_pd< + const NORM: _MM_MANTISSA_NORM_ENUM, + const SIGN: _MM_MANTISSA_SIGN_ENUM, + const SAE: i32, +>( src: __m512d, k: __mmask8, a: __m512d, - norm: _MM_MANTISSA_NORM_ENUM, - sign: _MM_MANTISSA_SIGN_ENUM, - sae: i32, ) -> __m512d { + static_assert_imm4!(NORM); + static_assert_imm2!(SIGN); + static_assert_mantissas_sae!(SAE); let a = a.as_f64x8(); let src = src.as_f64x8(); - macro_rules! call { - ($imm4_1:expr, $imm2:expr, $imm4_2:expr) => { - vgetmantpd(a, $imm2 << 2 | $imm4_1, src, k, $imm4_2) - }; - } - let r = constify_imm4_mantissas_sae!(norm, sign, sae, call); + let r = vgetmantpd(a, SIGN << 2 | NORM, src, k, SAE); transmute(r) } @@ -9998,23 +9901,22 @@ pub unsafe fn _mm512_mask_getmant_round_pd( /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_512_maskz_getmant_round_pd&expand=2885) #[inline] #[target_feature(enable = "avx512f")] -#[cfg_attr(test, assert_instr(vgetmantpd, norm = 0, sign = 0, sae = 4))] -#[rustc_args_required_const(2, 3, 4)] -pub unsafe fn _mm512_maskz_getmant_round_pd( +#[cfg_attr(test, assert_instr(vgetmantpd, NORM = 0, SIGN = 0, SAE = 4))] +#[rustc_legacy_const_generics(2, 3, 4)] +pub unsafe fn _mm512_maskz_getmant_round_pd< + const NORM: _MM_MANTISSA_NORM_ENUM, + const SIGN: _MM_MANTISSA_SIGN_ENUM, + const SAE: i32, +>( k: __mmask8, a: __m512d, - norm: _MM_MANTISSA_NORM_ENUM, - sign: _MM_MANTISSA_SIGN_ENUM, - sae: i32, ) -> __m512d { + static_assert_imm4!(NORM); + static_assert_imm2!(SIGN); + static_assert_mantissas_sae!(SAE); let a = a.as_f64x8(); let zero = _mm512_setzero_pd().as_f64x8(); - macro_rules! call { - ($imm4_1:expr, $imm2:expr, $imm4_2:expr) => { - vgetmantpd(a, $imm2 << 2 | $imm4_1, zero, k, $imm4_2) - }; - } - let r = constify_imm4_mantissas_sae!(norm, sign, sae, call); + let r = vgetmantpd(a, SIGN << 2 | NORM, zero, k, SAE); transmute(r) } @@ -19506,73 +19408,32 @@ pub unsafe fn _mm_maskz_srlv_epi64(k: __mmask8, a: __m128i, count: __m128i) -> _ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_permute_ps&expand=4170) #[inline] #[target_feature(enable = "avx512f")] -#[cfg_attr(test, assert_instr(vpermilps, imm8 = 1))] -#[rustc_args_required_const(1)] -pub unsafe fn _mm512_permute_ps(a: __m512, imm8: i32) -> __m512 { - let imm8 = (imm8 & 0xFF) as u8; - let undefined = _mm512_undefined_ps(); - macro_rules! shuffle4 { - ($a:expr, $b:expr, $c:expr, $d:expr) => { - simd_shuffle16( - a, - undefined, - [ - $a, - $b, - $c, - $d, - $a + 4, - $b + 4, - $c + 4, - $d + 4, - $a + 8, - $b + 8, - $c + 8, - $d + 8, - $a + 12, - $b + 12, - $c + 12, - $d + 12, - ], - ) - }; - } - macro_rules! shuffle3 { - ($a:expr, $b:expr, $c:expr) => { - match (imm8 >> 6) & 0b11 { - 0b00 => shuffle4!($a, $b, $c, 0), - 0b01 => shuffle4!($a, $b, $c, 1), - 0b10 => shuffle4!($a, $b, $c, 2), - _ => shuffle4!($a, $b, $c, 3), - } - }; - } - macro_rules! shuffle2 { - ($a:expr, $b:expr) => { - match (imm8 >> 4) & 0b11 { - 0b00 => shuffle3!($a, $b, 0), - 0b01 => shuffle3!($a, $b, 1), - 0b10 => shuffle3!($a, $b, 2), - _ => shuffle3!($a, $b, 3), - } - }; - } - macro_rules! shuffle1 { - ($a:expr) => { - match (imm8 >> 2) & 0b11 { - 0b00 => shuffle2!($a, 0), - 0b01 => shuffle2!($a, 1), - 0b10 => shuffle2!($a, 2), - _ => shuffle2!($a, 3), - } - }; - } - match imm8 & 0b11 { - 0b00 => shuffle1!(0), - 0b01 => shuffle1!(1), - 0b10 => shuffle1!(2), - _ => shuffle1!(3), - } +#[cfg_attr(test, assert_instr(vpermilps, MASK = 0b11_00_01_11))] +#[rustc_legacy_const_generics(1)] +pub unsafe fn _mm512_permute_ps(a: __m512) -> __m512 { + static_assert_imm8!(MASK); + simd_shuffle16( + a, + a, + [ + MASK as u32 & 0b11, + (MASK as u32 >> 2) & 0b11, + ((MASK as u32 >> 4) & 0b11), + ((MASK as u32 >> 6) & 0b11), + (MASK as u32 & 0b11) + 4, + ((MASK as u32 >> 2) & 0b11) + 4, + ((MASK as u32 >> 4) & 0b11) + 4, + ((MASK as u32 >> 6) & 0b11) + 4, + (MASK as u32 & 0b11) + 8, + ((MASK as u32 >> 2) & 0b11) + 8, + ((MASK as u32 >> 4) & 0b11) + 8, + ((MASK as u32 >> 6) & 0b11) + 8, + (MASK as u32 & 0b11) + 12, + ((MASK as u32 >> 2) & 0b11) + 12, + ((MASK as u32 >> 4) & 0b11) + 12, + ((MASK as u32 >> 6) & 0b11) + 12, + ], + ) } /// Shuffle single-precision (32-bit) floating-point elements in a within 128-bit lanes using the control in imm8, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set). @@ -19580,15 +19441,15 @@ pub unsafe fn _mm512_permute_ps(a: __m512, imm8: i32) -> __m512 { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_permute_ps&expand=4168) #[inline] #[target_feature(enable = "avx512f")] -#[cfg_attr(test, assert_instr(vpermilps, imm8 = 1))] -#[rustc_args_required_const(3)] -pub unsafe fn _mm512_mask_permute_ps(src: __m512, k: __mmask16, a: __m512, imm8: i32) -> __m512 { - macro_rules! call { - ($imm8:expr) => { - _mm512_permute_ps(a, $imm8) - }; - } - let r = constify_imm8_sae!(imm8, call); +#[cfg_attr(test, assert_instr(vpermilps, MASK = 0b11_00_01_11))] +#[rustc_legacy_const_generics(3)] +pub unsafe fn _mm512_mask_permute_ps( + src: __m512, + k: __mmask16, + a: __m512, +) -> __m512 { + static_assert_imm8!(MASK); + let r = _mm512_permute_ps::(a); transmute(simd_select_bitmask(k, r.as_f32x16(), src.as_f32x16())) } @@ -19597,15 +19458,11 @@ pub unsafe fn _mm512_mask_permute_ps(src: __m512, k: __mmask16, a: __m512, imm8: /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_permute_ps&expand=4169) #[inline] #[target_feature(enable = "avx512f")] -#[cfg_attr(test, assert_instr(vpermilps, imm8 = 1))] -#[rustc_args_required_const(2)] -pub unsafe fn _mm512_maskz_permute_ps(k: __mmask16, a: __m512, imm8: i32) -> __m512 { - macro_rules! call { - ($imm8:expr) => { - _mm512_permute_ps(a, $imm8) - }; - } - let r = constify_imm8_sae!(imm8, call); +#[cfg_attr(test, assert_instr(vpermilps, MASK = 0b11_00_01_11))] +#[rustc_legacy_const_generics(2)] +pub unsafe fn _mm512_maskz_permute_ps(k: __mmask16, a: __m512) -> __m512 { + static_assert_imm8!(MASK); + let r = _mm512_permute_ps::(a); let zero = _mm512_setzero_ps().as_f32x16(); transmute(simd_select_bitmask(k, r.as_f32x16(), zero)) } @@ -19615,15 +19472,14 @@ pub unsafe fn _mm512_maskz_permute_ps(k: __mmask16, a: __m512, imm8: i32) -> __m /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mask_permute_ps&expand=4165) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[cfg_attr(test, assert_instr(vpermilps, imm8 = 1))] -#[rustc_args_required_const(3)] -pub unsafe fn _mm256_mask_permute_ps(src: __m256, k: __mmask8, a: __m256, imm8: i32) -> __m256 { - macro_rules! call { - ($imm8:expr) => { - _mm256_permute_ps::<$imm8>(a) - }; - } - let r = constify_imm8_sae!(imm8, call); +#[cfg_attr(test, assert_instr(vpermilps, MASK = 0b11_00_01_11))] +#[rustc_legacy_const_generics(3)] +pub unsafe fn _mm256_mask_permute_ps( + src: __m256, + k: __mmask8, + a: __m256, +) -> __m256 { + let r = _mm256_permute_ps::(a); transmute(simd_select_bitmask(k, r.as_f32x8(), src.as_f32x8())) } @@ -19632,15 +19488,10 @@ pub unsafe fn _mm256_mask_permute_ps(src: __m256, k: __mmask8, a: __m256, imm8: /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_maskz_permute_ps&expand=4166) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[cfg_attr(test, assert_instr(vpermilps, imm8 = 1))] -#[rustc_args_required_const(2)] -pub unsafe fn _mm256_maskz_permute_ps(k: __mmask8, a: __m256, imm8: i32) -> __m256 { - macro_rules! call { - ($imm8:expr) => { - _mm256_permute_ps::<$imm8>(a) - }; - } - let r = constify_imm8_sae!(imm8, call); +#[cfg_attr(test, assert_instr(vpermilps, MASK = 0b11_00_01_11))] +#[rustc_legacy_const_generics(2)] +pub unsafe fn _mm256_maskz_permute_ps(k: __mmask8, a: __m256) -> __m256 { + let r = _mm256_permute_ps::(a); let zero = _mm256_setzero_ps().as_f32x8(); transmute(simd_select_bitmask(k, r.as_f32x8(), zero)) } @@ -19650,15 +19501,10 @@ pub unsafe fn _mm256_maskz_permute_ps(k: __mmask8, a: __m256, imm8: i32) -> __m2 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_permute_ps&expand=4162) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[cfg_attr(test, assert_instr(vpermilps, imm8 = 1))] -#[rustc_args_required_const(3)] -pub unsafe fn _mm_mask_permute_ps(src: __m128, k: __mmask8, a: __m128, imm8: i32) -> __m128 { - macro_rules! call { - ($imm8:expr) => { - _mm_permute_ps::<$imm8>(a) - }; - } - let r = constify_imm8_sae!(imm8, call); +#[cfg_attr(test, assert_instr(vpermilps, MASK = 0b11_00_01_11))] +#[rustc_legacy_const_generics(3)] +pub unsafe fn _mm_mask_permute_ps(src: __m128, k: __mmask8, a: __m128) -> __m128 { + let r = _mm_permute_ps::(a); transmute(simd_select_bitmask(k, r.as_f32x4(), src.as_f32x4())) } @@ -19667,15 +19513,10 @@ pub unsafe fn _mm_mask_permute_ps(src: __m128, k: __mmask8, a: __m128, imm8: i32 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_permute_ps&expand=4163) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[cfg_attr(test, assert_instr(vpermilps, imm8 = 1))] -#[rustc_args_required_const(2)] -pub unsafe fn _mm_maskz_permute_ps(k: __mmask8, a: __m128, imm8: i32) -> __m128 { - macro_rules! call { - ($imm8:expr) => { - _mm_permute_ps::<$imm8>(a) - }; - } - let r = constify_imm8_sae!(imm8, call); +#[cfg_attr(test, assert_instr(vpermilps, MASK = 0b11_00_01_11))] +#[rustc_legacy_const_generics(2)] +pub unsafe fn _mm_maskz_permute_ps(k: __mmask8, a: __m128) -> __m128 { + let r = _mm_permute_ps::(a); let zero = _mm_setzero_ps().as_f32x4(); transmute(simd_select_bitmask(k, r.as_f32x4(), zero)) } @@ -19685,48 +19526,24 @@ pub unsafe fn _mm_maskz_permute_ps(k: __mmask8, a: __m128, imm8: i32) -> __m128 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_permute_pd&expand=4161) #[inline] #[target_feature(enable = "avx512f")] -#[cfg_attr(test, assert_instr(vpermilpd, imm8 = 2))] -#[rustc_args_required_const(1)] -pub unsafe fn _mm512_permute_pd(a: __m512d, imm8: i32) -> __m512d { - let imm8 = (imm8 & 0xFF) as u8; - let undefined = _mm512_undefined_pd(); - macro_rules! shuffle4 { - ($a:expr, $b:expr, $c:expr, $d:expr) => { - simd_shuffle8( - a, - undefined, - [$a, $b, $c, $d, $a + 4, $b + 4, $c + 4, $d + 4], - ) - }; - } - macro_rules! shuffle3 { - ($a:expr, $b:expr, $c:expr) => { - match (imm8 >> 3) & 0x1 { - 0 => shuffle4!($a, $b, $c, 2), - _ => shuffle4!($a, $b, $c, 3), - } - }; - } - macro_rules! shuffle2 { - ($a:expr, $b:expr) => { - match (imm8 >> 2) & 0x1 { - 0 => shuffle3!($a, $b, 2), - _ => shuffle3!($a, $b, 3), - } - }; - } - macro_rules! shuffle1 { - ($a:expr) => { - match (imm8 >> 1) & 0x1 { - 0 => shuffle2!($a, 0), - _ => shuffle2!($a, 1), - } - }; - } - match imm8 & 0x1 { - 0 => shuffle1!(0), - _ => shuffle1!(1), - } +#[cfg_attr(test, assert_instr(vpermilpd, MASK = 0b11_01_10_01))] +#[rustc_legacy_const_generics(1)] +pub unsafe fn _mm512_permute_pd(a: __m512d) -> __m512d { + static_assert_imm8!(MASK); + simd_shuffle8( + a, + a, + [ + MASK as u32 & 0b1, + ((MASK as u32 >> 1) & 0b1), + ((MASK as u32 >> 2) & 0b1) + 2, + ((MASK as u32 >> 3) & 0b1) + 2, + ((MASK as u32 >> 4) & 0b1) + 4, + ((MASK as u32 >> 5) & 0b1) + 4, + ((MASK as u32 >> 6) & 0b1) + 6, + ((MASK as u32 >> 7) & 0b1) + 6, + ], + ) } /// Shuffle double-precision (64-bit) floating-point elements in a within 128-bit lanes using the control in imm8, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set). @@ -19734,15 +19551,15 @@ pub unsafe fn _mm512_permute_pd(a: __m512d, imm8: i32) -> __m512d { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_permute_pd&expand=4159) #[inline] #[target_feature(enable = "avx512f")] -#[cfg_attr(test, assert_instr(vpermilpd, imm8 = 2))] -#[rustc_args_required_const(3)] -pub unsafe fn _mm512_mask_permute_pd(src: __m512d, k: __mmask8, a: __m512d, imm8: i32) -> __m512d { - macro_rules! call { - ($imm8:expr) => { - _mm512_permute_pd(a, $imm8) - }; - } - let r = constify_imm8_sae!(imm8, call); +#[cfg_attr(test, assert_instr(vpermilpd, MASK = 0b11_01_10_01))] +#[rustc_legacy_const_generics(3)] +pub unsafe fn _mm512_mask_permute_pd( + src: __m512d, + k: __mmask8, + a: __m512d, +) -> __m512d { + static_assert_imm8!(MASK); + let r = _mm512_permute_pd::(a); transmute(simd_select_bitmask(k, r.as_f64x8(), src.as_f64x8())) } @@ -19751,15 +19568,11 @@ pub unsafe fn _mm512_mask_permute_pd(src: __m512d, k: __mmask8, a: __m512d, imm8 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_permute_pd&expand=4160) #[inline] #[target_feature(enable = "avx512f")] -#[cfg_attr(test, assert_instr(vpermilpd, imm8 = 2))] -#[rustc_args_required_const(2)] -pub unsafe fn _mm512_maskz_permute_pd(k: __mmask8, a: __m512d, imm8: i32) -> __m512d { - macro_rules! call { - ($imm8:expr) => { - _mm512_permute_pd(a, $imm8) - }; - } - let r = constify_imm8_sae!(imm8, call); +#[cfg_attr(test, assert_instr(vpermilpd, MASK = 0b11_01_10_01))] +#[rustc_legacy_const_generics(2)] +pub unsafe fn _mm512_maskz_permute_pd(k: __mmask8, a: __m512d) -> __m512d { + static_assert_imm8!(MASK); + let r = _mm512_permute_pd::(a); let zero = _mm512_setzero_pd().as_f64x8(); transmute(simd_select_bitmask(k, r.as_f64x8(), zero)) } @@ -19769,15 +19582,15 @@ pub unsafe fn _mm512_maskz_permute_pd(k: __mmask8, a: __m512d, imm8: i32) -> __m /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mask_permute_pd&expand=4156) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[cfg_attr(test, assert_instr(vpermilpd, imm8 = 2))] -#[rustc_args_required_const(3)] -pub unsafe fn _mm256_mask_permute_pd(src: __m256d, k: __mmask8, a: __m256d, imm8: i32) -> __m256d { - macro_rules! call { - ($imm8:expr) => { - _mm256_permute_pd::<$imm8>(a) - }; - } - let r = constify_imm4!(imm8, call); +#[cfg_attr(test, assert_instr(vpermilpd, MASK = 0b11_01))] +#[rustc_legacy_const_generics(3)] +pub unsafe fn _mm256_mask_permute_pd( + src: __m256d, + k: __mmask8, + a: __m256d, +) -> __m256d { + static_assert_imm4!(MASK); + let r = _mm256_permute_pd::(a); transmute(simd_select_bitmask(k, r.as_f64x4(), src.as_f64x4())) } @@ -19786,15 +19599,11 @@ pub unsafe fn _mm256_mask_permute_pd(src: __m256d, k: __mmask8, a: __m256d, imm8 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_maskz_permute_pd&expand=4157) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[cfg_attr(test, assert_instr(vpermilpd, imm8 = 2))] -#[rustc_args_required_const(2)] -pub unsafe fn _mm256_maskz_permute_pd(k: __mmask8, a: __m256d, imm8: i32) -> __m256d { - macro_rules! call { - ($imm8:expr) => { - _mm256_permute_pd::<$imm8>(a) - }; - } - let r = constify_imm4!(imm8, call); +#[cfg_attr(test, assert_instr(vpermilpd, MASK = 0b11_01))] +#[rustc_legacy_const_generics(2)] +pub unsafe fn _mm256_maskz_permute_pd(k: __mmask8, a: __m256d) -> __m256d { + static_assert_imm4!(MASK); + let r = _mm256_permute_pd::(a); let zero = _mm256_setzero_pd().as_f64x4(); transmute(simd_select_bitmask(k, r.as_f64x4(), zero)) } @@ -19835,56 +19644,24 @@ pub unsafe fn _mm_maskz_permute_pd(k: __mmask8, a: __m128d) -> /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_permutex_epi64&expand=4208) #[inline] #[target_feature(enable = "avx512f")] -#[cfg_attr(test, assert_instr(vperm, imm8 = 0b10011011))] //shoud be vpermq -#[rustc_args_required_const(1)] -pub unsafe fn _mm512_permutex_epi64(a: __m512i, imm8: i32) -> __m512i { - let imm8 = (imm8 & 0xFF) as u8; - let undefined = _mm512_set1_epi64(0); - macro_rules! shuffle4 { - ($a:expr, $b:expr, $c:expr, $d:expr) => { - simd_shuffle8( - a, - undefined, - [$a, $b, $c, $d, $a + 4, $b + 4, $c + 4, $d + 4], - ) - }; - } - macro_rules! shuffle3 { - ($a:expr, $b:expr, $c:expr) => { - match (imm8 >> 6) & 0b11 { - 0b00 => shuffle4!($a, $b, $c, 0), - 0b01 => shuffle4!($a, $b, $c, 1), - 0b10 => shuffle4!($a, $b, $c, 2), - _ => shuffle4!($a, $b, $c, 3), - } - }; - } - macro_rules! shuffle2 { - ($a:expr, $b:expr) => { - match (imm8 >> 4) & 0b11 { - 0b00 => shuffle3!($a, $b, 0), - 0b01 => shuffle3!($a, $b, 1), - 0b10 => shuffle3!($a, $b, 2), - _ => shuffle3!($a, $b, 3), - } - }; - } - macro_rules! shuffle1 { - ($a:expr) => { - match (imm8 >> 2) & 0b11 { - 0b00 => shuffle2!($a, 0), - 0b01 => shuffle2!($a, 1), - 0b10 => shuffle2!($a, 2), - _ => shuffle2!($a, 3), - } - }; - } - match imm8 & 0b11 { - 0b00 => shuffle1!(0), - 0b01 => shuffle1!(1), - 0b10 => shuffle1!(2), - _ => shuffle1!(3), - } +#[cfg_attr(test, assert_instr(vperm, MASK = 0b10_01_10_11))] //shoud be vpermq +#[rustc_legacy_const_generics(1)] +pub unsafe fn _mm512_permutex_epi64(a: __m512i) -> __m512i { + static_assert_imm8!(MASK); + simd_shuffle8( + a, + a, + [ + MASK as u32 & 0b11, + (MASK as u32 >> 2) & 0b11, + ((MASK as u32 >> 4) & 0b11), + ((MASK as u32 >> 6) & 0b11), + (MASK as u32 & 0b11) + 4, + ((MASK as u32 >> 2) & 0b11) + 4, + ((MASK as u32 >> 4) & 0b11) + 4, + ((MASK as u32 >> 6) & 0b11) + 4, + ], + ) } /// Shuffle 64-bit integers in a within 256-bit lanes using the control in imm8, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set). @@ -19892,20 +19669,15 @@ pub unsafe fn _mm512_permutex_epi64(a: __m512i, imm8: i32) -> __m512i { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_permutex_epi64&expand=4206) #[inline] #[target_feature(enable = "avx512f")] -#[cfg_attr(test, assert_instr(vperm, imm8 = 0b11111111))] //should be vpermq -#[rustc_args_required_const(3)] -pub unsafe fn _mm512_mask_permutex_epi64( +#[cfg_attr(test, assert_instr(vperm, MASK = 0b10_01_10_11))] //should be vpermq +#[rustc_legacy_const_generics(3)] +pub unsafe fn _mm512_mask_permutex_epi64( src: __m512i, k: __mmask8, a: __m512i, - imm8: i32, ) -> __m512i { - macro_rules! call { - ($imm8:expr) => { - _mm512_permutex_epi64(a, $imm8) - }; - } - let r = constify_imm8_sae!(imm8, call); + static_assert_imm8!(MASK); + let r = _mm512_permutex_epi64::(a); transmute(simd_select_bitmask(k, r.as_i64x8(), src.as_i64x8())) } @@ -19914,15 +19686,11 @@ pub unsafe fn _mm512_mask_permutex_epi64( /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_permutex_epi64&expand=4207) #[inline] #[target_feature(enable = "avx512f")] -#[cfg_attr(test, assert_instr(vperm, imm8 = 0b11111111))] //should be vpermq -#[rustc_args_required_const(2)] -pub unsafe fn _mm512_maskz_permutex_epi64(k: __mmask8, a: __m512i, imm8: i32) -> __m512i { - macro_rules! call { - ($imm8:expr) => { - _mm512_permutex_epi64(a, $imm8) - }; - } - let r = constify_imm8_sae!(imm8, call); +#[cfg_attr(test, assert_instr(vperm, MASK = 0b10_01_10_11))] //should be vpermq +#[rustc_legacy_const_generics(2)] +pub unsafe fn _mm512_maskz_permutex_epi64(k: __mmask8, a: __m512i) -> __m512i { + static_assert_imm8!(MASK); + let r = _mm512_permutex_epi64::(a); let zero = _mm512_setzero_si512().as_i64x8(); transmute(simd_select_bitmask(k, r.as_i64x8(), zero)) } @@ -19932,52 +19700,20 @@ pub unsafe fn _mm512_maskz_permutex_epi64(k: __mmask8, a: __m512i, imm8: i32) -> /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_permutex_epi64&expand=4205) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[cfg_attr(test, assert_instr(vperm, imm8 = 0b10011011))] //shoud be vpermq -#[rustc_args_required_const(1)] -pub unsafe fn _mm256_permutex_epi64(a: __m256i, imm8: i32) -> __m256i { - let imm8 = (imm8 & 0xFF) as u8; - let undefined = _mm256_set1_epi64x(0); - macro_rules! shuffle4 { - ($a:expr, $b:expr, $c:expr, $d:expr) => { - simd_shuffle4(a, undefined, [$a, $b, $c, $d]) - }; - } - macro_rules! shuffle3 { - ($a:expr, $b:expr, $c:expr) => { - match (imm8 >> 6) & 0b11 { - 0b00 => shuffle4!($a, $b, $c, 0), - 0b01 => shuffle4!($a, $b, $c, 1), - 0b10 => shuffle4!($a, $b, $c, 2), - _ => shuffle4!($a, $b, $c, 3), - } - }; - } - macro_rules! shuffle2 { - ($a:expr, $b:expr) => { - match (imm8 >> 4) & 0b11 { - 0b00 => shuffle3!($a, $b, 0), - 0b01 => shuffle3!($a, $b, 1), - 0b10 => shuffle3!($a, $b, 2), - _ => shuffle3!($a, $b, 3), - } - }; - } - macro_rules! shuffle1 { - ($a:expr) => { - match (imm8 >> 2) & 0b11 { - 0b00 => shuffle2!($a, 0), - 0b01 => shuffle2!($a, 1), - 0b10 => shuffle2!($a, 2), - _ => shuffle2!($a, 3), - } - }; - } - match imm8 & 0b11 { - 0b00 => shuffle1!(0), - 0b01 => shuffle1!(1), - 0b10 => shuffle1!(2), - _ => shuffle1!(3), - } +#[cfg_attr(test, assert_instr(vperm, MASK = 0b10_01_10_11))] //shoud be vpermq +#[rustc_legacy_const_generics(1)] +pub unsafe fn _mm256_permutex_epi64(a: __m256i) -> __m256i { + static_assert_imm8!(MASK); + simd_shuffle4( + a, + a, + [ + MASK as u32 & 0b11, + (MASK as u32 >> 2) & 0b11, + ((MASK as u32 >> 4) & 0b11), + ((MASK as u32 >> 6) & 0b11), + ], + ) } /// Shuffle 64-bit integers in a within 256-bit lanes using the control in imm8, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set). @@ -19985,20 +19721,15 @@ pub unsafe fn _mm256_permutex_epi64(a: __m256i, imm8: i32) -> __m256i { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mask_permutex_epi6&expand=4203) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[cfg_attr(test, assert_instr(vperm, imm8 = 0b10011011))] //should be vpermq -#[rustc_args_required_const(3)] -pub unsafe fn _mm256_mask_permutex_epi64( +#[cfg_attr(test, assert_instr(vperm, MASK = 0b10_01_10_11))] //should be vpermq +#[rustc_legacy_const_generics(3)] +pub unsafe fn _mm256_mask_permutex_epi64( src: __m256i, k: __mmask8, a: __m256i, - imm8: i32, ) -> __m256i { - macro_rules! call { - ($imm8:expr) => { - _mm256_permutex_epi64(a, $imm8) - }; - } - let r = constify_imm8_sae!(imm8, call); + static_assert_imm8!(MASK); + let r = _mm256_permutex_epi64::(a); transmute(simd_select_bitmask(k, r.as_i64x4(), src.as_i64x4())) } @@ -20007,15 +19738,11 @@ pub unsafe fn _mm256_mask_permutex_epi64( /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_maskz_permutex_epi64&expand=4204) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[cfg_attr(test, assert_instr(vperm, imm8 = 0b10011011))] //should be vpermq -#[rustc_args_required_const(2)] -pub unsafe fn _mm256_maskz_permutex_epi64(k: __mmask8, a: __m256i, imm8: i32) -> __m256i { - macro_rules! call { - ($imm8:expr) => { - _mm256_permutex_epi64(a, $imm8) - }; - } - let r = constify_imm8_sae!(imm8, call); +#[cfg_attr(test, assert_instr(vperm, MASK = 0b10_01_10_11))] //should be vpermq +#[rustc_legacy_const_generics(2)] +pub unsafe fn _mm256_maskz_permutex_epi64(k: __mmask8, a: __m256i) -> __m256i { + static_assert_imm8!(MASK); + let r = _mm256_permutex_epi64::(a); let zero = _mm256_setzero_si256().as_i64x4(); transmute(simd_select_bitmask(k, r.as_i64x4(), zero)) } @@ -20025,56 +19752,24 @@ pub unsafe fn _mm256_maskz_permutex_epi64(k: __mmask8, a: __m256i, imm8: i32) -> /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_permutex_pd&expand=4214) #[inline] #[target_feature(enable = "avx512f")] -#[cfg_attr(test, assert_instr(vperm, imm8 = 0b11111111))] //shoud be vpermpd -#[rustc_args_required_const(1)] -pub unsafe fn _mm512_permutex_pd(a: __m512d, imm8: i32) -> __m512d { - let imm8 = (imm8 & 0xFF) as u8; - let undefined = _mm512_undefined_pd(); - macro_rules! shuffle4 { - ($a:expr, $b:expr, $c:expr, $d:expr) => { - simd_shuffle8( - a, - undefined, - [$a, $b, $c, $d, $a + 4, $b + 4, $c + 4, $d + 4], - ) - }; - } - macro_rules! shuffle3 { - ($a:expr, $b:expr, $c:expr) => { - match (imm8 >> 6) & 0b11 { - 0b00 => shuffle4!($a, $b, $c, 0), - 0b01 => shuffle4!($a, $b, $c, 1), - 0b10 => shuffle4!($a, $b, $c, 2), - _ => shuffle4!($a, $b, $c, 3), - } - }; - } - macro_rules! shuffle2 { - ($a:expr, $b:expr) => { - match (imm8 >> 4) & 0b11 { - 0b00 => shuffle3!($a, $b, 0), - 0b01 => shuffle3!($a, $b, 1), - 0b10 => shuffle3!($a, $b, 2), - _ => shuffle3!($a, $b, 3), - } - }; - } - macro_rules! shuffle1 { - ($a:expr) => { - match (imm8 >> 2) & 0b11 { - 0b00 => shuffle2!($a, 0), - 0b01 => shuffle2!($a, 1), - 0b10 => shuffle2!($a, 2), - _ => shuffle2!($a, 3), - } - }; - } - match imm8 & 0b11 { - 0b00 => shuffle1!(0), - 0b01 => shuffle1!(1), - 0b10 => shuffle1!(2), - _ => shuffle1!(3), - } +#[cfg_attr(test, assert_instr(vperm, MASK = 0b10_01_10_11))] //shoud be vpermpd +#[rustc_legacy_const_generics(1)] +pub unsafe fn _mm512_permutex_pd(a: __m512d) -> __m512d { + static_assert_imm8!(MASK); + simd_shuffle8( + a, + a, + [ + MASK as u32 & 0b11, + (MASK as u32 >> 2) & 0b11, + ((MASK as u32 >> 4) & 0b11), + ((MASK as u32 >> 6) & 0b11), + (MASK as u32 & 0b11) + 4, + ((MASK as u32 >> 2) & 0b11) + 4, + ((MASK as u32 >> 4) & 0b11) + 4, + ((MASK as u32 >> 6) & 0b11) + 4, + ], + ) } /// Shuffle double-precision (64-bit) floating-point elements in a within 256-bit lanes using the control in imm8, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set). @@ -20082,15 +19777,14 @@ pub unsafe fn _mm512_permutex_pd(a: __m512d, imm8: i32) -> __m512d { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_permutex_pd&expand=4212) #[inline] #[target_feature(enable = "avx512f")] -#[cfg_attr(test, assert_instr(vperm, imm8 = 0b11111111))] //shoud be vpermpd -#[rustc_args_required_const(3)] -pub unsafe fn _mm512_mask_permutex_pd(src: __m512d, k: __mmask8, a: __m512d, imm8: i32) -> __m512d { - macro_rules! call { - ($imm8:expr) => { - _mm512_permutex_pd(a, $imm8) - }; - } - let r = constify_imm8_sae!(imm8, call); +#[cfg_attr(test, assert_instr(vperm, MASK = 0b10_01_10_11))] //shoud be vpermpd +#[rustc_legacy_const_generics(3)] +pub unsafe fn _mm512_mask_permutex_pd( + src: __m512d, + k: __mmask8, + a: __m512d, +) -> __m512d { + let r = _mm512_permutex_pd::(a); transmute(simd_select_bitmask(k, r.as_f64x8(), src.as_f64x8())) } @@ -20099,15 +19793,10 @@ pub unsafe fn _mm512_mask_permutex_pd(src: __m512d, k: __mmask8, a: __m512d, imm /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_permutex_pd&expand=4213) #[inline] #[target_feature(enable = "avx512f")] -#[cfg_attr(test, assert_instr(vperm, imm8 = 0b11111111))] //shoud be vpermpd -#[rustc_args_required_const(2)] -pub unsafe fn _mm512_maskz_permutex_pd(k: __mmask8, a: __m512d, imm8: i32) -> __m512d { - macro_rules! call { - ($imm8:expr) => { - _mm512_permutex_pd(a, $imm8) - }; - } - let r = constify_imm8_sae!(imm8, call); +#[cfg_attr(test, assert_instr(vperm, MASK = 0b10_01_10_11))] //shoud be vpermpd +#[rustc_legacy_const_generics(2)] +pub unsafe fn _mm512_maskz_permutex_pd(k: __mmask8, a: __m512d) -> __m512d { + let r = _mm512_permutex_pd::(a); let zero = _mm512_setzero_pd().as_f64x8(); transmute(simd_select_bitmask(k, r.as_f64x8(), zero)) } @@ -20117,52 +19806,20 @@ pub unsafe fn _mm512_maskz_permutex_pd(k: __mmask8, a: __m512d, imm8: i32) -> __ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_permutex_pd&expand=4211) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[cfg_attr(test, assert_instr(vperm, imm8 = 0b10011011))] //shoud be vpermpd -#[rustc_args_required_const(1)] -pub unsafe fn _mm256_permutex_pd(a: __m256d, imm8: i32) -> __m256d { - let imm8 = (imm8 & 0xFF) as u8; - let undefined = _mm256_undefined_pd(); - macro_rules! shuffle4 { - ($a:expr, $b:expr, $c:expr, $d:expr) => { - simd_shuffle4(a, undefined, [$a, $b, $c, $d]) - }; - } - macro_rules! shuffle3 { - ($a:expr, $b:expr, $c:expr) => { - match (imm8 >> 6) & 0b11 { - 0b00 => shuffle4!($a, $b, $c, 0), - 0b01 => shuffle4!($a, $b, $c, 1), - 0b10 => shuffle4!($a, $b, $c, 2), - _ => shuffle4!($a, $b, $c, 3), - } - }; - } - macro_rules! shuffle2 { - ($a:expr, $b:expr) => { - match (imm8 >> 4) & 0b11 { - 0b00 => shuffle3!($a, $b, 0), - 0b01 => shuffle3!($a, $b, 1), - 0b10 => shuffle3!($a, $b, 2), - _ => shuffle3!($a, $b, 3), - } - }; - } - macro_rules! shuffle1 { - ($a:expr) => { - match (imm8 >> 2) & 0b11 { - 0b00 => shuffle2!($a, 0), - 0b01 => shuffle2!($a, 1), - 0b10 => shuffle2!($a, 2), - _ => shuffle2!($a, 3), - } - }; - } - match imm8 & 0b11 { - 0b00 => shuffle1!(0), - 0b01 => shuffle1!(1), - 0b10 => shuffle1!(2), - _ => shuffle1!(3), - } +#[cfg_attr(test, assert_instr(vperm, MASK = 0b10_01_10_11))] //shoud be vpermpd +#[rustc_legacy_const_generics(1)] +pub unsafe fn _mm256_permutex_pd(a: __m256d) -> __m256d { + static_assert_imm8!(MASK); + simd_shuffle4( + a, + a, + [ + MASK as u32 & 0b11, + (MASK as u32 >> 2) & 0b11, + ((MASK as u32 >> 4) & 0b11), + ((MASK as u32 >> 6) & 0b11), + ], + ) } /// Shuffle double-precision (64-bit) floating-point elements in a within 256-bit lanes using the control in imm8, and store the results in dst using writemask k (elements are copied from src when the corresponding mask bit is not set). @@ -20170,15 +19827,15 @@ pub unsafe fn _mm256_permutex_pd(a: __m256d, imm8: i32) -> __m256d { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mask_permutex_pd&expand=4209) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[cfg_attr(test, assert_instr(vperm, imm8 = 0b10011011))] //shoud be vpermpd -#[rustc_args_required_const(3)] -pub unsafe fn _mm256_mask_permutex_pd(src: __m256d, k: __mmask8, a: __m256d, imm8: i32) -> __m256d { - macro_rules! call { - ($imm8:expr) => { - _mm256_permutex_pd(a, $imm8) - }; - } - let r = constify_imm8_sae!(imm8, call); +#[cfg_attr(test, assert_instr(vperm, MASK = 0b10_01_10_11))] //shoud be vpermpd +#[rustc_legacy_const_generics(3)] +pub unsafe fn _mm256_mask_permutex_pd( + src: __m256d, + k: __mmask8, + a: __m256d, +) -> __m256d { + static_assert_imm8!(MASK); + let r = _mm256_permutex_pd::(a); transmute(simd_select_bitmask(k, r.as_f64x4(), src.as_f64x4())) } @@ -20187,15 +19844,11 @@ pub unsafe fn _mm256_mask_permutex_pd(src: __m256d, k: __mmask8, a: __m256d, imm /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_maskz_permutex_pd&expand=4210) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[cfg_attr(test, assert_instr(vperm, imm8 = 0b10011011))] //shoud be vpermpd -#[rustc_args_required_const(2)] -pub unsafe fn _mm256_maskz_permutex_pd(k: __mmask8, a: __m256d, imm8: i32) -> __m256d { - macro_rules! call { - ($imm8:expr) => { - _mm256_permutex_pd(a, $imm8) - }; - } - let r = constify_imm8_sae!(imm8, call); +#[cfg_attr(test, assert_instr(vperm, MASK = 0b10_01_10_11))] //shoud be vpermpd +#[rustc_legacy_const_generics(2)] +pub unsafe fn _mm256_maskz_permutex_pd(k: __mmask8, a: __m256d) -> __m256d { + static_assert_imm8!(MASK); + let r = _mm256_permutex_pd::(a); let zero = _mm256_setzero_pd().as_f64x4(); transmute(simd_select_bitmask(k, r.as_f64x4(), zero)) } @@ -24946,13 +24599,13 @@ pub unsafe fn _mm_mask_blend_pd(k: __mmask8, a: __m128d, b: __m128d) -> __m128d /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_alignr_epi32&expand=245) #[inline] #[target_feature(enable = "avx512f")] -#[cfg_attr(test, assert_instr(valignd, imm8 = 1))] -#[rustc_args_required_const(2)] -pub unsafe fn _mm512_alignr_epi32(a: __m512i, b: __m512i, imm8: i32) -> __m512i { - assert!(imm8 >= 0 && imm8 <= 255); +#[cfg_attr(test, assert_instr(valignd, IMM8 = 1))] +#[rustc_legacy_const_generics(2)] +pub unsafe fn _mm512_alignr_epi32(a: __m512i, b: __m512i) -> __m512i { + static_assert_imm8!(IMM8); let a = a.as_i32x16(); let b = b.as_i32x16(); - let imm8: i32 = imm8 % 16; + let imm8: i32 = IMM8 % 16; let r: i32x16 = match imm8 { 0 => simd_shuffle16( a, @@ -25023,21 +24676,16 @@ pub unsafe fn _mm512_alignr_epi32(a: __m512i, b: __m512i, imm8: i32) -> __m512i /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_alignr_epi32&expand=246) #[inline] #[target_feature(enable = "avx512f")] -#[cfg_attr(test, assert_instr(valignd, imm8 = 1))] -#[rustc_args_required_const(4)] -pub unsafe fn _mm512_mask_alignr_epi32( +#[cfg_attr(test, assert_instr(valignd, IMM8 = 1))] +#[rustc_legacy_const_generics(4)] +pub unsafe fn _mm512_mask_alignr_epi32( src: __m512i, k: __mmask16, a: __m512i, b: __m512i, - imm8: i32, ) -> __m512i { - macro_rules! call { - ($imm8:expr) => { - _mm512_alignr_epi32(a, b, $imm8) - }; - } - let r = constify_imm8_sae!(imm8, call); + static_assert_imm8!(IMM8); + let r = _mm512_alignr_epi32::(a, b); transmute(simd_select_bitmask(k, r.as_i32x16(), src.as_i32x16())) } @@ -25046,20 +24694,15 @@ pub unsafe fn _mm512_mask_alignr_epi32( /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_alignr_epi32&expand=247) #[inline] #[target_feature(enable = "avx512f")] -#[cfg_attr(test, assert_instr(valignd, imm8 = 1))] -#[rustc_args_required_const(3)] -pub unsafe fn _mm512_maskz_alignr_epi32( +#[cfg_attr(test, assert_instr(valignd, IMM8 = 1))] +#[rustc_legacy_const_generics(3)] +pub unsafe fn _mm512_maskz_alignr_epi32( k: __mmask16, a: __m512i, b: __m512i, - imm8: i32, ) -> __m512i { - macro_rules! call { - ($imm8:expr) => { - _mm512_alignr_epi32(a, b, $imm8) - }; - } - let r = constify_imm8_sae!(imm8, call); + static_assert_imm8!(IMM8); + let r = _mm512_alignr_epi32::(a, b); let zero = _mm512_setzero_si512().as_i32x16(); transmute(simd_select_bitmask(k, r.as_i32x16(), zero)) } @@ -25069,13 +24712,13 @@ pub unsafe fn _mm512_maskz_alignr_epi32( /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_alignr_epi32&expand=242) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[cfg_attr(test, assert_instr(valignd, imm8 = 1))] -#[rustc_args_required_const(2)] -pub unsafe fn _mm256_alignr_epi32(a: __m256i, b: __m256i, imm8: i32) -> __m256i { - assert!(imm8 >= 0 && imm8 <= 255); +#[cfg_attr(test, assert_instr(valignd, IMM8 = 1))] +#[rustc_legacy_const_generics(2)] +pub unsafe fn _mm256_alignr_epi32(a: __m256i, b: __m256i) -> __m256i { + static_assert_imm8!(IMM8); let a = a.as_i32x8(); let b = b.as_i32x8(); - let imm8: i32 = imm8 % 16; + let imm8: i32 = IMM8 % 16; let r: i32x8 = match imm8 { 0 => simd_shuffle8(a, b, [8, 9, 10, 11, 12, 13, 14, 15]), 1 => simd_shuffle8(a, b, [9, 10, 11, 12, 13, 14, 15, 0]), @@ -25102,21 +24745,16 @@ pub unsafe fn _mm256_alignr_epi32(a: __m256i, b: __m256i, imm8: i32) -> __m256i /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mask_alignr_epi32&expand=243) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[cfg_attr(test, assert_instr(valignd, imm8 = 1))] -#[rustc_args_required_const(4)] -pub unsafe fn _mm256_mask_alignr_epi32( +#[cfg_attr(test, assert_instr(valignd, IMM8 = 1))] +#[rustc_legacy_const_generics(4)] +pub unsafe fn _mm256_mask_alignr_epi32( src: __m256i, k: __mmask8, a: __m256i, b: __m256i, - imm8: i32, ) -> __m256i { - macro_rules! call { - ($imm8:expr) => { - _mm256_alignr_epi32(a, b, $imm8) - }; - } - let r = constify_imm8_sae!(imm8, call); + static_assert_imm8!(IMM8); + let r = _mm256_alignr_epi32::(a, b); transmute(simd_select_bitmask(k, r.as_i32x8(), src.as_i32x8())) } @@ -25125,15 +24763,15 @@ pub unsafe fn _mm256_mask_alignr_epi32( /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_maskz_alignr_epi32&expand=244) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[cfg_attr(test, assert_instr(valignd, imm8 = 1))] -#[rustc_args_required_const(3)] -pub unsafe fn _mm256_maskz_alignr_epi32(k: __mmask8, a: __m256i, b: __m256i, imm8: i32) -> __m256i { - macro_rules! call { - ($imm8:expr) => { - _mm256_alignr_epi32(a, b, $imm8) - }; - } - let r = constify_imm8_sae!(imm8, call); +#[cfg_attr(test, assert_instr(valignd, IMM8 = 1))] +#[rustc_legacy_const_generics(3)] +pub unsafe fn _mm256_maskz_alignr_epi32( + k: __mmask8, + a: __m256i, + b: __m256i, +) -> __m256i { + static_assert_imm8!(IMM8); + let r = _mm256_alignr_epi32::(a, b); let zero = _mm256_setzero_si256().as_i32x8(); transmute(simd_select_bitmask(k, r.as_i32x8(), zero)) } @@ -25143,13 +24781,13 @@ pub unsafe fn _mm256_maskz_alignr_epi32(k: __mmask8, a: __m256i, b: __m256i, imm /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_alignr_epi32&expand=239) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[cfg_attr(test, assert_instr(vpalignr, imm8 = 1))] //should be valignd -#[rustc_args_required_const(2)] -pub unsafe fn _mm_alignr_epi32(a: __m128i, b: __m128i, imm8: i32) -> __m128i { - assert!(imm8 >= 0 && imm8 <= 255); +#[cfg_attr(test, assert_instr(vpalignr, IMM8 = 1))] //should be valignd +#[rustc_legacy_const_generics(2)] +pub unsafe fn _mm_alignr_epi32(a: __m128i, b: __m128i) -> __m128i { + static_assert_imm8!(IMM8); let a = a.as_i32x4(); let b = b.as_i32x4(); - let imm8: i32 = imm8 % 8; + let imm8: i32 = IMM8 % 8; let r: i32x4 = match imm8 { 0 => simd_shuffle4(a, b, [4, 5, 6, 7]), 1 => simd_shuffle4(a, b, [5, 6, 7, 0]), @@ -25168,21 +24806,16 @@ pub unsafe fn _mm_alignr_epi32(a: __m128i, b: __m128i, imm8: i32) -> __m128i { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_alignr_epi32&expand=240) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[cfg_attr(test, assert_instr(valignd, imm8 = 1))] -#[rustc_args_required_const(4)] -pub unsafe fn _mm_mask_alignr_epi32( +#[cfg_attr(test, assert_instr(valignd, IMM8 = 1))] +#[rustc_legacy_const_generics(4)] +pub unsafe fn _mm_mask_alignr_epi32( src: __m128i, k: __mmask8, a: __m128i, b: __m128i, - imm8: i32, ) -> __m128i { - macro_rules! call { - ($imm8:expr) => { - _mm_alignr_epi32(a, b, $imm8) - }; - } - let r = constify_imm8_sae!(imm8, call); + static_assert_imm8!(IMM8); + let r = _mm_alignr_epi32::(a, b); transmute(simd_select_bitmask(k, r.as_i32x4(), src.as_i32x4())) } @@ -25191,15 +24824,15 @@ pub unsafe fn _mm_mask_alignr_epi32( /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_alignr_epi32&expand=241) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[cfg_attr(test, assert_instr(valignd, imm8 = 1))] -#[rustc_args_required_const(3)] -pub unsafe fn _mm_maskz_alignr_epi32(k: __mmask8, a: __m128i, b: __m128i, imm8: i32) -> __m128i { - macro_rules! call { - ($imm8:expr) => { - _mm_alignr_epi32(a, b, $imm8) - }; - } - let r = constify_imm8_sae!(imm8, call); +#[cfg_attr(test, assert_instr(valignd, IMM8 = 1))] +#[rustc_legacy_const_generics(3)] +pub unsafe fn _mm_maskz_alignr_epi32( + k: __mmask8, + a: __m128i, + b: __m128i, +) -> __m128i { + static_assert_imm8!(IMM8); + let r = _mm_alignr_epi32::(a, b); let zero = _mm_setzero_si128().as_i32x4(); transmute(simd_select_bitmask(k, r.as_i32x4(), zero)) } @@ -25209,11 +24842,11 @@ pub unsafe fn _mm_maskz_alignr_epi32(k: __mmask8, a: __m128i, b: __m128i, imm8: /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_alignr_epi64&expand=254) #[inline] #[target_feature(enable = "avx512f")] -#[cfg_attr(test, assert_instr(valignq, imm8 = 1))] -#[rustc_args_required_const(2)] -pub unsafe fn _mm512_alignr_epi64(a: __m512i, b: __m512i, imm8: i32) -> __m512i { - assert!(imm8 >= 0 && imm8 <= 255); - let imm8: i32 = imm8 % 8; +#[cfg_attr(test, assert_instr(valignq, IMM8 = 1))] +#[rustc_legacy_const_generics(2)] +pub unsafe fn _mm512_alignr_epi64(a: __m512i, b: __m512i) -> __m512i { + static_assert_imm8!(IMM8); + let imm8: i32 = IMM8 % 8; let r: i64x8 = match imm8 { 0 => simd_shuffle8(a, b, [8, 9, 10, 11, 12, 13, 14, 15]), 1 => simd_shuffle8(a, b, [9, 10, 11, 12, 13, 14, 15, 0]), @@ -25232,21 +24865,16 @@ pub unsafe fn _mm512_alignr_epi64(a: __m512i, b: __m512i, imm8: i32) -> __m512i /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_mask_alignr_epi64&expand=255) #[inline] #[target_feature(enable = "avx512f")] -#[cfg_attr(test, assert_instr(valignq, imm8 = 1))] -#[rustc_args_required_const(4)] -pub unsafe fn _mm512_mask_alignr_epi64( +#[cfg_attr(test, assert_instr(valignq, IMM8 = 1))] +#[rustc_legacy_const_generics(4)] +pub unsafe fn _mm512_mask_alignr_epi64( src: __m512i, k: __mmask8, a: __m512i, b: __m512i, - imm8: i32, ) -> __m512i { - macro_rules! call { - ($imm8:expr) => { - _mm512_alignr_epi64(a, b, $imm8) - }; - } - let r = constify_imm8_sae!(imm8, call); + static_assert_imm8!(IMM8); + let r = _mm512_alignr_epi64::(a, b); transmute(simd_select_bitmask(k, r.as_i64x8(), src.as_i64x8())) } @@ -25255,15 +24883,15 @@ pub unsafe fn _mm512_mask_alignr_epi64( /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=512_maskz_alignr_epi64&expand=256) #[inline] #[target_feature(enable = "avx512f")] -#[cfg_attr(test, assert_instr(valignq, imm8 = 1))] -#[rustc_args_required_const(3)] -pub unsafe fn _mm512_maskz_alignr_epi64(k: __mmask8, a: __m512i, b: __m512i, imm8: i32) -> __m512i { - macro_rules! call { - ($imm8:expr) => { - _mm512_alignr_epi64(a, b, $imm8) - }; - } - let r = constify_imm8_sae!(imm8, call); +#[cfg_attr(test, assert_instr(valignq, IMM8 = 1))] +#[rustc_legacy_const_generics(3)] +pub unsafe fn _mm512_maskz_alignr_epi64( + k: __mmask8, + a: __m512i, + b: __m512i, +) -> __m512i { + static_assert_imm8!(IMM8); + let r = _mm512_alignr_epi64::(a, b); let zero = _mm512_setzero_si512().as_i64x8(); transmute(simd_select_bitmask(k, r.as_i64x8(), zero)) } @@ -25273,11 +24901,11 @@ pub unsafe fn _mm512_maskz_alignr_epi64(k: __mmask8, a: __m512i, b: __m512i, imm /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_alignr_epi64&expand=251) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[cfg_attr(test, assert_instr(valignq, imm8 = 1))] -#[rustc_args_required_const(2)] -pub unsafe fn _mm256_alignr_epi64(a: __m256i, b: __m256i, imm8: i32) -> __m256i { - assert!(imm8 >= 0 && imm8 <= 255); - let imm8: i32 = imm8 % 8; +#[cfg_attr(test, assert_instr(valignq, IMM8 = 1))] +#[rustc_legacy_const_generics(2)] +pub unsafe fn _mm256_alignr_epi64(a: __m256i, b: __m256i) -> __m256i { + static_assert_imm8!(IMM8); + let imm8: i32 = IMM8 % 8; let r: i64x4 = match imm8 { 0 => simd_shuffle4(a, b, [4, 5, 6, 7]), 1 => simd_shuffle4(a, b, [5, 6, 7, 0]), @@ -25296,21 +24924,16 @@ pub unsafe fn _mm256_alignr_epi64(a: __m256i, b: __m256i, imm8: i32) -> __m256i /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mask_alignr_epi64&expand=252) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[cfg_attr(test, assert_instr(valignq, imm8 = 1))] -#[rustc_args_required_const(4)] -pub unsafe fn _mm256_mask_alignr_epi64( +#[cfg_attr(test, assert_instr(valignq, IMM8 = 1))] +#[rustc_legacy_const_generics(4)] +pub unsafe fn _mm256_mask_alignr_epi64( src: __m256i, k: __mmask8, a: __m256i, b: __m256i, - imm8: i32, ) -> __m256i { - macro_rules! call { - ($imm8:expr) => { - _mm256_alignr_epi64(a, b, $imm8) - }; - } - let r = constify_imm8_sae!(imm8, call); + static_assert_imm8!(IMM8); + let r = _mm256_alignr_epi64::(a, b); transmute(simd_select_bitmask(k, r.as_i64x4(), src.as_i64x4())) } @@ -25319,15 +24942,15 @@ pub unsafe fn _mm256_mask_alignr_epi64( /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_maskz_alignr_epi64&expand=253) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[cfg_attr(test, assert_instr(valignq, imm8 = 1))] -#[rustc_args_required_const(3)] -pub unsafe fn _mm256_maskz_alignr_epi64(k: __mmask8, a: __m256i, b: __m256i, imm8: i32) -> __m256i { - macro_rules! call { - ($imm8:expr) => { - _mm256_alignr_epi64(a, b, $imm8) - }; - } - let r = constify_imm8_sae!(imm8, call); +#[cfg_attr(test, assert_instr(valignq, IMM8 = 1))] +#[rustc_legacy_const_generics(3)] +pub unsafe fn _mm256_maskz_alignr_epi64( + k: __mmask8, + a: __m256i, + b: __m256i, +) -> __m256i { + static_assert_imm8!(IMM8); + let r = _mm256_alignr_epi64::(a, b); let zero = _mm256_setzero_si256().as_i64x4(); transmute(simd_select_bitmask(k, r.as_i64x4(), zero)) } @@ -25337,11 +24960,11 @@ pub unsafe fn _mm256_maskz_alignr_epi64(k: __mmask8, a: __m256i, b: __m256i, imm /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_alignr_epi64&expand=248) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[cfg_attr(test, assert_instr(vpalignr, imm8 = 1))] //should be valignq -#[rustc_args_required_const(2)] -pub unsafe fn _mm_alignr_epi64(a: __m128i, b: __m128i, imm8: i32) -> __m128i { - assert!(imm8 >= 0 && imm8 <= 255); - let imm8: i32 = imm8 % 4; +#[cfg_attr(test, assert_instr(vpalignr, IMM8 = 1))] //should be valignq +#[rustc_legacy_const_generics(2)] +pub unsafe fn _mm_alignr_epi64(a: __m128i, b: __m128i) -> __m128i { + static_assert_imm8!(IMM8); + let imm8: i32 = IMM8 % 4; let r: i64x2 = match imm8 { 0 => simd_shuffle2(a, b, [2, 3]), 1 => simd_shuffle2(a, b, [3, 0]), @@ -25356,21 +24979,16 @@ pub unsafe fn _mm_alignr_epi64(a: __m128i, b: __m128i, imm8: i32) -> __m128i { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_alignr_epi64&expand=249) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[cfg_attr(test, assert_instr(valignq, imm8 = 1))] -#[rustc_args_required_const(4)] -pub unsafe fn _mm_mask_alignr_epi64( +#[cfg_attr(test, assert_instr(valignq, IMM8 = 1))] +#[rustc_legacy_const_generics(4)] +pub unsafe fn _mm_mask_alignr_epi64( src: __m128i, k: __mmask8, a: __m128i, b: __m128i, - imm8: i32, ) -> __m128i { - macro_rules! call { - ($imm8:expr) => { - _mm_alignr_epi64(a, b, $imm8) - }; - } - let r = constify_imm8_sae!(imm8, call); + static_assert_imm8!(IMM8); + let r = _mm_alignr_epi64::(a, b); transmute(simd_select_bitmask(k, r.as_i64x2(), src.as_i64x2())) } @@ -25379,15 +24997,15 @@ pub unsafe fn _mm_mask_alignr_epi64( /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_alignr_epi64&expand=250) #[inline] #[target_feature(enable = "avx512f,avx512vl")] -#[cfg_attr(test, assert_instr(valignq, imm8 = 1))] -#[rustc_args_required_const(3)] -pub unsafe fn _mm_maskz_alignr_epi64(k: __mmask8, a: __m128i, b: __m128i, imm8: i32) -> __m128i { - macro_rules! call { - ($imm8:expr) => { - _mm_alignr_epi64(a, b, $imm8) - }; - } - let r = constify_imm8_sae!(imm8, call); +#[cfg_attr(test, assert_instr(valignq, IMM8 = 1))] +#[rustc_legacy_const_generics(3)] +pub unsafe fn _mm_maskz_alignr_epi64( + k: __mmask8, + a: __m128i, + b: __m128i, +) -> __m128i { + static_assert_imm8!(IMM8); + let r = _mm_alignr_epi64::(a, b); let zero = _mm_setzero_si128().as_i64x2(); transmute(simd_select_bitmask(k, r.as_i64x2(), zero)) } @@ -27209,18 +26827,18 @@ pub unsafe fn _mm_mask_cmp_ps_mask(k1: __mmask8, a: __m128, b: __m128, imm8: i32 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cmp_round_ps_mask&expand=753) #[inline] #[target_feature(enable = "avx512f")] -#[rustc_args_required_const(2, 3)] -#[cfg_attr(test, assert_instr(vcmp, imm8 = 0, sae = 4))] -pub unsafe fn _mm512_cmp_round_ps_mask(a: __m512, b: __m512, imm8: i32, sae: i32) -> __mmask16 { +#[cfg_attr(test, assert_instr(vcmp, IMM5 = 0, SAE = 4))] +#[rustc_legacy_const_generics(2, 3)] +pub unsafe fn _mm512_cmp_round_ps_mask( + a: __m512, + b: __m512, +) -> __mmask16 { + static_assert_imm5!(IMM5); + static_assert_mantissas_sae!(SAE); let neg_one = -1; let a = a.as_f32x16(); let b = b.as_f32x16(); - macro_rules! call { - ($imm5:expr, $imm4:expr) => { - vcmpps(a, b, $imm5, neg_one, $imm4) - }; - } - let r = constify_imm5_sae!(imm8, sae, call); + let r = vcmpps(a, b, IMM5, neg_one, SAE); transmute(r) } @@ -27230,23 +26848,18 @@ pub unsafe fn _mm512_cmp_round_ps_mask(a: __m512, b: __m512, imm8: i32, sae: i32 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cmp_round_ps_mask&expand=754) #[inline] #[target_feature(enable = "avx512f")] -#[rustc_args_required_const(3, 4)] -#[cfg_attr(test, assert_instr(vcmp, imm8 = 0, sae = 4))] -pub unsafe fn _mm512_mask_cmp_round_ps_mask( +#[cfg_attr(test, assert_instr(vcmp, IMM5 = 0, SAE = 4))] +#[rustc_legacy_const_generics(3, 4)] +pub unsafe fn _mm512_mask_cmp_round_ps_mask( m: __mmask16, a: __m512, b: __m512, - imm8: i32, - sae: i32, ) -> __mmask16 { + static_assert_imm5!(IMM5); + static_assert_mantissas_sae!(SAE); let a = a.as_f32x16(); let b = b.as_f32x16(); - macro_rules! call { - ($imm5:expr, $imm4:expr) => { - vcmpps(a, b, $imm5, m as i16, $imm4) - }; - } - let r = constify_imm5_sae!(imm8, sae, call); + let r = vcmpps(a, b, IMM5, m as i16, SAE); transmute(r) } @@ -27533,18 +27146,18 @@ pub unsafe fn _mm_mask_cmp_pd_mask(k1: __mmask8, a: __m128d, b: __m128d, imm8: i /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cmp_round_pd_mask&expand=751) #[inline] #[target_feature(enable = "avx512f")] -#[rustc_args_required_const(2, 3)] -#[cfg_attr(test, assert_instr(vcmp, imm8 = 0, sae = 4))] -pub unsafe fn _mm512_cmp_round_pd_mask(a: __m512d, b: __m512d, imm8: i32, sae: i32) -> __mmask8 { +#[cfg_attr(test, assert_instr(vcmp, IMM5 = 0, SAE = 4))] +#[rustc_legacy_const_generics(2, 3)] +pub unsafe fn _mm512_cmp_round_pd_mask( + a: __m512d, + b: __m512d, +) -> __mmask8 { + static_assert_imm5!(IMM5); + static_assert_mantissas_sae!(SAE); let neg_one = -1; let a = a.as_f64x8(); let b = b.as_f64x8(); - macro_rules! call { - ($imm5:expr, $imm4:expr) => { - vcmppd(a, b, $imm5, neg_one, $imm4) - }; - } - let r = constify_imm5_sae!(imm8, sae, call); + let r = vcmppd(a, b, IMM5, neg_one, SAE); transmute(r) } @@ -27554,23 +27167,18 @@ pub unsafe fn _mm512_cmp_round_pd_mask(a: __m512d, b: __m512d, imm8: i32, sae: i /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cmp_round_pd_mask&expand=752) #[inline] #[target_feature(enable = "avx512f")] -#[rustc_args_required_const(3, 4)] -#[cfg_attr(test, assert_instr(vcmp, imm8 = 0, sae = 4))] -pub unsafe fn _mm512_mask_cmp_round_pd_mask( +#[cfg_attr(test, assert_instr(vcmp, IMM5 = 0, SAE = 4))] +#[rustc_legacy_const_generics(3, 4)] +pub unsafe fn _mm512_mask_cmp_round_pd_mask( k1: __mmask8, a: __m512d, b: __m512d, - imm8: i32, - sae: i32, ) -> __mmask8 { + static_assert_imm5!(IMM5); + static_assert_mantissas_sae!(SAE); let a = a.as_f64x8(); let b = b.as_f64x8(); - macro_rules! call { - ($imm5:expr, $imm4:expr) => { - vcmppd(a, b, $imm5, k1 as i8, $imm4) - }; - } - let r = constify_imm5_sae!(imm8, sae, call); + let r = vcmppd(a, b, IMM5, k1 as i8, SAE); transmute(r) } @@ -27655,16 +27263,16 @@ pub unsafe fn _mm_mask_cmp_ss_mask(k1: __mmask8, a: __m128, b: __m128, imm8: i32 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmp_round_ss_mask&expand=757) #[inline] #[target_feature(enable = "avx512f")] -#[rustc_args_required_const(2, 3)] -#[cfg_attr(test, assert_instr(vcmp, imm8 = 0, sae = 4))] -pub unsafe fn _mm_cmp_round_ss_mask(a: __m128, b: __m128, imm8: i32, sae: i32) -> __mmask8 { +#[cfg_attr(test, assert_instr(vcmp, IMM5 = 0, SAE = 4))] +#[rustc_legacy_const_generics(2, 3)] +pub unsafe fn _mm_cmp_round_ss_mask( + a: __m128, + b: __m128, +) -> __mmask8 { + static_assert_imm5!(IMM5); + static_assert_mantissas_sae!(SAE); let neg_one = -1; - macro_rules! call { - ($imm5:expr, $imm4:expr) => { - vcmpss(a, b, $imm5, neg_one, $imm4) - }; - } - let r = constify_imm5_sae!(imm8, sae, call); + let r = vcmpss(a, b, IMM5, neg_one, SAE); transmute(r) } @@ -27674,21 +27282,16 @@ pub unsafe fn _mm_cmp_round_ss_mask(a: __m128, b: __m128, imm8: i32, sae: i32) - /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_cmp_round_ss_mask&expand=758) #[inline] #[target_feature(enable = "avx512f")] -#[rustc_args_required_const(3, 4)] -#[cfg_attr(test, assert_instr(vcmp, imm8 = 0, sae = 4))] -pub unsafe fn _mm_mask_cmp_round_ss_mask( +#[cfg_attr(test, assert_instr(vcmp, IMM5 = 0, SAE = 4))] +#[rustc_legacy_const_generics(3, 4)] +pub unsafe fn _mm_mask_cmp_round_ss_mask( k1: __mmask8, a: __m128, b: __m128, - imm8: i32, - sae: i32, ) -> __mmask8 { - macro_rules! call { - ($imm5:expr, $imm4:expr) => { - vcmpss(a, b, $imm5, k1 as i8, $imm4) - }; - } - let r = constify_imm5_sae!(imm8, sae, call); + static_assert_imm5!(IMM5); + static_assert_mantissas_sae!(SAE); + let r = vcmpss(a, b, IMM5, k1 as i8, SAE); transmute(r) } @@ -27733,16 +27336,16 @@ pub unsafe fn _mm_mask_cmp_sd_mask(k1: __mmask8, a: __m128d, b: __m128d, imm8: i /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmp_round_sd_mask&expand=755) #[inline] #[target_feature(enable = "avx512f")] -#[rustc_args_required_const(2, 3)] -#[cfg_attr(test, assert_instr(vcmp, imm8 = 0, sae = 4))] -pub unsafe fn _mm_cmp_round_sd_mask(a: __m128d, b: __m128d, imm8: i32, sae: i32) -> __mmask8 { +#[cfg_attr(test, assert_instr(vcmp, IMM5 = 0, SAE = 4))] +#[rustc_legacy_const_generics(2, 3)] +pub unsafe fn _mm_cmp_round_sd_mask( + a: __m128d, + b: __m128d, +) -> __mmask8 { + static_assert_imm5!(IMM5); + static_assert_mantissas_sae!(SAE); let neg_one = -1; - macro_rules! call { - ($imm5:expr, $imm4:expr) => { - vcmpsd(a, b, $imm5, neg_one, $imm4) - }; - } - let r = constify_imm5_sae!(imm8, sae, call); + let r = vcmpsd(a, b, IMM5, neg_one, SAE); transmute(r) } @@ -27752,21 +27355,16 @@ pub unsafe fn _mm_cmp_round_sd_mask(a: __m128d, b: __m128d, imm8: i32, sae: i32) /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_cmp_round_sd_mask&expand=756) #[inline] #[target_feature(enable = "avx512f")] -#[rustc_args_required_const(3, 4)] -#[cfg_attr(test, assert_instr(vcmp, imm8 = 0, sae = 4))] -pub unsafe fn _mm_mask_cmp_round_sd_mask( +#[cfg_attr(test, assert_instr(vcmp, IMM5 = 0, SAE = 4))] +#[rustc_legacy_const_generics(3, 4)] +pub unsafe fn _mm_mask_cmp_round_sd_mask( k1: __mmask8, a: __m128d, b: __m128d, - imm8: i32, - sae: i32, ) -> __mmask8 { - macro_rules! call { - ($imm5:expr, $imm4:expr) => { - vcmpsd(a, b, $imm5, k1 as i8, $imm4) - }; - } - let r = constify_imm5_sae!(imm8, sae, call); + static_assert_imm5!(IMM5); + static_assert_mantissas_sae!(SAE); + let r = vcmpsd(a, b, IMM5, k1 as i8, SAE); transmute(r) } @@ -31968,30 +31566,21 @@ pub unsafe fn _mm_maskz_getexp_sd(k: __mmask8, a: __m128d, b: __m128d) -> __m128 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=mm_getmant_ss&expand=2898) #[inline] #[target_feature(enable = "avx512f")] -#[cfg_attr(test, assert_instr(vgetmantss, norm = 0, sign = 0))] -#[rustc_args_required_const(2, 3)] -pub unsafe fn _mm_getmant_ss( +#[cfg_attr(test, assert_instr(vgetmantss, NORM = 0, SIGN = 0))] +#[rustc_legacy_const_generics(2, 3)] +pub unsafe fn _mm_getmant_ss< + const NORM: _MM_MANTISSA_NORM_ENUM, + const SIGN: _MM_MANTISSA_SIGN_ENUM, +>( a: __m128, b: __m128, - norm: _MM_MANTISSA_NORM_ENUM, - sign: _MM_MANTISSA_SIGN_ENUM, ) -> __m128 { + static_assert_imm4!(NORM); + static_assert_imm2!(SIGN); let a = a.as_f32x4(); let b = b.as_f32x4(); let zero = _mm_setzero_ps().as_f32x4(); - macro_rules! call { - ($imm4_1:expr, $imm2:expr) => { - vgetmantss( - a, - b, - $imm2 << 2 | $imm4_1, - zero, - 0b1, - _MM_FROUND_CUR_DIRECTION, - ) - }; - } - let r = constify_imm4_mantissas!(norm, sign, call); + let r = vgetmantss(a, b, SIGN << 2 | NORM, zero, 0b1, _MM_FROUND_CUR_DIRECTION); transmute(r) } @@ -32010,25 +31599,23 @@ pub unsafe fn _mm_getmant_ss( /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=mm_mask_getmant_ss&expand=2899) #[inline] #[target_feature(enable = "avx512f")] -#[cfg_attr(test, assert_instr(vgetmantss, norm = 0, sign = 0))] -#[rustc_args_required_const(4, 5)] -pub unsafe fn _mm_mask_getmant_ss( +#[cfg_attr(test, assert_instr(vgetmantss, NORM = 0, SIGN = 0))] +#[rustc_legacy_const_generics(4, 5)] +pub unsafe fn _mm_mask_getmant_ss< + const NORM: _MM_MANTISSA_NORM_ENUM, + const SIGN: _MM_MANTISSA_SIGN_ENUM, +>( src: __m128, k: __mmask8, a: __m128, b: __m128, - norm: _MM_MANTISSA_NORM_ENUM, - sign: _MM_MANTISSA_SIGN_ENUM, ) -> __m128 { + static_assert_imm4!(NORM); + static_assert_imm2!(SIGN); let a = a.as_f32x4(); let b = b.as_f32x4(); let src = src.as_f32x4(); - macro_rules! call { - ($imm4_1:expr, $imm2:expr) => { - vgetmantss(a, b, $imm2 << 2 | $imm4_1, src, k, _MM_FROUND_CUR_DIRECTION) - }; - } - let r = constify_imm4_mantissas!(norm, sign, call); + let r = vgetmantss(a, b, SIGN << 2 | NORM, src, k, _MM_FROUND_CUR_DIRECTION); transmute(r) } @@ -32047,31 +31634,22 @@ pub unsafe fn _mm_mask_getmant_ss( /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=mm_maskz_getmant_ss&expand=2900) #[inline] #[target_feature(enable = "avx512f")] -#[cfg_attr(test, assert_instr(vgetmantss, norm = 0, sign = 0))] -#[rustc_args_required_const(3, 4)] -pub unsafe fn _mm_maskz_getmant_ss( +#[cfg_attr(test, assert_instr(vgetmantss, NORM = 0, SIGN = 0))] +#[rustc_legacy_const_generics(3, 4)] +pub unsafe fn _mm_maskz_getmant_ss< + const NORM: _MM_MANTISSA_NORM_ENUM, + const SIGN: _MM_MANTISSA_SIGN_ENUM, +>( k: __mmask8, a: __m128, b: __m128, - norm: _MM_MANTISSA_NORM_ENUM, - sign: _MM_MANTISSA_SIGN_ENUM, ) -> __m128 { + static_assert_imm4!(NORM); + static_assert_imm2!(SIGN); let a = a.as_f32x4(); let b = b.as_f32x4(); let zero = _mm_setzero_ps().as_f32x4(); - macro_rules! call { - ($imm4_1:expr, $imm2:expr) => { - vgetmantss( - a, - b, - $imm2 << 2 | $imm4_1, - zero, - k, - _MM_FROUND_CUR_DIRECTION, - ) - }; - } - let r = constify_imm4_mantissas!(norm, sign, call); + let r = vgetmantss(a, b, SIGN << 2 | NORM, zero, k, _MM_FROUND_CUR_DIRECTION); transmute(r) } @@ -32090,30 +31668,21 @@ pub unsafe fn _mm_maskz_getmant_ss( /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=mm_getmant_sd&expand=2895) #[inline] #[target_feature(enable = "avx512f")] -#[cfg_attr(test, assert_instr(vgetmantsd, norm = 0, sign = 0))] -#[rustc_args_required_const(2, 3)] -pub unsafe fn _mm_getmant_sd( +#[cfg_attr(test, assert_instr(vgetmantsd, NORM = 0, SIGN = 0))] +#[rustc_legacy_const_generics(2, 3)] +pub unsafe fn _mm_getmant_sd< + const NORM: _MM_MANTISSA_NORM_ENUM, + const SIGN: _MM_MANTISSA_SIGN_ENUM, +>( a: __m128d, b: __m128d, - norm: _MM_MANTISSA_NORM_ENUM, - sign: _MM_MANTISSA_SIGN_ENUM, ) -> __m128d { + static_assert_imm4!(NORM); + static_assert_imm2!(SIGN); let a = a.as_f64x2(); let b = b.as_f64x2(); let zero = _mm_setzero_pd().as_f64x2(); - macro_rules! call { - ($imm4_1:expr, $imm2:expr) => { - vgetmantsd( - a, - b, - $imm2 << 2 | $imm4_1, - zero, - 0b1, - _MM_FROUND_CUR_DIRECTION, - ) - }; - } - let r = constify_imm4_mantissas!(norm, sign, call); + let r = vgetmantsd(a, b, SIGN << 2 | NORM, zero, 0b1, _MM_FROUND_CUR_DIRECTION); transmute(r) } @@ -32132,25 +31701,23 @@ pub unsafe fn _mm_getmant_sd( /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=mm_mask_getmant_sd&expand=2896) #[inline] #[target_feature(enable = "avx512f")] -#[cfg_attr(test, assert_instr(vgetmantsd, norm = 0, sign = 0))] -#[rustc_args_required_const(4, 5)] -pub unsafe fn _mm_mask_getmant_sd( +#[cfg_attr(test, assert_instr(vgetmantsd, NORM = 0, SIGN = 0))] +#[rustc_legacy_const_generics(4, 5)] +pub unsafe fn _mm_mask_getmant_sd< + const NORM: _MM_MANTISSA_NORM_ENUM, + const SIGN: _MM_MANTISSA_SIGN_ENUM, +>( src: __m128d, k: __mmask8, a: __m128d, b: __m128d, - norm: _MM_MANTISSA_NORM_ENUM, - sign: _MM_MANTISSA_SIGN_ENUM, ) -> __m128d { + static_assert_imm4!(NORM); + static_assert_imm2!(SIGN); let a = a.as_f64x2(); let b = b.as_f64x2(); let src = src.as_f64x2(); - macro_rules! call { - ($imm4_1:expr, $imm2:expr) => { - vgetmantsd(a, b, $imm2 << 2 | $imm4_1, src, k, _MM_FROUND_CUR_DIRECTION) - }; - } - let r = constify_imm4_mantissas!(norm, sign, call); + let r = vgetmantsd(a, b, SIGN << 2 | NORM, src, k, _MM_FROUND_CUR_DIRECTION); transmute(r) } @@ -32169,31 +31736,22 @@ pub unsafe fn _mm_mask_getmant_sd( /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=mm_maskz_getmant_sd&expand=2897) #[inline] #[target_feature(enable = "avx512f")] -#[cfg_attr(test, assert_instr(vgetmantsd, norm = 0, sign = 0))] -#[rustc_args_required_const(3, 4)] -pub unsafe fn _mm_maskz_getmant_sd( +#[cfg_attr(test, assert_instr(vgetmantsd, NORM = 0, SIGN = 0))] +#[rustc_legacy_const_generics(3, 4)] +pub unsafe fn _mm_maskz_getmant_sd< + const NORM: _MM_MANTISSA_NORM_ENUM, + const SIGN: _MM_MANTISSA_SIGN_ENUM, +>( k: __mmask8, a: __m128d, b: __m128d, - norm: _MM_MANTISSA_NORM_ENUM, - sign: _MM_MANTISSA_SIGN_ENUM, ) -> __m128d { + static_assert_imm4!(NORM); + static_assert_imm2!(SIGN); let a = a.as_f64x2(); let b = b.as_f64x2(); let zero = _mm_setzero_pd().as_f64x2(); - macro_rules! call { - ($imm4_1:expr, $imm2:expr) => { - vgetmantsd( - a, - b, - $imm2 << 2 | $imm4_1, - zero, - k, - _MM_FROUND_CUR_DIRECTION, - ) - }; - } - let r = constify_imm4_mantissas!(norm, sign, call); + let r = vgetmantsd(a, b, SIGN << 2 | NORM, zero, k, _MM_FROUND_CUR_DIRECTION); transmute(r) } @@ -34042,24 +33600,23 @@ pub unsafe fn _mm_maskz_getexp_round_sd( /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=mm_getmant_round_ss&expand=2892) #[inline] #[target_feature(enable = "avx512f")] -#[cfg_attr(test, assert_instr(vgetmantss, norm = 0, sign = 0, sae = 4))] -#[rustc_args_required_const(2, 3, 4)] -pub unsafe fn _mm_getmant_round_ss( +#[cfg_attr(test, assert_instr(vgetmantss, NORM = 0, SIGN = 0, SAE = 4))] +#[rustc_legacy_const_generics(2, 3, 4)] +pub unsafe fn _mm_getmant_round_ss< + const NORM: _MM_MANTISSA_NORM_ENUM, + const SIGN: _MM_MANTISSA_SIGN_ENUM, + const SAE: i32, +>( a: __m128, b: __m128, - norm: _MM_MANTISSA_NORM_ENUM, - sign: _MM_MANTISSA_SIGN_ENUM, - sae: i32, ) -> __m128 { + static_assert_imm4!(NORM); + static_assert_imm2!(SIGN); + static_assert_mantissas_sae!(SAE); let a = a.as_f32x4(); let b = b.as_f32x4(); let zero = _mm_setzero_ps().as_f32x4(); - macro_rules! call { - ($imm4_1:expr, $imm2:expr, $imm4_2:expr) => { - vgetmantss(a, b, $imm2 << 2 | $imm4_1, zero, 0b1, $imm4_2) - }; - } - let r = constify_imm4_mantissas_sae!(norm, sign, sae, call); + let r = vgetmantss(a, b, SIGN << 2 | NORM, zero, 0b1, SAE); transmute(r) } @@ -34078,26 +33635,25 @@ pub unsafe fn _mm_getmant_round_ss( /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=mm_mask_getmant_round_ss&expand=2893) #[inline] #[target_feature(enable = "avx512f")] -#[cfg_attr(test, assert_instr(vgetmantss, norm = 0, sign = 0, sae = 4))] -#[rustc_args_required_const(4, 5, 6)] -pub unsafe fn _mm_mask_getmant_round_ss( +#[cfg_attr(test, assert_instr(vgetmantss, NORM = 0, SIGN = 0, SAE = 4))] +#[rustc_legacy_const_generics(4, 5, 6)] +pub unsafe fn _mm_mask_getmant_round_ss< + const NORM: _MM_MANTISSA_NORM_ENUM, + const SIGN: _MM_MANTISSA_SIGN_ENUM, + const SAE: i32, +>( src: __m128, k: __mmask8, a: __m128, b: __m128, - norm: _MM_MANTISSA_NORM_ENUM, - sign: _MM_MANTISSA_SIGN_ENUM, - sae: i32, ) -> __m128 { + static_assert_imm4!(NORM); + static_assert_imm2!(SIGN); + static_assert_mantissas_sae!(SAE); let a = a.as_f32x4(); let b = b.as_f32x4(); let src = src.as_f32x4(); - macro_rules! call { - ($imm4_1:expr, $imm2:expr, $imm4_2:expr) => { - vgetmantss(a, b, $imm2 << 2 | $imm4_1, src, k, $imm4_2) - }; - } - let r = constify_imm4_mantissas_sae!(norm, sign, sae, call); + let r = vgetmantss(a, b, SIGN << 2 | NORM, src, k, SAE); transmute(r) } @@ -34116,25 +33672,24 @@ pub unsafe fn _mm_mask_getmant_round_ss( /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=mm_maskz_getmant_round_ss&expand=2894) #[inline] #[target_feature(enable = "avx512f")] -#[cfg_attr(test, assert_instr(vgetmantss, norm = 0, sign = 0, sae = 4))] -#[rustc_args_required_const(3, 4, 5)] -pub unsafe fn _mm_maskz_getmant_round_ss( +#[cfg_attr(test, assert_instr(vgetmantss, NORM = 0, SIGN = 0, SAE = 4))] +#[rustc_legacy_const_generics(3, 4, 5)] +pub unsafe fn _mm_maskz_getmant_round_ss< + const NORM: _MM_MANTISSA_NORM_ENUM, + const SIGN: _MM_MANTISSA_SIGN_ENUM, + const SAE: i32, +>( k: __mmask8, a: __m128, b: __m128, - norm: _MM_MANTISSA_NORM_ENUM, - sign: _MM_MANTISSA_SIGN_ENUM, - sae: i32, ) -> __m128 { + static_assert_imm4!(NORM); + static_assert_imm2!(SIGN); + static_assert_mantissas_sae!(SAE); let a = a.as_f32x4(); let b = b.as_f32x4(); let zero = _mm_setzero_ps().as_f32x4(); - macro_rules! call { - ($imm4_1:expr, $imm2:expr, $imm4_2:expr) => { - vgetmantss(a, b, $imm2 << 2 | $imm4_1, zero, k, $imm4_2) - }; - } - let r = constify_imm4_mantissas_sae!(norm, sign, sae, call); + let r = vgetmantss(a, b, SIGN << 2 | NORM, zero, k, SAE); transmute(r) } @@ -34153,24 +33708,23 @@ pub unsafe fn _mm_maskz_getmant_round_ss( /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=mm_getmant_round_sd&expand=2889) #[inline] #[target_feature(enable = "avx512f")] -#[cfg_attr(test, assert_instr(vgetmantsd, norm = 0, sign = 0, sae = 4))] -#[rustc_args_required_const(2, 3, 4)] -pub unsafe fn _mm_getmant_round_sd( +#[cfg_attr(test, assert_instr(vgetmantsd, NORM = 0, SIGN = 0, SAE = 4))] +#[rustc_legacy_const_generics(2, 3, 4)] +pub unsafe fn _mm_getmant_round_sd< + const NORM: _MM_MANTISSA_NORM_ENUM, + const SIGN: _MM_MANTISSA_SIGN_ENUM, + const SAE: i32, +>( a: __m128d, b: __m128d, - norm: _MM_MANTISSA_NORM_ENUM, - sign: _MM_MANTISSA_SIGN_ENUM, - sae: i32, ) -> __m128d { + static_assert_imm4!(NORM); + static_assert_imm2!(SIGN); + static_assert_mantissas_sae!(SAE); let a = a.as_f64x2(); let b = b.as_f64x2(); let zero = _mm_setzero_pd().as_f64x2(); - macro_rules! call { - ($imm4_1:expr, $imm2:expr, $imm4_2:expr) => { - vgetmantsd(a, b, $imm2 << 2 | $imm4_1, zero, 0b1, $imm4_2) - }; - } - let r = constify_imm4_mantissas_sae!(norm, sign, sae, call); + let r = vgetmantsd(a, b, SIGN << 2 | NORM, zero, 0b1, SAE); transmute(r) } @@ -34189,26 +33743,25 @@ pub unsafe fn _mm_getmant_round_sd( /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=mm_mask_getmant_round_sd&expand=2890) #[inline] #[target_feature(enable = "avx512f")] -#[cfg_attr(test, assert_instr(vgetmantsd, norm = 0, sign = 0, sae = 4))] -#[rustc_args_required_const(4, 5, 6)] -pub unsafe fn _mm_mask_getmant_round_sd( +#[cfg_attr(test, assert_instr(vgetmantsd, NORM = 0, SIGN = 0, SAE = 4))] +#[rustc_legacy_const_generics(4, 5, 6)] +pub unsafe fn _mm_mask_getmant_round_sd< + const NORM: _MM_MANTISSA_NORM_ENUM, + const SIGN: _MM_MANTISSA_SIGN_ENUM, + const SAE: i32, +>( src: __m128d, k: __mmask8, a: __m128d, b: __m128d, - norm: _MM_MANTISSA_NORM_ENUM, - sign: _MM_MANTISSA_SIGN_ENUM, - sae: i32, ) -> __m128d { + static_assert_imm4!(NORM); + static_assert_imm2!(SIGN); + static_assert_mantissas_sae!(SAE); let a = a.as_f64x2(); let b = b.as_f64x2(); let src = src.as_f64x2(); - macro_rules! call { - ($imm4_1:expr, $imm2:expr, $imm4_2:expr) => { - vgetmantsd(a, b, $imm2 << 2 | $imm4_1, src, k, $imm4_2) - }; - } - let r = constify_imm4_mantissas_sae!(norm, sign, sae, call); + let r = vgetmantsd(a, b, SIGN << 2 | NORM, src, k, SAE); transmute(r) } @@ -34227,25 +33780,24 @@ pub unsafe fn _mm_mask_getmant_round_sd( /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=mm_maskz_getmant_round_sd&expand=2891) #[inline] #[target_feature(enable = "avx512f")] -#[cfg_attr(test, assert_instr(vgetmantsd, norm = 0, sign = 0, sae = 4))] -#[rustc_args_required_const(3, 4, 5)] -pub unsafe fn _mm_maskz_getmant_round_sd( +#[cfg_attr(test, assert_instr(vgetmantsd, NORM = 0, SIGN = 0, SAE = 4))] +#[rustc_legacy_const_generics(3, 4, 5)] +pub unsafe fn _mm_maskz_getmant_round_sd< + const NORM: _MM_MANTISSA_NORM_ENUM, + const SIGN: _MM_MANTISSA_SIGN_ENUM, + const SAE: i32, +>( k: __mmask8, a: __m128d, b: __m128d, - norm: _MM_MANTISSA_NORM_ENUM, - sign: _MM_MANTISSA_SIGN_ENUM, - sae: i32, ) -> __m128d { + static_assert_imm4!(NORM); + static_assert_imm2!(SIGN); + static_assert_mantissas_sae!(SAE); let a = a.as_f64x2(); let b = b.as_f64x2(); let zero = _mm_setzero_pd().as_f64x2(); - macro_rules! call { - ($imm4_1:expr, $imm2:expr, $imm4_2:expr) => { - vgetmantsd(a, b, $imm2 << 2 | $imm4_1, zero, k, $imm4_2) - }; - } - let r = constify_imm4_mantissas_sae!(norm, sign, sae, call); + let r = vgetmantsd(a, b, SIGN << 2 | NORM, zero, k, SAE); transmute(r) } @@ -34261,18 +33813,18 @@ pub unsafe fn _mm_maskz_getmant_round_sd( /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=mm_roundscale_round_ss&expand=4796) #[inline] #[target_feature(enable = "avx512f")] -#[cfg_attr(test, assert_instr(vrndscaless, imm8 = 0, sae = 8))] -#[rustc_args_required_const(2, 3)] -pub unsafe fn _mm_roundscale_round_ss(a: __m128, b: __m128, imm8: i32, sae: i32) -> __m128 { +#[cfg_attr(test, assert_instr(vrndscaless, IMM8 = 0, SAE = 8))] +#[rustc_legacy_const_generics(2, 3)] +pub unsafe fn _mm_roundscale_round_ss( + a: __m128, + b: __m128, +) -> __m128 { + static_assert_imm8!(IMM8); + static_assert_mantissas_sae!(SAE); let a = a.as_f32x4(); let b = b.as_f32x4(); let zero = _mm_setzero_ps().as_f32x4(); - macro_rules! call { - ($imm8:expr, $imm4:expr) => { - vrndscaless(a, b, zero, 0b11111111, $imm8, $imm4) - }; - } - let r = constify_imm8_roundscale!(imm8, sae, call); + let r = vrndscaless(a, b, zero, 0b11111111, IMM8, SAE); transmute(r) } @@ -34288,25 +33840,20 @@ pub unsafe fn _mm_roundscale_round_ss(a: __m128, b: __m128, imm8: i32, sae: i32) /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=mm_mask_roundscale_round_ss&expand=4794) #[inline] #[target_feature(enable = "avx512f")] -#[cfg_attr(test, assert_instr(vrndscaless, imm8 = 0, sae = 8))] -#[rustc_args_required_const(4, 5)] -pub unsafe fn _mm_mask_roundscale_round_ss( +#[cfg_attr(test, assert_instr(vrndscaless, IMM8 = 0, SAE = 8))] +#[rustc_legacy_const_generics(4, 5)] +pub unsafe fn _mm_mask_roundscale_round_ss( src: __m128, k: __mmask8, a: __m128, b: __m128, - imm8: i32, - sae: i32, ) -> __m128 { + static_assert_imm8!(IMM8); + static_assert_mantissas_sae!(SAE); let a = a.as_f32x4(); let b = b.as_f32x4(); let src = src.as_f32x4(); - macro_rules! call { - ($imm8:expr, $imm4:expr) => { - vrndscaless(a, b, src, k, $imm8, $imm4) - }; - } - let r = constify_imm8_roundscale!(imm8, sae, call); + let r = vrndscaless(a, b, src, k, IMM8, SAE); transmute(r) } @@ -34322,24 +33869,19 @@ pub unsafe fn _mm_mask_roundscale_round_ss( /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=mm_maskz_roundscale_round_ss&expand=4795) #[inline] #[target_feature(enable = "avx512f")] -#[cfg_attr(test, assert_instr(vrndscaless, imm8 = 0, sae = 8))] -#[rustc_args_required_const(3, 4)] -pub unsafe fn _mm_maskz_roundscale_round_ss( +#[cfg_attr(test, assert_instr(vrndscaless, IMM8 = 0, SAE = 8))] +#[rustc_legacy_const_generics(3, 4)] +pub unsafe fn _mm_maskz_roundscale_round_ss( k: __mmask8, a: __m128, b: __m128, - imm8: i32, - sae: i32, ) -> __m128 { + static_assert_imm8!(IMM8); + static_assert_mantissas_sae!(SAE); let a = a.as_f32x4(); let b = b.as_f32x4(); let zero = _mm_setzero_ps().as_f32x4(); - macro_rules! call { - ($imm8:expr, $imm4:expr) => { - vrndscaless(a, b, zero, k, $imm8, $imm4) - }; - } - let r = constify_imm8_roundscale!(imm8, sae, call); + let r = vrndscaless(a, b, zero, k, IMM8, SAE); transmute(r) } @@ -34355,18 +33897,18 @@ pub unsafe fn _mm_maskz_roundscale_round_ss( /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=mm_roundscale_round_sd&expand=4793) #[inline] #[target_feature(enable = "avx512f")] -#[cfg_attr(test, assert_instr(vrndscalesd, imm8 = 0, sae = 8))] -#[rustc_args_required_const(2, 3)] -pub unsafe fn _mm_roundscale_round_sd(a: __m128d, b: __m128d, imm8: i32, sae: i32) -> __m128d { +#[cfg_attr(test, assert_instr(vrndscalesd, IMM8 = 0, SAE = 8))] +#[rustc_legacy_const_generics(2, 3)] +pub unsafe fn _mm_roundscale_round_sd( + a: __m128d, + b: __m128d, +) -> __m128d { + static_assert_imm8!(IMM8); + static_assert_mantissas_sae!(SAE); let a = a.as_f64x2(); let b = b.as_f64x2(); let zero = _mm_setzero_pd().as_f64x2(); - macro_rules! call { - ($imm8:expr, $imm4:expr) => { - vrndscalesd(a, b, zero, 0b11111111, $imm8, $imm4) - }; - } - let r = constify_imm8_roundscale!(imm8, sae, call); + let r = vrndscalesd(a, b, zero, 0b11111111, IMM8, SAE); transmute(r) } @@ -34382,25 +33924,20 @@ pub unsafe fn _mm_roundscale_round_sd(a: __m128d, b: __m128d, imm8: i32, sae: i3 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=mm_mask_roundscale_round_sd&expand=4791) #[inline] #[target_feature(enable = "avx512f")] -#[cfg_attr(test, assert_instr(vrndscalesd, imm8 = 0, sae = 8))] -#[rustc_args_required_const(4, 5)] -pub unsafe fn _mm_mask_roundscale_round_sd( +#[cfg_attr(test, assert_instr(vrndscalesd, IMM8 = 0, SAE = 8))] +#[rustc_legacy_const_generics(4, 5)] +pub unsafe fn _mm_mask_roundscale_round_sd( src: __m128d, k: __mmask8, a: __m128d, b: __m128d, - imm8: i32, - sae: i32, ) -> __m128d { + static_assert_imm8!(IMM8); + static_assert_mantissas_sae!(SAE); let a = a.as_f64x2(); let b = b.as_f64x2(); let src = src.as_f64x2(); - macro_rules! call { - ($imm8:expr, $imm4:expr) => { - vrndscalesd(a, b, src, k, $imm8, $imm4) - }; - } - let r = constify_imm8_roundscale!(imm8, sae, call); + let r = vrndscalesd(a, b, src, k, IMM8, SAE); transmute(r) } @@ -34416,24 +33953,19 @@ pub unsafe fn _mm_mask_roundscale_round_sd( /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=mm_maskz_roundscale_round_sd&expand=4792) #[inline] #[target_feature(enable = "avx512f")] -#[cfg_attr(test, assert_instr(vrndscalesd, imm8 = 0, sae = 8))] -#[rustc_args_required_const(3, 4)] -pub unsafe fn _mm_maskz_roundscale_round_sd( +#[cfg_attr(test, assert_instr(vrndscalesd, IMM8 = 0, SAE = 8))] +#[rustc_legacy_const_generics(3, 4)] +pub unsafe fn _mm_maskz_roundscale_round_sd( k: __mmask8, a: __m128d, b: __m128d, - imm8: i32, - sae: i32, ) -> __m128d { + static_assert_imm8!(IMM8); + static_assert_mantissas_sae!(SAE); let a = a.as_f64x2(); let b = b.as_f64x2(); let zero = _mm_setzero_pd().as_f64x2(); - macro_rules! call { - ($imm8:expr, $imm4:expr) => { - vrndscalesd(a, b, zero, k, $imm8, $imm4) - }; - } - let r = constify_imm8_roundscale!(imm8, sae, call); + let r = vrndscalesd(a, b, zero, k, IMM8, SAE); transmute(r) } @@ -35600,8 +35132,8 @@ pub unsafe fn _mm_fixupimm_ss(a: __m128, b: __m128, c: __m128i, imm8: i32) -> __ vfixupimmss(a, b, c, $imm8, 0b11111111, _MM_FROUND_CUR_DIRECTION) }; } - let fixupimm = constify_imm8_sae!(imm8, call); - let fixupimm: f32 = simd_extract(fixupimm, 0); + let r = constify_imm8_sae!(imm8, call); + let fixupimm: f32 = simd_extract(r, 0); let r = simd_insert(a, 0, fixupimm); transmute(r) } @@ -35746,25 +35278,20 @@ pub unsafe fn _mm_maskz_fixupimm_sd( /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=mm_fixupimm_round_ss&expand=2511) #[inline] #[target_feature(enable = "avx512f")] -#[cfg_attr(test, assert_instr(vfixupimmss, imm8 = 0, sae = 8))] -#[rustc_args_required_const(3, 4)] -pub unsafe fn _mm_fixupimm_round_ss( +#[cfg_attr(test, assert_instr(vfixupimmss, IMM8 = 0, SAE = 8))] +#[rustc_legacy_const_generics(3, 4)] +pub unsafe fn _mm_fixupimm_round_ss( a: __m128, b: __m128, c: __m128i, - imm8: i32, - sae: i32, ) -> __m128 { + static_assert_imm8!(IMM8); + static_assert_mantissas_sae!(SAE); let a = a.as_f32x4(); let b = b.as_f32x4(); let c = c.as_i32x4(); - macro_rules! call { - ($imm8:expr, $imm4:expr) => { - vfixupimmss(a, b, c, $imm8, 0b11111111, $imm4) - }; - } - let fixupimm = constify_imm8_roundscale!(imm8, sae, call); - let fixupimm: f32 = simd_extract(fixupimm, 0); + let r = vfixupimmss(a, b, c, IMM8, 0b11111111, SAE); + let fixupimm: f32 = simd_extract(r, 0); let r = simd_insert(a, 0, fixupimm); transmute(r) } @@ -35775,26 +35302,21 @@ pub unsafe fn _mm_fixupimm_round_ss( /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=mm_mask_fixupimm_round_ss&expand=2512) #[inline] #[target_feature(enable = "avx512f")] -#[cfg_attr(test, assert_instr(vfixupimmss, imm8 = 0, sae = 8))] -#[rustc_args_required_const(4, 5)] -pub unsafe fn _mm_mask_fixupimm_round_ss( +#[cfg_attr(test, assert_instr(vfixupimmss, IMM8 = 0, SAE = 8))] +#[rustc_legacy_const_generics(4, 5)] +pub unsafe fn _mm_mask_fixupimm_round_ss( a: __m128, k: __mmask8, b: __m128, c: __m128i, - imm8: i32, - sae: i32, ) -> __m128 { + static_assert_imm8!(IMM8); + static_assert_mantissas_sae!(SAE); let a = a.as_f32x4(); let b = b.as_f32x4(); let c = c.as_i32x4(); - macro_rules! call { - ($imm8:expr, $imm4:expr) => { - vfixupimmss(a, b, c, $imm8, k, $imm4) - }; - } - let fixupimm = constify_imm8_roundscale!(imm8, sae, call); - let fixupimm: f32 = simd_extract(fixupimm, 0); + let r = vfixupimmss(a, b, c, IMM8, k, SAE); + let fixupimm: f32 = simd_extract(r, 0); let r = simd_insert(a, 0, fixupimm); transmute(r) } @@ -35805,26 +35327,21 @@ pub unsafe fn _mm_mask_fixupimm_round_ss( /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=mm_maskz_fixupimm_round_ss&expand=2513) #[inline] #[target_feature(enable = "avx512f")] -#[cfg_attr(test, assert_instr(vfixupimmss, imm8 = 0, sae = 8))] -#[rustc_args_required_const(4, 5)] -pub unsafe fn _mm_maskz_fixupimm_round_ss( +#[cfg_attr(test, assert_instr(vfixupimmss, IMM8 = 0, SAE = 8))] +#[rustc_legacy_const_generics(4, 5)] +pub unsafe fn _mm_maskz_fixupimm_round_ss( k: __mmask8, a: __m128, b: __m128, c: __m128i, - imm8: i32, - sae: i32, ) -> __m128 { + static_assert_imm8!(IMM8); + static_assert_mantissas_sae!(SAE); let a = a.as_f32x4(); let b = b.as_f32x4(); let c = c.as_i32x4(); - macro_rules! call { - ($imm8:expr, $imm4:expr) => { - vfixupimmssz(a, b, c, $imm8, k, $imm4) - }; - } - let fixupimm = constify_imm8_roundscale!(imm8, sae, call); - let fixupimm: f32 = simd_extract(fixupimm, 0); + let r = vfixupimmssz(a, b, c, IMM8, k, SAE); + let fixupimm: f32 = simd_extract(r, 0); let r = simd_insert(a, 0, fixupimm); transmute(r) } @@ -35835,25 +35352,20 @@ pub unsafe fn _mm_maskz_fixupimm_round_ss( /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=mm_fixupimm_round_sd&expand=2508) #[inline] #[target_feature(enable = "avx512f")] -#[cfg_attr(test, assert_instr(vfixupimmsd, imm8 = 0, sae = 8))] -#[rustc_args_required_const(3, 4)] -pub unsafe fn _mm_fixupimm_round_sd( +#[cfg_attr(test, assert_instr(vfixupimmsd, IMM8 = 0, SAE = 8))] +#[rustc_legacy_const_generics(3, 4)] +pub unsafe fn _mm_fixupimm_round_sd( a: __m128d, b: __m128d, c: __m128i, - imm8: i32, - sae: i32, ) -> __m128d { + static_assert_imm8!(IMM8); + static_assert_mantissas_sae!(SAE); let a = a.as_f64x2(); let b = b.as_f64x2(); let c = c.as_i64x2(); - macro_rules! call { - ($imm8:expr, $imm4:expr) => { - vfixupimmsd(a, b, c, $imm8, 0b11111111, $imm4) - }; - } - let fixupimm = constify_imm8_roundscale!(imm8, sae, call); - let fixupimm: f64 = simd_extract(fixupimm, 0); + let r = vfixupimmsd(a, b, c, IMM8, 0b11111111, SAE); + let fixupimm: f64 = simd_extract(r, 0); let r = simd_insert(a, 0, fixupimm); transmute(r) } @@ -35864,26 +35376,21 @@ pub unsafe fn _mm_fixupimm_round_sd( /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=mm_mask_fixupimm_round_sd&expand=2509) #[inline] #[target_feature(enable = "avx512f")] -#[cfg_attr(test, assert_instr(vfixupimmsd, imm8 = 0, sae = 8))] -#[rustc_args_required_const(4, 5)] -pub unsafe fn _mm_mask_fixupimm_round_sd( +#[cfg_attr(test, assert_instr(vfixupimmsd, IMM8 = 0, SAE = 8))] +#[rustc_legacy_const_generics(4, 5)] +pub unsafe fn _mm_mask_fixupimm_round_sd( a: __m128d, k: __mmask8, b: __m128d, c: __m128i, - imm8: i32, - sae: i32, ) -> __m128d { + static_assert_imm8!(IMM8); + static_assert_mantissas_sae!(SAE); let a = a.as_f64x2(); let b = b.as_f64x2(); let c = c.as_i64x2(); - macro_rules! call { - ($imm8:expr, $imm4:expr) => { - vfixupimmsd(a, b, c, $imm8, k, $imm4) - }; - } - let fixupimm = constify_imm8_roundscale!(imm8, sae, call); - let fixupimm: f64 = simd_extract(fixupimm, 0); + let r = vfixupimmsd(a, b, c, IMM8, k, SAE); + let fixupimm: f64 = simd_extract(r, 0); let r = simd_insert(a, 0, fixupimm); transmute(r) } @@ -35894,26 +35401,21 @@ pub unsafe fn _mm_mask_fixupimm_round_sd( /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=mm_maskz_fixupimm_round_sd&expand=2510) #[inline] #[target_feature(enable = "avx512f")] -#[cfg_attr(test, assert_instr(vfixupimmsd, imm8 = 0, sae = 8))] -#[rustc_args_required_const(4, 5)] -pub unsafe fn _mm_maskz_fixupimm_round_sd( +#[cfg_attr(test, assert_instr(vfixupimmsd, IMM8 = 0, SAE = 8))] +#[rustc_legacy_const_generics(4, 5)] +pub unsafe fn _mm_maskz_fixupimm_round_sd( k: __mmask8, a: __m128d, b: __m128d, c: __m128i, - imm8: i32, - sae: i32, ) -> __m128d { + static_assert_imm8!(IMM8); + static_assert_mantissas_sae!(SAE); let a = a.as_f64x2(); let b = b.as_f64x2(); let c = c.as_i64x2(); - macro_rules! call { - ($imm8:expr, $imm4:expr) => { - vfixupimmsdz(a, b, c, $imm8, k, $imm4) - }; - } - let fixupimm = constify_imm8_roundscale!(imm8, sae, call); - let fixupimm: f64 = simd_extract(fixupimm, 0); + let r = vfixupimmsdz(a, b, c, IMM8, k, SAE); + let fixupimm: f64 = simd_extract(r, 0); let r = simd_insert(a, 0, fixupimm); transmute(r) } @@ -36523,17 +36025,14 @@ pub unsafe fn _mm_cvtu32_sd(a: __m128d, b: u32) -> __m128d { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_comi_round_ss&expand=1175) #[inline] #[target_feature(enable = "avx512f")] -#[cfg_attr(test, assert_instr(vcmp, imm8 = 5, sae = 4))] //should be vcomiss -#[rustc_args_required_const(2, 3)] -pub unsafe fn _mm_comi_round_ss(a: __m128, b: __m128, imm8: i32, sae: i32) -> i32 { +#[cfg_attr(test, assert_instr(vcmp, IMM5 = 5, SAE = 4))] //should be vcomiss +#[rustc_legacy_const_generics(2, 3)] +pub unsafe fn _mm_comi_round_ss(a: __m128, b: __m128) -> i32 { + static_assert_imm5!(IMM5); + static_assert_mantissas_sae!(SAE); let a = a.as_f32x4(); let b = b.as_f32x4(); - macro_rules! call { - ($imm8:expr, $imm4:expr) => { - vcomiss(a, b, $imm8, $imm4) - }; - } - let r = constify_imm5_sae!(imm8, sae, call); + let r = vcomiss(a, b, IMM5, SAE); transmute(r) } @@ -36543,17 +36042,14 @@ pub unsafe fn _mm_comi_round_ss(a: __m128, b: __m128, imm8: i32, sae: i32) -> i3 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_comi_round_sd&expand=1174) #[inline] #[target_feature(enable = "avx512f")] -#[cfg_attr(test, assert_instr(vcmp, imm8 = 5, sae = 4))] //should be vcomisd -#[rustc_args_required_const(2, 3)] -pub unsafe fn _mm_comi_round_sd(a: __m128d, b: __m128d, imm8: i32, sae: i32) -> i32 { +#[cfg_attr(test, assert_instr(vcmp, IMM5 = 5, SAE = 4))] //should be vcomisd +#[rustc_legacy_const_generics(2, 3)] +pub unsafe fn _mm_comi_round_sd(a: __m128d, b: __m128d) -> i32 { + static_assert_imm5!(IMM5); + static_assert_mantissas_sae!(SAE); let a = a.as_f64x2(); let b = b.as_f64x2(); - macro_rules! call { - ($imm8:expr, $imm4:expr) => { - vcomisd(a, b, $imm8, $imm4) - }; - } - let r = constify_imm5_sae!(imm8, sae, call); + let r = vcomisd(a, b, IMM5, SAE); transmute(r) } @@ -40826,7 +40322,7 @@ mod tests { #[simd_test(enable = "avx512f")] unsafe fn test_mm512_getmant_ps() { let a = _mm512_set1_ps(10.); - let r = _mm512_getmant_ps(a, _MM_MANT_NORM_P75_1P5, _MM_MANT_SIGN_NAN); + let r = _mm512_getmant_ps::<_MM_MANT_NORM_P75_1P5, _MM_MANT_SIGN_NAN>(a); let e = _mm512_set1_ps(1.25); assert_eq_m512(r, e); } @@ -40834,14 +40330,12 @@ mod tests { #[simd_test(enable = "avx512f")] unsafe fn test_mm512_mask_getmant_ps() { let a = _mm512_set1_ps(10.); - let r = _mm512_mask_getmant_ps(a, 0, a, _MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC); + let r = _mm512_mask_getmant_ps::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(a, 0, a); assert_eq_m512(r, a); - let r = _mm512_mask_getmant_ps( + let r = _mm512_mask_getmant_ps::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>( a, 0b11111111_00000000, a, - _MM_MANT_NORM_1_2, - _MM_MANT_SIGN_SRC, ); let e = _mm512_setr_ps( 10., 10., 10., 10., 10., 10., 10., 10., 1.25, 1.25, 1.25, 1.25, 1.25, 1.25, 1.25, 1.25, @@ -40852,10 +40346,10 @@ mod tests { #[simd_test(enable = "avx512f")] unsafe fn test_mm512_maskz_getmant_ps() { let a = _mm512_set1_ps(10.); - let r = _mm512_maskz_getmant_ps(0, a, _MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC); + let r = _mm512_maskz_getmant_ps::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(0, a); assert_eq_m512(r, _mm512_setzero_ps()); let r = - _mm512_maskz_getmant_ps(0b11111111_00000000, a, _MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC); + _mm512_maskz_getmant_ps::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(0b11111111_00000000, a); let e = _mm512_setr_ps( 0., 0., 0., 0., 0., 0., 0., 0., 1.25, 1.25, 1.25, 1.25, 1.25, 1.25, 1.25, 1.25, ); @@ -40865,7 +40359,7 @@ mod tests { #[simd_test(enable = "avx512f,avx512vl")] unsafe fn test_mm256_getmant_ps() { let a = _mm256_set1_ps(10.); - let r = _mm256_getmant_ps(a, _MM_MANT_NORM_P75_1P5, _MM_MANT_SIGN_NAN); + let r = _mm256_getmant_ps::<_MM_MANT_NORM_P75_1P5, _MM_MANT_SIGN_NAN>(a); let e = _mm256_set1_ps(1.25); assert_eq_m256(r, e); } @@ -40873,9 +40367,9 @@ mod tests { #[simd_test(enable = "avx512f,avx512vl")] unsafe fn test_mm256_mask_getmant_ps() { let a = _mm256_set1_ps(10.); - let r = _mm256_mask_getmant_ps(a, 0, a, _MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC); + let r = _mm256_mask_getmant_ps::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(a, 0, a); assert_eq_m256(r, a); - let r = _mm256_mask_getmant_ps(a, 0b11111111, a, _MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC); + let r = _mm256_mask_getmant_ps::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(a, 0b11111111, a); let e = _mm256_set1_ps(1.25); assert_eq_m256(r, e); } @@ -40883,9 +40377,9 @@ mod tests { #[simd_test(enable = "avx512f,avx512vl")] unsafe fn test_mm256_maskz_getmant_ps() { let a = _mm256_set1_ps(10.); - let r = _mm256_maskz_getmant_ps(0, a, _MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC); + let r = _mm256_maskz_getmant_ps::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(0, a); assert_eq_m256(r, _mm256_setzero_ps()); - let r = _mm256_maskz_getmant_ps(0b11111111, a, _MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC); + let r = _mm256_maskz_getmant_ps::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(0b11111111, a); let e = _mm256_set1_ps(1.25); assert_eq_m256(r, e); } @@ -40893,7 +40387,7 @@ mod tests { #[simd_test(enable = "avx512f,avx512vl")] unsafe fn test_mm_getmant_ps() { let a = _mm_set1_ps(10.); - let r = _mm_getmant_ps(a, _MM_MANT_NORM_P75_1P5, _MM_MANT_SIGN_NAN); + let r = _mm_getmant_ps::<_MM_MANT_NORM_P75_1P5, _MM_MANT_SIGN_NAN>(a); let e = _mm_set1_ps(1.25); assert_eq_m128(r, e); } @@ -40901,9 +40395,9 @@ mod tests { #[simd_test(enable = "avx512f,avx512vl")] unsafe fn test_mm_mask_getmant_ps() { let a = _mm_set1_ps(10.); - let r = _mm_mask_getmant_ps(a, 0, a, _MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC); + let r = _mm_mask_getmant_ps::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(a, 0, a); assert_eq_m128(r, a); - let r = _mm_mask_getmant_ps(a, 0b00001111, a, _MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC); + let r = _mm_mask_getmant_ps::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(a, 0b00001111, a); let e = _mm_set1_ps(1.25); assert_eq_m128(r, e); } @@ -40911,9 +40405,9 @@ mod tests { #[simd_test(enable = "avx512f,avx512vl")] unsafe fn test_mm_maskz_getmant_ps() { let a = _mm_set1_ps(10.); - let r = _mm_maskz_getmant_ps(0, a, _MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC); + let r = _mm_maskz_getmant_ps::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(0, a); assert_eq_m128(r, _mm_setzero_ps()); - let r = _mm_maskz_getmant_ps(0b00001111, a, _MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC); + let r = _mm_maskz_getmant_ps::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(0b00001111, a); let e = _mm_set1_ps(1.25); assert_eq_m128(r, e); } @@ -41913,7 +41407,7 @@ mod tests { #[simd_test(enable = "avx512f")] unsafe fn test_mm512_roundscale_round_ps() { let a = _mm512_set1_ps(1.1); - let r = _mm512_roundscale_round_ps(a, 0, _MM_FROUND_CUR_DIRECTION); + let r = _mm512_roundscale_round_ps::<0, _MM_FROUND_CUR_DIRECTION>(a); let e = _mm512_set1_ps(1.0); assert_eq_m512(r, e); } @@ -41921,11 +41415,14 @@ mod tests { #[simd_test(enable = "avx512f")] unsafe fn test_mm512_mask_roundscale_round_ps() { let a = _mm512_set1_ps(1.1); - let r = _mm512_mask_roundscale_round_ps(a, 0, a, 0, _MM_FROUND_CUR_DIRECTION); + let r = _mm512_mask_roundscale_round_ps::<0, _MM_FROUND_CUR_DIRECTION>(a, 0, a); let e = _mm512_set1_ps(1.1); assert_eq_m512(r, e); - let r = - _mm512_mask_roundscale_round_ps(a, 0b11111111_11111111, a, 0, _MM_FROUND_CUR_DIRECTION); + let r = _mm512_mask_roundscale_round_ps::<0, _MM_FROUND_CUR_DIRECTION>( + a, + 0b11111111_11111111, + a, + ); let e = _mm512_set1_ps(1.0); assert_eq_m512(r, e); } @@ -41933,10 +41430,10 @@ mod tests { #[simd_test(enable = "avx512f")] unsafe fn test_mm512_maskz_roundscale_round_ps() { let a = _mm512_set1_ps(1.1); - let r = _mm512_maskz_roundscale_round_ps(0, a, 0, _MM_FROUND_CUR_DIRECTION); + let r = _mm512_maskz_roundscale_round_ps::<0, _MM_FROUND_CUR_DIRECTION>(0, a); assert_eq_m512(r, _mm512_setzero_ps()); let r = - _mm512_maskz_roundscale_round_ps(0b11111111_11111111, a, 0, _MM_FROUND_CUR_DIRECTION); + _mm512_maskz_roundscale_round_ps::<0, _MM_FROUND_CUR_DIRECTION>(0b11111111_11111111, a); let e = _mm512_set1_ps(1.0); assert_eq_m512(r, e); } @@ -41994,7 +41491,7 @@ mod tests { let a = _mm512_set1_ps(f32::NAN); let b = _mm512_set1_ps(f32::MAX); let c = _mm512_set1_epi32(i32::MAX); - let r = _mm512_fixupimm_round_ps(a, b, c, 5, _MM_FROUND_CUR_DIRECTION); + let r = _mm512_fixupimm_round_ps::<5, _MM_FROUND_CUR_DIRECTION>(a, b, c); let e = _mm512_set1_ps(0.0); assert_eq_m512(r, e); } @@ -42010,13 +41507,11 @@ mod tests { ); let b = _mm512_set1_ps(f32::MAX); let c = _mm512_set1_epi32(i32::MAX); - let r = _mm512_mask_fixupimm_round_ps( + let r = _mm512_mask_fixupimm_round_ps::<5, _MM_FROUND_CUR_DIRECTION>( a, 0b11111111_00000000, b, c, - 5, - _MM_FROUND_CUR_DIRECTION, ); let e = _mm512_set_ps( 0., 0., 0., 0., 0., 0., 0., 0., 1., 1., 1., 1., 1., 1., 1., 1., @@ -42035,13 +41530,11 @@ mod tests { ); let b = _mm512_set1_ps(f32::MAX); let c = _mm512_set1_epi32(i32::MAX); - let r = _mm512_maskz_fixupimm_round_ps( + let r = _mm512_maskz_fixupimm_round_ps::<5, _MM_FROUND_CUR_DIRECTION>( 0b11111111_00000000, a, b, c, - 5, - _MM_FROUND_CUR_DIRECTION, ); let e = _mm512_set_ps( 0., 0., 0., 0., 0., 0., 0., 0., 0., 0., 0., 0., 0., 0., 0., 0., @@ -42052,12 +41545,11 @@ mod tests { #[simd_test(enable = "avx512f")] unsafe fn test_mm512_getmant_round_ps() { let a = _mm512_set1_ps(10.); - let r = _mm512_getmant_round_ps( - a, + let r = _mm512_getmant_round_ps::< _MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC, _MM_FROUND_CUR_DIRECTION, - ); + >(a); let e = _mm512_set1_ps(1.25); assert_eq_m512(r, e); } @@ -42065,23 +41557,17 @@ mod tests { #[simd_test(enable = "avx512f")] unsafe fn test_mm512_mask_getmant_round_ps() { let a = _mm512_set1_ps(10.); - let r = _mm512_mask_getmant_round_ps( - a, - 0, - a, + let r = _mm512_mask_getmant_round_ps::< _MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC, _MM_FROUND_CUR_DIRECTION, - ); + >(a, 0, a); assert_eq_m512(r, a); - let r = _mm512_mask_getmant_round_ps( - a, - 0b11111111_00000000, - a, + let r = _mm512_mask_getmant_round_ps::< _MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC, _MM_FROUND_CUR_DIRECTION, - ); + >(a, 0b11111111_00000000, a); let e = _mm512_setr_ps( 10., 10., 10., 10., 10., 10., 10., 10., 1.25, 1.25, 1.25, 1.25, 1.25, 1.25, 1.25, 1.25, ); @@ -42091,21 +41577,17 @@ mod tests { #[simd_test(enable = "avx512f")] unsafe fn test_mm512_maskz_getmant_round_ps() { let a = _mm512_set1_ps(10.); - let r = _mm512_maskz_getmant_round_ps( - 0, - a, + let r = _mm512_maskz_getmant_round_ps::< _MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC, _MM_FROUND_CUR_DIRECTION, - ); + >(0, a); assert_eq_m512(r, _mm512_setzero_ps()); - let r = _mm512_maskz_getmant_round_ps( - 0b11111111_00000000, - a, + let r = _mm512_maskz_getmant_round_ps::< _MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC, _MM_FROUND_CUR_DIRECTION, - ); + >(0b11111111_00000000, a); let e = _mm512_setr_ps( 0., 0., 0., 0., 0., 0., 0., 0., 1.25, 1.25, 1.25, 1.25, 1.25, 1.25, 1.25, 1.25, ); @@ -44407,7 +43889,7 @@ mod tests { let a = _mm512_set_ps(0., 1., -1., 13., f32::MAX, f32::MIN, 100., -100., 0., 1., -1., 13., f32::MAX, f32::MIN, 100., -100.); let b = _mm512_set1_ps(-1.); - let m = _mm512_cmp_round_ps_mask(a, b, _CMP_LT_OQ, _MM_FROUND_CUR_DIRECTION); + let m = _mm512_cmp_round_ps_mask::<_CMP_LT_OQ, _MM_FROUND_CUR_DIRECTION>(a, b); assert_eq!(m, 0b00000101_00000101); } @@ -44418,7 +43900,7 @@ mod tests { 0., 1., -1., 13., f32::MAX, f32::MIN, 100., -100.); let b = _mm512_set1_ps(-1.); let mask = 0b01100110_01100110; - let r = _mm512_mask_cmp_round_ps_mask(mask, a, b, _CMP_LT_OQ, _MM_FROUND_CUR_DIRECTION); + let r = _mm512_mask_cmp_round_ps_mask::<_CMP_LT_OQ, _MM_FROUND_CUR_DIRECTION>(mask, a, b); assert_eq!(r, 0b00000100_00000100); } @@ -44495,7 +43977,7 @@ mod tests { unsafe fn test_mm_cmp_round_ss_mask() { let a = _mm_setr_ps(2., 1., 1., 1.); let b = _mm_setr_ps(1., 2., 2., 2.); - let m = _mm_cmp_round_ss_mask(a, b, _CMP_GE_OS, _MM_FROUND_CUR_DIRECTION); + let m = _mm_cmp_round_ss_mask::<_CMP_GE_OS, _MM_FROUND_CUR_DIRECTION>(a, b); assert_eq!(m, 1); } @@ -44503,9 +43985,9 @@ mod tests { unsafe fn test_mm_mask_cmp_round_ss_mask() { let a = _mm_setr_ps(2., 1., 1., 1.); let b = _mm_setr_ps(1., 2., 2., 2.); - let m = _mm_mask_cmp_round_ss_mask(0b10, a, b, _CMP_GE_OS, _MM_FROUND_CUR_DIRECTION); + let m = _mm_mask_cmp_round_ss_mask::<_CMP_GE_OS, _MM_FROUND_CUR_DIRECTION>(0b10, a, b); assert_eq!(m, 0); - let m = _mm_mask_cmp_round_ss_mask(0b1, a, b, _CMP_GE_OS, _MM_FROUND_CUR_DIRECTION); + let m = _mm_mask_cmp_round_ss_mask::<_CMP_GE_OS, _MM_FROUND_CUR_DIRECTION>(0b1, a, b); assert_eq!(m, 1); } @@ -44531,7 +44013,7 @@ mod tests { unsafe fn test_mm_cmp_round_sd_mask() { let a = _mm_setr_pd(2., 1.); let b = _mm_setr_pd(1., 2.); - let m = _mm_cmp_round_sd_mask(a, b, _CMP_GE_OS, _MM_FROUND_CUR_DIRECTION); + let m = _mm_cmp_round_sd_mask::<_CMP_GE_OS, _MM_FROUND_CUR_DIRECTION>(a, b); assert_eq!(m, 1); } @@ -44539,9 +44021,9 @@ mod tests { unsafe fn test_mm_mask_cmp_round_sd_mask() { let a = _mm_setr_pd(2., 1.); let b = _mm_setr_pd(1., 2.); - let m = _mm_mask_cmp_round_sd_mask(0b10, a, b, _CMP_GE_OS, _MM_FROUND_CUR_DIRECTION); + let m = _mm_mask_cmp_round_sd_mask::<_CMP_GE_OS, _MM_FROUND_CUR_DIRECTION>(0b10, a, b); assert_eq!(m, 0); - let m = _mm_mask_cmp_round_sd_mask(0b1, a, b, _CMP_GE_OS, _MM_FROUND_CUR_DIRECTION); + let m = _mm_mask_cmp_round_sd_mask::<_CMP_GE_OS, _MM_FROUND_CUR_DIRECTION>(0b1, a, b); assert_eq!(m, 1); } @@ -46602,7 +46084,7 @@ mod tests { let a = _mm512_setr_ps( 0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., ); - let r = _mm512_permute_ps(a, 0b11111111); + let r = _mm512_permute_ps::<0b11_11_11_11>(a); let e = _mm512_setr_ps( 3., 3., 3., 3., 7., 7., 7., 7., 11., 11., 11., 11., 15., 15., 15., 15., ); @@ -46614,9 +46096,9 @@ mod tests { let a = _mm512_setr_ps( 0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., ); - let r = _mm512_mask_permute_ps(a, 0, a, 0b11111111); + let r = _mm512_mask_permute_ps::<0b11_11_11_11>(a, 0, a); assert_eq_m512(r, a); - let r = _mm512_mask_permute_ps(a, 0b11111111_11111111, a, 0b111111111); + let r = _mm512_mask_permute_ps::<0b11_11_11_11>(a, 0b11111111_11111111, a); let e = _mm512_setr_ps( 3., 3., 3., 3., 7., 7., 7., 7., 11., 11., 11., 11., 15., 15., 15., 15., ); @@ -46628,9 +46110,9 @@ mod tests { let a = _mm512_setr_ps( 0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., ); - let r = _mm512_maskz_permute_ps(0, a, 0b11111111); + let r = _mm512_maskz_permute_ps::<0b11_11_11_11>(0, a); assert_eq_m512(r, _mm512_setzero_ps()); - let r = _mm512_maskz_permute_ps(0b11111111_11111111, a, 0b11111111); + let r = _mm512_maskz_permute_ps::<0b11_11_11_11>(0b11111111_11111111, a); let e = _mm512_setr_ps( 3., 3., 3., 3., 7., 7., 7., 7., 11., 11., 11., 11., 15., 15., 15., 15., ); @@ -46640,9 +46122,9 @@ mod tests { #[simd_test(enable = "avx512f,avx512vl")] unsafe fn test_mm256_mask_permute_ps() { let a = _mm256_set_ps(0., 1., 2., 3., 4., 5., 6., 7.); - let r = _mm256_mask_permute_ps(a, 0, a, 0b11111111); + let r = _mm256_mask_permute_ps::<0b11_11_11_11>(a, 0, a); assert_eq_m256(r, a); - let r = _mm256_mask_permute_ps(a, 0b11111111, a, 0b11111111); + let r = _mm256_mask_permute_ps::<0b11_11_11_11>(a, 0b11111111, a); let e = _mm256_set_ps(0., 0., 0., 0., 4., 4., 4., 4.); assert_eq_m256(r, e); } @@ -46650,9 +46132,9 @@ mod tests { #[simd_test(enable = "avx512f,avx512vl")] unsafe fn test_mm256_maskz_permute_ps() { let a = _mm256_set_ps(0., 1., 2., 3., 4., 5., 6., 7.); - let r = _mm256_maskz_permute_ps(0, a, 0b11111111); + let r = _mm256_maskz_permute_ps::<0b11_11_11_11>(0, a); assert_eq_m256(r, _mm256_setzero_ps()); - let r = _mm256_maskz_permute_ps(0b11111111, a, 0b11111111); + let r = _mm256_maskz_permute_ps::<0b11_11_11_11>(0b11111111, a); let e = _mm256_set_ps(0., 0., 0., 0., 4., 4., 4., 4.); assert_eq_m256(r, e); } @@ -46660,9 +46142,9 @@ mod tests { #[simd_test(enable = "avx512f,avx512vl")] unsafe fn test_mm_mask_permute_ps() { let a = _mm_set_ps(0., 1., 2., 3.); - let r = _mm_mask_permute_ps(a, 0, a, 0b11111111); + let r = _mm_mask_permute_ps::<0b11_11_11_11>(a, 0, a); assert_eq_m128(r, a); - let r = _mm_mask_permute_ps(a, 0b00001111, a, 0b11111111); + let r = _mm_mask_permute_ps::<0b11_11_11_11>(a, 0b00001111, a); let e = _mm_set_ps(0., 0., 0., 0.); assert_eq_m128(r, e); } @@ -46670,9 +46152,9 @@ mod tests { #[simd_test(enable = "avx512f,avx512vl")] unsafe fn test_mm_maskz_permute_ps() { let a = _mm_set_ps(0., 1., 2., 3.); - let r = _mm_maskz_permute_ps(0, a, 0b11111111); + let r = _mm_maskz_permute_ps::<0b11_11_11_11>(0, a); assert_eq_m128(r, _mm_setzero_ps()); - let r = _mm_maskz_permute_ps(0b00001111, a, 0b11111111); + let r = _mm_maskz_permute_ps::<0b11_11_11_11>(0b00001111, a); let e = _mm_set_ps(0., 0., 0., 0.); assert_eq_m128(r, e); } @@ -48743,11 +48225,11 @@ mod tests { let b = _mm512_set_epi32( 32, 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, 18, 17, ); - let r = _mm512_alignr_epi32(a, b, 0); + let r = _mm512_alignr_epi32::<0>(a, b); assert_eq_m512i(r, b); - let r = _mm512_alignr_epi32(a, b, 16); + let r = _mm512_alignr_epi32::<16>(a, b); assert_eq_m512i(r, b); - let r = _mm512_alignr_epi32(a, b, 1); + let r = _mm512_alignr_epi32::<1>(a, b); let e = _mm512_set_epi32( 1, 32, 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, 18, ); @@ -48760,9 +48242,9 @@ mod tests { let b = _mm512_set_epi32( 32, 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, 18, 17, ); - let r = _mm512_mask_alignr_epi32(a, 0, a, b, 1); + let r = _mm512_mask_alignr_epi32::<1>(a, 0, a, b); assert_eq_m512i(r, a); - let r = _mm512_mask_alignr_epi32(a, 0b11111111_11111111, a, b, 1); + let r = _mm512_mask_alignr_epi32::<1>(a, 0b11111111_11111111, a, b); let e = _mm512_set_epi32( 1, 32, 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, 18, ); @@ -48775,9 +48257,9 @@ mod tests { let b = _mm512_set_epi32( 32, 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, 18, 17, ); - let r = _mm512_maskz_alignr_epi32(0, a, b, 1); + let r = _mm512_maskz_alignr_epi32::<1>(0, a, b); assert_eq_m512i(r, _mm512_setzero_si512()); - let r = _mm512_maskz_alignr_epi32(0b00000000_11111111, a, b, 1); + let r = _mm512_maskz_alignr_epi32::<1>(0b00000000_11111111, a, b); let e = _mm512_set_epi32(0, 0, 0, 0, 0, 0, 0, 0, 25, 24, 23, 22, 21, 20, 19, 18); assert_eq_m512i(r, e); } @@ -48786,9 +48268,9 @@ mod tests { unsafe fn test_mm256_alignr_epi32() { let a = _mm256_set_epi32(8, 7, 6, 5, 4, 3, 2, 1); let b = _mm256_set_epi32(16, 15, 14, 13, 12, 11, 10, 9); - let r = _mm256_alignr_epi32(a, b, 0); + let r = _mm256_alignr_epi32::<0>(a, b); assert_eq_m256i(r, b); - let r = _mm256_alignr_epi32(a, b, 1); + let r = _mm256_alignr_epi32::<1>(a, b); let e = _mm256_set_epi32(1, 16, 15, 14, 13, 12, 11, 10); assert_eq_m256i(r, e); } @@ -48797,9 +48279,9 @@ mod tests { unsafe fn test_mm256_mask_alignr_epi32() { let a = _mm256_set_epi32(8, 7, 6, 5, 4, 3, 2, 1); let b = _mm256_set_epi32(16, 15, 14, 13, 12, 11, 10, 9); - let r = _mm256_mask_alignr_epi32(a, 0, a, b, 1); + let r = _mm256_mask_alignr_epi32::<1>(a, 0, a, b); assert_eq_m256i(r, a); - let r = _mm256_mask_alignr_epi32(a, 0b11111111, a, b, 1); + let r = _mm256_mask_alignr_epi32::<1>(a, 0b11111111, a, b); let e = _mm256_set_epi32(1, 16, 15, 14, 13, 12, 11, 10); assert_eq_m256i(r, e); } @@ -48808,9 +48290,9 @@ mod tests { unsafe fn test_mm256_maskz_alignr_epi32() { let a = _mm256_set_epi32(8, 7, 6, 5, 4, 3, 2, 1); let b = _mm256_set_epi32(16, 15, 14, 13, 12, 11, 10, 9); - let r = _mm256_maskz_alignr_epi32(0, a, b, 1); + let r = _mm256_maskz_alignr_epi32::<1>(0, a, b); assert_eq_m256i(r, _mm256_setzero_si256()); - let r = _mm256_maskz_alignr_epi32(0b11111111, a, b, 1); + let r = _mm256_maskz_alignr_epi32::<1>(0b11111111, a, b); let e = _mm256_set_epi32(1, 16, 15, 14, 13, 12, 11, 10); assert_eq_m256i(r, e); } @@ -48819,9 +48301,9 @@ mod tests { unsafe fn test_mm_alignr_epi32() { let a = _mm_set_epi32(4, 3, 2, 1); let b = _mm_set_epi32(8, 7, 6, 5); - let r = _mm_alignr_epi32(a, b, 0); + let r = _mm_alignr_epi32::<0>(a, b); assert_eq_m128i(r, b); - let r = _mm_alignr_epi32(a, b, 1); + let r = _mm_alignr_epi32::<1>(a, b); let e = _mm_set_epi32(1, 8, 7, 6); assert_eq_m128i(r, e); } @@ -48830,9 +48312,9 @@ mod tests { unsafe fn test_mm_mask_alignr_epi32() { let a = _mm_set_epi32(4, 3, 2, 1); let b = _mm_set_epi32(8, 7, 6, 5); - let r = _mm_mask_alignr_epi32(a, 0, a, b, 1); + let r = _mm_mask_alignr_epi32::<1>(a, 0, a, b); assert_eq_m128i(r, a); - let r = _mm_mask_alignr_epi32(a, 0b00001111, a, b, 1); + let r = _mm_mask_alignr_epi32::<1>(a, 0b00001111, a, b); let e = _mm_set_epi32(1, 8, 7, 6); assert_eq_m128i(r, e); } @@ -48841,9 +48323,9 @@ mod tests { unsafe fn test_mm_maskz_alignr_epi32() { let a = _mm_set_epi32(4, 3, 2, 1); let b = _mm_set_epi32(8, 7, 6, 5); - let r = _mm_maskz_alignr_epi32(0, a, b, 1); + let r = _mm_maskz_alignr_epi32::<1>(0, a, b); assert_eq_m128i(r, _mm_setzero_si128()); - let r = _mm_maskz_alignr_epi32(0b00001111, a, b, 1); + let r = _mm_maskz_alignr_epi32::<1>(0b00001111, a, b); let e = _mm_set_epi32(1, 8, 7, 6); assert_eq_m128i(r, e); } @@ -51187,7 +50669,7 @@ mod tests { unsafe fn test_mm_getmant_ss() { let a = _mm_set1_ps(20.); let b = _mm_set1_ps(10.); - let r = _mm_getmant_ss(a, b, _MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC); + let r = _mm_getmant_ss::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(a, b); let e = _mm_set_ps(20., 20., 20., 1.25); assert_eq_m128(r, e); } @@ -51196,10 +50678,10 @@ mod tests { unsafe fn test_mm_mask_getmant_ss() { let a = _mm_set1_ps(20.); let b = _mm_set1_ps(10.); - let r = _mm_mask_getmant_ss(a, 0, a, b, _MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC); + let r = _mm_mask_getmant_ss::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(a, 0, a, b); let e = _mm_set_ps(20., 20., 20., 20.); assert_eq_m128(r, e); - let r = _mm_mask_getmant_ss(a, 0b11111111, a, b, _MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC); + let r = _mm_mask_getmant_ss::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(a, 0b11111111, a, b); let e = _mm_set_ps(20., 20., 20., 1.25); assert_eq_m128(r, e); } @@ -51208,10 +50690,10 @@ mod tests { unsafe fn test_mm_maskz_getmant_ss() { let a = _mm_set1_ps(20.); let b = _mm_set1_ps(10.); - let r = _mm_maskz_getmant_ss(0, a, b, _MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC); + let r = _mm_maskz_getmant_ss::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(0, a, b); let e = _mm_set_ps(20., 20., 20., 0.); assert_eq_m128(r, e); - let r = _mm_maskz_getmant_ss(0b11111111, a, b, _MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC); + let r = _mm_maskz_getmant_ss::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(0b11111111, a, b); let e = _mm_set_ps(20., 20., 20., 1.25); assert_eq_m128(r, e); } @@ -51220,7 +50702,7 @@ mod tests { unsafe fn test_mm_getmant_sd() { let a = _mm_set1_pd(20.); let b = _mm_set1_pd(10.); - let r = _mm_getmant_sd(a, b, _MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC); + let r = _mm_getmant_sd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(a, b); let e = _mm_set_pd(20., 1.25); assert_eq_m128d(r, e); } @@ -51229,10 +50711,10 @@ mod tests { unsafe fn test_mm_mask_getmant_sd() { let a = _mm_set1_pd(20.); let b = _mm_set1_pd(10.); - let r = _mm_mask_getmant_sd(a, 0, a, b, _MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC); + let r = _mm_mask_getmant_sd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(a, 0, a, b); let e = _mm_set_pd(20., 20.); assert_eq_m128d(r, e); - let r = _mm_mask_getmant_sd(a, 0b11111111, a, b, _MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC); + let r = _mm_mask_getmant_sd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(a, 0b11111111, a, b); let e = _mm_set_pd(20., 1.25); assert_eq_m128d(r, e); } @@ -51241,10 +50723,10 @@ mod tests { unsafe fn test_mm_maskz_getmant_sd() { let a = _mm_set1_pd(20.); let b = _mm_set1_pd(10.); - let r = _mm_maskz_getmant_sd(0, a, b, _MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC); + let r = _mm_maskz_getmant_sd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(0, a, b); let e = _mm_set_pd(20., 0.); assert_eq_m128d(r, e); - let r = _mm_maskz_getmant_sd(0b11111111, a, b, _MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC); + let r = _mm_maskz_getmant_sd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(0b11111111, a, b); let e = _mm_set_pd(20., 1.25); assert_eq_m128d(r, e); } @@ -52249,13 +51731,10 @@ mod tests { unsafe fn test_mm_getmant_round_ss() { let a = _mm_set1_ps(20.); let b = _mm_set1_ps(10.); - let r = _mm_getmant_round_ss( - a, - b, - _MM_MANT_NORM_1_2, - _MM_MANT_SIGN_SRC, - _MM_FROUND_CUR_DIRECTION, - ); + let r = + _mm_getmant_round_ss::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC, _MM_FROUND_CUR_DIRECTION>( + a, b, + ); let e = _mm_set_ps(20., 20., 20., 1.25); assert_eq_m128(r, e); } @@ -52264,26 +51743,18 @@ mod tests { unsafe fn test_mm_mask_getmant_round_ss() { let a = _mm_set1_ps(20.); let b = _mm_set1_ps(10.); - let r = _mm_mask_getmant_round_ss( - a, - 0, - a, - b, + let r = _mm_mask_getmant_round_ss::< _MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC, _MM_FROUND_CUR_DIRECTION, - ); + >(a, 0, a, b); let e = _mm_set_ps(20., 20., 20., 20.); assert_eq_m128(r, e); - let r = _mm_mask_getmant_round_ss( - a, - 0b11111111, - a, - b, + let r = _mm_mask_getmant_round_ss::< _MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC, _MM_FROUND_CUR_DIRECTION, - ); + >(a, 0b11111111, a, b); let e = _mm_set_ps(20., 20., 20., 1.25); assert_eq_m128(r, e); } @@ -52292,24 +51763,18 @@ mod tests { unsafe fn test_mm_maskz_getmant_round_ss() { let a = _mm_set1_ps(20.); let b = _mm_set1_ps(10.); - let r = _mm_maskz_getmant_round_ss( - 0, - a, - b, + let r = _mm_maskz_getmant_round_ss::< _MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC, _MM_FROUND_CUR_DIRECTION, - ); + >(0, a, b); let e = _mm_set_ps(20., 20., 20., 0.); assert_eq_m128(r, e); - let r = _mm_maskz_getmant_round_ss( - 0b11111111, - a, - b, + let r = _mm_maskz_getmant_round_ss::< _MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC, _MM_FROUND_CUR_DIRECTION, - ); + >(0b11111111, a, b); let e = _mm_set_ps(20., 20., 20., 1.25); assert_eq_m128(r, e); } @@ -52318,13 +51783,10 @@ mod tests { unsafe fn test_mm_getmant_round_sd() { let a = _mm_set1_pd(20.); let b = _mm_set1_pd(10.); - let r = _mm_getmant_round_sd( - a, - b, - _MM_MANT_NORM_1_2, - _MM_MANT_SIGN_SRC, - _MM_FROUND_CUR_DIRECTION, - ); + let r = + _mm_getmant_round_sd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC, _MM_FROUND_CUR_DIRECTION>( + a, b, + ); let e = _mm_set_pd(20., 1.25); assert_eq_m128d(r, e); } @@ -52333,26 +51795,18 @@ mod tests { unsafe fn test_mm_mask_getmant_round_sd() { let a = _mm_set1_pd(20.); let b = _mm_set1_pd(10.); - let r = _mm_mask_getmant_round_sd( - a, - 0, - a, - b, + let r = _mm_mask_getmant_round_sd::< _MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC, _MM_FROUND_CUR_DIRECTION, - ); + >(a, 0, a, b); let e = _mm_set_pd(20., 20.); assert_eq_m128d(r, e); - let r = _mm_mask_getmant_round_sd( - a, - 0b11111111, - a, - b, + let r = _mm_mask_getmant_round_sd::< _MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC, _MM_FROUND_CUR_DIRECTION, - ); + >(a, 0b11111111, a, b); let e = _mm_set_pd(20., 1.25); assert_eq_m128d(r, e); } @@ -52361,24 +51815,18 @@ mod tests { unsafe fn test_mm_maskz_getmant_round_sd() { let a = _mm_set1_pd(20.); let b = _mm_set1_pd(10.); - let r = _mm_maskz_getmant_round_sd( - 0, - a, - b, + let r = _mm_maskz_getmant_round_sd::< _MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC, _MM_FROUND_CUR_DIRECTION, - ); + >(0, a, b); let e = _mm_set_pd(20., 0.); assert_eq_m128d(r, e); - let r = _mm_maskz_getmant_round_sd( - 0b11111111, - a, - b, + let r = _mm_maskz_getmant_round_sd::< _MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC, _MM_FROUND_CUR_DIRECTION, - ); + >(0b11111111, a, b); let e = _mm_set_pd(20., 1.25); assert_eq_m128d(r, e); } @@ -52387,7 +51835,7 @@ mod tests { unsafe fn test_mm_roundscale_round_ss() { let a = _mm_set1_ps(2.2); let b = _mm_set1_ps(1.1); - let r = _mm_roundscale_round_ss(a, b, 0, _MM_FROUND_CUR_DIRECTION); + let r = _mm_roundscale_round_ss::<0, _MM_FROUND_CUR_DIRECTION>(a, b); let e = _mm_set_ps(2.2, 2.2, 2.2, 1.0); assert_eq_m128(r, e); } @@ -52396,10 +51844,10 @@ mod tests { unsafe fn test_mm_mask_roundscale_round_ss() { let a = _mm_set1_ps(2.2); let b = _mm_set1_ps(1.1); - let r = _mm_mask_roundscale_round_ss(a, 0, a, b, 0, _MM_FROUND_CUR_DIRECTION); + let r = _mm_mask_roundscale_round_ss::<0, _MM_FROUND_CUR_DIRECTION>(a, 0, a, b); let e = _mm_set_ps(2.2, 2.2, 2.2, 2.2); assert_eq_m128(r, e); - let r = _mm_mask_roundscale_round_ss(a, 0b11111111, a, b, 0, _MM_FROUND_CUR_DIRECTION); + let r = _mm_mask_roundscale_round_ss::<0, _MM_FROUND_CUR_DIRECTION>(a, 0b11111111, a, b); let e = _mm_set_ps(2.2, 2.2, 2.2, 1.0); assert_eq_m128(r, e); } @@ -52408,10 +51856,10 @@ mod tests { unsafe fn test_mm_maskz_roundscale_round_ss() { let a = _mm_set1_ps(2.2); let b = _mm_set1_ps(1.1); - let r = _mm_maskz_roundscale_round_ss(0, a, b, 0, _MM_FROUND_CUR_DIRECTION); + let r = _mm_maskz_roundscale_round_ss::<0, _MM_FROUND_CUR_DIRECTION>(0, a, b); let e = _mm_set_ps(2.2, 2.2, 2.2, 0.0); assert_eq_m128(r, e); - let r = _mm_maskz_roundscale_round_ss(0b11111111, a, b, 0, _MM_FROUND_CUR_DIRECTION); + let r = _mm_maskz_roundscale_round_ss::<0, _MM_FROUND_CUR_DIRECTION>(0b11111111, a, b); let e = _mm_set_ps(2.2, 2.2, 2.2, 1.0); assert_eq_m128(r, e); } @@ -52420,7 +51868,7 @@ mod tests { unsafe fn test_mm_roundscale_round_sd() { let a = _mm_set1_pd(2.2); let b = _mm_set1_pd(1.1); - let r = _mm_roundscale_round_sd(a, b, 0, _MM_FROUND_CUR_DIRECTION); + let r = _mm_roundscale_round_sd::<0, _MM_FROUND_CUR_DIRECTION>(a, b); let e = _mm_set_pd(2.2, 1.0); assert_eq_m128d(r, e); } @@ -52429,10 +51877,10 @@ mod tests { unsafe fn test_mm_mask_roundscale_round_sd() { let a = _mm_set1_pd(2.2); let b = _mm_set1_pd(1.1); - let r = _mm_mask_roundscale_round_sd(a, 0, a, b, 0, _MM_FROUND_CUR_DIRECTION); + let r = _mm_mask_roundscale_round_sd::<0, _MM_FROUND_CUR_DIRECTION>(a, 0, a, b); let e = _mm_set_pd(2.2, 2.2); assert_eq_m128d(r, e); - let r = _mm_mask_roundscale_round_sd(a, 0b11111111, a, b, 0, _MM_FROUND_CUR_DIRECTION); + let r = _mm_mask_roundscale_round_sd::<0, _MM_FROUND_CUR_DIRECTION>(a, 0b11111111, a, b); let e = _mm_set_pd(2.2, 1.0); assert_eq_m128d(r, e); } @@ -52441,10 +51889,10 @@ mod tests { unsafe fn test_mm_maskz_roundscale_round_sd() { let a = _mm_set1_pd(2.2); let b = _mm_set1_pd(1.1); - let r = _mm_maskz_roundscale_round_sd(0, a, b, 0, _MM_FROUND_CUR_DIRECTION); + let r = _mm_maskz_roundscale_round_sd::<0, _MM_FROUND_CUR_DIRECTION>(0, a, b); let e = _mm_set_pd(2.2, 0.0); assert_eq_m128d(r, e); - let r = _mm_maskz_roundscale_round_sd(0b11111111, a, b, 0, _MM_FROUND_CUR_DIRECTION); + let r = _mm_maskz_roundscale_round_sd::<0, _MM_FROUND_CUR_DIRECTION>(0b11111111, a, b); let e = _mm_set_pd(2.2, 1.0); assert_eq_m128d(r, e); } @@ -53069,11 +52517,11 @@ mod tests { #[simd_test(enable = "avx512f")] unsafe fn test_mm_fixupimm_round_ss() { - let a = _mm_set_ps(0., 0., 0., f32::NAN); + let a = _mm_set_ps(1., 0., 0., f32::NAN); let b = _mm_set1_ps(f32::MAX); let c = _mm_set1_epi32(i32::MAX); - let r = _mm_fixupimm_round_ss(a, b, c, 5, _MM_FROUND_CUR_DIRECTION); - let e = _mm_set_ps(0., 0., 0., -0.0); + let r = _mm_fixupimm_round_ss::<5, _MM_FROUND_CUR_DIRECTION>(a, b, c); + let e = _mm_set_ps(1., 0., 0., -0.0); assert_eq_m128(r, e); } @@ -53082,7 +52530,7 @@ mod tests { let a = _mm_set_ps(0., 0., 0., f32::NAN); let b = _mm_set1_ps(f32::MAX); let c = _mm_set1_epi32(i32::MAX); - let r = _mm_mask_fixupimm_round_ss(a, 0b11111111, b, c, 5, _MM_FROUND_CUR_DIRECTION); + let r = _mm_mask_fixupimm_round_ss::<5, _MM_FROUND_CUR_DIRECTION>(a, 0b11111111, b, c); let e = _mm_set_ps(0., 0., 0., -0.0); assert_eq_m128(r, e); } @@ -53092,10 +52540,10 @@ mod tests { let a = _mm_set_ps(0., 0., 0., f32::NAN); let b = _mm_set1_ps(f32::MAX); let c = _mm_set1_epi32(i32::MAX); - let r = _mm_maskz_fixupimm_round_ss(0b00000000, a, b, c, 5, _MM_FROUND_CUR_DIRECTION); + let r = _mm_maskz_fixupimm_round_ss::<5, _MM_FROUND_CUR_DIRECTION>(0b00000000, a, b, c); let e = _mm_set_ps(0., 0., 0., 0.0); assert_eq_m128(r, e); - let r = _mm_maskz_fixupimm_round_ss(0b11111111, a, b, c, 5, _MM_FROUND_CUR_DIRECTION); + let r = _mm_maskz_fixupimm_round_ss::<5, _MM_FROUND_CUR_DIRECTION>(0b11111111, a, b, c); let e = _mm_set_ps(0., 0., 0., -0.0); assert_eq_m128(r, e); } @@ -53105,7 +52553,7 @@ mod tests { let a = _mm_set_pd(0., f64::NAN); let b = _mm_set1_pd(f64::MAX); let c = _mm_set1_epi64x(i32::MAX as i64); - let r = _mm_fixupimm_round_sd(a, b, c, 5, _MM_FROUND_CUR_DIRECTION); + let r = _mm_fixupimm_round_sd::<5, _MM_FROUND_CUR_DIRECTION>(a, b, c); let e = _mm_set_pd(0., -0.0); assert_eq_m128d(r, e); } @@ -53115,7 +52563,7 @@ mod tests { let a = _mm_set_pd(0., f64::NAN); let b = _mm_set1_pd(f64::MAX); let c = _mm_set1_epi64x(i32::MAX as i64); - let r = _mm_mask_fixupimm_round_sd(a, 0b11111111, b, c, 5, _MM_FROUND_CUR_DIRECTION); + let r = _mm_mask_fixupimm_round_sd::<5, _MM_FROUND_CUR_DIRECTION>(a, 0b11111111, b, c); let e = _mm_set_pd(0., -0.0); assert_eq_m128d(r, e); } @@ -53125,10 +52573,10 @@ mod tests { let a = _mm_set_pd(0., f64::NAN); let b = _mm_set1_pd(f64::MAX); let c = _mm_set1_epi64x(i32::MAX as i64); - let r = _mm_maskz_fixupimm_round_sd(0b00000000, a, b, c, 5, _MM_FROUND_CUR_DIRECTION); + let r = _mm_maskz_fixupimm_round_sd::<5, _MM_FROUND_CUR_DIRECTION>(0b00000000, a, b, c); let e = _mm_set_pd(0., 0.0); assert_eq_m128d(r, e); - let r = _mm_maskz_fixupimm_round_sd(0b11111111, a, b, c, 5, _MM_FROUND_CUR_DIRECTION); + let r = _mm_maskz_fixupimm_round_sd::<5, _MM_FROUND_CUR_DIRECTION>(0b11111111, a, b, c); let e = _mm_set_pd(0., -0.0); assert_eq_m128d(r, e); } @@ -53474,7 +52922,7 @@ mod tests { unsafe fn test_mm_comi_round_ss() { let a = _mm_set1_ps(2.2); let b = _mm_set1_ps(1.1); - let r = _mm_comi_round_ss(a, b, 0, _MM_FROUND_CUR_DIRECTION); + let r = _mm_comi_round_ss::<0, _MM_FROUND_CUR_DIRECTION>(a, b); let e: i32 = 0; assert_eq!(r, e); } @@ -53483,7 +52931,7 @@ mod tests { unsafe fn test_mm_comi_round_sd() { let a = _mm_set1_pd(2.2); let b = _mm_set1_pd(1.1); - let r = _mm_comi_round_sd(a, b, 0, _MM_FROUND_CUR_DIRECTION); + let r = _mm_comi_round_sd::<0, _MM_FROUND_CUR_DIRECTION>(a, b); let e: i32 = 0; assert_eq!(r, e); } diff --git a/library/stdarch/crates/core_arch/src/x86/macros.rs b/library/stdarch/crates/core_arch/src/x86/macros.rs index 73c6ab0ecdce..e7d8fdd60fc5 100644 --- a/library/stdarch/crates/core_arch/src/x86/macros.rs +++ b/library/stdarch/crates/core_arch/src/x86/macros.rs @@ -32,6 +32,22 @@ macro_rules! static_assert_sae { }; } +// Helper struct used to trigger const eval errors when the const generic immediate value `imm` is +// not a mantissas sae number. +pub(crate) struct ValidateConstMantissasSae; +impl ValidateConstMantissasSae { + pub(crate) const VALID: () = { + let _ = 1 / ((IMM == 4 || IMM == 8 || IMM == 12) as usize); + }; +} + +#[allow(unused)] +macro_rules! static_assert_mantissas_sae { + ($imm:ident) => { + let _ = $crate::core_arch::x86::macros::ValidateConstMantissasSae::<$imm>::VALID; + }; +} + // Helper struct used to trigger const eval errors when the unsigned const generic immediate value // `IMM` is out of `[MIN-MAX]` range. pub(crate) struct ValidateConstImmU32; @@ -81,114 +97,6 @@ macro_rules! constify_imm3 { }; } -// Constifies 5 bits along with an sae option without rounding control. -// See: https://github.com/llvm/llvm-project/blob/bd50cf905fa7c0c7caa134301c6ca0658c81eeb1/clang/lib/Sema/SemaChecking.cpp#L3497 -#[allow(unused)] -macro_rules! constify_imm5_sae { - ($imm5:expr, $imm4:expr, $expand:ident) => { - #[allow(overflowing_literals)] - match ($imm5 & 0b1111_1, $imm4 & 0b1111) { - (0, 4) => $expand!(0, 4), - (0, 8) => $expand!(0, 8), - (0, 12) => $expand!(0, 12), - (1, 4) => $expand!(1, 4), - (1, 8) => $expand!(1, 8), - (1, 12) => $expand!(1, 12), - (2, 4) => $expand!(2, 4), - (2, 8) => $expand!(2, 8), - (2, 12) => $expand!(2, 12), - (3, 4) => $expand!(3, 4), - (3, 8) => $expand!(3, 8), - (3, 12) => $expand!(3, 12), - (4, 4) => $expand!(4, 4), - (4, 8) => $expand!(4, 8), - (4, 12) => $expand!(4, 12), - (5, 4) => $expand!(5, 4), - (5, 8) => $expand!(5, 8), - (5, 12) => $expand!(5, 12), - (6, 4) => $expand!(6, 4), - (6, 8) => $expand!(6, 8), - (6, 12) => $expand!(6, 12), - (7, 4) => $expand!(7, 4), - (7, 8) => $expand!(7, 8), - (7, 12) => $expand!(7, 12), - (8, 4) => $expand!(8, 4), - (8, 8) => $expand!(8, 8), - (8, 12) => $expand!(8, 12), - (9, 4) => $expand!(9, 4), - (9, 8) => $expand!(9, 8), - (9, 12) => $expand!(9, 12), - (10, 4) => $expand!(10, 4), - (10, 8) => $expand!(10, 8), - (10, 12) => $expand!(10, 12), - (11, 4) => $expand!(11, 4), - (11, 8) => $expand!(11, 8), - (11, 12) => $expand!(11, 12), - (12, 4) => $expand!(12, 4), - (12, 8) => $expand!(12, 8), - (12, 12) => $expand!(12, 12), - (13, 4) => $expand!(13, 4), - (13, 8) => $expand!(13, 8), - (13, 12) => $expand!(13, 12), - (14, 4) => $expand!(14, 4), - (14, 8) => $expand!(14, 8), - (14, 12) => $expand!(14, 12), - (15, 4) => $expand!(15, 4), - (15, 8) => $expand!(15, 8), - (15, 12) => $expand!(15, 12), - (16, 4) => $expand!(16, 4), - (16, 8) => $expand!(16, 8), - (16, 12) => $expand!(16, 12), - (17, 4) => $expand!(17, 4), - (17, 8) => $expand!(17, 8), - (17, 12) => $expand!(17, 12), - (18, 4) => $expand!(18, 4), - (18, 8) => $expand!(18, 8), - (18, 12) => $expand!(18, 12), - (19, 4) => $expand!(19, 4), - (19, 8) => $expand!(19, 8), - (19, 12) => $expand!(19, 12), - (20, 4) => $expand!(20, 4), - (20, 8) => $expand!(20, 8), - (20, 12) => $expand!(20, 12), - (21, 4) => $expand!(21, 4), - (21, 8) => $expand!(21, 8), - (21, 12) => $expand!(21, 12), - (22, 4) => $expand!(22, 4), - (22, 8) => $expand!(22, 8), - (22, 12) => $expand!(22, 12), - (23, 4) => $expand!(23, 4), - (23, 8) => $expand!(23, 8), - (23, 12) => $expand!(23, 12), - (24, 4) => $expand!(24, 4), - (24, 8) => $expand!(24, 8), - (24, 12) => $expand!(24, 12), - (25, 4) => $expand!(25, 4), - (25, 8) => $expand!(25, 8), - (25, 12) => $expand!(25, 12), - (26, 4) => $expand!(26, 4), - (26, 8) => $expand!(26, 8), - (26, 12) => $expand!(26, 12), - (27, 4) => $expand!(27, 4), - (27, 8) => $expand!(27, 8), - (27, 12) => $expand!(27, 12), - (28, 4) => $expand!(28, 4), - (28, 8) => $expand!(28, 8), - (28, 12) => $expand!(28, 12), - (29, 4) => $expand!(29, 4), - (29, 8) => $expand!(29, 8), - (29, 12) => $expand!(29, 12), - (30, 4) => $expand!(30, 4), - (30, 8) => $expand!(30, 8), - (30, 12) => $expand!(30, 12), - (31, 4) => $expand!(31, 4), - (31, 8) => $expand!(31, 8), - (31, 12) => $expand!(31, 12), - (_, _) => panic!("Invalid sae value"), - } - }; -} - // For gather instructions, the only valid values for scale are 1, 2, 4 and 8. // This macro enforces that. #[allow(unused)] @@ -205,287 +113,6 @@ macro_rules! constify_imm8_gather { }; } -// Two mantissas parameters. -// This macro enforces that. -#[allow(unused)] -macro_rules! constify_imm4_mantissas { - ($imm4:expr, $imm2:expr, $expand:ident) => { - #[allow(overflowing_literals)] - match ($imm4, $imm2) { - (0, 0) => $expand!(0, 0), - (0, 1) => $expand!(0, 1), - (0, 2) => $expand!(0, 2), - (0, 3) => $expand!(0, 3), - (1, 0) => $expand!(1, 0), - (1, 1) => $expand!(1, 1), - (1, 2) => $expand!(1, 2), - (1, 3) => $expand!(1, 3), - (2, 0) => $expand!(2, 0), - (2, 1) => $expand!(2, 1), - (2, 2) => $expand!(2, 2), - (2, 3) => $expand!(2, 3), - (3, 0) => $expand!(3, 0), - (3, 1) => $expand!(3, 1), - (3, 2) => $expand!(3, 2), - (3, 3) => $expand!(3, 3), - (4, 0) => $expand!(4, 0), - (4, 1) => $expand!(4, 1), - (4, 2) => $expand!(4, 2), - (4, 3) => $expand!(4, 3), - (5, 0) => $expand!(5, 0), - (5, 1) => $expand!(5, 1), - (5, 2) => $expand!(5, 2), - (5, 3) => $expand!(5, 3), - (6, 0) => $expand!(6, 0), - (6, 1) => $expand!(6, 1), - (6, 2) => $expand!(6, 2), - (6, 3) => $expand!(6, 3), - (7, 0) => $expand!(7, 0), - (7, 1) => $expand!(7, 1), - (7, 2) => $expand!(7, 2), - (7, 3) => $expand!(7, 3), - (8, 0) => $expand!(8, 0), - (8, 1) => $expand!(8, 1), - (8, 2) => $expand!(8, 2), - (8, 3) => $expand!(8, 3), - (9, 0) => $expand!(9, 0), - (9, 1) => $expand!(9, 1), - (9, 2) => $expand!(9, 2), - (9, 3) => $expand!(9, 3), - (10, 0) => $expand!(10, 0), - (10, 1) => $expand!(10, 1), - (10, 2) => $expand!(10, 2), - (10, 3) => $expand!(10, 3), - (11, 0) => $expand!(11, 0), - (11, 1) => $expand!(11, 1), - (11, 2) => $expand!(11, 2), - (11, 3) => $expand!(11, 3), - (12, 0) => $expand!(12, 0), - (12, 1) => $expand!(12, 1), - (12, 2) => $expand!(12, 2), - (12, 3) => $expand!(12, 3), - (13, 0) => $expand!(13, 0), - (13, 1) => $expand!(13, 1), - (13, 2) => $expand!(13, 2), - (13, 3) => $expand!(13, 3), - (14, 0) => $expand!(14, 0), - (14, 1) => $expand!(14, 1), - (14, 2) => $expand!(14, 2), - (14, 3) => $expand!(14, 3), - (15, 0) => $expand!(15, 0), - (15, 1) => $expand!(15, 1), - (15, 2) => $expand!(15, 2), - (15, 3) => $expand!(15, 3), - (_, _) => panic!("Invalid sae value"), - } - }; -} - -// Include mantissas parameters. -// For sae instructions, the only valid values for sae are 4 and 8. -// This macro enforces that. -#[allow(unused)] -macro_rules! constify_imm4_mantissas_sae { - ($imm4_1:expr, $imm2:expr, $imm4_2:expr, $expand:ident) => { - #[allow(overflowing_literals)] - match ($imm4_1, $imm2, $imm4_2) { - (0, 0, 4) => $expand!(0, 0, 4), - (0, 0, 8) => $expand!(0, 0, 8), - (0, 0, 12) => $expand!(0, 0, 12), - (0, 1, 4) => $expand!(0, 1, 4), - (0, 1, 8) => $expand!(0, 1, 8), - (0, 1, 12) => $expand!(0, 1, 12), - (0, 2, 4) => $expand!(0, 2, 4), - (0, 2, 8) => $expand!(0, 2, 8), - (0, 2, 12) => $expand!(0, 2, 12), - (0, 3, 4) => $expand!(0, 3, 4), - (0, 3, 8) => $expand!(0, 3, 8), - (0, 3, 12) => $expand!(0, 3, 12), - (1, 0, 4) => $expand!(1, 0, 4), - (1, 0, 8) => $expand!(1, 0, 8), - (1, 0, 12) => $expand!(1, 0, 12), - (1, 1, 4) => $expand!(1, 1, 4), - (1, 1, 8) => $expand!(1, 1, 8), - (1, 1, 12) => $expand!(1, 1, 12), - (1, 2, 4) => $expand!(1, 2, 4), - (1, 2, 8) => $expand!(1, 2, 8), - (1, 2, 12) => $expand!(1, 2, 12), - (1, 3, 4) => $expand!(1, 3, 4), - (1, 3, 8) => $expand!(1, 3, 8), - (1, 3, 12) => $expand!(1, 3, 12), - (2, 0, 4) => $expand!(2, 0, 4), - (2, 0, 8) => $expand!(2, 0, 8), - (2, 0, 12) => $expand!(2, 0, 12), - (2, 1, 4) => $expand!(2, 1, 4), - (2, 1, 8) => $expand!(2, 1, 8), - (2, 1, 12) => $expand!(2, 1, 12), - (2, 2, 4) => $expand!(2, 2, 4), - (2, 2, 8) => $expand!(2, 2, 8), - (2, 2, 12) => $expand!(2, 2, 12), - (2, 3, 4) => $expand!(2, 3, 4), - (2, 3, 8) => $expand!(2, 3, 8), - (2, 3, 12) => $expand!(2, 3, 12), - (3, 0, 4) => $expand!(3, 0, 4), - (3, 0, 8) => $expand!(3, 0, 8), - (3, 0, 12) => $expand!(3, 0, 12), - (3, 1, 4) => $expand!(3, 1, 4), - (3, 1, 8) => $expand!(3, 1, 8), - (3, 1, 12) => $expand!(3, 1, 12), - (3, 2, 4) => $expand!(3, 2, 4), - (3, 2, 8) => $expand!(3, 2, 8), - (3, 2, 12) => $expand!(3, 2, 12), - (3, 3, 4) => $expand!(3, 3, 4), - (3, 3, 8) => $expand!(3, 3, 8), - (3, 3, 12) => $expand!(3, 3, 12), - (4, 0, 4) => $expand!(4, 0, 4), - (4, 0, 8) => $expand!(4, 0, 8), - (4, 0, 12) => $expand!(4, 0, 12), - (4, 1, 4) => $expand!(4, 1, 4), - (4, 1, 8) => $expand!(4, 1, 8), - (4, 1, 12) => $expand!(4, 1, 12), - (4, 2, 4) => $expand!(4, 2, 4), - (4, 2, 8) => $expand!(4, 2, 8), - (4, 2, 12) => $expand!(4, 2, 12), - (4, 3, 4) => $expand!(4, 3, 4), - (4, 3, 8) => $expand!(4, 3, 8), - (4, 3, 12) => $expand!(4, 3, 12), - (5, 0, 4) => $expand!(5, 0, 4), - (5, 0, 8) => $expand!(5, 0, 8), - (5, 0, 12) => $expand!(5, 0, 12), - (5, 1, 4) => $expand!(5, 1, 4), - (5, 1, 8) => $expand!(5, 1, 8), - (5, 1, 12) => $expand!(5, 1, 12), - (5, 2, 4) => $expand!(5, 2, 4), - (5, 2, 8) => $expand!(5, 2, 8), - (5, 2, 12) => $expand!(5, 2, 12), - (5, 3, 4) => $expand!(5, 3, 4), - (5, 3, 8) => $expand!(5, 3, 8), - (5, 3, 12) => $expand!(5, 3, 12), - (6, 0, 4) => $expand!(6, 0, 4), - (6, 0, 8) => $expand!(6, 0, 8), - (6, 0, 12) => $expand!(6, 0, 12), - (6, 1, 4) => $expand!(6, 1, 4), - (6, 1, 8) => $expand!(6, 1, 8), - (6, 1, 12) => $expand!(6, 1, 12), - (6, 2, 4) => $expand!(6, 2, 4), - (6, 2, 8) => $expand!(6, 2, 8), - (6, 2, 12) => $expand!(6, 2, 12), - (6, 3, 4) => $expand!(6, 3, 4), - (6, 3, 8) => $expand!(6, 3, 8), - (6, 3, 12) => $expand!(6, 3, 12), - (7, 0, 4) => $expand!(7, 0, 4), - (7, 0, 8) => $expand!(7, 0, 8), - (7, 0, 12) => $expand!(7, 0, 12), - (7, 1, 4) => $expand!(7, 1, 4), - (7, 1, 8) => $expand!(7, 1, 8), - (7, 1, 12) => $expand!(7, 1, 12), - (7, 2, 4) => $expand!(7, 2, 4), - (7, 2, 8) => $expand!(7, 2, 8), - (7, 2, 12) => $expand!(7, 2, 12), - (7, 3, 4) => $expand!(7, 3, 4), - (7, 3, 8) => $expand!(7, 3, 8), - (7, 3, 12) => $expand!(7, 3, 12), - (8, 0, 4) => $expand!(8, 0, 4), - (8, 0, 8) => $expand!(8, 0, 8), - (8, 0, 12) => $expand!(8, 0, 12), - (8, 1, 4) => $expand!(8, 1, 4), - (8, 1, 8) => $expand!(8, 1, 8), - (8, 1, 12) => $expand!(8, 1, 12), - (8, 2, 4) => $expand!(8, 2, 4), - (8, 2, 8) => $expand!(8, 2, 8), - (8, 2, 12) => $expand!(8, 2, 12), - (8, 3, 4) => $expand!(8, 3, 4), - (8, 3, 8) => $expand!(8, 3, 8), - (8, 3, 12) => $expand!(8, 3, 12), - (9, 0, 4) => $expand!(9, 0, 4), - (9, 0, 8) => $expand!(9, 0, 8), - (9, 0, 12) => $expand!(9, 0, 12), - (9, 1, 4) => $expand!(9, 1, 4), - (9, 1, 8) => $expand!(9, 1, 8), - (9, 1, 12) => $expand!(9, 1, 12), - (9, 2, 4) => $expand!(9, 2, 4), - (9, 2, 8) => $expand!(9, 2, 8), - (9, 2, 12) => $expand!(9, 2, 12), - (9, 3, 4) => $expand!(9, 3, 4), - (9, 3, 8) => $expand!(9, 3, 8), - (9, 3, 12) => $expand!(9, 3, 12), - (10, 0, 4) => $expand!(10, 0, 4), - (10, 0, 8) => $expand!(10, 0, 8), - (10, 0, 12) => $expand!(10, 0, 12), - (10, 1, 4) => $expand!(10, 1, 4), - (10, 1, 8) => $expand!(10, 1, 8), - (10, 1, 12) => $expand!(10, 1, 12), - (10, 2, 4) => $expand!(10, 2, 4), - (10, 2, 8) => $expand!(10, 2, 8), - (10, 2, 12) => $expand!(10, 2, 12), - (10, 3, 4) => $expand!(10, 3, 4), - (10, 3, 8) => $expand!(10, 3, 8), - (10, 3, 12) => $expand!(10, 3, 12), - (11, 0, 4) => $expand!(11, 0, 4), - (11, 0, 8) => $expand!(11, 0, 8), - (11, 0, 12) => $expand!(11, 0, 12), - (11, 1, 4) => $expand!(11, 1, 4), - (11, 1, 8) => $expand!(11, 1, 8), - (11, 1, 12) => $expand!(11, 1, 12), - (11, 2, 4) => $expand!(11, 2, 4), - (11, 2, 8) => $expand!(11, 2, 8), - (11, 2, 12) => $expand!(11, 2, 12), - (11, 3, 4) => $expand!(11, 3, 4), - (11, 3, 8) => $expand!(11, 3, 8), - (11, 3, 12) => $expand!(11, 3, 12), - (12, 0, 4) => $expand!(12, 0, 4), - (12, 0, 8) => $expand!(12, 0, 8), - (12, 0, 12) => $expand!(12, 0, 12), - (12, 1, 4) => $expand!(12, 1, 4), - (12, 1, 8) => $expand!(12, 1, 8), - (12, 1, 12) => $expand!(12, 1, 12), - (12, 2, 4) => $expand!(12, 2, 4), - (12, 2, 8) => $expand!(12, 2, 8), - (12, 2, 12) => $expand!(12, 2, 12), - (12, 3, 4) => $expand!(12, 3, 4), - (12, 3, 8) => $expand!(12, 3, 8), - (12, 3, 12) => $expand!(12, 3, 12), - (13, 0, 4) => $expand!(13, 0, 4), - (13, 0, 8) => $expand!(13, 0, 8), - (13, 0, 12) => $expand!(13, 0, 12), - (13, 1, 4) => $expand!(13, 1, 4), - (13, 1, 8) => $expand!(13, 1, 8), - (13, 1, 12) => $expand!(13, 1, 12), - (13, 2, 4) => $expand!(13, 2, 4), - (13, 2, 8) => $expand!(13, 2, 8), - (13, 2, 12) => $expand!(13, 2, 12), - (13, 3, 4) => $expand!(13, 3, 4), - (13, 3, 8) => $expand!(13, 3, 8), - (13, 3, 12) => $expand!(13, 3, 12), - (14, 0, 4) => $expand!(14, 0, 4), - (14, 0, 8) => $expand!(14, 0, 8), - (14, 0, 12) => $expand!(14, 0, 12), - (14, 1, 4) => $expand!(14, 1, 4), - (14, 1, 8) => $expand!(14, 1, 8), - (14, 1, 12) => $expand!(14, 1, 12), - (14, 2, 4) => $expand!(14, 2, 4), - (14, 2, 8) => $expand!(14, 2, 8), - (14, 2, 12) => $expand!(14, 2, 12), - (14, 3, 4) => $expand!(14, 3, 4), - (14, 3, 8) => $expand!(14, 3, 8), - (14, 3, 12) => $expand!(14, 3, 12), - (15, 0, 4) => $expand!(15, 0, 4), - (15, 0, 8) => $expand!(15, 0, 8), - (15, 0, 12) => $expand!(15, 0, 12), - (15, 1, 4) => $expand!(15, 1, 4), - (15, 1, 8) => $expand!(15, 1, 8), - (15, 1, 12) => $expand!(15, 1, 12), - (15, 2, 4) => $expand!(15, 2, 4), - (15, 2, 8) => $expand!(15, 2, 8), - (15, 2, 12) => $expand!(15, 2, 12), - (15, 3, 4) => $expand!(15, 3, 4), - (15, 3, 8) => $expand!(15, 3, 8), - (15, 3, 12) => $expand!(15, 3, 12), - (_, _, _) => panic!("Invalid sae value"), - } - }; -} - // Constifies 8 bits along with an sae option without rounding control. // The only valid values are 0 to 255. // This macro enforces that. @@ -755,786 +382,6 @@ macro_rules! constify_imm8_sae { }; } -// Two sae parameters. -// This macro enforces that. -#[allow(unused)] -macro_rules! constify_imm8_roundscale { - ($imm8:expr, $imm4:expr, $expand:ident) => { - #[allow(overflowing_literals)] - match ($imm8 & 0b11111111, $imm4) { - (0, 4) => $expand!(0, 4), - (0, 8) => $expand!(0, 8), - (0, 12) => $expand!(0, 12), - (1, 4) => $expand!(1, 4), - (1, 8) => $expand!(1, 8), - (1, 12) => $expand!(1, 12), - (2, 4) => $expand!(2, 4), - (2, 8) => $expand!(2, 8), - (2, 12) => $expand!(2, 12), - (3, 4) => $expand!(3, 4), - (3, 8) => $expand!(3, 8), - (3, 12) => $expand!(3, 12), - (4, 4) => $expand!(4, 4), - (4, 8) => $expand!(4, 8), - (4, 12) => $expand!(4, 12), - (5, 4) => $expand!(5, 4), - (5, 8) => $expand!(5, 8), - (5, 12) => $expand!(5, 12), - (6, 4) => $expand!(6, 4), - (6, 8) => $expand!(6, 8), - (6, 12) => $expand!(6, 12), - (7, 4) => $expand!(7, 4), - (7, 8) => $expand!(7, 8), - (7, 12) => $expand!(7, 12), - (8, 4) => $expand!(8, 4), - (8, 8) => $expand!(8, 8), - (8, 12) => $expand!(8, 12), - (9, 4) => $expand!(9, 4), - (9, 8) => $expand!(9, 8), - (9, 12) => $expand!(9, 12), - (10, 4) => $expand!(10, 4), - (10, 8) => $expand!(10, 8), - (10, 12) => $expand!(10, 12), - (11, 4) => $expand!(11, 4), - (11, 8) => $expand!(11, 8), - (11, 12) => $expand!(11, 12), - (12, 4) => $expand!(12, 4), - (12, 8) => $expand!(12, 8), - (12, 12) => $expand!(12, 12), - (13, 4) => $expand!(13, 4), - (13, 8) => $expand!(13, 8), - (13, 12) => $expand!(13, 12), - (14, 4) => $expand!(14, 4), - (14, 8) => $expand!(14, 8), - (14, 12) => $expand!(14, 12), - (15, 4) => $expand!(15, 4), - (15, 8) => $expand!(15, 8), - (15, 12) => $expand!(15, 12), - (16, 4) => $expand!(16, 4), - (16, 8) => $expand!(16, 8), - (16, 12) => $expand!(16, 12), - (17, 4) => $expand!(17, 4), - (17, 8) => $expand!(17, 8), - (17, 12) => $expand!(17, 12), - (18, 4) => $expand!(18, 4), - (18, 8) => $expand!(18, 8), - (18, 12) => $expand!(18, 12), - (19, 4) => $expand!(19, 4), - (19, 8) => $expand!(19, 8), - (19, 12) => $expand!(19, 12), - (20, 4) => $expand!(20, 4), - (20, 8) => $expand!(20, 8), - (20, 12) => $expand!(20, 12), - (21, 4) => $expand!(21, 4), - (21, 8) => $expand!(21, 8), - (21, 12) => $expand!(21, 12), - (22, 4) => $expand!(22, 4), - (22, 8) => $expand!(22, 8), - (22, 12) => $expand!(22, 12), - (23, 4) => $expand!(23, 4), - (23, 8) => $expand!(23, 8), - (23, 12) => $expand!(23, 12), - (24, 4) => $expand!(24, 4), - (24, 8) => $expand!(24, 8), - (24, 12) => $expand!(24, 12), - (25, 4) => $expand!(25, 4), - (25, 8) => $expand!(25, 8), - (25, 12) => $expand!(25, 12), - (26, 4) => $expand!(26, 4), - (26, 8) => $expand!(26, 8), - (26, 12) => $expand!(26, 12), - (27, 4) => $expand!(27, 4), - (27, 8) => $expand!(27, 8), - (27, 12) => $expand!(27, 12), - (28, 4) => $expand!(28, 4), - (28, 8) => $expand!(28, 8), - (28, 12) => $expand!(28, 12), - (29, 4) => $expand!(29, 4), - (29, 8) => $expand!(29, 8), - (29, 12) => $expand!(29, 12), - (30, 4) => $expand!(30, 4), - (30, 8) => $expand!(30, 8), - (30, 12) => $expand!(30, 12), - (31, 4) => $expand!(31, 4), - (31, 8) => $expand!(31, 8), - (31, 12) => $expand!(31, 12), - (32, 4) => $expand!(32, 4), - (32, 8) => $expand!(32, 8), - (32, 12) => $expand!(32, 12), - (33, 4) => $expand!(33, 4), - (33, 8) => $expand!(33, 8), - (33, 12) => $expand!(33, 12), - (34, 4) => $expand!(34, 4), - (34, 8) => $expand!(34, 8), - (34, 12) => $expand!(34, 12), - (35, 4) => $expand!(35, 4), - (35, 8) => $expand!(35, 8), - (35, 12) => $expand!(35, 12), - (36, 4) => $expand!(36, 4), - (36, 8) => $expand!(36, 8), - (36, 12) => $expand!(36, 12), - (37, 4) => $expand!(37, 4), - (37, 8) => $expand!(37, 8), - (37, 12) => $expand!(37, 12), - (38, 4) => $expand!(38, 4), - (38, 8) => $expand!(38, 8), - (38, 12) => $expand!(38, 12), - (39, 4) => $expand!(39, 4), - (39, 8) => $expand!(39, 8), - (39, 12) => $expand!(39, 12), - (40, 4) => $expand!(40, 4), - (40, 8) => $expand!(40, 8), - (40, 12) => $expand!(40, 12), - (41, 4) => $expand!(41, 4), - (41, 8) => $expand!(41, 8), - (41, 12) => $expand!(41, 12), - (42, 4) => $expand!(42, 4), - (42, 8) => $expand!(42, 8), - (42, 12) => $expand!(42, 12), - (43, 4) => $expand!(43, 4), - (43, 8) => $expand!(43, 8), - (43, 12) => $expand!(43, 12), - (44, 4) => $expand!(44, 4), - (44, 8) => $expand!(44, 8), - (44, 12) => $expand!(44, 12), - (45, 4) => $expand!(45, 4), - (45, 8) => $expand!(45, 8), - (45, 12) => $expand!(45, 12), - (46, 4) => $expand!(46, 4), - (46, 8) => $expand!(46, 8), - (46, 12) => $expand!(46, 12), - (47, 4) => $expand!(47, 4), - (47, 8) => $expand!(47, 8), - (47, 12) => $expand!(47, 12), - (48, 4) => $expand!(48, 4), - (48, 8) => $expand!(48, 8), - (48, 12) => $expand!(48, 12), - (49, 4) => $expand!(49, 4), - (49, 8) => $expand!(49, 8), - (49, 12) => $expand!(49, 12), - (50, 4) => $expand!(50, 4), - (50, 8) => $expand!(50, 8), - (50, 12) => $expand!(50, 12), - (51, 4) => $expand!(51, 4), - (51, 8) => $expand!(51, 8), - (51, 12) => $expand!(51, 12), - (52, 4) => $expand!(52, 4), - (52, 8) => $expand!(52, 8), - (52, 12) => $expand!(52, 12), - (53, 4) => $expand!(53, 4), - (53, 8) => $expand!(53, 8), - (53, 12) => $expand!(53, 12), - (54, 4) => $expand!(54, 4), - (54, 8) => $expand!(54, 8), - (54, 12) => $expand!(54, 12), - (55, 4) => $expand!(55, 4), - (55, 8) => $expand!(55, 8), - (55, 12) => $expand!(55, 12), - (56, 4) => $expand!(56, 4), - (56, 8) => $expand!(56, 8), - (56, 12) => $expand!(56, 12), - (57, 4) => $expand!(57, 4), - (57, 8) => $expand!(57, 8), - (57, 12) => $expand!(57, 12), - (58, 4) => $expand!(58, 4), - (58, 8) => $expand!(58, 8), - (58, 12) => $expand!(58, 12), - (59, 4) => $expand!(59, 4), - (59, 8) => $expand!(59, 8), - (59, 12) => $expand!(59, 12), - (60, 4) => $expand!(60, 4), - (60, 8) => $expand!(60, 8), - (60, 12) => $expand!(60, 12), - (61, 4) => $expand!(61, 4), - (61, 8) => $expand!(61, 8), - (61, 12) => $expand!(61, 12), - (62, 4) => $expand!(62, 4), - (62, 8) => $expand!(62, 8), - (62, 12) => $expand!(62, 12), - (63, 4) => $expand!(63, 4), - (63, 8) => $expand!(63, 8), - (63, 12) => $expand!(63, 12), - (64, 4) => $expand!(64, 4), - (64, 8) => $expand!(64, 8), - (64, 12) => $expand!(64, 12), - (65, 4) => $expand!(65, 4), - (65, 8) => $expand!(65, 8), - (65, 12) => $expand!(65, 12), - (66, 4) => $expand!(66, 4), - (66, 8) => $expand!(66, 8), - (66, 12) => $expand!(66, 12), - (67, 4) => $expand!(67, 4), - (67, 8) => $expand!(67, 8), - (67, 12) => $expand!(67, 12), - (68, 4) => $expand!(68, 4), - (68, 8) => $expand!(68, 8), - (68, 12) => $expand!(68, 12), - (69, 4) => $expand!(69, 4), - (69, 8) => $expand!(69, 8), - (69, 12) => $expand!(69, 12), - (70, 4) => $expand!(70, 4), - (70, 8) => $expand!(70, 8), - (70, 12) => $expand!(70, 12), - (71, 4) => $expand!(71, 4), - (71, 8) => $expand!(71, 8), - (71, 12) => $expand!(71, 12), - (72, 4) => $expand!(72, 4), - (72, 8) => $expand!(72, 8), - (72, 12) => $expand!(72, 12), - (73, 4) => $expand!(73, 4), - (73, 8) => $expand!(73, 8), - (73, 12) => $expand!(73, 12), - (74, 4) => $expand!(74, 4), - (74, 8) => $expand!(74, 8), - (74, 12) => $expand!(74, 12), - (75, 4) => $expand!(75, 4), - (75, 8) => $expand!(75, 8), - (75, 12) => $expand!(75, 12), - (76, 4) => $expand!(76, 4), - (76, 8) => $expand!(76, 8), - (76, 12) => $expand!(76, 12), - (77, 4) => $expand!(77, 4), - (77, 8) => $expand!(77, 8), - (77, 12) => $expand!(77, 12), - (78, 4) => $expand!(78, 4), - (78, 8) => $expand!(78, 8), - (78, 12) => $expand!(78, 12), - (79, 4) => $expand!(79, 4), - (79, 8) => $expand!(79, 8), - (79, 12) => $expand!(79, 12), - (80, 4) => $expand!(80, 4), - (80, 8) => $expand!(80, 8), - (80, 12) => $expand!(80, 12), - (81, 4) => $expand!(81, 4), - (81, 8) => $expand!(81, 8), - (81, 12) => $expand!(81, 12), - (82, 4) => $expand!(82, 4), - (82, 8) => $expand!(82, 8), - (82, 12) => $expand!(82, 12), - (83, 4) => $expand!(83, 4), - (83, 8) => $expand!(83, 8), - (83, 12) => $expand!(83, 12), - (84, 4) => $expand!(84, 4), - (84, 8) => $expand!(84, 8), - (84, 12) => $expand!(84, 12), - (85, 4) => $expand!(85, 4), - (85, 8) => $expand!(85, 8), - (85, 12) => $expand!(85, 12), - (86, 4) => $expand!(86, 4), - (86, 8) => $expand!(86, 8), - (86, 12) => $expand!(86, 12), - (87, 4) => $expand!(87, 4), - (87, 8) => $expand!(87, 8), - (87, 12) => $expand!(87, 12), - (88, 4) => $expand!(88, 4), - (88, 8) => $expand!(88, 8), - (88, 12) => $expand!(88, 12), - (89, 4) => $expand!(89, 4), - (89, 8) => $expand!(89, 8), - (89, 12) => $expand!(89, 12), - (90, 4) => $expand!(90, 4), - (90, 8) => $expand!(90, 8), - (90, 12) => $expand!(90, 12), - (91, 4) => $expand!(91, 4), - (91, 8) => $expand!(91, 8), - (91, 12) => $expand!(91, 12), - (92, 4) => $expand!(92, 4), - (92, 8) => $expand!(92, 8), - (92, 12) => $expand!(92, 12), - (93, 4) => $expand!(93, 4), - (93, 8) => $expand!(93, 8), - (93, 12) => $expand!(93, 12), - (94, 4) => $expand!(94, 4), - (94, 8) => $expand!(94, 8), - (94, 12) => $expand!(94, 12), - (95, 4) => $expand!(95, 4), - (95, 8) => $expand!(95, 8), - (95, 12) => $expand!(95, 12), - (96, 4) => $expand!(96, 4), - (96, 8) => $expand!(96, 8), - (96, 12) => $expand!(96, 12), - (97, 4) => $expand!(97, 4), - (97, 8) => $expand!(97, 8), - (97, 12) => $expand!(97, 12), - (98, 4) => $expand!(98, 4), - (98, 8) => $expand!(98, 8), - (98, 12) => $expand!(98, 12), - (99, 4) => $expand!(99, 4), - (99, 8) => $expand!(99, 8), - (99, 12) => $expand!(99, 12), - (100, 4) => $expand!(100, 4), - (100, 8) => $expand!(100, 8), - (100, 12) => $expand!(100, 12), - (101, 4) => $expand!(101, 4), - (101, 8) => $expand!(101, 8), - (101, 12) => $expand!(101, 12), - (102, 4) => $expand!(102, 4), - (102, 8) => $expand!(102, 8), - (102, 12) => $expand!(102, 12), - (103, 4) => $expand!(103, 4), - (103, 8) => $expand!(103, 8), - (103, 12) => $expand!(103, 12), - (104, 4) => $expand!(104, 4), - (104, 8) => $expand!(104, 8), - (104, 12) => $expand!(104, 12), - (105, 4) => $expand!(105, 4), - (105, 8) => $expand!(105, 8), - (105, 12) => $expand!(105, 12), - (106, 4) => $expand!(106, 4), - (106, 8) => $expand!(106, 8), - (106, 12) => $expand!(106, 12), - (107, 4) => $expand!(107, 4), - (107, 8) => $expand!(107, 8), - (107, 12) => $expand!(107, 12), - (108, 4) => $expand!(108, 4), - (108, 8) => $expand!(108, 8), - (108, 12) => $expand!(108, 12), - (109, 4) => $expand!(109, 4), - (109, 8) => $expand!(109, 8), - (109, 12) => $expand!(109, 12), - (110, 4) => $expand!(110, 4), - (110, 8) => $expand!(110, 8), - (110, 12) => $expand!(110, 12), - (111, 4) => $expand!(111, 4), - (111, 8) => $expand!(111, 8), - (111, 12) => $expand!(111, 12), - (112, 4) => $expand!(112, 4), - (112, 8) => $expand!(112, 8), - (112, 12) => $expand!(112, 12), - (113, 4) => $expand!(113, 4), - (113, 8) => $expand!(113, 8), - (113, 12) => $expand!(113, 12), - (114, 4) => $expand!(114, 4), - (114, 8) => $expand!(114, 8), - (114, 12) => $expand!(114, 12), - (115, 4) => $expand!(115, 4), - (115, 8) => $expand!(115, 8), - (115, 12) => $expand!(115, 12), - (116, 4) => $expand!(116, 4), - (116, 8) => $expand!(116, 8), - (116, 12) => $expand!(116, 12), - (117, 4) => $expand!(117, 4), - (117, 8) => $expand!(117, 8), - (117, 12) => $expand!(117, 12), - (118, 4) => $expand!(118, 4), - (118, 8) => $expand!(118, 8), - (118, 12) => $expand!(118, 12), - (119, 4) => $expand!(119, 4), - (119, 8) => $expand!(119, 8), - (119, 12) => $expand!(119, 12), - (120, 4) => $expand!(120, 4), - (120, 8) => $expand!(120, 8), - (120, 12) => $expand!(120, 12), - (121, 4) => $expand!(121, 4), - (121, 8) => $expand!(121, 8), - (121, 12) => $expand!(121, 12), - (122, 4) => $expand!(122, 4), - (122, 8) => $expand!(122, 8), - (122, 12) => $expand!(122, 12), - (123, 4) => $expand!(123, 4), - (123, 8) => $expand!(123, 8), - (123, 12) => $expand!(123, 12), - (124, 4) => $expand!(124, 4), - (124, 8) => $expand!(124, 8), - (124, 12) => $expand!(124, 12), - (125, 4) => $expand!(125, 4), - (125, 8) => $expand!(125, 8), - (125, 12) => $expand!(125, 12), - (126, 4) => $expand!(126, 4), - (126, 8) => $expand!(126, 8), - (126, 12) => $expand!(126, 12), - (127, 4) => $expand!(127, 4), - (127, 8) => $expand!(127, 8), - (127, 12) => $expand!(127, 12), - (128, 4) => $expand!(128, 4), - (128, 8) => $expand!(128, 8), - (128, 12) => $expand!(128, 12), - (129, 4) => $expand!(129, 4), - (129, 8) => $expand!(129, 8), - (129, 12) => $expand!(129, 12), - (130, 4) => $expand!(130, 4), - (130, 8) => $expand!(130, 8), - (130, 12) => $expand!(130, 12), - (131, 4) => $expand!(131, 4), - (131, 8) => $expand!(131, 8), - (131, 12) => $expand!(131, 12), - (132, 4) => $expand!(132, 4), - (132, 8) => $expand!(132, 8), - (132, 12) => $expand!(132, 12), - (133, 4) => $expand!(133, 4), - (133, 8) => $expand!(133, 8), - (133, 12) => $expand!(133, 12), - (134, 4) => $expand!(134, 4), - (134, 8) => $expand!(134, 8), - (134, 12) => $expand!(134, 12), - (135, 4) => $expand!(135, 4), - (135, 8) => $expand!(135, 8), - (135, 12) => $expand!(135, 12), - (136, 4) => $expand!(136, 4), - (136, 8) => $expand!(136, 8), - (136, 12) => $expand!(136, 12), - (137, 4) => $expand!(137, 4), - (137, 8) => $expand!(137, 8), - (137, 12) => $expand!(137, 12), - (138, 4) => $expand!(138, 4), - (138, 8) => $expand!(138, 8), - (138, 12) => $expand!(138, 12), - (139, 4) => $expand!(139, 4), - (139, 8) => $expand!(139, 8), - (139, 12) => $expand!(139, 12), - (140, 4) => $expand!(140, 4), - (140, 8) => $expand!(140, 8), - (140, 12) => $expand!(140, 12), - (141, 4) => $expand!(141, 4), - (141, 8) => $expand!(141, 8), - (141, 12) => $expand!(141, 12), - (142, 4) => $expand!(142, 4), - (142, 8) => $expand!(142, 8), - (142, 12) => $expand!(142, 12), - (143, 4) => $expand!(143, 4), - (143, 8) => $expand!(143, 8), - (143, 12) => $expand!(143, 12), - (144, 4) => $expand!(144, 4), - (144, 8) => $expand!(144, 8), - (144, 12) => $expand!(144, 12), - (145, 4) => $expand!(145, 4), - (145, 8) => $expand!(145, 8), - (145, 12) => $expand!(145, 12), - (146, 4) => $expand!(146, 4), - (146, 8) => $expand!(146, 8), - (146, 12) => $expand!(146, 12), - (147, 4) => $expand!(147, 4), - (147, 8) => $expand!(147, 8), - (147, 12) => $expand!(147, 12), - (148, 4) => $expand!(148, 4), - (148, 8) => $expand!(148, 8), - (148, 12) => $expand!(148, 12), - (149, 4) => $expand!(149, 4), - (149, 8) => $expand!(149, 8), - (149, 12) => $expand!(149, 12), - (150, 4) => $expand!(150, 4), - (150, 8) => $expand!(150, 8), - (150, 12) => $expand!(150, 12), - (151, 4) => $expand!(151, 4), - (151, 8) => $expand!(151, 8), - (151, 12) => $expand!(151, 12), - (152, 4) => $expand!(152, 4), - (152, 8) => $expand!(152, 8), - (152, 12) => $expand!(152, 12), - (153, 4) => $expand!(153, 4), - (153, 8) => $expand!(153, 8), - (153, 12) => $expand!(153, 12), - (154, 4) => $expand!(154, 4), - (154, 8) => $expand!(154, 8), - (154, 12) => $expand!(154, 12), - (155, 4) => $expand!(155, 4), - (155, 8) => $expand!(155, 8), - (155, 12) => $expand!(155, 12), - (156, 4) => $expand!(156, 4), - (156, 8) => $expand!(156, 8), - (156, 12) => $expand!(156, 12), - (157, 4) => $expand!(157, 4), - (157, 8) => $expand!(157, 8), - (157, 12) => $expand!(157, 12), - (158, 4) => $expand!(158, 4), - (158, 8) => $expand!(158, 8), - (158, 12) => $expand!(158, 12), - (159, 4) => $expand!(159, 4), - (159, 8) => $expand!(159, 8), - (159, 12) => $expand!(159, 12), - (160, 4) => $expand!(160, 4), - (160, 8) => $expand!(160, 8), - (160, 12) => $expand!(160, 12), - (161, 4) => $expand!(161, 4), - (161, 8) => $expand!(161, 8), - (161, 12) => $expand!(161, 12), - (162, 4) => $expand!(162, 4), - (162, 8) => $expand!(162, 8), - (162, 12) => $expand!(162, 12), - (163, 4) => $expand!(163, 4), - (163, 8) => $expand!(163, 8), - (163, 12) => $expand!(163, 12), - (164, 4) => $expand!(164, 4), - (164, 8) => $expand!(164, 8), - (164, 12) => $expand!(164, 12), - (165, 4) => $expand!(165, 4), - (165, 8) => $expand!(165, 8), - (165, 12) => $expand!(165, 12), - (166, 4) => $expand!(166, 4), - (166, 8) => $expand!(166, 8), - (166, 12) => $expand!(166, 12), - (167, 4) => $expand!(167, 4), - (167, 8) => $expand!(167, 8), - (167, 12) => $expand!(167, 12), - (168, 4) => $expand!(168, 4), - (168, 8) => $expand!(168, 8), - (168, 12) => $expand!(168, 12), - (169, 4) => $expand!(169, 4), - (169, 8) => $expand!(169, 8), - (169, 12) => $expand!(169, 12), - (170, 4) => $expand!(170, 4), - (170, 8) => $expand!(170, 8), - (170, 12) => $expand!(170, 12), - (171, 4) => $expand!(171, 4), - (171, 8) => $expand!(171, 8), - (171, 12) => $expand!(171, 12), - (172, 4) => $expand!(172, 4), - (172, 8) => $expand!(172, 8), - (172, 12) => $expand!(172, 12), - (173, 4) => $expand!(173, 4), - (173, 8) => $expand!(173, 8), - (173, 12) => $expand!(173, 12), - (174, 4) => $expand!(174, 4), - (174, 8) => $expand!(174, 8), - (174, 12) => $expand!(174, 12), - (175, 4) => $expand!(175, 4), - (175, 8) => $expand!(175, 8), - (175, 12) => $expand!(175, 12), - (176, 4) => $expand!(176, 4), - (176, 8) => $expand!(176, 8), - (176, 12) => $expand!(176, 12), - (177, 4) => $expand!(177, 4), - (177, 8) => $expand!(177, 8), - (177, 12) => $expand!(177, 12), - (178, 4) => $expand!(178, 4), - (178, 8) => $expand!(178, 8), - (178, 12) => $expand!(178, 12), - (179, 4) => $expand!(179, 4), - (179, 8) => $expand!(179, 8), - (179, 12) => $expand!(179, 12), - (180, 4) => $expand!(180, 4), - (180, 8) => $expand!(180, 8), - (180, 12) => $expand!(180, 12), - (181, 4) => $expand!(181, 4), - (181, 8) => $expand!(181, 8), - (181, 12) => $expand!(181, 12), - (182, 4) => $expand!(182, 4), - (182, 8) => $expand!(182, 8), - (182, 12) => $expand!(182, 12), - (183, 4) => $expand!(183, 4), - (183, 8) => $expand!(183, 8), - (183, 12) => $expand!(183, 12), - (184, 4) => $expand!(184, 4), - (184, 8) => $expand!(184, 8), - (184, 12) => $expand!(184, 12), - (185, 4) => $expand!(185, 4), - (185, 8) => $expand!(185, 8), - (185, 12) => $expand!(185, 12), - (186, 4) => $expand!(186, 4), - (186, 8) => $expand!(186, 8), - (186, 12) => $expand!(186, 12), - (187, 4) => $expand!(187, 4), - (187, 8) => $expand!(187, 8), - (187, 12) => $expand!(187, 12), - (188, 4) => $expand!(188, 4), - (188, 8) => $expand!(188, 8), - (188, 12) => $expand!(188, 12), - (189, 4) => $expand!(189, 4), - (189, 8) => $expand!(189, 8), - (189, 12) => $expand!(189, 12), - (190, 4) => $expand!(190, 4), - (190, 8) => $expand!(190, 8), - (190, 12) => $expand!(190, 12), - (191, 4) => $expand!(191, 4), - (191, 8) => $expand!(191, 8), - (191, 12) => $expand!(191, 12), - (192, 4) => $expand!(192, 4), - (192, 8) => $expand!(192, 8), - (192, 12) => $expand!(192, 12), - (193, 4) => $expand!(193, 4), - (193, 8) => $expand!(193, 8), - (193, 12) => $expand!(193, 12), - (194, 4) => $expand!(194, 4), - (194, 8) => $expand!(194, 8), - (194, 12) => $expand!(194, 12), - (195, 4) => $expand!(195, 4), - (195, 8) => $expand!(195, 8), - (195, 12) => $expand!(195, 12), - (196, 4) => $expand!(196, 4), - (196, 8) => $expand!(196, 8), - (196, 12) => $expand!(196, 12), - (197, 4) => $expand!(197, 4), - (197, 8) => $expand!(197, 8), - (197, 12) => $expand!(197, 12), - (198, 4) => $expand!(198, 4), - (198, 8) => $expand!(198, 8), - (198, 12) => $expand!(198, 12), - (199, 4) => $expand!(199, 4), - (199, 8) => $expand!(199, 8), - (199, 12) => $expand!(199, 12), - (200, 4) => $expand!(200, 4), - (200, 8) => $expand!(200, 8), - (200, 12) => $expand!(200, 12), - (201, 4) => $expand!(201, 4), - (201, 8) => $expand!(201, 8), - (201, 12) => $expand!(201, 12), - (202, 4) => $expand!(202, 4), - (202, 8) => $expand!(202, 8), - (202, 12) => $expand!(202, 12), - (203, 4) => $expand!(203, 4), - (203, 8) => $expand!(203, 8), - (203, 12) => $expand!(203, 12), - (204, 4) => $expand!(204, 4), - (204, 8) => $expand!(204, 8), - (204, 12) => $expand!(204, 12), - (205, 4) => $expand!(205, 4), - (205, 8) => $expand!(205, 8), - (205, 12) => $expand!(205, 12), - (206, 4) => $expand!(206, 4), - (206, 8) => $expand!(206, 8), - (206, 12) => $expand!(206, 12), - (207, 4) => $expand!(207, 4), - (207, 8) => $expand!(207, 8), - (207, 12) => $expand!(207, 12), - (208, 4) => $expand!(208, 4), - (208, 8) => $expand!(208, 8), - (208, 12) => $expand!(208, 12), - (209, 4) => $expand!(209, 4), - (209, 8) => $expand!(209, 8), - (209, 12) => $expand!(209, 12), - (210, 4) => $expand!(210, 4), - (210, 8) => $expand!(210, 8), - (210, 12) => $expand!(210, 12), - (211, 4) => $expand!(211, 4), - (211, 8) => $expand!(211, 8), - (211, 12) => $expand!(211, 12), - (212, 4) => $expand!(212, 4), - (212, 8) => $expand!(212, 8), - (212, 12) => $expand!(212, 12), - (213, 4) => $expand!(213, 4), - (213, 8) => $expand!(213, 8), - (213, 12) => $expand!(213, 12), - (214, 4) => $expand!(214, 4), - (214, 8) => $expand!(214, 8), - (214, 12) => $expand!(214, 12), - (215, 4) => $expand!(215, 4), - (215, 8) => $expand!(215, 8), - (215, 12) => $expand!(215, 12), - (216, 4) => $expand!(216, 4), - (216, 8) => $expand!(216, 8), - (216, 12) => $expand!(216, 12), - (217, 4) => $expand!(217, 4), - (217, 8) => $expand!(217, 8), - (217, 12) => $expand!(217, 12), - (218, 4) => $expand!(218, 4), - (218, 8) => $expand!(218, 8), - (218, 12) => $expand!(218, 12), - (219, 4) => $expand!(219, 4), - (219, 8) => $expand!(219, 8), - (219, 12) => $expand!(219, 12), - (220, 4) => $expand!(220, 4), - (220, 8) => $expand!(220, 8), - (220, 12) => $expand!(220, 12), - (221, 4) => $expand!(221, 4), - (221, 8) => $expand!(221, 8), - (221, 12) => $expand!(221, 12), - (222, 4) => $expand!(222, 4), - (222, 8) => $expand!(222, 8), - (222, 12) => $expand!(222, 12), - (223, 4) => $expand!(223, 4), - (223, 8) => $expand!(223, 8), - (223, 12) => $expand!(223, 12), - (224, 4) => $expand!(224, 4), - (224, 8) => $expand!(224, 8), - (224, 12) => $expand!(224, 12), - (225, 4) => $expand!(225, 4), - (225, 8) => $expand!(225, 8), - (225, 12) => $expand!(225, 12), - (226, 4) => $expand!(226, 4), - (226, 8) => $expand!(226, 8), - (226, 12) => $expand!(226, 12), - (227, 4) => $expand!(227, 4), - (227, 8) => $expand!(227, 8), - (227, 12) => $expand!(227, 12), - (228, 4) => $expand!(228, 4), - (228, 8) => $expand!(228, 8), - (228, 12) => $expand!(228, 12), - (229, 4) => $expand!(229, 4), - (229, 8) => $expand!(229, 8), - (229, 12) => $expand!(229, 12), - (230, 4) => $expand!(230, 4), - (230, 8) => $expand!(230, 8), - (230, 12) => $expand!(230, 12), - (231, 4) => $expand!(231, 4), - (231, 8) => $expand!(231, 8), - (231, 12) => $expand!(231, 12), - (232, 4) => $expand!(232, 4), - (232, 8) => $expand!(232, 8), - (232, 12) => $expand!(232, 12), - (233, 4) => $expand!(233, 4), - (233, 8) => $expand!(233, 8), - (233, 12) => $expand!(233, 12), - (234, 4) => $expand!(234, 4), - (234, 8) => $expand!(234, 8), - (234, 12) => $expand!(234, 12), - (235, 4) => $expand!(235, 4), - (235, 8) => $expand!(235, 8), - (235, 12) => $expand!(235, 12), - (236, 4) => $expand!(236, 4), - (236, 8) => $expand!(236, 8), - (236, 12) => $expand!(236, 12), - (237, 4) => $expand!(237, 4), - (237, 8) => $expand!(237, 8), - (237, 12) => $expand!(237, 12), - (238, 4) => $expand!(238, 4), - (238, 8) => $expand!(238, 8), - (238, 12) => $expand!(238, 12), - (239, 4) => $expand!(239, 4), - (239, 8) => $expand!(239, 8), - (239, 12) => $expand!(239, 12), - (240, 4) => $expand!(240, 4), - (240, 8) => $expand!(240, 8), - (240, 12) => $expand!(240, 12), - (241, 4) => $expand!(241, 4), - (241, 8) => $expand!(241, 8), - (241, 12) => $expand!(241, 12), - (242, 4) => $expand!(242, 4), - (242, 8) => $expand!(242, 8), - (242, 12) => $expand!(242, 12), - (243, 4) => $expand!(243, 4), - (243, 8) => $expand!(243, 8), - (243, 12) => $expand!(243, 12), - (244, 4) => $expand!(244, 4), - (244, 8) => $expand!(244, 8), - (244, 12) => $expand!(244, 12), - (245, 4) => $expand!(245, 4), - (245, 8) => $expand!(245, 8), - (245, 12) => $expand!(245, 12), - (246, 4) => $expand!(246, 4), - (246, 8) => $expand!(246, 8), - (246, 12) => $expand!(246, 12), - (247, 4) => $expand!(247, 4), - (247, 8) => $expand!(247, 8), - (247, 12) => $expand!(247, 12), - (248, 4) => $expand!(248, 4), - (248, 8) => $expand!(248, 8), - (248, 12) => $expand!(248, 12), - (249, 4) => $expand!(249, 4), - (249, 8) => $expand!(249, 8), - (249, 12) => $expand!(249, 12), - (250, 4) => $expand!(250, 4), - (250, 8) => $expand!(250, 8), - (250, 12) => $expand!(250, 12), - (251, 4) => $expand!(251, 4), - (251, 8) => $expand!(251, 8), - (251, 12) => $expand!(251, 12), - (252, 4) => $expand!(252, 4), - (252, 8) => $expand!(252, 8), - (252, 12) => $expand!(252, 12), - (253, 4) => $expand!(253, 4), - (253, 8) => $expand!(253, 8), - (253, 12) => $expand!(253, 12), - (254, 4) => $expand!(254, 4), - (254, 8) => $expand!(254, 8), - (254, 12) => $expand!(254, 12), - (255, 4) => $expand!(255, 4), - (255, 8) => $expand!(255, 8), - (255, 12) => $expand!(255, 12), - (_, _) => panic!("Invalid sae value"), - } - }; -} - #[cfg(test)] macro_rules! assert_approx_eq { ($a:expr, $b:expr, $eps:expr) => {{ diff --git a/library/stdarch/crates/core_arch/src/x86_64/avx512f.rs b/library/stdarch/crates/core_arch/src/x86_64/avx512f.rs index 9699f2bb684a..017ee20f6d72 100644 --- a/library/stdarch/crates/core_arch/src/x86_64/avx512f.rs +++ b/library/stdarch/crates/core_arch/src/x86_64/avx512f.rs @@ -3219,7 +3219,7 @@ mod tests { #[simd_test(enable = "avx512f")] unsafe fn test_mm512_getmant_pd() { let a = _mm512_set1_pd(10.); - let r = _mm512_getmant_pd(a, _MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC); + let r = _mm512_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(a); let e = _mm512_set1_pd(1.25); assert_eq_m512d(r, e); } @@ -3227,9 +3227,9 @@ mod tests { #[simd_test(enable = "avx512f")] unsafe fn test_mm512_mask_getmant_pd() { let a = _mm512_set1_pd(10.); - let r = _mm512_mask_getmant_pd(a, 0, a, _MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC); + let r = _mm512_mask_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(a, 0, a); assert_eq_m512d(r, a); - let r = _mm512_mask_getmant_pd(a, 0b11110000, a, _MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC); + let r = _mm512_mask_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(a, 0b11110000, a); let e = _mm512_setr_pd(10., 10., 10., 10., 1.25, 1.25, 1.25, 1.25); assert_eq_m512d(r, e); } @@ -3237,9 +3237,9 @@ mod tests { #[simd_test(enable = "avx512f")] unsafe fn test_mm512_maskz_getmant_pd() { let a = _mm512_set1_pd(10.); - let r = _mm512_maskz_getmant_pd(0, a, _MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC); + let r = _mm512_maskz_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(0, a); assert_eq_m512d(r, _mm512_setzero_pd()); - let r = _mm512_maskz_getmant_pd(0b11110000, a, _MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC); + let r = _mm512_maskz_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(0b11110000, a); let e = _mm512_setr_pd(0., 0., 0., 0., 1.25, 1.25, 1.25, 1.25); assert_eq_m512d(r, e); } @@ -3247,7 +3247,7 @@ mod tests { #[simd_test(enable = "avx512f,avx512vl")] unsafe fn test_mm256_getmant_pd() { let a = _mm256_set1_pd(10.); - let r = _mm256_getmant_pd(a, _MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC); + let r = _mm256_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(a); let e = _mm256_set1_pd(1.25); assert_eq_m256d(r, e); } @@ -3255,9 +3255,9 @@ mod tests { #[simd_test(enable = "avx512f,avx512vl")] unsafe fn test_mm256_mask_getmant_pd() { let a = _mm256_set1_pd(10.); - let r = _mm256_mask_getmant_pd(a, 0, a, _MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC); + let r = _mm256_mask_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(a, 0, a); assert_eq_m256d(r, a); - let r = _mm256_mask_getmant_pd(a, 0b00001111, a, _MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC); + let r = _mm256_mask_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(a, 0b00001111, a); let e = _mm256_set1_pd(1.25); assert_eq_m256d(r, e); } @@ -3265,9 +3265,9 @@ mod tests { #[simd_test(enable = "avx512f,avx512vl")] unsafe fn test_mm256_maskz_getmant_pd() { let a = _mm256_set1_pd(10.); - let r = _mm256_maskz_getmant_pd(0, a, _MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC); + let r = _mm256_maskz_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(0, a); assert_eq_m256d(r, _mm256_setzero_pd()); - let r = _mm256_maskz_getmant_pd(0b00001111, a, _MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC); + let r = _mm256_maskz_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(0b00001111, a); let e = _mm256_set1_pd(1.25); assert_eq_m256d(r, e); } @@ -3275,7 +3275,7 @@ mod tests { #[simd_test(enable = "avx512f,avx512vl")] unsafe fn test_mm_getmant_pd() { let a = _mm_set1_pd(10.); - let r = _mm_getmant_pd(a, _MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC); + let r = _mm_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(a); let e = _mm_set1_pd(1.25); assert_eq_m128d(r, e); } @@ -3283,9 +3283,9 @@ mod tests { #[simd_test(enable = "avx512f,avx512vl")] unsafe fn test_mm_mask_getmant_pd() { let a = _mm_set1_pd(10.); - let r = _mm_mask_getmant_pd(a, 0, a, _MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC); + let r = _mm_mask_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(a, 0, a); assert_eq_m128d(r, a); - let r = _mm_mask_getmant_pd(a, 0b00000011, a, _MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC); + let r = _mm_mask_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(a, 0b00000011, a); let e = _mm_set1_pd(1.25); assert_eq_m128d(r, e); } @@ -3293,9 +3293,9 @@ mod tests { #[simd_test(enable = "avx512f,avx512vl")] unsafe fn test_mm_maskz_getmant_pd() { let a = _mm_set1_pd(10.); - let r = _mm_maskz_getmant_pd(0, a, _MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC); + let r = _mm_maskz_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(0, a); assert_eq_m128d(r, _mm_setzero_pd()); - let r = _mm_maskz_getmant_pd(0b00000011, a, _MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC); + let r = _mm_maskz_getmant_pd::<_MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC>(0b00000011, a); let e = _mm_set1_pd(1.25); assert_eq_m128d(r, e); } @@ -6030,7 +6030,7 @@ mod tests { #[simd_test(enable = "avx512f")] unsafe fn test_mm512_roundscale_round_pd() { let a = _mm512_set1_pd(1.1); - let r = _mm512_roundscale_round_pd(a, 0, _MM_FROUND_CUR_DIRECTION); + let r = _mm512_roundscale_round_pd::<0, _MM_FROUND_CUR_DIRECTION>(a); let e = _mm512_set1_pd(1.0); assert_eq_m512d(r, e); } @@ -6038,10 +6038,10 @@ mod tests { #[simd_test(enable = "avx512f")] unsafe fn test_mm512_mask_roundscale_round_pd() { let a = _mm512_set1_pd(1.1); - let r = _mm512_mask_roundscale_round_pd(a, 0, a, 0, _MM_FROUND_CUR_DIRECTION); + let r = _mm512_mask_roundscale_round_pd::<0, _MM_FROUND_CUR_DIRECTION>(a, 0, a); let e = _mm512_set1_pd(1.1); assert_eq_m512d(r, e); - let r = _mm512_mask_roundscale_round_pd(a, 0b11111111, a, 0, _MM_FROUND_CUR_DIRECTION); + let r = _mm512_mask_roundscale_round_pd::<0, _MM_FROUND_CUR_DIRECTION>(a, 0b11111111, a); let e = _mm512_set1_pd(1.0); assert_eq_m512d(r, e); } @@ -6049,9 +6049,9 @@ mod tests { #[simd_test(enable = "avx512f")] unsafe fn test_mm512_maskz_roundscale_round_pd() { let a = _mm512_set1_pd(1.1); - let r = _mm512_maskz_roundscale_round_pd(0, a, 0, _MM_FROUND_CUR_DIRECTION); + let r = _mm512_maskz_roundscale_round_pd::<0, _MM_FROUND_CUR_DIRECTION>(0, a); assert_eq_m512d(r, _mm512_setzero_pd()); - let r = _mm512_maskz_roundscale_round_pd(0b11111111, a, 0, _MM_FROUND_CUR_DIRECTION); + let r = _mm512_maskz_roundscale_round_pd::<0, _MM_FROUND_CUR_DIRECTION>(0b11111111, a); let e = _mm512_set1_pd(1.0); assert_eq_m512d(r, e); } @@ -6100,7 +6100,7 @@ mod tests { let a = _mm512_set1_pd(f64::NAN); let b = _mm512_set1_pd(f64::MAX); let c = _mm512_set1_epi64(i32::MAX as i64); - let r = _mm512_fixupimm_round_pd(a, b, c, 5, _MM_FROUND_CUR_DIRECTION); + let r = _mm512_fixupimm_round_pd::<5, _MM_FROUND_CUR_DIRECTION>(a, b, c); let e = _mm512_set1_pd(0.0); assert_eq_m512d(r, e); } @@ -6110,7 +6110,7 @@ mod tests { let a = _mm512_set_pd(f64::NAN, f64::NAN, f64::NAN, f64::NAN, 1., 1., 1., 1.); let b = _mm512_set1_pd(f64::MAX); let c = _mm512_set1_epi64(i32::MAX as i64); - let r = _mm512_mask_fixupimm_round_pd(a, 0b11110000, b, c, 5, _MM_FROUND_CUR_DIRECTION); + let r = _mm512_mask_fixupimm_round_pd::<5, _MM_FROUND_CUR_DIRECTION>(a, 0b11110000, b, c); let e = _mm512_set_pd(0., 0., 0., 0., 1., 1., 1., 1.); assert_eq_m512d(r, e); } @@ -6120,7 +6120,7 @@ mod tests { let a = _mm512_set_pd(f64::NAN, f64::NAN, f64::NAN, f64::NAN, 1., 1., 1., 1.); let b = _mm512_set1_pd(f64::MAX); let c = _mm512_set1_epi64(i32::MAX as i64); - let r = _mm512_maskz_fixupimm_round_pd(0b11110000, a, b, c, 5, _MM_FROUND_CUR_DIRECTION); + let r = _mm512_maskz_fixupimm_round_pd::<5, _MM_FROUND_CUR_DIRECTION>(0b11110000, a, b, c); let e = _mm512_set_pd(0., 0., 0., 0., 0., 0., 0., 0.); assert_eq_m512d(r, e); } @@ -6128,12 +6128,11 @@ mod tests { #[simd_test(enable = "avx512f")] unsafe fn test_mm512_getmant_round_pd() { let a = _mm512_set1_pd(10.); - let r = _mm512_getmant_round_pd( - a, + let r = _mm512_getmant_round_pd::< _MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC, _MM_FROUND_CUR_DIRECTION, - ); + >(a); let e = _mm512_set1_pd(1.25); assert_eq_m512d(r, e); } @@ -6141,23 +6140,17 @@ mod tests { #[simd_test(enable = "avx512f")] unsafe fn test_mm512_mask_getmant_round_pd() { let a = _mm512_set1_pd(10.); - let r = _mm512_mask_getmant_round_pd( - a, - 0, - a, + let r = _mm512_mask_getmant_round_pd::< _MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC, _MM_FROUND_CUR_DIRECTION, - ); + >(a, 0, a); assert_eq_m512d(r, a); - let r = _mm512_mask_getmant_round_pd( - a, - 0b11110000, - a, + let r = _mm512_mask_getmant_round_pd::< _MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC, _MM_FROUND_CUR_DIRECTION, - ); + >(a, 0b11110000, a); let e = _mm512_setr_pd(10., 10., 10., 10., 1.25, 1.25, 1.25, 1.25); assert_eq_m512d(r, e); } @@ -6165,21 +6158,17 @@ mod tests { #[simd_test(enable = "avx512f")] unsafe fn test_mm512_maskz_getmant_round_pd() { let a = _mm512_set1_pd(10.); - let r = _mm512_maskz_getmant_round_pd( - 0, - a, + let r = _mm512_maskz_getmant_round_pd::< _MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC, _MM_FROUND_CUR_DIRECTION, - ); + >(0, a); assert_eq_m512d(r, _mm512_setzero_pd()); - let r = _mm512_maskz_getmant_round_pd( - 0b11110000, - a, + let r = _mm512_maskz_getmant_round_pd::< _MM_MANT_NORM_1_2, _MM_MANT_SIGN_SRC, _MM_FROUND_CUR_DIRECTION, - ); + >(0b11110000, a); let e = _mm512_setr_pd(0., 0., 0., 0., 1.25, 1.25, 1.25, 1.25); assert_eq_m512d(r, e); } @@ -6500,7 +6489,7 @@ mod tests { #[rustfmt::skip] let a = _mm512_set_pd(0., 1., -1., 13., f64::MAX, f64::MIN, 100., -100.); let b = _mm512_set1_pd(-1.); - let m = _mm512_cmp_round_pd_mask(a, b, _CMP_LT_OQ, _MM_FROUND_CUR_DIRECTION); + let m = _mm512_cmp_round_pd_mask::<_CMP_LT_OQ, _MM_FROUND_CUR_DIRECTION>(a, b); assert_eq!(m, 0b00000101); } @@ -6510,7 +6499,7 @@ mod tests { let a = _mm512_set_pd(0., 1., -1., 13., f64::MAX, f64::MIN, 100., -100.); let b = _mm512_set1_pd(-1.); let mask = 0b01100110; - let r = _mm512_mask_cmp_round_pd_mask(mask, a, b, _CMP_LT_OQ, _MM_FROUND_CUR_DIRECTION); + let r = _mm512_mask_cmp_round_pd_mask::<_CMP_LT_OQ, _MM_FROUND_CUR_DIRECTION>(mask, a, b); assert_eq!(r, 0b00000100); } @@ -8886,7 +8875,7 @@ mod tests { #[simd_test(enable = "avx512f")] unsafe fn test_mm512_permute_pd() { let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.); - let r = _mm512_permute_pd(a, 0b1111); + let r = _mm512_permute_pd::<0b11_11_11_11>(a); let e = _mm512_setr_pd(1., 1., 3., 3., 5., 5., 7., 7.); assert_eq_m512d(r, e); } @@ -8894,9 +8883,9 @@ mod tests { #[simd_test(enable = "avx512f")] unsafe fn test_mm512_mask_permute_pd() { let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.); - let r = _mm512_mask_permute_pd(a, 0, a, 0b1111); + let r = _mm512_mask_permute_pd::<0b11_11_11_11>(a, 0, a); assert_eq_m512d(r, a); - let r = _mm512_mask_permute_pd(a, 0b11111111, a, 0b1111); + let r = _mm512_mask_permute_pd::<0b11_11_11_11>(a, 0b11111111, a); let e = _mm512_setr_pd(1., 1., 3., 3., 5., 5., 7., 7.); assert_eq_m512d(r, e); } @@ -8904,9 +8893,9 @@ mod tests { #[simd_test(enable = "avx512f")] unsafe fn test_mm512_maskz_permute_pd() { let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.); - let r = _mm512_maskz_permute_pd(0, a, 0b1111); + let r = _mm512_maskz_permute_pd::<0b11_11_11_11>(0, a); assert_eq_m512d(r, _mm512_setzero_pd()); - let r = _mm512_maskz_permute_pd(0b11111111, a, 0b1111); + let r = _mm512_maskz_permute_pd::<0b11_11_11_11>(0b11111111, a); let e = _mm512_setr_pd(1., 1., 3., 3., 5., 5., 7., 7.); assert_eq_m512d(r, e); } @@ -8914,9 +8903,9 @@ mod tests { #[simd_test(enable = "avx512f,avx512vl")] unsafe fn test_mm256_mask_permute_pd() { let a = _mm256_set_pd(3., 2., 1., 0.); - let r = _mm256_mask_permute_pd(a, 0, a, 0b1111); + let r = _mm256_mask_permute_pd::<0b11_11>(a, 0, a); assert_eq_m256d(r, a); - let r = _mm256_mask_permute_pd(a, 0b00001111, a, 0b1111); + let r = _mm256_mask_permute_pd::<0b11_11>(a, 0b00001111, a); let e = _mm256_set_pd(3., 3., 1., 1.); assert_eq_m256d(r, e); } @@ -8924,9 +8913,9 @@ mod tests { #[simd_test(enable = "avx512f,avx512vl")] unsafe fn test_mm256_maskz_permute_pd() { let a = _mm256_set_pd(3., 2., 1., 0.); - let r = _mm256_maskz_permute_pd(0, a, 0b1111); + let r = _mm256_maskz_permute_pd::<0b11_11>(0, a); assert_eq_m256d(r, _mm256_setzero_pd()); - let r = _mm256_maskz_permute_pd(0b00001111, a, 0b1111); + let r = _mm256_maskz_permute_pd::<0b11_11>(0b00001111, a); let e = _mm256_set_pd(3., 3., 1., 1.); assert_eq_m256d(r, e); } @@ -8954,7 +8943,7 @@ mod tests { #[simd_test(enable = "avx512f")] unsafe fn test_mm512_permutex_epi64() { let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7); - let r = _mm512_permutex_epi64(a, 0b11111111); + let r = _mm512_permutex_epi64::<0b11_11_11_11>(a); let e = _mm512_setr_epi64(3, 3, 3, 3, 7, 7, 7, 7); assert_eq_m512i(r, e); } @@ -8962,9 +8951,9 @@ mod tests { #[simd_test(enable = "avx512f")] unsafe fn test_mm512_mask_permutex_epi64() { let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7); - let r = _mm512_mask_permutex_epi64(a, 0, a, 0b11111111); + let r = _mm512_mask_permutex_epi64::<0b11_11_11_11>(a, 0, a); assert_eq_m512i(r, a); - let r = _mm512_mask_permutex_epi64(a, 0b11111111, a, 0b11111111); + let r = _mm512_mask_permutex_epi64::<0b11_11_11_11>(a, 0b11111111, a); let e = _mm512_setr_epi64(3, 3, 3, 3, 7, 7, 7, 7); assert_eq_m512i(r, e); } @@ -8972,9 +8961,9 @@ mod tests { #[simd_test(enable = "avx512f")] unsafe fn test_mm512_maskz_permutex_epi64() { let a = _mm512_setr_epi64(0, 1, 2, 3, 4, 5, 6, 7); - let r = _mm512_maskz_permutex_epi64(0, a, 0b11111111); + let r = _mm512_maskz_permutex_epi64::<0b11_11_11_11>(0, a); assert_eq_m512i(r, _mm512_setzero_si512()); - let r = _mm512_maskz_permutex_epi64(0b11111111, a, 0b11111111); + let r = _mm512_maskz_permutex_epi64::<0b11_11_11_11>(0b11111111, a); let e = _mm512_setr_epi64(3, 3, 3, 3, 7, 7, 7, 7); assert_eq_m512i(r, e); } @@ -8982,7 +8971,7 @@ mod tests { #[simd_test(enable = "avx512f,avx512vl")] unsafe fn test_mm256_permutex_epi64() { let a = _mm256_set_epi64x(3, 2, 1, 0); - let r = _mm256_permutex_epi64(a, 0b11111111); + let r = _mm256_permutex_epi64::<0b11_11_11_11>(a); let e = _mm256_set_epi64x(3, 3, 3, 3); assert_eq_m256i(r, e); } @@ -8990,9 +8979,9 @@ mod tests { #[simd_test(enable = "avx512f,avx512vl")] unsafe fn test_mm256_mask_permutex_epi64() { let a = _mm256_set_epi64x(3, 2, 1, 0); - let r = _mm256_mask_permutex_epi64(a, 0, a, 0b11111111); + let r = _mm256_mask_permutex_epi64::<0b11_11_11_11>(a, 0, a); assert_eq_m256i(r, a); - let r = _mm256_mask_permutex_epi64(a, 0b00001111, a, 0b11111111); + let r = _mm256_mask_permutex_epi64::<0b11_11_11_11>(a, 0b00001111, a); let e = _mm256_set_epi64x(3, 3, 3, 3); assert_eq_m256i(r, e); } @@ -9000,9 +8989,9 @@ mod tests { #[simd_test(enable = "avx512f")] unsafe fn test_mm256_maskz_permutex_epi64() { let a = _mm256_set_epi64x(3, 2, 1, 0); - let r = _mm256_maskz_permutex_epi64(0, a, 0b11111111); + let r = _mm256_maskz_permutex_epi64::<0b11_11_11_11>(0, a); assert_eq_m256i(r, _mm256_setzero_si256()); - let r = _mm256_maskz_permutex_epi64(0b00001111, a, 0b11111111); + let r = _mm256_maskz_permutex_epi64::<0b11_11_11_11>(0b00001111, a); let e = _mm256_set_epi64x(3, 3, 3, 3); assert_eq_m256i(r, e); } @@ -9010,7 +8999,7 @@ mod tests { #[simd_test(enable = "avx512f")] unsafe fn test_mm512_permutex_pd() { let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.); - let r = _mm512_permutex_pd(a, 0b11111111); + let r = _mm512_permutex_pd::<0b11_11_11_11>(a); let e = _mm512_setr_pd(3., 3., 3., 3., 7., 7., 7., 7.); assert_eq_m512d(r, e); } @@ -9018,9 +9007,9 @@ mod tests { #[simd_test(enable = "avx512f")] unsafe fn test_mm512_mask_permutex_pd() { let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.); - let r = _mm512_mask_permutex_pd(a, 0, a, 0b11111111); + let r = _mm512_mask_permutex_pd::<0b11_11_11_11>(a, 0, a); assert_eq_m512d(r, a); - let r = _mm512_mask_permutex_pd(a, 0b11111111, a, 0b11111111); + let r = _mm512_mask_permutex_pd::<0b11_11_11_11>(a, 0b11111111, a); let e = _mm512_setr_pd(3., 3., 3., 3., 7., 7., 7., 7.); assert_eq_m512d(r, e); } @@ -9028,9 +9017,9 @@ mod tests { #[simd_test(enable = "avx512f")] unsafe fn test_mm512_maskz_permutex_pd() { let a = _mm512_setr_pd(0., 1., 2., 3., 4., 5., 6., 7.); - let r = _mm512_maskz_permutex_pd(0, a, 0b11111111); + let r = _mm512_maskz_permutex_pd::<0b11_11_11_11>(0, a); assert_eq_m512d(r, _mm512_setzero_pd()); - let r = _mm512_maskz_permutex_pd(0b11111111, a, 0b11111111); + let r = _mm512_maskz_permutex_pd::<0b11_11_11_11>(0b11111111, a); let e = _mm512_setr_pd(3., 3., 3., 3., 7., 7., 7., 7.); assert_eq_m512d(r, e); } @@ -9038,7 +9027,7 @@ mod tests { #[simd_test(enable = "avx512f,avx512vl")] unsafe fn test_mm256_permutex_pd() { let a = _mm256_set_pd(0., 1., 2., 3.); - let r = _mm256_permutex_pd(a, 0b11111111); + let r = _mm256_permutex_pd::<0b11_11_11_11>(a); let e = _mm256_set_pd(0., 0., 0., 0.); assert_eq_m256d(r, e); } @@ -9046,9 +9035,9 @@ mod tests { #[simd_test(enable = "avx512f,avx512vl")] unsafe fn test_mm256_mask_permutex_pd() { let a = _mm256_set_pd(0., 1., 2., 3.); - let r = _mm256_mask_permutex_pd(a, 0, a, 0b11111111); + let r = _mm256_mask_permutex_pd::<0b11_11_11_11>(a, 0, a); assert_eq_m256d(r, a); - let r = _mm256_mask_permutex_pd(a, 0b00001111, a, 0b11111111); + let r = _mm256_mask_permutex_pd::<0b11_11_11_11>(a, 0b00001111, a); let e = _mm256_set_pd(0., 0., 0., 0.); assert_eq_m256d(r, e); } @@ -9056,9 +9045,9 @@ mod tests { #[simd_test(enable = "avx512f,avx512vl")] unsafe fn test_mm256_maskz_permutex_pd() { let a = _mm256_set_pd(0., 1., 2., 3.); - let r = _mm256_maskz_permutex_pd(0, a, 0b11111111); + let r = _mm256_maskz_permutex_pd::<0b11_11_11_11>(0, a); assert_eq_m256d(r, _mm256_setzero_pd()); - let r = _mm256_maskz_permutex_pd(0b00001111, a, 0b11111111); + let r = _mm256_maskz_permutex_pd::<0b11_11_11_11>(0b00001111, a); let e = _mm256_set_pd(0., 0., 0., 0.); assert_eq_m256d(r, e); } @@ -10509,11 +10498,11 @@ mod tests { unsafe fn test_mm512_alignr_epi64() { let a = _mm512_set_epi64(8, 7, 6, 5, 4, 3, 2, 1); let b = _mm512_set_epi64(16, 15, 14, 13, 12, 11, 10, 9); - let r = _mm512_alignr_epi64(a, b, 0); + let r = _mm512_alignr_epi64::<0>(a, b); assert_eq_m512i(r, b); - let r = _mm512_alignr_epi64(a, b, 8); + let r = _mm512_alignr_epi64::<8>(a, b); assert_eq_m512i(r, b); - let r = _mm512_alignr_epi64(a, b, 1); + let r = _mm512_alignr_epi64::<1>(a, b); let e = _mm512_set_epi64(1, 16, 15, 14, 13, 12, 11, 10); assert_eq_m512i(r, e); } @@ -10522,9 +10511,9 @@ mod tests { unsafe fn test_mm512_mask_alignr_epi64() { let a = _mm512_set_epi64(8, 7, 6, 5, 4, 3, 2, 1); let b = _mm512_set_epi64(16, 15, 14, 13, 12, 11, 10, 9); - let r = _mm512_mask_alignr_epi64(a, 0, a, b, 1); + let r = _mm512_mask_alignr_epi64::<1>(a, 0, a, b); assert_eq_m512i(r, a); - let r = _mm512_mask_alignr_epi64(a, 0b11111111, a, b, 1); + let r = _mm512_mask_alignr_epi64::<1>(a, 0b11111111, a, b); let e = _mm512_set_epi64(1, 16, 15, 14, 13, 12, 11, 10); assert_eq_m512i(r, e); } @@ -10533,9 +10522,9 @@ mod tests { unsafe fn test_mm512_maskz_alignr_epi64() { let a = _mm512_set_epi64(8, 7, 6, 5, 4, 3, 2, 1); let b = _mm512_set_epi64(16, 15, 14, 13, 12, 11, 10, 9); - let r = _mm512_maskz_alignr_epi64(0, a, b, 1); + let r = _mm512_maskz_alignr_epi64::<1>(0, a, b); assert_eq_m512i(r, _mm512_setzero_si512()); - let r = _mm512_maskz_alignr_epi64(0b00001111, a, b, 1); + let r = _mm512_maskz_alignr_epi64::<1>(0b00001111, a, b); let e = _mm512_set_epi64(0, 0, 0, 0, 13, 12, 11, 10); assert_eq_m512i(r, e); } @@ -10544,10 +10533,10 @@ mod tests { unsafe fn test_mm256_alignr_epi64() { let a = _mm256_set_epi64x(4, 3, 2, 1); let b = _mm256_set_epi64x(8, 7, 6, 5); - let r = _mm256_alignr_epi64(a, b, 0); + let r = _mm256_alignr_epi64::<0>(a, b); let e = _mm256_set_epi64x(8, 7, 6, 5); assert_eq_m256i(r, e); - let r = _mm256_alignr_epi64(a, b, 6); + let r = _mm256_alignr_epi64::<6>(a, b); let e = _mm256_set_epi64x(6, 5, 4, 3); assert_eq_m256i(r, e); } @@ -10556,9 +10545,9 @@ mod tests { unsafe fn test_mm256_mask_alignr_epi64() { let a = _mm256_set_epi64x(4, 3, 2, 1); let b = _mm256_set_epi64x(8, 7, 6, 5); - let r = _mm256_mask_alignr_epi64(a, 0, a, b, 1); + let r = _mm256_mask_alignr_epi64::<1>(a, 0, a, b); assert_eq_m256i(r, a); - let r = _mm256_mask_alignr_epi64(a, 0b00001111, a, b, 0); + let r = _mm256_mask_alignr_epi64::<0>(a, 0b00001111, a, b); let e = _mm256_set_epi64x(8, 7, 6, 5); assert_eq_m256i(r, e); } @@ -10567,9 +10556,9 @@ mod tests { unsafe fn test_mm256_maskz_alignr_epi64() { let a = _mm256_set_epi64x(4, 3, 2, 1); let b = _mm256_set_epi64x(8, 7, 6, 5); - let r = _mm256_maskz_alignr_epi64(0, a, b, 1); + let r = _mm256_maskz_alignr_epi64::<1>(0, a, b); assert_eq_m256i(r, _mm256_setzero_si256()); - let r = _mm256_maskz_alignr_epi64(0b00001111, a, b, 0); + let r = _mm256_maskz_alignr_epi64::<0>(0b00001111, a, b); let e = _mm256_set_epi64x(8, 7, 6, 5); assert_eq_m256i(r, e); } @@ -10578,7 +10567,7 @@ mod tests { unsafe fn test_mm_alignr_epi64() { let a = _mm_set_epi64x(2, 1); let b = _mm_set_epi64x(4, 3); - let r = _mm_alignr_epi64(a, b, 0); + let r = _mm_alignr_epi64::<0>(a, b); let e = _mm_set_epi64x(4, 3); assert_eq_m128i(r, e); } @@ -10587,9 +10576,9 @@ mod tests { unsafe fn test_mm_mask_alignr_epi64() { let a = _mm_set_epi64x(2, 1); let b = _mm_set_epi64x(4, 3); - let r = _mm_mask_alignr_epi64(a, 0, a, b, 1); + let r = _mm_mask_alignr_epi64::<1>(a, 0, a, b); assert_eq_m128i(r, a); - let r = _mm_mask_alignr_epi64(a, 0b00000011, a, b, 0); + let r = _mm_mask_alignr_epi64::<0>(a, 0b00000011, a, b); let e = _mm_set_epi64x(4, 3); assert_eq_m128i(r, e); } @@ -10598,9 +10587,9 @@ mod tests { unsafe fn test_mm_maskz_alignr_epi64() { let a = _mm_set_epi64x(2, 1); let b = _mm_set_epi64x(4, 3); - let r = _mm_maskz_alignr_epi64(0, a, b, 1); + let r = _mm_maskz_alignr_epi64::<1>(0, a, b); assert_eq_m128i(r, _mm_setzero_si128()); - let r = _mm_maskz_alignr_epi64(0b00000011, a, b, 0); + let r = _mm_maskz_alignr_epi64::<0>(0b00000011, a, b); let e = _mm_set_epi64x(4, 3); assert_eq_m128i(r, e); }