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disable ptrace codepath since it doesn't build on many targets

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This commit is contained in:
Ralf Jung 2025-06-28 19:58:55 +02:00
parent a317123ad0
commit e56294060a
5 changed files with 29 additions and 59 deletions
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6
src/tools/miri/src/bin/miri.rs
View file

@ -227,8 +227,8 @@ impl rustc_driver::Callbacks for MiriCompilerCalls {
} else {
let return_code = miri::eval_entry(tcx, entry_def_id, entry_type, &config, None)
.unwrap_or_else(|| {
#[cfg(target_os = "linux")]
miri::native_lib::register_retcode_sv(rustc_driver::EXIT_FAILURE);
//#[cfg(target_os = "linux")]
//miri::native_lib::register_retcode_sv(rustc_driver::EXIT_FAILURE);
tcx.dcx().abort_if_errors();
rustc_driver::EXIT_FAILURE
});
@ -804,7 +804,7 @@ fn main() {
// thread in an async-signal-unsafe way such as by accessing shared
// semaphores, etc.; the handler only calls `sleep()` and `exit()`, which
// are async-signal-safe, as is accessing atomics
let _ = unsafe { miri::native_lib::init_sv() };
//let _ = unsafe { miri::native_lib::init_sv() };
}
run_compiler_and_exit(
&rustc_args,

8
src/tools/miri/src/lib.rs
View file

@ -100,10 +100,10 @@ pub use rustc_const_eval::interpret::{self, AllocMap, Provenance as _};
use rustc_middle::{bug, span_bug};
use tracing::{info, trace};
#[cfg(target_os = "linux")]
pub mod native_lib {
pub use crate::shims::{init_sv, register_retcode_sv};
}
//#[cfg(target_os = "linux")]
//pub mod native_lib {
// pub use crate::shims::{init_sv, register_retcode_sv};
//}
// Type aliases that set the provenance parameter.
pub type Pointer = interpret::Pointer<Option<machine::Provenance>>;

4
src/tools/miri/src/shims/mod.rs
View file

@ -21,8 +21,8 @@ pub mod time;
pub mod tls;
pub use self::files::FdTable;
#[cfg(target_os = "linux")]
pub use self::native_lib::trace::{init_sv, register_retcode_sv};
//#[cfg(target_os = "linux")]
//pub use self::native_lib::trace::{init_sv, register_retcode_sv};
pub use self::unix::{DirTable, EpollInterestTable};
/// What needs to be done after emulating an item (a shim or an intrinsic) is done.

35
src/tools/miri/src/shims/native_lib/mod.rs
View file

@ -1,7 +1,8 @@
//! Implements calling functions from a native library.
#[cfg(target_os = "linux")]
pub mod trace;
// FIXME: disabled since it fails to build on many targets.
//#[cfg(target_os = "linux")]
//pub mod trace;
use std::ops::Deref;
@ -12,13 +13,13 @@ use rustc_middle::mir::interpret::Pointer;
use rustc_middle::ty::{self as ty, IntTy, UintTy};
use rustc_span::Symbol;
#[cfg(target_os = "linux")]
use self::trace::Supervisor;
//#[cfg(target_os = "linux")]
//use self::trace::Supervisor;
use crate::*;
#[cfg(target_os = "linux")]
type CallResult<'tcx> = InterpResult<'tcx, (ImmTy<'tcx>, Option<self::trace::messages::MemEvents>)>;
#[cfg(not(target_os = "linux"))]
//#[cfg(target_os = "linux")]
//type CallResult<'tcx> = InterpResult<'tcx, (ImmTy<'tcx>, Option<self::trace::messages::MemEvents>)>;
//#[cfg(not(target_os = "linux"))]
type CallResult<'tcx> = InterpResult<'tcx, (ImmTy<'tcx>, Option<!>)>;
impl<'tcx> EvalContextExtPriv<'tcx> for crate::MiriInterpCx<'tcx> {}
@ -32,12 +33,12 @@ trait EvalContextExtPriv<'tcx>: crate::MiriInterpCxExt<'tcx> {
libffi_args: Vec<libffi::high::Arg<'a>>,
) -> CallResult<'tcx> {
let this = self.eval_context_mut();
#[cfg(target_os = "linux")]
let alloc = this.machine.allocator.as_ref().unwrap();
//#[cfg(target_os = "linux")]
//let alloc = this.machine.allocator.as_ref().unwrap();
// SAFETY: We don't touch the machine memory past this point.
#[cfg(target_os = "linux")]
let (guard, stack_ptr) = unsafe { Supervisor::start_ffi(alloc) };
//#[cfg(target_os = "linux")]
//let (guard, stack_ptr) = unsafe { Supervisor::start_ffi(alloc) };
// Call the function (`ptr`) with arguments `libffi_args`, and obtain the return value
// as the specified primitive integer type
@ -111,9 +112,9 @@ trait EvalContextExtPriv<'tcx>: crate::MiriInterpCxExt<'tcx> {
// SAFETY: We got the guard and stack pointer from start_ffi, and
// the allocator is the same
#[cfg(target_os = "linux")]
let events = unsafe { Supervisor::end_ffi(alloc, guard, stack_ptr) };
#[cfg(not(target_os = "linux"))]
//#[cfg(target_os = "linux")]
//let events = unsafe { Supervisor::end_ffi(alloc, guard, stack_ptr) };
//#[cfg(not(target_os = "linux"))]
let events = None;
interp_ok((res?, events))
@ -213,9 +214,9 @@ pub trait EvalContextExt<'tcx>: crate::MiriInterpCxExt<'tcx> {
if !this.machine.native_call_mem_warned.replace(true) {
// Newly set, so first time we get here.
this.emit_diagnostic(NonHaltingDiagnostic::NativeCallSharedMem {
#[cfg(target_os = "linux")]
tracing: self::trace::Supervisor::is_enabled(),
#[cfg(not(target_os = "linux"))]
//#[cfg(target_os = "linux")]
//tracing: self::trace::Supervisor::is_enabled(),
//#[cfg(not(target_os = "linux"))]
tracing: false,
});
}

35
src/tools/miri/src/shims/native_lib/trace/parent.rs
View file

@ -20,14 +20,11 @@ const ARCH_MAX_ACCESS_SIZE: usize = 64;
/// The largest arm64 simd instruction operates on 16 bytes.
#[cfg(any(target_arch = "arm", target_arch = "aarch64"))]
const ARCH_MAX_ACCESS_SIZE: usize = 16;
/// The max riscv vector instruction can access 8 consecutive 32-bit values.
#[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))]
const ARCH_MAX_ACCESS_SIZE: usize = 32;
/// The default word size on a given platform, in bytes.
#[cfg(any(target_arch = "x86", target_arch = "arm", target_arch = "riscv32"))]
#[cfg(any(target_arch = "x86", target_arch = "arm"))]
const ARCH_WORD_SIZE: usize = 4;
#[cfg(any(target_arch = "x86_64", target_arch = "aarch64", target_arch = "riscv64"))]
#[cfg(any(target_arch = "x86_64", target_arch = "aarch64"))]
const ARCH_WORD_SIZE: usize = 8;
/// The address of the page set to be edited, initialised to a sentinel null
@ -91,18 +88,6 @@ impl ArchIndependentRegs for libc::user_regs_struct {
fn set_sp(&mut self, sp: usize) { self.sp = sp as _ }
}
#[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))]
#[expect(clippy::as_conversions)]
#[rustfmt::skip]
impl ArchIndependentRegs for libc::user_regs_struct {
#[inline]
fn ip(&self) -> usize { self.pc as _ }
#[inline]
fn set_ip(&mut self, ip: usize) { self.pc = ip as _ }
#[inline]
fn set_sp(&mut self, sp: usize) { self.sp = sp as _ }
}
/// A unified event representing something happening on the child process. Wraps
/// `nix`'s `WaitStatus` and our custom signals so it can all be done with one
/// `match` statement.
@ -341,10 +326,6 @@ fn get_disasm() -> capstone::Capstone {
{cs_pre.arm64().mode(arch::arm64::ArchMode::Arm)}
#[cfg(target_arch = "arm")]
{cs_pre.arm().mode(arch::arm::ArchMode::Arm)}
#[cfg(target_arch = "riscv64")]
{cs_pre.riscv().mode(arch::riscv::ArchMode::RiscV64)}
#[cfg(target_arch = "riscv32")]
{cs_pre.riscv().mode(arch::riscv::ArchMode::RiscV32)}
}
.detail(true)
.build()
@ -501,18 +482,6 @@ fn handle_segfault(
}
_ => (),
},
#[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))]
arch::ArchOperand::RiscVOperand(risc_voperand) => {
match risc_voperand {
arch::riscv::RiscVOperand::Mem(_) => {
// We get basically no info here.
let push = addr..addr.strict_add(size);
acc_events.push(AccessEvent::Read(push.clone()));
acc_events.push(AccessEvent::Write(push));
}
_ => (),
}
}
_ => unimplemented!(),
}
}