Properly fix vext intrinsic tests
This was previously done as part of #1326, but it modified generated code without fixing the root issue in neon.spec.
This commit is contained in:
Amanieu d'Antras
parent
1a2eac5986
commit
e79701c56e
4 changed files with 152 additions and 117 deletions
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@ -20129,18 +20129,18 @@ mod test {
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#[simd_test(enable = "neon")]
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unsafe fn test_vextq_p64() {
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let a: i64x2 = i64x2::new(0, 8);
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let b: i64x2 = i64x2::new(9, 11);
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let e: i64x2 = i64x2::new(8, 9);
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let a: i64x2 = i64x2::new(1, 1);
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let b: i64x2 = i64x2::new(2, 2);
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let e: i64x2 = i64x2::new(1, 2);
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let r: i64x2 = transmute(vextq_p64::<1>(transmute(a), transmute(b)));
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assert_eq!(r, e);
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}
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#[simd_test(enable = "neon")]
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unsafe fn test_vextq_f64() {
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let a: f64x2 = f64x2::new(0., 2.);
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let b: f64x2 = f64x2::new(3., 4.);
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let e: f64x2 = f64x2::new(2., 3.);
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let a: f64x2 = f64x2::new(1., 1.);
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let b: f64x2 = f64x2::new(2., 2.);
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let e: f64x2 = f64x2::new(1., 2.);
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let r: f64x2 = transmute(vextq_f64::<1>(transmute(a), transmute(b)));
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assert_eq!(r, e);
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}
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@ -3904,8 +3904,8 @@ pub unsafe fn vdup_laneq_u64<const N: i32>(a: uint64x2_t) -> uint64x1_t {
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#[inline]
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#[target_feature(enable = "neon")]
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#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
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#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 4))]
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#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(ext, N = 4))]
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#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))]
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#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(ext, N = 7))]
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#[rustc_legacy_const_generics(2)]
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#[cfg_attr(target_arch = "aarch64", stable(feature = "neon_intrinsics", since = "1.59.0"))]
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pub unsafe fn vext_s8<const N: i32>(a: int8x8_t, b: int8x8_t) -> int8x8_t {
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@ -3929,8 +3929,8 @@ pub unsafe fn vext_s8<const N: i32>(a: int8x8_t, b: int8x8_t) -> int8x8_t {
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#[inline]
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#[target_feature(enable = "neon")]
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#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
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#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))]
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#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(ext, N = 3))]
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#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 15))]
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#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(ext, N = 15))]
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#[rustc_legacy_const_generics(2)]
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#[cfg_attr(target_arch = "aarch64", stable(feature = "neon_intrinsics", since = "1.59.0"))]
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pub unsafe fn vextq_s8<const N: i32>(a: int8x16_t, b: int8x16_t) -> int8x16_t {
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@ -3962,8 +3962,8 @@ pub unsafe fn vextq_s8<const N: i32>(a: int8x16_t, b: int8x16_t) -> int8x16_t {
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#[inline]
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#[target_feature(enable = "neon")]
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#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
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#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 2))]
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#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(ext, N = 2))]
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#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))]
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#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(ext, N = 3))]
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#[rustc_legacy_const_generics(2)]
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#[cfg_attr(target_arch = "aarch64", stable(feature = "neon_intrinsics", since = "1.59.0"))]
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pub unsafe fn vext_s16<const N: i32>(a: int16x4_t, b: int16x4_t) -> int16x4_t {
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@ -3983,8 +3983,8 @@ pub unsafe fn vext_s16<const N: i32>(a: int16x4_t, b: int16x4_t) -> int16x4_t {
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#[inline]
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#[target_feature(enable = "neon")]
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#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
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#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))]
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#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(ext, N = 3))]
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#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))]
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#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(ext, N = 7))]
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#[rustc_legacy_const_generics(2)]
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#[cfg_attr(target_arch = "aarch64", stable(feature = "neon_intrinsics", since = "1.59.0"))]
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pub unsafe fn vextq_s16<const N: i32>(a: int16x8_t, b: int16x8_t) -> int16x8_t {
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@ -4048,8 +4048,8 @@ pub unsafe fn vextq_s32<const N: i32>(a: int32x4_t, b: int32x4_t) -> int32x4_t {
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#[inline]
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#[target_feature(enable = "neon")]
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#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
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#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 4))]
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#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(ext, N = 4))]
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#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))]
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#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(ext, N = 7))]
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#[rustc_legacy_const_generics(2)]
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#[cfg_attr(target_arch = "aarch64", stable(feature = "neon_intrinsics", since = "1.59.0"))]
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pub unsafe fn vext_u8<const N: i32>(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
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@ -4073,8 +4073,8 @@ pub unsafe fn vext_u8<const N: i32>(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
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#[inline]
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#[target_feature(enable = "neon")]
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#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
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#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))]
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#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(ext, N = 3))]
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#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 15))]
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#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(ext, N = 15))]
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#[rustc_legacy_const_generics(2)]
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#[cfg_attr(target_arch = "aarch64", stable(feature = "neon_intrinsics", since = "1.59.0"))]
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pub unsafe fn vextq_u8<const N: i32>(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
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@ -4106,8 +4106,8 @@ pub unsafe fn vextq_u8<const N: i32>(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t
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#[inline]
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#[target_feature(enable = "neon")]
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#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
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#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 2))]
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#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(ext, N = 2))]
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#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))]
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#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(ext, N = 3))]
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#[rustc_legacy_const_generics(2)]
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#[cfg_attr(target_arch = "aarch64", stable(feature = "neon_intrinsics", since = "1.59.0"))]
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pub unsafe fn vext_u16<const N: i32>(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
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@ -4127,8 +4127,8 @@ pub unsafe fn vext_u16<const N: i32>(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t
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#[inline]
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#[target_feature(enable = "neon")]
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#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
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#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))]
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#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(ext, N = 3))]
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#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))]
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#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(ext, N = 7))]
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#[rustc_legacy_const_generics(2)]
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#[cfg_attr(target_arch = "aarch64", stable(feature = "neon_intrinsics", since = "1.59.0"))]
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pub unsafe fn vextq_u16<const N: i32>(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
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@ -4192,8 +4192,8 @@ pub unsafe fn vextq_u32<const N: i32>(a: uint32x4_t, b: uint32x4_t) -> uint32x4_
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#[inline]
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#[target_feature(enable = "neon")]
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#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
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#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 4))]
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#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(ext, N = 4))]
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#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))]
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#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(ext, N = 7))]
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#[rustc_legacy_const_generics(2)]
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#[cfg_attr(target_arch = "aarch64", stable(feature = "neon_intrinsics", since = "1.59.0"))]
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pub unsafe fn vext_p8<const N: i32>(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
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@ -4217,8 +4217,8 @@ pub unsafe fn vext_p8<const N: i32>(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
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#[inline]
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#[target_feature(enable = "neon")]
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#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
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#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))]
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#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(ext, N = 3))]
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#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 15))]
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#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(ext, N = 15))]
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#[rustc_legacy_const_generics(2)]
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#[cfg_attr(target_arch = "aarch64", stable(feature = "neon_intrinsics", since = "1.59.0"))]
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pub unsafe fn vextq_p8<const N: i32>(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t {
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@ -4250,8 +4250,8 @@ pub unsafe fn vextq_p8<const N: i32>(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t
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#[inline]
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#[target_feature(enable = "neon")]
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#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
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#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 2))]
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#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(ext, N = 2))]
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#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))]
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#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(ext, N = 3))]
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#[rustc_legacy_const_generics(2)]
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#[cfg_attr(target_arch = "aarch64", stable(feature = "neon_intrinsics", since = "1.59.0"))]
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pub unsafe fn vext_p16<const N: i32>(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t {
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@ -4271,8 +4271,8 @@ pub unsafe fn vext_p16<const N: i32>(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t
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#[inline]
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#[target_feature(enable = "neon")]
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#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
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#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))]
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#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(ext, N = 3))]
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#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))]
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#[cfg_attr(all(test, target_arch = "aarch64"), assert_instr(ext, N = 7))]
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#[rustc_legacy_const_generics(2)]
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#[cfg_attr(target_arch = "aarch64", stable(feature = "neon_intrinsics", since = "1.59.0"))]
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pub unsafe fn vextq_p16<const N: i32>(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t {
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@ -31946,181 +31946,181 @@ mod test {
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#[simd_test(enable = "neon")]
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unsafe fn test_vext_s8() {
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let a: i8x8 = i8x8::new(0, 8, 8, 9, 8, 9, 9, 11);
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let b: i8x8 = i8x8::new(9, 11, 14, 15, 16, 17, 18, 19);
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let e: i8x8 = i8x8::new(8, 9, 9, 11, 9, 11, 14, 15);
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let r: i8x8 = transmute(vext_s8::<4>(transmute(a), transmute(b)));
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let a: i8x8 = i8x8::new(1, 1, 1, 1, 1, 1, 1, 1);
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let b: i8x8 = i8x8::new(2, 2, 2, 2, 2, 2, 2, 2);
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let e: i8x8 = i8x8::new(1, 2, 2, 2, 2, 2, 2, 2);
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let r: i8x8 = transmute(vext_s8::<7>(transmute(a), transmute(b)));
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assert_eq!(r, e);
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}
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#[simd_test(enable = "neon")]
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unsafe fn test_vextq_s8() {
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let a: i8x16 = i8x16::new(0, 8, 8, 9, 8, 9, 9, 11, 8, 9, 9, 11, 9, 11, 14, 15);
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let b: i8x16 = i8x16::new(9, 11, 14, 15, 16, 17, 18, 19, 0, 8, 8, 9, 8, 9, 9, 11);
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let e: i8x16 = i8x16::new(8, 9, 9, 11, 9, 11, 14, 15, 9, 11, 14, 15, 16, 17, 18, 19);
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let r: i8x16 = transmute(vextq_s8::<8>(transmute(a), transmute(b)));
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let a: i8x16 = i8x16::new(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
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let b: i8x16 = i8x16::new(2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2);
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let e: i8x16 = i8x16::new(1, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2);
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let r: i8x16 = transmute(vextq_s8::<15>(transmute(a), transmute(b)));
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assert_eq!(r, e);
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}
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#[simd_test(enable = "neon")]
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unsafe fn test_vext_s16() {
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let a: i16x4 = i16x4::new(0, 8, 8, 9);
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let b: i16x4 = i16x4::new(9, 11, 14, 15);
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let e: i16x4 = i16x4::new(8, 9, 9, 11);
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let r: i16x4 = transmute(vext_s16::<2>(transmute(a), transmute(b)));
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let a: i16x4 = i16x4::new(1, 1, 1, 1);
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let b: i16x4 = i16x4::new(2, 2, 2, 2);
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let e: i16x4 = i16x4::new(1, 2, 2, 2);
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let r: i16x4 = transmute(vext_s16::<3>(transmute(a), transmute(b)));
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assert_eq!(r, e);
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}
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#[simd_test(enable = "neon")]
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unsafe fn test_vextq_s16() {
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let a: i16x8 = i16x8::new(0, 8, 8, 9, 8, 9, 9, 11);
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let b: i16x8 = i16x8::new(9, 11, 14, 15, 16, 17, 18, 19);
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let e: i16x8 = i16x8::new(8, 9, 9, 11, 9, 11, 14, 15);
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let r: i16x8 = transmute(vextq_s16::<4>(transmute(a), transmute(b)));
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let a: i16x8 = i16x8::new(1, 1, 1, 1, 1, 1, 1, 1);
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let b: i16x8 = i16x8::new(2, 2, 2, 2, 2, 2, 2, 2);
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let e: i16x8 = i16x8::new(1, 2, 2, 2, 2, 2, 2, 2);
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let r: i16x8 = transmute(vextq_s16::<7>(transmute(a), transmute(b)));
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assert_eq!(r, e);
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}
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#[simd_test(enable = "neon")]
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unsafe fn test_vext_s32() {
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let a: i32x2 = i32x2::new(0, 8);
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let b: i32x2 = i32x2::new(9, 11);
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let e: i32x2 = i32x2::new(8, 9);
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let a: i32x2 = i32x2::new(1, 1);
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let b: i32x2 = i32x2::new(2, 2);
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let e: i32x2 = i32x2::new(1, 2);
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let r: i32x2 = transmute(vext_s32::<1>(transmute(a), transmute(b)));
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assert_eq!(r, e);
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}
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#[simd_test(enable = "neon")]
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unsafe fn test_vextq_s32() {
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let a: i32x4 = i32x4::new(0, 8, 8, 9);
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let b: i32x4 = i32x4::new(9, 11, 14, 15);
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let e: i32x4 = i32x4::new(8, 9, 9, 11);
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let r: i32x4 = transmute(vextq_s32::<2>(transmute(a), transmute(b)));
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let a: i32x4 = i32x4::new(1, 1, 1, 1);
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let b: i32x4 = i32x4::new(2, 2, 2, 2);
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let e: i32x4 = i32x4::new(1, 2, 2, 2);
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let r: i32x4 = transmute(vextq_s32::<3>(transmute(a), transmute(b)));
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assert_eq!(r, e);
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}
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#[simd_test(enable = "neon")]
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unsafe fn test_vext_u8() {
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let a: u8x8 = u8x8::new(0, 8, 8, 9, 8, 9, 9, 11);
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let b: u8x8 = u8x8::new(9, 11, 14, 15, 16, 17, 18, 19);
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let e: u8x8 = u8x8::new(8, 9, 9, 11, 9, 11, 14, 15);
|
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let r: u8x8 = transmute(vext_u8::<4>(transmute(a), transmute(b)));
|
||||
let a: u8x8 = u8x8::new(1, 1, 1, 1, 1, 1, 1, 1);
|
||||
let b: u8x8 = u8x8::new(2, 2, 2, 2, 2, 2, 2, 2);
|
||||
let e: u8x8 = u8x8::new(1, 2, 2, 2, 2, 2, 2, 2);
|
||||
let r: u8x8 = transmute(vext_u8::<7>(transmute(a), transmute(b)));
|
||||
assert_eq!(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "neon")]
|
||||
unsafe fn test_vextq_u8() {
|
||||
let a: u8x16 = u8x16::new(0, 8, 8, 9, 8, 9, 9, 11, 8, 9, 9, 11, 9, 11, 14, 15);
|
||||
let b: u8x16 = u8x16::new(9, 11, 14, 15, 16, 17, 18, 19, 0, 8, 8, 9, 8, 9, 9, 11);
|
||||
let e: u8x16 = u8x16::new(8, 9, 9, 11, 9, 11, 14, 15, 9, 11, 14, 15, 16, 17, 18, 19);
|
||||
let r: u8x16 = transmute(vextq_u8::<8>(transmute(a), transmute(b)));
|
||||
let a: u8x16 = u8x16::new(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
|
||||
let b: u8x16 = u8x16::new(2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2);
|
||||
let e: u8x16 = u8x16::new(1, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2);
|
||||
let r: u8x16 = transmute(vextq_u8::<15>(transmute(a), transmute(b)));
|
||||
assert_eq!(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "neon")]
|
||||
unsafe fn test_vext_u16() {
|
||||
let a: u16x4 = u16x4::new(0, 8, 8, 9);
|
||||
let b: u16x4 = u16x4::new(9, 11, 14, 15);
|
||||
let e: u16x4 = u16x4::new(8, 9, 9, 11);
|
||||
let r: u16x4 = transmute(vext_u16::<2>(transmute(a), transmute(b)));
|
||||
let a: u16x4 = u16x4::new(1, 1, 1, 1);
|
||||
let b: u16x4 = u16x4::new(2, 2, 2, 2);
|
||||
let e: u16x4 = u16x4::new(1, 2, 2, 2);
|
||||
let r: u16x4 = transmute(vext_u16::<3>(transmute(a), transmute(b)));
|
||||
assert_eq!(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "neon")]
|
||||
unsafe fn test_vextq_u16() {
|
||||
let a: u16x8 = u16x8::new(0, 8, 8, 9, 8, 9, 9, 11);
|
||||
let b: u16x8 = u16x8::new(9, 11, 14, 15, 16, 17, 18, 19);
|
||||
let e: u16x8 = u16x8::new(8, 9, 9, 11, 9, 11, 14, 15);
|
||||
let r: u16x8 = transmute(vextq_u16::<4>(transmute(a), transmute(b)));
|
||||
let a: u16x8 = u16x8::new(1, 1, 1, 1, 1, 1, 1, 1);
|
||||
let b: u16x8 = u16x8::new(2, 2, 2, 2, 2, 2, 2, 2);
|
||||
let e: u16x8 = u16x8::new(1, 2, 2, 2, 2, 2, 2, 2);
|
||||
let r: u16x8 = transmute(vextq_u16::<7>(transmute(a), transmute(b)));
|
||||
assert_eq!(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "neon")]
|
||||
unsafe fn test_vext_u32() {
|
||||
let a: u32x2 = u32x2::new(0, 8);
|
||||
let b: u32x2 = u32x2::new(9, 11);
|
||||
let e: u32x2 = u32x2::new(8, 9);
|
||||
let a: u32x2 = u32x2::new(1, 1);
|
||||
let b: u32x2 = u32x2::new(2, 2);
|
||||
let e: u32x2 = u32x2::new(1, 2);
|
||||
let r: u32x2 = transmute(vext_u32::<1>(transmute(a), transmute(b)));
|
||||
assert_eq!(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "neon")]
|
||||
unsafe fn test_vextq_u32() {
|
||||
let a: u32x4 = u32x4::new(0, 8, 8, 9);
|
||||
let b: u32x4 = u32x4::new(9, 11, 14, 15);
|
||||
let e: u32x4 = u32x4::new(8, 9, 9, 11);
|
||||
let r: u32x4 = transmute(vextq_u32::<2>(transmute(a), transmute(b)));
|
||||
let a: u32x4 = u32x4::new(1, 1, 1, 1);
|
||||
let b: u32x4 = u32x4::new(2, 2, 2, 2);
|
||||
let e: u32x4 = u32x4::new(1, 2, 2, 2);
|
||||
let r: u32x4 = transmute(vextq_u32::<3>(transmute(a), transmute(b)));
|
||||
assert_eq!(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "neon")]
|
||||
unsafe fn test_vext_p8() {
|
||||
let a: i8x8 = i8x8::new(0, 8, 8, 9, 8, 9, 9, 11);
|
||||
let b: i8x8 = i8x8::new(9, 11, 14, 15, 16, 17, 18, 19);
|
||||
let e: i8x8 = i8x8::new(8, 9, 9, 11, 9, 11, 14, 15);
|
||||
let r: i8x8 = transmute(vext_p8::<4>(transmute(a), transmute(b)));
|
||||
let a: i8x8 = i8x8::new(1, 1, 1, 1, 1, 1, 1, 1);
|
||||
let b: i8x8 = i8x8::new(2, 2, 2, 2, 2, 2, 2, 2);
|
||||
let e: i8x8 = i8x8::new(1, 2, 2, 2, 2, 2, 2, 2);
|
||||
let r: i8x8 = transmute(vext_p8::<7>(transmute(a), transmute(b)));
|
||||
assert_eq!(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "neon")]
|
||||
unsafe fn test_vextq_p8() {
|
||||
let a: i8x16 = i8x16::new(0, 8, 8, 9, 8, 9, 9, 11, 8, 9, 9, 11, 9, 11, 14, 15);
|
||||
let b: i8x16 = i8x16::new(9, 11, 14, 15, 16, 17, 18, 19, 0, 8, 8, 9, 8, 9, 9, 11);
|
||||
let e: i8x16 = i8x16::new(8, 9, 9, 11, 9, 11, 14, 15, 9, 11, 14, 15, 16, 17, 18, 19);
|
||||
let r: i8x16 = transmute(vextq_p8::<8>(transmute(a), transmute(b)));
|
||||
let a: i8x16 = i8x16::new(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
|
||||
let b: i8x16 = i8x16::new(2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2);
|
||||
let e: i8x16 = i8x16::new(1, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2);
|
||||
let r: i8x16 = transmute(vextq_p8::<15>(transmute(a), transmute(b)));
|
||||
assert_eq!(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "neon")]
|
||||
unsafe fn test_vext_p16() {
|
||||
let a: i16x4 = i16x4::new(0, 8, 8, 9);
|
||||
let b: i16x4 = i16x4::new(9, 11, 14, 15);
|
||||
let e: i16x4 = i16x4::new(8, 9, 9, 11);
|
||||
let r: i16x4 = transmute(vext_p16::<2>(transmute(a), transmute(b)));
|
||||
let a: i16x4 = i16x4::new(1, 1, 1, 1);
|
||||
let b: i16x4 = i16x4::new(2, 2, 2, 2);
|
||||
let e: i16x4 = i16x4::new(1, 2, 2, 2);
|
||||
let r: i16x4 = transmute(vext_p16::<3>(transmute(a), transmute(b)));
|
||||
assert_eq!(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "neon")]
|
||||
unsafe fn test_vextq_p16() {
|
||||
let a: i16x8 = i16x8::new(0, 8, 8, 9, 8, 9, 9, 11);
|
||||
let b: i16x8 = i16x8::new(9, 11, 14, 15, 16, 17, 18, 19);
|
||||
let e: i16x8 = i16x8::new(8, 9, 9, 11, 9, 11, 14, 15);
|
||||
let r: i16x8 = transmute(vextq_p16::<4>(transmute(a), transmute(b)));
|
||||
let a: i16x8 = i16x8::new(1, 1, 1, 1, 1, 1, 1, 1);
|
||||
let b: i16x8 = i16x8::new(2, 2, 2, 2, 2, 2, 2, 2);
|
||||
let e: i16x8 = i16x8::new(1, 2, 2, 2, 2, 2, 2, 2);
|
||||
let r: i16x8 = transmute(vextq_p16::<7>(transmute(a), transmute(b)));
|
||||
assert_eq!(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "neon")]
|
||||
unsafe fn test_vextq_s64() {
|
||||
let a: i64x2 = i64x2::new(0, 8);
|
||||
let b: i64x2 = i64x2::new(9, 11);
|
||||
let e: i64x2 = i64x2::new(8, 9);
|
||||
let a: i64x2 = i64x2::new(1, 1);
|
||||
let b: i64x2 = i64x2::new(2, 2);
|
||||
let e: i64x2 = i64x2::new(1, 2);
|
||||
let r: i64x2 = transmute(vextq_s64::<1>(transmute(a), transmute(b)));
|
||||
assert_eq!(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "neon")]
|
||||
unsafe fn test_vextq_u64() {
|
||||
let a: u64x2 = u64x2::new(0, 8);
|
||||
let b: u64x2 = u64x2::new(9, 11);
|
||||
let e: u64x2 = u64x2::new(8, 9);
|
||||
let a: u64x2 = u64x2::new(1, 1);
|
||||
let b: u64x2 = u64x2::new(2, 2);
|
||||
let e: u64x2 = u64x2::new(1, 2);
|
||||
let r: u64x2 = transmute(vextq_u64::<1>(transmute(a), transmute(b)));
|
||||
assert_eq!(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "neon")]
|
||||
unsafe fn test_vext_f32() {
|
||||
let a: f32x2 = f32x2::new(0., 2.);
|
||||
let b: f32x2 = f32x2::new(3., 4.);
|
||||
let e: f32x2 = f32x2::new(2., 3.);
|
||||
let a: f32x2 = f32x2::new(1., 1.);
|
||||
let b: f32x2 = f32x2::new(2., 2.);
|
||||
let e: f32x2 = f32x2::new(1., 2.);
|
||||
let r: f32x2 = transmute(vext_f32::<1>(transmute(a), transmute(b)));
|
||||
assert_eq!(r, e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "neon")]
|
||||
unsafe fn test_vextq_f32() {
|
||||
let a: f32x4 = f32x4::new(0., 2., 2., 3.);
|
||||
let b: f32x4 = f32x4::new(3., 4., 5., 6.);
|
||||
let e: f32x4 = f32x4::new(2., 3., 3., 4.);
|
||||
let r: f32x4 = transmute(vextq_f32::<2>(transmute(a), transmute(b)));
|
||||
let a: f32x4 = f32x4::new(1., 1., 1., 1.);
|
||||
let b: f32x4 = f32x4::new(2., 2., 2., 2.);
|
||||
let e: f32x4 = f32x4::new(1., 2., 2., 2.);
|
||||
let r: f32x4 = transmute(vextq_f32::<3>(transmute(a), transmute(b)));
|
||||
assert_eq!(r, e);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -1570,10 +1570,10 @@ name = vext
|
|||
constn = N
|
||||
multi_fn = static_assert_imm-out_exp_len-N
|
||||
multi_fn = matchn-out_exp_len-N, simd_shuffle-out_len-!, a, b, {asc-n-out_len}
|
||||
a = 0, 8, 8, 9, 8, 9, 9, 11, 8, 9, 9, 11, 9, 11, 14, 15
|
||||
b = 9, 11, 14, 15, 16, 17, 18, 19, 0, 8, 8, 9, 8, 9, 9, 11
|
||||
n = HFLEN
|
||||
validate 8, 9, 9, 11, 9, 11, 14, 15, 9, 11, 14, 15, 16, 17, 18, 19
|
||||
a = 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1
|
||||
b = 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2
|
||||
n = LEN_M1
|
||||
validate 1, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2
|
||||
|
||||
arm = "vext.8"
|
||||
aarch64 = ext
|
||||
|
|
@ -1584,10 +1584,10 @@ name = vext
|
|||
constn = N
|
||||
multi_fn = static_assert_imm-out_exp_len-N
|
||||
multi_fn = matchn-out_exp_len-N, simd_shuffle-out_len-!, a, b, {asc-n-out_len}
|
||||
a = 0, 8, 8, 9, 8, 9, 9, 11, 8, 9, 9, 11, 9, 11, 14, 15
|
||||
b = 9, 11, 14, 15, 16, 17, 18, 19, 0, 8, 8, 9, 8, 9, 9, 11
|
||||
n = HFLEN
|
||||
validate 8, 9, 9, 11, 9, 11, 14, 15, 9, 11, 14, 15, 16, 17, 18, 19
|
||||
a = 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1
|
||||
b = 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2
|
||||
n = LEN_M1
|
||||
validate 1, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2
|
||||
|
||||
aarch64 = ext
|
||||
generate poly64x2_t
|
||||
|
|
@ -1600,10 +1600,10 @@ name = vext
|
|||
constn = N
|
||||
multi_fn = static_assert_imm-out_exp_len-N
|
||||
multi_fn = matchn-out_exp_len-N, simd_shuffle-out_len-!, a, b, {asc-n-out_len}
|
||||
a = 0., 2., 2., 3.
|
||||
b = 3., 4., 5., 6.,
|
||||
n = HFLEN
|
||||
validate 2., 3., 3., 4.
|
||||
a = 1., 1., 1., 1.
|
||||
b = 2., 2., 2., 2.,
|
||||
n = LEN_M1
|
||||
validate 1., 2., 2., 2.
|
||||
|
||||
aarch64 = ext
|
||||
generate float64x2_t
|
||||
|
|
|
|||
|
|
@ -856,6 +856,40 @@ fn type_len_str(t: &str) -> &'static str {
|
|||
}
|
||||
}
|
||||
|
||||
fn type_len_minus_one_str(t: &str) -> &'static str {
|
||||
match t {
|
||||
"int8x8_t" => "7",
|
||||
"int8x16_t" => "15",
|
||||
"int16x4_t" => "3",
|
||||
"int16x8_t" => "7",
|
||||
"int32x2_t" => "1",
|
||||
"int32x4_t" => "3",
|
||||
"int64x1_t" => "0",
|
||||
"int64x2_t" => "1",
|
||||
"uint8x8_t" => "7",
|
||||
"uint8x16_t" => "15",
|
||||
"uint16x4_t" => "3",
|
||||
"uint16x8_t" => "7",
|
||||
"uint32x2_t" => "1",
|
||||
"uint32x4_t" => "3",
|
||||
"uint64x1_t" => "0",
|
||||
"uint64x2_t" => "1",
|
||||
"float16x4_t" => "3",
|
||||
"float16x8_t" => "7",
|
||||
"float32x2_t" => "1",
|
||||
"float32x4_t" => "3",
|
||||
"float64x1_t" => "0",
|
||||
"float64x2_t" => "1",
|
||||
"poly8x8_t" => "7",
|
||||
"poly8x16_t" => "15",
|
||||
"poly16x4_t" => "3",
|
||||
"poly16x8_t" => "7",
|
||||
"poly64x1_t" => "0",
|
||||
"poly64x2_t" => "1",
|
||||
_ => panic!("unknown type: {}", t),
|
||||
}
|
||||
}
|
||||
|
||||
fn type_half_len_str(t: &str) -> &'static str {
|
||||
match t {
|
||||
"int8x8_t" => "4",
|
||||
|
|
@ -901,6 +935,7 @@ fn map_val<'v>(t: &str, v: &'v str) -> &'v str {
|
|||
"BITS_M1" => bits_minus_one(t),
|
||||
"HFBITS" => half_bits(t),
|
||||
"LEN" => type_len_str(t),
|
||||
"LEN_M1" => type_len_minus_one_str(t),
|
||||
"HFLEN" => type_half_len_str(t),
|
||||
o => o,
|
||||
}
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue