Merge pull request rust-lang/libm#493 from tgross35/fma-sign
fma: Ensure zero has the correct sign
This commit is contained in:
commit
f070e65e4f
3 changed files with 4 additions and 47 deletions
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@ -558,48 +558,5 @@ impl MaybeOverride<(f64, i32)> for SpecialCase {}
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#[cfg(f128_enabled)]
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impl MaybeOverride<(f128, i32)> for SpecialCase {}
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impl MaybeOverride<(f32, f32, f32)> for SpecialCase {
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fn check_float<F: Float>(
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input: (f32, f32, f32),
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actual: F,
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expected: F,
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ctx: &CheckCtx,
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) -> CheckAction {
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ternop_common(input, actual, expected, ctx)
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}
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}
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impl MaybeOverride<(f64, f64, f64)> for SpecialCase {
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fn check_float<F: Float>(
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input: (f64, f64, f64),
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actual: F,
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expected: F,
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ctx: &CheckCtx,
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) -> CheckAction {
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ternop_common(input, actual, expected, ctx)
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}
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}
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// F1 and F2 are always the same type, this is just to please generics
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fn ternop_common<F1: Float, F2: Float>(
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input: (F1, F1, F1),
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actual: F2,
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expected: F2,
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ctx: &CheckCtx,
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) -> CheckAction {
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// FIXME(fma): 754-2020 says "When the exact result of (a × b) + c is non-zero yet the result
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// of fusedMultiplyAdd is zero because of rounding, the zero result takes the sign of the
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// exact result". Our implementation returns the wrong sign:
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// fma(5e-324, -5e-324, 0.0) = 0.0 (should be -0.0)
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if ctx.base_name == BaseName::Fma
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&& (input.0.is_sign_negative() ^ input.1.is_sign_negative())
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&& input.0 != F1::ZERO
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&& input.1 != F1::ZERO
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&& input.2.biteq(F1::ZERO)
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&& expected.biteq(F2::NEG_ZERO)
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&& actual.biteq(F2::ZERO)
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{
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return XFAIL("fma sign");
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}
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DEFAULT
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}
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impl MaybeOverride<(f32, f32, f32)> for SpecialCase {}
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impl MaybeOverride<(f64, f64, f64)> for SpecialCase {}
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@ -1 +1 @@
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Subproject commit 0784374d561435f7c787a555aeab8ede699ed298
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Subproject commit 61399d4bd02ae1ec03068445aa7ffe9174466bfd
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@ -31,7 +31,7 @@ where
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if nz.e >= ZEROINFNAN {
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if nz.e > ZEROINFNAN {
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/* z==0 */
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return x * y + z;
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return x * y;
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}
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return z;
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}
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