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sse3: _mm_loaddup_pd and sse2: _mm_load1_pd

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gwenn 2017-09-30 14:01:13 +02:00 • committed by Andrew Gallant
parent 4cbb838e2e
commit f0f5108a98
2 changed files with 34 additions and 0 deletions
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17
library/stdarch/src/x86/sse2.rs
View file

@ -1762,6 +1762,16 @@ pub unsafe fn _mm_store_pd(mem_addr: *mut f64, a: f64x2) {
*(mem_addr as *mut f64x2) = a;
}
/// Load a double-precision (64-bit) floating-point element from memory
/// into both elements of returned vector.
#[inline(always)]
#[target_feature = "+sse2"]
#[cfg_attr(test, assert_instr(movddup))]
pub unsafe fn _mm_load1_pd(mem_addr: *const f64) -> f64x2 {
let d = *mem_addr;
f64x2::new(d, d)
}
#[allow(improper_ctypes)]
extern {
#[link_name = "llvm.x86.sse2.pause"]
@ -3463,4 +3473,11 @@ mod tests {
let r = sse2::_mm_cvtpd_epi32(f64x2::new(f64::NAN, f64::NAN));
assert_eq!(r, i32x4::new(i32::MIN, i32::MIN, 0, 0));
}
#[simd_test = "sse2"]
unsafe fn _mm_load1_pd() {
let d = -5.0;
let r = sse2::_mm_load1_pd(&d);
assert_eq!(r, f64x2::new(d, d));
}
}

17
library/stdarch/src/x86/sse3.rs
View file

@ -78,6 +78,16 @@ pub unsafe fn _mm_movedup_pd(a: f64x2) -> f64x2 {
simd_shuffle2(a, a, [0, 0])
}
/// Load a double-precision (64-bit) floating-point element from memory
/// into both elements of return vector.
#[inline(always)]
#[target_feature = "+sse3"]
#[cfg_attr(test, assert_instr(movddup))]
pub unsafe fn _mm_loaddup_pd(mem_addr: *const f64) -> f64x2 {
use x86::sse2::_mm_load1_pd;
_mm_load1_pd(mem_addr)
}
/// Duplicate odd-indexed single-precision (32-bit) floating-point elements
/// from `a`.
#[inline(always)]
@ -197,4 +207,11 @@ mod tests {
let r = sse3::_mm_moveldup_ps(a);
assert_eq!(r, f32x4::new(-1.0, -1.0, 0.0, 0.0));
}
#[simd_test = "sse3"]
unsafe fn _mm_loaddup_pd() {
let d = -5.0;
let r = sse3::_mm_loaddup_pd(&d);
assert_eq!(r, f64x2::new(d, d));
}
}