diff --git a/src/intrinsic/archs.rs b/src/intrinsic/archs.rs index 026ed7c6c7ca..427ca77e9d0b 100644 --- a/src/intrinsic/archs.rs +++ b/src/intrinsic/archs.rs @@ -1,6 +1,35 @@ // File generated by `rustc_codegen_gcc/tools/generate_intrinsics.py` // DO NOT EDIT IT! match name { + // AMDGPU + "llvm.AMDGPU.div.fixup.f32" => "__builtin_amdgpu_div_fixup", + "llvm.AMDGPU.div.fixup.f64" => "__builtin_amdgpu_div_fixup", + "llvm.AMDGPU.div.fixup.v2f64" => "__builtin_amdgpu_div_fixup", + "llvm.AMDGPU.div.fixup.v4f32" => "__builtin_amdgpu_div_fixup", + "llvm.AMDGPU.div.fmas.f32" => "__builtin_amdgpu_div_fmas", + "llvm.AMDGPU.div.fmas.f64" => "__builtin_amdgpu_div_fmas", + "llvm.AMDGPU.div.fmas.v2f64" => "__builtin_amdgpu_div_fmas", + "llvm.AMDGPU.div.fmas.v4f32" => "__builtin_amdgpu_div_fmas", + "llvm.AMDGPU.ldexp.f32" => "__builtin_amdgpu_ldexp", + "llvm.AMDGPU.ldexp.f64" => "__builtin_amdgpu_ldexp", + "llvm.AMDGPU.ldexp.v2f64" => "__builtin_amdgpu_ldexp", + "llvm.AMDGPU.ldexp.v4f32" => "__builtin_amdgpu_ldexp", + "llvm.AMDGPU.rcp.f32" => "__builtin_amdgpu_rcp", + "llvm.AMDGPU.rcp.f64" => "__builtin_amdgpu_rcp", + "llvm.AMDGPU.rcp.v2f64" => "__builtin_amdgpu_rcp", + "llvm.AMDGPU.rcp.v4f32" => "__builtin_amdgpu_rcp", + "llvm.AMDGPU.rsq.clamped.f32" => "__builtin_amdgpu_rsq_clamped", + "llvm.AMDGPU.rsq.clamped.f64" => "__builtin_amdgpu_rsq_clamped", + "llvm.AMDGPU.rsq.clamped.v2f64" => "__builtin_amdgpu_rsq_clamped", + "llvm.AMDGPU.rsq.clamped.v4f32" => "__builtin_amdgpu_rsq_clamped", + "llvm.AMDGPU.rsq.f32" => "__builtin_amdgpu_rsq", + "llvm.AMDGPU.rsq.f64" => "__builtin_amdgpu_rsq", + "llvm.AMDGPU.rsq.v2f64" => "__builtin_amdgpu_rsq", + "llvm.AMDGPU.rsq.v4f32" => "__builtin_amdgpu_rsq", + "llvm.AMDGPU.trig.preop.f32" => "__builtin_amdgpu_trig_preop", + "llvm.AMDGPU.trig.preop.f64" => "__builtin_amdgpu_trig_preop", + "llvm.AMDGPU.trig.preop.v2f64" => "__builtin_amdgpu_trig_preop", + "llvm.AMDGPU.trig.preop.v4f32" => "__builtin_amdgpu_trig_preop", // aarch64 "llvm.aarch64.dmb" => "__builtin_arm_dmb", "llvm.aarch64.dsb" => "__builtin_arm_dsb", @@ -91,8 +120,8 @@ match name { "llvm.amdgcn.s.setprio" => "__builtin_amdgcn_s_setprio", "llvm.amdgcn.s.setreg" => "__builtin_amdgcn_s_setreg", "llvm.amdgcn.s.sleep" => "__builtin_amdgcn_s_decperflevel", - "llvm.amdgcn.s.sleep" => "__builtin_amdgcn_s_incperflevel", - "llvm.amdgcn.s.sleep" => "__builtin_amdgcn_s_sleep", + // [DUPLICATE]: "llvm.amdgcn.s.sleep" => "__builtin_amdgcn_s_incperflevel", + // [DUPLICATE]: "llvm.amdgcn.s.sleep" => "__builtin_amdgcn_s_sleep", "llvm.amdgcn.s.waitcnt" => "__builtin_amdgcn_s_waitcnt", "llvm.amdgcn.sad.hi.u8" => "__builtin_amdgcn_sad_hi_u8", "llvm.amdgcn.sad.u16" => "__builtin_amdgcn_sad_u16", @@ -123,6 +152,8 @@ match name { "llvm.arm.ldcl" => "__builtin_arm_ldcl", "llvm.arm.mcr" => "__builtin_arm_mcr", "llvm.arm.mcr2" => "__builtin_arm_mcr2", + "llvm.arm.mcrr" => "__builtin_arm_mcrr", + "llvm.arm.mcrr2" => "__builtin_arm_mcrr2", "llvm.arm.mrc" => "__builtin_arm_mrc", "llvm.arm.mrc2" => "__builtin_arm_mrc2", "llvm.arm.qadd" => "__builtin_arm_qadd", @@ -179,6 +210,7 @@ match name { "llvm.arm.stcl" => "__builtin_arm_stcl", "llvm.arm.sxtab16" => "__builtin_arm_sxtab16", "llvm.arm.sxtb16" => "__builtin_arm_sxtb16", + "llvm.arm.thread.pointer" => "__builtin_thread_pointer", "llvm.arm.uadd16" => "__builtin_arm_uadd16", "llvm.arm.uadd8" => "__builtin_arm_uadd8", "llvm.arm.uasx" => "__builtin_arm_uasx", @@ -214,6 +246,862 @@ match name { "llvm.bpf.preserve.field.info" => "__builtin_bpf_preserve_field_info", "llvm.bpf.preserve.type.info" => "__builtin_bpf_preserve_type_info", "llvm.bpf.pseudo" => "__builtin_bpf_pseudo", + // cuda + "llvm.cuda.syncthreads" => "__syncthreads", + // hexagon + "llvm.hexagon.A2.abs" => "__builtin_HEXAGON_A2_abs", + "llvm.hexagon.A2.absp" => "__builtin_HEXAGON_A2_absp", + "llvm.hexagon.A2.abssat" => "__builtin_HEXAGON_A2_abssat", + "llvm.hexagon.A2.add" => "__builtin_HEXAGON_A2_add", + "llvm.hexagon.A2.addh.h16.hh" => "__builtin_HEXAGON_A2_addh_h16_hh", + "llvm.hexagon.A2.addh.h16.hl" => "__builtin_HEXAGON_A2_addh_h16_hl", + "llvm.hexagon.A2.addh.h16.lh" => "__builtin_HEXAGON_A2_addh_h16_lh", + "llvm.hexagon.A2.addh.h16.ll" => "__builtin_HEXAGON_A2_addh_h16_ll", + "llvm.hexagon.A2.addh.h16.sat.hh" => "__builtin_HEXAGON_A2_addh_h16_sat_hh", + "llvm.hexagon.A2.addh.h16.sat.hl" => "__builtin_HEXAGON_A2_addh_h16_sat_hl", + "llvm.hexagon.A2.addh.h16.sat.lh" => "__builtin_HEXAGON_A2_addh_h16_sat_lh", + "llvm.hexagon.A2.addh.h16.sat.ll" => "__builtin_HEXAGON_A2_addh_h16_sat_ll", + "llvm.hexagon.A2.addh.l16.hl" => "__builtin_HEXAGON_A2_addh_l16_hl", + "llvm.hexagon.A2.addh.l16.ll" => "__builtin_HEXAGON_A2_addh_l16_ll", + "llvm.hexagon.A2.addh.l16.sat.hl" => "__builtin_HEXAGON_A2_addh_l16_sat_hl", + "llvm.hexagon.A2.addh.l16.sat.ll" => "__builtin_HEXAGON_A2_addh_l16_sat_ll", + "llvm.hexagon.A2.addi" => "__builtin_HEXAGON_A2_addi", + "llvm.hexagon.A2.addp" => "__builtin_HEXAGON_A2_addp", + "llvm.hexagon.A2.addpsat" => "__builtin_HEXAGON_A2_addpsat", + "llvm.hexagon.A2.addsat" => "__builtin_HEXAGON_A2_addsat", + "llvm.hexagon.A2.addsp" => "__builtin_HEXAGON_A2_addsp", + "llvm.hexagon.A2.and" => "__builtin_HEXAGON_A2_and", + "llvm.hexagon.A2.andir" => "__builtin_HEXAGON_A2_andir", + "llvm.hexagon.A2.andp" => "__builtin_HEXAGON_A2_andp", + "llvm.hexagon.A2.aslh" => "__builtin_HEXAGON_A2_aslh", + "llvm.hexagon.A2.asrh" => "__builtin_HEXAGON_A2_asrh", + "llvm.hexagon.A2.combine.hh" => "__builtin_HEXAGON_A2_combine_hh", + "llvm.hexagon.A2.combine.hl" => "__builtin_HEXAGON_A2_combine_hl", + "llvm.hexagon.A2.combine.lh" => "__builtin_HEXAGON_A2_combine_lh", + "llvm.hexagon.A2.combine.ll" => "__builtin_HEXAGON_A2_combine_ll", + "llvm.hexagon.A2.combineii" => "__builtin_HEXAGON_A2_combineii", + "llvm.hexagon.A2.combinew" => "__builtin_HEXAGON_A2_combinew", + "llvm.hexagon.A2.max" => "__builtin_HEXAGON_A2_max", + "llvm.hexagon.A2.maxp" => "__builtin_HEXAGON_A2_maxp", + "llvm.hexagon.A2.maxu" => "__builtin_HEXAGON_A2_maxu", + "llvm.hexagon.A2.maxup" => "__builtin_HEXAGON_A2_maxup", + "llvm.hexagon.A2.min" => "__builtin_HEXAGON_A2_min", + "llvm.hexagon.A2.minp" => "__builtin_HEXAGON_A2_minp", + "llvm.hexagon.A2.minu" => "__builtin_HEXAGON_A2_minu", + "llvm.hexagon.A2.minup" => "__builtin_HEXAGON_A2_minup", + "llvm.hexagon.A2.neg" => "__builtin_HEXAGON_A2_neg", + "llvm.hexagon.A2.negp" => "__builtin_HEXAGON_A2_negp", + "llvm.hexagon.A2.negsat" => "__builtin_HEXAGON_A2_negsat", + "llvm.hexagon.A2.not" => "__builtin_HEXAGON_A2_not", + "llvm.hexagon.A2.notp" => "__builtin_HEXAGON_A2_notp", + "llvm.hexagon.A2.or" => "__builtin_HEXAGON_A2_or", + "llvm.hexagon.A2.orir" => "__builtin_HEXAGON_A2_orir", + "llvm.hexagon.A2.orp" => "__builtin_HEXAGON_A2_orp", + "llvm.hexagon.A2.roundsat" => "__builtin_HEXAGON_A2_roundsat", + "llvm.hexagon.A2.sat" => "__builtin_HEXAGON_A2_sat", + "llvm.hexagon.A2.satb" => "__builtin_HEXAGON_A2_satb", + "llvm.hexagon.A2.sath" => "__builtin_HEXAGON_A2_sath", + "llvm.hexagon.A2.satub" => "__builtin_HEXAGON_A2_satub", + "llvm.hexagon.A2.satuh" => "__builtin_HEXAGON_A2_satuh", + "llvm.hexagon.A2.sub" => "__builtin_HEXAGON_A2_sub", + "llvm.hexagon.A2.subh.h16.hh" => "__builtin_HEXAGON_A2_subh_h16_hh", + "llvm.hexagon.A2.subh.h16.hl" => "__builtin_HEXAGON_A2_subh_h16_hl", + "llvm.hexagon.A2.subh.h16.lh" => "__builtin_HEXAGON_A2_subh_h16_lh", + "llvm.hexagon.A2.subh.h16.ll" => "__builtin_HEXAGON_A2_subh_h16_ll", + "llvm.hexagon.A2.subh.h16.sat.hh" => "__builtin_HEXAGON_A2_subh_h16_sat_hh", + "llvm.hexagon.A2.subh.h16.sat.hl" => "__builtin_HEXAGON_A2_subh_h16_sat_hl", + "llvm.hexagon.A2.subh.h16.sat.lh" => "__builtin_HEXAGON_A2_subh_h16_sat_lh", + "llvm.hexagon.A2.subh.h16.sat.ll" => "__builtin_HEXAGON_A2_subh_h16_sat_ll", + "llvm.hexagon.A2.subh.l16.hl" => "__builtin_HEXAGON_A2_subh_l16_hl", + "llvm.hexagon.A2.subh.l16.ll" => "__builtin_HEXAGON_A2_subh_l16_ll", + "llvm.hexagon.A2.subh.l16.sat.hl" => "__builtin_HEXAGON_A2_subh_l16_sat_hl", + "llvm.hexagon.A2.subh.l16.sat.ll" => "__builtin_HEXAGON_A2_subh_l16_sat_ll", + "llvm.hexagon.A2.subp" => "__builtin_HEXAGON_A2_subp", + "llvm.hexagon.A2.subri" => "__builtin_HEXAGON_A2_subri", + "llvm.hexagon.A2.subsat" => "__builtin_HEXAGON_A2_subsat", + "llvm.hexagon.A2.svaddh" => "__builtin_HEXAGON_A2_svaddh", + "llvm.hexagon.A2.svaddhs" => "__builtin_HEXAGON_A2_svaddhs", + "llvm.hexagon.A2.svadduhs" => "__builtin_HEXAGON_A2_svadduhs", + "llvm.hexagon.A2.svavgh" => "__builtin_HEXAGON_A2_svavgh", + "llvm.hexagon.A2.svavghs" => "__builtin_HEXAGON_A2_svavghs", + "llvm.hexagon.A2.svnavgh" => "__builtin_HEXAGON_A2_svnavgh", + "llvm.hexagon.A2.svsubh" => "__builtin_HEXAGON_A2_svsubh", + "llvm.hexagon.A2.svsubhs" => "__builtin_HEXAGON_A2_svsubhs", + "llvm.hexagon.A2.svsubuhs" => "__builtin_HEXAGON_A2_svsubuhs", + "llvm.hexagon.A2.swiz" => "__builtin_HEXAGON_A2_swiz", + "llvm.hexagon.A2.sxtb" => "__builtin_HEXAGON_A2_sxtb", + "llvm.hexagon.A2.sxth" => "__builtin_HEXAGON_A2_sxth", + "llvm.hexagon.A2.sxtw" => "__builtin_HEXAGON_A2_sxtw", + "llvm.hexagon.A2.tfr" => "__builtin_HEXAGON_A2_tfr", + "llvm.hexagon.A2.tfrih" => "__builtin_HEXAGON_A2_tfrih", + "llvm.hexagon.A2.tfril" => "__builtin_HEXAGON_A2_tfril", + "llvm.hexagon.A2.tfrp" => "__builtin_HEXAGON_A2_tfrp", + "llvm.hexagon.A2.tfrpi" => "__builtin_HEXAGON_A2_tfrpi", + "llvm.hexagon.A2.tfrsi" => "__builtin_HEXAGON_A2_tfrsi", + "llvm.hexagon.A2.vabsh" => "__builtin_HEXAGON_A2_vabsh", + "llvm.hexagon.A2.vabshsat" => "__builtin_HEXAGON_A2_vabshsat", + "llvm.hexagon.A2.vabsw" => "__builtin_HEXAGON_A2_vabsw", + "llvm.hexagon.A2.vabswsat" => "__builtin_HEXAGON_A2_vabswsat", + "llvm.hexagon.A2.vaddb.map" => "__builtin_HEXAGON_A2_vaddb_map", + "llvm.hexagon.A2.vaddh" => "__builtin_HEXAGON_A2_vaddh", + "llvm.hexagon.A2.vaddhs" => "__builtin_HEXAGON_A2_vaddhs", + "llvm.hexagon.A2.vaddub" => "__builtin_HEXAGON_A2_vaddub", + "llvm.hexagon.A2.vaddubs" => "__builtin_HEXAGON_A2_vaddubs", + "llvm.hexagon.A2.vadduhs" => "__builtin_HEXAGON_A2_vadduhs", + "llvm.hexagon.A2.vaddw" => "__builtin_HEXAGON_A2_vaddw", + "llvm.hexagon.A2.vaddws" => "__builtin_HEXAGON_A2_vaddws", + "llvm.hexagon.A2.vavgh" => "__builtin_HEXAGON_A2_vavgh", + "llvm.hexagon.A2.vavghcr" => "__builtin_HEXAGON_A2_vavghcr", + "llvm.hexagon.A2.vavghr" => "__builtin_HEXAGON_A2_vavghr", + "llvm.hexagon.A2.vavgub" => "__builtin_HEXAGON_A2_vavgub", + "llvm.hexagon.A2.vavgubr" => "__builtin_HEXAGON_A2_vavgubr", + "llvm.hexagon.A2.vavguh" => "__builtin_HEXAGON_A2_vavguh", + "llvm.hexagon.A2.vavguhr" => "__builtin_HEXAGON_A2_vavguhr", + "llvm.hexagon.A2.vavguw" => "__builtin_HEXAGON_A2_vavguw", + "llvm.hexagon.A2.vavguwr" => "__builtin_HEXAGON_A2_vavguwr", + "llvm.hexagon.A2.vavgw" => "__builtin_HEXAGON_A2_vavgw", + "llvm.hexagon.A2.vavgwcr" => "__builtin_HEXAGON_A2_vavgwcr", + "llvm.hexagon.A2.vavgwr" => "__builtin_HEXAGON_A2_vavgwr", + "llvm.hexagon.A2.vcmpbeq" => "__builtin_HEXAGON_A2_vcmpbeq", + "llvm.hexagon.A2.vcmpbgtu" => "__builtin_HEXAGON_A2_vcmpbgtu", + "llvm.hexagon.A2.vcmpheq" => "__builtin_HEXAGON_A2_vcmpheq", + "llvm.hexagon.A2.vcmphgt" => "__builtin_HEXAGON_A2_vcmphgt", + "llvm.hexagon.A2.vcmphgtu" => "__builtin_HEXAGON_A2_vcmphgtu", + "llvm.hexagon.A2.vcmpweq" => "__builtin_HEXAGON_A2_vcmpweq", + "llvm.hexagon.A2.vcmpwgt" => "__builtin_HEXAGON_A2_vcmpwgt", + "llvm.hexagon.A2.vcmpwgtu" => "__builtin_HEXAGON_A2_vcmpwgtu", + "llvm.hexagon.A2.vconj" => "__builtin_HEXAGON_A2_vconj", + "llvm.hexagon.A2.vmaxb" => "__builtin_HEXAGON_A2_vmaxb", + "llvm.hexagon.A2.vmaxh" => "__builtin_HEXAGON_A2_vmaxh", + "llvm.hexagon.A2.vmaxub" => "__builtin_HEXAGON_A2_vmaxub", + "llvm.hexagon.A2.vmaxuh" => "__builtin_HEXAGON_A2_vmaxuh", + "llvm.hexagon.A2.vmaxuw" => "__builtin_HEXAGON_A2_vmaxuw", + "llvm.hexagon.A2.vmaxw" => "__builtin_HEXAGON_A2_vmaxw", + "llvm.hexagon.A2.vminb" => "__builtin_HEXAGON_A2_vminb", + "llvm.hexagon.A2.vminh" => "__builtin_HEXAGON_A2_vminh", + "llvm.hexagon.A2.vminub" => "__builtin_HEXAGON_A2_vminub", + "llvm.hexagon.A2.vminuh" => "__builtin_HEXAGON_A2_vminuh", + "llvm.hexagon.A2.vminuw" => "__builtin_HEXAGON_A2_vminuw", + "llvm.hexagon.A2.vminw" => "__builtin_HEXAGON_A2_vminw", + "llvm.hexagon.A2.vnavgh" => "__builtin_HEXAGON_A2_vnavgh", + "llvm.hexagon.A2.vnavghcr" => "__builtin_HEXAGON_A2_vnavghcr", + "llvm.hexagon.A2.vnavghr" => "__builtin_HEXAGON_A2_vnavghr", + "llvm.hexagon.A2.vnavgw" => "__builtin_HEXAGON_A2_vnavgw", + "llvm.hexagon.A2.vnavgwcr" => "__builtin_HEXAGON_A2_vnavgwcr", + "llvm.hexagon.A2.vnavgwr" => "__builtin_HEXAGON_A2_vnavgwr", + "llvm.hexagon.A2.vraddub" => "__builtin_HEXAGON_A2_vraddub", + "llvm.hexagon.A2.vraddub.acc" => "__builtin_HEXAGON_A2_vraddub_acc", + "llvm.hexagon.A2.vrsadub" => "__builtin_HEXAGON_A2_vrsadub", + "llvm.hexagon.A2.vrsadub.acc" => "__builtin_HEXAGON_A2_vrsadub_acc", + "llvm.hexagon.A2.vsubb.map" => "__builtin_HEXAGON_A2_vsubb_map", + "llvm.hexagon.A2.vsubh" => "__builtin_HEXAGON_A2_vsubh", + "llvm.hexagon.A2.vsubhs" => "__builtin_HEXAGON_A2_vsubhs", + "llvm.hexagon.A2.vsubub" => "__builtin_HEXAGON_A2_vsubub", + "llvm.hexagon.A2.vsububs" => "__builtin_HEXAGON_A2_vsububs", + "llvm.hexagon.A2.vsubuhs" => "__builtin_HEXAGON_A2_vsubuhs", + "llvm.hexagon.A2.vsubw" => "__builtin_HEXAGON_A2_vsubw", + "llvm.hexagon.A2.vsubws" => "__builtin_HEXAGON_A2_vsubws", + "llvm.hexagon.A2.xor" => "__builtin_HEXAGON_A2_xor", + "llvm.hexagon.A2.xorp" => "__builtin_HEXAGON_A2_xorp", + "llvm.hexagon.A2.zxtb" => "__builtin_HEXAGON_A2_zxtb", + "llvm.hexagon.A2.zxth" => "__builtin_HEXAGON_A2_zxth", + "llvm.hexagon.A4.andn" => "__builtin_HEXAGON_A4_andn", + "llvm.hexagon.A4.andnp" => "__builtin_HEXAGON_A4_andnp", + "llvm.hexagon.A4.bitsplit" => "__builtin_HEXAGON_A4_bitsplit", + "llvm.hexagon.A4.bitspliti" => "__builtin_HEXAGON_A4_bitspliti", + "llvm.hexagon.A4.boundscheck" => "__builtin_HEXAGON_A4_boundscheck", + "llvm.hexagon.A4.cmpbeq" => "__builtin_HEXAGON_A4_cmpbeq", + "llvm.hexagon.A4.cmpbeqi" => "__builtin_HEXAGON_A4_cmpbeqi", + "llvm.hexagon.A4.cmpbgt" => "__builtin_HEXAGON_A4_cmpbgt", + "llvm.hexagon.A4.cmpbgti" => "__builtin_HEXAGON_A4_cmpbgti", + "llvm.hexagon.A4.cmpbgtu" => "__builtin_HEXAGON_A4_cmpbgtu", + "llvm.hexagon.A4.cmpbgtui" => "__builtin_HEXAGON_A4_cmpbgtui", + "llvm.hexagon.A4.cmpheq" => "__builtin_HEXAGON_A4_cmpheq", + "llvm.hexagon.A4.cmpheqi" => "__builtin_HEXAGON_A4_cmpheqi", + "llvm.hexagon.A4.cmphgt" => "__builtin_HEXAGON_A4_cmphgt", + "llvm.hexagon.A4.cmphgti" => "__builtin_HEXAGON_A4_cmphgti", + "llvm.hexagon.A4.cmphgtu" => "__builtin_HEXAGON_A4_cmphgtu", + "llvm.hexagon.A4.cmphgtui" => "__builtin_HEXAGON_A4_cmphgtui", + "llvm.hexagon.A4.combineir" => "__builtin_HEXAGON_A4_combineir", + "llvm.hexagon.A4.combineri" => "__builtin_HEXAGON_A4_combineri", + "llvm.hexagon.A4.cround.ri" => "__builtin_HEXAGON_A4_cround_ri", + "llvm.hexagon.A4.cround.rr" => "__builtin_HEXAGON_A4_cround_rr", + "llvm.hexagon.A4.modwrapu" => "__builtin_HEXAGON_A4_modwrapu", + "llvm.hexagon.A4.orn" => "__builtin_HEXAGON_A4_orn", + "llvm.hexagon.A4.ornp" => "__builtin_HEXAGON_A4_ornp", + "llvm.hexagon.A4.rcmpeq" => "__builtin_HEXAGON_A4_rcmpeq", + "llvm.hexagon.A4.rcmpeqi" => "__builtin_HEXAGON_A4_rcmpeqi", + "llvm.hexagon.A4.rcmpneq" => "__builtin_HEXAGON_A4_rcmpneq", + "llvm.hexagon.A4.rcmpneqi" => "__builtin_HEXAGON_A4_rcmpneqi", + "llvm.hexagon.A4.round.ri" => "__builtin_HEXAGON_A4_round_ri", + "llvm.hexagon.A4.round.ri.sat" => "__builtin_HEXAGON_A4_round_ri_sat", + "llvm.hexagon.A4.round.rr" => "__builtin_HEXAGON_A4_round_rr", + "llvm.hexagon.A4.round.rr.sat" => "__builtin_HEXAGON_A4_round_rr_sat", + "llvm.hexagon.A4.tlbmatch" => "__builtin_HEXAGON_A4_tlbmatch", + "llvm.hexagon.A4.vcmpbeq.any" => "__builtin_HEXAGON_A4_vcmpbeq_any", + "llvm.hexagon.A4.vcmpbeqi" => "__builtin_HEXAGON_A4_vcmpbeqi", + "llvm.hexagon.A4.vcmpbgt" => "__builtin_HEXAGON_A4_vcmpbgt", + "llvm.hexagon.A4.vcmpbgti" => "__builtin_HEXAGON_A4_vcmpbgti", + "llvm.hexagon.A4.vcmpbgtui" => "__builtin_HEXAGON_A4_vcmpbgtui", + "llvm.hexagon.A4.vcmpheqi" => "__builtin_HEXAGON_A4_vcmpheqi", + "llvm.hexagon.A4.vcmphgti" => "__builtin_HEXAGON_A4_vcmphgti", + "llvm.hexagon.A4.vcmphgtui" => "__builtin_HEXAGON_A4_vcmphgtui", + "llvm.hexagon.A4.vcmpweqi" => "__builtin_HEXAGON_A4_vcmpweqi", + "llvm.hexagon.A4.vcmpwgti" => "__builtin_HEXAGON_A4_vcmpwgti", + "llvm.hexagon.A4.vcmpwgtui" => "__builtin_HEXAGON_A4_vcmpwgtui", + "llvm.hexagon.A4.vrmaxh" => "__builtin_HEXAGON_A4_vrmaxh", + "llvm.hexagon.A4.vrmaxuh" => "__builtin_HEXAGON_A4_vrmaxuh", + "llvm.hexagon.A4.vrmaxuw" => "__builtin_HEXAGON_A4_vrmaxuw", + "llvm.hexagon.A4.vrmaxw" => "__builtin_HEXAGON_A4_vrmaxw", + "llvm.hexagon.A4.vrminh" => "__builtin_HEXAGON_A4_vrminh", + "llvm.hexagon.A4.vrminuh" => "__builtin_HEXAGON_A4_vrminuh", + "llvm.hexagon.A4.vrminuw" => "__builtin_HEXAGON_A4_vrminuw", + "llvm.hexagon.A4.vrminw" => "__builtin_HEXAGON_A4_vrminw", + "llvm.hexagon.A5.vaddhubs" => "__builtin_HEXAGON_A5_vaddhubs", + "llvm.hexagon.C2.all8" => "__builtin_HEXAGON_C2_all8", + "llvm.hexagon.C2.and" => "__builtin_HEXAGON_C2_and", + "llvm.hexagon.C2.andn" => "__builtin_HEXAGON_C2_andn", + "llvm.hexagon.C2.any8" => "__builtin_HEXAGON_C2_any8", + "llvm.hexagon.C2.bitsclr" => "__builtin_HEXAGON_C2_bitsclr", + "llvm.hexagon.C2.bitsclri" => "__builtin_HEXAGON_C2_bitsclri", + "llvm.hexagon.C2.bitsset" => "__builtin_HEXAGON_C2_bitsset", + "llvm.hexagon.C2.cmpeq" => "__builtin_HEXAGON_C2_cmpeq", + "llvm.hexagon.C2.cmpeqi" => "__builtin_HEXAGON_C2_cmpeqi", + "llvm.hexagon.C2.cmpeqp" => "__builtin_HEXAGON_C2_cmpeqp", + "llvm.hexagon.C2.cmpgei" => "__builtin_HEXAGON_C2_cmpgei", + "llvm.hexagon.C2.cmpgeui" => "__builtin_HEXAGON_C2_cmpgeui", + "llvm.hexagon.C2.cmpgt" => "__builtin_HEXAGON_C2_cmpgt", + "llvm.hexagon.C2.cmpgti" => "__builtin_HEXAGON_C2_cmpgti", + "llvm.hexagon.C2.cmpgtp" => "__builtin_HEXAGON_C2_cmpgtp", + "llvm.hexagon.C2.cmpgtu" => "__builtin_HEXAGON_C2_cmpgtu", + "llvm.hexagon.C2.cmpgtui" => "__builtin_HEXAGON_C2_cmpgtui", + "llvm.hexagon.C2.cmpgtup" => "__builtin_HEXAGON_C2_cmpgtup", + "llvm.hexagon.C2.cmplt" => "__builtin_HEXAGON_C2_cmplt", + "llvm.hexagon.C2.cmpltu" => "__builtin_HEXAGON_C2_cmpltu", + "llvm.hexagon.C2.mask" => "__builtin_HEXAGON_C2_mask", + "llvm.hexagon.C2.mux" => "__builtin_HEXAGON_C2_mux", + "llvm.hexagon.C2.muxii" => "__builtin_HEXAGON_C2_muxii", + "llvm.hexagon.C2.muxir" => "__builtin_HEXAGON_C2_muxir", + "llvm.hexagon.C2.muxri" => "__builtin_HEXAGON_C2_muxri", + "llvm.hexagon.C2.not" => "__builtin_HEXAGON_C2_not", + "llvm.hexagon.C2.or" => "__builtin_HEXAGON_C2_or", + "llvm.hexagon.C2.orn" => "__builtin_HEXAGON_C2_orn", + "llvm.hexagon.C2.pxfer.map" => "__builtin_HEXAGON_C2_pxfer_map", + "llvm.hexagon.C2.tfrpr" => "__builtin_HEXAGON_C2_tfrpr", + "llvm.hexagon.C2.tfrrp" => "__builtin_HEXAGON_C2_tfrrp", + "llvm.hexagon.C2.vitpack" => "__builtin_HEXAGON_C2_vitpack", + "llvm.hexagon.C2.vmux" => "__builtin_HEXAGON_C2_vmux", + "llvm.hexagon.C2.xor" => "__builtin_HEXAGON_C2_xor", + "llvm.hexagon.C4.and.and" => "__builtin_HEXAGON_C4_and_and", + "llvm.hexagon.C4.and.andn" => "__builtin_HEXAGON_C4_and_andn", + "llvm.hexagon.C4.and.or" => "__builtin_HEXAGON_C4_and_or", + "llvm.hexagon.C4.and.orn" => "__builtin_HEXAGON_C4_and_orn", + "llvm.hexagon.C4.cmplte" => "__builtin_HEXAGON_C4_cmplte", + "llvm.hexagon.C4.cmpltei" => "__builtin_HEXAGON_C4_cmpltei", + "llvm.hexagon.C4.cmplteu" => "__builtin_HEXAGON_C4_cmplteu", + "llvm.hexagon.C4.cmplteui" => "__builtin_HEXAGON_C4_cmplteui", + "llvm.hexagon.C4.cmpneq" => "__builtin_HEXAGON_C4_cmpneq", + "llvm.hexagon.C4.cmpneqi" => "__builtin_HEXAGON_C4_cmpneqi", + "llvm.hexagon.C4.fastcorner9" => "__builtin_HEXAGON_C4_fastcorner9", + "llvm.hexagon.C4.fastcorner9.not" => "__builtin_HEXAGON_C4_fastcorner9_not", + "llvm.hexagon.C4.nbitsclr" => "__builtin_HEXAGON_C4_nbitsclr", + "llvm.hexagon.C4.nbitsclri" => "__builtin_HEXAGON_C4_nbitsclri", + "llvm.hexagon.C4.nbitsset" => "__builtin_HEXAGON_C4_nbitsset", + "llvm.hexagon.C4.or.and" => "__builtin_HEXAGON_C4_or_and", + "llvm.hexagon.C4.or.andn" => "__builtin_HEXAGON_C4_or_andn", + "llvm.hexagon.C4.or.or" => "__builtin_HEXAGON_C4_or_or", + "llvm.hexagon.C4.or.orn" => "__builtin_HEXAGON_C4_or_orn", + "llvm.hexagon.F2.conv.d2df" => "__builtin_HEXAGON_F2_conv_d2df", + "llvm.hexagon.F2.conv.d2sf" => "__builtin_HEXAGON_F2_conv_d2sf", + "llvm.hexagon.F2.conv.df2d" => "__builtin_HEXAGON_F2_conv_df2d", + "llvm.hexagon.F2.conv.df2d.chop" => "__builtin_HEXAGON_F2_conv_df2d_chop", + "llvm.hexagon.F2.conv.df2sf" => "__builtin_HEXAGON_F2_conv_df2sf", + "llvm.hexagon.F2.conv.df2ud" => "__builtin_HEXAGON_F2_conv_df2ud", + "llvm.hexagon.F2.conv.df2ud.chop" => "__builtin_HEXAGON_F2_conv_df2ud_chop", + "llvm.hexagon.F2.conv.df2uw" => "__builtin_HEXAGON_F2_conv_df2uw", + "llvm.hexagon.F2.conv.df2uw.chop" => "__builtin_HEXAGON_F2_conv_df2uw_chop", + "llvm.hexagon.F2.conv.df2w" => "__builtin_HEXAGON_F2_conv_df2w", + "llvm.hexagon.F2.conv.df2w.chop" => "__builtin_HEXAGON_F2_conv_df2w_chop", + "llvm.hexagon.F2.conv.sf2d" => "__builtin_HEXAGON_F2_conv_sf2d", + "llvm.hexagon.F2.conv.sf2d.chop" => "__builtin_HEXAGON_F2_conv_sf2d_chop", + "llvm.hexagon.F2.conv.sf2df" => "__builtin_HEXAGON_F2_conv_sf2df", + "llvm.hexagon.F2.conv.sf2ud" => "__builtin_HEXAGON_F2_conv_sf2ud", + "llvm.hexagon.F2.conv.sf2ud.chop" => "__builtin_HEXAGON_F2_conv_sf2ud_chop", + "llvm.hexagon.F2.conv.sf2uw" => "__builtin_HEXAGON_F2_conv_sf2uw", + "llvm.hexagon.F2.conv.sf2uw.chop" => "__builtin_HEXAGON_F2_conv_sf2uw_chop", + "llvm.hexagon.F2.conv.sf2w" => "__builtin_HEXAGON_F2_conv_sf2w", + "llvm.hexagon.F2.conv.sf2w.chop" => "__builtin_HEXAGON_F2_conv_sf2w_chop", + "llvm.hexagon.F2.conv.ud2df" => "__builtin_HEXAGON_F2_conv_ud2df", + "llvm.hexagon.F2.conv.ud2sf" => "__builtin_HEXAGON_F2_conv_ud2sf", + "llvm.hexagon.F2.conv.uw2df" => "__builtin_HEXAGON_F2_conv_uw2df", + "llvm.hexagon.F2.conv.uw2sf" => "__builtin_HEXAGON_F2_conv_uw2sf", + "llvm.hexagon.F2.conv.w2df" => "__builtin_HEXAGON_F2_conv_w2df", + "llvm.hexagon.F2.conv.w2sf" => "__builtin_HEXAGON_F2_conv_w2sf", + "llvm.hexagon.F2.dfadd" => "__builtin_HEXAGON_F2_dfadd", + "llvm.hexagon.F2.dfclass" => "__builtin_HEXAGON_F2_dfclass", + "llvm.hexagon.F2.dfcmpeq" => "__builtin_HEXAGON_F2_dfcmpeq", + "llvm.hexagon.F2.dfcmpge" => "__builtin_HEXAGON_F2_dfcmpge", + "llvm.hexagon.F2.dfcmpgt" => "__builtin_HEXAGON_F2_dfcmpgt", + "llvm.hexagon.F2.dfcmpuo" => "__builtin_HEXAGON_F2_dfcmpuo", + "llvm.hexagon.F2.dffixupd" => "__builtin_HEXAGON_F2_dffixupd", + "llvm.hexagon.F2.dffixupn" => "__builtin_HEXAGON_F2_dffixupn", + "llvm.hexagon.F2.dffixupr" => "__builtin_HEXAGON_F2_dffixupr", + "llvm.hexagon.F2.dffma" => "__builtin_HEXAGON_F2_dffma", + "llvm.hexagon.F2.dffma.lib" => "__builtin_HEXAGON_F2_dffma_lib", + "llvm.hexagon.F2.dffma.sc" => "__builtin_HEXAGON_F2_dffma_sc", + "llvm.hexagon.F2.dffms" => "__builtin_HEXAGON_F2_dffms", + "llvm.hexagon.F2.dffms.lib" => "__builtin_HEXAGON_F2_dffms_lib", + "llvm.hexagon.F2.dfimm.n" => "__builtin_HEXAGON_F2_dfimm_n", + "llvm.hexagon.F2.dfimm.p" => "__builtin_HEXAGON_F2_dfimm_p", + "llvm.hexagon.F2.dfmax" => "__builtin_HEXAGON_F2_dfmax", + "llvm.hexagon.F2.dfmin" => "__builtin_HEXAGON_F2_dfmin", + "llvm.hexagon.F2.dfmpy" => "__builtin_HEXAGON_F2_dfmpy", + "llvm.hexagon.F2.dfsub" => "__builtin_HEXAGON_F2_dfsub", + "llvm.hexagon.F2.sfadd" => "__builtin_HEXAGON_F2_sfadd", + "llvm.hexagon.F2.sfclass" => "__builtin_HEXAGON_F2_sfclass", + "llvm.hexagon.F2.sfcmpeq" => "__builtin_HEXAGON_F2_sfcmpeq", + "llvm.hexagon.F2.sfcmpge" => "__builtin_HEXAGON_F2_sfcmpge", + "llvm.hexagon.F2.sfcmpgt" => "__builtin_HEXAGON_F2_sfcmpgt", + "llvm.hexagon.F2.sfcmpuo" => "__builtin_HEXAGON_F2_sfcmpuo", + "llvm.hexagon.F2.sffixupd" => "__builtin_HEXAGON_F2_sffixupd", + "llvm.hexagon.F2.sffixupn" => "__builtin_HEXAGON_F2_sffixupn", + "llvm.hexagon.F2.sffixupr" => "__builtin_HEXAGON_F2_sffixupr", + "llvm.hexagon.F2.sffma" => "__builtin_HEXAGON_F2_sffma", + "llvm.hexagon.F2.sffma.lib" => "__builtin_HEXAGON_F2_sffma_lib", + "llvm.hexagon.F2.sffma.sc" => "__builtin_HEXAGON_F2_sffma_sc", + "llvm.hexagon.F2.sffms" => "__builtin_HEXAGON_F2_sffms", + "llvm.hexagon.F2.sffms.lib" => "__builtin_HEXAGON_F2_sffms_lib", + "llvm.hexagon.F2.sfimm.n" => "__builtin_HEXAGON_F2_sfimm_n", + "llvm.hexagon.F2.sfimm.p" => "__builtin_HEXAGON_F2_sfimm_p", + "llvm.hexagon.F2.sfmax" => "__builtin_HEXAGON_F2_sfmax", + "llvm.hexagon.F2.sfmin" => "__builtin_HEXAGON_F2_sfmin", + "llvm.hexagon.F2.sfmpy" => "__builtin_HEXAGON_F2_sfmpy", + "llvm.hexagon.F2.sfsub" => "__builtin_HEXAGON_F2_sfsub", + "llvm.hexagon.M2.acci" => "__builtin_HEXAGON_M2_acci", + "llvm.hexagon.M2.accii" => "__builtin_HEXAGON_M2_accii", + "llvm.hexagon.M2.cmaci.s0" => "__builtin_HEXAGON_M2_cmaci_s0", + "llvm.hexagon.M2.cmacr.s0" => "__builtin_HEXAGON_M2_cmacr_s0", + "llvm.hexagon.M2.cmacs.s0" => "__builtin_HEXAGON_M2_cmacs_s0", + "llvm.hexagon.M2.cmacs.s1" => "__builtin_HEXAGON_M2_cmacs_s1", + "llvm.hexagon.M2.cmacsc.s0" => "__builtin_HEXAGON_M2_cmacsc_s0", + "llvm.hexagon.M2.cmacsc.s1" => "__builtin_HEXAGON_M2_cmacsc_s1", + "llvm.hexagon.M2.cmpyi.s0" => "__builtin_HEXAGON_M2_cmpyi_s0", + "llvm.hexagon.M2.cmpyr.s0" => "__builtin_HEXAGON_M2_cmpyr_s0", + "llvm.hexagon.M2.cmpyrs.s0" => "__builtin_HEXAGON_M2_cmpyrs_s0", + "llvm.hexagon.M2.cmpyrs.s1" => "__builtin_HEXAGON_M2_cmpyrs_s1", + "llvm.hexagon.M2.cmpyrsc.s0" => "__builtin_HEXAGON_M2_cmpyrsc_s0", + "llvm.hexagon.M2.cmpyrsc.s1" => "__builtin_HEXAGON_M2_cmpyrsc_s1", + "llvm.hexagon.M2.cmpys.s0" => "__builtin_HEXAGON_M2_cmpys_s0", + "llvm.hexagon.M2.cmpys.s1" => "__builtin_HEXAGON_M2_cmpys_s1", + "llvm.hexagon.M2.cmpysc.s0" => "__builtin_HEXAGON_M2_cmpysc_s0", + "llvm.hexagon.M2.cmpysc.s1" => "__builtin_HEXAGON_M2_cmpysc_s1", + "llvm.hexagon.M2.cnacs.s0" => "__builtin_HEXAGON_M2_cnacs_s0", + "llvm.hexagon.M2.cnacs.s1" => "__builtin_HEXAGON_M2_cnacs_s1", + "llvm.hexagon.M2.cnacsc.s0" => "__builtin_HEXAGON_M2_cnacsc_s0", + "llvm.hexagon.M2.cnacsc.s1" => "__builtin_HEXAGON_M2_cnacsc_s1", + "llvm.hexagon.M2.dpmpyss.acc.s0" => "__builtin_HEXAGON_M2_dpmpyss_acc_s0", + "llvm.hexagon.M2.dpmpyss.nac.s0" => "__builtin_HEXAGON_M2_dpmpyss_nac_s0", + "llvm.hexagon.M2.dpmpyss.rnd.s0" => "__builtin_HEXAGON_M2_dpmpyss_rnd_s0", + "llvm.hexagon.M2.dpmpyss.s0" => "__builtin_HEXAGON_M2_dpmpyss_s0", + "llvm.hexagon.M2.dpmpyuu.acc.s0" => "__builtin_HEXAGON_M2_dpmpyuu_acc_s0", + "llvm.hexagon.M2.dpmpyuu.nac.s0" => "__builtin_HEXAGON_M2_dpmpyuu_nac_s0", + "llvm.hexagon.M2.dpmpyuu.s0" => "__builtin_HEXAGON_M2_dpmpyuu_s0", + "llvm.hexagon.M2.hmmpyh.rs1" => "__builtin_HEXAGON_M2_hmmpyh_rs1", + "llvm.hexagon.M2.hmmpyh.s1" => "__builtin_HEXAGON_M2_hmmpyh_s1", + "llvm.hexagon.M2.hmmpyl.rs1" => "__builtin_HEXAGON_M2_hmmpyl_rs1", + "llvm.hexagon.M2.hmmpyl.s1" => "__builtin_HEXAGON_M2_hmmpyl_s1", + "llvm.hexagon.M2.maci" => "__builtin_HEXAGON_M2_maci", + "llvm.hexagon.M2.macsin" => "__builtin_HEXAGON_M2_macsin", + "llvm.hexagon.M2.macsip" => "__builtin_HEXAGON_M2_macsip", + "llvm.hexagon.M2.mmachs.rs0" => "__builtin_HEXAGON_M2_mmachs_rs0", + "llvm.hexagon.M2.mmachs.rs1" => "__builtin_HEXAGON_M2_mmachs_rs1", + "llvm.hexagon.M2.mmachs.s0" => "__builtin_HEXAGON_M2_mmachs_s0", + "llvm.hexagon.M2.mmachs.s1" => "__builtin_HEXAGON_M2_mmachs_s1", + "llvm.hexagon.M2.mmacls.rs0" => "__builtin_HEXAGON_M2_mmacls_rs0", + "llvm.hexagon.M2.mmacls.rs1" => "__builtin_HEXAGON_M2_mmacls_rs1", + "llvm.hexagon.M2.mmacls.s0" => "__builtin_HEXAGON_M2_mmacls_s0", + "llvm.hexagon.M2.mmacls.s1" => "__builtin_HEXAGON_M2_mmacls_s1", + "llvm.hexagon.M2.mmacuhs.rs0" => "__builtin_HEXAGON_M2_mmacuhs_rs0", + "llvm.hexagon.M2.mmacuhs.rs1" => "__builtin_HEXAGON_M2_mmacuhs_rs1", + "llvm.hexagon.M2.mmacuhs.s0" => "__builtin_HEXAGON_M2_mmacuhs_s0", + "llvm.hexagon.M2.mmacuhs.s1" => "__builtin_HEXAGON_M2_mmacuhs_s1", + "llvm.hexagon.M2.mmaculs.rs0" => "__builtin_HEXAGON_M2_mmaculs_rs0", + "llvm.hexagon.M2.mmaculs.rs1" => "__builtin_HEXAGON_M2_mmaculs_rs1", + "llvm.hexagon.M2.mmaculs.s0" => "__builtin_HEXAGON_M2_mmaculs_s0", + "llvm.hexagon.M2.mmaculs.s1" => "__builtin_HEXAGON_M2_mmaculs_s1", + "llvm.hexagon.M2.mmpyh.rs0" => "__builtin_HEXAGON_M2_mmpyh_rs0", + "llvm.hexagon.M2.mmpyh.rs1" => "__builtin_HEXAGON_M2_mmpyh_rs1", + "llvm.hexagon.M2.mmpyh.s0" => "__builtin_HEXAGON_M2_mmpyh_s0", + "llvm.hexagon.M2.mmpyh.s1" => "__builtin_HEXAGON_M2_mmpyh_s1", + "llvm.hexagon.M2.mmpyl.rs0" => "__builtin_HEXAGON_M2_mmpyl_rs0", + "llvm.hexagon.M2.mmpyl.rs1" => "__builtin_HEXAGON_M2_mmpyl_rs1", + "llvm.hexagon.M2.mmpyl.s0" => "__builtin_HEXAGON_M2_mmpyl_s0", + "llvm.hexagon.M2.mmpyl.s1" => "__builtin_HEXAGON_M2_mmpyl_s1", + "llvm.hexagon.M2.mmpyuh.rs0" => "__builtin_HEXAGON_M2_mmpyuh_rs0", + "llvm.hexagon.M2.mmpyuh.rs1" => "__builtin_HEXAGON_M2_mmpyuh_rs1", + "llvm.hexagon.M2.mmpyuh.s0" => "__builtin_HEXAGON_M2_mmpyuh_s0", + "llvm.hexagon.M2.mmpyuh.s1" => "__builtin_HEXAGON_M2_mmpyuh_s1", + "llvm.hexagon.M2.mmpyul.rs0" => "__builtin_HEXAGON_M2_mmpyul_rs0", + "llvm.hexagon.M2.mmpyul.rs1" => "__builtin_HEXAGON_M2_mmpyul_rs1", + "llvm.hexagon.M2.mmpyul.s0" => "__builtin_HEXAGON_M2_mmpyul_s0", + "llvm.hexagon.M2.mmpyul.s1" => "__builtin_HEXAGON_M2_mmpyul_s1", + "llvm.hexagon.M2.mpy.acc.hh.s0" => "__builtin_HEXAGON_M2_mpy_acc_hh_s0", + "llvm.hexagon.M2.mpy.acc.hh.s1" => "__builtin_HEXAGON_M2_mpy_acc_hh_s1", + "llvm.hexagon.M2.mpy.acc.hl.s0" => "__builtin_HEXAGON_M2_mpy_acc_hl_s0", + "llvm.hexagon.M2.mpy.acc.hl.s1" => "__builtin_HEXAGON_M2_mpy_acc_hl_s1", + "llvm.hexagon.M2.mpy.acc.lh.s0" => "__builtin_HEXAGON_M2_mpy_acc_lh_s0", + "llvm.hexagon.M2.mpy.acc.lh.s1" => "__builtin_HEXAGON_M2_mpy_acc_lh_s1", + "llvm.hexagon.M2.mpy.acc.ll.s0" => "__builtin_HEXAGON_M2_mpy_acc_ll_s0", + "llvm.hexagon.M2.mpy.acc.ll.s1" => "__builtin_HEXAGON_M2_mpy_acc_ll_s1", + "llvm.hexagon.M2.mpy.acc.sat.hh.s0" => "__builtin_HEXAGON_M2_mpy_acc_sat_hh_s0", + "llvm.hexagon.M2.mpy.acc.sat.hh.s1" => "__builtin_HEXAGON_M2_mpy_acc_sat_hh_s1", + "llvm.hexagon.M2.mpy.acc.sat.hl.s0" => "__builtin_HEXAGON_M2_mpy_acc_sat_hl_s0", + "llvm.hexagon.M2.mpy.acc.sat.hl.s1" => "__builtin_HEXAGON_M2_mpy_acc_sat_hl_s1", + "llvm.hexagon.M2.mpy.acc.sat.lh.s0" => "__builtin_HEXAGON_M2_mpy_acc_sat_lh_s0", + "llvm.hexagon.M2.mpy.acc.sat.lh.s1" => "__builtin_HEXAGON_M2_mpy_acc_sat_lh_s1", + "llvm.hexagon.M2.mpy.acc.sat.ll.s0" => "__builtin_HEXAGON_M2_mpy_acc_sat_ll_s0", + "llvm.hexagon.M2.mpy.acc.sat.ll.s1" => "__builtin_HEXAGON_M2_mpy_acc_sat_ll_s1", + "llvm.hexagon.M2.mpy.hh.s0" => "__builtin_HEXAGON_M2_mpy_hh_s0", + "llvm.hexagon.M2.mpy.hh.s1" => "__builtin_HEXAGON_M2_mpy_hh_s1", + "llvm.hexagon.M2.mpy.hl.s0" => "__builtin_HEXAGON_M2_mpy_hl_s0", + "llvm.hexagon.M2.mpy.hl.s1" => "__builtin_HEXAGON_M2_mpy_hl_s1", + "llvm.hexagon.M2.mpy.lh.s0" => "__builtin_HEXAGON_M2_mpy_lh_s0", + "llvm.hexagon.M2.mpy.lh.s1" => "__builtin_HEXAGON_M2_mpy_lh_s1", + "llvm.hexagon.M2.mpy.ll.s0" => "__builtin_HEXAGON_M2_mpy_ll_s0", + "llvm.hexagon.M2.mpy.ll.s1" => "__builtin_HEXAGON_M2_mpy_ll_s1", + "llvm.hexagon.M2.mpy.nac.hh.s0" => "__builtin_HEXAGON_M2_mpy_nac_hh_s0", + "llvm.hexagon.M2.mpy.nac.hh.s1" => "__builtin_HEXAGON_M2_mpy_nac_hh_s1", + "llvm.hexagon.M2.mpy.nac.hl.s0" => "__builtin_HEXAGON_M2_mpy_nac_hl_s0", + "llvm.hexagon.M2.mpy.nac.hl.s1" => "__builtin_HEXAGON_M2_mpy_nac_hl_s1", + "llvm.hexagon.M2.mpy.nac.lh.s0" => "__builtin_HEXAGON_M2_mpy_nac_lh_s0", + "llvm.hexagon.M2.mpy.nac.lh.s1" => "__builtin_HEXAGON_M2_mpy_nac_lh_s1", + "llvm.hexagon.M2.mpy.nac.ll.s0" => "__builtin_HEXAGON_M2_mpy_nac_ll_s0", + "llvm.hexagon.M2.mpy.nac.ll.s1" => "__builtin_HEXAGON_M2_mpy_nac_ll_s1", + "llvm.hexagon.M2.mpy.nac.sat.hh.s0" => "__builtin_HEXAGON_M2_mpy_nac_sat_hh_s0", + "llvm.hexagon.M2.mpy.nac.sat.hh.s1" => "__builtin_HEXAGON_M2_mpy_nac_sat_hh_s1", + "llvm.hexagon.M2.mpy.nac.sat.hl.s0" => "__builtin_HEXAGON_M2_mpy_nac_sat_hl_s0", + "llvm.hexagon.M2.mpy.nac.sat.hl.s1" => "__builtin_HEXAGON_M2_mpy_nac_sat_hl_s1", + "llvm.hexagon.M2.mpy.nac.sat.lh.s0" => "__builtin_HEXAGON_M2_mpy_nac_sat_lh_s0", + "llvm.hexagon.M2.mpy.nac.sat.lh.s1" => "__builtin_HEXAGON_M2_mpy_nac_sat_lh_s1", + "llvm.hexagon.M2.mpy.nac.sat.ll.s0" => "__builtin_HEXAGON_M2_mpy_nac_sat_ll_s0", + "llvm.hexagon.M2.mpy.nac.sat.ll.s1" => "__builtin_HEXAGON_M2_mpy_nac_sat_ll_s1", + "llvm.hexagon.M2.mpy.rnd.hh.s0" => "__builtin_HEXAGON_M2_mpy_rnd_hh_s0", + "llvm.hexagon.M2.mpy.rnd.hh.s1" => "__builtin_HEXAGON_M2_mpy_rnd_hh_s1", + "llvm.hexagon.M2.mpy.rnd.hl.s0" => "__builtin_HEXAGON_M2_mpy_rnd_hl_s0", + "llvm.hexagon.M2.mpy.rnd.hl.s1" => "__builtin_HEXAGON_M2_mpy_rnd_hl_s1", + "llvm.hexagon.M2.mpy.rnd.lh.s0" => "__builtin_HEXAGON_M2_mpy_rnd_lh_s0", + "llvm.hexagon.M2.mpy.rnd.lh.s1" => "__builtin_HEXAGON_M2_mpy_rnd_lh_s1", + "llvm.hexagon.M2.mpy.rnd.ll.s0" => "__builtin_HEXAGON_M2_mpy_rnd_ll_s0", + "llvm.hexagon.M2.mpy.rnd.ll.s1" => "__builtin_HEXAGON_M2_mpy_rnd_ll_s1", + "llvm.hexagon.M2.mpy.sat.hh.s0" => "__builtin_HEXAGON_M2_mpy_sat_hh_s0", + "llvm.hexagon.M2.mpy.sat.hh.s1" => "__builtin_HEXAGON_M2_mpy_sat_hh_s1", + "llvm.hexagon.M2.mpy.sat.hl.s0" => "__builtin_HEXAGON_M2_mpy_sat_hl_s0", + "llvm.hexagon.M2.mpy.sat.hl.s1" => "__builtin_HEXAGON_M2_mpy_sat_hl_s1", + "llvm.hexagon.M2.mpy.sat.lh.s0" => "__builtin_HEXAGON_M2_mpy_sat_lh_s0", + "llvm.hexagon.M2.mpy.sat.lh.s1" => "__builtin_HEXAGON_M2_mpy_sat_lh_s1", + "llvm.hexagon.M2.mpy.sat.ll.s0" => "__builtin_HEXAGON_M2_mpy_sat_ll_s0", + "llvm.hexagon.M2.mpy.sat.ll.s1" => "__builtin_HEXAGON_M2_mpy_sat_ll_s1", + "llvm.hexagon.M2.mpy.sat.rnd.hh.s0" => "__builtin_HEXAGON_M2_mpy_sat_rnd_hh_s0", + "llvm.hexagon.M2.mpy.sat.rnd.hh.s1" => "__builtin_HEXAGON_M2_mpy_sat_rnd_hh_s1", + "llvm.hexagon.M2.mpy.sat.rnd.hl.s0" => "__builtin_HEXAGON_M2_mpy_sat_rnd_hl_s0", + "llvm.hexagon.M2.mpy.sat.rnd.hl.s1" => "__builtin_HEXAGON_M2_mpy_sat_rnd_hl_s1", + "llvm.hexagon.M2.mpy.sat.rnd.lh.s0" => "__builtin_HEXAGON_M2_mpy_sat_rnd_lh_s0", + "llvm.hexagon.M2.mpy.sat.rnd.lh.s1" => "__builtin_HEXAGON_M2_mpy_sat_rnd_lh_s1", + "llvm.hexagon.M2.mpy.sat.rnd.ll.s0" => "__builtin_HEXAGON_M2_mpy_sat_rnd_ll_s0", + "llvm.hexagon.M2.mpy.sat.rnd.ll.s1" => "__builtin_HEXAGON_M2_mpy_sat_rnd_ll_s1", + "llvm.hexagon.M2.mpy.up" => "__builtin_HEXAGON_M2_mpy_up", + "llvm.hexagon.M2.mpy.up.s1" => "__builtin_HEXAGON_M2_mpy_up_s1", + "llvm.hexagon.M2.mpy.up.s1.sat" => "__builtin_HEXAGON_M2_mpy_up_s1_sat", + "llvm.hexagon.M2.mpyd.acc.hh.s0" => "__builtin_HEXAGON_M2_mpyd_acc_hh_s0", + "llvm.hexagon.M2.mpyd.acc.hh.s1" => "__builtin_HEXAGON_M2_mpyd_acc_hh_s1", + "llvm.hexagon.M2.mpyd.acc.hl.s0" => "__builtin_HEXAGON_M2_mpyd_acc_hl_s0", + "llvm.hexagon.M2.mpyd.acc.hl.s1" => "__builtin_HEXAGON_M2_mpyd_acc_hl_s1", + "llvm.hexagon.M2.mpyd.acc.lh.s0" => "__builtin_HEXAGON_M2_mpyd_acc_lh_s0", + "llvm.hexagon.M2.mpyd.acc.lh.s1" => "__builtin_HEXAGON_M2_mpyd_acc_lh_s1", + "llvm.hexagon.M2.mpyd.acc.ll.s0" => "__builtin_HEXAGON_M2_mpyd_acc_ll_s0", + "llvm.hexagon.M2.mpyd.acc.ll.s1" => "__builtin_HEXAGON_M2_mpyd_acc_ll_s1", + "llvm.hexagon.M2.mpyd.hh.s0" => "__builtin_HEXAGON_M2_mpyd_hh_s0", + "llvm.hexagon.M2.mpyd.hh.s1" => "__builtin_HEXAGON_M2_mpyd_hh_s1", + "llvm.hexagon.M2.mpyd.hl.s0" => "__builtin_HEXAGON_M2_mpyd_hl_s0", + "llvm.hexagon.M2.mpyd.hl.s1" => "__builtin_HEXAGON_M2_mpyd_hl_s1", + "llvm.hexagon.M2.mpyd.lh.s0" => "__builtin_HEXAGON_M2_mpyd_lh_s0", + "llvm.hexagon.M2.mpyd.lh.s1" => "__builtin_HEXAGON_M2_mpyd_lh_s1", + "llvm.hexagon.M2.mpyd.ll.s0" => "__builtin_HEXAGON_M2_mpyd_ll_s0", + "llvm.hexagon.M2.mpyd.ll.s1" => "__builtin_HEXAGON_M2_mpyd_ll_s1", + "llvm.hexagon.M2.mpyd.nac.hh.s0" => "__builtin_HEXAGON_M2_mpyd_nac_hh_s0", + "llvm.hexagon.M2.mpyd.nac.hh.s1" => "__builtin_HEXAGON_M2_mpyd_nac_hh_s1", + "llvm.hexagon.M2.mpyd.nac.hl.s0" => "__builtin_HEXAGON_M2_mpyd_nac_hl_s0", + "llvm.hexagon.M2.mpyd.nac.hl.s1" => "__builtin_HEXAGON_M2_mpyd_nac_hl_s1", + "llvm.hexagon.M2.mpyd.nac.lh.s0" => "__builtin_HEXAGON_M2_mpyd_nac_lh_s0", + "llvm.hexagon.M2.mpyd.nac.lh.s1" => "__builtin_HEXAGON_M2_mpyd_nac_lh_s1", + "llvm.hexagon.M2.mpyd.nac.ll.s0" => "__builtin_HEXAGON_M2_mpyd_nac_ll_s0", + "llvm.hexagon.M2.mpyd.nac.ll.s1" => "__builtin_HEXAGON_M2_mpyd_nac_ll_s1", + "llvm.hexagon.M2.mpyd.rnd.hh.s0" => "__builtin_HEXAGON_M2_mpyd_rnd_hh_s0", + "llvm.hexagon.M2.mpyd.rnd.hh.s1" => "__builtin_HEXAGON_M2_mpyd_rnd_hh_s1", + "llvm.hexagon.M2.mpyd.rnd.hl.s0" => "__builtin_HEXAGON_M2_mpyd_rnd_hl_s0", + "llvm.hexagon.M2.mpyd.rnd.hl.s1" => "__builtin_HEXAGON_M2_mpyd_rnd_hl_s1", + "llvm.hexagon.M2.mpyd.rnd.lh.s0" => "__builtin_HEXAGON_M2_mpyd_rnd_lh_s0", + "llvm.hexagon.M2.mpyd.rnd.lh.s1" => "__builtin_HEXAGON_M2_mpyd_rnd_lh_s1", + "llvm.hexagon.M2.mpyd.rnd.ll.s0" => "__builtin_HEXAGON_M2_mpyd_rnd_ll_s0", + "llvm.hexagon.M2.mpyd.rnd.ll.s1" => "__builtin_HEXAGON_M2_mpyd_rnd_ll_s1", + "llvm.hexagon.M2.mpyi" => "__builtin_HEXAGON_M2_mpyi", + "llvm.hexagon.M2.mpysmi" => "__builtin_HEXAGON_M2_mpysmi", + "llvm.hexagon.M2.mpysu.up" => "__builtin_HEXAGON_M2_mpysu_up", + "llvm.hexagon.M2.mpyu.acc.hh.s0" => "__builtin_HEXAGON_M2_mpyu_acc_hh_s0", + "llvm.hexagon.M2.mpyu.acc.hh.s1" => "__builtin_HEXAGON_M2_mpyu_acc_hh_s1", + "llvm.hexagon.M2.mpyu.acc.hl.s0" => "__builtin_HEXAGON_M2_mpyu_acc_hl_s0", + "llvm.hexagon.M2.mpyu.acc.hl.s1" => "__builtin_HEXAGON_M2_mpyu_acc_hl_s1", + "llvm.hexagon.M2.mpyu.acc.lh.s0" => "__builtin_HEXAGON_M2_mpyu_acc_lh_s0", + "llvm.hexagon.M2.mpyu.acc.lh.s1" => "__builtin_HEXAGON_M2_mpyu_acc_lh_s1", + "llvm.hexagon.M2.mpyu.acc.ll.s0" => "__builtin_HEXAGON_M2_mpyu_acc_ll_s0", + "llvm.hexagon.M2.mpyu.acc.ll.s1" => "__builtin_HEXAGON_M2_mpyu_acc_ll_s1", + "llvm.hexagon.M2.mpyu.hh.s0" => "__builtin_HEXAGON_M2_mpyu_hh_s0", + "llvm.hexagon.M2.mpyu.hh.s1" => "__builtin_HEXAGON_M2_mpyu_hh_s1", + "llvm.hexagon.M2.mpyu.hl.s0" => "__builtin_HEXAGON_M2_mpyu_hl_s0", + "llvm.hexagon.M2.mpyu.hl.s1" => "__builtin_HEXAGON_M2_mpyu_hl_s1", + "llvm.hexagon.M2.mpyu.lh.s0" => "__builtin_HEXAGON_M2_mpyu_lh_s0", + "llvm.hexagon.M2.mpyu.lh.s1" => "__builtin_HEXAGON_M2_mpyu_lh_s1", + "llvm.hexagon.M2.mpyu.ll.s0" => "__builtin_HEXAGON_M2_mpyu_ll_s0", + "llvm.hexagon.M2.mpyu.ll.s1" => "__builtin_HEXAGON_M2_mpyu_ll_s1", + "llvm.hexagon.M2.mpyu.nac.hh.s0" => "__builtin_HEXAGON_M2_mpyu_nac_hh_s0", + "llvm.hexagon.M2.mpyu.nac.hh.s1" => "__builtin_HEXAGON_M2_mpyu_nac_hh_s1", + "llvm.hexagon.M2.mpyu.nac.hl.s0" => "__builtin_HEXAGON_M2_mpyu_nac_hl_s0", + "llvm.hexagon.M2.mpyu.nac.hl.s1" => "__builtin_HEXAGON_M2_mpyu_nac_hl_s1", + "llvm.hexagon.M2.mpyu.nac.lh.s0" => "__builtin_HEXAGON_M2_mpyu_nac_lh_s0", + "llvm.hexagon.M2.mpyu.nac.lh.s1" => "__builtin_HEXAGON_M2_mpyu_nac_lh_s1", + "llvm.hexagon.M2.mpyu.nac.ll.s0" => "__builtin_HEXAGON_M2_mpyu_nac_ll_s0", + "llvm.hexagon.M2.mpyu.nac.ll.s1" => "__builtin_HEXAGON_M2_mpyu_nac_ll_s1", + "llvm.hexagon.M2.mpyu.up" => "__builtin_HEXAGON_M2_mpyu_up", + "llvm.hexagon.M2.mpyud.acc.hh.s0" => "__builtin_HEXAGON_M2_mpyud_acc_hh_s0", + "llvm.hexagon.M2.mpyud.acc.hh.s1" => "__builtin_HEXAGON_M2_mpyud_acc_hh_s1", + "llvm.hexagon.M2.mpyud.acc.hl.s0" => "__builtin_HEXAGON_M2_mpyud_acc_hl_s0", + "llvm.hexagon.M2.mpyud.acc.hl.s1" => "__builtin_HEXAGON_M2_mpyud_acc_hl_s1", + "llvm.hexagon.M2.mpyud.acc.lh.s0" => "__builtin_HEXAGON_M2_mpyud_acc_lh_s0", + "llvm.hexagon.M2.mpyud.acc.lh.s1" => "__builtin_HEXAGON_M2_mpyud_acc_lh_s1", + "llvm.hexagon.M2.mpyud.acc.ll.s0" => "__builtin_HEXAGON_M2_mpyud_acc_ll_s0", + "llvm.hexagon.M2.mpyud.acc.ll.s1" => "__builtin_HEXAGON_M2_mpyud_acc_ll_s1", + "llvm.hexagon.M2.mpyud.hh.s0" => "__builtin_HEXAGON_M2_mpyud_hh_s0", + "llvm.hexagon.M2.mpyud.hh.s1" => "__builtin_HEXAGON_M2_mpyud_hh_s1", + "llvm.hexagon.M2.mpyud.hl.s0" => "__builtin_HEXAGON_M2_mpyud_hl_s0", + "llvm.hexagon.M2.mpyud.hl.s1" => "__builtin_HEXAGON_M2_mpyud_hl_s1", + "llvm.hexagon.M2.mpyud.lh.s0" => "__builtin_HEXAGON_M2_mpyud_lh_s0", + "llvm.hexagon.M2.mpyud.lh.s1" => "__builtin_HEXAGON_M2_mpyud_lh_s1", + "llvm.hexagon.M2.mpyud.ll.s0" => "__builtin_HEXAGON_M2_mpyud_ll_s0", + "llvm.hexagon.M2.mpyud.ll.s1" => "__builtin_HEXAGON_M2_mpyud_ll_s1", + "llvm.hexagon.M2.mpyud.nac.hh.s0" => "__builtin_HEXAGON_M2_mpyud_nac_hh_s0", + "llvm.hexagon.M2.mpyud.nac.hh.s1" => "__builtin_HEXAGON_M2_mpyud_nac_hh_s1", + "llvm.hexagon.M2.mpyud.nac.hl.s0" => "__builtin_HEXAGON_M2_mpyud_nac_hl_s0", + "llvm.hexagon.M2.mpyud.nac.hl.s1" => "__builtin_HEXAGON_M2_mpyud_nac_hl_s1", + "llvm.hexagon.M2.mpyud.nac.lh.s0" => "__builtin_HEXAGON_M2_mpyud_nac_lh_s0", + "llvm.hexagon.M2.mpyud.nac.lh.s1" => "__builtin_HEXAGON_M2_mpyud_nac_lh_s1", + "llvm.hexagon.M2.mpyud.nac.ll.s0" => "__builtin_HEXAGON_M2_mpyud_nac_ll_s0", + "llvm.hexagon.M2.mpyud.nac.ll.s1" => "__builtin_HEXAGON_M2_mpyud_nac_ll_s1", + "llvm.hexagon.M2.mpyui" => "__builtin_HEXAGON_M2_mpyui", + "llvm.hexagon.M2.nacci" => "__builtin_HEXAGON_M2_nacci", + "llvm.hexagon.M2.naccii" => "__builtin_HEXAGON_M2_naccii", + "llvm.hexagon.M2.subacc" => "__builtin_HEXAGON_M2_subacc", + "llvm.hexagon.M2.vabsdiffh" => "__builtin_HEXAGON_M2_vabsdiffh", + "llvm.hexagon.M2.vabsdiffw" => "__builtin_HEXAGON_M2_vabsdiffw", + "llvm.hexagon.M2.vcmac.s0.sat.i" => "__builtin_HEXAGON_M2_vcmac_s0_sat_i", + "llvm.hexagon.M2.vcmac.s0.sat.r" => "__builtin_HEXAGON_M2_vcmac_s0_sat_r", + "llvm.hexagon.M2.vcmpy.s0.sat.i" => "__builtin_HEXAGON_M2_vcmpy_s0_sat_i", + "llvm.hexagon.M2.vcmpy.s0.sat.r" => "__builtin_HEXAGON_M2_vcmpy_s0_sat_r", + "llvm.hexagon.M2.vcmpy.s1.sat.i" => "__builtin_HEXAGON_M2_vcmpy_s1_sat_i", + "llvm.hexagon.M2.vcmpy.s1.sat.r" => "__builtin_HEXAGON_M2_vcmpy_s1_sat_r", + "llvm.hexagon.M2.vdmacs.s0" => "__builtin_HEXAGON_M2_vdmacs_s0", + "llvm.hexagon.M2.vdmacs.s1" => "__builtin_HEXAGON_M2_vdmacs_s1", + "llvm.hexagon.M2.vdmpyrs.s0" => "__builtin_HEXAGON_M2_vdmpyrs_s0", + "llvm.hexagon.M2.vdmpyrs.s1" => "__builtin_HEXAGON_M2_vdmpyrs_s1", + "llvm.hexagon.M2.vdmpys.s0" => "__builtin_HEXAGON_M2_vdmpys_s0", + "llvm.hexagon.M2.vdmpys.s1" => "__builtin_HEXAGON_M2_vdmpys_s1", + "llvm.hexagon.M2.vmac2" => "__builtin_HEXAGON_M2_vmac2", + "llvm.hexagon.M2.vmac2es" => "__builtin_HEXAGON_M2_vmac2es", + "llvm.hexagon.M2.vmac2es.s0" => "__builtin_HEXAGON_M2_vmac2es_s0", + "llvm.hexagon.M2.vmac2es.s1" => "__builtin_HEXAGON_M2_vmac2es_s1", + "llvm.hexagon.M2.vmac2s.s0" => "__builtin_HEXAGON_M2_vmac2s_s0", + "llvm.hexagon.M2.vmac2s.s1" => "__builtin_HEXAGON_M2_vmac2s_s1", + "llvm.hexagon.M2.vmac2su.s0" => "__builtin_HEXAGON_M2_vmac2su_s0", + "llvm.hexagon.M2.vmac2su.s1" => "__builtin_HEXAGON_M2_vmac2su_s1", + "llvm.hexagon.M2.vmpy2es.s0" => "__builtin_HEXAGON_M2_vmpy2es_s0", + "llvm.hexagon.M2.vmpy2es.s1" => "__builtin_HEXAGON_M2_vmpy2es_s1", + "llvm.hexagon.M2.vmpy2s.s0" => "__builtin_HEXAGON_M2_vmpy2s_s0", + "llvm.hexagon.M2.vmpy2s.s0pack" => "__builtin_HEXAGON_M2_vmpy2s_s0pack", + "llvm.hexagon.M2.vmpy2s.s1" => "__builtin_HEXAGON_M2_vmpy2s_s1", + "llvm.hexagon.M2.vmpy2s.s1pack" => "__builtin_HEXAGON_M2_vmpy2s_s1pack", + "llvm.hexagon.M2.vmpy2su.s0" => "__builtin_HEXAGON_M2_vmpy2su_s0", + "llvm.hexagon.M2.vmpy2su.s1" => "__builtin_HEXAGON_M2_vmpy2su_s1", + "llvm.hexagon.M2.vraddh" => "__builtin_HEXAGON_M2_vraddh", + "llvm.hexagon.M2.vradduh" => "__builtin_HEXAGON_M2_vradduh", + "llvm.hexagon.M2.vrcmaci.s0" => "__builtin_HEXAGON_M2_vrcmaci_s0", + "llvm.hexagon.M2.vrcmaci.s0c" => "__builtin_HEXAGON_M2_vrcmaci_s0c", + "llvm.hexagon.M2.vrcmacr.s0" => "__builtin_HEXAGON_M2_vrcmacr_s0", + "llvm.hexagon.M2.vrcmacr.s0c" => "__builtin_HEXAGON_M2_vrcmacr_s0c", + "llvm.hexagon.M2.vrcmpyi.s0" => "__builtin_HEXAGON_M2_vrcmpyi_s0", + "llvm.hexagon.M2.vrcmpyi.s0c" => "__builtin_HEXAGON_M2_vrcmpyi_s0c", + "llvm.hexagon.M2.vrcmpyr.s0" => "__builtin_HEXAGON_M2_vrcmpyr_s0", + "llvm.hexagon.M2.vrcmpyr.s0c" => "__builtin_HEXAGON_M2_vrcmpyr_s0c", + "llvm.hexagon.M2.vrcmpys.acc.s1" => "__builtin_HEXAGON_M2_vrcmpys_acc_s1", + "llvm.hexagon.M2.vrcmpys.s1" => "__builtin_HEXAGON_M2_vrcmpys_s1", + "llvm.hexagon.M2.vrcmpys.s1rp" => "__builtin_HEXAGON_M2_vrcmpys_s1rp", + "llvm.hexagon.M2.vrmac.s0" => "__builtin_HEXAGON_M2_vrmac_s0", + "llvm.hexagon.M2.vrmpy.s0" => "__builtin_HEXAGON_M2_vrmpy_s0", + "llvm.hexagon.M2.xor.xacc" => "__builtin_HEXAGON_M2_xor_xacc", + "llvm.hexagon.M4.and.and" => "__builtin_HEXAGON_M4_and_and", + "llvm.hexagon.M4.and.andn" => "__builtin_HEXAGON_M4_and_andn", + "llvm.hexagon.M4.and.or" => "__builtin_HEXAGON_M4_and_or", + "llvm.hexagon.M4.and.xor" => "__builtin_HEXAGON_M4_and_xor", + "llvm.hexagon.M4.cmpyi.wh" => "__builtin_HEXAGON_M4_cmpyi_wh", + "llvm.hexagon.M4.cmpyi.whc" => "__builtin_HEXAGON_M4_cmpyi_whc", + "llvm.hexagon.M4.cmpyr.wh" => "__builtin_HEXAGON_M4_cmpyr_wh", + "llvm.hexagon.M4.cmpyr.whc" => "__builtin_HEXAGON_M4_cmpyr_whc", + "llvm.hexagon.M4.mac.up.s1.sat" => "__builtin_HEXAGON_M4_mac_up_s1_sat", + "llvm.hexagon.M4.mpyri.addi" => "__builtin_HEXAGON_M4_mpyri_addi", + "llvm.hexagon.M4.mpyri.addr" => "__builtin_HEXAGON_M4_mpyri_addr", + "llvm.hexagon.M4.mpyri.addr.u2" => "__builtin_HEXAGON_M4_mpyri_addr_u2", + "llvm.hexagon.M4.mpyrr.addi" => "__builtin_HEXAGON_M4_mpyrr_addi", + "llvm.hexagon.M4.mpyrr.addr" => "__builtin_HEXAGON_M4_mpyrr_addr", + "llvm.hexagon.M4.nac.up.s1.sat" => "__builtin_HEXAGON_M4_nac_up_s1_sat", + "llvm.hexagon.M4.or.and" => "__builtin_HEXAGON_M4_or_and", + "llvm.hexagon.M4.or.andn" => "__builtin_HEXAGON_M4_or_andn", + "llvm.hexagon.M4.or.or" => "__builtin_HEXAGON_M4_or_or", + "llvm.hexagon.M4.or.xor" => "__builtin_HEXAGON_M4_or_xor", + "llvm.hexagon.M4.pmpyw" => "__builtin_HEXAGON_M4_pmpyw", + "llvm.hexagon.M4.pmpyw.acc" => "__builtin_HEXAGON_M4_pmpyw_acc", + "llvm.hexagon.M4.vpmpyh" => "__builtin_HEXAGON_M4_vpmpyh", + "llvm.hexagon.M4.vpmpyh.acc" => "__builtin_HEXAGON_M4_vpmpyh_acc", + "llvm.hexagon.M4.vrmpyeh.acc.s0" => "__builtin_HEXAGON_M4_vrmpyeh_acc_s0", + "llvm.hexagon.M4.vrmpyeh.acc.s1" => "__builtin_HEXAGON_M4_vrmpyeh_acc_s1", + "llvm.hexagon.M4.vrmpyeh.s0" => "__builtin_HEXAGON_M4_vrmpyeh_s0", + "llvm.hexagon.M4.vrmpyeh.s1" => "__builtin_HEXAGON_M4_vrmpyeh_s1", + "llvm.hexagon.M4.vrmpyoh.acc.s0" => "__builtin_HEXAGON_M4_vrmpyoh_acc_s0", + "llvm.hexagon.M4.vrmpyoh.acc.s1" => "__builtin_HEXAGON_M4_vrmpyoh_acc_s1", + "llvm.hexagon.M4.vrmpyoh.s0" => "__builtin_HEXAGON_M4_vrmpyoh_s0", + "llvm.hexagon.M4.vrmpyoh.s1" => "__builtin_HEXAGON_M4_vrmpyoh_s1", + "llvm.hexagon.M4.xor.and" => "__builtin_HEXAGON_M4_xor_and", + "llvm.hexagon.M4.xor.andn" => "__builtin_HEXAGON_M4_xor_andn", + "llvm.hexagon.M4.xor.or" => "__builtin_HEXAGON_M4_xor_or", + "llvm.hexagon.M4.xor.xacc" => "__builtin_HEXAGON_M4_xor_xacc", + "llvm.hexagon.M5.vdmacbsu" => "__builtin_HEXAGON_M5_vdmacbsu", + "llvm.hexagon.M5.vdmpybsu" => "__builtin_HEXAGON_M5_vdmpybsu", + "llvm.hexagon.M5.vmacbsu" => "__builtin_HEXAGON_M5_vmacbsu", + "llvm.hexagon.M5.vmacbuu" => "__builtin_HEXAGON_M5_vmacbuu", + "llvm.hexagon.M5.vmpybsu" => "__builtin_HEXAGON_M5_vmpybsu", + "llvm.hexagon.M5.vmpybuu" => "__builtin_HEXAGON_M5_vmpybuu", + "llvm.hexagon.M5.vrmacbsu" => "__builtin_HEXAGON_M5_vrmacbsu", + "llvm.hexagon.M5.vrmacbuu" => "__builtin_HEXAGON_M5_vrmacbuu", + "llvm.hexagon.M5.vrmpybsu" => "__builtin_HEXAGON_M5_vrmpybsu", + "llvm.hexagon.M5.vrmpybuu" => "__builtin_HEXAGON_M5_vrmpybuu", + "llvm.hexagon.S2.addasl.rrri" => "__builtin_HEXAGON_S2_addasl_rrri", + "llvm.hexagon.S2.asl.i.p" => "__builtin_HEXAGON_S2_asl_i_p", + "llvm.hexagon.S2.asl.i.p.acc" => "__builtin_HEXAGON_S2_asl_i_p_acc", + "llvm.hexagon.S2.asl.i.p.and" => "__builtin_HEXAGON_S2_asl_i_p_and", + "llvm.hexagon.S2.asl.i.p.nac" => "__builtin_HEXAGON_S2_asl_i_p_nac", + "llvm.hexagon.S2.asl.i.p.or" => "__builtin_HEXAGON_S2_asl_i_p_or", + "llvm.hexagon.S2.asl.i.p.xacc" => "__builtin_HEXAGON_S2_asl_i_p_xacc", + "llvm.hexagon.S2.asl.i.r" => "__builtin_HEXAGON_S2_asl_i_r", + "llvm.hexagon.S2.asl.i.r.acc" => "__builtin_HEXAGON_S2_asl_i_r_acc", + "llvm.hexagon.S2.asl.i.r.and" => "__builtin_HEXAGON_S2_asl_i_r_and", + "llvm.hexagon.S2.asl.i.r.nac" => "__builtin_HEXAGON_S2_asl_i_r_nac", + "llvm.hexagon.S2.asl.i.r.or" => "__builtin_HEXAGON_S2_asl_i_r_or", + "llvm.hexagon.S2.asl.i.r.sat" => "__builtin_HEXAGON_S2_asl_i_r_sat", + "llvm.hexagon.S2.asl.i.r.xacc" => "__builtin_HEXAGON_S2_asl_i_r_xacc", + "llvm.hexagon.S2.asl.i.vh" => "__builtin_HEXAGON_S2_asl_i_vh", + "llvm.hexagon.S2.asl.i.vw" => "__builtin_HEXAGON_S2_asl_i_vw", + "llvm.hexagon.S2.asl.r.p" => "__builtin_HEXAGON_S2_asl_r_p", + "llvm.hexagon.S2.asl.r.p.acc" => "__builtin_HEXAGON_S2_asl_r_p_acc", + "llvm.hexagon.S2.asl.r.p.and" => "__builtin_HEXAGON_S2_asl_r_p_and", + "llvm.hexagon.S2.asl.r.p.nac" => "__builtin_HEXAGON_S2_asl_r_p_nac", + "llvm.hexagon.S2.asl.r.p.or" => "__builtin_HEXAGON_S2_asl_r_p_or", + "llvm.hexagon.S2.asl.r.p.xor" => "__builtin_HEXAGON_S2_asl_r_p_xor", + "llvm.hexagon.S2.asl.r.r" => "__builtin_HEXAGON_S2_asl_r_r", + "llvm.hexagon.S2.asl.r.r.acc" => "__builtin_HEXAGON_S2_asl_r_r_acc", + "llvm.hexagon.S2.asl.r.r.and" => "__builtin_HEXAGON_S2_asl_r_r_and", + "llvm.hexagon.S2.asl.r.r.nac" => "__builtin_HEXAGON_S2_asl_r_r_nac", + "llvm.hexagon.S2.asl.r.r.or" => "__builtin_HEXAGON_S2_asl_r_r_or", + "llvm.hexagon.S2.asl.r.r.sat" => "__builtin_HEXAGON_S2_asl_r_r_sat", + "llvm.hexagon.S2.asl.r.vh" => "__builtin_HEXAGON_S2_asl_r_vh", + "llvm.hexagon.S2.asl.r.vw" => "__builtin_HEXAGON_S2_asl_r_vw", + "llvm.hexagon.S2.asr.i.p" => "__builtin_HEXAGON_S2_asr_i_p", + "llvm.hexagon.S2.asr.i.p.acc" => "__builtin_HEXAGON_S2_asr_i_p_acc", + "llvm.hexagon.S2.asr.i.p.and" => "__builtin_HEXAGON_S2_asr_i_p_and", + "llvm.hexagon.S2.asr.i.p.nac" => "__builtin_HEXAGON_S2_asr_i_p_nac", + "llvm.hexagon.S2.asr.i.p.or" => "__builtin_HEXAGON_S2_asr_i_p_or", + "llvm.hexagon.S2.asr.i.p.rnd" => "__builtin_HEXAGON_S2_asr_i_p_rnd", + "llvm.hexagon.S2.asr.i.p.rnd.goodsyntax" => "__builtin_HEXAGON_S2_asr_i_p_rnd_goodsyntax", + "llvm.hexagon.S2.asr.i.r" => "__builtin_HEXAGON_S2_asr_i_r", + "llvm.hexagon.S2.asr.i.r.acc" => "__builtin_HEXAGON_S2_asr_i_r_acc", + "llvm.hexagon.S2.asr.i.r.and" => "__builtin_HEXAGON_S2_asr_i_r_and", + "llvm.hexagon.S2.asr.i.r.nac" => "__builtin_HEXAGON_S2_asr_i_r_nac", + "llvm.hexagon.S2.asr.i.r.or" => "__builtin_HEXAGON_S2_asr_i_r_or", + "llvm.hexagon.S2.asr.i.r.rnd" => "__builtin_HEXAGON_S2_asr_i_r_rnd", + "llvm.hexagon.S2.asr.i.r.rnd.goodsyntax" => "__builtin_HEXAGON_S2_asr_i_r_rnd_goodsyntax", + "llvm.hexagon.S2.asr.i.svw.trun" => "__builtin_HEXAGON_S2_asr_i_svw_trun", + "llvm.hexagon.S2.asr.i.vh" => "__builtin_HEXAGON_S2_asr_i_vh", + "llvm.hexagon.S2.asr.i.vw" => "__builtin_HEXAGON_S2_asr_i_vw", + "llvm.hexagon.S2.asr.r.p" => "__builtin_HEXAGON_S2_asr_r_p", + "llvm.hexagon.S2.asr.r.p.acc" => "__builtin_HEXAGON_S2_asr_r_p_acc", + "llvm.hexagon.S2.asr.r.p.and" => "__builtin_HEXAGON_S2_asr_r_p_and", + "llvm.hexagon.S2.asr.r.p.nac" => "__builtin_HEXAGON_S2_asr_r_p_nac", + "llvm.hexagon.S2.asr.r.p.or" => "__builtin_HEXAGON_S2_asr_r_p_or", + "llvm.hexagon.S2.asr.r.p.xor" => "__builtin_HEXAGON_S2_asr_r_p_xor", + "llvm.hexagon.S2.asr.r.r" => "__builtin_HEXAGON_S2_asr_r_r", + "llvm.hexagon.S2.asr.r.r.acc" => "__builtin_HEXAGON_S2_asr_r_r_acc", + "llvm.hexagon.S2.asr.r.r.and" => "__builtin_HEXAGON_S2_asr_r_r_and", + "llvm.hexagon.S2.asr.r.r.nac" => "__builtin_HEXAGON_S2_asr_r_r_nac", + "llvm.hexagon.S2.asr.r.r.or" => "__builtin_HEXAGON_S2_asr_r_r_or", + "llvm.hexagon.S2.asr.r.r.sat" => "__builtin_HEXAGON_S2_asr_r_r_sat", + "llvm.hexagon.S2.asr.r.svw.trun" => "__builtin_HEXAGON_S2_asr_r_svw_trun", + "llvm.hexagon.S2.asr.r.vh" => "__builtin_HEXAGON_S2_asr_r_vh", + "llvm.hexagon.S2.asr.r.vw" => "__builtin_HEXAGON_S2_asr_r_vw", + "llvm.hexagon.S2.brev" => "__builtin_HEXAGON_S2_brev", + "llvm.hexagon.S2.brevp" => "__builtin_HEXAGON_S2_brevp", + "llvm.hexagon.S2.cl0" => "__builtin_HEXAGON_S2_cl0", + "llvm.hexagon.S2.cl0p" => "__builtin_HEXAGON_S2_cl0p", + "llvm.hexagon.S2.cl1" => "__builtin_HEXAGON_S2_cl1", + "llvm.hexagon.S2.cl1p" => "__builtin_HEXAGON_S2_cl1p", + "llvm.hexagon.S2.clb" => "__builtin_HEXAGON_S2_clb", + "llvm.hexagon.S2.clbnorm" => "__builtin_HEXAGON_S2_clbnorm", + "llvm.hexagon.S2.clbp" => "__builtin_HEXAGON_S2_clbp", + "llvm.hexagon.S2.clrbit.i" => "__builtin_HEXAGON_S2_clrbit_i", + "llvm.hexagon.S2.clrbit.r" => "__builtin_HEXAGON_S2_clrbit_r", + "llvm.hexagon.S2.ct0" => "__builtin_HEXAGON_S2_ct0", + "llvm.hexagon.S2.ct0p" => "__builtin_HEXAGON_S2_ct0p", + "llvm.hexagon.S2.ct1" => "__builtin_HEXAGON_S2_ct1", + "llvm.hexagon.S2.ct1p" => "__builtin_HEXAGON_S2_ct1p", + "llvm.hexagon.S2.deinterleave" => "__builtin_HEXAGON_S2_deinterleave", + "llvm.hexagon.S2.extractu" => "__builtin_HEXAGON_S2_extractu", + "llvm.hexagon.S2.extractu.rp" => "__builtin_HEXAGON_S2_extractu_rp", + "llvm.hexagon.S2.extractup" => "__builtin_HEXAGON_S2_extractup", + "llvm.hexagon.S2.extractup.rp" => "__builtin_HEXAGON_S2_extractup_rp", + "llvm.hexagon.S2.insert" => "__builtin_HEXAGON_S2_insert", + "llvm.hexagon.S2.insert.rp" => "__builtin_HEXAGON_S2_insert_rp", + "llvm.hexagon.S2.insertp" => "__builtin_HEXAGON_S2_insertp", + "llvm.hexagon.S2.insertp.rp" => "__builtin_HEXAGON_S2_insertp_rp", + "llvm.hexagon.S2.interleave" => "__builtin_HEXAGON_S2_interleave", + "llvm.hexagon.S2.lfsp" => "__builtin_HEXAGON_S2_lfsp", + "llvm.hexagon.S2.lsl.r.p" => "__builtin_HEXAGON_S2_lsl_r_p", + "llvm.hexagon.S2.lsl.r.p.acc" => "__builtin_HEXAGON_S2_lsl_r_p_acc", + "llvm.hexagon.S2.lsl.r.p.and" => "__builtin_HEXAGON_S2_lsl_r_p_and", + "llvm.hexagon.S2.lsl.r.p.nac" => "__builtin_HEXAGON_S2_lsl_r_p_nac", + "llvm.hexagon.S2.lsl.r.p.or" => "__builtin_HEXAGON_S2_lsl_r_p_or", + "llvm.hexagon.S2.lsl.r.p.xor" => "__builtin_HEXAGON_S2_lsl_r_p_xor", + "llvm.hexagon.S2.lsl.r.r" => "__builtin_HEXAGON_S2_lsl_r_r", + "llvm.hexagon.S2.lsl.r.r.acc" => "__builtin_HEXAGON_S2_lsl_r_r_acc", + "llvm.hexagon.S2.lsl.r.r.and" => "__builtin_HEXAGON_S2_lsl_r_r_and", + "llvm.hexagon.S2.lsl.r.r.nac" => "__builtin_HEXAGON_S2_lsl_r_r_nac", + "llvm.hexagon.S2.lsl.r.r.or" => "__builtin_HEXAGON_S2_lsl_r_r_or", + "llvm.hexagon.S2.lsl.r.vh" => "__builtin_HEXAGON_S2_lsl_r_vh", + "llvm.hexagon.S2.lsl.r.vw" => "__builtin_HEXAGON_S2_lsl_r_vw", + "llvm.hexagon.S2.lsr.i.p" => "__builtin_HEXAGON_S2_lsr_i_p", + "llvm.hexagon.S2.lsr.i.p.acc" => "__builtin_HEXAGON_S2_lsr_i_p_acc", + "llvm.hexagon.S2.lsr.i.p.and" => "__builtin_HEXAGON_S2_lsr_i_p_and", + "llvm.hexagon.S2.lsr.i.p.nac" => "__builtin_HEXAGON_S2_lsr_i_p_nac", + "llvm.hexagon.S2.lsr.i.p.or" => "__builtin_HEXAGON_S2_lsr_i_p_or", + "llvm.hexagon.S2.lsr.i.p.xacc" => "__builtin_HEXAGON_S2_lsr_i_p_xacc", + "llvm.hexagon.S2.lsr.i.r" => "__builtin_HEXAGON_S2_lsr_i_r", + "llvm.hexagon.S2.lsr.i.r.acc" => "__builtin_HEXAGON_S2_lsr_i_r_acc", + "llvm.hexagon.S2.lsr.i.r.and" => "__builtin_HEXAGON_S2_lsr_i_r_and", + "llvm.hexagon.S2.lsr.i.r.nac" => "__builtin_HEXAGON_S2_lsr_i_r_nac", + "llvm.hexagon.S2.lsr.i.r.or" => "__builtin_HEXAGON_S2_lsr_i_r_or", + "llvm.hexagon.S2.lsr.i.r.xacc" => "__builtin_HEXAGON_S2_lsr_i_r_xacc", + "llvm.hexagon.S2.lsr.i.vh" => "__builtin_HEXAGON_S2_lsr_i_vh", + "llvm.hexagon.S2.lsr.i.vw" => "__builtin_HEXAGON_S2_lsr_i_vw", + "llvm.hexagon.S2.lsr.r.p" => "__builtin_HEXAGON_S2_lsr_r_p", + "llvm.hexagon.S2.lsr.r.p.acc" => "__builtin_HEXAGON_S2_lsr_r_p_acc", + "llvm.hexagon.S2.lsr.r.p.and" => "__builtin_HEXAGON_S2_lsr_r_p_and", + "llvm.hexagon.S2.lsr.r.p.nac" => "__builtin_HEXAGON_S2_lsr_r_p_nac", + "llvm.hexagon.S2.lsr.r.p.or" => "__builtin_HEXAGON_S2_lsr_r_p_or", + "llvm.hexagon.S2.lsr.r.p.xor" => "__builtin_HEXAGON_S2_lsr_r_p_xor", + "llvm.hexagon.S2.lsr.r.r" => "__builtin_HEXAGON_S2_lsr_r_r", + "llvm.hexagon.S2.lsr.r.r.acc" => "__builtin_HEXAGON_S2_lsr_r_r_acc", + "llvm.hexagon.S2.lsr.r.r.and" => "__builtin_HEXAGON_S2_lsr_r_r_and", + "llvm.hexagon.S2.lsr.r.r.nac" => "__builtin_HEXAGON_S2_lsr_r_r_nac", + "llvm.hexagon.S2.lsr.r.r.or" => "__builtin_HEXAGON_S2_lsr_r_r_or", + "llvm.hexagon.S2.lsr.r.vh" => "__builtin_HEXAGON_S2_lsr_r_vh", + "llvm.hexagon.S2.lsr.r.vw" => "__builtin_HEXAGON_S2_lsr_r_vw", + "llvm.hexagon.S2.packhl" => "__builtin_HEXAGON_S2_packhl", + "llvm.hexagon.S2.parityp" => "__builtin_HEXAGON_S2_parityp", + "llvm.hexagon.S2.setbit.i" => "__builtin_HEXAGON_S2_setbit_i", + "llvm.hexagon.S2.setbit.r" => "__builtin_HEXAGON_S2_setbit_r", + "llvm.hexagon.S2.shuffeb" => "__builtin_HEXAGON_S2_shuffeb", + "llvm.hexagon.S2.shuffeh" => "__builtin_HEXAGON_S2_shuffeh", + "llvm.hexagon.S2.shuffob" => "__builtin_HEXAGON_S2_shuffob", + "llvm.hexagon.S2.shuffoh" => "__builtin_HEXAGON_S2_shuffoh", + "llvm.hexagon.S2.svsathb" => "__builtin_HEXAGON_S2_svsathb", + "llvm.hexagon.S2.svsathub" => "__builtin_HEXAGON_S2_svsathub", + "llvm.hexagon.S2.tableidxb.goodsyntax" => "__builtin_HEXAGON_S2_tableidxb_goodsyntax", + "llvm.hexagon.S2.tableidxd.goodsyntax" => "__builtin_HEXAGON_S2_tableidxd_goodsyntax", + "llvm.hexagon.S2.tableidxh.goodsyntax" => "__builtin_HEXAGON_S2_tableidxh_goodsyntax", + "llvm.hexagon.S2.tableidxw.goodsyntax" => "__builtin_HEXAGON_S2_tableidxw_goodsyntax", + "llvm.hexagon.S2.togglebit.i" => "__builtin_HEXAGON_S2_togglebit_i", + "llvm.hexagon.S2.togglebit.r" => "__builtin_HEXAGON_S2_togglebit_r", + "llvm.hexagon.S2.tstbit.i" => "__builtin_HEXAGON_S2_tstbit_i", + "llvm.hexagon.S2.tstbit.r" => "__builtin_HEXAGON_S2_tstbit_r", + "llvm.hexagon.S2.valignib" => "__builtin_HEXAGON_S2_valignib", + "llvm.hexagon.S2.valignrb" => "__builtin_HEXAGON_S2_valignrb", + "llvm.hexagon.S2.vcnegh" => "__builtin_HEXAGON_S2_vcnegh", + "llvm.hexagon.S2.vcrotate" => "__builtin_HEXAGON_S2_vcrotate", + "llvm.hexagon.S2.vrcnegh" => "__builtin_HEXAGON_S2_vrcnegh", + "llvm.hexagon.S2.vrndpackwh" => "__builtin_HEXAGON_S2_vrndpackwh", + "llvm.hexagon.S2.vrndpackwhs" => "__builtin_HEXAGON_S2_vrndpackwhs", + "llvm.hexagon.S2.vsathb" => "__builtin_HEXAGON_S2_vsathb", + "llvm.hexagon.S2.vsathb.nopack" => "__builtin_HEXAGON_S2_vsathb_nopack", + "llvm.hexagon.S2.vsathub" => "__builtin_HEXAGON_S2_vsathub", + "llvm.hexagon.S2.vsathub.nopack" => "__builtin_HEXAGON_S2_vsathub_nopack", + "llvm.hexagon.S2.vsatwh" => "__builtin_HEXAGON_S2_vsatwh", + "llvm.hexagon.S2.vsatwh.nopack" => "__builtin_HEXAGON_S2_vsatwh_nopack", + "llvm.hexagon.S2.vsatwuh" => "__builtin_HEXAGON_S2_vsatwuh", + "llvm.hexagon.S2.vsatwuh.nopack" => "__builtin_HEXAGON_S2_vsatwuh_nopack", + "llvm.hexagon.S2.vsplatrb" => "__builtin_HEXAGON_S2_vsplatrb", + "llvm.hexagon.S2.vsplatrh" => "__builtin_HEXAGON_S2_vsplatrh", + "llvm.hexagon.S2.vspliceib" => "__builtin_HEXAGON_S2_vspliceib", + "llvm.hexagon.S2.vsplicerb" => "__builtin_HEXAGON_S2_vsplicerb", + "llvm.hexagon.S2.vsxtbh" => "__builtin_HEXAGON_S2_vsxtbh", + "llvm.hexagon.S2.vsxthw" => "__builtin_HEXAGON_S2_vsxthw", + "llvm.hexagon.S2.vtrunehb" => "__builtin_HEXAGON_S2_vtrunehb", + "llvm.hexagon.S2.vtrunewh" => "__builtin_HEXAGON_S2_vtrunewh", + "llvm.hexagon.S2.vtrunohb" => "__builtin_HEXAGON_S2_vtrunohb", + "llvm.hexagon.S2.vtrunowh" => "__builtin_HEXAGON_S2_vtrunowh", + "llvm.hexagon.S2.vzxtbh" => "__builtin_HEXAGON_S2_vzxtbh", + "llvm.hexagon.S2.vzxthw" => "__builtin_HEXAGON_S2_vzxthw", + "llvm.hexagon.S4.addaddi" => "__builtin_HEXAGON_S4_addaddi", + "llvm.hexagon.S4.addi.asl.ri" => "__builtin_HEXAGON_S4_addi_asl_ri", + "llvm.hexagon.S4.addi.lsr.ri" => "__builtin_HEXAGON_S4_addi_lsr_ri", + "llvm.hexagon.S4.andi.asl.ri" => "__builtin_HEXAGON_S4_andi_asl_ri", + "llvm.hexagon.S4.andi.lsr.ri" => "__builtin_HEXAGON_S4_andi_lsr_ri", + "llvm.hexagon.S4.clbaddi" => "__builtin_HEXAGON_S4_clbaddi", + "llvm.hexagon.S4.clbpaddi" => "__builtin_HEXAGON_S4_clbpaddi", + "llvm.hexagon.S4.clbpnorm" => "__builtin_HEXAGON_S4_clbpnorm", + "llvm.hexagon.S4.extract" => "__builtin_HEXAGON_S4_extract", + "llvm.hexagon.S4.extract.rp" => "__builtin_HEXAGON_S4_extract_rp", + "llvm.hexagon.S4.extractp" => "__builtin_HEXAGON_S4_extractp", + "llvm.hexagon.S4.extractp.rp" => "__builtin_HEXAGON_S4_extractp_rp", + "llvm.hexagon.S4.lsli" => "__builtin_HEXAGON_S4_lsli", + "llvm.hexagon.S4.ntstbit.i" => "__builtin_HEXAGON_S4_ntstbit_i", + "llvm.hexagon.S4.ntstbit.r" => "__builtin_HEXAGON_S4_ntstbit_r", + "llvm.hexagon.S4.or.andi" => "__builtin_HEXAGON_S4_or_andi", + "llvm.hexagon.S4.or.andix" => "__builtin_HEXAGON_S4_or_andix", + "llvm.hexagon.S4.or.ori" => "__builtin_HEXAGON_S4_or_ori", + "llvm.hexagon.S4.ori.asl.ri" => "__builtin_HEXAGON_S4_ori_asl_ri", + "llvm.hexagon.S4.ori.lsr.ri" => "__builtin_HEXAGON_S4_ori_lsr_ri", + "llvm.hexagon.S4.parity" => "__builtin_HEXAGON_S4_parity", + "llvm.hexagon.S4.subaddi" => "__builtin_HEXAGON_S4_subaddi", + "llvm.hexagon.S4.subi.asl.ri" => "__builtin_HEXAGON_S4_subi_asl_ri", + "llvm.hexagon.S4.subi.lsr.ri" => "__builtin_HEXAGON_S4_subi_lsr_ri", + "llvm.hexagon.S4.vrcrotate" => "__builtin_HEXAGON_S4_vrcrotate", + "llvm.hexagon.S4.vrcrotate.acc" => "__builtin_HEXAGON_S4_vrcrotate_acc", + "llvm.hexagon.S4.vxaddsubh" => "__builtin_HEXAGON_S4_vxaddsubh", + "llvm.hexagon.S4.vxaddsubhr" => "__builtin_HEXAGON_S4_vxaddsubhr", + "llvm.hexagon.S4.vxaddsubw" => "__builtin_HEXAGON_S4_vxaddsubw", + "llvm.hexagon.S4.vxsubaddh" => "__builtin_HEXAGON_S4_vxsubaddh", + "llvm.hexagon.S4.vxsubaddhr" => "__builtin_HEXAGON_S4_vxsubaddhr", + "llvm.hexagon.S4.vxsubaddw" => "__builtin_HEXAGON_S4_vxsubaddw", + "llvm.hexagon.S5.asrhub.rnd.sat.goodsyntax" => "__builtin_HEXAGON_S5_asrhub_rnd_sat_goodsyntax", + "llvm.hexagon.S5.asrhub.sat" => "__builtin_HEXAGON_S5_asrhub_sat", + "llvm.hexagon.S5.popcountp" => "__builtin_HEXAGON_S5_popcountp", + "llvm.hexagon.S5.vasrhrnd.goodsyntax" => "__builtin_HEXAGON_S5_vasrhrnd_goodsyntax", + "llvm.hexagon.SI.to.SXTHI.asrh" => "__builtin_SI_to_SXTHI_asrh", + "llvm.hexagon.circ.ldd" => "__builtin_circ_ldd", // mips "llvm.mips.absq.s.ph" => "__builtin_mips_absq_s_ph", "llvm.mips.absq.s.qb" => "__builtin_mips_absq_s_qb", @@ -887,7 +1775,531 @@ match name { "llvm.mips.xor.v" => "__builtin_msa_xor_v", "llvm.mips.xori.b" => "__builtin_msa_xori_b", // nvvm + "llvm.nvvm.abs.i" => "__nvvm_abs_i", + "llvm.nvvm.abs.ll" => "__nvvm_abs_ll", + "llvm.nvvm.add.rm.d" => "__nvvm_add_rm_d", + "llvm.nvvm.add.rm.f" => "__nvvm_add_rm_f", + "llvm.nvvm.add.rm.ftz.f" => "__nvvm_add_rm_ftz_f", + "llvm.nvvm.add.rn.d" => "__nvvm_add_rn_d", + "llvm.nvvm.add.rn.f" => "__nvvm_add_rn_f", + "llvm.nvvm.add.rn.ftz.f" => "__nvvm_add_rn_ftz_f", + "llvm.nvvm.add.rp.d" => "__nvvm_add_rp_d", + "llvm.nvvm.add.rp.f" => "__nvvm_add_rp_f", + "llvm.nvvm.add.rp.ftz.f" => "__nvvm_add_rp_ftz_f", + "llvm.nvvm.add.rz.d" => "__nvvm_add_rz_d", + "llvm.nvvm.add.rz.f" => "__nvvm_add_rz_f", + "llvm.nvvm.add.rz.ftz.f" => "__nvvm_add_rz_ftz_f", + "llvm.nvvm.barrier0" => "__nvvm_bar0", + "llvm.nvvm.barrier0.and" => "__nvvm_bar0_and", + "llvm.nvvm.barrier0.or" => "__nvvm_bar0_or", + "llvm.nvvm.barrier0.popc" => "__nvvm_bar0_popc", + "llvm.nvvm.bitcast.d2ll" => "__nvvm_bitcast_d2ll", + "llvm.nvvm.bitcast.f2i" => "__nvvm_bitcast_f2i", + "llvm.nvvm.bitcast.i2f" => "__nvvm_bitcast_i2f", + "llvm.nvvm.bitcast.ll2d" => "__nvvm_bitcast_ll2d", + "llvm.nvvm.brev32" => "__nvvm_brev32", + "llvm.nvvm.brev64" => "__nvvm_brev64", + "llvm.nvvm.ceil.d" => "__nvvm_ceil_d", + "llvm.nvvm.ceil.f" => "__nvvm_ceil_f", + "llvm.nvvm.ceil.ftz.f" => "__nvvm_ceil_ftz_f", + "llvm.nvvm.clz.i" => "__nvvm_clz_i", + "llvm.nvvm.clz.ll" => "__nvvm_clz_ll", + "llvm.nvvm.cos.approx.f" => "__nvvm_cos_approx_f", + "llvm.nvvm.cos.approx.ftz.f" => "__nvvm_cos_approx_ftz_f", + "llvm.nvvm.d2f.rm" => "__nvvm_d2f_rm", + "llvm.nvvm.d2f.rm.ftz" => "__nvvm_d2f_rm_ftz", + "llvm.nvvm.d2f.rn" => "__nvvm_d2f_rn", + "llvm.nvvm.d2f.rn.ftz" => "__nvvm_d2f_rn_ftz", + "llvm.nvvm.d2f.rp" => "__nvvm_d2f_rp", + "llvm.nvvm.d2f.rp.ftz" => "__nvvm_d2f_rp_ftz", + "llvm.nvvm.d2f.rz" => "__nvvm_d2f_rz", + "llvm.nvvm.d2f.rz.ftz" => "__nvvm_d2f_rz_ftz", + "llvm.nvvm.d2i.hi" => "__nvvm_d2i_hi", + "llvm.nvvm.d2i.lo" => "__nvvm_d2i_lo", + "llvm.nvvm.d2i.rm" => "__nvvm_d2i_rm", + "llvm.nvvm.d2i.rn" => "__nvvm_d2i_rn", + "llvm.nvvm.d2i.rp" => "__nvvm_d2i_rp", + "llvm.nvvm.d2i.rz" => "__nvvm_d2i_rz", + "llvm.nvvm.d2ll.rm" => "__nvvm_d2ll_rm", + "llvm.nvvm.d2ll.rn" => "__nvvm_d2ll_rn", + "llvm.nvvm.d2ll.rp" => "__nvvm_d2ll_rp", + "llvm.nvvm.d2ll.rz" => "__nvvm_d2ll_rz", + "llvm.nvvm.d2ui.rm" => "__nvvm_d2ui_rm", + "llvm.nvvm.d2ui.rn" => "__nvvm_d2ui_rn", + "llvm.nvvm.d2ui.rp" => "__nvvm_d2ui_rp", + "llvm.nvvm.d2ui.rz" => "__nvvm_d2ui_rz", + "llvm.nvvm.d2ull.rm" => "__nvvm_d2ull_rm", + "llvm.nvvm.d2ull.rn" => "__nvvm_d2ull_rn", + "llvm.nvvm.d2ull.rp" => "__nvvm_d2ull_rp", + "llvm.nvvm.d2ull.rz" => "__nvvm_d2ull_rz", + "llvm.nvvm.div.approx.f" => "__nvvm_div_approx_f", + "llvm.nvvm.div.approx.ftz.f" => "__nvvm_div_approx_ftz_f", + "llvm.nvvm.div.rm.d" => "__nvvm_div_rm_d", + "llvm.nvvm.div.rm.f" => "__nvvm_div_rm_f", + "llvm.nvvm.div.rm.ftz.f" => "__nvvm_div_rm_ftz_f", + "llvm.nvvm.div.rn.d" => "__nvvm_div_rn_d", + "llvm.nvvm.div.rn.f" => "__nvvm_div_rn_f", + "llvm.nvvm.div.rn.ftz.f" => "__nvvm_div_rn_ftz_f", + "llvm.nvvm.div.rp.d" => "__nvvm_div_rp_d", + "llvm.nvvm.div.rp.f" => "__nvvm_div_rp_f", + "llvm.nvvm.div.rp.ftz.f" => "__nvvm_div_rp_ftz_f", + "llvm.nvvm.div.rz.d" => "__nvvm_div_rz_d", + "llvm.nvvm.div.rz.f" => "__nvvm_div_rz_f", + "llvm.nvvm.div.rz.ftz.f" => "__nvvm_div_rz_ftz_f", + "llvm.nvvm.ex2.approx.d" => "__nvvm_ex2_approx_d", + "llvm.nvvm.ex2.approx.f" => "__nvvm_ex2_approx_f", + "llvm.nvvm.ex2.approx.ftz.f" => "__nvvm_ex2_approx_ftz_f", + "llvm.nvvm.f2h.rn" => "__nvvm_f2h_rn", + "llvm.nvvm.f2h.rn.ftz" => "__nvvm_f2h_rn_ftz", + "llvm.nvvm.f2i.rm" => "__nvvm_f2i_rm", + "llvm.nvvm.f2i.rm.ftz" => "__nvvm_f2i_rm_ftz", + "llvm.nvvm.f2i.rn" => "__nvvm_f2i_rn", + "llvm.nvvm.f2i.rn.ftz" => "__nvvm_f2i_rn_ftz", + "llvm.nvvm.f2i.rp" => "__nvvm_f2i_rp", + "llvm.nvvm.f2i.rp.ftz" => "__nvvm_f2i_rp_ftz", + "llvm.nvvm.f2i.rz" => "__nvvm_f2i_rz", + "llvm.nvvm.f2i.rz.ftz" => "__nvvm_f2i_rz_ftz", + "llvm.nvvm.f2ll.rm" => "__nvvm_f2ll_rm", + "llvm.nvvm.f2ll.rm.ftz" => "__nvvm_f2ll_rm_ftz", + "llvm.nvvm.f2ll.rn" => "__nvvm_f2ll_rn", + "llvm.nvvm.f2ll.rn.ftz" => "__nvvm_f2ll_rn_ftz", + "llvm.nvvm.f2ll.rp" => "__nvvm_f2ll_rp", + "llvm.nvvm.f2ll.rp.ftz" => "__nvvm_f2ll_rp_ftz", + "llvm.nvvm.f2ll.rz" => "__nvvm_f2ll_rz", + "llvm.nvvm.f2ll.rz.ftz" => "__nvvm_f2ll_rz_ftz", + "llvm.nvvm.f2ui.rm" => "__nvvm_f2ui_rm", + "llvm.nvvm.f2ui.rm.ftz" => "__nvvm_f2ui_rm_ftz", + "llvm.nvvm.f2ui.rn" => "__nvvm_f2ui_rn", + "llvm.nvvm.f2ui.rn.ftz" => "__nvvm_f2ui_rn_ftz", + "llvm.nvvm.f2ui.rp" => "__nvvm_f2ui_rp", + "llvm.nvvm.f2ui.rp.ftz" => "__nvvm_f2ui_rp_ftz", + "llvm.nvvm.f2ui.rz" => "__nvvm_f2ui_rz", + "llvm.nvvm.f2ui.rz.ftz" => "__nvvm_f2ui_rz_ftz", + "llvm.nvvm.f2ull.rm" => "__nvvm_f2ull_rm", + "llvm.nvvm.f2ull.rm.ftz" => "__nvvm_f2ull_rm_ftz", + "llvm.nvvm.f2ull.rn" => "__nvvm_f2ull_rn", + "llvm.nvvm.f2ull.rn.ftz" => "__nvvm_f2ull_rn_ftz", + "llvm.nvvm.f2ull.rp" => "__nvvm_f2ull_rp", + "llvm.nvvm.f2ull.rp.ftz" => "__nvvm_f2ull_rp_ftz", + "llvm.nvvm.f2ull.rz" => "__nvvm_f2ull_rz", + "llvm.nvvm.f2ull.rz.ftz" => "__nvvm_f2ull_rz_ftz", + "llvm.nvvm.fabs.d" => "__nvvm_fabs_d", + "llvm.nvvm.fabs.f" => "__nvvm_fabs_f", + "llvm.nvvm.fabs.ftz.f" => "__nvvm_fabs_ftz_f", + "llvm.nvvm.floor.d" => "__nvvm_floor_d", + "llvm.nvvm.floor.f" => "__nvvm_floor_f", + "llvm.nvvm.floor.ftz.f" => "__nvvm_floor_ftz_f", + "llvm.nvvm.fma.rm.d" => "__nvvm_fma_rm_d", + "llvm.nvvm.fma.rm.f" => "__nvvm_fma_rm_f", + "llvm.nvvm.fma.rm.ftz.f" => "__nvvm_fma_rm_ftz_f", + "llvm.nvvm.fma.rn.d" => "__nvvm_fma_rn_d", + "llvm.nvvm.fma.rn.f" => "__nvvm_fma_rn_f", + "llvm.nvvm.fma.rn.ftz.f" => "__nvvm_fma_rn_ftz_f", + "llvm.nvvm.fma.rp.d" => "__nvvm_fma_rp_d", + "llvm.nvvm.fma.rp.f" => "__nvvm_fma_rp_f", + "llvm.nvvm.fma.rp.ftz.f" => "__nvvm_fma_rp_ftz_f", + "llvm.nvvm.fma.rz.d" => "__nvvm_fma_rz_d", + "llvm.nvvm.fma.rz.f" => "__nvvm_fma_rz_f", + "llvm.nvvm.fma.rz.ftz.f" => "__nvvm_fma_rz_ftz_f", + "llvm.nvvm.fmax.d" => "__nvvm_fmax_d", + "llvm.nvvm.fmax.f" => "__nvvm_fmax_f", + "llvm.nvvm.fmax.ftz.f" => "__nvvm_fmax_ftz_f", + "llvm.nvvm.fmin.d" => "__nvvm_fmin_d", + "llvm.nvvm.fmin.f" => "__nvvm_fmin_f", + "llvm.nvvm.fmin.ftz.f" => "__nvvm_fmin_ftz_f", + "llvm.nvvm.h2f" => "__nvvm_h2f", + "llvm.nvvm.i2d.rm" => "__nvvm_i2d_rm", + "llvm.nvvm.i2d.rn" => "__nvvm_i2d_rn", + "llvm.nvvm.i2d.rp" => "__nvvm_i2d_rp", + "llvm.nvvm.i2d.rz" => "__nvvm_i2d_rz", + "llvm.nvvm.i2f.rm" => "__nvvm_i2f_rm", + "llvm.nvvm.i2f.rn" => "__nvvm_i2f_rn", + "llvm.nvvm.i2f.rp" => "__nvvm_i2f_rp", + "llvm.nvvm.i2f.rz" => "__nvvm_i2f_rz", + "llvm.nvvm.isspacep.const" => "__nvvm_isspacep_const", + "llvm.nvvm.isspacep.global" => "__nvvm_isspacep_global", + "llvm.nvvm.isspacep.local" => "__nvvm_isspacep_local", + "llvm.nvvm.isspacep.shared" => "__nvvm_isspacep_shared", + "llvm.nvvm.istypep.sampler" => "__nvvm_istypep_sampler", + "llvm.nvvm.istypep.surface" => "__nvvm_istypep_surface", + "llvm.nvvm.istypep.texture" => "__nvvm_istypep_texture", + "llvm.nvvm.lg2.approx.d" => "__nvvm_lg2_approx_d", + "llvm.nvvm.lg2.approx.f" => "__nvvm_lg2_approx_f", + "llvm.nvvm.lg2.approx.ftz.f" => "__nvvm_lg2_approx_ftz_f", + "llvm.nvvm.ll2d.rm" => "__nvvm_ll2d_rm", + "llvm.nvvm.ll2d.rn" => "__nvvm_ll2d_rn", + "llvm.nvvm.ll2d.rp" => "__nvvm_ll2d_rp", + "llvm.nvvm.ll2d.rz" => "__nvvm_ll2d_rz", + "llvm.nvvm.ll2f.rm" => "__nvvm_ll2f_rm", + "llvm.nvvm.ll2f.rn" => "__nvvm_ll2f_rn", + "llvm.nvvm.ll2f.rp" => "__nvvm_ll2f_rp", + "llvm.nvvm.ll2f.rz" => "__nvvm_ll2f_rz", + "llvm.nvvm.lohi.i2d" => "__nvvm_lohi_i2d", + "llvm.nvvm.max.i" => "__nvvm_max_i", + "llvm.nvvm.max.ll" => "__nvvm_max_ll", + "llvm.nvvm.max.ui" => "__nvvm_max_ui", + "llvm.nvvm.max.ull" => "__nvvm_max_ull", + "llvm.nvvm.membar.cta" => "__nvvm_membar_cta", + "llvm.nvvm.membar.gl" => "__nvvm_membar_gl", + "llvm.nvvm.membar.sys" => "__nvvm_membar_sys", + "llvm.nvvm.min.i" => "__nvvm_min_i", + "llvm.nvvm.min.ll" => "__nvvm_min_ll", + "llvm.nvvm.min.ui" => "__nvvm_min_ui", + "llvm.nvvm.min.ull" => "__nvvm_min_ull", + "llvm.nvvm.mul.rm.d" => "__nvvm_mul_rm_d", + "llvm.nvvm.mul.rm.f" => "__nvvm_mul_rm_f", + "llvm.nvvm.mul.rm.ftz.f" => "__nvvm_mul_rm_ftz_f", + "llvm.nvvm.mul.rn.d" => "__nvvm_mul_rn_d", + "llvm.nvvm.mul.rn.f" => "__nvvm_mul_rn_f", + "llvm.nvvm.mul.rn.ftz.f" => "__nvvm_mul_rn_ftz_f", + "llvm.nvvm.mul.rp.d" => "__nvvm_mul_rp_d", + "llvm.nvvm.mul.rp.f" => "__nvvm_mul_rp_f", + "llvm.nvvm.mul.rp.ftz.f" => "__nvvm_mul_rp_ftz_f", + "llvm.nvvm.mul.rz.d" => "__nvvm_mul_rz_d", + "llvm.nvvm.mul.rz.f" => "__nvvm_mul_rz_f", + "llvm.nvvm.mul.rz.ftz.f" => "__nvvm_mul_rz_ftz_f", + "llvm.nvvm.mul24.i" => "__nvvm_mul24_i", + "llvm.nvvm.mul24.ui" => "__nvvm_mul24_ui", + "llvm.nvvm.mulhi.i" => "__nvvm_mulhi_i", + "llvm.nvvm.mulhi.ll" => "__nvvm_mulhi_ll", + "llvm.nvvm.mulhi.ui" => "__nvvm_mulhi_ui", + "llvm.nvvm.mulhi.ull" => "__nvvm_mulhi_ull", + "llvm.nvvm.popc.i" => "__nvvm_popc_i", + "llvm.nvvm.popc.ll" => "__nvvm_popc_ll", "llvm.nvvm.prmt" => "__nvvm_prmt", + "llvm.nvvm.rcp.approx.ftz.d" => "__nvvm_rcp_approx_ftz_d", + "llvm.nvvm.rcp.rm.d" => "__nvvm_rcp_rm_d", + "llvm.nvvm.rcp.rm.f" => "__nvvm_rcp_rm_f", + "llvm.nvvm.rcp.rm.ftz.f" => "__nvvm_rcp_rm_ftz_f", + "llvm.nvvm.rcp.rn.d" => "__nvvm_rcp_rn_d", + "llvm.nvvm.rcp.rn.f" => "__nvvm_rcp_rn_f", + "llvm.nvvm.rcp.rn.ftz.f" => "__nvvm_rcp_rn_ftz_f", + "llvm.nvvm.rcp.rp.d" => "__nvvm_rcp_rp_d", + "llvm.nvvm.rcp.rp.f" => "__nvvm_rcp_rp_f", + "llvm.nvvm.rcp.rp.ftz.f" => "__nvvm_rcp_rp_ftz_f", + "llvm.nvvm.rcp.rz.d" => "__nvvm_rcp_rz_d", + "llvm.nvvm.rcp.rz.f" => "__nvvm_rcp_rz_f", + "llvm.nvvm.rcp.rz.ftz.f" => "__nvvm_rcp_rz_ftz_f", + "llvm.nvvm.read.ptx.sreg.ctaid.x" => "__nvvm_read_ptx_sreg_ctaid_x", + "llvm.nvvm.read.ptx.sreg.ctaid.y" => "__nvvm_read_ptx_sreg_ctaid_y", + "llvm.nvvm.read.ptx.sreg.ctaid.z" => "__nvvm_read_ptx_sreg_ctaid_z", + "llvm.nvvm.read.ptx.sreg.envreg0" => "__nvvm_read_ptx_sreg_envreg0", + "llvm.nvvm.read.ptx.sreg.envreg1" => "__nvvm_read_ptx_sreg_envreg1", + "llvm.nvvm.read.ptx.sreg.envreg10" => "__nvvm_read_ptx_sreg_envreg10", + "llvm.nvvm.read.ptx.sreg.envreg11" => "__nvvm_read_ptx_sreg_envreg11", + "llvm.nvvm.read.ptx.sreg.envreg12" => "__nvvm_read_ptx_sreg_envreg12", + "llvm.nvvm.read.ptx.sreg.envreg13" => "__nvvm_read_ptx_sreg_envreg13", + "llvm.nvvm.read.ptx.sreg.envreg14" => "__nvvm_read_ptx_sreg_envreg14", + "llvm.nvvm.read.ptx.sreg.envreg15" => "__nvvm_read_ptx_sreg_envreg15", + "llvm.nvvm.read.ptx.sreg.envreg16" => "__nvvm_read_ptx_sreg_envreg16", + "llvm.nvvm.read.ptx.sreg.envreg17" => "__nvvm_read_ptx_sreg_envreg17", + "llvm.nvvm.read.ptx.sreg.envreg18" => "__nvvm_read_ptx_sreg_envreg18", + "llvm.nvvm.read.ptx.sreg.envreg19" => "__nvvm_read_ptx_sreg_envreg19", + "llvm.nvvm.read.ptx.sreg.envreg2" => "__nvvm_read_ptx_sreg_envreg2", + "llvm.nvvm.read.ptx.sreg.envreg20" => "__nvvm_read_ptx_sreg_envreg20", + "llvm.nvvm.read.ptx.sreg.envreg21" => "__nvvm_read_ptx_sreg_envreg21", + "llvm.nvvm.read.ptx.sreg.envreg22" => "__nvvm_read_ptx_sreg_envreg22", + "llvm.nvvm.read.ptx.sreg.envreg23" => "__nvvm_read_ptx_sreg_envreg23", + "llvm.nvvm.read.ptx.sreg.envreg24" => "__nvvm_read_ptx_sreg_envreg24", + "llvm.nvvm.read.ptx.sreg.envreg25" => "__nvvm_read_ptx_sreg_envreg25", + "llvm.nvvm.read.ptx.sreg.envreg26" => "__nvvm_read_ptx_sreg_envreg26", + "llvm.nvvm.read.ptx.sreg.envreg27" => "__nvvm_read_ptx_sreg_envreg27", + "llvm.nvvm.read.ptx.sreg.envreg28" => "__nvvm_read_ptx_sreg_envreg28", + "llvm.nvvm.read.ptx.sreg.envreg29" => "__nvvm_read_ptx_sreg_envreg29", + "llvm.nvvm.read.ptx.sreg.envreg3" => "__nvvm_read_ptx_sreg_envreg3", + "llvm.nvvm.read.ptx.sreg.envreg30" => "__nvvm_read_ptx_sreg_envreg30", + "llvm.nvvm.read.ptx.sreg.envreg31" => "__nvvm_read_ptx_sreg_envreg31", + "llvm.nvvm.read.ptx.sreg.envreg4" => "__nvvm_read_ptx_sreg_envreg4", + "llvm.nvvm.read.ptx.sreg.envreg5" => "__nvvm_read_ptx_sreg_envreg5", + "llvm.nvvm.read.ptx.sreg.envreg6" => "__nvvm_read_ptx_sreg_envreg6", + "llvm.nvvm.read.ptx.sreg.envreg7" => "__nvvm_read_ptx_sreg_envreg7", + "llvm.nvvm.read.ptx.sreg.envreg8" => "__nvvm_read_ptx_sreg_envreg8", + "llvm.nvvm.read.ptx.sreg.envreg9" => "__nvvm_read_ptx_sreg_envreg9", + "llvm.nvvm.read.ptx.sreg.nctaid.x" => "__nvvm_read_ptx_sreg_nctaid_x", + "llvm.nvvm.read.ptx.sreg.nctaid.y" => "__nvvm_read_ptx_sreg_nctaid_y", + "llvm.nvvm.read.ptx.sreg.nctaid.z" => "__nvvm_read_ptx_sreg_nctaid_z", + "llvm.nvvm.read.ptx.sreg.ntid.x" => "__nvvm_read_ptx_sreg_ntid_x", + "llvm.nvvm.read.ptx.sreg.ntid.y" => "__nvvm_read_ptx_sreg_ntid_y", + "llvm.nvvm.read.ptx.sreg.ntid.z" => "__nvvm_read_ptx_sreg_ntid_z", + "llvm.nvvm.read.ptx.sreg.tid.x" => "__nvvm_read_ptx_sreg_tid_x", + "llvm.nvvm.read.ptx.sreg.tid.y" => "__nvvm_read_ptx_sreg_tid_y", + "llvm.nvvm.read.ptx.sreg.tid.z" => "__nvvm_read_ptx_sreg_tid_z", + "llvm.nvvm.read.ptx.sreg.warpsize" => "__nvvm_read_ptx_sreg_warpsize", + "llvm.nvvm.rotate.b32" => "__nvvm_rotate_b32", + "llvm.nvvm.rotate.b64" => "__nvvm_rotate_b64", + "llvm.nvvm.rotate.right.b64" => "__nvvm_rotate_right_b64", + "llvm.nvvm.round.d" => "__nvvm_round_d", + "llvm.nvvm.round.f" => "__nvvm_round_f", + "llvm.nvvm.round.ftz.f" => "__nvvm_round_ftz_f", + "llvm.nvvm.rsqrt.approx.d" => "__nvvm_rsqrt_approx_d", + "llvm.nvvm.rsqrt.approx.f" => "__nvvm_rsqrt_approx_f", + "llvm.nvvm.rsqrt.approx.ftz.f" => "__nvvm_rsqrt_approx_ftz_f", + "llvm.nvvm.sad.i" => "__nvvm_sad_i", + "llvm.nvvm.sad.ui" => "__nvvm_sad_ui", + "llvm.nvvm.saturate.d" => "__nvvm_saturate_d", + "llvm.nvvm.saturate.f" => "__nvvm_saturate_f", + "llvm.nvvm.saturate.ftz.f" => "__nvvm_saturate_ftz_f", + "llvm.nvvm.sin.approx.f" => "__nvvm_sin_approx_f", + "llvm.nvvm.sin.approx.ftz.f" => "__nvvm_sin_approx_ftz_f", + "llvm.nvvm.sqrt.approx.f" => "__nvvm_sqrt_approx_f", + "llvm.nvvm.sqrt.approx.ftz.f" => "__nvvm_sqrt_approx_ftz_f", + "llvm.nvvm.sqrt.f" => "__nvvm_sqrt_f", + "llvm.nvvm.sqrt.rm.d" => "__nvvm_sqrt_rm_d", + "llvm.nvvm.sqrt.rm.f" => "__nvvm_sqrt_rm_f", + "llvm.nvvm.sqrt.rm.ftz.f" => "__nvvm_sqrt_rm_ftz_f", + "llvm.nvvm.sqrt.rn.d" => "__nvvm_sqrt_rn_d", + "llvm.nvvm.sqrt.rn.f" => "__nvvm_sqrt_rn_f", + "llvm.nvvm.sqrt.rn.ftz.f" => "__nvvm_sqrt_rn_ftz_f", + "llvm.nvvm.sqrt.rp.d" => "__nvvm_sqrt_rp_d", + "llvm.nvvm.sqrt.rp.f" => "__nvvm_sqrt_rp_f", + "llvm.nvvm.sqrt.rp.ftz.f" => "__nvvm_sqrt_rp_ftz_f", + "llvm.nvvm.sqrt.rz.d" => "__nvvm_sqrt_rz_d", + "llvm.nvvm.sqrt.rz.f" => "__nvvm_sqrt_rz_f", + "llvm.nvvm.sqrt.rz.ftz.f" => "__nvvm_sqrt_rz_ftz_f", + "llvm.nvvm.suq.array.size" => "__nvvm_suq_array_size", + "llvm.nvvm.suq.channel.data.type" => "__nvvm_suq_channel_data_type", + "llvm.nvvm.suq.channel.order" => "__nvvm_suq_channel_order", + "llvm.nvvm.suq.depth" => "__nvvm_suq_depth", + "llvm.nvvm.suq.height" => "__nvvm_suq_height", + "llvm.nvvm.suq.width" => "__nvvm_suq_width", + "llvm.nvvm.sust.b.1d.array.i16.clamp" => "__nvvm_sust_b_1d_array_i16_clamp", + "llvm.nvvm.sust.b.1d.array.i16.trap" => "__nvvm_sust_b_1d_array_i16_trap", + "llvm.nvvm.sust.b.1d.array.i16.zero" => "__nvvm_sust_b_1d_array_i16_zero", + "llvm.nvvm.sust.b.1d.array.i32.clamp" => "__nvvm_sust_b_1d_array_i32_clamp", + "llvm.nvvm.sust.b.1d.array.i32.trap" => "__nvvm_sust_b_1d_array_i32_trap", + "llvm.nvvm.sust.b.1d.array.i32.zero" => "__nvvm_sust_b_1d_array_i32_zero", + "llvm.nvvm.sust.b.1d.array.i64.clamp" => "__nvvm_sust_b_1d_array_i64_clamp", + "llvm.nvvm.sust.b.1d.array.i64.trap" => "__nvvm_sust_b_1d_array_i64_trap", + "llvm.nvvm.sust.b.1d.array.i64.zero" => "__nvvm_sust_b_1d_array_i64_zero", + "llvm.nvvm.sust.b.1d.array.i8.clamp" => "__nvvm_sust_b_1d_array_i8_clamp", + "llvm.nvvm.sust.b.1d.array.i8.trap" => "__nvvm_sust_b_1d_array_i8_trap", + "llvm.nvvm.sust.b.1d.array.i8.zero" => "__nvvm_sust_b_1d_array_i8_zero", + "llvm.nvvm.sust.b.1d.array.v2i16.clamp" => "__nvvm_sust_b_1d_array_v2i16_clamp", + "llvm.nvvm.sust.b.1d.array.v2i16.trap" => "__nvvm_sust_b_1d_array_v2i16_trap", + "llvm.nvvm.sust.b.1d.array.v2i16.zero" => "__nvvm_sust_b_1d_array_v2i16_zero", + "llvm.nvvm.sust.b.1d.array.v2i32.clamp" => "__nvvm_sust_b_1d_array_v2i32_clamp", + "llvm.nvvm.sust.b.1d.array.v2i32.trap" => "__nvvm_sust_b_1d_array_v2i32_trap", + "llvm.nvvm.sust.b.1d.array.v2i32.zero" => "__nvvm_sust_b_1d_array_v2i32_zero", + "llvm.nvvm.sust.b.1d.array.v2i64.clamp" => "__nvvm_sust_b_1d_array_v2i64_clamp", + "llvm.nvvm.sust.b.1d.array.v2i64.trap" => "__nvvm_sust_b_1d_array_v2i64_trap", + "llvm.nvvm.sust.b.1d.array.v2i64.zero" => "__nvvm_sust_b_1d_array_v2i64_zero", + "llvm.nvvm.sust.b.1d.array.v2i8.clamp" => "__nvvm_sust_b_1d_array_v2i8_clamp", + "llvm.nvvm.sust.b.1d.array.v2i8.trap" => "__nvvm_sust_b_1d_array_v2i8_trap", + "llvm.nvvm.sust.b.1d.array.v2i8.zero" => "__nvvm_sust_b_1d_array_v2i8_zero", + "llvm.nvvm.sust.b.1d.array.v4i16.clamp" => "__nvvm_sust_b_1d_array_v4i16_clamp", + "llvm.nvvm.sust.b.1d.array.v4i16.trap" => "__nvvm_sust_b_1d_array_v4i16_trap", + "llvm.nvvm.sust.b.1d.array.v4i16.zero" => "__nvvm_sust_b_1d_array_v4i16_zero", + "llvm.nvvm.sust.b.1d.array.v4i32.clamp" => "__nvvm_sust_b_1d_array_v4i32_clamp", + "llvm.nvvm.sust.b.1d.array.v4i32.trap" => "__nvvm_sust_b_1d_array_v4i32_trap", + "llvm.nvvm.sust.b.1d.array.v4i32.zero" => "__nvvm_sust_b_1d_array_v4i32_zero", + "llvm.nvvm.sust.b.1d.array.v4i8.clamp" => "__nvvm_sust_b_1d_array_v4i8_clamp", + "llvm.nvvm.sust.b.1d.array.v4i8.trap" => "__nvvm_sust_b_1d_array_v4i8_trap", + "llvm.nvvm.sust.b.1d.array.v4i8.zero" => "__nvvm_sust_b_1d_array_v4i8_zero", + "llvm.nvvm.sust.b.1d.i16.clamp" => "__nvvm_sust_b_1d_i16_clamp", + "llvm.nvvm.sust.b.1d.i16.trap" => "__nvvm_sust_b_1d_i16_trap", + "llvm.nvvm.sust.b.1d.i16.zero" => "__nvvm_sust_b_1d_i16_zero", + "llvm.nvvm.sust.b.1d.i32.clamp" => "__nvvm_sust_b_1d_i32_clamp", + "llvm.nvvm.sust.b.1d.i32.trap" => "__nvvm_sust_b_1d_i32_trap", + "llvm.nvvm.sust.b.1d.i32.zero" => "__nvvm_sust_b_1d_i32_zero", + "llvm.nvvm.sust.b.1d.i64.clamp" => "__nvvm_sust_b_1d_i64_clamp", + "llvm.nvvm.sust.b.1d.i64.trap" => "__nvvm_sust_b_1d_i64_trap", + "llvm.nvvm.sust.b.1d.i64.zero" => "__nvvm_sust_b_1d_i64_zero", + "llvm.nvvm.sust.b.1d.i8.clamp" => "__nvvm_sust_b_1d_i8_clamp", + "llvm.nvvm.sust.b.1d.i8.trap" => "__nvvm_sust_b_1d_i8_trap", + "llvm.nvvm.sust.b.1d.i8.zero" => "__nvvm_sust_b_1d_i8_zero", + "llvm.nvvm.sust.b.1d.v2i16.clamp" => "__nvvm_sust_b_1d_v2i16_clamp", + "llvm.nvvm.sust.b.1d.v2i16.trap" => "__nvvm_sust_b_1d_v2i16_trap", + "llvm.nvvm.sust.b.1d.v2i16.zero" => "__nvvm_sust_b_1d_v2i16_zero", + "llvm.nvvm.sust.b.1d.v2i32.clamp" => "__nvvm_sust_b_1d_v2i32_clamp", + "llvm.nvvm.sust.b.1d.v2i32.trap" => "__nvvm_sust_b_1d_v2i32_trap", + "llvm.nvvm.sust.b.1d.v2i32.zero" => "__nvvm_sust_b_1d_v2i32_zero", + "llvm.nvvm.sust.b.1d.v2i64.clamp" => "__nvvm_sust_b_1d_v2i64_clamp", + "llvm.nvvm.sust.b.1d.v2i64.trap" => "__nvvm_sust_b_1d_v2i64_trap", + "llvm.nvvm.sust.b.1d.v2i64.zero" => "__nvvm_sust_b_1d_v2i64_zero", + "llvm.nvvm.sust.b.1d.v2i8.clamp" => "__nvvm_sust_b_1d_v2i8_clamp", + "llvm.nvvm.sust.b.1d.v2i8.trap" => "__nvvm_sust_b_1d_v2i8_trap", + "llvm.nvvm.sust.b.1d.v2i8.zero" => "__nvvm_sust_b_1d_v2i8_zero", + "llvm.nvvm.sust.b.1d.v4i16.clamp" => "__nvvm_sust_b_1d_v4i16_clamp", + "llvm.nvvm.sust.b.1d.v4i16.trap" => "__nvvm_sust_b_1d_v4i16_trap", + "llvm.nvvm.sust.b.1d.v4i16.zero" => "__nvvm_sust_b_1d_v4i16_zero", + "llvm.nvvm.sust.b.1d.v4i32.clamp" => "__nvvm_sust_b_1d_v4i32_clamp", + "llvm.nvvm.sust.b.1d.v4i32.trap" => "__nvvm_sust_b_1d_v4i32_trap", + "llvm.nvvm.sust.b.1d.v4i32.zero" => "__nvvm_sust_b_1d_v4i32_zero", + "llvm.nvvm.sust.b.1d.v4i8.clamp" => "__nvvm_sust_b_1d_v4i8_clamp", + "llvm.nvvm.sust.b.1d.v4i8.trap" => "__nvvm_sust_b_1d_v4i8_trap", + "llvm.nvvm.sust.b.1d.v4i8.zero" => "__nvvm_sust_b_1d_v4i8_zero", + "llvm.nvvm.sust.b.2d.array.i16.clamp" => "__nvvm_sust_b_2d_array_i16_clamp", + "llvm.nvvm.sust.b.2d.array.i16.trap" => "__nvvm_sust_b_2d_array_i16_trap", + "llvm.nvvm.sust.b.2d.array.i16.zero" => "__nvvm_sust_b_2d_array_i16_zero", + "llvm.nvvm.sust.b.2d.array.i32.clamp" => "__nvvm_sust_b_2d_array_i32_clamp", + "llvm.nvvm.sust.b.2d.array.i32.trap" => "__nvvm_sust_b_2d_array_i32_trap", + "llvm.nvvm.sust.b.2d.array.i32.zero" => "__nvvm_sust_b_2d_array_i32_zero", + "llvm.nvvm.sust.b.2d.array.i64.clamp" => "__nvvm_sust_b_2d_array_i64_clamp", + "llvm.nvvm.sust.b.2d.array.i64.trap" => "__nvvm_sust_b_2d_array_i64_trap", + "llvm.nvvm.sust.b.2d.array.i64.zero" => "__nvvm_sust_b_2d_array_i64_zero", + "llvm.nvvm.sust.b.2d.array.i8.clamp" => "__nvvm_sust_b_2d_array_i8_clamp", + "llvm.nvvm.sust.b.2d.array.i8.trap" => "__nvvm_sust_b_2d_array_i8_trap", + "llvm.nvvm.sust.b.2d.array.i8.zero" => "__nvvm_sust_b_2d_array_i8_zero", + "llvm.nvvm.sust.b.2d.array.v2i16.clamp" => "__nvvm_sust_b_2d_array_v2i16_clamp", + "llvm.nvvm.sust.b.2d.array.v2i16.trap" => "__nvvm_sust_b_2d_array_v2i16_trap", + "llvm.nvvm.sust.b.2d.array.v2i16.zero" => "__nvvm_sust_b_2d_array_v2i16_zero", + "llvm.nvvm.sust.b.2d.array.v2i32.clamp" => "__nvvm_sust_b_2d_array_v2i32_clamp", + "llvm.nvvm.sust.b.2d.array.v2i32.trap" => "__nvvm_sust_b_2d_array_v2i32_trap", + "llvm.nvvm.sust.b.2d.array.v2i32.zero" => "__nvvm_sust_b_2d_array_v2i32_zero", + "llvm.nvvm.sust.b.2d.array.v2i64.clamp" => "__nvvm_sust_b_2d_array_v2i64_clamp", + "llvm.nvvm.sust.b.2d.array.v2i64.trap" => "__nvvm_sust_b_2d_array_v2i64_trap", + "llvm.nvvm.sust.b.2d.array.v2i64.zero" => "__nvvm_sust_b_2d_array_v2i64_zero", + "llvm.nvvm.sust.b.2d.array.v2i8.clamp" => "__nvvm_sust_b_2d_array_v2i8_clamp", + "llvm.nvvm.sust.b.2d.array.v2i8.trap" => "__nvvm_sust_b_2d_array_v2i8_trap", + "llvm.nvvm.sust.b.2d.array.v2i8.zero" => "__nvvm_sust_b_2d_array_v2i8_zero", + "llvm.nvvm.sust.b.2d.array.v4i16.clamp" => "__nvvm_sust_b_2d_array_v4i16_clamp", + "llvm.nvvm.sust.b.2d.array.v4i16.trap" => "__nvvm_sust_b_2d_array_v4i16_trap", + "llvm.nvvm.sust.b.2d.array.v4i16.zero" => "__nvvm_sust_b_2d_array_v4i16_zero", + "llvm.nvvm.sust.b.2d.array.v4i32.clamp" => "__nvvm_sust_b_2d_array_v4i32_clamp", + "llvm.nvvm.sust.b.2d.array.v4i32.trap" => "__nvvm_sust_b_2d_array_v4i32_trap", + "llvm.nvvm.sust.b.2d.array.v4i32.zero" => "__nvvm_sust_b_2d_array_v4i32_zero", + "llvm.nvvm.sust.b.2d.array.v4i8.clamp" => "__nvvm_sust_b_2d_array_v4i8_clamp", + "llvm.nvvm.sust.b.2d.array.v4i8.trap" => "__nvvm_sust_b_2d_array_v4i8_trap", + "llvm.nvvm.sust.b.2d.array.v4i8.zero" => "__nvvm_sust_b_2d_array_v4i8_zero", + "llvm.nvvm.sust.b.2d.i16.clamp" => "__nvvm_sust_b_2d_i16_clamp", + "llvm.nvvm.sust.b.2d.i16.trap" => "__nvvm_sust_b_2d_i16_trap", + "llvm.nvvm.sust.b.2d.i16.zero" => "__nvvm_sust_b_2d_i16_zero", + "llvm.nvvm.sust.b.2d.i32.clamp" => "__nvvm_sust_b_2d_i32_clamp", + "llvm.nvvm.sust.b.2d.i32.trap" => "__nvvm_sust_b_2d_i32_trap", + "llvm.nvvm.sust.b.2d.i32.zero" => "__nvvm_sust_b_2d_i32_zero", + "llvm.nvvm.sust.b.2d.i64.clamp" => "__nvvm_sust_b_2d_i64_clamp", + "llvm.nvvm.sust.b.2d.i64.trap" => "__nvvm_sust_b_2d_i64_trap", + "llvm.nvvm.sust.b.2d.i64.zero" => "__nvvm_sust_b_2d_i64_zero", + "llvm.nvvm.sust.b.2d.i8.clamp" => "__nvvm_sust_b_2d_i8_clamp", + "llvm.nvvm.sust.b.2d.i8.trap" => "__nvvm_sust_b_2d_i8_trap", + "llvm.nvvm.sust.b.2d.i8.zero" => "__nvvm_sust_b_2d_i8_zero", + "llvm.nvvm.sust.b.2d.v2i16.clamp" => "__nvvm_sust_b_2d_v2i16_clamp", + "llvm.nvvm.sust.b.2d.v2i16.trap" => "__nvvm_sust_b_2d_v2i16_trap", + "llvm.nvvm.sust.b.2d.v2i16.zero" => "__nvvm_sust_b_2d_v2i16_zero", + "llvm.nvvm.sust.b.2d.v2i32.clamp" => "__nvvm_sust_b_2d_v2i32_clamp", + "llvm.nvvm.sust.b.2d.v2i32.trap" => "__nvvm_sust_b_2d_v2i32_trap", + "llvm.nvvm.sust.b.2d.v2i32.zero" => "__nvvm_sust_b_2d_v2i32_zero", + "llvm.nvvm.sust.b.2d.v2i64.clamp" => "__nvvm_sust_b_2d_v2i64_clamp", + "llvm.nvvm.sust.b.2d.v2i64.trap" => "__nvvm_sust_b_2d_v2i64_trap", + "llvm.nvvm.sust.b.2d.v2i64.zero" => "__nvvm_sust_b_2d_v2i64_zero", + "llvm.nvvm.sust.b.2d.v2i8.clamp" => "__nvvm_sust_b_2d_v2i8_clamp", + "llvm.nvvm.sust.b.2d.v2i8.trap" => "__nvvm_sust_b_2d_v2i8_trap", + "llvm.nvvm.sust.b.2d.v2i8.zero" => "__nvvm_sust_b_2d_v2i8_zero", + "llvm.nvvm.sust.b.2d.v4i16.clamp" => "__nvvm_sust_b_2d_v4i16_clamp", + "llvm.nvvm.sust.b.2d.v4i16.trap" => "__nvvm_sust_b_2d_v4i16_trap", + "llvm.nvvm.sust.b.2d.v4i16.zero" => "__nvvm_sust_b_2d_v4i16_zero", + "llvm.nvvm.sust.b.2d.v4i32.clamp" => "__nvvm_sust_b_2d_v4i32_clamp", + "llvm.nvvm.sust.b.2d.v4i32.trap" => "__nvvm_sust_b_2d_v4i32_trap", + "llvm.nvvm.sust.b.2d.v4i32.zero" => "__nvvm_sust_b_2d_v4i32_zero", + "llvm.nvvm.sust.b.2d.v4i8.clamp" => "__nvvm_sust_b_2d_v4i8_clamp", + "llvm.nvvm.sust.b.2d.v4i8.trap" => "__nvvm_sust_b_2d_v4i8_trap", + "llvm.nvvm.sust.b.2d.v4i8.zero" => "__nvvm_sust_b_2d_v4i8_zero", + "llvm.nvvm.sust.b.3d.i16.clamp" => "__nvvm_sust_b_3d_i16_clamp", + "llvm.nvvm.sust.b.3d.i16.trap" => "__nvvm_sust_b_3d_i16_trap", + "llvm.nvvm.sust.b.3d.i16.zero" => "__nvvm_sust_b_3d_i16_zero", + "llvm.nvvm.sust.b.3d.i32.clamp" => "__nvvm_sust_b_3d_i32_clamp", + "llvm.nvvm.sust.b.3d.i32.trap" => "__nvvm_sust_b_3d_i32_trap", + "llvm.nvvm.sust.b.3d.i32.zero" => "__nvvm_sust_b_3d_i32_zero", + "llvm.nvvm.sust.b.3d.i64.clamp" => "__nvvm_sust_b_3d_i64_clamp", + "llvm.nvvm.sust.b.3d.i64.trap" => "__nvvm_sust_b_3d_i64_trap", + "llvm.nvvm.sust.b.3d.i64.zero" => "__nvvm_sust_b_3d_i64_zero", + "llvm.nvvm.sust.b.3d.i8.clamp" => "__nvvm_sust_b_3d_i8_clamp", + "llvm.nvvm.sust.b.3d.i8.trap" => "__nvvm_sust_b_3d_i8_trap", + "llvm.nvvm.sust.b.3d.i8.zero" => "__nvvm_sust_b_3d_i8_zero", + "llvm.nvvm.sust.b.3d.v2i16.clamp" => "__nvvm_sust_b_3d_v2i16_clamp", + "llvm.nvvm.sust.b.3d.v2i16.trap" => "__nvvm_sust_b_3d_v2i16_trap", + "llvm.nvvm.sust.b.3d.v2i16.zero" => "__nvvm_sust_b_3d_v2i16_zero", + "llvm.nvvm.sust.b.3d.v2i32.clamp" => "__nvvm_sust_b_3d_v2i32_clamp", + "llvm.nvvm.sust.b.3d.v2i32.trap" => "__nvvm_sust_b_3d_v2i32_trap", + "llvm.nvvm.sust.b.3d.v2i32.zero" => "__nvvm_sust_b_3d_v2i32_zero", + "llvm.nvvm.sust.b.3d.v2i64.clamp" => "__nvvm_sust_b_3d_v2i64_clamp", + "llvm.nvvm.sust.b.3d.v2i64.trap" => "__nvvm_sust_b_3d_v2i64_trap", + "llvm.nvvm.sust.b.3d.v2i64.zero" => "__nvvm_sust_b_3d_v2i64_zero", + "llvm.nvvm.sust.b.3d.v2i8.clamp" => "__nvvm_sust_b_3d_v2i8_clamp", + "llvm.nvvm.sust.b.3d.v2i8.trap" => "__nvvm_sust_b_3d_v2i8_trap", + "llvm.nvvm.sust.b.3d.v2i8.zero" => "__nvvm_sust_b_3d_v2i8_zero", + "llvm.nvvm.sust.b.3d.v4i16.clamp" => "__nvvm_sust_b_3d_v4i16_clamp", + "llvm.nvvm.sust.b.3d.v4i16.trap" => "__nvvm_sust_b_3d_v4i16_trap", + "llvm.nvvm.sust.b.3d.v4i16.zero" => "__nvvm_sust_b_3d_v4i16_zero", + "llvm.nvvm.sust.b.3d.v4i32.clamp" => "__nvvm_sust_b_3d_v4i32_clamp", + "llvm.nvvm.sust.b.3d.v4i32.trap" => "__nvvm_sust_b_3d_v4i32_trap", + "llvm.nvvm.sust.b.3d.v4i32.zero" => "__nvvm_sust_b_3d_v4i32_zero", + "llvm.nvvm.sust.b.3d.v4i8.clamp" => "__nvvm_sust_b_3d_v4i8_clamp", + "llvm.nvvm.sust.b.3d.v4i8.trap" => "__nvvm_sust_b_3d_v4i8_trap", + "llvm.nvvm.sust.b.3d.v4i8.zero" => "__nvvm_sust_b_3d_v4i8_zero", + "llvm.nvvm.sust.p.1d.array.i16.trap" => "__nvvm_sust_p_1d_array_i16_trap", + "llvm.nvvm.sust.p.1d.array.i32.trap" => "__nvvm_sust_p_1d_array_i32_trap", + "llvm.nvvm.sust.p.1d.array.i8.trap" => "__nvvm_sust_p_1d_array_i8_trap", + "llvm.nvvm.sust.p.1d.array.v2i16.trap" => "__nvvm_sust_p_1d_array_v2i16_trap", + "llvm.nvvm.sust.p.1d.array.v2i32.trap" => "__nvvm_sust_p_1d_array_v2i32_trap", + "llvm.nvvm.sust.p.1d.array.v2i8.trap" => "__nvvm_sust_p_1d_array_v2i8_trap", + "llvm.nvvm.sust.p.1d.array.v4i16.trap" => "__nvvm_sust_p_1d_array_v4i16_trap", + "llvm.nvvm.sust.p.1d.array.v4i32.trap" => "__nvvm_sust_p_1d_array_v4i32_trap", + "llvm.nvvm.sust.p.1d.array.v4i8.trap" => "__nvvm_sust_p_1d_array_v4i8_trap", + "llvm.nvvm.sust.p.1d.i16.trap" => "__nvvm_sust_p_1d_i16_trap", + "llvm.nvvm.sust.p.1d.i32.trap" => "__nvvm_sust_p_1d_i32_trap", + "llvm.nvvm.sust.p.1d.i8.trap" => "__nvvm_sust_p_1d_i8_trap", + "llvm.nvvm.sust.p.1d.v2i16.trap" => "__nvvm_sust_p_1d_v2i16_trap", + "llvm.nvvm.sust.p.1d.v2i32.trap" => "__nvvm_sust_p_1d_v2i32_trap", + "llvm.nvvm.sust.p.1d.v2i8.trap" => "__nvvm_sust_p_1d_v2i8_trap", + "llvm.nvvm.sust.p.1d.v4i16.trap" => "__nvvm_sust_p_1d_v4i16_trap", + "llvm.nvvm.sust.p.1d.v4i32.trap" => "__nvvm_sust_p_1d_v4i32_trap", + "llvm.nvvm.sust.p.1d.v4i8.trap" => "__nvvm_sust_p_1d_v4i8_trap", + "llvm.nvvm.sust.p.2d.array.i16.trap" => "__nvvm_sust_p_2d_array_i16_trap", + "llvm.nvvm.sust.p.2d.array.i32.trap" => "__nvvm_sust_p_2d_array_i32_trap", + "llvm.nvvm.sust.p.2d.array.i8.trap" => "__nvvm_sust_p_2d_array_i8_trap", + "llvm.nvvm.sust.p.2d.array.v2i16.trap" => "__nvvm_sust_p_2d_array_v2i16_trap", + "llvm.nvvm.sust.p.2d.array.v2i32.trap" => "__nvvm_sust_p_2d_array_v2i32_trap", + "llvm.nvvm.sust.p.2d.array.v2i8.trap" => "__nvvm_sust_p_2d_array_v2i8_trap", + "llvm.nvvm.sust.p.2d.array.v4i16.trap" => "__nvvm_sust_p_2d_array_v4i16_trap", + "llvm.nvvm.sust.p.2d.array.v4i32.trap" => "__nvvm_sust_p_2d_array_v4i32_trap", + "llvm.nvvm.sust.p.2d.array.v4i8.trap" => "__nvvm_sust_p_2d_array_v4i8_trap", + "llvm.nvvm.sust.p.2d.i16.trap" => "__nvvm_sust_p_2d_i16_trap", + "llvm.nvvm.sust.p.2d.i32.trap" => "__nvvm_sust_p_2d_i32_trap", + "llvm.nvvm.sust.p.2d.i8.trap" => "__nvvm_sust_p_2d_i8_trap", + "llvm.nvvm.sust.p.2d.v2i16.trap" => "__nvvm_sust_p_2d_v2i16_trap", + "llvm.nvvm.sust.p.2d.v2i32.trap" => "__nvvm_sust_p_2d_v2i32_trap", + "llvm.nvvm.sust.p.2d.v2i8.trap" => "__nvvm_sust_p_2d_v2i8_trap", + "llvm.nvvm.sust.p.2d.v4i16.trap" => "__nvvm_sust_p_2d_v4i16_trap", + "llvm.nvvm.sust.p.2d.v4i32.trap" => "__nvvm_sust_p_2d_v4i32_trap", + "llvm.nvvm.sust.p.2d.v4i8.trap" => "__nvvm_sust_p_2d_v4i8_trap", + "llvm.nvvm.sust.p.3d.i16.trap" => "__nvvm_sust_p_3d_i16_trap", + "llvm.nvvm.sust.p.3d.i32.trap" => "__nvvm_sust_p_3d_i32_trap", + "llvm.nvvm.sust.p.3d.i8.trap" => "__nvvm_sust_p_3d_i8_trap", + "llvm.nvvm.sust.p.3d.v2i16.trap" => "__nvvm_sust_p_3d_v2i16_trap", + "llvm.nvvm.sust.p.3d.v2i32.trap" => "__nvvm_sust_p_3d_v2i32_trap", + "llvm.nvvm.sust.p.3d.v2i8.trap" => "__nvvm_sust_p_3d_v2i8_trap", + "llvm.nvvm.sust.p.3d.v4i16.trap" => "__nvvm_sust_p_3d_v4i16_trap", + "llvm.nvvm.sust.p.3d.v4i32.trap" => "__nvvm_sust_p_3d_v4i32_trap", + "llvm.nvvm.sust.p.3d.v4i8.trap" => "__nvvm_sust_p_3d_v4i8_trap", + "llvm.nvvm.swap.lo.hi.b64" => "__nvvm_swap_lo_hi_b64", + "llvm.nvvm.trunc.d" => "__nvvm_trunc_d", + "llvm.nvvm.trunc.f" => "__nvvm_trunc_f", + "llvm.nvvm.trunc.ftz.f" => "__nvvm_trunc_ftz_f", + "llvm.nvvm.txq.array.size" => "__nvvm_txq_array_size", + "llvm.nvvm.txq.channel.data.type" => "__nvvm_txq_channel_data_type", + "llvm.nvvm.txq.channel.order" => "__nvvm_txq_channel_order", + "llvm.nvvm.txq.depth" => "__nvvm_txq_depth", + "llvm.nvvm.txq.height" => "__nvvm_txq_height", + "llvm.nvvm.txq.num.mipmap.levels" => "__nvvm_txq_num_mipmap_levels", + "llvm.nvvm.txq.num.samples" => "__nvvm_txq_num_samples", + "llvm.nvvm.txq.width" => "__nvvm_txq_width", + "llvm.nvvm.ui2d.rm" => "__nvvm_ui2d_rm", + "llvm.nvvm.ui2d.rn" => "__nvvm_ui2d_rn", + "llvm.nvvm.ui2d.rp" => "__nvvm_ui2d_rp", + "llvm.nvvm.ui2d.rz" => "__nvvm_ui2d_rz", + "llvm.nvvm.ui2f.rm" => "__nvvm_ui2f_rm", + "llvm.nvvm.ui2f.rn" => "__nvvm_ui2f_rn", + "llvm.nvvm.ui2f.rp" => "__nvvm_ui2f_rp", + "llvm.nvvm.ui2f.rz" => "__nvvm_ui2f_rz", + "llvm.nvvm.ull2d.rm" => "__nvvm_ull2d_rm", + "llvm.nvvm.ull2d.rn" => "__nvvm_ull2d_rn", + "llvm.nvvm.ull2d.rp" => "__nvvm_ull2d_rp", + "llvm.nvvm.ull2d.rz" => "__nvvm_ull2d_rz", + "llvm.nvvm.ull2f.rm" => "__nvvm_ull2f_rm", + "llvm.nvvm.ull2f.rn" => "__nvvm_ull2f_rn", + "llvm.nvvm.ull2f.rp" => "__nvvm_ull2f_rp", + "llvm.nvvm.ull2f.rz" => "__nvvm_ull2f_rz", // ppc "llvm.ppc.addex" => "__builtin_ppc_addex", "llvm.ppc.addf128.round.to.odd" => "__builtin_addf128_round_to_odd", @@ -909,8 +2321,21 @@ match name { "llvm.ppc.altivec.mtvsrhm" => "__builtin_altivec_mtvsrhm", "llvm.ppc.altivec.mtvsrqm" => "__builtin_altivec_mtvsrqm", "llvm.ppc.altivec.mtvsrwm" => "__builtin_altivec_mtvsrwm", + "llvm.ppc.altivec.vaddcuw" => "__builtin_altivec_vaddcuw", "llvm.ppc.altivec.vaddecuq" => "__builtin_altivec_vaddecuq", "llvm.ppc.altivec.vaddeuqm" => "__builtin_altivec_vaddeuqm", + "llvm.ppc.altivec.vaddsbs" => "__builtin_altivec_vaddsbs", + "llvm.ppc.altivec.vaddshs" => "__builtin_altivec_vaddshs", + "llvm.ppc.altivec.vaddsws" => "__builtin_altivec_vaddsws", + "llvm.ppc.altivec.vaddubs" => "__builtin_altivec_vaddubs", + "llvm.ppc.altivec.vadduhs" => "__builtin_altivec_vadduhs", + "llvm.ppc.altivec.vadduws" => "__builtin_altivec_vadduws", + "llvm.ppc.altivec.vavgsb" => "__builtin_altivec_vavgsb", + "llvm.ppc.altivec.vavgsh" => "__builtin_altivec_vavgsh", + "llvm.ppc.altivec.vavgsw" => "__builtin_altivec_vavgsw", + "llvm.ppc.altivec.vavgub" => "__builtin_altivec_vavgub", + "llvm.ppc.altivec.vavguh" => "__builtin_altivec_vavguh", + "llvm.ppc.altivec.vavguw" => "__builtin_altivec_vavguw", "llvm.ppc.altivec.vbpermd" => "__builtin_altivec_vbpermd", "llvm.ppc.altivec.vbpermq" => "__builtin_altivec_vbpermq", "llvm.ppc.altivec.vcfsx" => "__builtin_altivec_vcfsx", @@ -983,6 +2408,7 @@ match name { "llvm.ppc.altivec.vexpandhm" => "__builtin_altivec_vexpandhm", "llvm.ppc.altivec.vexpandqm" => "__builtin_altivec_vexpandqm", "llvm.ppc.altivec.vexpandwm" => "__builtin_altivec_vexpandwm", + "llvm.ppc.altivec.vexptefp" => "__builtin_altivec_vexptefp", "llvm.ppc.altivec.vextddvlx" => "__builtin_altivec_vextddvlx", "llvm.ppc.altivec.vextddvrx" => "__builtin_altivec_vextddvrx", "llvm.ppc.altivec.vextdubvlx" => "__builtin_altivec_vextdubvlx", @@ -1018,9 +2444,24 @@ match name { "llvm.ppc.altivec.vinswrx" => "__builtin_altivec_vinswrx", "llvm.ppc.altivec.vinswvlx" => "__builtin_altivec_vinswvlx", "llvm.ppc.altivec.vinswvrx" => "__builtin_altivec_vinswvrx", + "llvm.ppc.altivec.vlogefp" => "__builtin_altivec_vlogefp", "llvm.ppc.altivec.vmaddfp" => "__builtin_altivec_vmaddfp", + "llvm.ppc.altivec.vmaxfp" => "__builtin_altivec_vmaxfp", + "llvm.ppc.altivec.vmaxsb" => "__builtin_altivec_vmaxsb", + "llvm.ppc.altivec.vmaxsh" => "__builtin_altivec_vmaxsh", + "llvm.ppc.altivec.vmaxsw" => "__builtin_altivec_vmaxsw", + "llvm.ppc.altivec.vmaxub" => "__builtin_altivec_vmaxub", + "llvm.ppc.altivec.vmaxuh" => "__builtin_altivec_vmaxuh", + "llvm.ppc.altivec.vmaxuw" => "__builtin_altivec_vmaxuw", "llvm.ppc.altivec.vmhaddshs" => "__builtin_altivec_vmhaddshs", "llvm.ppc.altivec.vmhraddshs" => "__builtin_altivec_vmhraddshs", + "llvm.ppc.altivec.vminfp" => "__builtin_altivec_vminfp", + "llvm.ppc.altivec.vminsb" => "__builtin_altivec_vminsb", + "llvm.ppc.altivec.vminsh" => "__builtin_altivec_vminsh", + "llvm.ppc.altivec.vminsw" => "__builtin_altivec_vminsw", + "llvm.ppc.altivec.vminub" => "__builtin_altivec_vminub", + "llvm.ppc.altivec.vminuh" => "__builtin_altivec_vminuh", + "llvm.ppc.altivec.vminuw" => "__builtin_altivec_vminuw", "llvm.ppc.altivec.vmladduhm" => "__builtin_altivec_vmladduhm", "llvm.ppc.altivec.vmsumcud" => "__builtin_altivec_vmsumcud", "llvm.ppc.altivec.vmsummbm" => "__builtin_altivec_vmsummbm", @@ -1059,13 +2500,31 @@ match name { "llvm.ppc.altivec.vprtybd" => "__builtin_altivec_vprtybd", "llvm.ppc.altivec.vprtybq" => "__builtin_altivec_vprtybq", "llvm.ppc.altivec.vprtybw" => "__builtin_altivec_vprtybw", + "llvm.ppc.altivec.vrefp" => "__builtin_altivec_vrefp", "llvm.ppc.altivec.vrfim" => "__builtin_altivec_vrfim", "llvm.ppc.altivec.vrfin" => "__builtin_altivec_vrfin", "llvm.ppc.altivec.vrfip" => "__builtin_altivec_vrfip", "llvm.ppc.altivec.vrfiz" => "__builtin_altivec_vrfiz", + "llvm.ppc.altivec.vrlb" => "__builtin_altivec_vrlb", + "llvm.ppc.altivec.vrlh" => "__builtin_altivec_vrlh", + "llvm.ppc.altivec.vrlw" => "__builtin_altivec_vrlw", + "llvm.ppc.altivec.vrsqrtefp" => "__builtin_altivec_vrsqrtefp", "llvm.ppc.altivec.vsel" => "__builtin_altivec_vsel_4si", + "llvm.ppc.altivec.vsl" => "__builtin_altivec_vsl", + "llvm.ppc.altivec.vslb" => "__builtin_altivec_vslb", "llvm.ppc.altivec.vsldbi" => "__builtin_altivec_vsldbi", + "llvm.ppc.altivec.vslh" => "__builtin_altivec_vslh", + "llvm.ppc.altivec.vslo" => "__builtin_altivec_vslo", + "llvm.ppc.altivec.vslw" => "__builtin_altivec_vslw", + "llvm.ppc.altivec.vsr" => "__builtin_altivec_vsr", + "llvm.ppc.altivec.vsrab" => "__builtin_altivec_vsrab", + "llvm.ppc.altivec.vsrah" => "__builtin_altivec_vsrah", + "llvm.ppc.altivec.vsraw" => "__builtin_altivec_vsraw", + "llvm.ppc.altivec.vsrb" => "__builtin_altivec_vsrb", "llvm.ppc.altivec.vsrdbi" => "__builtin_altivec_vsrdbi", + "llvm.ppc.altivec.vsrh" => "__builtin_altivec_vsrh", + "llvm.ppc.altivec.vsro" => "__builtin_altivec_vsro", + "llvm.ppc.altivec.vsrw" => "__builtin_altivec_vsrw", "llvm.ppc.altivec.vstribl" => "__builtin_altivec_vstribl", "llvm.ppc.altivec.vstribl.p" => "__builtin_altivec_vstribl_p", "llvm.ppc.altivec.vstribr" => "__builtin_altivec_vstribr", @@ -1074,8 +2533,15 @@ match name { "llvm.ppc.altivec.vstrihl.p" => "__builtin_altivec_vstrihl_p", "llvm.ppc.altivec.vstrihr" => "__builtin_altivec_vstrihr", "llvm.ppc.altivec.vstrihr.p" => "__builtin_altivec_vstrihr_p", + "llvm.ppc.altivec.vsubcuw" => "__builtin_altivec_vsubcuw", "llvm.ppc.altivec.vsubecuq" => "__builtin_altivec_vsubecuq", "llvm.ppc.altivec.vsubeuqm" => "__builtin_altivec_vsubeuqm", + "llvm.ppc.altivec.vsubsbs" => "__builtin_altivec_vsubsbs", + "llvm.ppc.altivec.vsubshs" => "__builtin_altivec_vsubshs", + "llvm.ppc.altivec.vsubsws" => "__builtin_altivec_vsubsws", + "llvm.ppc.altivec.vsububs" => "__builtin_altivec_vsububs", + "llvm.ppc.altivec.vsubuhs" => "__builtin_altivec_vsubuhs", + "llvm.ppc.altivec.vsubuws" => "__builtin_altivec_vsubuws", "llvm.ppc.altivec.vsum2sws" => "__builtin_altivec_vsum2sws", "llvm.ppc.altivec.vsum4sbs" => "__builtin_altivec_vsum4sbs", "llvm.ppc.altivec.vsum4shs" => "__builtin_altivec_vsum4shs", @@ -1224,6 +2690,25 @@ match name { "llvm.ppc.vsx.xvrsqrtedp" => "__builtin_vsx_xvrsqrtedp", "llvm.ppc.vsx.xvrsqrtesp" => "__builtin_vsx_xvrsqrtesp", "llvm.ppc.vsx.xxpermx" => "__builtin_vsx_xxpermx", + // ptx + "llvm.ptx.bar.sync" => "__builtin_ptx_bar_sync", + "llvm.ptx.read.clock" => "__builtin_ptx_read_clock", + "llvm.ptx.read.clock64" => "__builtin_ptx_read_clock64", + "llvm.ptx.read.gridid" => "__builtin_ptx_read_gridid", + "llvm.ptx.read.laneid" => "__builtin_ptx_read_laneid", + "llvm.ptx.read.lanemask.eq" => "__builtin_ptx_read_lanemask_eq", + "llvm.ptx.read.lanemask.ge" => "__builtin_ptx_read_lanemask_ge", + "llvm.ptx.read.lanemask.gt" => "__builtin_ptx_read_lanemask_gt", + "llvm.ptx.read.lanemask.le" => "__builtin_ptx_read_lanemask_le", + "llvm.ptx.read.lanemask.lt" => "__builtin_ptx_read_lanemask_lt", + "llvm.ptx.read.nsmid" => "__builtin_ptx_read_nsmid", + "llvm.ptx.read.nwarpid" => "__builtin_ptx_read_nwarpid", + "llvm.ptx.read.pm0" => "__builtin_ptx_read_pm0", + "llvm.ptx.read.pm1" => "__builtin_ptx_read_pm1", + "llvm.ptx.read.pm2" => "__builtin_ptx_read_pm2", + "llvm.ptx.read.pm3" => "__builtin_ptx_read_pm3", + "llvm.ptx.read.smid" => "__builtin_ptx_read_smid", + "llvm.ptx.read.warpid" => "__builtin_ptx_read_warpid", // s390 "llvm.s390.efpc" => "__builtin_s390_efpc", "llvm.s390.etnd" => "__builtin_tx_nesting_depth", @@ -1278,6 +2763,10 @@ match name { "llvm.x86.3dnowa.pfnacc" => "__builtin_ia32_pfnacc", "llvm.x86.3dnowa.pfpnacc" => "__builtin_ia32_pfpnacc", "llvm.x86.3dnowa.pi2fw" => "__builtin_ia32_pi2fw", + "llvm.x86.addcarry.u32" => "__builtin_ia32_addcarry_u32", + "llvm.x86.addcarry.u64" => "__builtin_ia32_addcarry_u64", + "llvm.x86.addcarryx.u32" => "__builtin_ia32_addcarryx_u32", + "llvm.x86.addcarryx.u64" => "__builtin_ia32_addcarryx_u64", "llvm.x86.aesni.aesdec" => "__builtin_ia32_aesdec128", "llvm.x86.aesni.aesdec.256" => "__builtin_ia32_aesdec256", "llvm.x86.aesni.aesdec.512" => "__builtin_ia32_aesdec512", @@ -1294,11 +2783,18 @@ match name { "llvm.x86.aesni.aeskeygenassist" => "__builtin_ia32_aeskeygenassist128", "llvm.x86.avx.addsub.pd.256" => "__builtin_ia32_addsubpd256", "llvm.x86.avx.addsub.ps.256" => "__builtin_ia32_addsubps256", + "llvm.x86.avx.blend.pd.256" => "__builtin_ia32_blendpd256", + "llvm.x86.avx.blend.ps.256" => "__builtin_ia32_blendps256", "llvm.x86.avx.blendv.pd.256" => "__builtin_ia32_blendvpd256", "llvm.x86.avx.blendv.ps.256" => "__builtin_ia32_blendvps256", + "llvm.x86.avx.cmp.pd.256" => "__builtin_ia32_cmppd256", + "llvm.x86.avx.cmp.ps.256" => "__builtin_ia32_cmpps256", "llvm.x86.avx.cvt.pd2.ps.256" => "__builtin_ia32_cvtpd2ps256", "llvm.x86.avx.cvt.pd2dq.256" => "__builtin_ia32_cvtpd2dq256", + "llvm.x86.avx.cvt.ps2.pd.256" => "__builtin_ia32_cvtps2pd256", "llvm.x86.avx.cvt.ps2dq.256" => "__builtin_ia32_cvtps2dq256", + "llvm.x86.avx.cvtdq2.pd.256" => "__builtin_ia32_cvtdq2pd256", + "llvm.x86.avx.cvtdq2.ps.256" => "__builtin_ia32_cvtdq2ps256", "llvm.x86.avx.cvtt.pd2dq.256" => "__builtin_ia32_cvttpd2dq256", "llvm.x86.avx.cvtt.ps2dq.256" => "__builtin_ia32_cvttps2dq256", "llvm.x86.avx.dp.ps.256" => "__builtin_ia32_dpps256", @@ -1328,6 +2824,22 @@ match name { "llvm.x86.avx.round.pd.256" => "__builtin_ia32_roundpd256", "llvm.x86.avx.round.ps.256" => "__builtin_ia32_roundps256", "llvm.x86.avx.rsqrt.ps.256" => "__builtin_ia32_rsqrtps256", + "llvm.x86.avx.sqrt.pd.256" => "__builtin_ia32_sqrtpd256", + "llvm.x86.avx.sqrt.ps.256" => "__builtin_ia32_sqrtps256", + "llvm.x86.avx.storeu.dq.256" => "__builtin_ia32_storedqu256", + "llvm.x86.avx.storeu.pd.256" => "__builtin_ia32_storeupd256", + "llvm.x86.avx.storeu.ps.256" => "__builtin_ia32_storeups256", + "llvm.x86.avx.vbroadcastf128.pd.256" => "__builtin_ia32_vbroadcastf128_pd256", + "llvm.x86.avx.vbroadcastf128.ps.256" => "__builtin_ia32_vbroadcastf128_ps256", + "llvm.x86.avx.vextractf128.pd.256" => "__builtin_ia32_vextractf128_pd256", + "llvm.x86.avx.vextractf128.ps.256" => "__builtin_ia32_vextractf128_ps256", + "llvm.x86.avx.vextractf128.si.256" => "__builtin_ia32_vextractf128_si256", + "llvm.x86.avx.vinsertf128.pd.256" => "__builtin_ia32_vinsertf128_pd256", + "llvm.x86.avx.vinsertf128.ps.256" => "__builtin_ia32_vinsertf128_ps256", + "llvm.x86.avx.vinsertf128.si.256" => "__builtin_ia32_vinsertf128_si256", + "llvm.x86.avx.vperm2f128.pd.256" => "__builtin_ia32_vperm2f128_pd256", + "llvm.x86.avx.vperm2f128.ps.256" => "__builtin_ia32_vperm2f128_ps256", + "llvm.x86.avx.vperm2f128.si.256" => "__builtin_ia32_vperm2f128_si256", "llvm.x86.avx.vpermilvar.pd" => "__builtin_ia32_vpermilvarpd", "llvm.x86.avx.vpermilvar.pd.256" => "__builtin_ia32_vpermilvarpd256", "llvm.x86.avx.vpermilvar.ps" => "__builtin_ia32_vpermilvarps", @@ -1370,14 +2882,33 @@ match name { "llvm.x86.avx2.maskstore.d.256" => "__builtin_ia32_maskstored256", "llvm.x86.avx2.maskstore.q" => "__builtin_ia32_maskstoreq", "llvm.x86.avx2.maskstore.q.256" => "__builtin_ia32_maskstoreq256", + "llvm.x86.avx2.movntdqa" => "__builtin_ia32_movntdqa256", "llvm.x86.avx2.mpsadbw" => "__builtin_ia32_mpsadbw256", + "llvm.x86.avx2.pabs.b" => "__builtin_ia32_pabsb256", + "llvm.x86.avx2.pabs.d" => "__builtin_ia32_pabsd256", + "llvm.x86.avx2.pabs.w" => "__builtin_ia32_pabsw256", "llvm.x86.avx2.packssdw" => "__builtin_ia32_packssdw256", "llvm.x86.avx2.packsswb" => "__builtin_ia32_packsswb256", "llvm.x86.avx2.packusdw" => "__builtin_ia32_packusdw256", "llvm.x86.avx2.packuswb" => "__builtin_ia32_packuswb256", + "llvm.x86.avx2.padds.b" => "__builtin_ia32_paddsb256", + "llvm.x86.avx2.padds.w" => "__builtin_ia32_paddsw256", + "llvm.x86.avx2.paddus.b" => "__builtin_ia32_paddusb256", + "llvm.x86.avx2.paddus.w" => "__builtin_ia32_paddusw256", "llvm.x86.avx2.pavg.b" => "__builtin_ia32_pavgb256", "llvm.x86.avx2.pavg.w" => "__builtin_ia32_pavgw256", + "llvm.x86.avx2.pblendd.128" => "__builtin_ia32_pblendd128", + "llvm.x86.avx2.pblendd.256" => "__builtin_ia32_pblendd256", "llvm.x86.avx2.pblendvb" => "__builtin_ia32_pblendvb256", + "llvm.x86.avx2.pblendw" => "__builtin_ia32_pblendw256", + "llvm.x86.avx2.pbroadcastb.128" => "__builtin_ia32_pbroadcastb128", + "llvm.x86.avx2.pbroadcastb.256" => "__builtin_ia32_pbroadcastb256", + "llvm.x86.avx2.pbroadcastd.128" => "__builtin_ia32_pbroadcastd128", + "llvm.x86.avx2.pbroadcastd.256" => "__builtin_ia32_pbroadcastd256", + "llvm.x86.avx2.pbroadcastq.128" => "__builtin_ia32_pbroadcastq128", + "llvm.x86.avx2.pbroadcastq.256" => "__builtin_ia32_pbroadcastq256", + "llvm.x86.avx2.pbroadcastw.128" => "__builtin_ia32_pbroadcastw128", + "llvm.x86.avx2.pbroadcastw.256" => "__builtin_ia32_pbroadcastw256", "llvm.x86.avx2.permd" => "__builtin_ia32_permvarsi256", "llvm.x86.avx2.permps" => "__builtin_ia32_permvarsf256", "llvm.x86.avx2.phadd.d" => "__builtin_ia32_phaddd256", @@ -1388,16 +2919,44 @@ match name { "llvm.x86.avx2.phsub.w" => "__builtin_ia32_phsubw256", "llvm.x86.avx2.pmadd.ub.sw" => "__builtin_ia32_pmaddubsw256", "llvm.x86.avx2.pmadd.wd" => "__builtin_ia32_pmaddwd256", + "llvm.x86.avx2.pmaxs.b" => "__builtin_ia32_pmaxsb256", + "llvm.x86.avx2.pmaxs.d" => "__builtin_ia32_pmaxsd256", + "llvm.x86.avx2.pmaxs.w" => "__builtin_ia32_pmaxsw256", + "llvm.x86.avx2.pmaxu.b" => "__builtin_ia32_pmaxub256", + "llvm.x86.avx2.pmaxu.d" => "__builtin_ia32_pmaxud256", + "llvm.x86.avx2.pmaxu.w" => "__builtin_ia32_pmaxuw256", + "llvm.x86.avx2.pmins.b" => "__builtin_ia32_pminsb256", + "llvm.x86.avx2.pmins.d" => "__builtin_ia32_pminsd256", + "llvm.x86.avx2.pmins.w" => "__builtin_ia32_pminsw256", + "llvm.x86.avx2.pminu.b" => "__builtin_ia32_pminub256", + "llvm.x86.avx2.pminu.d" => "__builtin_ia32_pminud256", + "llvm.x86.avx2.pminu.w" => "__builtin_ia32_pminuw256", "llvm.x86.avx2.pmovmskb" => "__builtin_ia32_pmovmskb256", + "llvm.x86.avx2.pmovsxbd" => "__builtin_ia32_pmovsxbd256", + "llvm.x86.avx2.pmovsxbq" => "__builtin_ia32_pmovsxbq256", + "llvm.x86.avx2.pmovsxbw" => "__builtin_ia32_pmovsxbw256", + "llvm.x86.avx2.pmovsxdq" => "__builtin_ia32_pmovsxdq256", + "llvm.x86.avx2.pmovsxwd" => "__builtin_ia32_pmovsxwd256", + "llvm.x86.avx2.pmovsxwq" => "__builtin_ia32_pmovsxwq256", + "llvm.x86.avx2.pmovzxbd" => "__builtin_ia32_pmovzxbd256", + "llvm.x86.avx2.pmovzxbq" => "__builtin_ia32_pmovzxbq256", + "llvm.x86.avx2.pmovzxbw" => "__builtin_ia32_pmovzxbw256", + "llvm.x86.avx2.pmovzxdq" => "__builtin_ia32_pmovzxdq256", + "llvm.x86.avx2.pmovzxwd" => "__builtin_ia32_pmovzxwd256", + "llvm.x86.avx2.pmovzxwq" => "__builtin_ia32_pmovzxwq256", + "llvm.x86.avx2.pmul.dq" => "__builtin_ia32_pmuldq256", "llvm.x86.avx2.pmul.hr.sw" => "__builtin_ia32_pmulhrsw256", "llvm.x86.avx2.pmulh.w" => "__builtin_ia32_pmulhw256", "llvm.x86.avx2.pmulhu.w" => "__builtin_ia32_pmulhuw256", + "llvm.x86.avx2.pmulu.dq" => "__builtin_ia32_pmuludq256", "llvm.x86.avx2.psad.bw" => "__builtin_ia32_psadbw256", "llvm.x86.avx2.pshuf.b" => "__builtin_ia32_pshufb256", "llvm.x86.avx2.psign.b" => "__builtin_ia32_psignb256", "llvm.x86.avx2.psign.d" => "__builtin_ia32_psignd256", "llvm.x86.avx2.psign.w" => "__builtin_ia32_psignw256", "llvm.x86.avx2.psll.d" => "__builtin_ia32_pslld256", + "llvm.x86.avx2.psll.dq" => "__builtin_ia32_pslldqi256", + "llvm.x86.avx2.psll.dq.bs" => "__builtin_ia32_pslldqi256_byteshift", "llvm.x86.avx2.psll.q" => "__builtin_ia32_psllq256", "llvm.x86.avx2.psll.w" => "__builtin_ia32_psllw256", "llvm.x86.avx2.pslli.d" => "__builtin_ia32_pslldi256", @@ -1414,6 +2973,8 @@ match name { "llvm.x86.avx2.psrav.d" => "__builtin_ia32_psrav4si", "llvm.x86.avx2.psrav.d.256" => "__builtin_ia32_psrav8si", "llvm.x86.avx2.psrl.d" => "__builtin_ia32_psrld256", + "llvm.x86.avx2.psrl.dq" => "__builtin_ia32_psrldqi256", + "llvm.x86.avx2.psrl.dq.bs" => "__builtin_ia32_psrldqi256_byteshift", "llvm.x86.avx2.psrl.q" => "__builtin_ia32_psrlq256", "llvm.x86.avx2.psrl.w" => "__builtin_ia32_psrlw256", "llvm.x86.avx2.psrli.d" => "__builtin_ia32_psrldi256", @@ -1423,6 +2984,16 @@ match name { "llvm.x86.avx2.psrlv.d.256" => "__builtin_ia32_psrlv8si", "llvm.x86.avx2.psrlv.q" => "__builtin_ia32_psrlv2di", "llvm.x86.avx2.psrlv.q.256" => "__builtin_ia32_psrlv4di", + "llvm.x86.avx2.psubs.b" => "__builtin_ia32_psubsb256", + "llvm.x86.avx2.psubs.w" => "__builtin_ia32_psubsw256", + "llvm.x86.avx2.psubus.b" => "__builtin_ia32_psubusb256", + "llvm.x86.avx2.psubus.w" => "__builtin_ia32_psubusw256", + "llvm.x86.avx2.vbroadcast.sd.pd.256" => "__builtin_ia32_vbroadcastsd_pd256", + "llvm.x86.avx2.vbroadcast.ss.ps" => "__builtin_ia32_vbroadcastss_ps", + "llvm.x86.avx2.vbroadcast.ss.ps.256" => "__builtin_ia32_vbroadcastss_ps256", + "llvm.x86.avx2.vextracti128" => "__builtin_ia32_extract128i256", + "llvm.x86.avx2.vinserti128" => "__builtin_ia32_insert128i256", + "llvm.x86.avx2.vperm2i128" => "__builtin_ia32_permti256", "llvm.x86.avx512.add.pd.512" => "__builtin_ia32_addpd512", "llvm.x86.avx512.add.ps.512" => "__builtin_ia32_addps512", "llvm.x86.avx512.broadcastmb.128" => "__builtin_ia32_broadcastmb128", @@ -1437,20 +3008,32 @@ match name { "llvm.x86.avx512.conflict.q.128" => "__builtin_ia32_vpconflictdi_128", "llvm.x86.avx512.conflict.q.256" => "__builtin_ia32_vpconflictdi_256", "llvm.x86.avx512.conflict.q.512" => "__builtin_ia32_vpconflictdi_512", + "llvm.x86.avx512.cvtsd2usi" => "__builtin_ia32_cvtsd2usi", + "llvm.x86.avx512.cvtsd2usi64" => "__builtin_ia32_cvtsd2usi64", "llvm.x86.avx512.cvtsi2sd64" => "__builtin_ia32_cvtsi2sd64", "llvm.x86.avx512.cvtsi2ss32" => "__builtin_ia32_cvtsi2ss32", "llvm.x86.avx512.cvtsi2ss64" => "__builtin_ia32_cvtsi2ss64", + "llvm.x86.avx512.cvtss2usi" => "__builtin_ia32_cvtss2usi", + "llvm.x86.avx512.cvtss2usi64" => "__builtin_ia32_cvtss2usi64", "llvm.x86.avx512.cvttsd2si" => "__builtin_ia32_vcvttsd2si32", "llvm.x86.avx512.cvttsd2si64" => "__builtin_ia32_vcvttsd2si64", - "llvm.x86.avx512.cvttsd2usi" => "__builtin_ia32_vcvttsd2usi32", - "llvm.x86.avx512.cvttsd2usi64" => "__builtin_ia32_vcvttsd2usi64", + "llvm.x86.avx512.cvttsd2usi" => "__builtin_ia32_cvttsd2usi", + // [DUPLICATE]: "llvm.x86.avx512.cvttsd2usi" => "__builtin_ia32_vcvttsd2usi32", + "llvm.x86.avx512.cvttsd2usi64" => "__builtin_ia32_cvttsd2usi64", + // [DUPLICATE]: "llvm.x86.avx512.cvttsd2usi64" => "__builtin_ia32_vcvttsd2usi64", "llvm.x86.avx512.cvttss2si" => "__builtin_ia32_vcvttss2si32", "llvm.x86.avx512.cvttss2si64" => "__builtin_ia32_vcvttss2si64", - "llvm.x86.avx512.cvttss2usi" => "__builtin_ia32_vcvttss2usi32", - "llvm.x86.avx512.cvttss2usi64" => "__builtin_ia32_vcvttss2usi64", - "llvm.x86.avx512.cvtusi2ss" => "__builtin_ia32_cvtusi2ss32", + "llvm.x86.avx512.cvttss2usi" => "__builtin_ia32_cvttss2usi", + // [DUPLICATE]: "llvm.x86.avx512.cvttss2usi" => "__builtin_ia32_vcvttss2usi32", + "llvm.x86.avx512.cvttss2usi64" => "__builtin_ia32_cvttss2usi64", + // [DUPLICATE]: "llvm.x86.avx512.cvttss2usi64" => "__builtin_ia32_vcvttss2usi64", + "llvm.x86.avx512.cvtusi2sd" => "__builtin_ia32_cvtusi2sd", + "llvm.x86.avx512.cvtusi2ss" => "__builtin_ia32_cvtusi2ss", + // [DUPLICATE]: "llvm.x86.avx512.cvtusi2ss" => "__builtin_ia32_cvtusi2ss32", "llvm.x86.avx512.cvtusi642sd" => "__builtin_ia32_cvtusi2sd64", + // [DUPLICATE]: "llvm.x86.avx512.cvtusi642sd" => "__builtin_ia32_cvtusi642sd", "llvm.x86.avx512.cvtusi642ss" => "__builtin_ia32_cvtusi2ss64", + // [DUPLICATE]: "llvm.x86.avx512.cvtusi642ss" => "__builtin_ia32_cvtusi642ss", "llvm.x86.avx512.dbpsadbw.128" => "__builtin_ia32_dbpsadbw128", "llvm.x86.avx512.dbpsadbw.256" => "__builtin_ia32_dbpsadbw256", "llvm.x86.avx512.dbpsadbw.512" => "__builtin_ia32_dbpsadbw512", @@ -1458,14 +3041,41 @@ match name { "llvm.x86.avx512.div.ps.512" => "__builtin_ia32_divps512", "llvm.x86.avx512.exp2.pd" => "__builtin_ia32_exp2pd_mask", "llvm.x86.avx512.exp2.ps" => "__builtin_ia32_exp2ps_mask", + "llvm.x86.avx512.gather.dpd.512" => "__builtin_ia32_gathersiv8df", + "llvm.x86.avx512.gather.dpi.512" => "__builtin_ia32_gathersiv16si", + "llvm.x86.avx512.gather.dpq.512" => "__builtin_ia32_gathersiv8di", + "llvm.x86.avx512.gather.dps.512" => "__builtin_ia32_gathersiv16sf", + "llvm.x86.avx512.gather.qpd.512" => "__builtin_ia32_gatherdiv8df", + "llvm.x86.avx512.gather.qpi.512" => "__builtin_ia32_gatherdiv16si", + "llvm.x86.avx512.gather.qpq.512" => "__builtin_ia32_gatherdiv8di", + "llvm.x86.avx512.gather.qps.512" => "__builtin_ia32_gatherdiv16sf", "llvm.x86.avx512.gatherpf.dpd.512" => "__builtin_ia32_gatherpfdpd", "llvm.x86.avx512.gatherpf.dps.512" => "__builtin_ia32_gatherpfdps", "llvm.x86.avx512.gatherpf.qpd.512" => "__builtin_ia32_gatherpfqpd", "llvm.x86.avx512.gatherpf.qps.512" => "__builtin_ia32_gatherpfqps", + "llvm.x86.avx512.kand.w" => "__builtin_ia32_kandhi", + "llvm.x86.avx512.kandn.w" => "__builtin_ia32_kandnhi", + "llvm.x86.avx512.knot.w" => "__builtin_ia32_knothi", + "llvm.x86.avx512.kor.w" => "__builtin_ia32_korhi", + "llvm.x86.avx512.kortestc.w" => "__builtin_ia32_kortestchi", + "llvm.x86.avx512.kortestz.w" => "__builtin_ia32_kortestzhi", + "llvm.x86.avx512.kunpck.bw" => "__builtin_ia32_kunpckhi", + "llvm.x86.avx512.kxnor.w" => "__builtin_ia32_kxnorhi", + "llvm.x86.avx512.kxor.w" => "__builtin_ia32_kxorhi", "llvm.x86.avx512.mask.add.sd.round" => "__builtin_ia32_addsd_round_mask", "llvm.x86.avx512.mask.add.ss.round" => "__builtin_ia32_addss_round_mask", + "llvm.x86.avx512.mask.blend.d.512" => "__builtin_ia32_blendmd_512_mask", + "llvm.x86.avx512.mask.blend.pd.512" => "__builtin_ia32_blendmpd_512_mask", + "llvm.x86.avx512.mask.blend.ps.512" => "__builtin_ia32_blendmps_512_mask", + "llvm.x86.avx512.mask.blend.q.512" => "__builtin_ia32_blendmq_512_mask", + "llvm.x86.avx512.mask.cmp.pd.512" => "__builtin_ia32_cmppd512_mask", + "llvm.x86.avx512.mask.cmp.ps.512" => "__builtin_ia32_cmpps512_mask", "llvm.x86.avx512.mask.cmp.sd" => "__builtin_ia32_cmpsd_mask", "llvm.x86.avx512.mask.cmp.ss" => "__builtin_ia32_cmpss_mask", + "llvm.x86.avx512.mask.conflict.d.512" => "__builtin_ia32_vpconflictsi_512_mask", + "llvm.x86.avx512.mask.conflict.q.512" => "__builtin_ia32_vpconflictdi_512_mask", + "llvm.x86.avx512.mask.cvtdq2pd.512" => "__builtin_ia32_cvtdq2pd512_mask", + "llvm.x86.avx512.mask.cvtdq2ps.512" => "__builtin_ia32_cvtdq2ps512_mask", "llvm.x86.avx512.mask.cvtpd2dq.128" => "__builtin_ia32_cvtpd2dq128_mask", "llvm.x86.avx512.mask.cvtpd2dq.512" => "__builtin_ia32_cvtpd2dq512_mask", "llvm.x86.avx512.mask.cvtpd2ps" => "__builtin_ia32_cvtpd2ps_mask", @@ -1516,6 +3126,8 @@ match name { "llvm.x86.avx512.mask.cvttps2uqq.128" => "__builtin_ia32_cvttps2uqq128_mask", "llvm.x86.avx512.mask.cvttps2uqq.256" => "__builtin_ia32_cvttps2uqq256_mask", "llvm.x86.avx512.mask.cvttps2uqq.512" => "__builtin_ia32_cvttps2uqq512_mask", + "llvm.x86.avx512.mask.cvtudq2pd.512" => "__builtin_ia32_cvtudq2pd512_mask", + "llvm.x86.avx512.mask.cvtudq2ps.512" => "__builtin_ia32_cvtudq2ps512_mask", "llvm.x86.avx512.mask.cvtuqq2ps.128" => "__builtin_ia32_cvtuqq2ps128_mask", "llvm.x86.avx512.mask.div.sd.round" => "__builtin_ia32_divsd_round_mask", "llvm.x86.avx512.mask.div.ss.round" => "__builtin_ia32_divss_round_mask", @@ -1545,12 +3157,61 @@ match name { "llvm.x86.avx512.mask.getmant.ps.512" => "__builtin_ia32_getmantps512_mask", "llvm.x86.avx512.mask.getmant.sd" => "__builtin_ia32_getmantsd_round_mask", "llvm.x86.avx512.mask.getmant.ss" => "__builtin_ia32_getmantss_round_mask", + "llvm.x86.avx512.mask.loadu.d.512" => "__builtin_ia32_loaddqusi512_mask", + "llvm.x86.avx512.mask.loadu.pd.512" => "__builtin_ia32_loadupd512_mask", + "llvm.x86.avx512.mask.loadu.ps.512" => "__builtin_ia32_loadups512_mask", + "llvm.x86.avx512.mask.loadu.q.512" => "__builtin_ia32_loaddqudi512_mask", + "llvm.x86.avx512.mask.lzcnt.d.512" => "__builtin_ia32_vplzcntd_512_mask", + "llvm.x86.avx512.mask.lzcnt.q.512" => "__builtin_ia32_vplzcntq_512_mask", + "llvm.x86.avx512.mask.max.pd.512" => "__builtin_ia32_maxpd512_mask", + "llvm.x86.avx512.mask.max.ps.512" => "__builtin_ia32_maxps512_mask", "llvm.x86.avx512.mask.max.sd.round" => "__builtin_ia32_maxsd_round_mask", "llvm.x86.avx512.mask.max.ss.round" => "__builtin_ia32_maxss_round_mask", + "llvm.x86.avx512.mask.min.pd.512" => "__builtin_ia32_minpd512_mask", + "llvm.x86.avx512.mask.min.ps.512" => "__builtin_ia32_minps512_mask", "llvm.x86.avx512.mask.min.sd.round" => "__builtin_ia32_minsd_round_mask", "llvm.x86.avx512.mask.min.ss.round" => "__builtin_ia32_minss_round_mask", "llvm.x86.avx512.mask.mul.sd.round" => "__builtin_ia32_mulsd_round_mask", "llvm.x86.avx512.mask.mul.ss.round" => "__builtin_ia32_mulss_round_mask", + "llvm.x86.avx512.mask.pabs.d.512" => "__builtin_ia32_pabsd512_mask", + "llvm.x86.avx512.mask.pabs.q.512" => "__builtin_ia32_pabsq512_mask", + "llvm.x86.avx512.mask.pand.d.512" => "__builtin_ia32_pandd512_mask", + "llvm.x86.avx512.mask.pand.q.512" => "__builtin_ia32_pandq512_mask", + "llvm.x86.avx512.mask.pbroadcast.d.gpr.512" => "__builtin_ia32_pbroadcastd512_gpr_mask", + "llvm.x86.avx512.mask.pbroadcast.q.gpr.512" => "__builtin_ia32_pbroadcastq512_gpr_mask", + "llvm.x86.avx512.mask.pbroadcast.q.mem.512" => "__builtin_ia32_pbroadcastq512_mem_mask", + "llvm.x86.avx512.mask.pcmpeq.b.128" => "__builtin_ia32_pcmpeqb128_mask", + "llvm.x86.avx512.mask.pcmpeq.b.256" => "__builtin_ia32_pcmpeqb256_mask", + "llvm.x86.avx512.mask.pcmpeq.b.512" => "__builtin_ia32_pcmpeqb512_mask", + "llvm.x86.avx512.mask.pcmpeq.d.128" => "__builtin_ia32_pcmpeqd128_mask", + "llvm.x86.avx512.mask.pcmpeq.d.256" => "__builtin_ia32_pcmpeqd256_mask", + "llvm.x86.avx512.mask.pcmpeq.d.512" => "__builtin_ia32_pcmpeqd512_mask", + "llvm.x86.avx512.mask.pcmpeq.q.128" => "__builtin_ia32_pcmpeqq128_mask", + "llvm.x86.avx512.mask.pcmpeq.q.256" => "__builtin_ia32_pcmpeqq256_mask", + "llvm.x86.avx512.mask.pcmpeq.q.512" => "__builtin_ia32_pcmpeqq512_mask", + "llvm.x86.avx512.mask.pcmpeq.w.128" => "__builtin_ia32_pcmpeqw128_mask", + "llvm.x86.avx512.mask.pcmpeq.w.256" => "__builtin_ia32_pcmpeqw256_mask", + "llvm.x86.avx512.mask.pcmpeq.w.512" => "__builtin_ia32_pcmpeqw512_mask", + "llvm.x86.avx512.mask.pcmpgt.b.128" => "__builtin_ia32_pcmpgtb128_mask", + "llvm.x86.avx512.mask.pcmpgt.b.256" => "__builtin_ia32_pcmpgtb256_mask", + "llvm.x86.avx512.mask.pcmpgt.b.512" => "__builtin_ia32_pcmpgtb512_mask", + "llvm.x86.avx512.mask.pcmpgt.d.128" => "__builtin_ia32_pcmpgtd128_mask", + "llvm.x86.avx512.mask.pcmpgt.d.256" => "__builtin_ia32_pcmpgtd256_mask", + "llvm.x86.avx512.mask.pcmpgt.d.512" => "__builtin_ia32_pcmpgtd512_mask", + "llvm.x86.avx512.mask.pcmpgt.q.128" => "__builtin_ia32_pcmpgtq128_mask", + "llvm.x86.avx512.mask.pcmpgt.q.256" => "__builtin_ia32_pcmpgtq256_mask", + "llvm.x86.avx512.mask.pcmpgt.q.512" => "__builtin_ia32_pcmpgtq512_mask", + "llvm.x86.avx512.mask.pcmpgt.w.128" => "__builtin_ia32_pcmpgtw128_mask", + "llvm.x86.avx512.mask.pcmpgt.w.256" => "__builtin_ia32_pcmpgtw256_mask", + "llvm.x86.avx512.mask.pcmpgt.w.512" => "__builtin_ia32_pcmpgtw512_mask", + "llvm.x86.avx512.mask.pmaxs.d.512" => "__builtin_ia32_pmaxsd512_mask", + "llvm.x86.avx512.mask.pmaxs.q.512" => "__builtin_ia32_pmaxsq512_mask", + "llvm.x86.avx512.mask.pmaxu.d.512" => "__builtin_ia32_pmaxud512_mask", + "llvm.x86.avx512.mask.pmaxu.q.512" => "__builtin_ia32_pmaxuq512_mask", + "llvm.x86.avx512.mask.pmins.d.512" => "__builtin_ia32_pminsd512_mask", + "llvm.x86.avx512.mask.pmins.q.512" => "__builtin_ia32_pminsq512_mask", + "llvm.x86.avx512.mask.pminu.d.512" => "__builtin_ia32_pminud512_mask", + "llvm.x86.avx512.mask.pminu.q.512" => "__builtin_ia32_pminuq512_mask", "llvm.x86.avx512.mask.pmov.db.128" => "__builtin_ia32_pmovdb128_mask", "llvm.x86.avx512.mask.pmov.db.256" => "__builtin_ia32_pmovdb256_mask", "llvm.x86.avx512.mask.pmov.db.mem.128" => "__builtin_ia32_pmovdb128mem_mask", @@ -1652,6 +3313,10 @@ match name { "llvm.x86.avx512.mask.pmovus.wb.mem.128" => "__builtin_ia32_pmovuswb128mem_mask", "llvm.x86.avx512.mask.pmovus.wb.mem.256" => "__builtin_ia32_pmovuswb256mem_mask", "llvm.x86.avx512.mask.pmovus.wb.mem.512" => "__builtin_ia32_pmovuswb512mem_mask", + "llvm.x86.avx512.mask.pmul.dq.512" => "__builtin_ia32_pmuldq512_mask", + "llvm.x86.avx512.mask.pmulu.dq.512" => "__builtin_ia32_pmuludq512_mask", + "llvm.x86.avx512.mask.ptestm.d.512" => "__builtin_ia32_ptestmd512", + "llvm.x86.avx512.mask.ptestm.q.512" => "__builtin_ia32_ptestmq512", "llvm.x86.avx512.mask.range.pd.128" => "__builtin_ia32_rangepd128_mask", "llvm.x86.avx512.mask.range.pd.256" => "__builtin_ia32_rangepd256_mask", "llvm.x86.avx512.mask.range.pd.512" => "__builtin_ia32_rangepd512_mask", @@ -1684,11 +3349,23 @@ match name { "llvm.x86.avx512.mask.scalef.ps.512" => "__builtin_ia32_scalefps512_mask", "llvm.x86.avx512.mask.scalef.sd" => "__builtin_ia32_scalefsd_round_mask", "llvm.x86.avx512.mask.scalef.ss" => "__builtin_ia32_scalefss_round_mask", + "llvm.x86.avx512.mask.store.ss" => "__builtin_ia32_storess_mask", + "llvm.x86.avx512.mask.storeu.d.512" => "__builtin_ia32_storedqusi512_mask", + "llvm.x86.avx512.mask.storeu.pd.512" => "__builtin_ia32_storeupd512_mask", + "llvm.x86.avx512.mask.storeu.ps.512" => "__builtin_ia32_storeups512_mask", + "llvm.x86.avx512.mask.storeu.q.512" => "__builtin_ia32_storedqudi512_mask", "llvm.x86.avx512.mask.sub.sd.round" => "__builtin_ia32_subsd_round_mask", "llvm.x86.avx512.mask.sub.ss.round" => "__builtin_ia32_subss_round_mask", + "llvm.x86.avx512.mask.valign.d.512" => "__builtin_ia32_alignd512_mask", + "llvm.x86.avx512.mask.valign.q.512" => "__builtin_ia32_alignq512_mask", + "llvm.x86.avx512.mask.vcvtph2ps.512" => "__builtin_ia32_vcvtph2ps512_mask", "llvm.x86.avx512.mask.vcvtps2ph.128" => "__builtin_ia32_vcvtps2ph_mask", "llvm.x86.avx512.mask.vcvtps2ph.256" => "__builtin_ia32_vcvtps2ph256_mask", "llvm.x86.avx512.mask.vcvtps2ph.512" => "__builtin_ia32_vcvtps2ph512_mask", + "llvm.x86.avx512.mask.vpermt.d.512" => "__builtin_ia32_vpermt2vard512_mask", + "llvm.x86.avx512.mask.vpermt.pd.512" => "__builtin_ia32_vpermt2varpd512_mask", + "llvm.x86.avx512.mask.vpermt.ps.512" => "__builtin_ia32_vpermt2varps512_mask", + "llvm.x86.avx512.mask.vpermt.q.512" => "__builtin_ia32_vpermt2varq512_mask", "llvm.x86.avx512.maskz.fixupimm.pd.128" => "__builtin_ia32_fixupimmpd128_maskz", "llvm.x86.avx512.maskz.fixupimm.pd.256" => "__builtin_ia32_fixupimmpd256_maskz", "llvm.x86.avx512.maskz.fixupimm.pd.512" => "__builtin_ia32_fixupimmpd512_maskz", @@ -1701,6 +3378,7 @@ match name { "llvm.x86.avx512.max.ps.512" => "__builtin_ia32_maxps512", "llvm.x86.avx512.min.pd.512" => "__builtin_ia32_minpd512", "llvm.x86.avx512.min.ps.512" => "__builtin_ia32_minps512", + "llvm.x86.avx512.movntdqa" => "__builtin_ia32_movntdqa512", "llvm.x86.avx512.mul.pd.512" => "__builtin_ia32_mulpd512", "llvm.x86.avx512.mul.ps.512" => "__builtin_ia32_mulps512", "llvm.x86.avx512.packssdw.512" => "__builtin_ia32_packssdw512", @@ -1709,6 +3387,8 @@ match name { "llvm.x86.avx512.packuswb.512" => "__builtin_ia32_packuswb512", "llvm.x86.avx512.pavg.b.512" => "__builtin_ia32_pavgb512", "llvm.x86.avx512.pavg.w.512" => "__builtin_ia32_pavgw512", + "llvm.x86.avx512.pbroadcastd.512" => "__builtin_ia32_pbroadcastd512", + "llvm.x86.avx512.pbroadcastq.512" => "__builtin_ia32_pbroadcastq512", "llvm.x86.avx512.permvar.df.256" => "__builtin_ia32_permvardf256", "llvm.x86.avx512.permvar.df.512" => "__builtin_ia32_permvardf512", "llvm.x86.avx512.permvar.di.256" => "__builtin_ia32_permvardi256", @@ -1723,6 +3403,11 @@ match name { "llvm.x86.avx512.permvar.si.512" => "__builtin_ia32_permvarsi512", "llvm.x86.avx512.pmaddubs.w.512" => "__builtin_ia32_pmaddubsw512", "llvm.x86.avx512.pmaddw.d.512" => "__builtin_ia32_pmaddwd512", + "llvm.x86.avx512.pmovzxbd" => "__builtin_ia32_pmovzxbd512", + "llvm.x86.avx512.pmovzxbq" => "__builtin_ia32_pmovzxbq512", + "llvm.x86.avx512.pmovzxdq" => "__builtin_ia32_pmovzxdq512", + "llvm.x86.avx512.pmovzxwd" => "__builtin_ia32_pmovzxwd512", + "llvm.x86.avx512.pmovzxwq" => "__builtin_ia32_pmovzxwq512", "llvm.x86.avx512.pmul.hr.sw.512" => "__builtin_ia32_pmulhrsw512", "llvm.x86.avx512.pmulh.w.512" => "__builtin_ia32_pmulhw512", "llvm.x86.avx512.pmulhu.w.512" => "__builtin_ia32_pmulhuw512", @@ -1732,6 +3417,8 @@ match name { "llvm.x86.avx512.psad.bw.512" => "__builtin_ia32_psadbw512", "llvm.x86.avx512.pshuf.b.512" => "__builtin_ia32_pshufb512", "llvm.x86.avx512.psll.d.512" => "__builtin_ia32_pslld512", + "llvm.x86.avx512.psll.dq" => "__builtin_ia32_pslldqi512", + "llvm.x86.avx512.psll.dq.bs" => "__builtin_ia32_pslldqi512_byteshift", "llvm.x86.avx512.psll.q.512" => "__builtin_ia32_psllq512", "llvm.x86.avx512.psll.w.512" => "__builtin_ia32_psllw512", "llvm.x86.avx512.pslli.d.512" => "__builtin_ia32_pslldi512", @@ -1760,6 +3447,8 @@ match name { "llvm.x86.avx512.psrav.w.256" => "__builtin_ia32_psrav16hi", "llvm.x86.avx512.psrav.w.512" => "__builtin_ia32_psrav32hi", "llvm.x86.avx512.psrl.d.512" => "__builtin_ia32_psrld512", + "llvm.x86.avx512.psrl.dq" => "__builtin_ia32_psrldqi512", + "llvm.x86.avx512.psrl.dq.bs" => "__builtin_ia32_psrldqi512_byteshift", "llvm.x86.avx512.psrl.q.512" => "__builtin_ia32_psrlq512", "llvm.x86.avx512.psrl.w.512" => "__builtin_ia32_psrlw512", "llvm.x86.avx512.psrli.d.512" => "__builtin_ia32_psrldi512", @@ -1786,8 +3475,12 @@ match name { "llvm.x86.avx512.rcp14.ss" => "__builtin_ia32_rcp14ss_mask", "llvm.x86.avx512.rcp28.pd" => "__builtin_ia32_rcp28pd_mask", "llvm.x86.avx512.rcp28.ps" => "__builtin_ia32_rcp28ps_mask", - "llvm.x86.avx512.rcp28.sd" => "__builtin_ia32_rcp28sd_round_mask", - "llvm.x86.avx512.rcp28.ss" => "__builtin_ia32_rcp28ss_round_mask", + "llvm.x86.avx512.rcp28.sd" => "__builtin_ia32_rcp28sd_mask", + // [DUPLICATE]: "llvm.x86.avx512.rcp28.sd" => "__builtin_ia32_rcp28sd_round_mask", + "llvm.x86.avx512.rcp28.ss" => "__builtin_ia32_rcp28ss_mask", + // [DUPLICATE]: "llvm.x86.avx512.rcp28.ss" => "__builtin_ia32_rcp28ss_round_mask", + "llvm.x86.avx512.rndscale.sd" => "__builtin_ia32_rndscalesd", + "llvm.x86.avx512.rndscale.ss" => "__builtin_ia32_rndscaless", "llvm.x86.avx512.rsqrt14.pd.128" => "__builtin_ia32_rsqrt14pd128_mask", "llvm.x86.avx512.rsqrt14.pd.256" => "__builtin_ia32_rsqrt14pd256_mask", "llvm.x86.avx512.rsqrt14.pd.512" => "__builtin_ia32_rsqrt14pd512_mask", @@ -1798,14 +3491,32 @@ match name { "llvm.x86.avx512.rsqrt14.ss" => "__builtin_ia32_rsqrt14ss_mask", "llvm.x86.avx512.rsqrt28.pd" => "__builtin_ia32_rsqrt28pd_mask", "llvm.x86.avx512.rsqrt28.ps" => "__builtin_ia32_rsqrt28ps_mask", - "llvm.x86.avx512.rsqrt28.sd" => "__builtin_ia32_rsqrt28sd_round_mask", - "llvm.x86.avx512.rsqrt28.ss" => "__builtin_ia32_rsqrt28ss_round_mask", + "llvm.x86.avx512.rsqrt28.sd" => "__builtin_ia32_rsqrt28sd_mask", + // [DUPLICATE]: "llvm.x86.avx512.rsqrt28.sd" => "__builtin_ia32_rsqrt28sd_round_mask", + "llvm.x86.avx512.rsqrt28.ss" => "__builtin_ia32_rsqrt28ss_mask", + // [DUPLICATE]: "llvm.x86.avx512.rsqrt28.ss" => "__builtin_ia32_rsqrt28ss_round_mask", + "llvm.x86.avx512.scatter.dpd.512" => "__builtin_ia32_scattersiv8df", + "llvm.x86.avx512.scatter.dpi.512" => "__builtin_ia32_scattersiv16si", + "llvm.x86.avx512.scatter.dpq.512" => "__builtin_ia32_scattersiv8di", + "llvm.x86.avx512.scatter.dps.512" => "__builtin_ia32_scattersiv16sf", + "llvm.x86.avx512.scatter.qpd.512" => "__builtin_ia32_scatterdiv8df", + "llvm.x86.avx512.scatter.qpi.512" => "__builtin_ia32_scatterdiv16si", + "llvm.x86.avx512.scatter.qpq.512" => "__builtin_ia32_scatterdiv8di", + "llvm.x86.avx512.scatter.qps.512" => "__builtin_ia32_scatterdiv16sf", "llvm.x86.avx512.scatterpf.dpd.512" => "__builtin_ia32_scatterpfdpd", "llvm.x86.avx512.scatterpf.dps.512" => "__builtin_ia32_scatterpfdps", "llvm.x86.avx512.scatterpf.qpd.512" => "__builtin_ia32_scatterpfqpd", "llvm.x86.avx512.scatterpf.qps.512" => "__builtin_ia32_scatterpfqps", + "llvm.x86.avx512.sqrt.pd.512" => "__builtin_ia32_sqrtpd512_mask", + "llvm.x86.avx512.sqrt.ps.512" => "__builtin_ia32_sqrtps512_mask", + "llvm.x86.avx512.sqrt.sd" => "__builtin_ia32_sqrtrndsd", + "llvm.x86.avx512.sqrt.ss" => "__builtin_ia32_sqrtrndss", "llvm.x86.avx512.sub.pd.512" => "__builtin_ia32_subpd512", "llvm.x86.avx512.sub.ps.512" => "__builtin_ia32_subps512", + "llvm.x86.avx512.vbroadcast.sd.512" => "__builtin_ia32_vbroadcastsd512", + "llvm.x86.avx512.vbroadcast.sd.pd.512" => "__builtin_ia32_vbroadcastsd_pd512", + "llvm.x86.avx512.vbroadcast.ss.512" => "__builtin_ia32_vbroadcastss512", + "llvm.x86.avx512.vbroadcast.ss.ps.512" => "__builtin_ia32_vbroadcastss_ps512", "llvm.x86.avx512.vcomi.sd" => "__builtin_ia32_vcomisd", "llvm.x86.avx512.vcomi.ss" => "__builtin_ia32_vcomiss", "llvm.x86.avx512.vcvtsd2si32" => "__builtin_ia32_vcvtsd2si32", @@ -2027,10 +3738,50 @@ match name { "llvm.x86.flags.read.u64" => "__builtin_ia32_readeflags_u64", "llvm.x86.flags.write.u32" => "__builtin_ia32_writeeflags_u32", "llvm.x86.flags.write.u64" => "__builtin_ia32_writeeflags_u64", + "llvm.x86.fma.mask.vfmadd.pd.512" => "__builtin_ia32_vfmaddpd512_mask", + "llvm.x86.fma.mask.vfmadd.ps.512" => "__builtin_ia32_vfmaddps512_mask", + "llvm.x86.fma.mask.vfmaddsub.pd.512" => "__builtin_ia32_vfmaddsubpd512_mask", + "llvm.x86.fma.mask.vfmaddsub.ps.512" => "__builtin_ia32_vfmaddsubps512_mask", + "llvm.x86.fma.mask.vfmsub.pd.512" => "__builtin_ia32_vfmsubpd512_mask", + "llvm.x86.fma.mask.vfmsub.ps.512" => "__builtin_ia32_vfmsubps512_mask", + "llvm.x86.fma.mask.vfmsubadd.pd.512" => "__builtin_ia32_vfmsubaddpd512_mask", + "llvm.x86.fma.mask.vfmsubadd.ps.512" => "__builtin_ia32_vfmsubaddps512_mask", + "llvm.x86.fma.mask.vfnmadd.pd.512" => "__builtin_ia32_vfnmaddpd512_mask", + "llvm.x86.fma.mask.vfnmadd.ps.512" => "__builtin_ia32_vfnmaddps512_mask", + "llvm.x86.fma.mask.vfnmsub.pd.512" => "__builtin_ia32_vfnmsubpd512_mask", + "llvm.x86.fma.mask.vfnmsub.ps.512" => "__builtin_ia32_vfnmsubps512_mask", + "llvm.x86.fma.vfmadd.pd" => "__builtin_ia32_vfmaddpd", + "llvm.x86.fma.vfmadd.pd.256" => "__builtin_ia32_vfmaddpd256", + "llvm.x86.fma.vfmadd.ps" => "__builtin_ia32_vfmaddps", + "llvm.x86.fma.vfmadd.ps.256" => "__builtin_ia32_vfmaddps256", + "llvm.x86.fma.vfmadd.sd" => "__builtin_ia32_vfmaddsd", + "llvm.x86.fma.vfmadd.ss" => "__builtin_ia32_vfmaddss", "llvm.x86.fma.vfmaddsub.pd" => "__builtin_ia32_vfmaddsubpd", "llvm.x86.fma.vfmaddsub.pd.256" => "__builtin_ia32_vfmaddsubpd256", "llvm.x86.fma.vfmaddsub.ps" => "__builtin_ia32_vfmaddsubps", "llvm.x86.fma.vfmaddsub.ps.256" => "__builtin_ia32_vfmaddsubps256", + "llvm.x86.fma.vfmsub.pd" => "__builtin_ia32_vfmsubpd", + "llvm.x86.fma.vfmsub.pd.256" => "__builtin_ia32_vfmsubpd256", + "llvm.x86.fma.vfmsub.ps" => "__builtin_ia32_vfmsubps", + "llvm.x86.fma.vfmsub.ps.256" => "__builtin_ia32_vfmsubps256", + "llvm.x86.fma.vfmsub.sd" => "__builtin_ia32_vfmsubsd", + "llvm.x86.fma.vfmsub.ss" => "__builtin_ia32_vfmsubss", + "llvm.x86.fma.vfmsubadd.pd" => "__builtin_ia32_vfmsubaddpd", + "llvm.x86.fma.vfmsubadd.pd.256" => "__builtin_ia32_vfmsubaddpd256", + "llvm.x86.fma.vfmsubadd.ps" => "__builtin_ia32_vfmsubaddps", + "llvm.x86.fma.vfmsubadd.ps.256" => "__builtin_ia32_vfmsubaddps256", + "llvm.x86.fma.vfnmadd.pd" => "__builtin_ia32_vfnmaddpd", + "llvm.x86.fma.vfnmadd.pd.256" => "__builtin_ia32_vfnmaddpd256", + "llvm.x86.fma.vfnmadd.ps" => "__builtin_ia32_vfnmaddps", + "llvm.x86.fma.vfnmadd.ps.256" => "__builtin_ia32_vfnmaddps256", + "llvm.x86.fma.vfnmadd.sd" => "__builtin_ia32_vfnmaddsd", + "llvm.x86.fma.vfnmadd.ss" => "__builtin_ia32_vfnmaddss", + "llvm.x86.fma.vfnmsub.pd" => "__builtin_ia32_vfnmsubpd", + "llvm.x86.fma.vfnmsub.pd.256" => "__builtin_ia32_vfnmsubpd256", + "llvm.x86.fma.vfnmsub.ps" => "__builtin_ia32_vfnmsubps", + "llvm.x86.fma.vfnmsub.ps.256" => "__builtin_ia32_vfnmsubps256", + "llvm.x86.fma.vfnmsub.sd" => "__builtin_ia32_vfnmsubsd", + "llvm.x86.fma.vfnmsub.ss" => "__builtin_ia32_vfnmsubss", "llvm.x86.fxrstor" => "__builtin_ia32_fxrstor", "llvm.x86.fxrstor64" => "__builtin_ia32_fxrstor64", "llvm.x86.fxsave" => "__builtin_ia32_fxsave", @@ -2134,6 +3885,7 @@ match name { "llvm.x86.rdsspd" => "__builtin_ia32_rdsspd", "llvm.x86.rdsspq" => "__builtin_ia32_rdsspq", "llvm.x86.rdtsc" => "__builtin_ia32_rdtsc", + "llvm.x86.rdtscp" => "__builtin_ia32_rdtscp", "llvm.x86.rstorssp" => "__builtin_ia32_rstorssp", "llvm.x86.saveprevssp" => "__builtin_ia32_saveprevssp", "llvm.x86.senduipi" => "__builtin_ia32_senduipi", @@ -2147,6 +3899,8 @@ match name { "llvm.x86.sha256msg2" => "__builtin_ia32_sha256msg2", "llvm.x86.sha256rnds2" => "__builtin_ia32_sha256rnds2", "llvm.x86.slwpcb" => "__builtin_ia32_slwpcb", + "llvm.x86.sse.add.ss" => "__builtin_ia32_addss", + "llvm.x86.sse.cmp.ps" => "__builtin_ia32_cmpps", "llvm.x86.sse.cmp.ss" => "__builtin_ia32_cmpss", "llvm.x86.sse.comieq.ss" => "__builtin_ia32_comieq", "llvm.x86.sse.comige.ss" => "__builtin_ia32_comige", @@ -2158,30 +3912,40 @@ match name { "llvm.x86.sse.cvtpi2pd" => "__builtin_ia32_cvtpi2pd", "llvm.x86.sse.cvtpi2ps" => "__builtin_ia32_cvtpi2ps", "llvm.x86.sse.cvtps2pi" => "__builtin_ia32_cvtps2pi", + "llvm.x86.sse.cvtsi2ss" => "__builtin_ia32_cvtsi2ss", + "llvm.x86.sse.cvtsi642ss" => "__builtin_ia32_cvtsi642ss", "llvm.x86.sse.cvtss2si" => "__builtin_ia32_cvtss2si", "llvm.x86.sse.cvtss2si64" => "__builtin_ia32_cvtss2si64", "llvm.x86.sse.cvttpd2pi" => "__builtin_ia32_cvttpd2pi", "llvm.x86.sse.cvttps2pi" => "__builtin_ia32_cvttps2pi", "llvm.x86.sse.cvttss2si" => "__builtin_ia32_cvttss2si", "llvm.x86.sse.cvttss2si64" => "__builtin_ia32_cvttss2si64", + "llvm.x86.sse.div.ss" => "__builtin_ia32_divss", "llvm.x86.sse.max.ps" => "__builtin_ia32_maxps", "llvm.x86.sse.max.ss" => "__builtin_ia32_maxss", "llvm.x86.sse.min.ps" => "__builtin_ia32_minps", "llvm.x86.sse.min.ss" => "__builtin_ia32_minss", "llvm.x86.sse.movmsk.ps" => "__builtin_ia32_movmskps", + "llvm.x86.sse.mul.ss" => "__builtin_ia32_mulss", "llvm.x86.sse.pshuf.w" => "__builtin_ia32_pshufw", "llvm.x86.sse.rcp.ps" => "__builtin_ia32_rcpps", "llvm.x86.sse.rcp.ss" => "__builtin_ia32_rcpss", "llvm.x86.sse.rsqrt.ps" => "__builtin_ia32_rsqrtps", "llvm.x86.sse.rsqrt.ss" => "__builtin_ia32_rsqrtss", "llvm.x86.sse.sfence" => "__builtin_ia32_sfence", + "llvm.x86.sse.sqrt.ps" => "__builtin_ia32_sqrtps", + "llvm.x86.sse.sqrt.ss" => "__builtin_ia32_sqrtss", + "llvm.x86.sse.storeu.ps" => "__builtin_ia32_storeups", + "llvm.x86.sse.sub.ss" => "__builtin_ia32_subss", "llvm.x86.sse.ucomieq.ss" => "__builtin_ia32_ucomieq", "llvm.x86.sse.ucomige.ss" => "__builtin_ia32_ucomige", "llvm.x86.sse.ucomigt.ss" => "__builtin_ia32_ucomigt", "llvm.x86.sse.ucomile.ss" => "__builtin_ia32_ucomile", "llvm.x86.sse.ucomilt.ss" => "__builtin_ia32_ucomilt", "llvm.x86.sse.ucomineq.ss" => "__builtin_ia32_ucomineq", + "llvm.x86.sse2.add.sd" => "__builtin_ia32_addsd", "llvm.x86.sse2.clflush" => "__builtin_ia32_clflush", + "llvm.x86.sse2.cmp.pd" => "__builtin_ia32_cmppd", "llvm.x86.sse2.cmp.sd" => "__builtin_ia32_cmpsd", "llvm.x86.sse2.comieq.sd" => "__builtin_ia32_comisdeq", "llvm.x86.sse2.comige.sd" => "__builtin_ia32_comisdge", @@ -2189,16 +3953,23 @@ match name { "llvm.x86.sse2.comile.sd" => "__builtin_ia32_comisdle", "llvm.x86.sse2.comilt.sd" => "__builtin_ia32_comisdlt", "llvm.x86.sse2.comineq.sd" => "__builtin_ia32_comisdneq", + "llvm.x86.sse2.cvtdq2pd" => "__builtin_ia32_cvtdq2pd", + "llvm.x86.sse2.cvtdq2ps" => "__builtin_ia32_cvtdq2ps", "llvm.x86.sse2.cvtpd2dq" => "__builtin_ia32_cvtpd2dq", "llvm.x86.sse2.cvtpd2ps" => "__builtin_ia32_cvtpd2ps", "llvm.x86.sse2.cvtps2dq" => "__builtin_ia32_cvtps2dq", + "llvm.x86.sse2.cvtps2pd" => "__builtin_ia32_cvtps2pd", "llvm.x86.sse2.cvtsd2si" => "__builtin_ia32_cvtsd2si", "llvm.x86.sse2.cvtsd2si64" => "__builtin_ia32_cvtsd2si64", "llvm.x86.sse2.cvtsd2ss" => "__builtin_ia32_cvtsd2ss", + "llvm.x86.sse2.cvtsi2sd" => "__builtin_ia32_cvtsi2sd", + "llvm.x86.sse2.cvtsi642sd" => "__builtin_ia32_cvtsi642sd", + "llvm.x86.sse2.cvtss2sd" => "__builtin_ia32_cvtss2sd", "llvm.x86.sse2.cvttpd2dq" => "__builtin_ia32_cvttpd2dq", "llvm.x86.sse2.cvttps2dq" => "__builtin_ia32_cvttps2dq", "llvm.x86.sse2.cvttsd2si" => "__builtin_ia32_cvttsd2si", "llvm.x86.sse2.cvttsd2si64" => "__builtin_ia32_cvttsd2si64", + "llvm.x86.sse2.div.sd" => "__builtin_ia32_divsd", "llvm.x86.sse2.lfence" => "__builtin_ia32_lfence", "llvm.x86.sse2.maskmov.dqu" => "__builtin_ia32_maskmovdqu", "llvm.x86.sse2.max.pd" => "__builtin_ia32_maxpd", @@ -2207,18 +3978,33 @@ match name { "llvm.x86.sse2.min.pd" => "__builtin_ia32_minpd", "llvm.x86.sse2.min.sd" => "__builtin_ia32_minsd", "llvm.x86.sse2.movmsk.pd" => "__builtin_ia32_movmskpd", + "llvm.x86.sse2.mul.sd" => "__builtin_ia32_mulsd", "llvm.x86.sse2.packssdw.128" => "__builtin_ia32_packssdw128", "llvm.x86.sse2.packsswb.128" => "__builtin_ia32_packsswb128", "llvm.x86.sse2.packuswb.128" => "__builtin_ia32_packuswb128", + "llvm.x86.sse2.padds.b" => "__builtin_ia32_paddsb128", + "llvm.x86.sse2.padds.w" => "__builtin_ia32_paddsw128", + "llvm.x86.sse2.paddus.b" => "__builtin_ia32_paddusb128", + "llvm.x86.sse2.paddus.w" => "__builtin_ia32_paddusw128", "llvm.x86.sse2.pause" => "__builtin_ia32_pause", "llvm.x86.sse2.pavg.b" => "__builtin_ia32_pavgb128", "llvm.x86.sse2.pavg.w" => "__builtin_ia32_pavgw128", "llvm.x86.sse2.pmadd.wd" => "__builtin_ia32_pmaddwd128", + "llvm.x86.sse2.pmaxs.w" => "__builtin_ia32_pmaxsw128", + "llvm.x86.sse2.pmaxu.b" => "__builtin_ia32_pmaxub128", + "llvm.x86.sse2.pmins.w" => "__builtin_ia32_pminsw128", + "llvm.x86.sse2.pminu.b" => "__builtin_ia32_pminub128", "llvm.x86.sse2.pmovmskb.128" => "__builtin_ia32_pmovmskb128", "llvm.x86.sse2.pmulh.w" => "__builtin_ia32_pmulhw128", "llvm.x86.sse2.pmulhu.w" => "__builtin_ia32_pmulhuw128", + "llvm.x86.sse2.pmulu.dq" => "__builtin_ia32_pmuludq128", "llvm.x86.sse2.psad.bw" => "__builtin_ia32_psadbw128", + "llvm.x86.sse2.pshuf.d" => "__builtin_ia32_pshufd", + "llvm.x86.sse2.pshufh.w" => "__builtin_ia32_pshufhw", + "llvm.x86.sse2.pshufl.w" => "__builtin_ia32_pshuflw", "llvm.x86.sse2.psll.d" => "__builtin_ia32_pslld128", + "llvm.x86.sse2.psll.dq" => "__builtin_ia32_pslldqi128", + "llvm.x86.sse2.psll.dq.bs" => "__builtin_ia32_pslldqi128_byteshift", "llvm.x86.sse2.psll.q" => "__builtin_ia32_psllq128", "llvm.x86.sse2.psll.w" => "__builtin_ia32_psllw128", "llvm.x86.sse2.pslli.d" => "__builtin_ia32_pslldi128", @@ -2229,11 +4015,23 @@ match name { "llvm.x86.sse2.psrai.d" => "__builtin_ia32_psradi128", "llvm.x86.sse2.psrai.w" => "__builtin_ia32_psrawi128", "llvm.x86.sse2.psrl.d" => "__builtin_ia32_psrld128", + "llvm.x86.sse2.psrl.dq" => "__builtin_ia32_psrldqi128", + "llvm.x86.sse2.psrl.dq.bs" => "__builtin_ia32_psrldqi128_byteshift", "llvm.x86.sse2.psrl.q" => "__builtin_ia32_psrlq128", "llvm.x86.sse2.psrl.w" => "__builtin_ia32_psrlw128", "llvm.x86.sse2.psrli.d" => "__builtin_ia32_psrldi128", "llvm.x86.sse2.psrli.q" => "__builtin_ia32_psrlqi128", "llvm.x86.sse2.psrli.w" => "__builtin_ia32_psrlwi128", + "llvm.x86.sse2.psubs.b" => "__builtin_ia32_psubsb128", + "llvm.x86.sse2.psubs.w" => "__builtin_ia32_psubsw128", + "llvm.x86.sse2.psubus.b" => "__builtin_ia32_psubusb128", + "llvm.x86.sse2.psubus.w" => "__builtin_ia32_psubusw128", + "llvm.x86.sse2.sqrt.pd" => "__builtin_ia32_sqrtpd", + "llvm.x86.sse2.sqrt.sd" => "__builtin_ia32_sqrtsd", + "llvm.x86.sse2.storel.dq" => "__builtin_ia32_storelv4si", + "llvm.x86.sse2.storeu.dq" => "__builtin_ia32_storedqu", + "llvm.x86.sse2.storeu.pd" => "__builtin_ia32_storeupd", + "llvm.x86.sse2.sub.sd" => "__builtin_ia32_subsd", "llvm.x86.sse2.ucomieq.sd" => "__builtin_ia32_ucomisdeq", "llvm.x86.sse2.ucomige.sd" => "__builtin_ia32_ucomisdge", "llvm.x86.sse2.ucomigt.sd" => "__builtin_ia32_ucomisdgt", @@ -2249,15 +4047,41 @@ match name { "llvm.x86.sse3.ldu.dq" => "__builtin_ia32_lddqu", "llvm.x86.sse3.monitor" => "__builtin_ia32_monitor", "llvm.x86.sse3.mwait" => "__builtin_ia32_mwait", + "llvm.x86.sse41.blendpd" => "__builtin_ia32_blendpd", + "llvm.x86.sse41.blendps" => "__builtin_ia32_blendps", "llvm.x86.sse41.blendvpd" => "__builtin_ia32_blendvpd", "llvm.x86.sse41.blendvps" => "__builtin_ia32_blendvps", "llvm.x86.sse41.dppd" => "__builtin_ia32_dppd", "llvm.x86.sse41.dpps" => "__builtin_ia32_dpps", + "llvm.x86.sse41.extractps" => "__builtin_ia32_extractps128", "llvm.x86.sse41.insertps" => "__builtin_ia32_insertps128", + "llvm.x86.sse41.movntdqa" => "__builtin_ia32_movntdqa", "llvm.x86.sse41.mpsadbw" => "__builtin_ia32_mpsadbw128", "llvm.x86.sse41.packusdw" => "__builtin_ia32_packusdw128", "llvm.x86.sse41.pblendvb" => "__builtin_ia32_pblendvb128", + "llvm.x86.sse41.pblendw" => "__builtin_ia32_pblendw128", "llvm.x86.sse41.phminposuw" => "__builtin_ia32_phminposuw128", + "llvm.x86.sse41.pmaxsb" => "__builtin_ia32_pmaxsb128", + "llvm.x86.sse41.pmaxsd" => "__builtin_ia32_pmaxsd128", + "llvm.x86.sse41.pmaxud" => "__builtin_ia32_pmaxud128", + "llvm.x86.sse41.pmaxuw" => "__builtin_ia32_pmaxuw128", + "llvm.x86.sse41.pminsb" => "__builtin_ia32_pminsb128", + "llvm.x86.sse41.pminsd" => "__builtin_ia32_pminsd128", + "llvm.x86.sse41.pminud" => "__builtin_ia32_pminud128", + "llvm.x86.sse41.pminuw" => "__builtin_ia32_pminuw128", + "llvm.x86.sse41.pmovsxbd" => "__builtin_ia32_pmovsxbd128", + "llvm.x86.sse41.pmovsxbq" => "__builtin_ia32_pmovsxbq128", + "llvm.x86.sse41.pmovsxbw" => "__builtin_ia32_pmovsxbw128", + "llvm.x86.sse41.pmovsxdq" => "__builtin_ia32_pmovsxdq128", + "llvm.x86.sse41.pmovsxwd" => "__builtin_ia32_pmovsxwd128", + "llvm.x86.sse41.pmovsxwq" => "__builtin_ia32_pmovsxwq128", + "llvm.x86.sse41.pmovzxbd" => "__builtin_ia32_pmovzxbd128", + "llvm.x86.sse41.pmovzxbq" => "__builtin_ia32_pmovzxbq128", + "llvm.x86.sse41.pmovzxbw" => "__builtin_ia32_pmovzxbw128", + "llvm.x86.sse41.pmovzxdq" => "__builtin_ia32_pmovzxdq128", + "llvm.x86.sse41.pmovzxwd" => "__builtin_ia32_pmovzxwd128", + "llvm.x86.sse41.pmovzxwq" => "__builtin_ia32_pmovzxwq128", + "llvm.x86.sse41.pmuldq" => "__builtin_ia32_pmuldq128", "llvm.x86.sse41.ptestc" => "__builtin_ia32_ptestc128", "llvm.x86.sse41.ptestnzc" => "__builtin_ia32_ptestnzc128", "llvm.x86.sse41.ptestz" => "__builtin_ia32_ptestz128", @@ -2287,9 +4111,14 @@ match name { "llvm.x86.sse4a.extrqi" => "__builtin_ia32_extrqi", "llvm.x86.sse4a.insertq" => "__builtin_ia32_insertq", "llvm.x86.sse4a.insertqi" => "__builtin_ia32_insertqi", + "llvm.x86.sse4a.movnt.sd" => "__builtin_ia32_movntsd", + "llvm.x86.sse4a.movnt.ss" => "__builtin_ia32_movntss", "llvm.x86.ssse3.pabs.b" => "__builtin_ia32_pabsb", + "llvm.x86.ssse3.pabs.b.128" => "__builtin_ia32_pabsb128", "llvm.x86.ssse3.pabs.d" => "__builtin_ia32_pabsd", + "llvm.x86.ssse3.pabs.d.128" => "__builtin_ia32_pabsd128", "llvm.x86.ssse3.pabs.w" => "__builtin_ia32_pabsw", + "llvm.x86.ssse3.pabs.w.128" => "__builtin_ia32_pabsw128", "llvm.x86.ssse3.phadd.d" => "__builtin_ia32_phaddd", "llvm.x86.ssse3.phadd.d.128" => "__builtin_ia32_phaddd128", "llvm.x86.ssse3.phadd.sw" => "__builtin_ia32_phaddsw", @@ -2316,6 +4145,8 @@ match name { "llvm.x86.ssse3.psign.w.128" => "__builtin_ia32_psignw128", "llvm.x86.sttilecfg" => "__builtin_ia32_tile_storeconfig", "llvm.x86.stui" => "__builtin_ia32_stui", + "llvm.x86.subborrow.u32" => "__builtin_ia32_subborrow_u32", + "llvm.x86.subborrow.u64" => "__builtin_ia32_subborrow_u64", "llvm.x86.tbm.bextri.u32" => "__builtin_ia32_bextri_u32", "llvm.x86.tbm.bextri.u64" => "__builtin_ia32_bextri_u64", "llvm.x86.tdpbf16ps" => "__builtin_ia32_tdpbf16ps", @@ -2341,6 +4172,8 @@ match name { "llvm.x86.tpause" => "__builtin_ia32_tpause", "llvm.x86.umonitor" => "__builtin_ia32_umonitor", "llvm.x86.umwait" => "__builtin_ia32_umwait", + "llvm.x86.vcvtph2ps.128" => "__builtin_ia32_vcvtph2ps", + "llvm.x86.vcvtph2ps.256" => "__builtin_ia32_vcvtph2ps256", "llvm.x86.vcvtps2ph.128" => "__builtin_ia32_vcvtps2ph", "llvm.x86.vcvtps2ph.256" => "__builtin_ia32_vcvtps2ph256", "llvm.x86.vgf2p8affineinvqb.128" => "__builtin_ia32_vgf2p8affineinvqb_v16qi", @@ -2372,6 +4205,16 @@ match name { "llvm.x86.xop.vfrcz.ps.256" => "__builtin_ia32_vfrczps256", "llvm.x86.xop.vfrcz.sd" => "__builtin_ia32_vfrczsd", "llvm.x86.xop.vfrcz.ss" => "__builtin_ia32_vfrczss", + "llvm.x86.xop.vpcmov" => "__builtin_ia32_vpcmov", + "llvm.x86.xop.vpcmov.256" => "__builtin_ia32_vpcmov_256", + "llvm.x86.xop.vpcomb" => "__builtin_ia32_vpcomb", + "llvm.x86.xop.vpcomd" => "__builtin_ia32_vpcomd", + "llvm.x86.xop.vpcomq" => "__builtin_ia32_vpcomq", + "llvm.x86.xop.vpcomub" => "__builtin_ia32_vpcomub", + "llvm.x86.xop.vpcomud" => "__builtin_ia32_vpcomud", + "llvm.x86.xop.vpcomuq" => "__builtin_ia32_vpcomuq", + "llvm.x86.xop.vpcomuw" => "__builtin_ia32_vpcomuw", + "llvm.x86.xop.vpcomw" => "__builtin_ia32_vpcomw", "llvm.x86.xop.vpermil2pd" => "__builtin_ia32_vpermil2pd", "llvm.x86.xop.vpermil2pd.256" => "__builtin_ia32_vpermil2pd256", "llvm.x86.xop.vpermil2ps" => "__builtin_ia32_vpermil2ps", @@ -2404,6 +4247,14 @@ match name { "llvm.x86.xop.vpmadcsswd" => "__builtin_ia32_vpmadcsswd", "llvm.x86.xop.vpmadcswd" => "__builtin_ia32_vpmadcswd", "llvm.x86.xop.vpperm" => "__builtin_ia32_vpperm", + "llvm.x86.xop.vprotb" => "__builtin_ia32_vprotb", + "llvm.x86.xop.vprotbi" => "__builtin_ia32_vprotbi", + "llvm.x86.xop.vprotd" => "__builtin_ia32_vprotd", + "llvm.x86.xop.vprotdi" => "__builtin_ia32_vprotdi", + "llvm.x86.xop.vprotq" => "__builtin_ia32_vprotq", + "llvm.x86.xop.vprotqi" => "__builtin_ia32_vprotqi", + "llvm.x86.xop.vprotw" => "__builtin_ia32_vprotw", + "llvm.x86.xop.vprotwi" => "__builtin_ia32_vprotwi", "llvm.x86.xop.vpshab" => "__builtin_ia32_vpshab", "llvm.x86.xop.vpshad" => "__builtin_ia32_vpshad", "llvm.x86.xop.vpshaq" => "__builtin_ia32_vpshaq",