Mark feature with missing corresponding target feature cfgs as such
Computed by diffing of:
$ rg "[ ]+@FEATURE: .*: \"(.*)\";" -r '$1' --no-filename \
crates/std_detect/src/detect/ | sort | uniq
With (from the main Rust repo[^1]):
$ rg "target_feature" tests/ui/check-cfg/well-known-values.stderr
[^1]: e8c698bb3b/tests/ui/check-cfg/well-known-values.stderr (L177)
This commit is contained in:
Urgau
Amanieu d'Antras
parent
a6a49cfd90
commit
f62e1daa2d
6 changed files with 27 additions and 0 deletions
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@ -160,6 +160,7 @@ features! {
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@FEATURE: #[unstable(feature = "stdarch_aarch64_feature_detection", issue = "127764")] fp8fma: "fp8fma";
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/// FEAT_FP8FMA (F8FMA Instructions)
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@FEATURE: #[unstable(feature = "stdarch_aarch64_feature_detection", issue = "127764")] fpmr: "fpmr";
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without cfg check: true;
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/// FEAT_FPMR (Special-purpose AArch64-FPMR register)
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@FEATURE: #[stable(feature = "simd_aarch64", since = "1.60.0")] frintts: "frintts";
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/// FEAT_FRINTTS (float to integer rounding instructions)
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@ -14,6 +14,7 @@ features! {
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@FEATURE: #[unstable(feature = "stdarch_arm_feature_detection", issue = "111190")] neon: "neon";
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/// ARM Advanced SIMD (NEON) - Aarch32
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@FEATURE: #[unstable(feature = "stdarch_arm_feature_detection", issue = "111190")] pmull: "pmull";
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without cfg check: true;
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/// Polynomial Multiply
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@FEATURE: #[unstable(feature = "stdarch_arm_feature_detection", issue = "111190")] crc: "crc";
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/// CRC32 (Cyclic Redundancy Check)
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@ -12,5 +12,6 @@ features! {
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@FEATURE: #[unstable(feature = "stdarch_powerpc_feature_detection", issue = "111191")] vsx: "vsx";
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/// VSX
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@FEATURE: #[unstable(feature = "stdarch_powerpc_feature_detection", issue = "111191")] power8: "power8";
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without cfg check: true;
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/// Power8
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}
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@ -12,5 +12,6 @@ features! {
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@FEATURE: #[unstable(feature = "stdarch_powerpc_feature_detection", issue = "111191")] vsx: "vsx";
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/// VSX
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@FEATURE: #[unstable(feature = "stdarch_powerpc_feature_detection", issue = "111191")] power8: "power8";
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without cfg check: true;
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/// Power8
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}
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@ -90,28 +90,36 @@ features! {
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/// [ISA manual]: https://github.com/riscv/riscv-isa-manual/
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#[stable(feature = "riscv_ratified", since = "1.76.0")]
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] rv32i: "rv32i";
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without cfg check: true;
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/// RV32I Base Integer Instruction Set
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zifencei: "zifencei";
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without cfg check: true;
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/// "Zifencei" Instruction-Fetch Fence
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zihintpause: "zihintpause";
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without cfg check: true;
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/// "Zihintpause" Pause Hint
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] rv64i: "rv64i";
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without cfg check: true;
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/// RV64I Base Integer Instruction Set
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@FEATURE: #[stable(feature = "riscv_ratified", since = "1.76.0")] m: "m";
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/// "M" Standard Extension for Integer Multiplication and Division
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@FEATURE: #[stable(feature = "riscv_ratified", since = "1.76.0")] a: "a";
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/// "A" Standard Extension for Atomic Instructions
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zicsr: "zicsr";
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without cfg check: true;
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/// "Zicsr", Control and Status Register (CSR) Instructions
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zicntr: "zicntr";
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without cfg check: true;
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/// "Zicntr", Standard Extension for Base Counters and Timers
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zihpm: "zihpm";
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without cfg check: true;
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/// "Zihpm", Standard Extension for Hardware Performance Counters
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] f: "f";
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/// "F" Standard Extension for Single-Precision Floating-Point
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] d: "d";
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/// "D" Standard Extension for Double-Precision Floating-Point
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] q: "q";
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without cfg check: true;
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/// "Q" Standard Extension for Quad-Precision Floating-Point
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@FEATURE: #[stable(feature = "riscv_ratified", since = "1.76.0")] c: "c";
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/// "C" Standard Extension for Compressed Instructions
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@ -125,34 +133,45 @@ features! {
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zhinxmin: "zhinxmin";
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/// "Zhinxmin" Standard Extension for Minimal Half-Precision Floating-Point in Integer Registers
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] ztso: "ztso";
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without cfg check: true;
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/// "Ztso" Standard Extension for Total Store Ordering
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] rv32e: "rv32e";
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without cfg check: true;
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/// RV32E Base Integer Instruction Set
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] rv128i: "rv128i";
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without cfg check: true;
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/// RV128I Base Integer Instruction Set
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zfh: "zfh";
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/// "Zfh" Standard Extension for 16-Bit Half-Precision Floating-Point
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zfhmin: "zfhmin";
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/// "Zfhmin" Standard Extension for Minimal Half-Precision Floating-Point Support
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] j: "j";
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without cfg check: true;
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/// "J" Standard Extension for Dynamically Translated Languages
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] p: "p";
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without cfg check: true;
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/// "P" Standard Extension for Packed-SIMD Instructions
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] v: "v";
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/// "V" Standard Extension for Vector Operations
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zam: "zam";
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without cfg check: true;
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/// "Zam" Standard Extension for Misaligned Atomics
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] s: "s";
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without cfg check: true;
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/// Supervisor-Level ISA
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] svnapot: "svnapot";
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without cfg check: true;
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/// "Svnapot" Standard Extension for NAPOT Translation Contiguity
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] svpbmt: "svpbmt";
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without cfg check: true;
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/// "Svpbmt" Standard Extension for Page-Based Memory Types
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] svinval: "svinval";
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without cfg check: true;
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/// "Svinval" Standard Extension for Fine-Grained Address-Translation Cache Invalidation
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@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] h: "h";
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without cfg check: true;
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/// Hypervisor Extension
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@FEATURE: #[stable(feature = "riscv_ratified", since = "1.76.0")] zba: "zba";
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@ -123,8 +123,10 @@ features! {
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@FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] rdseed: "rdseed";
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/// RDSEED
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@FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] tsc: "tsc";
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without cfg check: true;
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/// TSC (Time Stamp Counter)
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@FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] mmx: "mmx";
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without cfg check: true;
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/// MMX (MultiMedia eXtensions)
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@FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] sse: "sse";
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/// SSE (Streaming SIMD Extensions)
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@ -157,8 +159,10 @@ features! {
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@FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] avx512cd: "avx512cd" ;
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/// AVX-512 CD (Conflict Detection Instructions)
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@FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] avx512er: "avx512er";
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without cfg check: true;
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/// AVX-512 ER (Expo nential and Reciprocal Instructions)
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@FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] avx512pf: "avx512pf";
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without cfg check: true;
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/// AVX-512 PF (Prefetch Instructions)
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@FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] avx512bw: "avx512bw";
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/// AVX-512 BW (Byte and Word Instructions)
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