From f87d80f7c4cb975643adcd1ddaf26a094feb1780 Mon Sep 17 00:00:00 2001 From: tyler Date: Fri, 19 Apr 2019 10:16:48 -0700 Subject: [PATCH] Add link to intel instruction set reference --- library/stdarch/crates/core_arch/src/x86/rtm.rs | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/library/stdarch/crates/core_arch/src/x86/rtm.rs b/library/stdarch/crates/core_arch/src/x86/rtm.rs index 0b4f6096e26b..00595c718006 100644 --- a/library/stdarch/crates/core_arch/src/x86/rtm.rs +++ b/library/stdarch/crates/core_arch/src/x86/rtm.rs @@ -2,10 +2,14 @@ //! //! This CPU feature is available on Intel Broadwell or later CPUs (and some Haswell). //! +//! The reference is [Intel 64 and IA-32 Architectures Software Developer's +//! Manual Volume 2: Instruction Set Reference, A-Z][intel64_ref]. +//! //! [Wikipedia][wikipedia_rtm] provides a quick overview of the assembly instructions, and //! Intel's [programming considerations][intel_consid] details what sorts of instructions within a //! transaction are likely to cause an abort. //! +//! [intel64_ref]: http://www.intel.de/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf //! [wikipedia_rtm]: https://en.wikipedia.org/wiki/Transactional_Synchronization_Extensions#Restricted_Transactional_Memory //! [intel_consid]: https://software.intel.com/en-us/cpp-compiler-developer-guide-and-reference-intel-transactional-synchronization-extensions-intel-tsx-programming-considerations