From fef16d2cbaa9288631ce6047eaf006c58b419a56 Mon Sep 17 00:00:00 2001 From: Jonathan 'theJPster' Pallant Date: Sun, 12 Oct 2025 17:52:57 +0100 Subject: [PATCH] Change armv7a-none-eabihf CFLAGS to assume only single-precision FPU Not all ARMv7-A CPUs have a double-precision FPU. So adjust the CFLAGS from `+vfpv3` (which assumes 32 double-precision registers) to `+fp` (which only assumes 16 double-precision registers). --- src/ci/docker/host-x86_64/dist-various-1/Dockerfile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/ci/docker/host-x86_64/dist-various-1/Dockerfile b/src/ci/docker/host-x86_64/dist-various-1/Dockerfile index 6fcd9242699e..ab29d0e80ac2 100644 --- a/src/ci/docker/host-x86_64/dist-various-1/Dockerfile +++ b/src/ci/docker/host-x86_64/dist-various-1/Dockerfile @@ -130,7 +130,7 @@ ENV CFLAGS_armv5te_unknown_linux_musleabi="-march=armv5te -marm -mfloat-abi=soft CC_armv7a_none_eabi=arm-none-eabi-gcc \ CC_armv7a_none_eabihf=arm-none-eabi-gcc \ CFLAGS_armv7a_none_eabi=-march=armv7-a \ - CFLAGS_armv7a_none_eabihf=-march=armv7-a+vfpv3 \ + CFLAGS_armv7a_none_eabihf=-march=armv7-a+fp \ CC_armv8r_none_eabihf=arm-none-eabi-gcc \ CFLAGS_armv8r_none_eabihf="-march=armv8-r+fp.sp -mfpu=fp-armv8" \ CC_aarch64_unknown_none_softfloat=aarch64-none-elf-gcc \