From ffc9ab629568169f16e8e59720204cdaf8473b25 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?R=C3=A9my=20Rakic?= <remy.rakic+github@gmail.com>
Date: Sat, 6 Mar 2021 01:44:50 +0100
Subject: [PATCH] convert `_mm256_mask_i64gather_epi64` to const generics

---
 .../stdarch/crates/core_arch/src/x86/avx2.rs   | 18 ++++++------------
 1 file changed, 6 insertions(+), 12 deletions(-)

diff --git a/library/stdarch/crates/core_arch/src/x86/avx2.rs b/library/stdarch/crates/core_arch/src/x86/avx2.rs
index 08e284496e81..86ee61c0f7f1 100644
--- a/library/stdarch/crates/core_arch/src/x86/avx2.rs
+++ b/library/stdarch/crates/core_arch/src/x86/avx2.rs
@@ -1707,26 +1707,21 @@ pub unsafe fn _mm256_i64gather_epi64<const SCALE: i32>(
 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mask_i64gather_epi64)
 #[inline]
 #[target_feature(enable = "avx2")]
-#[cfg_attr(test, assert_instr(vpgatherqq, scale = 1))]
-#[rustc_args_required_const(4)]
+#[cfg_attr(test, assert_instr(vpgatherqq, SCALE = 1))]
+#[rustc_legacy_const_generics(4)]
 #[stable(feature = "simd_x86", since = "1.27.0")]
-pub unsafe fn _mm256_mask_i64gather_epi64(
+pub unsafe fn _mm256_mask_i64gather_epi64<const SCALE: i32>(
     src: __m256i,
     slice: *const i64,
     offsets: __m256i,
     mask: __m256i,
-    scale: i32,
 ) -> __m256i {
+    static_assert_imm8_scale!(SCALE);
     let src = src.as_i64x4();
     let mask = mask.as_i64x4();
     let offsets = offsets.as_i64x4();
     let slice = slice as *const i8;
-    macro_rules! call {
-        ($imm8:expr) => {
-            vpgatherqq(src, slice, offsets, mask, $imm8)
-        };
-    }
-    let r = constify_imm8_gather!(scale, call);
+    let r = vpgatherqq(src, slice, offsets, mask, SCALE as i8);
     transmute(r)
 }
 
@@ -5870,12 +5865,11 @@ mod tests {
             arr[i as usize] = i;
         }
         // A multiplier of 8 is word-addressing for i64s
-        let r = _mm256_mask_i64gather_epi64(
+        let r = _mm256_mask_i64gather_epi64::<8>(
             _mm256_set1_epi64x(256),
             arr.as_ptr(),
             _mm256_setr_epi64x(0, 16, 64, 96),
             _mm256_setr_epi64x(-1, -1, -1, 0),
-            8,
         );
         assert_eq_m256i(r, _mm256_setr_epi64x(0, 16, 64, 256));
     }