Commit graph

10 commits

Author SHA1 Message Date
Guillaume Gomez
efb79975f6 Merge commit 'fda0bb9588' into subtree-update_cg_gcc_2025-06-18 2025-06-18 15:11:44 +02:00
Guillaume Gomez
c92f054085 Merge commit '98ed962c7d' into master 2024-07-10 12:44:23 +02:00
Guillaume Gomez
faebf73983 Merge commit 'b385428e3d' into subtree-update_cg_gcc_2024-03-05 2024-03-05 19:58:36 +01:00
Antoni Boucher
242a482c88 Merge commit '11a0cceab9' into subtree-update_cg_gcc_2023-10-09 2023-10-09 15:53:34 -04:00
Antoni Boucher
38c16e9862 Merge commit '1bbee3e217' into sync-cg_gcc-2023-06-19 2023-06-19 18:51:02 -04:00
Antoni Boucher
fac57d9a06 Merge commit 'e8dca3e87d' into sync_from_cg_gcc 2022-06-06 22:04:37 -04:00
bjorn3
3888aafe3a Merge commit '39683d8eb7' into sync_cg_gcc-2022-03-26 2022-03-26 18:29:37 +01:00
Commeownist
7c707e4b95
Implement basic inline asm support (#72)
* Implement basic support for inline assembly

* Disable LTO

We don't support it yet at all

* Handle `inout(reg) var` correctly

Turns out that `+` readwrite output registers cannot be tied with
input variables.

* Add limited support for llvm_asm!

* Handle CHANNEL correctly

* Add support for arbitrary explicit registers

* Handle symbols properly

* Add rudimentary asm tests

* Exclude llvm_asm! tests from tests runs

* Insert `__builtin_unreachable()` after diverging asm blocks
2021-09-05 11:26:01 -04:00
antoyo
5dad13cc3b
Update custom rustc instructions (#73) 2021-08-28 11:34:47 -04:00
Antoni Boucher
afae271d5d Initial commit 2021-08-12 21:46:50 -04:00