Commit graph

40 commits

Author SHA1 Message Date
hyd-dev
2fd4dd20d7
Allow using -C force-unwind-tables=no when panic=unwind 2021-04-11 22:32:40 +08:00
bors
0c7d4effd7 Auto merge of #83592 - nagisa:nagisa/dso_local, r=davidtwco
Set dso_local for hidden, private and local items

This should probably have no real effect in most cases, as e.g. `hidden`
visibility already implies `dso_local` (or at least LLVM IR does not
preserve the `dso_local` setting if the item is already `hidden`), but
it should fix `-Crelocation-model=static` and improve codegen in
executables.

Note that this PR does not exhaustively port the logic in [clang], only the
portion that is necessary to fix a regression from LLVM 12 that relates to
`-Crelocation_model=static`.

Fixes #83335

[clang]: 3001d080c8/clang/lib/CodeGen/CodeGenModule.cpp (L945-L1039)
2021-04-06 02:09:01 +00:00
Amanieu d'Antras
b1bcff0731 Disallow the use of high byte registes as operands on x86_64
They are still allowed on x86 though.

Fixes #83495
2021-04-05 13:38:24 +01:00
Simonas Kazlauskas
2f000a78bf Manually set dso_local when its valid to do so
This should have no real effect in most cases, as e.g. `hidden`
visibility already implies `dso_local` (or at least LLVM IR does not
preserve the `dso_local` setting if the item is already `hidden`), but
it should fix `-Crelocation-model=static` and improve codegen in
executables.

Note that this PR does not exhaustively port the logic in [clang]. Only
the obviously correct portion and what is necessary to fix a regression
from LLVM 12 that relates to `-Crelocation_model=static`.

Fixes #83335

[clang]: 3001d080c8/clang/lib/CodeGen/CodeGenModule.cpp (L945-L1039)
2021-04-03 00:00:29 +03:00
Amanieu d'Antras
62e7331bd2 Mark inline asm tests as requiring LLVM 10.0.1 2021-03-25 20:21:58 +00:00
Simonas Kazlauskas
72fb4379d5 Adjust -Ctarget-cpu=native handling in cg_llvm
When cg_llvm encounters the `-Ctarget-cpu=native` it computes an
explciit set of features that applies to the target in order to
correctly compile code for the host CPU (because e.g. `skylake` alone is
not sufficient to tell if some of the instructions are available or
not).

However there were a couple of issues with how we did this. Firstly, the
order in which features were overriden wasn't quite right – conceptually
you'd expect `-Ctarget-cpu=native` option to override the features that
are implicitly set by the target definition. However due to how other
`-Ctarget-cpu` values are handled we must adopt the following order
of priority:

* Features from -Ctarget-cpu=*; are overriden by
* Features implied by --target; are overriden by
* Features from -Ctarget-feature; are overriden by
* function specific features.

Another problem was in that the function level `target-features`
attribute would overwrite the entire set of the globally enabled
features, rather than just the features the
`#[target_feature(enable/disable)]` specified. With something like
`-Ctarget-cpu=native` we'd end up in a situation wherein a function
without `#[target_feature(enable)]` annotation would have a broader
set of features compared to a function with one such attribute. This
turned out to be a cause of heavy run-time regressions in some code
using these function-level attributes in conjunction with
`-Ctarget-cpu=native`, for example.

With this PR rustc is more careful about specifying the entire set of
features for functions that use `#[target_feature(enable/disable)]` or
`#[instruction_set]` attributes.

Sadly testing the original reproducer for this behaviour is quite
impossible – we cannot rely on `-Ctarget-cpu=native` to be anything in
particular on developer or CI machines.
2021-03-16 21:32:55 +02:00
Nikita Popov
55f345f325 Support LLVM 12 in rustc 2021-02-28 10:19:44 +01:00
Johnathan Van Why
fd21eb18e9 32-bit ARM: Emit lr instead of r14 when specified as an asm! output register.
On 32-bit ARM platforms, the register `r14` has the alias `lr`. When used as an output register in `asm!`, rustc canonicalizes the name to `r14`. LLVM only knows the register by the name `lr`, and rejects it. This changes rustc's LLVM code generation to output `lr` instead.
2021-02-14 23:41:10 -08:00
Erik Desjardins
cd25807223 Use probe-stack=inline-asm in LLVM 11+ 2021-01-14 22:49:16 -05:00
Gus Caplan
d9f237caa6
Add wasm32 support to inline asm 2020-12-01 12:18:21 -06:00
Lzu Tao
79f477bb1f Add asm! support for mips64 2020-10-04 12:01:21 +00:00
Lzu Tao
6cb062dacf mips32: Add f64 hard-float support
co-authored-by: Amanieu <amanieu@gmail.com>
2020-10-04 03:35:52 +00:00
Lzu Tao
446f86e370 Remove useless stringify 2020-09-30 04:33:23 +00:00
bors
6369a98ebd Auto merge of #77008 - fortanix:raoul/lvi-tests, r=Mark-Simulacrum
LVI hardening tests

Mitigating the speculative execution LVI attack against SGX enclaves requires compiler changes (i.e., adding lfences). This pull requests adds various tests to check if this happens correctly.
2020-09-28 03:28:04 +00:00
Lzu Tao
9000710959 Add MIPS asm! support
This patch also:
* Add soft-float supports: only f32
* zero-extend i8/i16 to i32 because MIPS only supports register-length
  arithmetic.
* Update table in asm! chapter in unstable book.
2020-09-27 02:36:50 +00:00
Raoul Strackx
7d3c3fdc1d cleaning up code 2020-09-25 15:13:55 +02:00
Raoul Strackx
8ca26cca29 Building libunwind with new CMakeLists.
The old CMakeLists file of libunwind used the C compiler to compile assembly files. This caused such code not to be hardened.
2020-09-25 15:09:57 +02:00
Raoul Strackx
4d1d0c6bd7 skeleton check module level assembly 2020-09-25 15:02:14 +02:00
Raoul Strackx
bca8e07ef4 rust inline assembly lvi hardening test 2020-09-25 15:02:07 +02:00
Raoul Strackx
cd31f40b6f generic load hardening test 2020-09-22 13:54:15 +02:00
Raoul Strackx
a13239dac2 generic ret hardening test 2020-09-22 13:54:14 +02:00
Amanieu d'Antras
9ae5e95b28 Fix test 2020-08-28 18:53:09 +01:00
Amanieu d'Antras
178c1bbb5b Fix a typo in #75781 2020-08-26 10:49:15 +01:00
Josh Stone
a210a29303 Expand RISCV pseudo-instructions to match LLVM 11 2020-08-22 13:44:54 -07:00
Amanieu d'Antras
4fe4c3b7e3 Add regression test 2020-08-21 19:52:48 +01:00
Amanieu d'Antras
9198e8ad62 Work around LLVM issues with explicit register in inline asm
Fixes #74658
2020-08-03 10:43:09 +01:00
Vadim Petrochenkov
d3277b927a compiletest: Support ignoring tests requiring missing LLVM components 2020-08-02 20:35:24 +03:00
Brian Cain
7a9f29d305 Add initial asm!() support for hexagon
GPRs only
2020-06-16 08:58:13 -05:00
Michal Sudwoj
e18054d5c0 Added comment about static variables 2020-05-24 08:20:40 +02:00
Michal Sudwoj
5ec6b5eaee Fixed tests 2020-05-24 08:20:40 +02:00
Michal Sudwoj
baa801a929 Minor fixes, as requested in PR review 2020-05-24 08:20:40 +02:00
Michal Sudwoj
58fdc43e03 NVPTX support for new asm! 2020-05-24 08:20:35 +02:00
Amanieu d'Antras
46db0dfe8c Fix tests 2020-05-18 14:41:34 +01:00
Amanieu d'Antras
330bdf89b1 Disable asm tests on system llvm 2020-05-18 14:41:33 +01:00
Amanieu d'Antras
ddcdea45b6 The h modifier is only supported by reg_abcd 2020-05-18 14:41:33 +01:00
Amanieu d'Antras
7dfa486d4a Add support for high byte registers on x86 2020-05-18 14:41:32 +01:00
Amanieu d'Antras
8ab0f2d3c5 Add tests for asm! 2020-05-18 14:41:32 +01:00
John Kåre Alsaker
f8f9a2869c Ignore NVPTX tests 2019-06-12 23:09:08 +02:00
varkor
7f0f0e31ec Remove double trailing newlines 2019-04-22 16:57:01 +01:00
Denys Zariaiev
5c7ec6c421 Introduce assembly tests 2019-02-27 23:33:05 +01:00