6ecb3f33f0
The existing `aarch64-unknown-none` target assumes Armv8.0-A as a baseline. However, Arm recently released the Arm Cortex-R82 processor which is the first to implement the Armv8-R AArch64 mode architecture. This architecture is similar to Armv8-A AArch64, however it has a different set of mandatory features, and is based off of Armv8.4. It is largely unrelated to the existing Armv8-R architecture target (`armv8r-none-eabihf`), which only operates in AArch32 mode. The second `aarch64v8r-unknown-none-softfloat` target allows for possible Armv8-R AArch64 CPUs with no FPU, or for use-cases where FPU register stacking is not desired. As with the existing `aarch64-unknown-none` target we have coupled FPU support and Neon support together - there is no 'has FPU but does not have NEON' target proposed even though the architecture technically allows for it. This PR was developed by Ferrous Systems on behalf of Arm. Arm is the owner of these changes. |
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| .. | ||
| cfi | ||
| kcfi | ||
| aarch64-shadow-call-stack-with-fixed-x18.rs | ||
| address-sanitizer-globals-tracking.rs | ||
| dataflow-instrument-functions.rs | ||
| kasan-emits-instrumentation.rs | ||
| memory-track-origins.rs | ||
| memtag-attr-check.rs | ||
| riscv64-shadow-call-stack.rs | ||
| safestack-attr-check.rs | ||
| sanitize-off-asan-kasan.rs | ||
| sanitize-off-inlining.rs | ||
| sanitize-off-kasan-asan.rs | ||
| sanitize-off.rs | ||
| sanitizer-recover.rs | ||
| scs-attr-check.rs | ||