a56b1b9283
Introduces `BackendRepr::ScalableVector` corresponding to scalable vector types annotated with `repr(scalable)` which lowers to a scalable vector type in LLVM. Co-authored-by: Jamie Cunliffe <Jamie.Cunliffe@arm.com>
49 lines
1.6 KiB
Rust
49 lines
1.6 KiB
Rust
//@ edition: 2021
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//@ only-aarch64
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#![crate_type = "lib"]
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#![allow(incomplete_features, internal_features)]
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#![feature(simd_ffi, rustc_attrs, link_llvm_intrinsics)]
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#[derive(Copy, Clone)]
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#[rustc_scalable_vector(4)]
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#[allow(non_camel_case_types)]
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pub struct svint32_t(i32);
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#[inline(never)]
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#[target_feature(enable = "sve")]
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pub unsafe fn svdup_n_s32(op: i32) -> svint32_t {
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extern "C" {
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#[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.dup.x.nxv4i32")]
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fn _svdup_n_s32(op: i32) -> svint32_t;
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}
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unsafe { _svdup_n_s32(op) }
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}
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#[inline]
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#[target_feature(enable = "sve,sve2")]
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pub unsafe fn svxar_n_s32<const IMM3: i32>(op1: svint32_t, op2: svint32_t) -> svint32_t {
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extern "C" {
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#[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.xar.nxv4i32")]
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fn _svxar_n_s32(op1: svint32_t, op2: svint32_t, imm3: i32) -> svint32_t;
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}
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unsafe { _svxar_n_s32(op1, op2, IMM3) }
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}
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#[inline(never)]
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#[no_mangle]
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#[target_feature(enable = "sve,sve2")]
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// CHECK: define <vscale x 4 x i32> @pass_as_ref(ptr {{.*}}align 16{{.*}} %a, <vscale x 4 x i32> %b)
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pub unsafe fn pass_as_ref(a: &svint32_t, b: svint32_t) -> svint32_t {
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// CHECK: load <vscale x 4 x i32>, ptr %a, align 16
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svxar_n_s32::<1>(*a, b)
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}
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#[no_mangle]
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#[target_feature(enable = "sve,sve2")]
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// CHECK: define <vscale x 4 x i32> @test()
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pub unsafe fn test() -> svint32_t {
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let a = svdup_n_s32(1);
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let b = svdup_n_s32(2);
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// CHECK: %_0 = call <vscale x 4 x i32> @pass_as_ref(ptr {{.*}}align 16{{.*}} %a, <vscale x 4 x i32> %b)
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pass_as_ref(&a, b)
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}
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