rust/compiler/rustc_codegen_llvm/src
bors fd847d4d5d Auto merge of #142696 - ZuseZ4:offload-device1, r=oli-obk
Offload host2

r? `@oli-obk`

A follow-up to my previous gpu host PR. With this, I can (in theory) run a sufficiently simple Rust function on GPUs. I tested it on AMD, where the amdgcn tartget of rustc causes issues due to Addressspace castings, which might not be valid. If I (manually) fix them, I can run the generated IR on an AMD GPU. This should conceptually also work on NVIDIA or Intel. I updated the dev-guide acordingly: https://rustc-dev-guide.rust-lang.org/offload/usage.html

I am unhappy with the amount of standalone functions in my offload code, so in my second commit I bundled some of the code around two structs which are Rust versions of the LLVM/Offload structs which they represent. The structs themselves only have doc comments. Since I directly lower everything to llvm-ir I didn't saw a big value in modelling the struct member variables.
2025-10-20 10:17:29 +00:00
..
back Remove inherent methods from llvm::Type 2025-10-04 18:47:18 +10:00
builder Auto merge of #142696 - ZuseZ4:offload-device1, r=oli-obk 2025-10-20 10:17:29 +00:00
coverageinfo use declarative macro for #[derive(TryFromU32)] 2025-10-06 14:54:38 +00:00
debuginfo Use LLVMDIBuilderCreateGlobalVariableExpression 2025-10-12 23:36:26 +11:00
llvm Auto merge of #142696 - ZuseZ4:offload-device1, r=oli-obk 2025-10-20 10:17:29 +00:00
abi.rs Consistently import llvm::Type and llvm::Value 2025-10-06 13:09:16 +11:00
allocator.rs miri: use allocator_shim_contents codegen helper 2025-10-15 21:23:14 +02:00
asm.rs Allow vector-scalar (vs) registers in ppc inline assembly 2025-10-14 09:52:56 -05:00
attributes.rs Consistently import llvm::Type and llvm::Value 2025-10-06 13:09:16 +11:00
base.rs Consistently import llvm::Type and llvm::Value 2025-10-06 13:09:16 +11:00
builder.rs remove intrinsic wrapper functions from LLVM bindings 2025-10-09 09:26:44 +02:00
callee.rs Consistently import llvm::Type and llvm::Value 2025-10-06 13:09:16 +11:00
common.rs Fix ICE on offsetted ZST pointer 2025-10-15 20:06:46 -04:00
consts.rs refactor: Remove LLVMRustInsertPrivateGlobal and define_private_global 2025-10-08 21:59:48 +02:00
context.rs Consistently import llvm::Type and llvm::Value 2025-10-06 13:09:16 +11:00
declare.rs refactor: Remove LLVMRustInsertPrivateGlobal and define_private_global 2025-10-08 21:59:48 +02:00
errors.rs Use the object crate rather than LLVM for extracting bitcode sections 2025-07-25 11:21:28 +00:00
intrinsic.rs Consistently import llvm::Type and llvm::Value 2025-10-06 13:09:16 +11:00
lib.rs Rollup merge of #147526 - bjorn3:alloc_shim_weak_shape, r=petrochenkov,RalfJung 2025-10-14 19:47:29 +02:00
llvm_util.rs Add panic=immediate-abort 2025-09-21 13:12:18 -04:00
macros.rs use declarative macro for #[derive(TryFromU32)] 2025-10-06 14:54:38 +00:00
mono_item.rs Replace the llvm::Bool typedef with a proper newtype 2025-08-24 23:09:54 +10:00
type_.rs Consistently import llvm::Type and llvm::Value 2025-10-06 13:09:16 +11:00
type_of.rs Consistently import llvm::Type and llvm::Value 2025-10-06 13:09:16 +11:00
typetree.rs autodiff: typetree recursive depth query from enzyme with fallback 2025-09-19 05:42:27 +00:00
va_arg.rs Consistently import llvm::Type and llvm::Value 2025-10-06 13:09:16 +11:00
value.rs Consistently import llvm::Type and llvm::Value 2025-10-06 13:09:16 +11:00