| .. |
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aarch64.rs
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compiler: remove rustc_target::abi entirely
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2025-02-07 11:23:12 -08:00 |
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amdgpu.rs
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compiler: remove rustc_target::abi entirely
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2025-02-07 11:23:12 -08:00 |
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arm.rs
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compiler: change Conv to CanonAbi
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2025-06-03 10:03:44 -07:00 |
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avr.rs
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compiler: remove rustc_target::abi entirely
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2025-02-07 11:23:12 -08:00 |
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bpf.rs
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compiler: remove rustc_target::abi entirely
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2025-02-07 11:23:12 -08:00 |
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csky.rs
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compiler: remove rustc_target::abi entirely
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2025-02-07 11:23:12 -08:00 |
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hexagon.rs
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compiler: remove rustc_target::abi entirely
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2025-02-07 11:23:12 -08:00 |
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loongarch.rs
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remove compiler support for extern "rust-intrinsic" blocks
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2025-04-06 21:32:58 +02:00 |
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m68k.rs
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compiler: remove rustc_target::abi entirely
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2025-02-07 11:23:12 -08:00 |
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mips.rs
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compiler: remove rustc_target::abi entirely
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2025-02-07 11:23:12 -08:00 |
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mips64.rs
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compiler: make rustc_target have less weird reexports
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2025-02-06 01:39:46 -08:00 |
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mod.rs
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x86 (32/64): go back to passing SIMD vectors by-ptr
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2025-06-04 08:38:49 +02:00 |
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msp430.rs
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compiler: remove rustc_target::abi entirely
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2025-02-07 11:23:12 -08:00 |
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nvptx64.rs
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compiler: remove rustc_target::abi entirely
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2025-02-07 11:23:12 -08:00 |
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powerpc.rs
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compiler: remove rustc_target::abi entirely
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2025-02-07 11:23:12 -08:00 |
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powerpc64.rs
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compiler: remove rustc_target::abi entirely
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2025-02-07 11:23:12 -08:00 |
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riscv.rs
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remove compiler support for extern "rust-intrinsic" blocks
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2025-04-06 21:32:58 +02:00 |
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s390x.rs
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rename BackendRepr::Vector → SimdVector
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2025-02-28 17:17:45 +01:00 |
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sparc.rs
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compiler: remove rustc_target::abi entirely
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2025-02-07 11:23:12 -08:00 |
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sparc64.rs
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compiler: remove rustc_target::abi entirely
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2025-02-07 11:23:12 -08:00 |
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wasm.rs
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add FCW to warn about wasm ABI transition
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2025-03-25 08:22:35 +01:00 |
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x86.rs
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remove compiler support for extern "rust-intrinsic" blocks
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2025-04-06 21:32:58 +02:00 |
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x86_64.rs
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rename BackendRepr::Vector → SimdVector
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2025-02-28 17:17:45 +01:00 |
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x86_win32.rs
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compiler: factor Windows x86-32 ABI impl into its own file
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2025-03-05 15:11:20 -08:00 |
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x86_win64.rs
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rename BackendRepr::Vector → SimdVector
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2025-02-28 17:17:45 +01:00 |
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xtensa.rs
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rename BackendRepr::Vector → SimdVector
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2025-02-28 17:17:45 +01:00 |
