Guillaume Gomez 470c4f94e8 Rollup merge of #133452 - taiki-e:hexagon-asm-pred, r=Amanieu ... Support predicate registers (clobber-only) in Hexagon inline assembly The result of the Hexagon instructions such as comparison, store conditional, etc. is stored in predicate registers (`p[0-3]`), but currently there is no way to mark it as clobbered in `asm!`. This is also needed for `clobber_abi` (although implementing `clobber_abi` will require the addition of support for [several more register classes](https://github.com/llvm/llvm-project/blob/llvmorg-19.1.0/llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp#L71-L90). see also https://github.com/rust-lang/rust/issues/93335#issuecomment-2395210055). Refs: - [Section 6 "Conditional Execution" in Qualcomm Hexagon V73 Programmer’s Reference Manual](https://docs.qualcomm.com/bundle/publicresource/80-N2040-53_REV_AB_Qualcomm_Hexagon_V73_Programmers_Reference_Manual.pdf#page=90) - [Register definition in LLVM](https://github.com/llvm/llvm-project/blob/llvmorg-19.1.0/llvm/lib/Target/Hexagon/HexagonRegisterInfo.td#L155) cc `@androm3da` (target maintainer of hexagon-unknown-{[none-elf](https://doc.rust-lang.org/nightly/rustc/platform-support/hexagon-unknown-none-elf.html#target-maintainers),[linux-musl](https://doc.rust-lang.org/nightly/rustc/platform-support/hexagon-unknown-linux-musl.html#target-maintainers)}) r? `@Amanieu` `@rustbot` label +A-inline-assembly (Currently there is no O-hexagon label...)		2024-11-28 12:06:02 +01:00
..
back	embed-bitcode is no longer used in iOS	2024-11-24 15:51:47 +08:00
coverageinfo	coverage: Identify source files by ID, not by interned filename	2024-11-24 23:46:41 +11:00
debuginfo	When the required discriminator value exceeds LLVM's limits, drop the debug info for the function instead of panicking.	2024-11-19 05:19:09 -08:00
llvm	Rollup merge of #127483 - BertalanD:no_sanitize-global-var, r=rcvalle	2024-11-23 20:19:51 +08:00
abi.rs	compiler: Directly use rustc_abi in codegen	2024-11-03 12:30:32 -08:00
allocator.rs	Clean up FFI calls for operand bundles	2024-10-30 13:26:24 +11:00
asm.rs	Support predicate registers (clobber-only) in Hexagon inline assembly	2024-11-25 23:11:17 +09:00
attributes.rs	Rollup merge of #132259 - mrkajetanp:branch-protection-pauth-lr, r=davidtwco	2024-11-05 20:10:49 +01:00
base.rs	Allow disabling ASan instrumentation for globals	2024-11-02 22:35:34 +01:00
builder.rs	use TypingEnv when no infcx is available	2024-11-18 10:38:56 +01:00
callee.rs	use TypingEnv when no infcx is available	2024-11-18 10:38:56 +01:00
common.rs	Clean up FFI calls for operand bundles	2024-10-30 13:26:24 +11:00
consts.rs	Rollup merge of #127483 - BertalanD:no_sanitize-global-var, r=rcvalle	2024-11-23 20:19:51 +08:00
context.rs	use TypingEnv when no infcx is available	2024-11-18 10:38:56 +01:00
declare.rs	Use a type-safe helper to cast &str and &[u8] to *const c_char	2024-10-28 21:31:32 +11:00
errors.rs	mark some target features as 'forbidden' so they cannot be (un)set	2024-11-04 22:56:47 +01:00
intrinsic.rs	use TypingEnv when no infcx is available	2024-11-18 10:38:56 +01:00
lib.rs	coverage: Store coverage source regions as Span until codegen	2024-11-24 23:46:39 +11:00
llvm_util.rs	target_features: explain what exacty 'implied' means here	2024-11-11 07:33:39 +01:00
mono_item.rs	use TypingEnv when no infcx is available	2024-11-18 10:38:56 +01:00
type_.rs	compiler: Directly use rustc_abi in codegen	2024-11-03 12:30:32 -08:00
type_of.rs	compiler: rustc_abi::Abi => BackendRepr	2024-10-29 14:56:00 -07:00
va_arg.rs	compiler: Directly use rustc_abi in codegen	2024-11-03 12:30:32 -08:00
value.rs	Add warn(unreachable_pub) to rustc_codegen_llvm.	2024-08-16 08:46:57 +10:00