Tsukasa OI 5c0c7ac77c RISC-V: tidying: Make auxvec-based enablement a block ... Because this function will be no longer auxvec-only, this commit adds a comment to mark auxvec-based part. It *does not* add a comment to "base ISA" part because it may also use `riscv_hwprobe`-based results.		2025-04-16 00:56:48 +00:00
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stdarch	RISC-V: tidying: Make auxvec-based enablement a block	2025-04-16 00:56:48 +00:00