rust/src/test/codegen
Pietro Albini 1997c706bd
Rollup merge of #52908 - lnicola:vec-truncate-opt, r=alexcrichton
Use SetLenOnDrop in Vec::truncate()

This avoids a redundant length check in some cases when calling
`Vec::truncate` or `Vec::clear`.

Fixes #51802

Note that the generated code still seems suboptimal. I tested with the following functions:

```rust
#[no_mangle]
pub extern fn foo(x: &mut Vec<u8>) {
    x.clear();
}

#[no_mangle]
pub extern fn bar(x: &mut Vec<u8>) {
    x.truncate(5);
}

#[no_mangle]
pub extern fn baz(x: &mut Vec<u8>, n: usize) {
    x.truncate(n);
}

#[no_mangle]
pub extern fn foo_string(x: &mut Vec<String>) {
    x.clear();
}

#[no_mangle]
pub extern fn bar_string(x: &mut Vec<String>) {
    x.truncate(5);
}

#[no_mangle]
pub extern fn baz_string(x: &mut Vec<String>, n: usize) {
    x.truncate(n);
}
```

<details>
  <summary>Old output</summary>

```asm
00000000000460a0 <foo>:
   460a0:       48 83 7f 10 00          cmpq   $0x0,0x10(%rdi)
   460a5:       74 08                   je     460af <foo+0xf>
   460a7:       48 c7 47 10 00 00 00    movq   $0x0,0x10(%rdi)
   460ae:       00
   460af:       c3                      retq

00000000000460b0 <bar>:
   460b0:       48 83 7f 10 06          cmpq   $0x6,0x10(%rdi)
   460b5:       72 08                   jb     460bf <bar+0xf>
   460b7:       48 c7 47 10 05 00 00    movq   $0x5,0x10(%rdi)
   460be:       00
   460bf:       c3                      retq

00000000000460c0 <baz>:
   460c0:       48 39 77 10             cmp    %rsi,0x10(%rdi)
   460c4:       76 04                   jbe    460ca <baz+0xa>
   460c6:       48 89 77 10             mov    %rsi,0x10(%rdi)
   460ca:       c3                      retq
   460cb:       0f 1f 44 00 00          nopl   0x0(%rax,%rax,1)

00000000000460d0 <foo_string>:
   460d0:       41 57                   push   %r15
   460d2:       41 56                   push   %r14
   460d4:       53                      push   %rbx
   460d5:       48 8b 47 10             mov    0x10(%rdi),%rax
   460d9:       48 85 c0                test   %rax,%rax
   460dc:       74 4a                   je     46128 <foo_string+0x58>
   460de:       49 89 fe                mov    %rdi,%r14
   460e1:       48 8b 0f                mov    (%rdi),%rcx
   460e4:       48 8d 14 40             lea    (%rax,%rax,2),%rdx
   460e8:       48 8d 58 ff             lea    -0x1(%rax),%rbx
   460ec:       4c 8d 3c d1             lea    (%rcx,%rdx,8),%r15
   460f0:       49 83 c7 f0             add    $0xfffffffffffffff0,%r15
   460f4:       66 2e 0f 1f 84 00 00    nopw   %cs:0x0(%rax,%rax,1)
   460fb:       00 00 00
   460fe:       66 90                   xchg   %ax,%ax
   46100:       49 89 5e 10             mov    %rbx,0x10(%r14)
   46104:       49 8b 37                mov    (%r15),%rsi
   46107:       48 85 f6                test   %rsi,%rsi
   4610a:       74 0e                   je     4611a <foo_string+0x4a>
   4610c:       49 8b 7f f8             mov    -0x8(%r15),%rdi
   46110:       ba 01 00 00 00          mov    $0x1,%edx
   46115:       e8 a6 e9 ff ff          callq  44ac0 <__rust_dealloc@plt>
   4611a:       48 83 c3 ff             add    $0xffffffffffffffff,%rbx
   4611e:       49 83 c7 e8             add    $0xffffffffffffffe8,%r15
   46122:       48 83 fb ff             cmp    $0xffffffffffffffff,%rbx
   46126:       75 d8                   jne    46100 <foo_string+0x30>
   46128:       5b                      pop    %rbx
   46129:       41 5e                   pop    %r14
   4612b:       41 5f                   pop    %r15
   4612d:       c3                      retq
   4612e:       66 90                   xchg   %ax,%ax

0000000000046130 <bar_string>:
   46130:       41 57                   push   %r15
   46132:       41 56                   push   %r14
   46134:       53                      push   %rbx
   46135:       4c 8b 7f 10             mov    0x10(%rdi),%r15
   46139:       49 83 ff 06             cmp    $0x6,%r15
   4613d:       72 49                   jb     46188 <bar_string+0x58>
   4613f:       49 89 fe                mov    %rdi,%r14
   46142:       48 8b 07                mov    (%rdi),%rax
   46145:       4b 8d 0c 7f             lea    (%r15,%r15,2),%rcx
   46149:       48 8d 1c c8             lea    (%rax,%rcx,8),%rbx
   4614d:       48 83 c3 f0             add    $0xfffffffffffffff0,%rbx
   46151:       66 2e 0f 1f 84 00 00    nopw   %cs:0x0(%rax,%rax,1)
   46158:       00 00 00
   4615b:       0f 1f 44 00 00          nopl   0x0(%rax,%rax,1)
   46160:       49 83 c7 ff             add    $0xffffffffffffffff,%r15
   46164:       4d 89 7e 10             mov    %r15,0x10(%r14)
   46168:       48 8b 33                mov    (%rbx),%rsi
   4616b:       48 85 f6                test   %rsi,%rsi
   4616e:       74 0e                   je     4617e <bar_string+0x4e>
   46170:       48 8b 7b f8             mov    -0x8(%rbx),%rdi
   46174:       ba 01 00 00 00          mov    $0x1,%edx
   46179:       e8 42 e9 ff ff          callq  44ac0 <__rust_dealloc@plt>
   4617e:       48 83 c3 e8             add    $0xffffffffffffffe8,%rbx
   46182:       49 83 ff 05             cmp    $0x5,%r15
   46186:       77 d8                   ja     46160 <bar_string+0x30>
   46188:       5b                      pop    %rbx
   46189:       41 5e                   pop    %r14
   4618b:       41 5f                   pop    %r15
   4618d:       c3                      retq
   4618e:       66 90                   xchg   %ax,%ax

0000000000046190 <baz_string>:
   46190:       41 57                   push   %r15
   46192:       41 56                   push   %r14
   46194:       41 54                   push   %r12
   46196:       53                      push   %rbx
   46197:       50                      push   %rax
   46198:       4c 8b 67 10             mov    0x10(%rdi),%r12
   4619c:       49 39 f4                cmp    %rsi,%r12
   4619f:       76 46                   jbe    461e7 <baz_string+0x57>
   461a1:       49 89 f6                mov    %rsi,%r14
   461a4:       49 89 ff                mov    %rdi,%r15
   461a7:       48 8b 07                mov    (%rdi),%rax
   461aa:       4b 8d 0c 64             lea    (%r12,%r12,2),%rcx
   461ae:       48 8d 1c c8             lea    (%rax,%rcx,8),%rbx
   461b2:       48 83 c3 f0             add    $0xfffffffffffffff0,%rbx
   461b6:       66 2e 0f 1f 84 00 00    nopw   %cs:0x0(%rax,%rax,1)
   461bd:       00 00 00
   461c0:       49 83 c4 ff             add    $0xffffffffffffffff,%r12
   461c4:       4d 89 67 10             mov    %r12,0x10(%r15)
   461c8:       48 8b 33                mov    (%rbx),%rsi
   461cb:       48 85 f6                test   %rsi,%rsi
   461ce:       74 0e                   je     461de <baz_string+0x4e>
   461d0:       48 8b 7b f8             mov    -0x8(%rbx),%rdi
   461d4:       ba 01 00 00 00          mov    $0x1,%edx
   461d9:       e8 e2 e8 ff ff          callq  44ac0 <__rust_dealloc@plt>
   461de:       48 83 c3 e8             add    $0xffffffffffffffe8,%rbx
   461e2:       4d 39 f4                cmp    %r14,%r12
   461e5:       77 d9                   ja     461c0 <baz_string+0x30>
   461e7:       48 83 c4 08             add    $0x8,%rsp
   461eb:       5b                      pop    %rbx
   461ec:       41 5c                   pop    %r12
   461ee:       41 5e                   pop    %r14
   461f0:       41 5f                   pop    %r15
   461f2:       c3                      retq
   461f3:       90                      nop
   461f4:       66 2e 0f 1f 84 00 00    nopw   %cs:0x0(%rax,%rax,1)
   461fb:       00 00 00
   461fe:       66 90                   xchg   %ax,%ax
```
</details>

<details>
  <summary>New output</summary>

```asm
0000000000084d10 <foo>:
   84d10:       48 c7 47 10 00 00 00    movq   $0x0,0x10(%rdi)
   84d17:       00
   84d18:       c3                      retq
   84d19:       0f 1f 80 00 00 00 00    nopl   0x0(%rax)

0000000000084d20 <bar>:
   84d20:       48 8b 47 10             mov    0x10(%rdi),%rax
   84d24:       48 83 f8 05             cmp    $0x5,%rax
   84d28:       b9 05 00 00 00          mov    $0x5,%ecx
   84d2d:       48 0f 42 c8             cmovb  %rax,%rcx
   84d31:       48 89 4f 10             mov    %rcx,0x10(%rdi)
   84d35:       c3                      retq
   84d36:       66 2e 0f 1f 84 00 00    nopw   %cs:0x0(%rax,%rax,1)
   84d3d:       00 00 00

0000000000084d40 <baz>:
   84d40:       48 8b 47 10             mov    0x10(%rdi),%rax
   84d44:       48 39 f0                cmp    %rsi,%rax
   84d47:       48 0f 47 c6             cmova  %rsi,%rax
   84d4b:       48 89 47 10             mov    %rax,0x10(%rdi)
   84d4f:       c3                      retq

0000000000084d50 <foo_string>:
   84d50:       41 57                   push   %r15
   84d52:       41 56                   push   %r14
   84d54:       53                      push   %rbx
   84d55:       49 89 fe                mov    %rdi,%r14
   84d58:       4c 8b 7f 10             mov    0x10(%rdi),%r15
   84d5c:       4d 85 ff                test   %r15,%r15
   84d5f:       74 2f                   je     84d90 <foo_string+0x40>
   84d61:       49 8b 06                mov    (%r14),%rax
   84d64:       4b 8d 0c 7f             lea    (%r15,%r15,2),%rcx
   84d68:       48 8d 1c c8             lea    (%rax,%rcx,8),%rbx
   84d6c:       48 83 c3 f0             add    $0xfffffffffffffff0,%rbx
   84d70:       48 8b 33                mov    (%rbx),%rsi
   84d73:       48 85 f6                test   %rsi,%rsi
   84d76:       74 0e                   je     84d86 <foo_string+0x36>
   84d78:       48 8b 7b f8             mov    -0x8(%rbx),%rdi
   84d7c:       ba 01 00 00 00          mov    $0x1,%edx
   84d81:       e8 1a b1 ff ff          callq  7fea0 <__rust_dealloc@plt>
   84d86:       48 83 c3 e8             add    $0xffffffffffffffe8,%rbx
   84d8a:       49 83 c7 ff             add    $0xffffffffffffffff,%r15
   84d8e:       75 e0                   jne    84d70 <foo_string+0x20>
   84d90:       49 c7 46 10 00 00 00    movq   $0x0,0x10(%r14)
   84d97:       00
   84d98:       5b                      pop    %rbx
   84d99:       41 5e                   pop    %r14
   84d9b:       41 5f                   pop    %r15
   84d9d:       c3                      retq
   84d9e:       66 90                   xchg   %ax,%ax

0000000000084da0 <bar_string>:
   84da0:       41 57                   push   %r15
   84da2:       41 56                   push   %r14
   84da4:       53                      push   %rbx
   84da5:       49 89 fe                mov    %rdi,%r14
   84da8:       4c 8b 7f 10             mov    0x10(%rdi),%r15
   84dac:       49 83 ff 06             cmp    $0x6,%r15
   84db0:       72 44                   jb     84df6 <bar_string+0x56>
   84db2:       49 8b 06                mov    (%r14),%rax
   84db5:       4b 8d 0c 7f             lea    (%r15,%r15,2),%rcx
   84db9:       48 8d 1c c8             lea    (%rax,%rcx,8),%rbx
   84dbd:       48 83 c3 f0             add    $0xfffffffffffffff0,%rbx
   84dc1:       49 83 c7 fb             add    $0xfffffffffffffffb,%r15
   84dc5:       66 2e 0f 1f 84 00 00    nopw   %cs:0x0(%rax,%rax,1)
   84dcc:       00 00 00
   84dcf:       90                      nop
   84dd0:       48 8b 33                mov    (%rbx),%rsi
   84dd3:       48 85 f6                test   %rsi,%rsi
   84dd6:       74 0e                   je     84de6 <bar_string+0x46>
   84dd8:       48 8b 7b f8             mov    -0x8(%rbx),%rdi
   84ddc:       ba 01 00 00 00          mov    $0x1,%edx
   84de1:       e8 ba b0 ff ff          callq  7fea0 <__rust_dealloc@plt>
   84de6:       48 83 c3 e8             add    $0xffffffffffffffe8,%rbx
   84dea:       49 83 c7 ff             add    $0xffffffffffffffff,%r15
   84dee:       75 e0                   jne    84dd0 <bar_string+0x30>
   84df0:       41 bf 05 00 00 00       mov    $0x5,%r15d
   84df6:       4d 89 7e 10             mov    %r15,0x10(%r14)
   84dfa:       5b                      pop    %rbx
   84dfb:       41 5e                   pop    %r14
   84dfd:       41 5f                   pop    %r15
   84dff:       c3                      retq

0000000000084e00 <baz_string>:
   84e00:       41 57                   push   %r15
   84e02:       41 56                   push   %r14
   84e04:       41 54                   push   %r12
   84e06:       53                      push   %rbx
   84e07:       50                      push   %rax
   84e08:       49 89 ff                mov    %rdi,%r15
   84e0b:       48 8b 47 10             mov    0x10(%rdi),%rax
   84e0f:       49 89 c4                mov    %rax,%r12
   84e12:       49 29 f4                sub    %rsi,%r12
   84e15:       76 3c                   jbe    84e53 <baz_string+0x53>
   84e17:       49 89 f6                mov    %rsi,%r14
   84e1a:       49 8b 0f                mov    (%r15),%rcx
   84e1d:       48 8d 04 40             lea    (%rax,%rax,2),%rax
   84e21:       48 8d 1c c1             lea    (%rcx,%rax,8),%rbx
   84e25:       48 83 c3 f0             add    $0xfffffffffffffff0,%rbx
   84e29:       0f 1f 80 00 00 00 00    nopl   0x0(%rax)
   84e30:       48 8b 33                mov    (%rbx),%rsi
   84e33:       48 85 f6                test   %rsi,%rsi
   84e36:       74 0e                   je     84e46 <baz_string+0x46>
   84e38:       48 8b 7b f8             mov    -0x8(%rbx),%rdi
   84e3c:       ba 01 00 00 00          mov    $0x1,%edx
   84e41:       e8 5a b0 ff ff          callq  7fea0 <__rust_dealloc@plt>
   84e46:       48 83 c3 e8             add    $0xffffffffffffffe8,%rbx
   84e4a:       49 83 c4 ff             add    $0xffffffffffffffff,%r12
   84e4e:       75 e0                   jne    84e30 <baz_string+0x30>
   84e50:       4c 89 f0                mov    %r14,%rax
   84e53:       49 89 47 10             mov    %rax,0x10(%r15)
   84e57:       48 83 c4 08             add    $0x8,%rsp
   84e5b:       5b                      pop    %rbx
   84e5c:       41 5c                   pop    %r12
   84e5e:       41 5e                   pop    %r14
   84e60:       41 5f                   pop    %r15
   84e62:       c3                      retq
   84e63:       90                      nop
   84e64:       66 2e 0f 1f 84 00 00    nopw   %cs:0x0(%rax,%rax,1)
   84e6b:       00 00 00
   84e6e:       66 90                   xchg   %ax,%ax
```
</details>

For calling `truncate` with non-zero lengths on non-`Drop` types, it seems that a redundant load and comparison gets replaced with an awkward sequence with a conditional move. In the unknown length case, the new code is no longer awkward.

Maybe someone moderately proficient at assembly could tell if this looks like a win or not.

---

This came up when discussing replacing `unsafe { vec.set_len(0) }` with `vec.clear()` in a project where the author was worried about potential performance degradation. It might be worth replacing some unsafe code, even it it's trivial to see that it's actually safe.
2018-08-01 21:46:31 +02:00
..
auxiliary rustc: Add LLVM nounwind with -C panic=abort 2017-10-11 09:05:38 -07:00
dllimports Add 'ignore-cloudabi' to tests that don't and won't build on CloudABI. 2018-01-02 14:11:41 +01:00
remap_path_prefix Codegen tests 2018-03-08 08:34:08 +01:00
abi-main-signature-16bit-c-int.rs test: Ignore some problematic tests on sparc and sparc64 2018-06-04 23:59:40 +02:00
abi-main-signature-32bit-c-int.rs rustc: Use 16bit c_int for msp430 2017-09-30 16:30:12 +02:00
abi-sysv64.rs Stabilize abi_sysv64 2017-12-06 01:19:35 +01:00
abi-x86-interrupt.rs Remove two obsolete min-llvm-version tests 2017-10-18 07:54:35 -07:00
abi-x86_64_sysv.rs Fix oversized loads on x86_64 SysV FFI calls 2018-02-08 13:50:18 +01:00
adjustments.rs rustc: encode scalar pairs in layout ABI. 2017-11-19 02:43:32 +02:00
align-struct.rs Upgrade to LLVM's master branch (LLVM 7) 2018-07-10 13:43:01 -07:00
alloc-optimisation.rs Add a no-system-llvm compilecheck header 2017-06-15 19:11:55 +03:00
call-metadata.rs bump minimum LLVM version to 5.0 2018-07-09 11:35:52 +02:00
coercions.rs Disable old trans access via -Z orbit, #[rustc_no_mir] or --disable-orbit. 2016-08-24 13:23:37 +03:00
consts.rs Upgrade to LLVM's master branch (LLVM 7) 2018-07-10 13:43:01 -07:00
dealloc-no-unwind.rs std: Mark allocation functions as nounwind 2017-08-28 08:06:52 -07:00
drop.rs Update test/codegen/drop.rs to reflect inconsequential change in basic block ordering. 2017-06-12 13:06:42 +02:00
enum-bounds-check.rs emit an assume that cast-from enums are in range 2016-10-05 14:12:30 +03:00
exact_div.rs Add a codegen test for exact_div intrinsic 2018-03-23 23:47:22 -07:00
extern-functions.rs make #[unwind] attribute specify expectations more clearly 2018-02-20 19:12:52 -05:00
fastcall-inreg.rs test: Ignore some problematic tests on sparc and sparc64 2018-06-04 23:59:40 +02:00
fatptr.rs Avoid FCA loads and extractvalue when copying fat pointers 2015-11-20 21:42:13 +01:00
float_math.rs Fix typo in codegen test 2017-10-07 18:04:23 +02:00
foo.s Add global_asm tests 2017-04-12 19:12:50 -05:00
force-frame-pointers.rs Rework force-frame-pointer 2018-05-01 10:44:44 +03:00
function-arguments.rs dont hardcode vtable size in codegen test 2018-07-29 20:24:26 +02:00
gdb_debug_script_load.rs Avoid loading the whole gdb debug scripts section. 2015-09-21 15:43:52 -05:00
global_asm.rs Revert "Remove useless powerpc64 entry from ARCH_TABLE, closes #47737" 2018-03-19 01:34:32 +00:00
global_asm_include.rs Revert "Remove useless powerpc64 entry from ARCH_TABLE, closes #47737" 2018-03-19 01:34:32 +00:00
global_asm_x2.rs Revert "Remove useless powerpc64 entry from ARCH_TABLE, closes #47737" 2018-03-19 01:34:32 +00:00
internalize-closures.rs Add codegen test to make sure that closures are 'internalized' properly. 2016-07-19 06:22:35 -04:00
intrinsic-no-unnamed-attr.rs Don't add unnamed address attributes to intrinsics. 2015-09-06 19:26:41 -05:00
issue-15953.rs Add tests for issues with the 'E-needtest' label. 2017-03-07 14:01:19 +09:00
issue-32031.rs rustc: unpack scalar newtype layout ABIs. 2017-11-19 02:43:55 +02:00
issue-32364.rs adapt tests 2016-10-25 19:56:36 +02:00
issue-34947-pow-i32.rs add test for not optimized pow with constant power 2017-09-02 19:10:00 +03:00
issue-37945.rs bump minimum LLVM version to 5.0 2018-07-09 11:35:52 +02:00
issue-44056-macos-tls-align.rs Do not allow LLVM to increase a TLS's alignment on macOS. 2018-06-30 21:36:03 +08:00
issue-45222.rs Change RangeInclusive to a three-field struct. 2018-07-13 09:53:36 +08:00
issue-45466.rs bump llvm version of failing codegen test 2018-07-09 11:35:53 +02:00
issue-47278.rs Compute LLVM argument indices correctly in face of padding 2018-01-16 12:49:38 +01:00
issue-47442.rs remove noop landing pads in cleanup shims 2018-01-16 00:07:06 +02:00
lifetime_start_end.rs Ensure StorageDead is created even if variable initialization fails 2018-07-12 10:13:41 -07:00
likely.rs core: add likely and unlikely intrinsics 2016-09-02 10:29:32 -07:00
link-dead-code.rs Generate code for const- and inline-fns if -Clink-dead-code is specified. 2018-01-04 10:12:20 +01:00
link_section.rs Ensure that statics are always ByRef 2018-05-19 14:24:24 +02:00
loads.rs Disable old trans access via -Z orbit, #[rustc_no_mir] or --disable-orbit. 2016-08-24 13:23:37 +03:00
local-generics-in-exe-internalized.rs Make sure that generics are internalized in executables even with -Zshare-generics 2018-04-06 12:14:08 +02:00
lto-removes-invokes.rs rustc: Implement custom panic runtimes 2016-05-09 08:22:36 -07:00
mainsubprogram.rs bump minimum LLVM version to 5.0 2018-07-09 11:35:52 +02:00
mainsubprogramstart.rs bump minimum LLVM version to 5.0 2018-07-09 11:35:52 +02:00
match-optimizes-away.rs Don't glob-import overlapping variant names in test/codegen/match-optimizes-away.rs. 2017-11-19 09:12:10 +02:00
match.rs rustc_mir: always run the deaggregator. 2018-02-20 02:50:26 +02:00
mir_zst_stores.rs Update codegen tests. 2017-11-07 08:54:38 +01:00
move-val-init.rs Avoid unnecessary copies of arguments that are simple bindings 2017-10-26 12:54:34 +02:00
naked-functions.rs Update codegen tests. 2017-11-07 08:54:38 +01:00
no-output-asm-is-volatile.rs Make inline assembly volatile if it has no outputs. Fixes #46026 2018-02-05 15:56:44 +01:00
nontemporal.rs rustc: Add support for some more x86 SIMD ops 2017-11-25 11:03:13 -08:00
noreturnflag.rs bump minimum LLVM version to 5.0 2018-07-09 11:35:52 +02:00
nounwind.rs rustc: Always emit uwtable on Android 2018-04-21 08:38:44 -07:00
packed.rs Upgrade to LLVM's master branch (LLVM 7) 2018-07-10 13:43:01 -07:00
panic-abort-windows.rs Add 'ignore-cloudabi' to tests that don't and won't build on CloudABI. 2018-01-02 14:11:41 +01:00
personality_lifetimes.rs remove cleanup branches to the resume block 2017-04-22 21:00:50 +03:00
prefetch.rs Remove excessive trailing newlines. 2017-12-30 15:50:52 +08:00
refs.rs rustc: unpack scalar pair newtype layout ABIs. 2017-11-19 02:43:55 +02:00
repeat-trusted-len.rs Upgrade to LLVM's master branch (LLVM 7) 2018-07-10 13:43:01 -07:00
repr-transparent-aggregates-1.rs Stabilize #[repr(transparent)] 2018-06-12 06:49:07 +02:00
repr-transparent-aggregates-2.rs test: Ignore some problematic tests on powerpc and powerpc64* 2018-06-17 12:00:47 +02:00
repr-transparent-aggregates-3.rs Stabilize #[repr(transparent)] 2018-06-12 06:49:07 +02:00
repr-transparent-sysv64.rs Stabilize #[repr(transparent)] 2018-06-12 06:49:07 +02:00
repr-transparent.rs Stabilize #[repr(transparent)] 2018-06-12 06:49:07 +02:00
scalar-pair-bool.rs Update scalar pairs per review comments 2018-07-05 14:22:09 -07:00
simd-intrinsic-float-abs.rs enable fast-math flags 2018-05-24 16:04:39 +02:00
simd-intrinsic-float-ceil.rs enable fast-math flags 2018-05-24 16:04:39 +02:00
simd-intrinsic-float-cos.rs enable fast-math flags 2018-05-24 16:04:39 +02:00
simd-intrinsic-float-exp.rs enable fast-math flags 2018-05-24 16:04:39 +02:00
simd-intrinsic-float-exp2.rs enable fast-math flags 2018-05-24 16:04:39 +02:00
simd-intrinsic-float-floor.rs enable fast-math flags 2018-05-24 16:04:39 +02:00
simd-intrinsic-float-fma.rs enable fast-math flags 2018-05-24 16:04:39 +02:00
simd-intrinsic-float-fsqrt.rs enable fast-math flags 2018-05-24 16:04:39 +02:00
simd-intrinsic-float-log.rs enable fast-math flags 2018-05-24 16:04:39 +02:00
simd-intrinsic-float-log2.rs enable fast-math flags 2018-05-24 16:04:39 +02:00
simd-intrinsic-float-log10.rs enable fast-math flags 2018-05-24 16:04:39 +02:00
simd-intrinsic-float-minmax.rs Upgrade to LLVM's master branch (LLVM 7) 2018-07-10 13:43:01 -07:00
simd-intrinsic-float-pow.rs enable fast-math flags 2018-05-24 16:04:39 +02:00
simd-intrinsic-float-powi.rs enable fast-math flags 2018-05-24 16:04:39 +02:00
simd-intrinsic-float-sin.rs enable fast-math flags 2018-05-24 16:04:39 +02:00
simd-intrinsic-generic-gather.rs add gather/scatter run-time test 2018-05-24 16:04:39 +02:00
simd-intrinsic-generic-scatter.rs add gather/scatter run-time test 2018-05-24 16:04:39 +02:00
simd-intrinsic-generic-select.rs add codegen test 2018-03-18 19:55:20 +01:00
slice-init.rs rustc_trans: use more of the trans::mir and ty::layout APIs throughout. 2017-11-19 02:14:28 +02:00
slice-position-bounds-check.rs hopefully make test pass on windows 2018-07-31 11:17:26 +02:00
sparc-struct-abi.rs Only run the sparc-abi test on sparc 2018-07-31 22:47:12 +03:00
stack-probes.rs bump minimum LLVM version to 5.0 2018-07-09 11:35:52 +02:00
stores.rs Upgrade to LLVM's master branch (LLVM 7) 2018-07-10 13:43:01 -07:00
swap-small-types.rs Only run the test on x86_64 2018-07-21 23:13:51 -07:00
target-feature-on-functions.rs Add -C target-feature to all functions 2018-04-28 14:28:15 -07:00
unchecked-float-casts.rs Stabilize i128_type 2018-03-26 08:36:50 -05:00
vec-clear.rs Use SetLenOnDrop in Vec::truncate() 2018-07-31 20:53:53 +03:00
vec-iter-collect-len.rs std: Ensure OOM is classified as nounwind 2018-05-24 12:03:05 -07:00
vec-optimizes-away.rs std: Mark Layout::repeat as #[inline] 2017-07-29 09:03:06 -07:00
vtabletype.rs bump minimum LLVM version to 5.0 2018-07-09 11:35:52 +02:00
x86_mmx.rs test: Ignore some problematic tests on powerpc and powerpc64* 2018-06-17 12:00:47 +02:00
zip.rs Expand .zip() specialization to .map() and .cloned() 2016-10-17 10:58:21 +02:00