rust/compiler/rustc_codegen_llvm/src
Matthias Krüger 041ecb124a
Rollup merge of #146949 - pmur:murp/improve-ppc-inline-asm, r=Amanieu
Add vsx register support for ppc inline asm, and implement preserves_flag option

This should address the last(?) missing pieces of inline asm for ppc:

* Explicit VSX register support. ISA 2.06 (POWER7) added a 64x128b register overlay extending the fpr's to 128b, and unifies them with the vmx (altivec) registers. Implementations details within gcc/llvm percolate up, and require using the `x` template modifier. I have updated the inline asm to implicitly include this for vsx arguments which do not specify it. ~~Support for the gcc codegen backend is still a todo.~~

* Implement the `preserves_flags` option. All ABI's, and all ISAs store their flags in `cr`, and the carry bit lives inside `xer`. The other status registers hold sticky bits or control bits which do not affect branch instructions.

There is some interest in the e500 (powerpcspe) port. Architecturally, it has a very different FP ISA, and includes a simd extension called SPR (which is not IBM's cell SPE). Notably, it does not have altivec/fpr/vsx registers. It also has an SPE accumulator register which its ABI marks as volatile, but I am not sure if the compiler uses it.
2025-10-15 07:09:54 +02:00
..
back Remove inherent methods from llvm::Type 2025-10-04 18:47:18 +10:00
builder Use globals instead of metadata, since metadata isn't emitted in debug builds 2025-10-07 20:13:59 -04:00
coverageinfo use declarative macro for #[derive(TryFromU32)] 2025-10-06 14:54:38 +00:00
debuginfo Use LLVMDIBuilderCreateGlobalVariableExpression 2025-10-12 23:36:26 +11:00
llvm Rollup merge of #147608 - Zalathar:debuginfo, r=nnethercote 2025-10-13 11:25:23 +02:00
abi.rs Consistently import llvm::Type and llvm::Value 2025-10-06 13:09:16 +11:00
allocator.rs Move computation of allocator shim contents to cg_ssa 2025-10-10 13:04:55 +00:00
asm.rs Allow vector-scalar (vs) registers in ppc inline assembly 2025-10-14 09:52:56 -05:00
attributes.rs Consistently import llvm::Type and llvm::Value 2025-10-06 13:09:16 +11:00
base.rs Consistently import llvm::Type and llvm::Value 2025-10-06 13:09:16 +11:00
builder.rs remove intrinsic wrapper functions from LLVM bindings 2025-10-09 09:26:44 +02:00
callee.rs Consistently import llvm::Type and llvm::Value 2025-10-06 13:09:16 +11:00
common.rs Consistently import llvm::Type and llvm::Value 2025-10-06 13:09:16 +11:00
consts.rs refactor: Remove LLVMRustInsertPrivateGlobal and define_private_global 2025-10-08 21:59:48 +02:00
context.rs Consistently import llvm::Type and llvm::Value 2025-10-06 13:09:16 +11:00
declare.rs refactor: Remove LLVMRustInsertPrivateGlobal and define_private_global 2025-10-08 21:59:48 +02:00
errors.rs Use the object crate rather than LLVM for extracting bitcode sections 2025-07-25 11:21:28 +00:00
intrinsic.rs Consistently import llvm::Type and llvm::Value 2025-10-06 13:09:16 +11:00
lib.rs Rollup merge of #147526 - bjorn3:alloc_shim_weak_shape, r=petrochenkov,RalfJung 2025-10-14 19:47:29 +02:00
llvm_util.rs Add panic=immediate-abort 2025-09-21 13:12:18 -04:00
macros.rs use declarative macro for #[derive(TryFromU32)] 2025-10-06 14:54:38 +00:00
mono_item.rs Replace the llvm::Bool typedef with a proper newtype 2025-08-24 23:09:54 +10:00
type_.rs Consistently import llvm::Type and llvm::Value 2025-10-06 13:09:16 +11:00
type_of.rs Consistently import llvm::Type and llvm::Value 2025-10-06 13:09:16 +11:00
typetree.rs autodiff: typetree recursive depth query from enzyme with fallback 2025-09-19 05:42:27 +00:00
va_arg.rs Consistently import llvm::Type and llvm::Value 2025-10-06 13:09:16 +11:00
value.rs Consistently import llvm::Type and llvm::Value 2025-10-06 13:09:16 +11:00