..
aarch64.rs
compiler: remove rustc_target::abi entirely
2025-02-07 11:23:12 -08:00
amdgpu.rs
compiler: remove rustc_target::abi entirely
2025-02-07 11:23:12 -08:00
arm.rs
compiler: remove rustc_target::abi entirely
2025-02-07 11:23:12 -08:00
avr.rs
compiler: remove rustc_target::abi entirely
2025-02-07 11:23:12 -08:00
bpf.rs
compiler: remove rustc_target::abi entirely
2025-02-07 11:23:12 -08:00
csky.rs
compiler: remove rustc_target::abi entirely
2025-02-07 11:23:12 -08:00
hexagon.rs
compiler: remove rustc_target::abi entirely
2025-02-07 11:23:12 -08:00
loongarch.rs
rename BackendRepr::Vector → SimdVector
2025-02-28 17:17:45 +01:00
m68k.rs
compiler: remove rustc_target::abi entirely
2025-02-07 11:23:12 -08:00
mips.rs
compiler: remove rustc_target::abi entirely
2025-02-07 11:23:12 -08:00
mips64.rs
compiler: make rustc_target have less weird reexports
2025-02-06 01:39:46 -08:00
mod.rs
Rollup merge of #137363 - workingjubilee:untangle-x86-abi-impl, r=jieyouxu
2025-03-07 21:57:48 -05:00
msp430.rs
compiler: remove rustc_target::abi entirely
2025-02-07 11:23:12 -08:00
nvptx64.rs
compiler: remove rustc_target::abi entirely
2025-02-07 11:23:12 -08:00
powerpc.rs
compiler: remove rustc_target::abi entirely
2025-02-07 11:23:12 -08:00
powerpc64.rs
compiler: remove rustc_target::abi entirely
2025-02-07 11:23:12 -08:00
riscv.rs
rename BackendRepr::Vector → SimdVector
2025-02-28 17:17:45 +01:00
s390x.rs
rename BackendRepr::Vector → SimdVector
2025-02-28 17:17:45 +01:00
sparc.rs
compiler: remove rustc_target::abi entirely
2025-02-07 11:23:12 -08:00
sparc64.rs
compiler: remove rustc_target::abi entirely
2025-02-07 11:23:12 -08:00
wasm.rs
compiler: remove rustc_target::abi entirely
2025-02-07 11:23:12 -08:00
x86.rs
Rollup merge of #137363 - workingjubilee:untangle-x86-abi-impl, r=jieyouxu
2025-03-07 21:57:48 -05:00
x86_64.rs
rename BackendRepr::Vector → SimdVector
2025-02-28 17:17:45 +01:00
x86_win32.rs
compiler: factor Windows x86-32 ABI impl into its own file
2025-03-05 15:11:20 -08:00
x86_win64.rs
rename BackendRepr::Vector → SimdVector
2025-02-28 17:17:45 +01:00
xtensa.rs
rename BackendRepr::Vector → SimdVector
2025-02-28 17:17:45 +01:00