Some data-independent timing vector instructions may have subtle data-dependent timing due to MXCSR configuration; dependent on (potentially secret) data instruction retirement may be delayed by one cycle. |
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|---|---|---|
| .. | ||
| alloc | ||
| backtrace@8ad84ca5ad | ||
| core | ||
| panic_abort | ||
| panic_unwind | ||
| portable-simd | ||
| proc_macro | ||
| profiler_builtins | ||
| rtstartup | ||
| rustc-std-workspace-alloc | ||
| rustc-std-workspace-core | ||
| rustc-std-workspace-std | ||
| std | ||
| stdarch@b655243782 | ||
| test | ||
| unwind | ||