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rust/compiler/rustc_codegen_llvm
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Tsukasa OI 5ebdec5ac2 rustc_codegen_llvm: Adjust RISC-V inline assembly's clobber list 
Despite that the `fflags` register (representing floating point
exception flags) is stated as a flag register in the reference, it's not
in the default clobber list of the RISC-V inline assembly and it would
be better to fix it.
2025-09-15 02:16:34 +00:00
..
src rustc_codegen_llvm: Adjust RISC-V inline assembly's clobber list 2025-09-15 02:16:34 +00:00
Cargo.toml Revert introduction of [workspace.dependencies]. 2025-09-02 19:12:54 +10:00
messages.ftl Use the object crate rather than LLVM for extracting bitcode sections 2025-07-25 11:21:28 +00:00
README.md mv compiler to compiler/ 2020-08-30 18:45:07 +03:00

README.md

The codegen crate contains the code to convert from MIR into LLVM IR, and then from LLVM IR into machine code. In general it contains code that runs towards the end of the compilation process.

For more information about how codegen works, see the rustc dev guide.