Simplify register name output for x86
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parent
5a20f39672
commit
62ff543c36
1 changed files with 7 additions and 8 deletions
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@ -297,7 +297,7 @@ impl X86InlineAsmReg {
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_ => unreachable!(),
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}
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} else if self as u32 <= Self::di as u32 {
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let root = ["si", "di"][self as usize - Self::si as usize];
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let root = self.name();
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match modifier.unwrap_or(reg_default_modifier) {
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'l' => write!(out, "{}l", root),
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'x' => write!(out, "{}", root),
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@ -306,12 +306,12 @@ impl X86InlineAsmReg {
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_ => unreachable!(),
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}
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} else if self as u32 <= Self::r15 as u32 {
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let index = self as u32 - Self::r8 as u32 + 8;
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let root = self.name();
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match modifier.unwrap_or(reg_default_modifier) {
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'l' => write!(out, "r{}b", index),
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'x' => write!(out, "r{}w", index),
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'e' => write!(out, "r{}d", index),
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'r' => write!(out, "r{}", index),
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'l' => write!(out, "{}b", root),
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'x' => write!(out, "{}w", root),
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'e' => write!(out, "{}d", root),
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'r' => out.write_str(root),
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_ => unreachable!(),
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}
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} else if self as u32 <= Self::r15b as u32 {
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@ -329,8 +329,7 @@ impl X86InlineAsmReg {
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let index = self as u32 - Self::zmm0 as u32;
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write!(out, "{}{}", prefix, index)
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} else {
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let index = self as u32 - Self::k1 as u32 + 1;
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write!(out, "k{}", index)
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out.write_str(self.name())
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}
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}
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