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fixup atomics

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This commit is contained in:
Alexis Beingessner 2015-07-26 18:19:50 -07:00
parent 36a8b94464
commit 8c7111da07
1 changed files with 3 additions and 3 deletions
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6
src/doc/tarpl/atomics.md
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@ -85,12 +85,12 @@ x = 1; y *= 2;
Ideally this program has 2 possible final states:
* `y = 3`: (thread 2 did the check before thread 1 completed) y = 6`: (thread 2
* `did the check after thread 1 completed)
* `y = 3`: (thread 2 did the check before thread 1 completed)
* `y = 6`: (thread 2 did the check after thread 1 completed)
However there's a third potential state that the hardware enables:
* `y = 2`: (thread 2 saw `x = 2`, but not `y = 3`, and then overwrote `y = 3`)
* `y = 2`: (thread 2 saw `x = 1`, but not `y = 3`, and then overwrote `y = 3`)
It's worth noting that different kinds of CPU provide different guarantees. It
is common to separate hardware into two categories: strongly-ordered and weakly-