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convert _mm256_maskz_srli_epi16 to const generics

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Rémy Rakic 2021-03-05 00:26:51 +01:00 • committed by Amanieu d'Antras
parent ce16a2fcfb
commit aff4cb0630
1 changed files with 7 additions and 11 deletions
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18
library/stdarch/crates/core_arch/src/x86/avx512bw.rs
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@ -5393,15 +5393,11 @@ pub unsafe fn _mm256_mask_srli_epi16<const IMM8: i32>(
/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_maskz_srli_epi16&expand=5509)
#[inline]
#[target_feature(enable = "avx512bw,avx512vl")]
#[cfg_attr(test, assert_instr(vpsrlw, imm8 = 5))]
#[rustc_args_required_const(2)]
pub unsafe fn _mm256_maskz_srli_epi16(k: __mmask16, a: __m256i, imm8: i32) -> __m256i {
macro_rules! call {
($imm8:expr) => {
_mm256_srli_epi16::<$imm8>(a)
};
}
let shf = constify_imm8_sae!(imm8, call);
#[cfg_attr(test, assert_instr(vpsrlw, IMM8 = 5))]
#[rustc_legacy_const_generics(2)]
pub unsafe fn _mm256_maskz_srli_epi16<const IMM8: i32>(k: __mmask16, a: __m256i) -> __m256i {
static_assert_imm8!(IMM8);
let shf = _mm256_srli_epi16::<IMM8>(a);
let zero = _mm256_setzero_si256().as_i16x16();
transmute(simd_select_bitmask(k, shf.as_i16x16(), zero))
}
@ -14734,9 +14730,9 @@ mod tests {
#[simd_test(enable = "avx512bw,avx512vl")]
unsafe fn test_mm256_maskz_srli_epi16() {
let a = _mm256_set1_epi16(1 << 1);
let r = _mm256_maskz_srli_epi16(0, a, 2);
let r = _mm256_maskz_srli_epi16::<2>(0, a);
assert_eq_m256i(r, _mm256_setzero_si256());
let r = _mm256_maskz_srli_epi16(0b11111111_11111111, a, 2);
let r = _mm256_maskz_srli_epi16::<2>(0b11111111_11111111, a);
let e = _mm256_set1_epi16(0);
assert_eq_m256i(r, e);
}