Remove hand crafted intrinsics that are now generated
This commit is contained in:
James Barford-Evans
Amanieu d'Antras
parent
3b93df83b2
commit
d12027810c
8 changed files with 492 additions and 9382 deletions
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@ -10,10 +10,7 @@ mod mte;
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#[unstable(feature = "stdarch_aarch64_mte", issue = "129010")]
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pub use self::mte::*;
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// NEON intrinsics are currently broken on big-endian, so don't expose them. (#1484)
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#[cfg(target_endian = "little")]
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mod neon;
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#[cfg(target_endian = "little")]
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#[stable(feature = "neon_intrinsics", since = "1.59.0")]
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pub use self::neon::*;
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File diff suppressed because it is too large
Load diff
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@ -64,12 +64,3 @@ pub use crate::core_arch::arm_shared::*;
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#[cfg(test)]
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use stdarch_test::assert_instr;
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// NEON intrinsics are currently broken on big-endian, so don't expose them. (#1484)
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#[cfg(target_endian = "little")]
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#[cfg(any(target_feature = "v7", doc))]
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pub(crate) mod neon;
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#[cfg(target_endian = "little")]
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#[cfg(any(target_feature = "v7", doc))]
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#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")]
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pub use neon::*;
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File diff suppressed because it is too large
Load diff
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@ -1,279 +0,0 @@
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unsafe extern "unadjusted" {
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#[cfg_attr(
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any(target_arch = "aarch64", target_arch = "arm64ec"),
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link_name = "llvm.aarch64.crc32b"
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)]
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#[cfg_attr(target_arch = "arm", link_name = "llvm.arm.crc32b")]
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fn crc32b_(crc: u32, data: u32) -> u32;
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#[cfg_attr(
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any(target_arch = "aarch64", target_arch = "arm64ec"),
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link_name = "llvm.aarch64.crc32h"
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)]
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#[cfg_attr(target_arch = "arm", link_name = "llvm.arm.crc32h")]
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fn crc32h_(crc: u32, data: u32) -> u32;
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#[cfg_attr(
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any(target_arch = "aarch64", target_arch = "arm64ec"),
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link_name = "llvm.aarch64.crc32w"
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)]
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#[cfg_attr(target_arch = "arm", link_name = "llvm.arm.crc32w")]
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fn crc32w_(crc: u32, data: u32) -> u32;
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#[cfg_attr(
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any(target_arch = "aarch64", target_arch = "arm64ec"),
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link_name = "llvm.aarch64.crc32cb"
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)]
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#[cfg_attr(target_arch = "arm", link_name = "llvm.arm.crc32cb")]
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fn crc32cb_(crc: u32, data: u32) -> u32;
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#[cfg_attr(
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any(target_arch = "aarch64", target_arch = "arm64ec"),
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link_name = "llvm.aarch64.crc32ch"
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)]
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#[cfg_attr(target_arch = "arm", link_name = "llvm.arm.crc32ch")]
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fn crc32ch_(crc: u32, data: u32) -> u32;
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#[cfg_attr(
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any(target_arch = "aarch64", target_arch = "arm64ec"),
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link_name = "llvm.aarch64.crc32cw"
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)]
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#[cfg_attr(target_arch = "arm", link_name = "llvm.arm.crc32cw")]
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fn crc32cw_(crc: u32, data: u32) -> u32;
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#[cfg_attr(
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any(target_arch = "aarch64", target_arch = "arm64ec"),
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link_name = "llvm.aarch64.crc32x"
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)]
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fn crc32x_(crc: u32, data: u64) -> u32;
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#[cfg_attr(
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any(target_arch = "aarch64", target_arch = "arm64ec"),
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link_name = "llvm.aarch64.crc32cx"
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)]
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fn crc32cx_(crc: u32, data: u64) -> u32;
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}
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#[cfg(test)]
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use stdarch_test::assert_instr;
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/// CRC32 single round checksum for bytes (8 bits).
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///
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/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32b)
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#[inline]
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#[target_feature(enable = "crc")]
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#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
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#[cfg_attr(test, assert_instr(crc32b))]
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#[cfg_attr(
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target_arch = "arm",
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unstable(feature = "stdarch_aarch32_crc32", issue = "125085")
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)]
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#[cfg_attr(
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not(target_arch = "arm"),
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stable(feature = "stdarch_aarch64_crc32", since = "1.80.0")
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)]
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pub unsafe fn __crc32b(crc: u32, data: u8) -> u32 {
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crc32b_(crc, data as u32)
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}
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/// CRC32 single round checksum for half words (16 bits).
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///
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/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32h)
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#[inline]
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#[target_feature(enable = "crc")]
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#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
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#[cfg_attr(test, assert_instr(crc32h))]
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#[cfg_attr(
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target_arch = "arm",
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unstable(feature = "stdarch_aarch32_crc32", issue = "125085")
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)]
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#[cfg_attr(
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not(target_arch = "arm"),
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stable(feature = "stdarch_aarch64_crc32", since = "1.80.0")
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)]
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pub unsafe fn __crc32h(crc: u32, data: u16) -> u32 {
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crc32h_(crc, data as u32)
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}
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/// CRC32 single round checksum for words (32 bits).
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///
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/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32w)
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#[inline]
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#[target_feature(enable = "crc")]
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#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
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#[cfg_attr(test, assert_instr(crc32w))]
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#[cfg_attr(
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target_arch = "arm",
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unstable(feature = "stdarch_aarch32_crc32", issue = "125085")
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)]
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#[cfg_attr(
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not(target_arch = "arm"),
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stable(feature = "stdarch_aarch64_crc32", since = "1.80.0")
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)]
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pub unsafe fn __crc32w(crc: u32, data: u32) -> u32 {
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crc32w_(crc, data)
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}
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/// CRC32-C single round checksum for bytes (8 bits).
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///
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/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32cb)
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#[inline]
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#[target_feature(enable = "crc")]
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#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
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#[cfg_attr(test, assert_instr(crc32cb))]
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#[cfg_attr(
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target_arch = "arm",
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unstable(feature = "stdarch_aarch32_crc32", issue = "125085")
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)]
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#[cfg_attr(
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not(target_arch = "arm"),
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stable(feature = "stdarch_aarch64_crc32", since = "1.80.0")
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)]
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pub unsafe fn __crc32cb(crc: u32, data: u8) -> u32 {
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crc32cb_(crc, data as u32)
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}
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/// CRC32-C single round checksum for half words (16 bits).
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///
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/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32ch)
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#[inline]
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#[target_feature(enable = "crc")]
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#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
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#[cfg_attr(test, assert_instr(crc32ch))]
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#[cfg_attr(
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target_arch = "arm",
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unstable(feature = "stdarch_aarch32_crc32", issue = "125085")
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)]
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#[cfg_attr(
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not(target_arch = "arm"),
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stable(feature = "stdarch_aarch64_crc32", since = "1.80.0")
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)]
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pub unsafe fn __crc32ch(crc: u32, data: u16) -> u32 {
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crc32ch_(crc, data as u32)
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}
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/// CRC32-C single round checksum for words (32 bits).
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///
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/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32cw)
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#[inline]
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#[target_feature(enable = "crc")]
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#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
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#[cfg_attr(test, assert_instr(crc32cw))]
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#[cfg_attr(
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target_arch = "arm",
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unstable(feature = "stdarch_aarch32_crc32", issue = "125085")
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)]
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#[cfg_attr(
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not(target_arch = "arm"),
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stable(feature = "stdarch_aarch64_crc32", since = "1.80.0")
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)]
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pub unsafe fn __crc32cw(crc: u32, data: u32) -> u32 {
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crc32cw_(crc, data)
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}
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/// CRC32 single round checksum for quad words (64 bits).
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///
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/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32d)
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#[inline]
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#[target_feature(enable = "crc")]
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#[cfg(not(target_arch = "arm"))]
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#[cfg_attr(test, assert_instr(crc32x))]
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#[stable(feature = "stdarch_aarch64_crc32", since = "1.80.0")]
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pub unsafe fn __crc32d(crc: u32, data: u64) -> u32 {
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crc32x_(crc, data)
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}
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/// CRC32 single round checksum for quad words (64 bits).
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///
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/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32d)
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#[inline]
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#[target_feature(enable = "crc")]
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#[cfg(target_arch = "arm")]
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#[cfg_attr(test, assert_instr(crc32w))]
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#[unstable(feature = "stdarch_aarch32_crc32", issue = "125085")]
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pub unsafe fn __crc32d(crc: u32, data: u64) -> u32 {
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// On 32-bit ARM this intrinsic emits a chain of two `crc32_w` instructions
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// and truncates the data to 32 bits in both clang and gcc
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crc32w_(
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crc32w_(crc, (data & 0xffffffff) as u32),
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(data >> 32) as u32,
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)
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}
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/// CRC32 single round checksum for quad words (64 bits).
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///
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/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32cd)
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#[inline]
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#[target_feature(enable = "crc")]
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#[cfg(not(target_arch = "arm"))]
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#[cfg_attr(test, assert_instr(crc32cx))]
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#[stable(feature = "stdarch_aarch64_crc32", since = "1.80.0")]
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pub unsafe fn __crc32cd(crc: u32, data: u64) -> u32 {
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crc32cx_(crc, data)
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}
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/// CRC32 single round checksum for quad words (64 bits).
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///
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/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32cd)
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#[inline]
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#[target_feature(enable = "crc")]
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#[cfg(target_arch = "arm")]
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#[cfg_attr(test, assert_instr(crc32cw))]
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#[unstable(feature = "stdarch_aarch32_crc32", issue = "125085")]
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pub unsafe fn __crc32cd(crc: u32, data: u64) -> u32 {
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// On 32-bit ARM this intrinsic emits a chain of two `crc32_cw` instructions
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// and truncates the data to 32 bits in both clang and gcc
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crc32cw_(
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crc32cw_(crc, (data & 0xffffffff) as u32),
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(data >> 32) as u32,
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)
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}
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#[cfg(test)]
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mod tests {
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use crate::core_arch::{arm_shared::*, simd::*};
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use std::mem;
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use stdarch_test::simd_test;
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#[simd_test(enable = "crc")]
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unsafe fn test_crc32d() {
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assert_eq!(__crc32d(0, 0), 0);
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assert_eq!(__crc32d(0, 18446744073709551615), 1147535477);
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}
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#[simd_test(enable = "crc")]
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unsafe fn test_crc32cd() {
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assert_eq!(__crc32cd(0, 0), 0);
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assert_eq!(__crc32cd(0, 18446744073709551615), 3293575501);
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}
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#[simd_test(enable = "crc")]
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unsafe fn test_crc32b() {
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assert_eq!(__crc32b(0, 0), 0);
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assert_eq!(__crc32b(0, 255), 755167117);
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}
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#[simd_test(enable = "crc")]
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unsafe fn test_crc32h() {
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assert_eq!(__crc32h(0, 0), 0);
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assert_eq!(__crc32h(0, 16384), 1994146192);
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}
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#[simd_test(enable = "crc")]
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unsafe fn test_crc32w() {
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assert_eq!(__crc32w(0, 0), 0);
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assert_eq!(__crc32w(0, 4294967295), 3736805603);
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}
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#[simd_test(enable = "crc")]
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unsafe fn test_crc32cb() {
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assert_eq!(__crc32cb(0, 0), 0);
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assert_eq!(__crc32cb(0, 255), 2910671697);
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}
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#[simd_test(enable = "crc")]
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unsafe fn test_crc32ch() {
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assert_eq!(__crc32ch(0, 0), 0);
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assert_eq!(__crc32ch(0, 16384), 1098587580);
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}
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#[simd_test(enable = "crc")]
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unsafe fn test_crc32cw() {
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assert_eq!(__crc32cw(0, 0), 0);
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assert_eq!(__crc32cw(0, 4294967295), 3080238136);
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}
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}
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@ -1,544 +0,0 @@
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use crate::core_arch::arm_shared::{uint8x16_t, uint32x4_t};
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#[allow(improper_ctypes)]
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unsafe extern "unadjusted" {
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#[cfg_attr(
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any(target_arch = "aarch64", target_arch = "arm64ec"),
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link_name = "llvm.aarch64.crypto.aese"
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)]
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#[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.aese")]
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fn vaeseq_u8_(data: uint8x16_t, key: uint8x16_t) -> uint8x16_t;
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#[cfg_attr(
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any(target_arch = "aarch64", target_arch = "arm64ec"),
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link_name = "llvm.aarch64.crypto.aesd"
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)]
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#[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.aesd")]
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fn vaesdq_u8_(data: uint8x16_t, key: uint8x16_t) -> uint8x16_t;
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#[cfg_attr(
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any(target_arch = "aarch64", target_arch = "arm64ec"),
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link_name = "llvm.aarch64.crypto.aesmc"
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)]
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#[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.aesmc")]
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fn vaesmcq_u8_(data: uint8x16_t) -> uint8x16_t;
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#[cfg_attr(
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any(target_arch = "aarch64", target_arch = "arm64ec"),
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link_name = "llvm.aarch64.crypto.aesimc"
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)]
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#[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.aesimc")]
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fn vaesimcq_u8_(data: uint8x16_t) -> uint8x16_t;
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#[cfg_attr(
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any(target_arch = "aarch64", target_arch = "arm64ec"),
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link_name = "llvm.aarch64.crypto.sha1h"
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)]
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#[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha1h")]
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fn vsha1h_u32_(hash_e: u32) -> u32;
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#[cfg_attr(
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any(target_arch = "aarch64", target_arch = "arm64ec"),
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link_name = "llvm.aarch64.crypto.sha1su0"
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)]
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#[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha1su0")]
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fn vsha1su0q_u32_(w0_3: uint32x4_t, w4_7: uint32x4_t, w8_11: uint32x4_t) -> uint32x4_t;
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#[cfg_attr(
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any(target_arch = "aarch64", target_arch = "arm64ec"),
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link_name = "llvm.aarch64.crypto.sha1su1"
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)]
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#[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha1su1")]
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fn vsha1su1q_u32_(tw0_3: uint32x4_t, w12_15: uint32x4_t) -> uint32x4_t;
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#[cfg_attr(
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any(target_arch = "aarch64", target_arch = "arm64ec"),
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link_name = "llvm.aarch64.crypto.sha1c"
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)]
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#[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha1c")]
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fn vsha1cq_u32_(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32x4_t;
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#[cfg_attr(
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any(target_arch = "aarch64", target_arch = "arm64ec"),
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link_name = "llvm.aarch64.crypto.sha1p"
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)]
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#[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha1p")]
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fn vsha1pq_u32_(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32x4_t;
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#[cfg_attr(
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any(target_arch = "aarch64", target_arch = "arm64ec"),
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link_name = "llvm.aarch64.crypto.sha1m"
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)]
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#[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha1m")]
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fn vsha1mq_u32_(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32x4_t;
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||||
|
||||
#[cfg_attr(
|
||||
any(target_arch = "aarch64", target_arch = "arm64ec"),
|
||||
link_name = "llvm.aarch64.crypto.sha256h"
|
||||
)]
|
||||
#[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha256h")]
|
||||
fn vsha256hq_u32_(hash_abcd: uint32x4_t, hash_efgh: uint32x4_t, wk: uint32x4_t) -> uint32x4_t;
|
||||
#[cfg_attr(
|
||||
any(target_arch = "aarch64", target_arch = "arm64ec"),
|
||||
link_name = "llvm.aarch64.crypto.sha256h2"
|
||||
)]
|
||||
#[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha256h2")]
|
||||
fn vsha256h2q_u32_(hash_efgh: uint32x4_t, hash_abcd: uint32x4_t, wk: uint32x4_t) -> uint32x4_t;
|
||||
#[cfg_attr(
|
||||
any(target_arch = "aarch64", target_arch = "arm64ec"),
|
||||
link_name = "llvm.aarch64.crypto.sha256su0"
|
||||
)]
|
||||
#[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha256su0")]
|
||||
fn vsha256su0q_u32_(w0_3: uint32x4_t, w4_7: uint32x4_t) -> uint32x4_t;
|
||||
#[cfg_attr(
|
||||
any(target_arch = "aarch64", target_arch = "arm64ec"),
|
||||
link_name = "llvm.aarch64.crypto.sha256su1"
|
||||
)]
|
||||
#[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sha256su1")]
|
||||
fn vsha256su1q_u32_(tw0_3: uint32x4_t, w8_11: uint32x4_t, w12_15: uint32x4_t) -> uint32x4_t;
|
||||
}
|
||||
|
||||
#[cfg(test)]
|
||||
use stdarch_test::assert_instr;
|
||||
|
||||
/// AES single round encryption.
|
||||
///
|
||||
/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaeseq_u8)
|
||||
#[inline]
|
||||
#[target_feature(enable = "aes")]
|
||||
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
|
||||
#[cfg_attr(test, assert_instr(aese))]
|
||||
#[cfg_attr(
|
||||
target_arch = "arm",
|
||||
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
|
||||
)]
|
||||
#[cfg_attr(
|
||||
not(target_arch = "arm"),
|
||||
stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0")
|
||||
)]
|
||||
pub unsafe fn vaeseq_u8(data: uint8x16_t, key: uint8x16_t) -> uint8x16_t {
|
||||
vaeseq_u8_(data, key)
|
||||
}
|
||||
|
||||
/// AES single round decryption.
|
||||
///
|
||||
/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaesdq_u8)
|
||||
#[inline]
|
||||
#[target_feature(enable = "aes")]
|
||||
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
|
||||
#[cfg_attr(test, assert_instr(aesd))]
|
||||
#[cfg_attr(
|
||||
target_arch = "arm",
|
||||
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
|
||||
)]
|
||||
#[cfg_attr(
|
||||
not(target_arch = "arm"),
|
||||
stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0")
|
||||
)]
|
||||
pub unsafe fn vaesdq_u8(data: uint8x16_t, key: uint8x16_t) -> uint8x16_t {
|
||||
vaesdq_u8_(data, key)
|
||||
}
|
||||
|
||||
/// AES mix columns.
|
||||
///
|
||||
/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaesmcq_u8)
|
||||
#[inline]
|
||||
#[target_feature(enable = "aes")]
|
||||
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
|
||||
#[cfg_attr(test, assert_instr(aesmc))]
|
||||
#[cfg_attr(
|
||||
target_arch = "arm",
|
||||
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
|
||||
)]
|
||||
#[cfg_attr(
|
||||
not(target_arch = "arm"),
|
||||
stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0")
|
||||
)]
|
||||
pub unsafe fn vaesmcq_u8(data: uint8x16_t) -> uint8x16_t {
|
||||
vaesmcq_u8_(data)
|
||||
}
|
||||
|
||||
/// AES inverse mix columns.
|
||||
///
|
||||
/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaesimcq_u8)
|
||||
#[inline]
|
||||
#[target_feature(enable = "aes")]
|
||||
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
|
||||
#[cfg_attr(test, assert_instr(aesimc))]
|
||||
#[cfg_attr(
|
||||
target_arch = "arm",
|
||||
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
|
||||
)]
|
||||
#[cfg_attr(
|
||||
not(target_arch = "arm"),
|
||||
stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0")
|
||||
)]
|
||||
pub unsafe fn vaesimcq_u8(data: uint8x16_t) -> uint8x16_t {
|
||||
vaesimcq_u8_(data)
|
||||
}
|
||||
|
||||
/// SHA1 fixed rotate.
|
||||
///
|
||||
/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha1h_u32)
|
||||
#[inline]
|
||||
#[target_feature(enable = "sha2")]
|
||||
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
|
||||
#[cfg_attr(test, assert_instr(sha1h))]
|
||||
#[cfg_attr(
|
||||
target_arch = "arm",
|
||||
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
|
||||
)]
|
||||
#[cfg_attr(
|
||||
not(target_arch = "arm"),
|
||||
stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0")
|
||||
)]
|
||||
pub unsafe fn vsha1h_u32(hash_e: u32) -> u32 {
|
||||
vsha1h_u32_(hash_e)
|
||||
}
|
||||
|
||||
/// SHA1 hash update accelerator, choose.
|
||||
///
|
||||
/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha1cq_u32)
|
||||
#[inline]
|
||||
#[target_feature(enable = "sha2")]
|
||||
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
|
||||
#[cfg_attr(test, assert_instr(sha1c))]
|
||||
#[cfg_attr(
|
||||
target_arch = "arm",
|
||||
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
|
||||
)]
|
||||
#[cfg_attr(
|
||||
not(target_arch = "arm"),
|
||||
stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0")
|
||||
)]
|
||||
pub unsafe fn vsha1cq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32x4_t {
|
||||
vsha1cq_u32_(hash_abcd, hash_e, wk)
|
||||
}
|
||||
|
||||
/// SHA1 hash update accelerator, majority.
|
||||
///
|
||||
/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha1mq_u32)
|
||||
#[inline]
|
||||
#[target_feature(enable = "sha2")]
|
||||
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
|
||||
#[cfg_attr(test, assert_instr(sha1m))]
|
||||
#[cfg_attr(
|
||||
target_arch = "arm",
|
||||
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
|
||||
)]
|
||||
#[cfg_attr(
|
||||
not(target_arch = "arm"),
|
||||
stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0")
|
||||
)]
|
||||
pub unsafe fn vsha1mq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32x4_t {
|
||||
vsha1mq_u32_(hash_abcd, hash_e, wk)
|
||||
}
|
||||
|
||||
/// SHA1 hash update accelerator, parity.
|
||||
///
|
||||
/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha1pq_u32)
|
||||
#[inline]
|
||||
#[target_feature(enable = "sha2")]
|
||||
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
|
||||
#[cfg_attr(test, assert_instr(sha1p))]
|
||||
#[cfg_attr(
|
||||
target_arch = "arm",
|
||||
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
|
||||
)]
|
||||
#[cfg_attr(
|
||||
not(target_arch = "arm"),
|
||||
stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0")
|
||||
)]
|
||||
pub unsafe fn vsha1pq_u32(hash_abcd: uint32x4_t, hash_e: u32, wk: uint32x4_t) -> uint32x4_t {
|
||||
vsha1pq_u32_(hash_abcd, hash_e, wk)
|
||||
}
|
||||
|
||||
/// SHA1 schedule update accelerator, first part.
|
||||
///
|
||||
/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha1su0q_u32)
|
||||
#[inline]
|
||||
#[target_feature(enable = "sha2")]
|
||||
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
|
||||
#[cfg_attr(test, assert_instr(sha1su0))]
|
||||
#[cfg_attr(
|
||||
target_arch = "arm",
|
||||
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
|
||||
)]
|
||||
#[cfg_attr(
|
||||
not(target_arch = "arm"),
|
||||
stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0")
|
||||
)]
|
||||
pub unsafe fn vsha1su0q_u32(w0_3: uint32x4_t, w4_7: uint32x4_t, w8_11: uint32x4_t) -> uint32x4_t {
|
||||
vsha1su0q_u32_(w0_3, w4_7, w8_11)
|
||||
}
|
||||
|
||||
/// SHA1 schedule update accelerator, second part.
|
||||
///
|
||||
/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha1su1q_u32)
|
||||
#[inline]
|
||||
#[target_feature(enable = "sha2")]
|
||||
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
|
||||
#[cfg_attr(test, assert_instr(sha1su1))]
|
||||
#[cfg_attr(
|
||||
target_arch = "arm",
|
||||
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
|
||||
)]
|
||||
#[cfg_attr(
|
||||
not(target_arch = "arm"),
|
||||
stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0")
|
||||
)]
|
||||
pub unsafe fn vsha1su1q_u32(tw0_3: uint32x4_t, w12_15: uint32x4_t) -> uint32x4_t {
|
||||
vsha1su1q_u32_(tw0_3, w12_15)
|
||||
}
|
||||
|
||||
/// SHA256 hash update accelerator.
|
||||
///
|
||||
/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha256hq_u32)
|
||||
#[inline]
|
||||
#[target_feature(enable = "sha2")]
|
||||
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
|
||||
#[cfg_attr(test, assert_instr(sha256h))]
|
||||
#[cfg_attr(
|
||||
target_arch = "arm",
|
||||
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
|
||||
)]
|
||||
#[cfg_attr(
|
||||
not(target_arch = "arm"),
|
||||
stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0")
|
||||
)]
|
||||
pub unsafe fn vsha256hq_u32(
|
||||
hash_abcd: uint32x4_t,
|
||||
hash_efgh: uint32x4_t,
|
||||
wk: uint32x4_t,
|
||||
) -> uint32x4_t {
|
||||
vsha256hq_u32_(hash_abcd, hash_efgh, wk)
|
||||
}
|
||||
|
||||
/// SHA256 hash update accelerator, upper part.
|
||||
///
|
||||
/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha256h2q_u32)
|
||||
#[inline]
|
||||
#[target_feature(enable = "sha2")]
|
||||
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
|
||||
#[cfg_attr(test, assert_instr(sha256h2))]
|
||||
#[cfg_attr(
|
||||
target_arch = "arm",
|
||||
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
|
||||
)]
|
||||
#[cfg_attr(
|
||||
not(target_arch = "arm"),
|
||||
stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0")
|
||||
)]
|
||||
pub unsafe fn vsha256h2q_u32(
|
||||
hash_efgh: uint32x4_t,
|
||||
hash_abcd: uint32x4_t,
|
||||
wk: uint32x4_t,
|
||||
) -> uint32x4_t {
|
||||
vsha256h2q_u32_(hash_efgh, hash_abcd, wk)
|
||||
}
|
||||
|
||||
/// SHA256 schedule update accelerator, first part.
|
||||
///
|
||||
/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha256su0q_u32)
|
||||
#[inline]
|
||||
#[target_feature(enable = "sha2")]
|
||||
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
|
||||
#[cfg_attr(test, assert_instr(sha256su0))]
|
||||
#[cfg_attr(
|
||||
target_arch = "arm",
|
||||
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
|
||||
)]
|
||||
#[cfg_attr(
|
||||
not(target_arch = "arm"),
|
||||
stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0")
|
||||
)]
|
||||
pub unsafe fn vsha256su0q_u32(w0_3: uint32x4_t, w4_7: uint32x4_t) -> uint32x4_t {
|
||||
vsha256su0q_u32_(w0_3, w4_7)
|
||||
}
|
||||
|
||||
/// SHA256 schedule update accelerator, second part.
|
||||
///
|
||||
/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha256su1q_u32)
|
||||
#[inline]
|
||||
#[target_feature(enable = "sha2")]
|
||||
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
|
||||
#[cfg_attr(test, assert_instr(sha256su1))]
|
||||
#[cfg_attr(
|
||||
target_arch = "arm",
|
||||
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
|
||||
)]
|
||||
#[cfg_attr(
|
||||
not(target_arch = "arm"),
|
||||
stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0")
|
||||
)]
|
||||
pub unsafe fn vsha256su1q_u32(
|
||||
tw0_3: uint32x4_t,
|
||||
w8_11: uint32x4_t,
|
||||
w12_15: uint32x4_t,
|
||||
) -> uint32x4_t {
|
||||
vsha256su1q_u32_(tw0_3, w8_11, w12_15)
|
||||
}
|
||||
|
||||
#[cfg(test)]
|
||||
mod tests {
|
||||
use super::*;
|
||||
use crate::core_arch::{arm_shared::*, simd::*};
|
||||
use std::mem;
|
||||
use stdarch_test::simd_test;
|
||||
|
||||
#[simd_test(enable = "aes")]
|
||||
unsafe fn test_vaeseq_u8() {
|
||||
let data = mem::transmute(u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8));
|
||||
let key = mem::transmute(u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7));
|
||||
let r: u8x16 = mem::transmute(vaeseq_u8(data, key));
|
||||
assert_eq!(
|
||||
r,
|
||||
u8x16::new(
|
||||
124, 123, 124, 118, 124, 123, 124, 197, 124, 123, 124, 118, 124, 123, 124, 197
|
||||
)
|
||||
);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "aes")]
|
||||
unsafe fn test_vaesdq_u8() {
|
||||
let data = mem::transmute(u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8));
|
||||
let key = mem::transmute(u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7));
|
||||
let r: u8x16 = mem::transmute(vaesdq_u8(data, key));
|
||||
assert_eq!(
|
||||
r,
|
||||
u8x16::new(9, 213, 9, 251, 9, 213, 9, 56, 9, 213, 9, 251, 9, 213, 9, 56)
|
||||
);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "aes")]
|
||||
unsafe fn test_vaesmcq_u8() {
|
||||
let data = mem::transmute(u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8));
|
||||
let r: u8x16 = mem::transmute(vaesmcq_u8(data));
|
||||
assert_eq!(
|
||||
r,
|
||||
u8x16::new(3, 4, 9, 10, 15, 8, 21, 30, 3, 4, 9, 10, 15, 8, 21, 30)
|
||||
);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "aes")]
|
||||
unsafe fn test_vaesimcq_u8() {
|
||||
let data = mem::transmute(u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8));
|
||||
let r: u8x16 = mem::transmute(vaesimcq_u8(data));
|
||||
assert_eq!(
|
||||
r,
|
||||
u8x16::new(
|
||||
43, 60, 33, 50, 103, 80, 125, 70, 43, 60, 33, 50, 103, 80, 125, 70
|
||||
)
|
||||
);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "sha2")]
|
||||
unsafe fn test_vsha1h_u32() {
|
||||
assert_eq!(vsha1h_u32(0x1234), 0x048d);
|
||||
assert_eq!(vsha1h_u32(0x5678), 0x159e);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "sha2")]
|
||||
unsafe fn test_vsha1su0q_u32() {
|
||||
let r: u32x4 = mem::transmute(vsha1su0q_u32(
|
||||
mem::transmute(u32x4::new(0x1234_u32, 0x5678_u32, 0x9abc_u32, 0xdef0_u32)),
|
||||
mem::transmute(u32x4::new(0x1234_u32, 0x5678_u32, 0x9abc_u32, 0xdef0_u32)),
|
||||
mem::transmute(u32x4::new(0x1234_u32, 0x5678_u32, 0x9abc_u32, 0xdef0_u32)),
|
||||
));
|
||||
assert_eq!(r, u32x4::new(0x9abc, 0xdef0, 0x1234, 0x5678));
|
||||
}
|
||||
|
||||
#[simd_test(enable = "sha2")]
|
||||
unsafe fn test_vsha1su1q_u32() {
|
||||
let r: u32x4 = mem::transmute(vsha1su1q_u32(
|
||||
mem::transmute(u32x4::new(0x1234, 0x5678, 0x9abc, 0xdef0)),
|
||||
mem::transmute(u32x4::new(0x1234, 0x5678, 0x9abc, 0xdef0)),
|
||||
));
|
||||
assert_eq!(
|
||||
r,
|
||||
u32x4::new(0x00008898, 0x00019988, 0x00008898, 0x0000acd0)
|
||||
);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "sha2")]
|
||||
unsafe fn test_vsha1cq_u32() {
|
||||
let r: u32x4 = mem::transmute(vsha1cq_u32(
|
||||
mem::transmute(u32x4::new(0x1234, 0x5678, 0x9abc, 0xdef0)),
|
||||
0x1234,
|
||||
mem::transmute(u32x4::new(0x1234, 0x5678, 0x9abc, 0xdef0)),
|
||||
));
|
||||
assert_eq!(
|
||||
r,
|
||||
u32x4::new(0x8a32cbd8, 0x0c518a96, 0x0018a081, 0x0000c168)
|
||||
);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "sha2")]
|
||||
unsafe fn test_vsha1pq_u32() {
|
||||
let r: u32x4 = mem::transmute(vsha1pq_u32(
|
||||
mem::transmute(u32x4::new(0x1234, 0x5678, 0x9abc, 0xdef0)),
|
||||
0x1234,
|
||||
mem::transmute(u32x4::new(0x1234, 0x5678, 0x9abc, 0xdef0)),
|
||||
));
|
||||
assert_eq!(
|
||||
r,
|
||||
u32x4::new(0x469f0ba3, 0x0a326147, 0x80145d7f, 0x00009f47)
|
||||
);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "sha2")]
|
||||
unsafe fn test_vsha1mq_u32() {
|
||||
let r: u32x4 = mem::transmute(vsha1mq_u32(
|
||||
mem::transmute(u32x4::new(0x1234, 0x5678, 0x9abc, 0xdef0)),
|
||||
0x1234,
|
||||
mem::transmute(u32x4::new(0x1234, 0x5678, 0x9abc, 0xdef0)),
|
||||
));
|
||||
assert_eq!(
|
||||
r,
|
||||
u32x4::new(0xaa39693b, 0x0d51bf84, 0x001aa109, 0x0000d278)
|
||||
);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "sha2")]
|
||||
unsafe fn test_vsha256hq_u32() {
|
||||
let r: u32x4 = mem::transmute(vsha256hq_u32(
|
||||
mem::transmute(u32x4::new(0x1234, 0x5678, 0x9abc, 0xdef0)),
|
||||
mem::transmute(u32x4::new(0x1234, 0x5678, 0x9abc, 0xdef0)),
|
||||
mem::transmute(u32x4::new(0x1234, 0x5678, 0x9abc, 0xdef0)),
|
||||
));
|
||||
assert_eq!(
|
||||
r,
|
||||
u32x4::new(0x05e9aaa8, 0xec5f4c02, 0x20a1ea61, 0x28738cef)
|
||||
);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "sha2")]
|
||||
unsafe fn test_vsha256h2q_u32() {
|
||||
let r: u32x4 = mem::transmute(vsha256h2q_u32(
|
||||
mem::transmute(u32x4::new(0x1234, 0x5678, 0x9abc, 0xdef0)),
|
||||
mem::transmute(u32x4::new(0x1234, 0x5678, 0x9abc, 0xdef0)),
|
||||
mem::transmute(u32x4::new(0x1234, 0x5678, 0x9abc, 0xdef0)),
|
||||
));
|
||||
assert_eq!(
|
||||
r,
|
||||
u32x4::new(0x3745362e, 0x2fb51d00, 0xbd4c529b, 0x968b8516)
|
||||
);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "sha2")]
|
||||
unsafe fn test_vsha256su0q_u32() {
|
||||
let r: u32x4 = mem::transmute(vsha256su0q_u32(
|
||||
mem::transmute(u32x4::new(0x1234, 0x5678, 0x9abc, 0xdef0)),
|
||||
mem::transmute(u32x4::new(0x1234, 0x5678, 0x9abc, 0xdef0)),
|
||||
));
|
||||
assert_eq!(
|
||||
r,
|
||||
u32x4::new(0xe59e1c97, 0x5eaf68da, 0xd7bcb51f, 0x6c8de152)
|
||||
);
|
||||
}
|
||||
|
||||
#[simd_test(enable = "sha2")]
|
||||
unsafe fn test_vsha256su1q_u32() {
|
||||
let r: u32x4 = mem::transmute(vsha256su1q_u32(
|
||||
mem::transmute(u32x4::new(0x1234, 0x5678, 0x9abc, 0xdef0)),
|
||||
mem::transmute(u32x4::new(0x1234, 0x5678, 0x9abc, 0xdef0)),
|
||||
mem::transmute(u32x4::new(0x1234, 0x5678, 0x9abc, 0xdef0)),
|
||||
));
|
||||
assert_eq!(
|
||||
r,
|
||||
u32x4::new(0x5e09e8d2, 0x74a6f16b, 0xc966606b, 0xa686ee9f)
|
||||
);
|
||||
}
|
||||
}
|
||||
|
|
@ -60,46 +60,6 @@ mod hints;
|
|||
#[unstable(feature = "stdarch_arm_hints", issue = "117218")]
|
||||
pub use self::hints::*;
|
||||
|
||||
mod crc;
|
||||
#[cfg_attr(
|
||||
target_arch = "arm",
|
||||
unstable(feature = "stdarch_aarch32_crc32", issue = "125085")
|
||||
)]
|
||||
#[cfg_attr(
|
||||
not(target_arch = "arm"),
|
||||
stable(feature = "stdarch_aarch64_crc32", since = "1.80.0")
|
||||
)]
|
||||
pub use crc::*;
|
||||
|
||||
// NEON intrinsics are currently broken on big-endian, so don't expose them. (#1484)
|
||||
#[cfg(target_endian = "little")]
|
||||
#[cfg(any(
|
||||
target_arch = "aarch64",
|
||||
target_arch = "arm64ec",
|
||||
target_feature = "v7",
|
||||
doc
|
||||
))]
|
||||
mod crypto;
|
||||
// NEON intrinsics are currently broken on big-endian, so don't expose them. (#1484)
|
||||
#[cfg(target_endian = "little")]
|
||||
#[cfg(any(
|
||||
target_arch = "aarch64",
|
||||
target_arch = "arm64ec",
|
||||
target_feature = "v7",
|
||||
doc
|
||||
))]
|
||||
#[cfg_attr(
|
||||
target_arch = "arm",
|
||||
unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
|
||||
)]
|
||||
#[cfg_attr(
|
||||
not(target_arch = "arm"),
|
||||
stable(feature = "aarch64_neon_crypto_intrinsics", since = "1.72.0")
|
||||
)]
|
||||
pub use self::crypto::*;
|
||||
|
||||
// NEON intrinsics are currently broken on big-endian, so don't expose them. (#1484)
|
||||
#[cfg(target_endian = "little")]
|
||||
#[cfg(any(
|
||||
target_arch = "aarch64",
|
||||
target_arch = "arm64ec",
|
||||
|
|
@ -107,7 +67,7 @@ pub use self::crypto::*;
|
|||
doc
|
||||
))]
|
||||
pub(crate) mod neon;
|
||||
#[cfg(target_endian = "little")]
|
||||
|
||||
#[cfg(any(
|
||||
target_arch = "aarch64",
|
||||
target_arch = "arm64ec",
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
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Add table
Add a link
Reference in a new issue