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Convert _mm256_insert_epi64 to const generics

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Tomasz Miąsko 2021-03-03 00:00:00 +00:00 • committed by Amanieu d'Antras
parent 4faf16f979
commit df368a531f
3 changed files with 12 additions and 15 deletions
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6
library/stdarch/crates/core_arch/src/x86/avx2.rs
View file

@ -4533,7 +4533,7 @@ mod tests {
let a = _mm256_setr_epi64x(0, 1, 2, 3);
let b = _mm256_setr_epi64x(3, 2, 2, 0);
let r = _mm256_cmpeq_epi64(a, b);
assert_eq_m256i(r, _mm256_insert_epi64(_mm256_set1_epi64x(0), !0, 2));
assert_eq_m256i(r, _mm256_insert_epi64::<2>(_mm256_set1_epi64x(0), !0));
}
#[simd_test(enable = "avx2")]
@ -4562,10 +4562,10 @@ mod tests {
#[simd_test(enable = "avx2")]
unsafe fn test_mm256_cmpgt_epi64() {
let a = _mm256_insert_epi64(_mm256_set1_epi64x(0), 5, 0);
let a = _mm256_insert_epi64::<0>(_mm256_set1_epi64x(0), 5);
let b = _mm256_set1_epi64x(0);
let r = _mm256_cmpgt_epi64(a, b);
assert_eq_m256i(r, _mm256_insert_epi64(_mm256_set1_epi64x(0), !0, 0));
assert_eq_m256i(r, _mm256_insert_epi64::<0>(_mm256_set1_epi64x(0), !0));
}
#[simd_test(enable = "avx2")]

6
library/stdarch/crates/core_arch/src/x86/test.rs
View file

@ -104,14 +104,16 @@ mod x86_polyfill {
}
#[target_feature(enable = "avx2")]
pub unsafe fn _mm256_insert_epi64(a: __m256i, val: i64, idx: i32) -> __m256i {
#[rustc_legacy_const_generics(2)]
pub unsafe fn _mm256_insert_epi64<const INDEX: i32>(a: __m256i, val: i64) -> __m256i {
static_assert_imm2!(INDEX);
#[repr(C)]
union A {
a: __m256i,
b: [i64; 4],
}
let mut a = A { a };
a.b[idx as usize] = val;
a.b[INDEX as usize] = val;
a.a
}
}

15
library/stdarch/crates/core_arch/src/x86_64/avx.rs
View file

@ -23,18 +23,13 @@ use crate::{
///
/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_insert_epi64)
#[inline]
#[rustc_args_required_const(2)]
#[rustc_legacy_const_generics(2)]
#[target_feature(enable = "avx")]
// This intrinsic has no corresponding instruction.
#[stable(feature = "simd_x86", since = "1.27.0")]
pub unsafe fn _mm256_insert_epi64(a: __m256i, i: i64, index: i32) -> __m256i {
let a = a.as_i64x4();
match index & 3 {
0 => transmute(simd_insert(a, 0, i)),
1 => transmute(simd_insert(a, 1, i)),
2 => transmute(simd_insert(a, 2, i)),
_ => transmute(simd_insert(a, 3, i)),
}
pub unsafe fn _mm256_insert_epi64<const INDEX: i32>(a: __m256i, i: i64) -> __m256i {
static_assert_imm2!(INDEX);
transmute(simd_insert(a.as_i64x4(), INDEX as u32, i))
}
#[cfg(test)]
@ -46,7 +41,7 @@ mod tests {
#[simd_test(enable = "avx")]
unsafe fn test_mm256_insert_epi64() {
let a = _mm256_setr_epi64x(1, 2, 3, 4);
let r = _mm256_insert_epi64(a, 0, 3);
let r = _mm256_insert_epi64::<3>(a, 0);
let e = _mm256_setr_epi64x(1, 2, 3, 0);
assert_eq_m256i(r, e);
}