Rationale: some ISAs, e.g. OR1K, do not have atomic instructions for byte and halfword access, and at the same time do not have a fixed endianness, which makes it unreasonable to implement these through word-sized atomic accesses. |
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| .. | ||
| target | ||
| Cargo.toml | ||
| dynamic_lib.rs | ||
| lib.rs | ||
| slice.rs | ||
| tempdir.rs | ||